View detail for AVR32800: 32-bit AVR UC3 L series Schematic Checklist

AVR32800: UC3L Schematic Checklist
Features
•
•
•
•
•
•
Power circuits
Reset circuit
Clock and crystal oscillators
aWire™, JTAG and Nexus debug ports
Capacitive Touch (CAT) Module
Patents & Trademarks :
- Atmel® QTouch® (patented charge-transfer method)
- Atmel QMatrix™ (patented charge-transfer method)
32-bit
Microcontrollers
Application Note
1 Introduction
A good hardware design comes from a proper schematic. Since UC3L devices
have a fair number of pins and functions, the schematic for these devices can be
large and quite complex.
This application note describes a common checklist which should be used when
starting and reviewing the schematics for a UC3L design.
Rev. 32129B-AVR32-06/10
2 Power circuit
2.1 Single 3.3 volt power supply
Figure 2-1. Single 3.3 volt power example schematic
Close to
each pin
VDDIO
DC/DC converter
100nF
VDDIN
10µF
100nF
3.33.3
volt
volt
Voltage
regulator
VDDCORE
2.2µF
100nF
Table 2-1. Single 3.3 volt power supply checklist
Signal name
Recommended pin connection
VDDIO
1.62 V to 3.6 V
Decoupling/filtering capacitors
100 nF(1)(2) and 10 µF(1)
VDDIN
1.98 V to 3.6 V
Decoupling/filtering capacitors
100 nF(1)(2) and 10 µF(1)
Description
Powers I/O lines, OSC32K, RC32K, AST, wake, POR33 and SM33.
Decoupling/filtering capacitors must be added to improve startup
stability and reduce source voltage drop.
Powers I/O lines and internal voltage regulator.
Decoupling/filtering capacitors must be added to improve startup
stability and reduce source voltage drop.
Output of the on-chip 1.8V voltage regulator. Powers CPU, peripherals,
memories, SCIF, BOD, RCSYS and DFLL.
2
VDDCORE
Decoupling/filtering capacitors
100 nF(1)(2) and 2.2 µF(1)
Note 1:
These values are given only as a typical example.
Note 2:
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
Decoupling/filtering capacitors must be added to improve startup
stability and reduce source voltage drop.
AVR32800
32129B-AVR32-06/10
AVR32800
2.2 Single 1.8 volt power supply
Figure 2-2. Single 1.8 volt power example schematic
DC/DC converter
Close to
each pin
VDDIO
10 µF
100nF
1.83.3
volt
volt
VDDIN
100nF
Voltage
regulator
VDDCORE
100nF
Table 2-2. Single 1.8 volt power supply checklist
Signal name
Recommended pin connection
VDDIO
1.62 V to 1.98 V
Decoupling/filtering capacitors
100 nF(1)(2) and 10 µF(1)
VDDIN
1.62 V to 1.98 V
Decoupling/filtering capacitors
100 nF(1)(2) and 10 µF(1)
VDDCORE
1.62 V to 1.98 V
Decoupling/filtering capacitors
100 nF(1)(2) and 10 µF(1)
Description
Powers I/O lines, OSC32K, RC32K, AST, wake, POR33 and SM33.
Decoupling/filtering capacitors must be added to improve startup
stability and reduce source voltage drop.
Powers I/O lines, internal voltage regulator not in use.
Decoupling/filtering capacitors must be added to improve startup
stability and reduce source voltage drop.
Powers CPU, peripherals, memories, SCIF, BOD, RCSYS and DFLL.
Decoupling/filtering capacitors must be added to improve startup
stability and reduce source voltage drop.
Note 1:
These values are given only as a typical example.
Note 2:
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
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32129B-AVR32-06/10
2.3 Single 3.3 volt power supply with 1.8 V I/O lines
Figure 2-3. Single 3.3 volt power with 1.8 volt I/O lines example schematic
Close to
each pin
VDDIN
DC/DC converter
10µF
100nF
3.3 volt
VDDIO
Voltage
regulator
100nF
VDDCORE
2.2µF
100nF
Table 2-3. Single 3.3 volt power supply with 1.8 volt I/O lines checklist
Signal name
Recommended pin connection
VDDIO
Connected to VDDCORE.
Decoupling/filtering capacitors
100 nF(1)(2) and 2.2 µF(1)
VDDIN
1.98 V to 3.6 V
Decoupling/filtering capacitors
100 nF(1)(2) and 10 µF(1)
Description
Powers I/O lines, OSC32K, RC32K, AST, wake, POR33 and SM33.
Decoupling/filtering capacitors must be added to improve startup
stability and reduce source voltage drop.
Powers I/O lines and internal voltage regulator.
Decoupling/filtering capacitors must be added to improve startup
stability and reduce source voltage drop.
Output of the on-chip 1.8V voltage regulator. Powers CPU, peripherals,
memories, SCIF, BOD, RCSYS and DFLL.
4
VDDCORE
Decoupling/filtering capacitors
100 nF(1)(2) and 2.2 µF(1)
Note 1:
These values are given only as a typical example.
Note 2:
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
Decoupling/filtering capacitors must be added to improve startup
stability and reduce source voltage drop.
AVR32800
32129B-AVR32-06/10
AVR32800
2.4 ADC reference power supply
The following schematic checklist is mandatory even if the internal ADC is not in use.
Figure 2-4. ADC reference power supply example schematic
Close to pin
VDDANA
VDDCORE
100nF
ADVREF
GNDANA
Table 2-4. ADC reference power supply checklist
Signal name
Recommended pin connection
VDDANA
1.62 V to 1.98 V
(3)
RF EMI inductor
Decoupling/filtering capacitor
(1)(2)
100 nF
ADVREF
1.62 V to VDDANA
Connect with VDDANA
GNDANA
Connect to analog ground
Note 1:
Description
Powers the on-chip ADC, must always be powered since the analog
multiplexer is powered by another domain.
Decoupling/filtering capacitor must be added to improve startup stability
and reduce source voltage drop.
ADVREF is a pure analog input.
These values are given only as a typical example.
Note 2:
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
Note 3:
RF EMI inductor only needed if ADC is used in the design.
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3 Reset circuit
Figure 3-1. Reset circuit example schematic
VDDIO
10k ohm
Reset
100nF
Table 3-1. Reset circuit checklist
Signal name
Recommended pin connection
RESET(1)
Can be left unconnected in case no
The RESET_N pin is a Schmitt input and integrates a permanent pullreset from the system needs to be
applied to the product
up resistor to VDDIO.
Note 1:
Description
RESET_N pin is used by aWire. Reset circuitry should be disabled when using RESET_N pin during aWire operation.
Check section 5 of this document.
4 Clocks and crystal oscillators
4.1 External clock source
Figure 4-1. External clock source schematic
Table 4-1. External clock source checklist
6
Signal name
Recommended pin connection
Description
XIN
Connected to clock output from
external clock source
Up to VDDIO volt square wave signal up to 50 MHz.
XOUT
Can be left unconnected or used as
GPIO
AVR32800
32129B-AVR32-06/10
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4.2 Crystal oscillator
Figure 4-2. Crystal oscillator example schematic
XIN
22pF
XOUT
22pF
Table 4-2. Crystal oscillator checklist
Signal name
XIN
XOUT
Note 1:
Recommended pin connection
Description
Biasing capacitor 22 pF
(1)(2)
External crystal between 3 MHz and 16 MHz, powered by VDDIO.
Biasing capacitor 22 pF
(1)(2)
Powered by VDDIO.
These values are given only as a typical example. The capacitance C of the biasing capacitors can be computed based
on the crystal load capacitance CL and the internal capacitance Ci of the MCU as follows:
C = 2 (CL – Ci)
The value of CL can be found in the crystal datasheet and the value of Ci can be found in the MCU datasheet.
Note 2:
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
4.3 32 kHz Crystal oscillator
Figure 4-3. 32 kHz crystal oscillator example schematic
Table 4-3. 32 kHz crystal oscillator checklist
Signal name
Recommended pin connection
Description
XIN32
Biasing capacitor max 15 pF(1)(2)
External 32 kHz crystal.Primary (PA10) powered by VDDIO, Secondary
(PA13- XIN32_2) powered by VDDIN.
XOUT32
Biasing capacitor max 15 pF(1)(2)
Primary (PA12) powered by VDDIO, Secondary (PA20 – XOUT32_2)
powered by VDDIN.
Note 1:
These values are given only as a typical example. The capacitance C of the biasing capacitors can be computed based
on the crystal load capacitance CL and the internal capacitance Ci of the MCU as follows:
C = 2 (CL – Ci)
The value of CL can be found in the crystal datasheet and the value of Ci can be found in the MCU datasheet.
Note 2:
Capacitor should be placed as close as possible to each pin in the signal group, vias should be avoided.
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32129B-AVR32-06/10
5 JTAG and Nexus debug ports
5.1 aWire port interface
Figure 5-1. aWire port interface example schematic
RESET_N / DATA
aWire data in/out
PA00 / DATAOUT
aWire data out
Optional
MCU
aWire master connector
Board Reset
Circuitry
Jumper
AW Debug
Interface
RESET_N
Power Manager
Table 5-1. aWire port interface checklist
Signal name
Recommended pin connection
Description
DATA
Connect to aWire DATA signal on
external tool.
Device external reset line used for data input and output. Reset circuitry
should be disabled as shown above when the RESET_N pin is used
during aWire operation.
DATAOUT
Optional, connect to aWire
DATAOUT signal on external tool.
Data output is optional and only needed for aWire full duplex mode.
Note 1:
8
The aWire needs an external pullup on the RESET_N pin to ensure that the pin is pulled up when the bus is not driven.
AVR32800
32129B-AVR32-06/10
AVR32800
5.2 JTAG port interface
Figure 5-2. JTAG port interface example schematic
Table 5-2. JTAG port interface checklist
Signal name
Recommended pin connection
Description
TMS
PA01
Test mode select, sampled on rising TCK.
TDO
PA02
Test data output, driven on falling TCK.
TCK
PA00
Test clock, fully asynchronous to system clock frequency.
RESET
RESET
Device external reset line.
TDI
PA03
Test data input, sampled on rising TCK.
EVTO
Event output, not used.
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32129B-AVR32-06/10
5.3 Nexus port interface
Figure 5-3. Nexus port interface example schematic
TDI
1
3
5
7
9
11
13
15
17
19
VDD
100nF
21
2
3
4
5
6
7
8
RESET
EVTI
TDO
VCC
13
14
TCK
16
TMS
18
TDI
MDO5
TRST
MDO4
23
MDO3
25
MDO2
27
MDO1
29
MDO0
2
TMS
4
6
TCK
8
TDO
10
12
14
16
VDD
100nF
RESET
EVTI
18
20
MDO[0:5]
22
10k
23
25
27
29
31
33
35
35
39
41
43
10
1
Nexus interface
31
EVTO
33
MCK0
35
MSEO1
37
MSEO0
GND
GND
GND
GND
24
26
28
30
EVTO
32
34
MCK0
36
MSEO[0:1]
38
40
42
GND
AVR32800
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AVR32800
Table 5-3. Nexus port interface checklist
Signal name
Recommended pin connection
Description
TDI
PA03
Test data input, sampled on rising TCK.
TMS
PA01
Test mode select, sampled on rising TCK.
TCK
PA00
Test clock, fully asynchronous to system clock frequency.
TDO
PA02
Test data output, driven on falling TCK.
RESET
Device external reset line.
RESET
EVTI
(1)
MDO[0:5]
Event input.
(1)
EVTO
Trace data output.
PA04
(1)
MCK0
MSE[0:1]
Event output.
Trace data output clock.
(1)
Note 1:
Trace frame control.
Two different connections are possible based on the value of OCD AXS register. Please refer to MCU datasheet section
Nexus OCD AUX Port Connections
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32129B-AVR32-06/10
6 Capacitive Touch (CAT) Module
6.1 QTouch
Figure 6-1. QTouch Typical connection
Table 6.1 QTouch Pin selection guide
CAT module PIN name
(5)
QTouch Method Pin Name
CSA0
PA13
SNS0
CSB0
PA18
SNSK0
CSA1
PA01
SNS1
CSB1
PA06
SNSK1
CSA2
PA00
SNS2
CSB2
PA07
SNSK2
CSA3
PA02
SNS3
CSB3
PA03
SNSK3
CSA4
CSB4
CSA5
12
PIN Name
(1)
SNS4
(2)
SNSK4
(3)
SNS5
(4)
PA08
PA09
PA10
CSB5
PA12
SNSK5
CSA6
PA14
SNS6
CSB6
PA15
SNSK6
CSA7
PA04
SNS7
CSB7
PA05
SNSK7
CSA8
PA16
SNS8
CSB8
PA17
SNSK8
CSA9
PB00
SNS9
AVR32800
32129B-AVR32-06/10
AVR32800
CAT module PIN name
PIN Name
QTouch Method Pin Name
CSB9
PB01
SNSK9
CSA10
PA19
SNS10
CSB10
PA22
SNSK10
CSA11
PB03
SNS11
CSB11
PB02
SNSK11
(6)
CSA12
PA20
SNS12
CSB12
PB08
SNSK12
CSA13
PB07
SNS13
CSB13
PB06
SNSK13
CSA14
PB04
SNS14
CSB14
PB05
SNSK14
CSA15
PB12
SNS15
CSB15
PB09
SNSK15
CSA16
PB11
SNS16
CSB16
PB10
SNSK16
Note 1:
This pin has an alternate function of XIN0
Note 2:
This pin has an alternate function of XOUT0
Note 3:
This pin has an alternate function of XIN32
Note 4:
This pin has an alternate function of XOUT32
Note 5:
This pin has an alternate function of XIN32_2
Note 6:
This pin has an alternate function of XOUT32_2
6.2 QMatrix
There are three different ways of connecting QMatrix to the CAT module
1. Internal Current sources Disabled.
2. Internal Current sources Enabled with DICS.INTREFSEL= 0.
3. Internal Current sources Enabled with DICS.INTREFSEL= 1.
In all the three modes, Ra=10kohm, Rb=50ohm are recommended values. These two
resistors should only be needed in some specialized applications (touch screens)
where the sense capacitors are charged to low voltages (15 to 20 mV). In this case,
we need to insure that the comparator threshold is 0 or slightly positive.
In a more typical QMatrix application with an array of buttons, the capacitors will be
charged to 50 mV or more, and then a comparator offset of -15 mV is not a problem.
In this case ACREFN can be grounded and it is unnecessary to use VDIVEN.
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32129B-AVR32-06/10
Figure 6-2 . QMatrix example schematic for Internal Current Sources Disabled
X2
X3
X6
QMatrix Sensor Array
X7
YK0
Y0
Cs0 (Sense Capacitor)
YK1
Y1
Cs1 (Sense Capacitor)
AVR32 Chip
Rsmp1
Rsmp0
SMP
VDIVEN
Ra
ACREFN
Rb
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32129B-AVR32-06/10
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Table 6-2. Some of Maximum possible combination for QMatrix (Internal Current Sources Disabled).
PIN Name
CAT
module
PIN name
(5)
QMatrix
Method Pin
Name
Internal Current Sources Disabled ( Five different possible combination)
A
B
C
D
E
F
CSA0
PA13
X0
X0
SMP
X0
X0
X0
X0
CSB0
PA18
X1
X1
X1
X1
X1
X1
X1
CSA1
PA01
Y0
Y0
Y0
Y0
Y0
Y0
Y0
CSB1
PA06
YK0
YK0
YK0
YK0
YK0
YK0
YK0
CSA2
PA00
X2
X2
X2
X2
X2
X2
X2
CSB2
PA07
X3
X3
X3
X3
X3
X3
X3
CSA3
PA02
Y1
Y1
Y1
Y1
Y1
Y1
Y1
CSB3
PA03
YK1
YK1
YK1
YK1
YK1
YK1
YK1
CSA4
(1)
PA08
X4
X4
X4
X4
X4
X4
X4
CSB4
PA09(2)
X5
X5
X5
X5
X5
X5
X5
CSA5
(3)
Y2
Y2
Y2
Y2
Y2
Y2
PA10
(4)
CSB5
PA12
YK2
YK2
YK2
YK2
SMP
YK2
YK2
CSA6
PA14
X6
X6
X6
X6
X6
SMP
X6
CSB6
PA15
X7
X7
X7
X7
X7
X7
X7
CSA7
PA04
Y3
Y3
Y3
Y3
Y3
Y3
Y3
CSB7
PA05
YK3
YK3
YK3
YK3
YK3
YK3
YK3
CSA8
PA16
X8
ACREFN
ACREFN
ACREFN
ACREFN
ACREFN
ACREFN
CSB8
PA17
X9
SMP
X9
X9
X9
X9
X9
CSA9
PB00
Y4
Y4
Y4
Y4
Y4
Y4
Y4
CSB9
PB01
YK4
YK4
YK4
YK4
YK4
YK4
YK4
CSA10
PA19
X10
X10
X10
X10
X10
X10
X10
CSB10
PA22
X11
X11
X11
SMP
X11
X11
X11
CSA11
PB03
Y5
Y5
Y5
Y5
Y5
Y5
Y5
CSB11
PB02
YK5
YK5
YK5
YK5
YK5
YK5
YK5
CSA12
PA20(6)
X12
X12
X12
X12
X12
X12
X12
CSB12
PB08
X13
X13
X13
X13
X13
X13
X13
CSA13
PB07
Y6
Y6
Y6
Y6
Y6
Y6
Y6
CSB13
PB06
YK6
YK6
YK6
YK6
YK6
YK6
YK6
CSA14
PB04
X14
X14
X14
X14
X14
X14
X14
CSB14
PB05
X15
X15
X15
X15
X15
X15
X15
CSA15
PB12
Y7
Y7
Y7
Y7
Y7
Y7
Y7
CSB15
PB09
YK7
YK7
YK7
YK7
YK7
YK7
YK7
CSA16
PB11
X16
X16
X16
X16
X16
X16
X16
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PIN Name
CAT
module
PIN name
QMatrix
Method Pin
Name
Internal Current Sources Disabled ( Five different possible combination)
A
B
C
D
E
F
CSB16
X17
X17
X17
X17
X17
X17
X17
PB10
PA21
SMP
Note 1:
This pin has an alternate function of XIN0
Note 2:
This pin has an alternate function of XOUT0
Note 3:
This pin has an alternate function of XIN32
Note 4:
This pin has an alternate function of XOUT32
Note 5:
This pin has an alternate function of XIN32_2
Note 6:
This pin has an alternate function of XOUT32_2
Table 6-3. Some of Maximum possible combination for QMatrix with SYNC and DIVEN (Internal Current Sources
Disabled).
Table 6.2-1
Table 6-2 “A” combination +SYNC
QMatrix
CAT
“A”
Method Pin
module
combination
PIN name PIN Name
Name
I
J
K
L
M
+VDIVEN
CSA0
PA13(5)
X0
X0
X0
X0
X0
X0
X0
CSB0
PA18
X1
X1
SYNC
X1
X1
X1
X1
CSA1
PA01
Y0
Y0
Y0
Y0
Y0
Y0
Y0
CSB1
PA06
YK0
YK0
YK0
YK0
YK0
YK0
YK0
CSA2
PA00
X2
X2
X2
X2
X2
X2
X2
CSB2
PA07
X3
X3
X3
X3
X3
X3
X3
CSA3
PA02
Y1
Y1
Y1
Y1
Y1
Y1
Y1
CSB3
PA03
CSA4
YK1
YK1
YK1
YK1
YK1
YK1
YK1
(1)
X4
X4
X4
X4
X4
X4
X4
(2)
X5
X5
X5
X5
X5
X5
X5
(3)
Y2
Y2
Y2
Y2
Y2
Y2
Y2
(4)
PA08
CSB4
PA09
CSA5
PA10
CSB5
PA12
YK2
YK2
YK2
YK2
YK2
YK2
YK2
CSA6
PA14
X6
X6
X6
X6
X6
X6
X6
CSB6
PA15
X7
SYNC
X7
X7
X7
X7
X7
CSA7
PA04
Y3
Y3
Y3
Y3
Y3
Y3
Y3
CSB7
PA05
YK3
YK3
YK3
YK3
YK3
YK3
YK3
CSA8
PA16
X8
ACREFN
ACREFN
ACREFN
ACREFN
ACREFN
ACREFN
CSB8
PA17
X9
SMP
SMP
SMP
SMP
SMP
SMP
CSA9
PB00
Y4
Y4
Y4
Y4
Y4
Y4
Y4
CSB9
PB01
YK4
YK4
YK4
YK4
YK4
YK4
YK4
CSA10
PA19
X10
X10
X10
X10
X10
SYNC
X10
CSB10
PA22
X11
X11
X11
X11
X11
X11
X11
CSA11
PB03
Y5
Y5
Y5
Y5
Y5
Y5
Y5
CSB11
PB02
YK5
YK5
YK5
YK5
YK5
YK5
YK5
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CAT
module
PIN name PIN Name
(6)
QMatrix
Method Pin
Name
Table 6-2 “A” combination +SYNC
I
J
K
L
M
Table 6.2-1
“A”
combination
+VDIVEN
CSA12
PA20
X12
X12
X12
X12
X12
X12
X12
CSB12
PB08
X13
X13
X13
SYNC
X13
X13
X13
CSA13
PB07
Y6
Y6
Y6
Y6
Y6
Y6
Y6
CSB13
PB06
YK6
YK6
YK6
YK6
YK6
YK6
YK6
CSA14
PB04
X14
X14
X14
X14
X14
X14
X14
CSB14
PB05
X15
X15
X15
X15
X15
X15
X15
CSA15
PB12
Y7
Y7
Y7
Y7
SYNC
Y7
Y7
CSB15
PB09
YK7
YK7
YK7
YK7
YK7
YK7
CSA16
PB11
X16
X16
X16
X16
X16
X16
VDIVEN
CSB16
PB10
X17
X17
X17
X17
X17
X17
X17
Note 1:
This pin has an alternate function of XIN0
Note 2:
This pin has an alternate function of XOUT0
Note 3:
This pin has an alternate function of XIN32
Note 4:
This pin has an alternate function of XOUT32
Note 5:
This pin has an alternate function of XIN32_2
Note 6:
This pin has an alternate function of XOUT32_2
17
32129B-AVR32-06/10
Figure 6-3. Qmatrix example schematic for Internal Current Sources Enabled with DICS.INTREFSEL= 0 and
DICS.INTREFSEL= 1
X2
X3
X6
QMatrix Sensor Array
X7
YK0
Y0
Cs0 (Sense Capacitor)
YK1
Y1
Cs1 (Sense Capacitor)
AVR32 Chip
DIS
Rdis
VDIVEN
Ra
ACREFN
NOTE: If DICS.INTREFSEL= 1
then it is not required to include
DIS signal and Rdis resistor in
design
Rb
18
AVR32800
32129B-AVR32-06/10
AVR32800
Table 6-4. Some of Maximum possible combination for QMatrix (Internal Current sources Enabled) with
DICS.INTREFSEL= 0 and DICS.INTREFSEL= 1.
CAT
module
PIN name PIN Name
(5)
QMatrix Method Pin Name
DICS.INTREFSEL= 0
DICS.INTREFSEL= 1
CSA0
PA13
X0
X0
X0
CSB0
PA18
X1
X1
X1
CSA1
PA01
Y0
Y0
Y0
CSB1
PA06
YK0
YK0
YK0
CSA2
PA00
X2
X2
X2
CSB2
PA07
X3
X3
X3
CSA3
PA02
Y1
Y1
Y1
CSB3
PA03
CSA4
CSB4
CSA5
YK1
YK1
YK1
(1)
X4
X4
X4
(2)
X5
X5
X5
(3)
Y2
Y2
Y2
(4)
PA08
PA09
PA10
CSB5
PA12
YK2
YK2
YK2
CSA6
PA14
X6
X6
X6
CSB6
PA15
X7
X7
X7
CSA7
PA04
Y3
Y3
Y3
CSB7
PA05
YK3
YK3
YK3
CSA8
PA16
X8
ACREFN
ACREFN
CSB8
PA17
X9
DIS
X9
CSA9
PB00
Y4
Y4
Y4
CSB9
PB01
YK4
YK4
YK4
CSA10
PA19
X10
X10
X10
CSB10
PA22
X11
X11
X11
CSA11
PB03
Y5
Y5
Y5
CSB11
PB02
YK5
YK5
YK5
(6)
CSA12
PA20
X12
X12
X12
CSB12
PB08
X13
X13
X13
CSA13
PB07
Y6
Y6
Y6
CSB13
PB06
YK6
YK6
YK6
CSA14
PB04
X14
X14
X14
CSB14
PB05
X15
X15
X15
CSA15
PB12
Y7
Y7
Y7
CSB15
PB09
YK7
YK7
YK7
CSA16
PB11
X16
X16
X16
CSB16
PB10
X17
X17
X17
Note 1:
This pin has an alternate function of XIN0
Note 2:
This pin has an alternate function of XOUT0
19
32129B-AVR32-06/10
CAT
module
PIN name PIN Name
QMatrix Method Pin Name
Note 3:
This pin has an alternate function of XIN32
Note 4:
This pin has an alternate function of XOUT32
Note 5:
This pin has an alternate function of XIN32_2
Note 6:
This pin has an alternate function of XOUT32_2
DICS.INTREFSEL= 0
DICS.INTREFSEL= 1
7 Resistive Touch Screen
Refer to "Resistive Touch Screen” of MCU data sheet for more details.
8 Miscellaneous Topics
8.1 I/O Line considerations
The device datasheet contains subsection “ I/O Line Considerations” under section
“Package and Pinout” .
8.2 Bootloader pin
If a pin is used to enter in the bootloader mode provided by the default bootloader
programmed on all chips, that pin should be pulled-up or pulled-low depending on the
chosen bootloader pin configuration.
9 Suggested reading
9.1 Device datasheet
The device datasheet contains block diagrams of the peripherals and details about
implementing firmware for the device. The datasheet is available on
http://www.atmel.com/AVR32 in the Datasheets section.
0
9.2 Touch design documents
Touch design documents contain the principles required for designing with Buttons,
sliders and wheels. They are available on,
http://www.atmel.com/dyn/products/app_notes_v2.asp?family_id=697 .
9.3 Hardware – QT600
QT600 is a complete touch development kit for buttons, sliders and wheels. They are
available on http://www.atmel.com/dyn/products/tools_card_v2.asp?tool_id=4658.
20
AVR32800
32129B-AVR32-06/10
AVR32800
9.4 Hardware – STK600 Routing card for 48 pin AT32UC3L0 - STK600-RCUC3L0-34
STK600-RCUC3L0-34 is the correct Routing card for using with STK600. Schematics
of same is available on http://www.atmel.com/dyn/resources/prod_documents/A090644_STK600-RCUC3L0-34_sch.PDF
21
32129B-AVR32-06/10
Disclaimer
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32129B-AVR32-06/10