APPLICATION NOTE Application Hints for ATA5723/ATA5724/ATA5728 ATA5723/ATA5724/ATA5728 Introduction The UHF receiver ATA5723, ATA5724, and ATA5728 are designed specially for automotive application like Remote Keyless Entry as well as Tire Pressure Monitoring System. These receivers are upgrades of ATA5743 and ATA5760. They have compatible pinning that allows the development of one layout for applications in three different ISM (industrial Scientific Medical) frequency bands. The frequency ranges are 312.5MHz to 317.5MHz, 431.5MHz to 436.5MHz and 868MHz to 870MHz. Another benefit of the receiver is the reuse of the software from Atmel®’s older receiver, the ATA5743. Additional features include the RSSI output, the pierce crystal oscillator achieving a better oscillation margin, an improved sensitivity as well as the image rejection. The purpose of this application note is to give a designer some hints how to start developing a receiver module with ATA5723/ATA5724/ATA5728. Calculating the Required Crystal Frequency Figure 1. System Block Diagram for the Receivers Containing the Internal Frequency Generation and Processing (Synthesizer) fXTAL Loop Filter XTO fXTO f fVCO LC-VCO fIF :2 or :3 fRef f fLO f :2 or :4 fLO :128 or :64 fRF 9118C-AUTO-05/15 A reference frequency (fRef) in the receiver is based on the crystal oscillator's frequency (fXTO), the loaded crystal resonance frequency (fXTAL) respectively. The defined reference frequency is: f XTO For ATA5723: f Ref = ----------3 Equation 1 f XTO For ATA5724: f Ref = ----------2 Equation 2 f XTO For ATA5728: f Ref = ----------2 Equation 3 The fixed intermediate frequencies (IF) for the receivers are: IF of ATA5723 is 987kHz IF of ATA5724 is 987kHz IF of ATA5728 is 947.8kHz The local oscillator frequency (fLO) can be calculated as: fLO = fRF – fIF Equation 4 The correlation between local oscillator frequency (fLO) and the Voltage Oscillator frequency (fVCO) is: f VCO For ATA5723: f LO = -----------4 Equation 5 f VCO For ATA5724: f LO = -----------4 Equation 6 f VCO For ATA5728: f LO = -----------2 Equation 7 The reference frequency (fRef) will be compared with the local oscillator frequency divided by a factor of 64 or 128. 2 f LO For ATA5723: f Ref = -------64 Equation 8 f LO For ATA5724: f Ref = -------64 Equation 9 f LO For ATA5728: f Ref = --------128 Equation 10 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 Using the aforementioned formulas, the crystal frequency for the receivers can be calculated as follows: f RF – f IF 3 For ATA5723: f XTAL = ---------------------------------64 Equation 11 f RF – f IF 2 For ATA5724: f XTAL = ---------------------------------64 Equation 12 f RF – f IF 2 For ATA5728: f XTAL = ---------------------------------128 Equation 13 Example: 1. For the 315 MHz receiving frequency (ATA5723) the crystal frequency required can be calculated as follows: fRF = 315MHz fIF = 987kHz 315MHz – 987kHz 3 f XTAL = ------------------------------------------------------------ = 14.71935938MHz 64 2. For the 433.92MHz receiving frequency (ATA5724) the crystal frequency required can be calculated as follows: fRF = 433.92MHz fIF = 987kHz 433.92MHz – 987kHz 2 f XTAL = -------------------------------------------------------------------- = 13.52915625 64 3. For the 868.3MHz receiving frequency (ATA5728) the crystal frequency required can be calculated as follows: fRF = 868.3MHz fIF = 947.8kHz 868.3MHz – 947.8kHz 2 f XTAL = --------------------------------------------------------------------- = 13.55237813MHz 128 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 3 1. Matching the Receiver Input to the 50 The input matching for the optimal sensitivity is matching to 50. This can be achieved with the LC high-pass filter combination. Figure 1-1 shows an LC matching network, the equivalent circuit of the receiver's input and the 50 generator source. This section provides some mathematical correlations, which help to find the start values in the tuning of the matching values to 50 impedance. The determined start values are used for the matching of Atmel’s development boards. The results of the demo boards’ matching will be shown. Figure 1-1. LC Matching Network to 50 Zin Rs 50Ω Cm Us Lm Cin Rin The first important step is to find out the input impedance of the receivers and convert it into an equivalent parallel circuit. The input impedance of the receiver is listed below: ATA5723 Zin = 26.97 – j158.7 at 315MHz ATA5724 Zin = 19.3 – j113.3 at 433.92MHz ATA5728 Zin = 14.15 – j73.53 at 868.3MHz The admittance of the receiver (Bin) can be estimated from the impedance Zin. 1 B in = ------Z in Equation 14 The input resistance Rin is: 1 R in = --------------------Re B in Equation 15 Thus the reactance of the parallel input capacitance Cin can be given as: 1 X in = --------------------Im B in Equation 16 Using equation 17, the quality factor of the matching network (Qm) can be estimated. Qm = R in ------- + 1 Rs Equation 17 The matching capacitance is derived from the reactance of the matching network and can be given as: 1 C m = ----------------2fX m 4 Equation 18 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 The ideal inductor value can be calculated with equation 19: X in – X m L m = ------------------------------------2f X in + X m Equation 19 From the equations 18 and 19 the start values of the matching elements for tuning purpose can be calculated: ATA5723 at 315 MHz would be: Lm = 46.8nH (47nH); Cm = 2.36pF (2.2pF) ATA5724 at 433.92 MHz would be: Lm = 25.9nH (27nH); Cm = 2.05pF (2pF) ATA5728 at 868.3 MHz would be: Lm = 8.87nH (8.2nH); Cm = 1.38pF (1.5pF) The optimal matching values after tuning are: ATA5723 at 315MHz is: Lm = 39nH; Cm = 3pF ATA5724 at 433.92MHz is: Lm = 22nH; Cm = 2.2pF ATA5728 at 868.3MHz is: Lm = 5.6nH; Cm = 1.8pF Figure 1-2, Figure 1-3 and Figure 1-4 show the input impedances of the receivers during the matching progress. Note: Smith chart: - The red curve shows the input impedance without matching elements. - The green curve illustrates the theoretical receiver input impedance with the determined start values for the tuning. - The blue curve shows the measured input impedance after tuning progress. Rectangular diagram: - The blue curve illustrates the theoretical receiver input impedance with the determined start values for the tuning. - The red curve shows the measured input impedance after tuning progress. Figure 1-2. Input Impedance of ATA5723 before and after Matching ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 5 Figure 1-3. Input Impedance of ATA5724 before and after Matching Figure 1-4. Input Impedance of ATA5728 before and after Matching 6 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 2. Development Board Atmel’s receiver development boards can be ordered with the SAP number ATA5723-DK, ATA5724-DK and ATA5728-DK. The development boards contain an interface to the mother boards ATAB-RFMB or ATAB-STK-F. The connection with the mother boards allows the receivers to be configured with a personal computer via the serial data interface. Figure 2-1 shows the schematic of the development boards. Figure 2-2 to Figure 2-4 show the layout of the development board. The bill of material is listed in the Table 2-1 on page 10. Figure 2-1. Schematic of Atmel’s Development Board VS C7 + 2.2μF C6 10nF IC_ACTIVE R7 R3 R2 GND Sensitivity reduction DATA D1 1 C14 DATA 2 18 CDEM DGND AVCC DATA_CLK C12 17 16 5 TEST1 MODE C11 MODE 15 6 RSSI DVCC AGND XTAL2 LNAREF XTAL1 7 14 13 8 C17 DATA_CLK POLLING/_ON 4 COAX R4 19 IC_ACTIVE 3 RSSI POLLING/_ON 20 SENS 9 R5 Q1 12 LNA_IN TEST3 LNAGND TEST2 10 11 L3 Mode C10 R6 Figure 2-2. Layout of Atmel’s Development Board (Top Layer) ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 7 Figure 2-3. Layout of Atmel’s Development Board (Bottom Layer) Figure 2-4. Layout of Atmel’s Development Board (Designator Layer) 8 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 Layout hints for a general application using the receivers: 1. The blocking capacitors (for AVCC and DVCC) must be placed as near as possible to the IC. 2. If the signal from the DATA_CLK will be used and connected to a microprocessor, the trace for this connection must be designed as short as possible and as far as possible from the crystal area. Figure 2-5 shows an ineffectual design for the DATA CLK trace. 3. If the trace between DATA_CLK and the microprocessor is relative long, a resistor can be inserted in series into the trace. This is particularly useful if EMC and coupling effects are a design issue. Figure 2-5. An Example of a Bad Wiring of the DATA_CLCK Trace ATA5723/24/28 XTAL DATA_CLK ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 9 Table 2-1. Bill of Material of the Development Boards Component List ATA5723/24/28-DK V1.0 Housing Manufacture/ Distributor ATA5723 SS020 Atmel® ATA5724 SS020 Atmel x ATA5728 SS020 Atmel Components pcs 315MHz 433MHz 868MHz Value x U1 1 x Tolerance Material/Series R2 1 x x x 56k 5% SMD 0603 R3 1 x x x 8.2k 5% SMD 0603 R4 1 x x x 0 SMD 0603 R5 1 x x 10k 5% SMD 0603 R6 1 x 10k 5% SMD 0603 R7 1 x 1.8k 5% SMD 0603 x x C2 n.m. Murata® C6, C12, C13 3 x x x 10nF 10% X7R 0603 C7 1 x x x 2.2µ/35V 20% Tantal Size 3528 mm/BfB C10, C11 2 x x x 18pF 5% COG 0603 Murata C14 1 x x x 39n 10% X7R 0603 Murata 3pF 5% COG 0603 Murata x C17 D1 1 1 x x x 2.2pF 5% COG 0603 Murata x 1.8pF 5% COG 0603 Murata x x TLMD3100 P-LCC-2 (sizeB) Vishay® 39nH 5% FSL LL1608 TOKO® 22nH 5% FSL LL1608 TOKO 5.6nH 5% FSL LL1608 TOKO Metal lid 5mm 3.2mm KDS 12 pins/ 0.1” pitch CAB x L3 1 x x x Q1 1 X1, X2 2 X5 14.71875MHz x 13.528MHz x 13.55234MHz x x x Row connector 800-10-012-10-001 x x x SMB connector R114 426 000 x x x Pin connector - white 240-333 TP1Data, TP2Polling, TP3Active, TP4DCLK, TP5RSSI 5 X3 1 x x x Pin connector - red 240-345 X4 1 x x x Pin connector - black 240-333 PCB 1 ATA5723/24/28-DK V1.0 NoSAW FR4/1.5 mm 10 Radiall® Single pin ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 Farnell Wagner 3. Evaluation of Receivers using ATA5723/24/28-DK and RF Design Kit Software One of the benefits of using the receiver ATA5723/24/28 is the reuse of the ATA5743/60 software. For evaluation with the Atmel’s RF Design Kit software up to V1.05, the designer can use the existing settings of ATA5743 (ATA5760), as follow: ● Choose receiver setting “T5743 (315MHz)” for configuration of ATA5723 ● ● Choose receiver setting “T5743 (433MHz)” for configuration of ATA5724 Choose receiver setting “T5760 (868MHz)” for configuration of ATA5728 With the RF Design Kit software V1.06 the optimum settings for the receiver are implemented. The suitable receiver settings are described by receiver type as well as the operating frequency under the Receiver pull down menu, as follow: ● The setting “ATA5723 (315MHz)” ● ● The setting “ATA5724 (433MHz)” The setting “ATA5728 (868MHz)” For a more detailed description of the RF Design Kit software and ATAB-RFMB (ATAB-STK-F), please refer to the application notes “ATAK57xx and ATAK862xx hardware description” and “ATAK57xx, ATAK57xx-F, ATAK862xx and ATAK862xx-F software description”. The documents also explain how to evaluate the RF system Link between Atmel’s receivers and suitable transmitter products. ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 11 4. Consideration of the Transmission Protocol Manchester coding is required for the optimal operation of the receivers. Therefore the explanation in this section assumes that the telegram of the system is Manchester encoded. For a general application, the recommended protocol will consist of preburst, start bit, and data. The preburst is the first part of the telegram with an identical number of bits, “111111…” as well as “00000…”. The start bit is defined by changing the bit from “1” to “0” (or from “0” to “1”). Figure 4-1 illustrates this protocol. Figure 4-1. The Recommended Protocol (Manchester Coding) Start Bit Preburst Data Preburst "1" "1" "1" "1" Data "1" "1" "1" "1" "0" Start Bit Preburst length is very important item in the definition of the protocol timing. This value depends on the defined sleep time, start-up time of the receiver, the number of the bit check and last but not least the start-up time of the microcontroller. TPreburst ≥ TSleep + TStartup + TBit-check + TStartup_uC Equation 20 The following is an example for the definition of the preburst length. It is assumed that the system has the following requirements. ● Receiving frequency: 433.92MHz ● ● ● ● Data rate: 1kBps (Manchester) Sleep time: 12.71ms Number of the bit check: 3 Start-up time of the microcontroller: 1ms The maximum time for the bit check (NBit-Check = 3) will be estimated as 3.5/fsig. In case of 1kBps the TBit-Ckeck = 3.5ms. The startup time for BR_Range0 is 1.827ms (TStartup). TPreburst ≥ 12.71ms + 1.827ms + 3.5ms + 1ms = 19.037ms TPreburst ≥ 19.037ms, which a means minimum 20 bits (Manchester) are only necessary for the preburst. For security the number of preburst bits can be defined as 25 bits. 12 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 5. Bit Check Limits The basic of the bit check processing is the internally measurement of the timing between EDGE to EDGE (please see Figure 5-1) on the demodulator output. TLim_min and TLim_max create the time window for bit check processing. Both values can be set in the Limit Register of the receiver. Figure 5-1. Valid Time Window for Bit Check 1/fSig tee Dem_out TLim_min TLim_max Figure 5-2 shows an example of a successful bit check with the NBit_Check = 3. The number of bit check means here the number of Manchester encoded bit. If the bit check is successful the receiver leaves the bit check mode and the data will be transferred to the pin DATA (receiving mode). Figure 5-2. Successful Bit Check Processing with Bit Check = 3 Bit check ok IC_ACTIVE Bit check 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit 1/2 Bit Dem_out Data_out (DATA) TStart-up TBit-check Start-up mode Bit-check mode Bit 1 Note: Receiving mode Bit 2 Bit 3 ½ Bit here means ½ Manchester encoded Bit Figure 5-3. Failed Bit Check Processing Bit check failed IC_ACTIVE Bit check 1/2 Bit Dem_out TStart-up TBit-check TSleep Start-up mode Bit-check mode Sleep mode Bit 1 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 13 Figure 5-3 shows a failed bit check. As soon as the bit check failed, the receiver breaks the bit check processing and goes into the sleep mode. The limits of the bit check must be defined very carefully because these values determine both the wake-up behavior and the sensitivity of the receiver. The limit values must be set such that the receiver will not be woken up by noise and the sensitivity will not be reduced. The calculation of the limit must consider the jitter effect of the signal, which occurs in case of a weak input signal. The best compromise between the sensitivity and the susceptibility to noise will be achieved with a bit check’s valid time window between ±25% to ±30%. The equations 21 and 22 show the correlation between the bit check’s time limit and the setting values in the LIMIT register. Tlim_min = Lim_min Txclk Equation 21 Tlim_max = (Lim_max-1) Txclk Equation 22 Note: Lim_Min and Lim_max are the values set in the LIMIT register. TXCLK is the extended basic clock cycle for the different data ranges - TXCLK for BR_Range0 is 8xTCLK - TXCLK for BR_Range1 is 4xTCLK - TXCLK for BR_Range2 is 2xTCLK - TXCLK for BR_Range3 is 1xTCLK - TCLK is the basic clock cycle and derived from the crystal frequency. For ATA5723, this value will be defined as 30/fXTO, whereas for ATA5724/28 the value is 28/fXTO. In addition to the bit check limits, there are 2 other important limit values in respect to the time violation of the Manchester coding, the Lim_min2T and Lim_max2T. The values will be internally calculated based on the values of Lim_min and Lim_max. Lim_min2T = (Lim_min + Lim_max) – (Lim_max-Lim_min) 0.5 Equation 23 Lim_max2T = (Lim_min + Lim_max) + (Lim_max-Lim_min) 0.5 Equation 24 For the example calculation in this section Tlim_min and Tlim_max are defined with ±25% of the 0.5 Tsig. The values Tlim_min2T and Tlim_max2T must be calculated with ±12.5% of Tsig. Tlim_min = 0.75/(2 fsig) Lim_min = 0.75/(2 fsig TXCLK) Tlim_max = 1.25/(2 fsig) Lim_max = [1.25/(2 fsig TXCLK)] + 1 Lim_min2T = [3.5/(4 fsig TXCLK)] + 0.5 Lim_max2T = [4.5/(4 fsig TXCLK)] + 1.5 5.1 Calculating the Limit Values Due to the Tolerance on the Transmitted Data Rate For the calculation, the data rate including tolerance must be converted into periods. Assume the tolerance of the data rate is x% and the data rate's frequency is fx (the period of the data rate (Tx) is 1/fx). The frequency range for the data rate is given by: x x f x 1 – --------- f x f x 1 + --------- 100 100 Equation 25 The period range of the data rate will be: 1 --------------------------------------1 1 --------------------------------------- --- f x x- x --------------fx 1 – fx 1 + 100 100 1 1 T x ----------------------- T x T x ------------------------ x x 1 – --------- 1 + --------- 100 100 14 Equation 26 Equation 27 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 Figure 5-4 shows the setting of the time limit required for a successful bit check. Figure 5-4. The Required Time Limit Ranges for a Successful Bit Check 1/fSig tee Dem_out tx_min tx_max txlim_min txlim_min Note: Notes to Figure 5-4: - tx_min and tx_max are the possible jitter of the data rate to be received. - txlim_min and txlim_max are the limit values that must be set for an optimal bit check, when the tolerance of the data rate is taken into account. Tx Tx 1 - ------------------------------fx = t x_min = 2 2 x- -------1 + 100 t x_max Tx 1 = ------ ----------------------- 2 x- 1 – -------100 Equation 28 Equation 29 The recommended 25% of the limit values: t xlim_min Tx 1 = 0.75 ------ ------------------------ 2 x 1 + -------100 Equation 30 t xlim_max Tx 1 = 1,25 ------ ----------------------- 2 x- 1 – -------100 Equation 31 The values of the limit_2T will be calculated internally as follows (±12.5%): t xlim_min 2T t xlim_max 2T 1 = 0.875 T x ------------------------ x- 1 + ------- 100 1 = 1.125 T x ----------------------- x- 1 – ------- 100 Equation 32 Equation 33 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 15 5.2 Example Data rate = 2.2kBit/s (fsig) with a tolerance of ±5% Txclk = 8.278µs 8.3µs (for receiving frequency at 433.92MHz) 5 5 2200 1 – --------- f x 2200 1 + --------- 2090Hz f x 2310Hz 100 100 1 - 1 - -------------------------------------------Tx Tx Tx 478.47µs T x 432.9µs x- x- 1 – ------- 1 + ------- 100 100 The tolerance of the data rate’s period is –4.8% and +5.3%. Tx 1 432.9 t xlim_min = 0.75 ------ ------------------------ = 0.75 ------------- = 162.34µs 2 2 x - 1 + -------100 Tx 1 478.47 t xlim_max = 1.25 ------ ----------------------- = 1.25 ---------------- = 299.04µs 2 2 x- 1 – -------100 t xlim_min 2T t xlim_max 2T 1 = 0.875 T x ------------------------ = 0.875 432.9 = 378.79µs x 1 + ------- 100 1 = 1.125 T x ----------------------- = 1.125 478.47 = 538.28µs x 1 – --------- 100 The possible setting Lim_min = 17 and Lim_max = 39 in the Limit register means: TLim_min = 17 8.3µs = 141.1µs TLim_max = (39 – 1) 8.3µs = 315.4µs The values are optimal for the bit check because: Tlim_min < txlim_min and Tlim_max > txlim_max The limit setting is also optimal for the perfect Manchester coding: Lim_min2T = 45 Tlim_min2T = 373.5µs < txlim_min2T Lim_max2T = 67 Tlim_max2T = 556.1µs > txlim_max2T 16 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 6. DATA filter The data filter circuitry of the analog signal processing is mostly integrated except for the external capacitor CDEM, which determines the lower cut-off frequency of the data filter (fcu_DF) together with the internal resistor of 30k. The capacitor’s value must set according to the desired data ranges. The upper cut-off frequency (fu_DF) is defined automatically by the setting of the BR_Range. Equation 34 shows the calculation of the lower cut-off frequency. 1 f CU_DF = ---------------------------------------------------2 30 k CDEM Table 6-1. 7. Equation 34 The Recommended CDEM Value of the Related Data Filter’s Cut-off Frequency CDEM Lower cut-off Frequency Upper cut-off Frequency BR_Range0 39nF 0.136kHz 3.4kHz BR_Range1 22nF 0.241kHz 6kHz BR_Range2 12nF 0.442kHz 10kHz BR_Range3 8.2nF 0.647kHz 19kHz IC_ACTIVE for LNA The pin IC_ACTIVE is designed to signal the status of the receiver, i.e., if the receiver is in sleep mode or active (receiving) mode. Therefore, this pin can be also used to control the biasing of an external preamplifier to boost the sensitivity of the receiver. The pin is specified for a current consumption of 1 mA. Therefore, is the pin is suitable only for biasing of the preamplifier and can not drive the preamplifier’s supply current. The saturation voltage of the pin is specified as a typical value of 4.85V and minimum value of 4.6V. 8. The External Circuitry of Pin DATA 8.1 Determining the Pull-up Resistor Depends on the Load Capacitance The load capacitance on the pin must be taken into account as this can influence the signal quality passed through this pin. Depending on the load capacitance on the pin and the data rate, the pull-up resistor on that pin must be properly determined. Table 8-1 shows the resistor ranges for different data rate ranges for two load capacitance values. Table 8-1. The Recommended Pull-up Resistor (Datasheet Page 32, Table 14-1) - CL ≤ 1nF CL ≤ 100pF BR_range Applicable Rpup B0 1.6k to 47k B1 1.6k to 22k B2 1.6k to 12k B3 1.6k to 5.6k B0 1.6k to 470k B1 1.6k to 220k B2 1.6k to 120k B3 1.6k to 56k ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 17 8.2 Some Hints for Connecting the Pin Data Directly to another Control Module The following conditions can be found in some automotive applications, ● The receiver module doesn't have its own microprocessor. The programming of the receiver as well as the received data processing will be performed by another control module. ● The only connection between the receiver module and the control module is the data interface on pin 20, which is connected directly to the power supply over a pull-up resistor. For this type of application, the receiver circuitry must be protected against both load dump and jump start. 8.2.1 Principle Circuit for Protection against Load Dump and Jump Start Figure 8-1 type 1 and type 2 give two possibilities for a protecting circuit. In the first circuit type 1, the protection will be performed by the LC low-pass filter, the protection diode (D1) as well as the voltage regulator. Depending on the needs, the inductor can be replaced by a resistor. A TVS (Transient Voltage Suppressor) diode is optimal for D1. In some cases a Zener diode can be used also. Figure 8-1. Principle Circuit of a Protection against Load Dump and Jump Start Type 1 12V 5V 12V 5V Rpup TP D1 T5743 Controller AVCC DVCC IC1 IC2 Type 2 12V D2 12V 12V 5V 5V Rpup TP D1 T5743 AVCC Controller DVCC IC1 IC2 In the circuit type 2 the pull up resistor is connected directly to the 12V power supply instead of 5V regulated power supply. A protecting diode D2 must be placed between the power supply line and the pull-up resistor protecting the data out. 18 ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 8.2.2 Shifting of the Ground Potential A “relatively” long connection between the receiver (pin data) and the control module can cause a fail of programming because of a different ground potential between the control module and the receiver module. This “shift” of the ground potential could distort the signal low level decision. If the receiver can not detect the low level set by the microprocessor, the circuit can not be programmed successfully. Generally the pin data can recognize a signal voltage 0.35 VS = 0.35 5V d 1.7V as “LOW”. This must be secured also in case of production variations. One possible solution would be to use a switch transistor in the control module, as illustrated in Figure 8-2. Figure 8-2. Principle Application Circuit with a Switch Transistor Controlling the Serial Data Interface of the Receiver Microcontroller Control module 9. Revision History Please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. Revision No. History 9118C-AUTO-05/15 Put document in the latest template Section 2 “Calculating the Required Crystal Frequency” on page 2 updated 9118B-AUTO-09/08 Section 5 “Evaluation of Receivers using ATA5723/24/28-DK and RF Design Kit Software” on page 12 updated ATA5723/ATA5724/ATA5728 [APPLICATION NOTE] 9118C–AUTO–05/15 19 XXXXXX Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com © 2015 Atmel Corporation. / Rev.: 9118C–AUTO–05/15 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation in U.S. and other countries. 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