Low Power, High Output Current, Quad Op Amp, Dual-Channel ADSL/ADSL2+ Line Driver AD8392 PIN CONFIGURATIONS VEE1, 2 1 28 GND PD0 1, 2 2 27 NC PD1 1, 2 3 26 NC +VIN1 4 –VIN1 5 1 25 +VIN2 2 24 –VIN2 VOUT1 6 VCC1, 2 7 NC 8 21 VCC3, 4 VOUT3 9 20 VOUT4 23 VOUT2 22 NC AD8392 –VIN3 10 3 +VIN3 11 19 –VIN4 4 18 +VIN4 NC 12 17 PD1 3, 4 NC 13 16 PD0 3, 4 GND 14 15 VEE3, 4 NC = NO CONNECT +VIN2 NC VCOM1, 2 GND PD0 1, 2 VEE1, 2 PD1 1, 2 Figure 1. AD8392ARE, 28-Lead TSSOP/EP +VIN1 Four current feedback, high current amplifiers Ideal for use as ADSL/ADSL2+ dual-channel Central Office (CO) line drivers Low power operation Power supply operation from ±5 V (+10 V) up to ±12 V (+24 V) Less than 3 mA/Amp quiescent supply current for full power ADSL/ADSL2+ CO applications (20.4 dBm line power, 5.5 CF) Three active power modes plus shutdown High output voltage and current drive 400 mA peak output drive current 44 V p-p differential output voltage Low distortion −72 dBc @1 MHz second harmonic −82 dBc @ 1 MHz third harmonic High speed: 900 V/µs differential slew rate Additional functionality of AD8392ACP On-chip common-mode voltage generation 04802-0-001 FEATURES 32 31 30 29 28 27 26 25 The AD8392 is available in two thermally enhanced packages, a 28-lead TSSOP EP (AD8392ARE) and a 5 mm × 5 mm 32-lead LFCSP (AD8392ACP). Four bias modes are available via the use of two digital bits (PD1, PD0). VOUT3 6 –VIN3 7 NC 8 AD8392 3 9 4 NC 23 –VIN2 22 VOUT2 21 NC 20 VCC3, 4 19 VOUT4 18 –VIN4 17 NC 10 11 12 13 14 15 16 04802-0-002 5 +VIN4 4 NC PD1 3, 4 VCC1, 2 VEE3, 4 3 PD0 3, 4 VOUT1 2 GND The AD8392 is comprised of four high output current, low power consumption, operational amplifiers. It is particularly well suited for the CO driver interface in digital subscriber line systems, such as ADSL and ADSL2+. The driver is capable of providing enough power to deliver 20.4 dBm to a line, while compensating for losses due to hybrid insertion and back termination resistors. In addition, the low distortion, fast slew rate, and high output current capability make the AD8392 ideal for many other applications, including medical, instrumentation, DAC output drivers, and other high peak current circuits. 24 1 VCOM3, 4 GENERAL DESCRIPTION 2 NC ADSL/ADSL2+ CO line drivers XDSL line drives High output current, low distortion amplifiers DAC output buffer –VIN1 +VIN3 APPLICATIONS NC 1 Figure 2. AD8392ACP, 32-Lead LFCSP 5 mm × 5 mm Additionally, the AD8392ACP provides VCOM pins for on-chip common mode voltage generation. The low power consumption, high output current, high output voltage swing, and robust thermal packaging enable the AD8392 to be used as the CO line drivers in ADSL and other xDSL systems, as well as other high current, single-ended or differential amplifier applications. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. AD8392 TABLE OF CONTENTS Specifications..................................................................................... 3 Power Management ................................................................... 12 Absolute Maximum Ratings............................................................ 5 Driving Capacitive Loads.......................................................... 12 Thermal Resistance ...................................................................... 5 Thermal Considerations............................................................ 13 ESD Caution.................................................................................. 5 Typical ADSL/ADSL2+ Application ........................................ 13 Typical Performance Characteristics ............................................. 6 Multitone Power Ratio............................................................... 14 Theory of Operation ...................................................................... 11 Lightning and AC Power Fault ................................................. 15 Applications..................................................................................... 12 Outline Dimensions ....................................................................... 16 Supplies, Grounding, and Layout ............................................. 12 Ordering Guide .......................................................................... 16 Resistor Selection........................................................................ 12 REVISION HISTORY 7/04—Revision 0: Initial Version Rev. 0 | Page 2 of 16 AD8392 SPECIFICATIONS VS = ±12 V or +24 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted. Table 1. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large Signal Bandwidth Peaking Slew Rate NOISE/DISTORTION PERFORMANCE Second Harmonic Distortion Third Harmonic Distortion Multitone Input Power Ratio Voltage Noise (RTI) +Input Current Noise −Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage +Input Bias Current −Input Bias Current Input Resistance Input Capacitance Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Differential Output Voltage Swing Single-Ended Output Voltage Swing Linear Output Current POWER SUPPLY Operating Range (Dual Supply) Operating Range (Single Supply) Total Quiescent Current PD1, PD0 = (0, 0) PD1, PD0 = (0, 1) PD1, PD0 = (1, 0) PD1, PD0 = (1, 1) (Shutdown State) PD = 0 Threshold PD = 1 Threshold +Power Supply Rejection Ratio −Power Supply Rejection Ratio Min Typ 30 20 850 −5.0 64 42.0 21.0 Unit Test Conditions/Comments 40 25 0.05 900 MHz MHz dB V/µs VOUT = 0.1 V p-p, RF = 2 kΩ VOUT = 4 V p-p, RF = 2 kΩ VOUT = 0.1 V p-p, RF = 2 kΩ VOUT = 20 V p-p, RF = 2 kΩ −72 −82 −70 4.3 10 13 dBc dBc dBc nV/√Hz pA/√Hz pA/√Hz fC = 1 MHz, VOUT = 2 V p-p fC = 1 MHz, VOUT = 2 V p-p 26 kHz to 2.2 MHz, ZLINE = 100 Ω Differential Load f = 10 kHz f = 10 kHz f = 10 kHz mV µA µA kΩ pF dB V+IN − V−IN ∆VOUT ∆VOUT RL = 10 Ω, fC = 100 kHz ±3.0 5.0 10.0 400 2.0 68 +5.0 10.0 15.0 44.0 22.0 400 46.0 23.0 V V mA ±12 24 V V 7.0 4.0 3.3 1.2 0.8 mA/Amp mA/Amp mA/Amp mA/Amp V V dB dB ±5 10 6.0 3.6 2.8 0.4 1.8 64 76 Max 68 79 Rev. 0 | Page 3 of 16 (∆VOS, DM (RTI))/(∆VIN, CM) ∆VOS, DM (RTI)/∆VCC, ∆VCC = ±1 V ∆VOS, DM (RTI)/∆VEE, ∆VEE = ±1 V AD8392 VS = ±5 V or +10 V, RL = 100 Ω, G = +5, PD = (0, 0), T = 25°C, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE −3 dB Small Signal Bandwidth −3 dB Large signal Bandwidth Peaking Slew Rate (Rise) Slew Rate (Fall) NOISE/DISTORTION PERFORMANCE Second Harmonic Distortion Third Harmonic Distortion Voltage Noise (RTI) +Input Current Noise −Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage +Input Bias Current −Input Bias Current Input Resistance Input Capacitance Common-Mode Rejection Ratio OUTPUT CHARACTERISTICS Differential Output Voltage Swing Single-Ended Output Voltage Swing Linear Output Current POWER SUPPLY Operating Range (Dual Supply) Operating Range (Single Supply) Total Quiescent Current PD1, PD0 = (0, 0) PD1, PD0 = (0, 1) PD1, PD0 = (1, 0) PD1, PD0 = (1, 1) (Shutdown State) PD = 0 Threshold PD = 1 Threshold +Power Supply Rejection Ratio −Power Supply Rejection Ratio Min Typ 30 20 300 400 −5.0 62 14.0 7.0 Unit Test Conditions/Comments 40 25 0.05 350 450 MHz MHz dB V/µs V/µs VOUT = 0.1 V p-p, RF = 2 kΩ VOUT = 4 V p-p, RF = 2 kΩ VOUT = 0.1 V p-p, RF = 2 kΩ VOUT = 7 V p-p, RF = 2 kΩ VOUT = 7 V p-p, RF = 2 kΩ −72 −82 4.3 10 13 dBc dBc nV/√Hz pA/√Hz pA/√Hz fC = 1 MHz, VOUT = 2 V p-p fC = 1 MHz, VOUT = 2 V p-p f = 10 kHz f = 10 kHz f = 10 kHz mV µA µA kΩ pF dB V+IN − V−IN ∆VOUT ∆VOUT RL = 10 Ω, fC = 100 kHz ±3.0 5.0 10.0 400 2.0 66 +5.0 10.0 15.0 16.0 8.0 400 18.0 9.0 V V mA ±12 +24 V V 6.0 4.0 3.0 1.0 0.8 mA/Amp mA/Amp mA/Amp mA/Amp V V dB dB ±5 +10 5.4 3.5 2.6 0.4 1.8 72 64 Max 76 68 Rev. 0 | Page 4 of 16 (∆VOS, DM (RTI))/(∆VIN, CM) ∆VOS, DM (RTI)/∆VCC, ∆VCC = ±1 V ∆VOS, DM (RTI)/∆VEE, ∆VEE = ±1 V AD8392 ABSOLUTE MAXIMUM RATINGS Rating ±13 V (+26 V) See Figure 3 −65°C to +150°C −40°C to +85°C 300°C 150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RMS output voltages should be considered. If RL is referenced to VS− as in single-supply operation, the total power is VS × IOUT. In single supply with RL to VS−, worst case is VOUT = VS/2. Airflow increases heat dissipation, effectively reducing θJA. Also, more metal directly in contact with the package leads from metal traces, through holes, ground, and power planes reduces the θJA. Figure 3 shows the maximum safe power dissipation in the package versus the ambient temperature for the LFCSP-32 and TSSOP-28/EP packages on a JEDEC standard 4-layer board. θJA values are approximations. 7 TJ = 150°C THERMAL RESISTANCE θJA is specified for the worst-case conditions, i.e., θJA is specified for device soldered in circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type LFCSP-32 (CP) TSSOP-28/EP (RE) θJA 27.27 35.33 Unit °C/W °C/W Maximum Power Dissipation 6 5 LFCSP-32 4 TSSOP-28/EP 3 2 1 0 –40 –30 –20 –10 The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). Assuming that the load (RL) is midsupply, the total drive power is VS/2 × IOUT, some of which is dissipated in the package and some in the load (VOUT × IOUT). 0 10 20 30 40 50 TEMPERATURE (°C) 60 70 80 90 04802-0-003 Parameter Supply Voltage Power Dissipation Storage Temperature Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature MAXIMUM POWER DISSIPATION (W) Table 3. Figure 3. Maximum Power Dissipation vs. Temperature for a 4-Layer Board See the Thermal Considerations section for additional thermal design guidance. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 16 AD8392 TYPICAL PERFORMANCE CHARACTERISTICS 950 –45 CREST FACTOR = 5.45 CREST FACTOR = 5.45 900 PD (0, 0) POWER CONSUMPTION (mW) MULTITONE POWER RATIO (dBc) –50 –55 –60 PD (1, 0) PD (0, 1) PD (0, 0) –65 850 800 PD (0, 1) 750 700 PD (1, 0) 650 16 17 19 18 OUTPUT POWER (dBm) 20 21 550 15 16 17 18 19 OUTPUT POWER (dBm) 21 Figure 7. Power Consumption vs. Output Power (26 kHz to 2.2 MHz) ADSL/ADSL2+ Circuit (Figure 32) VS = ±12 V, RLOAD = 100 Ω, CF = 5.45 Figure 4. MTPR vs. Output Power (1.75 MHz Empty Bin) ADSL/ADSL2+ Circuit (Figure 32) VS = ±12 V, RLOAD = 100 Ω, CF = 5.45 –50 –50 HD2 PD (1, 0) HD2 PD (1, 0) HD2 PD (0, 1) HD2 PD (0, 1) –60 HARMONIC DISTORTION (dBc) HARMONIC DISTORTION (dBc) 20 04802-0-007 –70 15 04802-0-004 600 –70 HD2 PD (0, 0) –80 HD3 PD (1, 0) HD3 PD (0, 0) –90 –60 –70 HD2 PD (0, 0) HD3 PD (1, 0) –80 HD3 PD (0, 0) –90 HD3 PD (0, 1) 1 FREQUENCY (MHz) 10 –100 0.1 1 FREQUENCY (MHz) Figure 8. Harmonic Distortion vs. Frequency Dual Differential Driver Circuit (Figure 30) VS = ±5 V, RLOAD = 100 Ω, G = +5, VOUT = 2 V p-p Figure 5. Harmonic Distortion vs. Frequency Dual Differential Driver Circuit (Figure 30) VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 2 V p-p –50 –50 HD2 PD (1, 0) HD2 PD (0, 1) HD2 PD (1, 0) HD2 PD (0, 1) –60 HARMONIC DISTORTION (dBc) –60 –70 –80 HD2 PD (0, 0) HD3 PD (0, 0) HD3 PD (0, 1) –90 HD3 PD (1, 0) –100 –80 HD2 PD (0, 0) HD3 PD (0, 0) HD3 PD (0, 1) –90 HD3 PD (1, 0) –100 1 FREQUENCY (MHz) 10 –120 0.1 1 FREQUENCY (MHz) Figure 9. Harmonic Distortion vs. Frequency Quad Op Amp Circuit (Figure 29) VS = ±5 V, RLOAD = 100 Ω, G = +5, VOUT = 2 V p-p Figure 6. Harmonic Distortion vs. Frequency Quad Op Amp Circuit (Figure 29) VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 2 V p-p Rev. 0 | Page 6 of 16 10 04802-0-009 –120 0.1 –70 –110 –110 04802-0-006 HARMONIC DISTORTION (dBc) 10 04802-0-008 –100 0.1 04802-0-005 HD3 PD (0, 1) AD8392 15 15 10 10 PD (0, 0) PD (0, 0) 5 5 GAIN (dB) –5 PD (0, 1) 0 –5 –10 –10 –15 –15 PD (1, 0) 10 FREQUENCY (MHz) 100 1000 –20 0.1 Figure 10. Small Signal Frequency Response Quad Op Amp Circuit (Figure 29) VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 100 mV p-p 100 1000 0 –10 75Ω 100Ω –20 SIGNAL FEEDTHROUGH (dB) 10 5 GAIN (dB) 10 FREQUENCY (MHz) Figure 13. Small Signal Frequency Response Quad Op Amp Circuit (Figure 29) VS = ±5 V, RLOAD = 100 Ω, G = +5, VOUT = 100 mV p-p 15 0 25Ω 50Ω –5 –10 1Ω –15 4.7Ω –30 –40 –50 –60 –70 –80 10Ω 1 10 FREQUENCY (MHz) 100 –90 04802-0-011 –20 0.1 1 04802-0-013 1 PD (1, 0) 04802-0-010 –20 0.1 1000 –100 0.1 Figure 11. Small Signal Frequency Response vs. Load Quad Op Amp Circuit (Figure 29) VS = ±12 V, G = +5, VOUT = 100 mV p-p 1 10 FREQUENCY (MHz) 100 1000 Figure 14. Signal Feedthrough vs. Frequency Quad Op Amp Circuit (Figure 29) VS = ±12 V, G = +5, VIN = 800 mV p-p, PD (1, 1) 15 15 10 10 PD (0, 0) 5 PD (0, 1) GAIN (dB) 0 –5 –5 –10 –10 –15 –15 PD (1, 0) 1 10 FREQUENCY (MHz) 100 1000 04802-0-012 PD (1, 0) –20 0.1 PD (0, 0) PD (0, 1) 0 –20 0.1 Figure 12. Large Signal Frequency Response Quad Op Amp Circuit (Figure 29) VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 4 V p-p 1 10 FREQUENCY (MHz) 100 Figure 15. Large Signal Frequency Response Quad Op Amp Circuit (Figure 29) VS = ±5 V, RLOAD = 100 Ω, G = +5, VOUT = 4 V p-p Rev. 0 | Page 7 of 16 1000 04802-0-015 GAIN (dB) 5 04802-0-014 GAIN (dB) PD (0, 1) 0 AD8392 2.5 0.06 2.0 OUTPUT VOLTAGE (V) 1.5 0.02 0 –0.02 1.0 0.5 0 –0.5 –1.0 –1.5 –0.04 –6 –4 –2 0 2 TIME (µs) 4 6 8 10 –2.5 –10 –8 –6 –4 –2 0 2 TIME (µs) 4 6 8 10 Figure 19. Large Signal Pulse Response Quad Op Amp Circuit (Figure 29) VS = ±12 V, RLOAD = 100 Ω, G = +5, 4 V Step Figure 16. Small Signal Pulse Response Quad Op Amp Circuit (Figure 29) VS = ±12 V, RLOAD = 100 Ω, G = +5, 100 mV Step PD PINS OUTPUT 1 1 OUTPUT 2 004802-0-017 004802-0-020 2 PD PINS CH1 200mVΩ BW CH2 1.00mVΩ BW M 50.0ns A CH2 CH1 200mVΩBW CH2 1.00VΩBW 2.38V M 400ns CH2 2.38V Figure 20. Power-Down Time: PD (0, 0) to PD (1, 1) Quad Op Amp Circuit (Figure 29) VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 1 V p-p Figure 17. Power-Up Time: PD (1, 1) to PD (0, 0) Quad Op Amp Circuit (Figure 29) VS = ±12 V, RLOAD = 100 Ω, G = +5, VOUT = 1 V p-p ∆: 460ns @: –1.32µs ∆: 420ns @: 2.84µs C1 p-p 27.0V C2 p-p 21.4V C1 p-p 6.00V C2 p-p 21.8V 1 2 1 2 INPUT CH1 5.00VΩ CH2 5.00VΩ M1.00µs CH1 004802-0-021 OUTPUT OUTPUT INPUT CH1 1.00VΩ 700mV CH2 5.00VΩ M1.00µs CH1 800mV Figure 21. Output Overdrive Recovery Quad Op Amp Circuit (Figure 29) VS = ±12 V, RLOAD = 100 Ω, G = +5, VIN = 6 V p-p Figure 18. Input Overdrive Recovery Quad Op Amp Circuit (Figure 29) VS = ±12 V, RLOAD = 100 Ω, G = +1, VIN = 27 V p-p Rev. 0 | Page 8 of 16 04802-0-019 –8 04802-0-016 –2.0 –0.06 –10 004802-0-018 OUTPUT VOLTAGE (V) 0.04 0 0 –10 –10 –20 –20 –30 –30 CROSSTALK (dB) –40 –50 ADSL CHANNEL 3, 4 –60 ADSL CHANNEL 1, 2 –70 –40 –50 DIFF CHANNEL 3, 4 –60 –80 –90 0.1 1 10 FREQUENCY (MHz) 100 04802-0-022 –80 –90 0.1 1 10 FREQUENCY (MHz) 100 Figure 25. Crosstalk vs. Frequency Dual Differential Driver Circuit (Figure 30) VS = ±12 V, G = +5, RLOAD = 100 Ω, VIN = 200 mV p-p Figure 22. Crosstalk vs. Frequency ADSL/ADSL2+ Circuit (Figure 32) VS = ±12 V, G = +11, RLOAD = 100 Ω, VIN = 200 mV p-p 45 0 VS = ±12V –10 DIFFERENTIAL OUTPUT SWING (V) 40 –20 CROSSTALK (dB) DIFF CHANNEL 1, 2 –70 04802-0-025 CROSSTALK (dB) AD8392 –30 –40 –50 –60 CHANNEL 1 –70 CHANNEL 2 CHANNEL 3 –80 35 30 25 20 VS = ±5V 15 100 10 10 Figure 23. Crosstalk vs. Frequency Quad Op Amp Circuit (Figure 29) VS = ±12 V, G = +5, RLOAD = 100 Ω, VIN = 200 mV p-p 40 50 60 70 RESISTIVE LOAD (Ω) 80 90 100 10 0.1 1 10 100 FREQUENCY (kHz) 1000 Figure 24. Voltage Noise vs. Frequency 100 –INOISE 10 1 0.01 +INOISE 0.1 1 10 100 FREQUENCY (kHz) Figure 27. Current Noise vs. Frequency Rev. 0 | Page 9 of 16 1000 04802-0-027 CURRENT NOISE (pA/ Hz) 1000 04802-0-024 VOLTAGE NOISE (nV/ Hz) 30 Figure 26. Differential Output Swing vs. RLOAD ADSL/ADSL2+ Circuit (Figure 32) G = +11 100 1 0.01 20 04802-0-026 1 10 FREQUENCY (MHz) 04802-0-023 CHANNEL 4 –90 0.1 AD8392 180 1G 1k 60 100 40 10 20 1 0 0.1 –20 0.01 –40 0.001 –60 1k 10k 100k 1M 10M –80 1G 100M FREQUENCY (Hz) OUTPUT IMPEDANCE (Ω) 80 PHASE (Degrees) 10k 04802-0-028 100 10 PD (0, 0) PD (0, 1) 1 0.1 0.01 0.01 0.1 10 1 100 1000 FREQUENCY (MHz) Figure 28. Open-Loop Transimpedance and Phase Figure 31. Output Impedance vs. Frequency Quad Op Amp Circuit (Figure 29) VS = ±12 V, G = +5, PD (0, 0) 280kΩ 100nF 866Ω 6.19Ω 162Ω 49.9Ω 2kΩ 226Ω 499Ω VCM 04802-0-033 100Ω 100Ω 100nF 162Ω 2kΩ 100nF 2kΩ 6.19Ω 866Ω 280kΩ Figure 29. Quad Op Amp Circuit 100nF Figure 32. ADSL/ADSL2+ Circuit 49.9Ω 2kΩ 1kΩ 100Ω 2kΩ 100nF 49.9Ω Figure 30. Dual Differential Driver Circuit Rev. 0 | Page 10 of 16 04802-0-032 100nF 04802-0-030 TRANSIMPEDANCE (Ω) 120 TRANSIMPEDANCE 100k 0.0001 100 PD (1, 0) 140 10M 1M 100 160 PHASE 04802-0-031 100M AD8392 THEORY OF OPERATION Of course, for a real amplifier there are additional poles that contribute excess phase, and there is a value for RF below which the amplifier is unstable. Tolerance for peaking and desired flatness determines the optimum RF in each application. RF The open-loop transimpedance is analogous to the open-loop voltage gain of a voltage feedback amplifier. Figure 33 shows a simplified model of a current feedback amplifier. Since RIN is proportional to 1/gm, the equivalent voltage gain is just TZ × gm, where gm is the transconductance of the input stage. Basic analysis of the follower with gain circuit yields RG RIN IIN VIN VO TZ (S ) = G× VIN TZ (S ) + G × RIN + RF R IN = VOUT Figure 33. Simplified Block Diagram where: G = 1+ TZ RN 04802-0-034 The AD8392 is a current feedback amplifier with high (400 mA) output current capability. With a current feedback amplifier, the current into the inverting input is the feedback signal, and the open-loop behavior is that of a transimpedance, dVO/dIIN or TZ. The AD8392 is capable of delivering 400 mA of output current while swinging to within 2 V of either power supply rail. The AD8392 also has a power management system included on-chip. It features four user-programmable power levels (three active power modes as well as the provision for complete shutdown). RF RG 1 ≈ 50 Ω gm Since G × RIN << RF for low gains, a current feedback amplifier has relatively constant bandwidth versus gain, the 3 dB point being set when |TZ| = RF. Rev. 0 | Page 11 of 16 AD8392 APPLICATIONS As with all high speed amplifiers, close attention should be paid to supply decoupling, grounding, and overall board layout. Low frequency supply decoupling should be provided with 10 µF tantalum capacitors from each supply to ground. In addition, all supply pins should be decoupled with 0.1 µF quality ceramic chip capacitors placed as close as possible to the driver. An internal low impedance ground plane should be used to provide a common ground point for all driver and decoupling capacitor ground requirements. Whenever possible, separate ground planes should be used for analog and digital circuitry. High speed layout techniques should be followed to minimize parasitic capacitance around the inverting inputs. Some practical examples of these techniques are keeping feedback traces as short as possible and clearing away ground plane in the area of the inverting inputs. Input and output traces should be kept short and as far apart from each other as practical to avoid crosstalk. When used as a differential driver, all differential signal traces should be kept as symmetrical as possible. The AD8392 exhibits low output impedance for the three active states. However, the output impedance in the shutdown state (PD1, 0 = 1, 1) is undefined. DRIVING CAPACITIVE LOADS When driving a capacitive load, most op amps exhibit peaking in their frequency response. In general, to minimize peaking or to ensure device stability for larger values of capacitive loads, a small series resistor can be added between the op amp output and the load capacitor. Figure 34 shows the frequency response of the AD8392 for various capacitive loads without any series resistance. In this condition, the maximum recommended capacitive load is around 20 pF. As shown in Figure 35, the addition of a 5.1 Ω series resistor limits peaking to approximately 3 dB when driving capacitive loads up to 100 pF. 20 15 20pF 10 15pF 499Ω 2kΩ VIN –10 In current feedback amplifiers, selection of feedback and gain resistors can impact harmonic distortion performance, bandwidth, and gain flatness. Care should be exercised in the selection of these resistors so that optimum performance is achieved. Table 5 shows some suggested resistor values for use in a variety of gain settings. These values are suggested as a good starting point when designing for any application. 10pF 1kΩ CL 50Ω –15 0.1 1 10 100 1000 FREQUENCY (MHz) Figure 34. AD8392 Capacitive Load Frequency Response without Series Resistance 20 100pF 15 Table 5. Resistor Selection Guide 47pF 22pF RG Open 1.5k 249 82.5 10 5 0 499Ω 2kΩ –5 POWER MANAGEMENT 5.1Ω VIN –10 The AD8392 can be configured in any of three active bias states as well as a shutdown state via the use of two sets of digitally programmable logic pins. Pins PD(0, 1) 1, 2 control Amplifiers 1 and 2, while PD(0, 1) 3, 4 control Amplifiers 3 and 4. These pins can be controlled directly with either 3.3 V or 5 V CMOS logic by using the GND pins as a reference. If left unconnected, the PD pins float low, placing the amplifier in the full bias mode. Refer to the Specifications for the per amplifier quiescent current for each of the available bias states. Rev. 0 | Page 12 of 16 CL 50Ω –15 0.1 1 1kΩ 10 100 1000 FREQUENCY (MHz) Figure 35. AD8392 Capacitive Load Frequency Response with Series Resistance 04802-0-035 GAIN (dB) RF 2.0k 1.5k 1.0k 750 0 –5 RESISTOR SELECTION Gain 1 2 5 10 5 04802-0-034 The AD8392 can be powered from either single or dual supplies, with the total supply voltage ranging from 10 V to 24 V. For optimum performance, a well regulated low ripple supply should be used. GAIN (dB) SUPPLIES, GROUNDING, AND LAYOUT AD8392 When using a quad, high output current amplifier, such as the AD8392, special consideration should be given to system level thermal design. In applications such as ADSL/ADSL2+, the AD8392 could be required to dissipate as much as 1.4 W or more on chip. Under these conditions, particular attention should be paid to the thermal design in order to maintain safe operating temperatures on the die. To aid in the thermal design, the thermal information in the Thermal Resistance section can be combined with what follows here. The information in Table 4 and Figure 3 is based on a standard JEDEC 4-layer board and a maximum die temperature of 150°C. To provide additional guidance and design suggestions, a thermal study was performed under a set of conditions more closely aligned with an actual ADSL/ADSL2+ application. This data is only provided as guidance to assist in the thermal design process. Due diligence should be performed with regards to power dissipation because there are many factors that can affect thermal performance. TYPICAL ADSL/ADSL2+ APPLICATION In a typical ADSL/ADSL2+ application, a differential line driver is used to take the signal from the analog front end (AFE) and drive it onto the twisted pair telephone line. Referring to the typical circuit representation in Figure 37, the differential input appears at VIN+ and VIN− from the AFE, while the differential output is transformer coupled to the telephone line at tip and ring. The common-mode operating point, generally midway between the supplies, is set through VCOM. R3 R4 VIN+ In a typical ADSL/ADSL2+ line card, component density usually dictates that most of the copper plane used for thermal dissipation be internal. Additionally, each ADSL/ADSL2+ port may be allotted only 1 square inch, or even less, of board space. For these reasons, a special thermal test board was constructed for this study. The 4-layer board measured approximately 4 inches × 4 inches and contained two internal 1 oz copper ground planes, each measuring 2 inches × 3 inches. The top layer contained signal traces and an exposed copper strip ¼ inch × 3 inches to accommodate heat sinking, with no other copper on the top or bottom of the board. Three 28-lead TSSOPs were placed on the board representing six ADSL channels, or one channel per square inch of copper, with each channel dissipating 700 mW on-chip (1.4 W per package). The die temperature is then measured in still air and in a wind tunnel with calibrated airflow of 100 LFM, 200 LFM, and 400 LFM. Figure 36 shows the power dissipation versus the ambient temperature for each airflow condition. The figure assumes a maximum die temperature of 135°C. No heat sink was used. 4.5 TJ = 135°C VOA VP TIP Rm RBIAS RIN R2 ROUT 1:N VCOM R1 R2 RBIAS VIN– R4 VP Rm RING VOA R3 04802-0-037 THERMAL CONSIDERATIONS Figure 37. Typical ADSL/ADSL2+ Application Circuit In ADSL/ADSL2+ applications, it is common practice to conserve power by using positive feedback to synthesize the output resistance, thereby lowering the required ohmic value of the line matching resistors, Rm. The circuit in Figure 37 is somewhat unique in that the positive feedback introduced via R3 has the effect of synthesizing the input resistance as well. The following definitions and equations can be used to calculate the resistor values necessary to obtain the desired gain, input resistance, and output resistance for a given application. For simplicity the following calculations assume a lossless transformer. 4.0 The following values are used in the design equations and are assumed already known or chosen by the designer. 200LFM VIN RIN N VLINE Rm 3.0 2.5 STILL AIR 2.0 100LFM 1.5 1.0 5 15 25 35 45 55 65 AMBIENT TEMPERATURE (°C) 75 85 04802-0-036 POWER DISSIPATION (W) 400LFM 3.5 R2 VP RL Figure 36. Power Dissipation vs. Ambient Temperature and Air Flow 28-Lead TSSOP/EP Rev. 0 | Page 13 of 16 Differential input voltage Desired differential input resistance Transformer turns ratio Differential output voltage at tip and ring Each is typically 5% to 15% of the transformer reflected line impedance Recommended in the amplifier data sheet Voltage at the + inputs to the amplifier, approximately ½ VIN (must be less than VIN for positive input resistance) Transformer reflected line impedance AD8392 Additional definitions for calculating resistor values include: MULTITONE POWER RATIO VOA Voltage at the amplifier outputs k Matching resistance reduction factor AV Gain from VIN to transformer primary Negative feedback factor β Positive feedback factor α Note: R1 must be calculated before β and α. The DMT signal used in ADSL/ADSL2+ systems carries data in discrete tones or bins, which appear in the frequency domain in evenly spaced 4.3125 kHz intervals. In applications using this type of waveform, multitone power ratio (MTPR) is a commonly used measure of linearity. Generally, there are two types of MTPR that designers are typically concerned with: in-band and out-of-band MTPR. In-band MTPR is defined as the measured difference from the peak of one tone that is loaded with data to the peak of an adjacent tone that is intentionally left empty. Out-of-band MTPR is more loosely defined as the spurious emissions that occur in the receive band located between 25.875 kHz and the first downstream tone at 138 kHz. Figure 38 and Figure 39 show the AD8392 in-band MTPR for a 5.5 crest factor waveform for empty bins in the ADSL and extended ADSL2+ bandwidths. Figure 40 shows the AD8392 out-of-band MTPR for the same waveform. VOA = β= VLINE (1 + k ) N k= 2 Rm RL AV = R1 R1 + 2 R2 VLINE N VIN α = β (1 − k ) With the above known quantities and definitions, the remaining resistors can readily be calculated. R1 = R4 = 2VP R2 VOA − VP –20 R IN (VIN − VP ) 2 VIN –30 –40 AV R4 (2 R1 Rm + R1 RL − α R1 RL − 2α R2 RL ) R3 = α RL (R1 + 2 R2 ) R BIAS = –50 72.2dB –60 –70 –80 α R3 R4 R4 − α (R3 + R4 ) –90 After building the circuit with the closest 1% resistor values, the actual gain, input resistance, and output resistance can be verified with the following equations. GAIN (VIN to LINE ) = R IN = N R4 R4 ⎞ R4 ⎛ β (k + 1)⎜1 + + ⎟− ⎝ R3 R BIAS ⎠ R3 2 ⎛ 2 Rm + RL 1 − AV β⎜⎜ R4 ⎝ R4 RL –110 –120 CENTER 647kHz 1kHz/ SPAN 10kHz 04802-0-038 –100 Figure 38. In-Band MTPR at 647 kHz –20 –30 –40 ⎞ ⎟ ⎟ ⎠ –50 –60 64.4dB –70 2 Rm N 2 ⎛ ⎜ ⎛ R4 R BIAS ⎞⎜ R1 + 2R2 ⎟ 1 − ⎜⎜ ⎟ R4 R BIAS ⎜ R1 R4 R ( ) + BIAS ⎠ ⎝ ⎜ R3 + R4 + R BIAS ⎝ –80 ⎞ ⎟ ⎟ ⎟ ⎟ ⎠ –90 –100 –110 –120 CENTER 1.75MHz 1kHz/ SPAN 10kHz Figure 39. In-Band MTPR at 1.751 MHz Rev. 0 | Page 14 of 16 04802-0-039 ROUT = AD8392 –20 LIGHTNING AND AC POWER FAULT –30 –40 –50 –60 –70 –80 –90 –110 –120 START 3kHz 14.2kHz/ STOP 145kHz 04802-0-040 –100 The AD8392 can be used is as an ADSL/ADSL2+ line driver. In this application, the line driver is transformer-coupled to the twisted pair telephone line and could be subjected to large line transients resulting from events such as lightning strikes or downed power lines. In this type of environment, additional circuitry may be required to protect the AD8392 from damage that may occur as a result of these events. Using a minimal amount of external protection, the AD8392 has successfully passed overvoltage and overcurrent compliance testing per the ITU K-20 specification. For details on the external protection circuitry, contact the high current driver product line at [email protected]. Figure 40. Out-of-Band MTPR Rev. 0 | Page 15 of 16 AD8392 OUTLINE DIMENSIONS 9.80 9.70 9.60 BOTTOM VIEW 28 15 4.50 4.40 4.30 1 EXPOSED PAD (Pins Down) 6.40 BSC 3.00 BSC 14 PIN 1 0.65 BSC 1.20 MAX 0.30 0.19 0.15 0.00 3.50 BSC 1.05 1.00 0.80 SEATING PLANE 0.20 0.09 8° 0° 0.75 0.60 0.45 COMPLIANT TO JEDEC STANDARDS MO-153AET Figure 41. 28-Lead Thin Shrink Small Outline with Exposed Pad [TSSOP/EP] (RE-28-1) Dimensions shown in millimeters 5.00 BSC SQ 0.60 MAX 32 25 24 PIN 1 INDICATOR 0.50 BSC 4.75 BSC SQ TOP VIEW 0.50 0.40 0.30 12° MAX PIN 1 INDICATOR 0.60 MAX 1 3.25 3.10 SQ 2.95 BOTTOM VIEW 17 16 9 8 0.25 MIN 3.50 REF 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM 1.00 0.85 0.80 SEATING PLANE 0.30 0.23 0.18 0.20 REF COPLANARITY 0.08 COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2 Figure 42. 32-Lead Lead Frame Chip Scale Package [LFCSP] 5 mm × 5 mm Body (CP-32-2) Dimensions shown in millimeters ORDERING GUIDE Model AD8392ARE AD8392ARE-REEL AD8392ARE-REEL7 AD8392ACP-R2 AD8392ACP-REEL AD8392ACP-REEL7 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 28-Lead Thin Shrink Small Outline Package (TSSOP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) 32-Lead Lead Frame Chip Scale Package (LFCSP) © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04802–0–7/04(0) Rev. 0 | Page 16 of 16 Package Outline RE-28-1 RE-28-1 RE-28-1 CP-32-2 CP-32-2 CP-32-2