APPLICATION NOTE
How to Simulate I2S Interface With USART Port On
SAM9G15 eMPU
Atmel | SMART SAM9G15 Series
Scope
This application note introduces an example on how to use the USART and Timer
Counter in the Atmel® | SMART ARM®-based SAM9G15 embedded
microprocessor unit (eMPU) to simulate an interface with an Integrated Inter-IC
Sound (I2S) formatted audio codec.
This simulation can be used to provide an audio interface in addition to the I2S
peripheral included in the SAM9G15 device.
References
Type
Item
Atmel Lit. No.
SAM9G15 Datasheet
Datasheet
Software Library
®
11052
Wolfson WM8731 Datasheet
–
SAM9G15 Software Package
–
SMART
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1.
I2S Introduction
I2S (also known as Inter-IC Sound, Integrated Inter-chip Sound, or IIS) is an electrical serial bus interface standard
introduced in 1986 and used for connecting digital audio devices together. It is used to communicate PCM audio
data between integrated circuits in an electronic device. The I2S bus separates clock and serial data signals,
resulting in a lower jitter than the typical communication systems that recover the clock from the data stream.
The I2S transmitter and receiver have the same clock signal for data transmission. The transmitter can be a
master to generate the clock signal or be a slave to use the clock signal from the receiver which acts as a master,
or either of the transmitter and the receiver can be salve and the other controller will act as a master to generate
the clock signal for both.
Figure 1-1 shows the different use-cases.
Figure 1-1.
I2S System Configurations
The I2S bus consists of at least three lines:
Bit clock (also called continuous serial clock): SCK
Word select: WS (also called left right clock LRCLK)
Serial data (SD)
Figure 1-2 shows the typical I2S waveform.
Figure 1-2.
I2S Interface Timing
In this application, SAM9G15 will act as a master to provide the two clocks: SCK and WS. During playback,
SAM9G15 acts as a transmitter and when recording, SAM9G15 acts as a receiver. The codec works as a slave to
be clocked by SAM9G15.
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2.
Device Overview
2.1
SAM9G15 Overview
SAM9G15 is a high performance eMPU with an ARM926 core, running up to 400 MHz.
The SAM9G15 features a graphics LCD controller with 4-layer overlay and 2D acceleration (picture-in-picture,
alpha-blending, scaling, rotation, color conversion), and a 10-bit ADC that supports 4/5-wire resistive touchscreen
panels. Multiple communication interfaces include a soft modem supporting exclusively the Conexant SmartDAA
line driver, HS USB Host and Device and FS USB Host with dedicated onchip transceivers, two HS
SDCard/SDIO/MMC interfaces, USARTs, SPIs, I2S and TWIs.
The 10-layer bus matrix coupled with multiple DMA channels ensures uninterrupted data transfers with minimal
processor overhead.
The External Bus Interface incorporates controllers offering support for 4-bank and 8-bank DDR2/LPDDR,
SDRAM/LPSDRAM, static memories, as well as specific circuitry for MLC/SLC NAND Flash with integrated ECC
up to 24 bits.
2.2
Wolfson WM8731 Codec Overview
The Wolfson WM8731 is a low-power stereo codec with an integrated headphone driver. It supports sample
frequency from 8 kHz to 96 kHz (8/32/44.1/48/88.2/96 kHz) and various word length (16/20/24/32-bit). It also can
be programmed to support different types of Audio Data Interface such as I2S, Left-justified, Right-justified and
DSP mode and it can work in Master or Slave clocking mode. The clock can be generated by the oscillator
connected with the codec if it works in Master mode.
For detailed information of this codec, refer to the Wolfson WM8731 datasheet available on www.cirrus.com.
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3.
Implementation
3.1
Overall Introduction of Solution
In the application, we use two channels of Timer Counter 0 (TC0) to generate BCLK and LRC clock for the codec,
and use USART2 to transmit or receive the PCM data to or from the codec. Figure 3-1 gives the overall diagram of
the signal connection between SAM9G15 and WM8731.
Figure 3-1.
TC USART Signal
TWI0
MCK/2
TWD0
TWCK0
SDIN
SCLK
TCLK0
TIOA0
TC0
BCLK
TCLK1
DACLRC/
ADCLRC
WM8731
TIOA1
SAM9G15
SCK2
USART2
TXD2
DACDAT
RXD2
CTS2
3.2
ADCDAT
GND
Clock Generation
In this application, we select Left-justified mode for the data transfer and receiving. Figure 3-2 illustrates the
waveform of this mode.
Figure 3-2.
Left-justified Waveform
As can be seen from the diagram, the DACDAT or ADCDAT (SD) is available as long as LRC (WS) level changes,
and is sampled from the first rising edge of BCLK (SCK). The data is MSB first ordered.
The Timer Counter (TC) in SAM9G15 includes six identical 32-bit TC channels. Each channel can be configured to
perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse
generation, delay timing and pulse width modulation. In this application, we select two TC channels (TIOA0 and
TIOA1) to generate the waveform for BCLK and DACLRC/ADCLRC.
TIOA0 is selected to generate BCLK and TIOA1 is selected to generate LRC. Both channels are configured as
Waveform mode to provide wave generation.
The TC’s clock source is optional. We select TIMER_CLOCK1 (MCK/2) as the clock source for TIOA0, and use
the TIOA0 output waveform as the clock source for TIOA1.
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Both TIOA0 and TIOA1 use the RA and RC register to set the compare value and every time when the TC counter
reaches the RA or RC value, the TIOA output level will invert. When the TC counter reaches RC value, its value
will be reset to zero, and then continue to increase and so on. With this mode, we can generate the desured
frequency by setting the register value of RA and RC.
To ensure the accuracy of the data transfer, the code is programmed to set the initial status of TIOA0 and TIOA1
output to high level.
Note:
The first time the TC begins to output the waveform, the initial output level of TIOA is low level.
Consequently, in the initialization part, the TC output will be enabled once to make sure that when restarted
the TC output in the following time, its initial status is high level.
How to calculate the RA and RC register value of TIOA0 to generate BCLK with the required frequency:
Freq (tcsrc) = Frequency of clock source of the TC channel
Freq (bclk) = Frequency of the generated waveform
DutyCycle = The duty cycle percent of the positive level of the generated waveform
RC = Freq(tcsrc)/Freq(bclk)
In this application: Freq(tcsrc) = Board_MCK/2
RA = RC * DutyCycle/100
In this application, DutyCycle = 50, so RA = RC/2
How to calculate the RA and RC register value of TIOA1 to generate LRC with the required frequency:
From the waveform diagram, we can see the relationship between BCLK and LRC. Normally in one LRC
cycle, the number of BCLK cycles is not less than two times of the number of sample length (bits per
sample). For example, for the stereo PCM data with 16-bit sample length, every LRC cycle includes at least
32 (2*16) BCLK cycles. So if we take the TIOA0 as the clock source of TIOA1, then the RA register value is
set to bit number per each sample, and RC register value is set to double of bit number per each sample.
RA = Sample length
RC = 2 * Sample length
3.3
Data Transfer
The Universal Synchronous Asynchronous Receiver Transceiver (USART) in SAM9G15 supports specific
operating modes, providing interfaces on SPI, RS485, LIN, ISO7816 and infrared transceivers. In this application,
we select SPI mode of USART to transmit the PCM data to the codec and receive the PCM data from the codec.
To ensure the clock synchronization, the clock of the SPI transfer is connected to the output of TIOA0 (BCLK), so
we need to set the SPI in slave mode.
The maximum data length that can be transferred in SPI mode is 9 bits. Since the normal PCM data length is times
of 8 bits (16, 24, or 32 bits per each sample), we set the data length for SPI transfer to 8 bits.
The data transfer order of MSB first is compliant with the data order requirement of the codec.
We also need to set the SPI transfer mode to read the data in each rising edge of the clock.
Figure 3-3 illustrates the waveform generated for the USART SPI Slave mode.
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Figure 3-3.
3.4
USART SPI Slave Mode Waveform
DMA Configuration
The data transfer of the USART SPI mode can use DMA mode, which will save processor bandwidth and
significantly improve the system efficiency. SAM9G15 DMA can use Single-buffer transfer and Multi-buffer
transfer. In this application, we use the Multi-buffer DMA transfer method: Linked Lists (buffer chaining). The
buffers are linked by the pointer like a chain. The previous buffer contains the descriptor pointer which points to the
next buffer’s location in the system memory. The LLI (Linked List Item) registers should be initialized before DMA
transfer.
Figure 3-4 gives the diagram overview of how to use DMA to transfer data.
Figure 3-4.
DMA Audio Transfer
Buffer in Memory
High Address
Sample n MSB
LLI 0
Buffer in RAM
Sample n LSB
DMAC
Sample n-1 MSB
LLI 1
LLI 2
…...
Sample n-1 LSB
LLI n
… ...
Sample 1 MSB
Sample 1 LSB
Sample 0 MSB
USART2
Sample 0 LSB
… ...
Transmit Register
Receive Register
TX
DACDAT
RX
ADCDAT
Low Address
For detailed description of how LLI DMA works, please refer to section “DMA Controller (DMAC)” in the SAM9G15
datasheet.
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3.5
Communication with the Audio Codec
Before operating the codec (WM8731), we need to configure it to the right working mode. This device can be
programmed with 3-wire or 2-wire interface to access all feature settings such as volume control, mutes, deemphasis, data transfer mode, data format, sample rate, etc.
In this application, we use 2-wire (I2C) mode to communicate with WM8731 to control the audio interface, volume
adjustment, data format, sample frequency and other relative features for the audio playback and recording.
For a detailed description of the codec feature setting, refer to the Wolfson WM8731 datasheet.
3.6
Hardware Connection
This application is realized on the SAM9G15-EK. Hardware modifications need to be made by installing flying
leads before running this demo on the board.
The instructions to modify SAM9G15-EK are the following.
1.
Disconnect the original connection of the following signals:
̶
̶
̶
̶
̶
̶
̶
2.
Remove R147 connected with PA7 (refer to Figure 3-7)
Remove R156 connected with PA21 (refer to Figure 3-7)
Remove R157 connected with PA22 (refer to Figure 3-7)
Remove RR17 connected with PB1 and PB2 (refer to Figure 3-8)
Remove R86, R87, R88, R89 connected with pin3, pin6 and pin7 of WM8731 (refer to Figure 3-6)
Disconnect PA26 with pin4 of WM8731 (refer to Figure 3-6)
Disconnect PA25 with pin5 of WM8731 (refer to Figure 3-6)
Connect the corresponding signals according to the following direction:
TC0 → TIOA0 (PA21) connects to USART2 → SCK (PB2) and BCLK (pin3) of WM8731
̶
̶
TC0 → TIOA1 (PA22) connects to DACLRC (pin5) and ADCLRC (pin7) of WM8731
̶
USART2 → SCK (PB2) connects to TC0 → TIOA0 (PA21)
̶
USART2 → TXD (PA7) connects to DACDAT (pin4) of WM8731
̶
USART2 → RXD (PA8) connects to ADCDAT (pin6)
̶
USART2 → CTS (PB1) connects to GND
Figure 3-5, Figure 3-6, Figure 3-7 and Figure 3-8 are the schematics with the signals that need to be modified.
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Atmel-11260A-ATARM-How-to-Simulate-I2S-Interface-With-USART-Port-On-SAM9G15-eMPU-ApplicationNote_17-Mar-15
A
B
C
D
PA25
PA27
PA29
PC0
PC2
PC4
PC7
PC9
PC11
PC12
PC14
PC17
PC19
PC21
PC22
PC24
PC26
PC29
PC31
VDDANA
PB0
PB2
PB4
PB6
PB8
PB9
PB11
PB13
PB15
PB17
PB18
{8}
{8}
{8}
{14}
{14}
{14}
{14}
{14}
{14}
{14}
{14}
{14}
{11,14}
{11,14}
{7,14}
{7,14}
{11,14}
{11,14}
{11}
{10}
{10}
{10}
{10}
{10}
{10}
{14}
{14}
{14}
{12}
{13,14}
PA16
PA18
PA20
PA5
PA10
{5}
{5}
{5}
{6}
{6,7}
{6,7,14}
{5,7}
{5}
{5}
{5,6,14}
PA8
PA22
PA31
PA0
PA2
PA4
PA11
PA13
{5}
{12,14}
{12}
{12}
{6,14}
{8,14}
PD10
PD12
PD14
PD16
PD18
PD20
5
{12}
{12}
{10}
{10}
{10}
{10}
ONE_WIRE
E0_RX0
E0_RXER
E0_TXCK
E0_MDC
E0_INTR
E0_TX0
E1_TXCK
E1_MDIO
E1_INTR
E1_TX1
E1_RX1
TF
RD
RF
CANTX1
CANTX0
(MCI0_CDA)
(MCI0_DA1)
(MCI0_DA3)
(MCI1_DA1)
(MCI1_DA3)
(MCI1_DA0)
(MCI1_CK)
USBA_DM
USBA_DP
DIBP
DIBN
USBB_DM
USBB_DP
{12}
{12}
{9}
{9}
USBC_DP
USBC_DM
{12}
{12}
5
ETH0_TX+
ETH0_TXETH0_RX+
ETH0_RX-
AD0_XP
AD2_YP
AD4_LR
OVCUR_USB
LCDDEN
PB0
PB2
PB4
PB6
PB8
PB9
PB11
PB13
PB15
PB17
PB18
PC29
PC31
PC17
PC19
PC21
PC22
PC24
PC26
LCDDAT17
LCDDAT19
LCDDAT21
LCDDAT22
LCDDISP
LCDPWM
TXD3
RTS3
PC7
PC9
PC11
PC12
PC14
LCDDAT7
LCDDAT9
LCDDAT11
LCDDAT12
LCDDAT14
ISI_D7
ISI_D9
ISI_D11
ISI_PCK
ISI_HSYNC
PC0
PC2
PC4
PA25
PA27
PA29
PA16
PA18
PA20
PA5
PA10
PA8
PA22
PA31
PA0
PA2
PA4
PA11
PA13
LCDDAT0
LCDDAT2
LCDDAT4
VDDIOP1
SPI1_MOSI
ZB_IRQ1
SPI1_NPCS1
PD10
PD12
PD14
PD16
PD18
PD20
PD0
PD2
PD4
PD6
PD8
ISI_D0
ISI_D2
ISI_D4
DTXD
TWCK0
TXD0
RTS0
VDDIOP0
ZB_RSTN
EN5V_HDA#
EN5V_HDC#
(MCI1_CD)
VDDNF
3V3
How to Simulate I2S Interface With USART Port On SAM9G15 eMPU [APPLICATION NOTE]
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41
43
45
47
49
51
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61
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199
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
4
KEY
1612618-4
GND7
RFU11
RFU13
RFU15
RFU17
GND9
RFU19
RFU21
RFU23
RFU25
VDDNF1
PD0/NANDOE
PD2/A21/NANDALE
PD4/NCS3
PD6/D16
PD8/D18
NC
PD10/D20
PD12/D22
PD14/D24
PD16/D26/A23
PD18/D28/A25
PD20/D30/NCS4
VDDIOP0_0
PA0/TXD0/SPI1_NPCS1
PA2/RTS0/MCI1_DA1/E0_ETX0
PA4/SCK0/MCI1_DA3/E0_ETXER
PA11/SPI0_MISO/MCI1_DA0
PA13/SPI0_SPCK/MCI1_CK
GND13
PA8/TIOA0/SPI1_MISO
PA22/TIOA1/SPI1_MOSI
PA31/TWCK0/SPI1_NPCS2/E0_ETXEN
GND14
PA16/MCI0_CDA
PA18/MCI0_DA1
PA20/MCI0_DA3
PA5/TXD1/CANTX1
PA10/DTXD/CANTX0
GND15
PA25/TCLK1/TF
PA27/TIOB0/RD
PA29/TIOB2/RF
VDDIOP1_0
PC0/LCDDAT0/ISI_D0/TWD1
PC2/LCDDAT2/ISI_D2/TIOA3
PC4/LCDDAT4/ISI_D4/TCLK3
GND18
PC7/LCDDAT7/ISI_D7/TCLK4
PC9/LCDDAT9/ISI_D9/URXD0
PC11/LCDDAT11/ISI_D11/PWM1
PC12/LCDDAT12/ISI_PCK/TIOA5
PC14/LCDDAT14/ISI_HSYNC/TCLK5
GND20
PC17/LCDDAT17/URXD1
PC19/LCDDAT19/E1_TX1/PWM1
PC21/LCDDAT21/E1_RX1/PWM3
PC22/LCDDAT22/TXD3
PC24/LCDDISP/RTS3
PC26/LCDPWM/SCK3
GND22
PC29/LCDDEN/E1_TXCK/SCK1
PC31/FIQ/E1_MDIO/PCK1
VDDANA_0
PB0/E0_RX0/RTS2
PB2/E0_RXER/SCK2
PB4/E0_TXCK/TWD2
PB6/E0_MDC/AD7
PB8/E0_TXER/AD9
PB9/E0_TX0/PCK1/AD10
PB11/E0_TX2/PWM0/AD0
PB13/E0_RX2/PWM2/AD2
PB15/E0_RXCK/AD4
PB17/E0_COL/AD6
PB18/IRQ/ADTRG
GND23
ETH0_TX+
ETH0_TXETH0_RX+
ETH0_RX-
VCC1
VCC3
GND1
USBC_DP
USBC_DM
GND3
USBB_DM
USBB_DP
GND4
DIBP
DIBN
GND5
USBA_DM
USBA_DP
GND6
RFU1
RFU3
RFU5
RFU7
RFU9
CON1
VCC2
VCC4
VBAT
JTAGSEL
WKUP
SHDN
BMS
nRST
nTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
RFU2
RFU4
RFU6
RFU8
RFU10
3
GND8
RFU12
RFU14
RFU16
RFU18
GND10
RFU20
RFU22
RFU24
RFU26
VDDNF2
PD1/NANDWE
PD3/A22/NANDCLE
PD5/NWAIT
PD7/D17
PD9/D19
GND11
PD11/D21
PD13/D23
PD15/D25/A20
PD17/D27/A24
PD19/D29/NCS2
PD21/D31/NCS5
VDDIOP0_1
PA1/RXD0
PA3/CTS0/MCI1_DA2/E0_ETX1
GND12
PA12/SPI0_MOSI/MCI1_CDA
PA14/SPI0_NPCS0
PA7/TXD2
PA21/RXD2/SPI1_NPCS0
PA23/TIOA2/SPI1_SPCK
PA30/TWD0/SPI1_NPCS3/E0_EMDC
PA15/MCI0_DA0
PA17/MCI0_CK
PA19/MCI0_DA2
GND16
PA6/RXD1/CANRX1
PA9/DRXD/CANRX0
PA24/TCLK0/TK
PA26/TCLK2/TD
PA28/TIOB1/RK
GND17
VDDIOP1_1
PC1/LCDDAT1/ISI_D1/TWCK1
PC3/LCDDAT3/ISI_D3/TIOB3
PC5/LCDDAT5/ISI_D5/TIOA4
PC6/LCDDAT6/ISI_D6/TIOB4
PC8/LCDDAT8/ISI_D8/UTXD0
PC10/LCDDAT10/ISI_D10/PWM0
GND19
PC13/LCDDAT13/ISI_VSYNC/TIOB5
PC15/LCDDAT15/ISI_MCK
PC16/LCDDAT16/E1_RXER/UTXD1
PC18/LCDDAT18/E1_TX0/PWM0
PC20/LCDDAT20/E1_RX0/PWM2
GND21
PC23/LCDDAT23/RXD3
PC25/CTS3
PC27/LCDVSYNC/E1_TXEN/RST1
PC28/LCDHSYNC/E1_CRSDV/CTS1
PC30/LCDPCK/E1_MDC
SELCONFIG
VDDANA_1
PB1/E0_RX1/CTS2
PB3/E0_RXDV/SPI0_NPCS3
PB5/E0_MDIO/TWCK2
PB7/E0_TXEN/AD8
GNDANA1
PB10/E0_TX1/PCK0/AD11
PB12/E0_TX3/PWM1/AD1
PB14/E0_RX3/PWM3/AD3
PB16/E0_CRS/AD5
GNDANA2
ADVREF
LED0
LED1
LED2
AVDDT
GND_ETH
3
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
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200
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
LCDDAT13
LCDDAT15
LCDDAT16
LCDDAT18
LCDDAT20
LCDDAT23
PC13
PC15
PC16
PC18
PC20
PC23
PC25
PC27
PC28
PC30
2
ETH0_LED0 {10}
ETH0_LED1 {10}
ETH0_LED2 {10}
ETH0_AVDDT {10}
ETH0_GND {10}
E0_TX1
PB10 PCK0
PB12
PB14
PB16 VBUS_SENSE
E1_TXEN
E1_CRSDV
E1_MDC
E1_RXER
E1_TX0
E1_RX0
TK
TD
RK
CANRX1
CANRX0
(MCI0_DA0)
(MCI0_CK)
(MCI0_DA2)
E0_RX1
E0_RXDV
E0_MDIO
E0_TXEN
AD1_XM
AD3_YM
RXD3
CTS3
ISI_VSYNC
ISI_MCK
ISI_D1
ISI_D3
ISI_D5
ISI_D6
ISI_D8
ISI_D10
VDDIOP1
DRXD
TWD0
(MCI1_CDA)
(MCI1_DA2)
1
SIP2
JTAG
ZB_SLPTR
{6,10,11,13}
{6}
{6}
{6}
{6}
{6}
{6}
{4,7}
SPI1_MISO
RXD0
CTS0
NRST
NTRST
TDI
TCK
TMS
TDO
RTCK
PWR_EN
JP9
{14}
{14}
{11,14}
{11,14}
{11,14}
{14}
{14}
{14}
{14}
{14}
{14}
{6}
{6,7}
{8}
{8}
{8}
{6,14}
{6,14}
{6,14}
{8,14}
{5}
{5}
{5}
{5}
{7}
{5,7}
{5}
{12,14}
{12}
3V3
3V3
{8,10}
{14}
{14}
{12}
JP1
1
3
JP2
JP3
1/1
PD14
PD15
PD16
PD17
PD18
PD19
PD20
PD21
PB16
PB17
PB18
5V
PC16
PC17
PC18
PC19
PC20
PC21
PC22
PC23
PC24
PC25
PC26
PC27
PC28
PC29
PC30
PC31
5V
PA16
PA17
PA18
PA19
PA20
PA21
PA22
PA23
PA24
PA25
PA26
PA27
PA28
PA29
PA30
PA31
5V
DES.
DATE
SHEET
3
14
B
1
DATE
XX-XXX-XX
XX-XXX-XX
3V3
3V3
3V3
REV.
VER.
Derek 11-Oct-10 X.X
Derek 10-JUN-10 X.X
J3
HD2X20-HH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3
J2
HD2X20-HH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3
J1
HD2X20-HH
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
MODIF.
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3V3
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3V3
SCALE
REV
B
A
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
PB8
PB9
PB10
PB11
PB12
PB13
PB14
PB15
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PA8
PA9
PA10
PA11
PA12
PA13
PA14
PA15
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
1
3V3
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
SODIMM
AT91SAM9x5-EK
ADVREF {13}
PB10
PB12
PB14
PB16
PC23
{7,14}
PC25
{7}
PC27
{11,14}
PC28
{11,14}
PC30
{11,14}
SELCONFIG {7,11,14}
VDDANA
PB1
{10}
PB3
{10}
PB5
{10}
3V3
PB7
{10}
PC13
PC15
PC16
PC18
PC20
PC1
PC3
PC5
PC6
PC8
PC10
PA6
PA9
PA24
PA26
PA28
PA12
PA14
PA7
PA21
PA23
PA30
PA15
PA17
PA19
PA1
PA3
PD11
PD13
PD15
PD17
PD19
PD21
PD9
PD5
2
JP9 for BMS Config:
When Open,BMS=1: Boot on embeded ROM
When Close,BMS=0: Boot on External memory
VDDIOP0
R83
4.7k
PB1
PB3
PB5
PB7
LCDVSYNC
LCDHSYNC
LCDPCK
LCDDAT1
LCDDAT3
LCDDAT5
LCDDAT6
LCDDAT8
LCDDAT10
SPI1_SPCK
ZB_IRQ0
{4,13}
WAKE UP {13}
SHDN
{4}
VBAT
VDDIOP0
EN5V_HDB#
(MCI0_CD)
VDDNF
PC1
PC3
PC5
PC6
PC8
PC10
PA6
PA9
PA24
PA26
PA28
PA12
PA14
PA7
PA21
PA23
PA30
PA15
PA17
PA19
PA1
PA3
PD11
PD13
PD15
PD17
PD19
PD21
PD1
PD3
PD5
PD7
PD9
BMS
3V3
2
2
2
7
2
A
B
C
D
Figure 3-5.
SODIMM Schematics
5
2
1
C42
470p
PB10
3
2
C61
470p
1
AUDIO_GND
4
STEREO_3.5mm
J15
5
HEADPHONE
3
4
STEREO_3.5mm
J13
AUDIO_GND
5
LINE_IN
{3,10}
R164
L7
220ohm at 100MHz
2
1
4
AUDIO_GND
5.6K
R91
47k
C60
C59
0R
DNP
470p
C44
C121
22p
220uF/10V
220uF/10V
AUDIO_GND
AUDIO_GND
470p
C41
AUDIO_GND
R90
47k
AUDIO_GND
5.6K
R81
R162
R164 near SODIMM
R162 near CODEC
R80
R78
5.6K
L6
220ohm at 100MHz
1
2
C62
470p
AUDIO_GND
C43
470p
L4
220ohm at 100MHz
1
2
22R DNP
L3
R74
220ohm at 100MHz
5.6K
1
2
PCK0
4
+
A
B
C
D
5
3
LHPOUT
9
VDDIOP0
C115
10u
OSC
0R
2
100n
0R
33R
28
AUDIO_GND
C117
100n
VCC_DAC
2
R88
R89
0R
0R
R77
4.7k
100n
10u
10u
100n
10u
RK
TK
TD
TF
RD
RF
PA28
PA24
PA26
PA25
PA27
PA29
AUDIO_GND
AUDIO_GND
R79
4.7k
VDDIOP0
B
A
1/1
DES.
DATE
SHEET
8
14
B
1
DATE
XX-XXX-XX
XX-XXX-XX
REV.
VER.
Derek 11-Oct-10 X.X
Derek 10-JUN-10 X.X
{3,14}
{3,14}
MODIF.
SCALE
REV
{3}
{3}
{3}
{3}
{3}
{3}
PA30
PA31
1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
AUDIO
AT91SAM9x5-EK
100n
10u
100n
DGND
C56
C53
10u
C51
C50
C47
C48
C46
C45
C40
IIS of Audio Interface
in Slave Mode
R86
R87
C54
VCC_DAC
VDDIOP0
TWI_addr
TWD0
TWCK0
3
4
5
6
7
16
8
14
27
1
21
22
23
24
R76
10k
CSB = 1:
addr=0011011
BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
VMID
HPVDD
AVDD
DCVDD
DBVDD
MODE
CSB
SDIN
SCLK
R75
10k
MODE = 0: 2-wire
MPU mode for 9x5
TWI interface
WM8731SEDS
L18
220ohm at 100MHz
1
2
11
HPGND
C116
100n
R165
AUDIO_GND
15
AGND
RHPOUT
MICBIAS
MICIN
10
17
100n 18
C55
RLINEIN
19
1u
C52
LLINEIN
ROUT
20
LOUT
XTO
26
13
XTI/MCLK
25
12
CLKOUT
MN10
Y3
12.288MHz
2
1u
3
C122
22p
C49
1
3
2
4
A
B
C
D
Figure 3-6.
AUDIO Schematic
+
How to Simulate I2S Interface With USART Port On SAM9G15 eMPU [APPLICATION NOTE]
Atmel-11260A-ATARM-How-to-Simulate-I2S-Interface-With-USART-Port-On-SAM9G15-eMPU-ApplicationNote_17-Mar-15
8
9
Atmel-11260A-ATARM-How-to-Simulate-I2S-Interface-With-USART-Port-On-SAM9G15-eMPU-ApplicationNote_17-Mar-15
A
B
C
D
PC24
PC27
PC29
PB11
PB13
PB15
{3,7}
{3,11}
{3,11}
{3}
{3}
{3}
5
{3,6}
PA21
{3,6}
PA23
{3,7,11} SELCONFIG
{3,12}
PD16
PC16
PC18
PC20
PC22
PC1
PC3
PC5
PC7
PC9
PC11
{3,11}
{3,11}
{3,11}
{3,7}
{3}
{3}
{3}
{3}
{3}
{3}
{4}
VDDISI
{3,6} PA7
{3,8} PA31
R147
R146
DNP
0R
0R
0R
0R
R156
R158
R160
R163
R187
0R
0R
0R
22R
22R
22R
R208
R209
R210
R150
R152
R154
22R
22R
22R
22R
PB18
0R
0R
0R
22R
22R
22R
22R
22R
22R
R204
R205
R206
R207
{12} 5V_INTER
R188
R189
R190
R191
R192
R193
ISI only For G25
LCD For G15/G35/X35
5
4
LCDHSYNC
SPI1_MISO
SPI1_SPCK
EN_PWRLCD
AD0_XP
AD2_YP
AD4_LR
LCDDISP
LCDVSYNC
LCDDEN
LCDDAT1
LCDDAT3
LCDDAT5
LCDDAT7
LCDDAT9
LCDDAT11
ZB_IRQ0
TWCK0
3V3
5V_INTER
ISI_D1
ISI_D3
ISI_D5
ISI_D7
ISI_D9
ISI_D11
LCDDAT16
LCDDAT18
LCDDAT20
LCDDAT22
4
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
J22
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
3
ESW-120-33-L-D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
ESW-115-33-L-D
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
J21
3
ISI_MCK
ISI_VSYNC
ISI_HSYNC
ISI_PCK
ISI_D0
ISI_D2
ISI_D4
ISI_D6
ISI_D8
ISI_D10
R157
R159
R161
R170
R151
R153
R155
R215
R216
R217
R211
R212
R213
R214
How to Simulate I2S Interface With USART Port On SAM9G15 eMPU [APPLICATION NOTE]
1/1
MODIF.
SCALE
REV
B
A
0R
0R
0R
0R
0R
0R
0R
22R
22R
22R
22R
22R
22R
22R
R148
R149
R194
R195
R196
R197
R198
R199
R200
R201
R202
R203
{3}
{3}
{3,13}
{3,11}
{3,11}
{3,11}
{3}
{3,11}
{3,11}
{3,7}
PA22
{3,6}
PA0
{3,6,7}
LCD_DETECT# {12}
PD17
{3,12}
PB12
PB14
PB18
PC26
PC28
PC30
PC17
PC19
PC21
PC23
2
PA13
PA30
PC15
PC13
PC14
PC12
PC0
PC2
PC4
PC6
PC8
PC10
DES.
DATE
1
14
14
B
DATE
SHEET
REV.
VER.
A
B
C
{3,5,6} D
{3,8}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
{3}
Derek 11-Oct-10 X.X XX-XXX-XX
Derek 10-JUN-10 X.X XX-XXX-XX
0R
0R
22R
22R
22R
22R
22R
22R
22R
22R
22R
22R
1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
LCD & ISI
AT91SAM9x5-EK
SPI1_MOSI
SPI1_NPCS1
AD1_XM
AD3_YM
ONE_WIRE
LCDPCK
LCDHSYNC
LCDPWM
LCDDAT17
LCDDAT19
LCDDAT21
LCDDAT23
LCD/TSC
ZB_IRQ1
TWD0
LCDDAT15
LCDDAT13
LCDDAT14
LCDDAT12
LCDDAT0
LCDDAT2
LCDDAT4
LCDDAT6
LCDDAT8
LCDDAT10
LCD&ISI
2
Figure 3-7.
LCD&ISI Schematic
PC30
PC31
PC26
{3,14}
{3}
{3,14}
A
B
PC21
PC20
PC28
PC16
{3,7,14} SELCONFIG
PC29
PC19
PC18
PC27
C
{3,14}
{3,14}
{3,14}
{3,14}
{3,14}
{3,14}
{3,14}
{3,14}
1
2
3
4
1
2
3
4
E1_TXCK
5
22R
RR12
22R
RR10
8
7
6
5
8
7
6
5
E1_INTR
E1_RXER
E1_CRSDV
E1_RX0
E1_RX1
SELCONFIG
8
7
6
5
74AC244SC
1 OE1
2 I0
3 O4
4 I1
5 O5
6 I2
7 O6
8 I3
9 O7
10
GND
MN17
VCC
OE2
O0
I4
O1
I5
O2
I6
O3
I7
E1_INTR
SELCONFIG
E1_TXCK
E1_MDC
E1_MDIO
E1_INTR
20
19
18
17
16
15
14
13
12
11
VDDIOP1
E1_TXCK
E1_TX1
E1_TX0
E1_TXEN
C114 100n
VDDIOP1
E1_RXER
SELCONFIG
RR14
10k
4
{3,6,10,13} NRST
RR13
10k
RR15
10k
0R
JP13
VDDIOP1
R133
0R
VDD 4
10k
47k
R134
100n
C98
C99
100n
100n
C97
1.5k
R125
3
BGRESG
AGND
AGND
AGND
AVDDT
AVDDR
AVDDR
RX-
RX+
TX-
TX+
XT1
C100
10u
10V
R136
VDDIOP1
N.C
BGRES
LEDMODE
LED0/OP0
LED1/OP1
LED2/OP2
CABLESTS/LINKSTS
DM9161AEP
L20
220ohm at 100MHz
1
2
RESET
PWRDWN
DGND
DGND
DGND
DVDD
DVDD
DVDD
DISMDIX
MDC
MDIO
MDINTR
COL/RMII
CRS/PHYAD4
TX_ER/TXD4
RX_ER/RXD4/RPTR
RX_CLK/10BTSER
RX_DV/TESTMODE
RXD3/PHYAD3
RXD2/PHYAD2
RXD1/PHYAD1
RXD0/PHYAD0
TXD3
TXD2
TXD1
TXD0
TX_EN
TX_CLK/ISOLATE
C88
100n
VDDIOP1
REF_CLK/XT2
EARTH_ETH1
40
10
15
33
44
23
30
41
VDDIOP1
39
24
25
32
36
35
16
38
34
37
26
27
28
29
17
18
19
20
21
0R DNP 22
42
0R
3
MN13
50MHz
2 VSS
OUT 3
Y2
1 OE
R120
R122
VDDIOP1 R128
E1_CRSDV
E1_RX1
E1_RX0
R121
8
7
6
5
1
2
3
4
22R
RR11
8
7
6
5
1
2
3
4
1
2
3
4
8
7
6
5
1
2
3
4
D
2
1
4
C92
2
100n
100n
0R
45
48
31
11
12
13
14
47
5
6
46
GND_ETH1
R130
6.8k
R129 0R
E1_AVDDT
9
C95 100n
C90
1
4
3
8
7
43
2200R
C93
10u
10V
1
L11
2
2
2
R169
11
1/1
MODIF.
SCALE
REV
B
A
470R
VDDIOP1
Right LED
Left LED
1nF
75
R132
R131
75
75
3
6
RX+
RX-
DES.
DATE
B
1
DATE
SHEET
11
14
REV.
VER.
VDDIOP1
XX-XXX-XX
XX-XXX-XX
470R
470R
8
7
5
4
2
TX-
Derek 11-Oct-10 X.X
Derek 10-JUN-10 X.X
75
1
TX+
EARTH_ETH1
This agreement is our property. Reproduction and publication without our written authorization shall expose offender to legal proceedings.
ETH1
5
4
8 RD-
6 CT
7 RD+
2 TD-
3 CT
10
AT91SAM9x5-EK
1 Red
EARTH_ETH1
FULL DUPLEX2 D8
RR16
10k
C91
100n
J18
J0026D21B
RJ45 ETHERNET CONNECTOR
1 TD+
GND_ETH1
GND_ETH1
R127
49.9R
VDDIOP1GND_ETH1
C96
100n
E1_AVDDT
R126
49.9R
C94
10u
10V
R124
49.9R
E1_AVDDT
R123
49.9R
C89
100n
ETH1
(Only For X25)
1
16
9
5
8
7
6
5
1
2
3
4
15
12
A
B
C
D
Figure 3-8.
ETH Schematic
How to Simulate I2S Interface With USART Port On SAM9G15 eMPU [APPLICATION NOTE]
Atmel-11260A-ATARM-How-to-Simulate-I2S-Interface-With-USART-Port-On-SAM9G15-eMPU-ApplicationNote_17-Mar-15
10
3.7
Software Implementation
The software demo provided for this application includes the contents listed in Table 3-1.
Table 3-1.
3.8
Contents of Provided Software Demo
Directory
Description
libraries
Includes the library files to support the SAM9G15 chip, EK and other peripherals such as USB,
storage. Users can simply call the functions in the libraries.
usart_i2s_dma_audio
Includes the application IAR project
Readme.txt
A brief introduction document to tell users how to make the code run on SAM9G15-EK
Code Overview
Users can use commands through the debug interface to start and stop playing or recording the audio, download
the PCM data into the memory of SAM9G15 by Xmodem of HyperTerminal. Figure 3-9 is the overview for the
functions of this demo.
Figure 3-9.
Function Flow Chart
System
Initialization
Timer Counter
Initializtion
Codec
Initialization
Wait for Command
Command
Check
Stop playback
11
USART
Initialization
Send the Audio to
Memory from Xmoderm
USART
Initialization
Timer Counter
Initialization
Timer Counter
Initialization
DMA
Configuration
DMA
Configuration
Play the PCM data
in Memory
Record the PCM
from Line-in
Stop Recording
How to Simulate I2S Interface With USART Port On SAM9G15 eMPU [APPLICATION NOTE]
Atmel-11260A-ATARM-How-to-Simulate-I2S-Interface-With-USART-Port-On-SAM9G15-eMPU-ApplicationNote_17-Mar-15
3.8.1
System Initialization
In this part, it is necessary to disable the system watchdog, configure the system clock, and configure the GPIO for
the corresponding peripherals such as pins of USART2, TIOA0, TIOA1, etc.
Here is the code for reference:
/* Disable watchdog */
WDT_Disable( WDT ) ;
/* System tick configuration */
_ConfigureTick(BOARD_MCK);
/* Configure all pins used for this application */
PIO_Configure(pins, PIO_LISTSIZE(pins));
As for the pins structure, it includes all the PIOs used in this demo:
/** List of pins to configure. */
static const Pin pins[] = {
PIN_GPIO_PA26,
//used as
PIN_GPIO_PB7,
//used as
GPIO
GPIO
PINS_TWI0,
PIN_TC0_TIOA0,
PIN_TC0_TIOA1,
PIN_USART2_RXD,
PIN_USART2_TXD,
PIN_USART2_SCK,
PIN_USART2_CTS,
PIN_PCK0
};
How to Simulate I2S Interface With USART Port On SAM9G15 eMPU [APPLICATION NOTE]
Atmel-11260A-ATARM-How-to-Simulate-I2S-Interface-With-USART-Port-On-SAM9G15-eMPU-ApplicationNote_17-Mar-15
12
3.8.2
Timer Counter Initialization
In this part, mainly set the clock source and working mode for the two TC channels according to the default
frequency firstly. And also need to define the start level status for the two waveform outputs.
/* Initialize TC, to make sure TC0 Ch0 TIOA output initial status is high level,
so pls make sure this initialization done before any other action */
_TcWaveformInitialize(wavFrequency,wavBitsPerSample);
/* Start the TC once, to make sure the initial output level of TIOA0&TIOA1 are
high when next time TC starts */
_TcClkEnable();
_TcClkDisable();
In function _TcWaveformInitialize(), there are two functions to set each TC channel in detailed.
static void TcCh0WaveformConfigure(uint32_t frequency)
{
const uint32_t divisors[5] = {2, 8, 32, 128, BOARD_MCK / 32768};
uint32_t ra, rc;
/* Set channel 0 as waveform mode */
REG_TC0_CMR0 =
waveformConfigurations[configuration].clockSelection
/* Waveform Clock Selection */
| TC_CMR_WAVE /* Waveform mode is enabled */
| TC_CMR_ACPA_CLEAR /* RA Compare Effect: Clear */
| TC_CMR_ACPC_SET /* RC Compare Effect: Set */
| TC_CMR_WAVSEL_UP_RC /* UP mode with automatic trigger on
RC Compare */
| TC_CMR_ASWTRG_SET; /* Soft
trigger effect on TIOA: Set */
/* Configure the BCLK frequency based on the wav file's sample
frequency */
if (frequency == 8000)
configuration = 0;
else if (frequency == 32000)
configuration = 1;
else if (frequency == 44100)
configuration = 2;
else if (frequency == 48000)
configuration = 3;
else
{
printf("This frequency: %d is not supported
\r\n", frequency);
return;
}
/* Set the RA and RC compare register value */
rc = (BOARD_MCK /
divisors[waveformConfigurations[configuration].clockSelection]) /
waveformConfigurations[configuration].frequency;
REG_TC0_RC0 = rc;
ra = (100 - waveformConfigurations[configuration].dutyCycle) * rc / 100;
REG_TC0_RA0 = ra;
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}
/**
* \brief Configure clock, frequency and duty cycle for TC0 channel 1 in
waveform mode.
*/
static void TcCh1WaveformConfigure(uint8_t DatLen)
{
uint32_t ra, rc;
/* Set channel 1's clock source as TIOA0 */
REG_TC0_BMR = TC_BMR_TC1XC1S_TIOA0;
/* Set channel 1 as waveform mode */
REG_TC0_CMR1 = TC_CMR_TCCLKS_XC1 /* Waveform Clock Selection */
| TC_CMR_CLKI /*counter is
increamented on falling edge of the clock */
| TC_CMR_WAVE /* Waveform mode is enabled */
| TC_CMR_ACPA_CLEAR /* RA Compare Effect: clear */
| TC_CMR_ACPC_SET /* RC Compare Effect: set */
| TC_CMR_WAVSEL_UP_RC /* UP mode with automatic trigger on RC
Compare */
| TC_CMR_ASWTRG_SET; /* Soft
trigger effect on TIOA: Set */
ra = DatLen;
REG_TC0_RA1 = ra;
rc = DatLen*2;
REG_TC0_RC1 = rc;
}
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3.8.3
Codec Initialization
In this part, SAM9G15 will configure the WM8731 with the I2C interface to set the headphone output volume, PCM
data format, and configure the sampling frequency, etc.
/**
* Initialize PCK & WM8731 for Audio
* 12MHz PCK
*/
static void _ConfigureAudio(uint32_t sampleRate, uint8_t sampleBit)
{
/* -- WM8731 Initialize -- */
/* Enable TWI peripheral clock */
PMC_EnablePeripheral(ID_TWI0);
/* Configure and enable the TWI (required for accessing the DAC) */
TWI_ConfigureMaster(TWI0, TWI_CLOCK, BOARD_MCK);
TWID_Initialize(&twid, TWI0);
/* WM8731 as slave */
printf("Initialize WM8731 in Slave mode\r\n");
/* If not use OSC on Codec, use 12M PCK, we select this mode in this
demo */
/* USB mode, can support 8k/32k/44.1k/48k */
WM8731_Init_1(&twid, WM8731_SLAVE_ADDRESS, 1, 0,
0,sampleRate,sampleBit);
/* Enable the DAC master clock (Uses 12M, USB mode) */
REG_PMC_PCK = PMC_MCKR_CSS_MAIN_CLK | PMC_MCKR_PRES_CLOCK;
/* Programmable Clock 0 Output Enable */
REG_PMC_SCER = PMC_SCER_PCK0;
/* Wait for the PCKRDYx bit to be set in the PMC_SR register */
while ((REG_PMC_SR & PMC_SR_PCKRDY0) == 0);
/* -- Load WAV file information if wav file is available -- */
CheckWavFile();
}
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3.8.4
USART Initialization
In this part, it is necessary to configure the USART to work in SPI slave mode, set the transferred data length to 8bit per each transfer with MSB firstly, and sample the data in the rising edge of the clock, etc.
Please refer to the following code for detailed settings.
/**
* \brief Configure USART2 in SPI slave mode.
*/
static void _ConfigureUsart( void )
{
uint32_t mode = US_MR_USART_MODE_SPI_SLAVE /* USART works as SPI Slave mode
*/
| US_MR_CHRL_8_BIT
/*Transmit data length is 8-bit*/
| US_MR_CHMODE_NORMAL
| US_SPI_BPMODE_3;
/* Enable the peripheral clock for USART2 in the PMC */
PMC_EnablePeripheral( ID_USART2 );
/* Configure the USART in the desired mode @USART_SPI_CLK bauds */
USART_Configure( USART2, mode, USART_SPI_CLK, BOARD_MCK );
}
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3.8.5
DMA Configuration
In this part, it is necessary to create the DMA channels and set callback function for both USART transmitting and
receiving.
/**
* \brief DMA driver configuration.
*/
static void _ConfigureDma(void)
{
uint32_t dwCfg;
uint8_t iController;
/* Driver initialize */
DMAD_Initialize( &dmad, 0);
/* IRQ configure */
IRQ_ConfigureIT(ID_DMAC0, 0, DMA_IrqHandler);
IRQ_ConfigureIT(ID_DMAC1, 0, DMA_IrqHandler);
IRQ_EnableIT(ID_DMAC0);
IRQ_EnableIT(ID_DMAC1);
/* Allocate DMA channels for USART2 */
usart2DmaTxChannel = DMAD_AllocateChannel( &dmad,
DMAD_TRANSFER_MEMORY, ID_USART2);
usart2DmaRxChannel = DMAD_AllocateChannel( &dmad,
ID_USART2, DMAD_TRANSFER_MEMORY);
if (
usart2DmaTxChannel == DMAD_ALLOC_FAILED
|| usart2DmaRxChannel == DMAD_ALLOC_FAILED )
{
printf("DMA channel allocate error\n\r");
while(1);
}
/* Set RX callback */
DMAD_SetCallback(&dmad, usart2DmaRxChannel,
(DmadTransferCallback)_DmaRxCallback, 0);
/* Set TX callback */
DMAD_SetCallback(&dmad, usart2DmaTxChannel,
(DmadTransferCallback)_DmaTxCallback, 0);
/* Configure DMA RX channel */
iController = (usart2DmaRxChannel >> 8);
dwCfg = 0
| DMAC_CFG_SRC_PER(
DMAIF_Get_ChannelNumber( iController,
ID_USART2, DMAD_TRANSFER_RX ))
| DMAC_CFG_SRC_H2SEL
| DMAC_CFG_SOD
| DMAC_CFG_FIFOCFG_ALAP_CFG;
DMAD_PrepareChannel( &dmad, usart2DmaRxChannel, dwCfg );
printf("USART2 DMA RX channel number:
%d\r\n",DMAIF_Get_ChannelNumber( iController, ID_USART2, DMAD_TRANSFER_RX ));
/* Configure DMA TX channel */
iController = (usart2DmaTxChannel >> 8);
dwCfg = 0
| DMAC_CFG_DST_PER(
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DMAIF_Get_ChannelNumber( iController,
ID_USART2, DMAD_TRANSFER_TX ))
| DMAC_CFG_DST_H2SEL
| DMAC_CFG_SOD
| DMAC_CFG_FIFOCFG_ALAP_CFG;
DMAD_PrepareChannel( &dmad, usart2DmaTxChannel, dwCfg );
printf("USART2 DMA TX channel number:
%d\r\n",DMAIF_Get_ChannelNumber( iController, ID_USART2, DMAD_TRANSFER_TX ));
}
3.8.6
Audio PCM Data Playback
In this part, SAM9G15 will send the PCM data in its memory to the codec with the USART port. Before sending the
data to codec, the system must perform two actions:
ensure that each PCM sample stored in the memory can be sent to the codec with the MSB first order
configure the LLI DMA pointer for each DMA transfer buffer:
The 16-bit PCM data from WAV file is stored in the memory as described below.
The following is the storage order in PCM files:
Sample 0
High Byte 0, Low Byte 0
Sample 1
High Byte 1, Low Byte 1
...
...
Sample n
High Byte n, Low Byte n
When the PCM files are sent to SAM9G15’s memory, they will be stored in the order shown in Figure 3-10.
Figure 3-10.
DMA Data Storage
Buffer in Memory
High Address
Sample n MSB
Buffer in RAM
Sample n LSB
Sample n-1 MSB
Sample n-1 LSB
… ...
Sample 1 MSB
Sample 1 LSB
Sample 0 MSB
Sample 0 LSB
… ...
Low Address
For the USART DMA transfer, each time it will send one byte because the maximum data length for transfer is 8bit. So every time when transferring one sample (e.g., 16-bit), DMA will transfer the bytes stored in the lower
address firstly, and then the bytes stored in the higher address. To make sure the 16-bit sample can be transferred
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18
with MSB firstly, we need to convert the Low bytes and High bytes of each sample before starting the DMA
transfer. For the 24-bit or 32-bit sample, the data also need to be converted with the same rule.
Note:
For the PCM data recorded in the memory, there is no need to do the inversion because the recorded data
received from USART is directly from codec and it can be sent back to the codec without data processing.
After having ensured that each PCM sample stored in the memory can be sent to the codec with the MSB first
order and after having configured the LLI DMA pointer for each DMA transfer buffer, the system can start the DMA
transfer by enabling the TC clock generation and the recorded data becomes audible from the headphone.
The following is the detailed code for reference:
/**
* \brief Play a WAV file pre-loaded in DDRAM.
*/
static void PlayWav(uint32_t wavDataAddress, uint32_t wavSize)
{
uint32_t size;
uint32_t src;
int i;
remainingBytes = wavSize;
transmittedBytes = 0;
/* For the wav file, the sample storage is like: */
/*Sample 0
- Sample 1
- Sample
n */
/*High Byte0, Low Byte0 - High Byte1, Low Byte1 - High Byten, Low Byten
*/
/ *For SAM9G15 DMA transmission, it sends the bytes with lower address
firstly. But for I2S, MSB should be transmitted firstly. */
/* So before starting the DMA transmission, need to reverse the high and
low bytes of the samples in the source file to adapt the DMA transmission order.
*/
/* For the recorded PCM data in the flash, there is no need to do the data
reversion. */
/* Here only provide the data conversion sample for 16-bit data, users
can add their own data processing code here. */
if (userWav->bitsPerSample == 16)
{
//change the wav file contents value
uint16_t *pWords = (uint16_t*)(wavDataAddress);
uint16_t tmp1, tmp2;
/* Audio Data Processing: only for 16-bit sample now */
/* Convert the high and low bytes of one sample, because DMA
transfers the lower bytes firstly and WM7831 requires MSB first. */
if (DatConverted ==0)
{
for (i =0; i<(wavSize/2);i++ )
{
tmp1 = pWords[i]&0x00ff;
tmp2 = pWords[i]&0xff00;
pWords[i] = (tmp1<<8)|(tmp2>>8);
//printf("2. pWords[%d] = %x\r\n", i, pWords[i]);
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}
DatConverted = 1;
}
}
/* Set the DMA LLI to transmit the audio data */
src = wavDataAddress+ transmittedBytes;
TX_LLI_NO = 0;
for ( i = 0; (i<MAX_LLI_SIZE&& remainingBytes>0); i++)
{
size = min(remainingBytes, 65535);
txLLI[i].dwSrcAddr = (uint32_t)src;
txLLI[i].dwDstAddr = (uint32_t)(&USART2->US_THR);
txLLI[i].dwCtrlA = DMAC_CTRLA_BTSIZE(size)
|DMAC_CTRLA_SRC_WIDTH_BYTE |
DMAC_CTRLA_DST_WIDTH_BYTE;
txLLI[i].dwCtrlB = DMAC_CTRLB_FC_MEM2PER_DMA_FC
| DMAC_CTRLB_SRC_INCR_INCREMENTING
| DMAC_CTRLB_DST_INCR_FIXED;
txLLI[i].dwDscAddr =((uint32_t)&txLLI[ i + 1 ].dwSrcAddr);
src += size;
remainingBytes -=size;
transmittedBytes +=size;
TX_LLI_NO++;
//printf("i = %d\r\n",i);
}
txLLI[i-1].dwDscAddr = 0;
/*Start DMA transmit*/
isWavPlaying = 1;
DMAD_PrepareMultiTransfer(&dmad, usart2DmaTxChannel, &txLLI[0]);
DMAD_StartTransfer(&dmad, usart2DmaTxChannel);
USART_SetTransmitterEnabled(USART2, 1 ) ;
Wait (100);
_TcClkEnable();
}
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3.8.7
Record PCM Data from Line-in
In this function, we need to set the LLI DMA pointers for the receive buffer and then we can start the recording by
enabling the DMA transfer and TC clock generation.
/* Record the audio from Line-in input */
static void RecordWav(uint32_t recordDataAddr)
{
uint32_t src;
uint32_t size;
uint8_t i;
ReceivedBytes = 0;
/* Use LLI to transmit data with DMA */
src = recordDataAddr+ ReceivedBytes;
RX_LLI_NO = 0;
for ( i = 0; (i<MAX_LLI_SIZE&& ReceivedBytes<MAX_RECORD_SIZE); i++)
{
size = 65535;
rxLLI[i].dwSrcAddr = (uint32_t)(&USART2->US_RHR);
rxLLI[i].dwDstAddr = (uint32_t)src;
rxLLI[i].dwCtrlA = DMAC_CTRLA_BTSIZE(size)
| DMAC_CTRLA_SRC_WIDTH_BYTE
| DMAC_CTRLA_DST_WIDTH_BYTE;
rxLLI[i].dwCtrlB = DMAC_CTRLB_FC_PER2MEM_DMA_FC
| DMAC_CTRLB_SRC_INCR_FIXED
| DMAC_CTRLB_DST_INCR_INCREMENTING;
rxLLI[i].dwDscAddr =((uint32_t)&rxLLI[ i + 1 ].dwSrcAddr);
src += size;
ReceivedBytes +=size;
RX_LLI_NO++;
}
rxLLI[i-1].dwDscAddr = 0;
/* Start DMA Receive */
isRecording = 1;
DMAD_PrepareMultiTransfer(&dmad, usart2DmaRxChannel, &rxLLI[0]);
DMAD_StartTransfer(&dmad, usart2DmaRxChannel);
USART_SetReceiverEnabled(USART2, 1 );
Wait (100);
_TcClkEnable();
}
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3.8.8
Callback Function for DMA
The callback function is used to handle condition checking when the DMA interrupt happens. Normally we will
check if the LLI buffer reaches the end or if the PCM data in the memory is finished.
/**
* \brief DMA TX callback.
*/
static void _DmaTxCallback(uint8_t status, void* pArg)
{
pArg = pArg;
//printf("Call back \r\n");
if (status >= DMAD_ERROR)
{
isWavPlaying = 0;
isWavPlaying = 0;
return;
}
INT_NO++;
/* Check if read the last LLI, if yes, stop the playing */
if (INT_NO == TX_LLI_NO)
{
isWavPlaying = 0;
INT_NO = 0;
/* Disable USART2 SPI transmitting */
USART_SetTransmitterEnabled( USART2, 0 ) ;
/*Stop DMA*/
DMAD_StopTransfer(&dmad, usart2DmaTxChannel);
/* Stop BCLK and LRCLK */
_TcClkDisable();
DisplayMenu();
}
}
/**
* \brief DMA RX callback.
*/
static void _DmaRxCallback(uint8_t status, void* pArg)
{
pArg = pArg;
if (status >= DMAD_ERROR)
{
isRecording= 0;
return;
}
INT_NO++;
/* Check if read the last LLI, if yes, stop the recording */
if (INT_NO == RX_LLI_NO)
{
isRecording = 0;
INT_NO = 0;
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/* Disable USART2 SPI receiving */
USART_SetReceiverEnabled( USART2, 0 );
/*Stop DMA*/
DMAD_StopTransfer(&dmad, usart2DmaRxChannel);
/*Stop BCLK and LRCLK*/
_TcClkDisable();
DisplayMenu();
}
}
3.8.9
Stop Playback or Recording
Users can stop audio playing or recording by inputting commands from the Debug window.
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4.
Conclusion
With this application demo, users can add one more audio interface in their application if more than one I2S
interface is required. Although in this application we only provide the Left-justified mode demo code, users can
very easily modify the code to generate the waveform they want to keep compliant with I2S or Right-justified mode.
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5.
Revision History
Table 5-1.
Revision History
Document Rev.
11260A
17-Mar-15
25
Changes
First issue.
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