Application Note Migrating from SAM9x5-based to SAMA5D3x-based Applications ARM-based Embedded MPU Scope The Atmel® SAMA5D3x series is a high-performance, power-efficient, embedded MPU based on the ARM® Cortex®-A5 core, offering the best balance between performance and power consumption. Compared to the SAM9x5 series, SAMA5D3x features higher CPU performance and lower power consumption. Thus, in some applications, users might consider upgrading the microcontroller from SAM9x5 to SAMA5D3x. This application note provides a reference solution to the migration (hardware and software) from SAM9x5-based applications to SAMA5D3x-based applications. The hardware migration focuses on signal names and the software migration focuses on the libraries in the software package. 11214A–ATARM–11-Oct-13 1. Reference Documents Table 1-1. Reference Documents Type Name SAMA5D3 Series Datasheet SAM9G15 Datasheet Datasheet SAM9G25 Datasheet SAM9G35 Datasheet SAM9X25 Datasheet SAM9X35 Datasheet SAMA5D3x Microcontroller Schematic Check List SAM9G15 Microcontroller Schematic Check List Application Note SAM9G25 Microcontroller Schematic Check List SAM9G35 Microcontroller Schematic Check List SAM9X25 Microcontroller Schematic Check List SAM9X35 Microcontroller Schematic Check List User Guide Software Pack 2. SAMA5D3x-EK User Guide SAM9G15/G25/G35/X25/X35-EK User Guide SAMA5D3x Softpack SAM9x5 Softpack Hardware Migration The SAMA5D3x and SAM9x5 are neither package nor pin-compatible. A new board layout is required for the applications being moved from SAM9x5 to SAMA5D3x to accommodate the changes in pinout and package. This section introduces the hardware migration based on functionalities. Certain SAMA5D3x signal names and functionalities are identical or similar to those of SAM9x5, which simplifies migrating from SAM9x5 to SAMA5D3x. For the signals and functionalities that are different between the two devices, some adjustments are necessary for the migration. The following sections give a brief description of the required adjustments. For details, please refer to the “Signal Description” section in the SAMA5D3 Series Datasheet and to the schematics in the SAMA5D3x-EK User Guide. Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 2 2.1 Power Supplies The following table describes the differences between the SAMA5D3x and SAM9x5 power supplies. Table 2-1. Power Supplies Differences SAM9x5 Power Supply Domain Range (V) VDDCORE 0.9–1.1 VDDNF 1.65–1.95 or 3.0–3.6 VDDIODDR — VDDUTMIC Power SAMA5D3x Range (V) Power Core, including processor, embedded memories, and peripherals 1.1–1.32 Core, including processor, embedded memories, and peripherals NAND Flash I/Os 1.65–1.95 or 3.0–3.6 Replaced by VDDIOM — 1.7–1.9 or 1.14–1.30 DDR2/LPDDR Interface I/O lines 0.9–1.1 USB device and host UTMI+ core 1.1–1.32 USB device and host UTMI+ core VDDPLLA 0.9–1.1 PLLA cell 1.1–1.32 PLLA cell VDDFUSE — — 2.25–2.75 Fusebox for programming (can be tied to ground with a 100 Ω resistor for fuse reading only) LPDDR2 Interface I/O lines During migration, note that: Power supply range required for VDDCORE, VDDUTMIC and VDDPLLA is changed from 0.9–1.1 V to 1.1–1.32 V, requiring this power supply rail to be altered from 1 V to 1.2 V. SAMA5D3x does not have the VDDNF power supply rail. For the NAND Flash I/Os power supply, replace SAM9x5 VDDNF with SAMA5D3x VDDIOM. SAMA5D3x has an extra VDDIODDR power supply rail dedicated for DDR2/LPDDR/LPDDR2, with the range from 1.7 V to 1.9 V or from 1.14 V to 1.30 V (depending on interfacing DDR2/LPDDR or LPDDR2). So for power supply for DDR2/LPDDR/LPDDR2, replace SAM9x5 VDDIOM with SAMA5D3x VDDIODDR. The board design must comply with the power-up and power-down sequence guidelines to guarantee reliable operation of the device. Both the SAMA5D3x and SAM9x5 have the same power-up and power-down sequences: 2.2 Power-up sequence — Establish VDDIOP and VDDIOM first, then VDDPLL, and VDDCORE last, to ensure reliable operation of the device. Power-down sequence — Remove VDDCORE first, then VDDPLL, and VDDIOP and VDDIOM last, to ensure reliable operation of the device. The SAMA5D3x introduces a new power supply VDDFUSE which is used to write the fuses. If the fuses do not need to be written (i.e., read only or simply not used) VDDFUSE can be tied to ground with a 100 Ω resistor. Clock and Crystal In addition to PCK0 and PCK1, SAMA5D3x provides an extra Programmable Clock Output (PCK2). Electrical characteristics of the crystal oscillator are not the same on the SAMA5D3x. This means crystal characteristics must be checked carefully to ensure correct device functionality. Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 3 2.3 ICE/JTAG SAMA5D3x provides a 2-pin debug port Serial Wire Debug (SWD), with two signals SWDIO and SWCLK overlaid on the TMS and TCK pins. SWD provides the same functionalities as the standard JTAG debug method. Table 2-2. ICE/JTAG Signal Differences SAM9x5 SAMA5D3x Function Signal Name Signal Name Function Test Clock TCK TCK/SWCLK Test Clock/Serial Wire Clock Test Mode Select TMS TMS/SWDIO Test Mode Select/Serial Wire Input/Output 2.4 Memories 2.4.1 SMC The SMC in SAMA5D3x has four chip selects (NCS0–NCS3) and a 16-bit data bus (D0–D15), different from the six chip selects and the 32-bit data bus in SAM9x5 SMC. Accordingly, SMC only provides two write signals (NWR0–NWR1) and two selection signals (NBS0–NBS1) for 16-bit devices. Table 2-3. SMC Signal Differences SAM9x5 2.4.2 SAMA5D3x Function Signal Name Signal Name Function Data Bus D0–D31 D0–D15 Data Bus Chip Select Lines NCS0–NCS5 NCS0–NCS3 Chip Select Lines Write Signal NWR0–NWR3 NWR0–NWR1 Write Signal Byte Mask Signal NBS0–NBS3 NBS0–NBS1 Byte Mask Signal DDR2 Controller The Multiport DDR Controller (MPDDRC) in SAMA5D3x has its own dedicated DDR2 pins for interfacing DDR-SDRAM devices, different from the EBI pins in SAM9x5, which are multiplexed with the PIO lines. SAMA5D3x provides the interface to external 16-bit or 32-bit DDR-SDRAM devices, including LPDDR2. SAMA5D3x supports 4-bank and 8-bank DDR memories, whereas the SAM9x5 supports only 4-bank DDR memories. Only 32-bit accesses are possible on the SAMA5D3x, e.g., 1 x 32-bit, 2 x 16-bit, or 4 x 8-bit DDR memories (1 x 16-bit memory access is not possible). Table 2-4. DDRC Feature Differences Feature SAM9x5 SAMA5D3x DDR Bit Width 16 bits 32 bits Supported Memory SDR/DDR2/LPDDR DDR2/LPDDR/LPDDR2 Supported DDR Memory 4-bank 4-bank / 8-bank DDR Memory Access 1 x 16-bit / 2 x 8-bit 1 x 32-bit / 2 x 16-bit / 4 x 8-bit Auto Adaptive Pads — DDR_CALP, DDR_CALN For the DDR-SDRAM devices interfacing differences between SAMA5D3x and SAM9x5, please refer to the application note SAMA5D3x Microcontroller Schematic Check List and the applicable SAM9x5 series Microcontroller Schematic Check List application notes (see Table 1-1 on page 2). Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 4 Note: Table 2-5. In SAMA5D3x, serial resistors are not needed on DDR2 I/O lines due to the auto adaptive pads (auto adaptive pads are not present on SAM9x5). DDRC Signal Differences SAM9x5 DDR2/SDRAM Function SAMA5D3x DDR2 Signal Name — — Signal Name Positive Calibration Reference (1) Negative Calibration Reference DDR_CALP — — DDR_CALN — — DDR_VREF SDCK, DDR_CK, #SDCK DDR_CKN SDCKE DDR_CKE SDCS DDR_CS Bank Select BA[0..2] DDR_BA[2..0] DDR2/SDRAM Write Enable SDWE DDR_WE DDR2/SDRAM Differential Clock DDR2/SDRAM Clock Enable DDR2/SDRAM Controller Chip Select Row and Column Signal Address Bus Data Bus RAS-CAS DDR_RAS, DDR_CAS Note: DDR2 differential clock DDR2 Clock Enable DDR2 Controller Chip Select Bank Select DDR2 Write Enable Row and Column Signal DDR_A[13..0] DDR2 Address Bus D0–D15 D16–D31 (SDRAM) DDR_D[31..0] DDR2 Data Bus DQS[0..1] Write Data Mask Reference Voltage EBI_A[11..2], EBI_SDA10, EBI_A[15..13] DQS[3..0] Data Strobe Function (1) DQM[0..1] DQM[2..3] (SDRAM) DQSN[3..0](2) DQM[3..0] Differential Data Strobe DQSN must be connected to DDR_VREF for DDR2 memories Write Data Mask 1. Connect DDR_CALP to GND via 200 Ω (DDR2/LPDDR mode) / 240 Ω (LPDDR2 mode) resistor. Connect DDR_CALN to VDDIODDR via 200 Ω (DDR2/LPDDR mode) / 240 Ω (LPDDR2 mode) resistor. 2. DQSN are connected to LPDDR2 memory in LPDDR2 mode. In DDR2/LPDDR mode, connect the DQSN to DDR_VREF. 2.5 Peripherals 2.5.1 LCD and ISI In SAM9x5 series, the ISI is available only in SAM9G25, and the LCDC is available only in SAM9G15/G35/X35. The ISI signals in SAM9G25 and the LCDC signals in SAM9G15/G35/X35 are multiplexed with the same PIO lines. In SAMA5D3x, both ISI and LCDC are available, with the signals also multiplexed with PIO lines. During migration, note the configuration of the related multiplexed PIO lines to avoid pin conflicts. The LCDC in SAMA5D3x and SAM9G15/G35/X35 both support Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion. Compared with SAM9G15/G35/X35, the LCDC in SAMA5D3x has an additional Overlay Layer (OVR2) as well as an additional Post Processing Controller, and the display resolution is upgraded from 800 x 600 to 1280 x 720. Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 5 2.5.2 UHPHS, UDPHS SAMA5D3x USB differs from SAM9x5 USB in Port C, which is HS Host in SAMA5D3x, while FS Host in SAM9x5. The signals are HHSDPC and HHSDMC. For Port A (HS Host/Device), Port B (HS Host) and Port C (HS Host), the FS and HS signals share the same pins on the SAMA5D3x, such as HHSDM/HFSDM, HHSDP/HFSDP, DHSDM/DFSDM, DHSDP/DFSDP, which simplifies the USB connection. Table 2-6. USB Signal Differences SAM9x5 Function SAMA5D3x Signal Name Signal Name Function USB Host High Speed Port - UHPHS USB Host Port A High Speed Data + HHSDPA USB Host Port A Full Speed Data + HFSDPA USB Host Port A High Speed Data - HHSDMA USB Host Port A Full Speed Data - HFSDMA USB Host Port B High Speed Data + HHSDPB USB Host Port B Full Speed Data + HFSDPB USB Host Port B High Speed Data - HHSDMB USB Host Port B Full Speed Data - HFSDMB USB Host Port C Full Speed Data + USB Host Port C Full Speed Data - HHSDPA USB Host Port A High Speed Data + HHSDMA USB Host Port A High Speed Data - HHSDPB USB Host Port B High Speed Data + HHSDMB USB Host Port B High Speed Data - HFSDPC HHSDPC USB Host Port C High Speed Data + HFSDMC HHSDMC USB Host Port C High Speed Data - USB Device High Speed Port - UDPHS 2.5.3 USB Device High Speed Data + DHSDP USB Device Full Speed Data + DFSDP USB Device High Speed Data - DHSDM USB Device Full Speed Data - DFSDM DHSDP USB Device High Speed Data + DHSDM USB Device High Speed Data - EMAC, GMAC An Ethernet Media Access Controller (EMAC) is provided in all SAM9x5 series except SAM9G15. The EMAC is capable of connecting to an MII or RMII. Although internally using the same signals, the RMII maps the signals in a more pinefficient manner. The transmit and receive bits are converted from a 4-bit parallel format to a 2-bit parallel scheme that is clocked at twice the rate. It uses two bits for transmit (ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). The Carrier Sense (ECRS) and Data Valid signals (ERXDV) in MII are combined into the ECRSDV signal in RMII. The Transmit error bit (ETXER) and Collision Detect (ECOL) in MII are not used in RMII mode. In addition to the EMAC, the SAMA5D3x provides an extra 10/100/1000 Mbps Gigabit Ethernet Media Access Controller (GMAC) with IEEE1588 support. The GMAC is capable of connecting to an MII, GMII or RGMII. The GMII and RGMII should be used for 1000 Mbps operation only. The MII is provided for 10/100 Mbps operation and uses TXD[3:0] and RXD[3:0], with TXD[7:4] and RXD[7:4] not used. For additional details, please refer to the application note “Gigabit Ethernet Implementation on SAMA5D3 Series” (document ref. 11164). Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 6 Table 2-7. EMAC/GMAC Signal Differences SAM9x5 Function Signal Name SAMA5D3x Function Signal Name Signal Name Function EMAC MII RMII RMII Transmit Clock or Reference Clock ETXCK Transmit Clock or Reference Clock REFCK EREFCK Transmit Clock or Reference Clock Receive Clock ERXCK — — — — Transmit Enable ETXEN Transmit Enable ETXEN ETXEN Transmit Enable Transmit Data ETX0–ETX3 Transmit Data ETX0–ETX1 ETX[1..0] Transmit Data Transmit Coding Error ETXER — — — — Carrier Sense and Data Valid ECRS Receive Data Valid CRSDV ECRSDV Carrier Sense/Data Valid Receive Data Valid ERXDV Receive Data ERX0–ERX3 Receive Data ERX0–ERX1 ERX[1..0] Receive Data Receive Error ERXER Receive Error ERXER ERXER Receive Error Collision Detect ECOL — — — — Management Data Clock EMDC Management Data Clock EMDC EMDC Management Data Clock Management Data Input/Output EMDIO Management Data Input/Output EMDIO EMDIO Management Data Input/Output — GTXCK Transmit Clock or Reference Clock — G125CK 125 MHz input Clock — G125CKO 125 MHz output Clock — GTXEN Transmit Enable — GTX[7..0] Transmit Data — GTXER Transmit Coding Error — GRXCK Receive Clock — GRXDV Receive Data Valid — GRX[7..0] Receive Data GMAC Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 7 Table 2-7. EMAC/GMAC Signal Differences (Continued) SAM9x5 Function 2.5.4 Signal Name SAMA5D3x Function Signal Name Signal Name Function — GRXER Receive Error — GCRS Carrier Sense and Data Valid — GCOL Collision Detect — GMDC Management Data Clock — GMDIO Management Data Input/Output HSMCI SAMA5D3x includes an extra High Speed Memory Card Interface (MCI2) supporting 4-bit connections and provides signals MCI2_CK, MCI2_CDA, and MCI2_DA[3..0]. Additionally for SAMA5D3x , MCI0 increases from 4-bit to 8-bit data path size and includes signals MCI0_DA[7..4]. Table 2-8. HSMCI Signal Differences SAM9x5 SAMA5D3x Function Multimedia Card Clock Signal Name Signal Name MCI0_CK, MCI0_CK, MCI1_CK MCI1_CK, Function Multimedia Card Clock MCI2_CK Multimedia Card Slot Command MCI0_CDA, MCI0_CDA, MCI1_CDA MCI1_CDA, Multimedia Card Command MCI2_CDA 2.5.5 Multimedia Card 0 Slot A Data MCI0_DA0–MCI0_DA3 MCI0_DA[7..0] Multimedia Card 0 Data Multimedia Card 1 Slot A Data MCI1_DA0–MCI1_DA3 MCI1_DA[3..0] Multimedia Card 1 Data — — MCI2_DA[3..0] Multimedia Card 2 Data PWMC SAMA5D3x has four Pulse Width Modulation Controllers, with each channel controlling two complementary square output waveforms (PWMH, PWML), instead of controlling one square output waveform (PWM) in SAM9x5. The PWMC also has programmable Fault Inputs (PWMFI) providing asynchronous protection of outputs. The PWMC signals are PWMH[3..0], PWML[3..0] and PWMFIx[3..0], which are also multiplexed with PIO lines. Table 2-9. PWMC Signal Differences SAM9x5 Function Pulse Width Modulation Output SAMA5D3x Signal Name PWM0–PWM3 Signal Name Function PWMH[3..0] PWM Waveform Output High PWML[3..0] PWM Waveform Output Low PWMFIx PWM Fault Input Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 8 2.5.6 SSC SAMA5D3x provides an extra Synchronous Serial Controller, with the signals of TD1, RD1, TK1, RK1, TF1, and RF1. 2.6 PIO SAMA5D3x provides an extra 32-bit Parallel IO Controller E, which manages up to 32 fully programmable I/O lines PE0– PE31. Note: Each pin is configurable, according to product definition as either a general-purpose I/O line only, or as an I/O line multiplexed with one or two peripheral I/Os. As the multiplexing is hardware defined and thus productdependent, during migration users must carefully determine the configuration of the PIO controllers required by their application. 3. Software Migration 3.1 Software Package Structure Atmel provides a SAMA5D3x software package for both the CodeSourcery GCC compiler and the IAR EWARM toolchain. In this application note, the IAR version serves as an example. Download the sama5d3x_softpack_0.5_for_ewarm_5.50_6.50.exe and install it on the PC. The library for SAMA5D3x will be installed in the default directory: Program Files\IAR Systems\ Embedded Workbench 6.0xxx\arm\exmples\Atmel\sama5d3x-ek. Note: The IAR version number in the directory name might be different depending on the version of IAR installed in user’s computer(s). The SAMA5D3x softpack consists of SAMA5D3x microcontroller drivers, software services and libraries, and demonstration application. The softpack includes the following seven folders: build: one batch file which can generate the binary files for all the included application projects without opening them by IAR IDE documentation: html documentation to introduce software structure, function definition, etc. examples: basic demo application projects for most of the peripherals examples_ethernet: demo application projects for Ethernet functions examples_storage: demo application projects for NAND, NOR, Serial Flash, MMC card, SD card examples_usb: demo application projects for USB functions libraries: includes the library files for the SAMA5D3x chip, SAMA5D3x-EK board, USB and different types of memory devices The software package for SAMA5D3x is structure-compliant with that of SAM9x5, which enables users to easily migrate from SAM9x5 to SAMA5D3x in software. 3.2 Library Migration The software package migration concerns mainly the libraries, which include libboard, libchip, libnandflash, libnorflash, liboweeprom and libspiflash. The application programming interface (API) changes in the libraries are detailed for the user’s information in the following summary. Note: Users do not need to change or update the listed APIs. Users may need to modify and adapt their application to the modified APIs. Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 9 libchip The migration of libchip library occurs in: 1. libraries\libchip\include\adc.h Changed function: void ADC_Initialize( Adc* pAdc, uint8_t idAdc, uint8_t trgEn, uint8_t trgSel, uint8_t sleepMode, uint8_t resolution, uint32_t mckClock, uint32_t adcClock, uint32_t startupTime, uint32_t sampleAndHoldTime ) ; uint32_t ADC_GetData( Adc* pAdc, uint32_t dwChannel ); to void ADC_Initialize( Adc* pAdc, uint32_t dwId ); uint32_t ADC_GetConvertedData( Adc* pAdc, uint32_t dwChannel ) ; Removed function: void ADC_StartConversion(Adc * pAdc); void ADC_Reset(Adc * pAdc); void ADC_TsCalibration(Adc * pAdc); void ADC_ConfigureMode(Adc * pAdc,uint32_t dwMode); void ADC_EnableChannel(Adc * pAdc,uint32_t dwChannel); void ADC_DisableChannel(Adc * pAdc,uint32_t dwChannel); uint32_t ADC_GetChannelStatus(Adc * pAdc); uint32_t ADC_GetLastData(Adc * pAdc); void ADC_EnableIt(Adc * pAdc,uint32_t dwSources); void ADC_DisableIt(Adc * pAdc,uint32_t dwSources); uint32_t ADC_GetItMask(Adc * pAdc); uint32_t ADC_GetItStatus(Adc * pAdc); uint32_t ADC_GetOverrunStatus(Adc * pAdc); void ADC_ConfigureExtMode(Adc * pAdc,uint32_t dwMode); uint32_t ADC_GetTsMode(Adc * pAdc); 2. Added function: void ADC_SetTiming( Adc* pAdc, uint32_t dwStartup, uint32_t dwTracking, uint32_t dwSettling ); void ADC_SetTrigger( Adc* pAdc, uint32_t dwTrgSel ); void ADC_SetAnalogChange( Adc *pAdc, uint8_t bEnDis ); uint8_t ADC_CheckConfiguration( Adc* pAdc, uint32_t dwMcK ) ; libraries\libchip\include\irq.h Changed function: void IRQ_ConfigureIT(uint32_t source, uint32_t mode, void( *handler )( void )); to 3. uint32_t IRQ_ConfigureIT(uint32_t source, uint32_t mode, void( *handler )( void )); libraries\libchip\include\pio.h 4. Added function: void PIO_Output_Low (Pio * pio, uint32_t pioId); libraries\libchip\include\pmc.h Added function: void PMC_SelectExt32KCrystal(void); void PMC_SelectInt32kCrystal(void); void PMC_SelectExt12M_Osc(void); void PMC_SelectInt12M_Osc(void); void PMC_SwitchMck2Pll(void); Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 10 5. void PMC_SwitchMck2Main(void); void PMC_SwitchMck2Slck(void); void PMC_SetPllA(uint32_t pll, uint32_t cpcr); void PMC_SetMckPrescaler(uint32_t prescaler); void PMC_SetMckDivider(uint32_t divider); void PMC_SetMckPllaDiv(uint32_t divider); void PMC_DisablePllA(void); uint32_t PMC_GetPeriMaxFreq( uint32_t dwId ); uint32_t PMC_SetPeriMaxClock( uint32_t dwId, uint32_t mck); libraries\libchip\include\ssc.h Changed function: void SSC_Configure(uint32_t bitRate, uint32_t masterClock); void SSC_ConfigureTransmitter(uint32_t tcmr, uint32_t tfmr); void SSC_ConfigureReceiver(uint32_t rcmr, uint32_t rfmr); void SSC_EnableTransmitter(void); void SSC_DisableTransmitter(void); void SSC_EnableReceiver(void); void SSC_DisableReceiver(void); void SSC_EnableInterrupts(uint32_t sources); void SSC_DisableInterrupts(uint32_t sources); void SSC_Write(uint32_t frame); uint32_t SSC_Read(void); uint8_t SSC_IsRxReady(void); to 6. void SSC_Configure(Ssc *ssc, uint32_t bitRate, uint32_t masterClock); void SSC_ConfigureTransmitter(Ssc *ssc, uint32_t tcmr, uint32_t tfmr); void SSC_ConfigureReceiver(Ssc *ssc, uint32_t rcmr, uint32_t rfmr); void SSC_EnableTransmitter(Ssc *ssc); void SSC_DisableTransmitter(Ssc *ssc); void SSC_EnableReceiver(Ssc *ssc); void SSC_DisableReceiver(Ssc *ssc ); void SSC_EnableInterrupts(Ssc *ssc, uint32_t sources); void SSC_DisableInterrupts(Ssc *ssc, uint32_t sources); void SSC_Write(Ssc *ssc, uint32_t frame); uint32_t SSC_Read(Ssc *ssc ); uint8_t SSC_IsRxReady(Ssc *ssc); Replaced libraries\libchip_sam9xx5\include\SAM9G15.h, SAM9G25.h, SAM9G35.h, SAM9X25.h, SAM9X35.h with libraries\libchip_sama5d3x\include\SAMA5D3X.h. 7. Removed \libraries\libchip_sam9xx5\include\dacc.h. 8. Removed \libraries\libchip_sam9xx5\include\isi.h. 9. Removed \libraries\libchip_sam9xx5\include\video.h. 10. Added \libraries\libchip_sama5d3x\include\fuse.h. 11. Added \libraries\libchip_sama5d3x\include\gmac.h for GMAC support. 12. Added \libraries\libchip_sama5d3x\include\smcNfc.h. 13. Added libraries\libchip_sama5d3x\include\component and libraries\libchip_sama5d3x\include\instance. Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 11 libboard The migration of libboard library occurs in: 1. libraries\libboard\include\board_memories.h Changed function: void BOARD_ConfigureDdram( void ); void BOARD_ConfigureNorFlash( void ) ; to 2. void BOARD_ConfigureDdram( uint8_t device ); void BOARD_ConfigureNorFlash( uint8_t busWidth ) ; libraries\libboard\include\dbgu_console.h 3. Added function: void DBGU_ConsoleUseUSART1(void); libraries\libboard\include\lcd_draw.h 4. Added function: void LCDD_Fill0( void ) ; libraries\libboard\include\lcdd.h 5. Added function: void LCDD_Flush_CurrentCanvas(void); Changed libraries\libboard_sam9xx5-ek\include\wm8731.h to libraries\libboard_sama5d3x-ek\include\wm8904.h. 6. Removed libraries\libboard_sam9xx5-ek\include\cand.h. 7. Removed libraries\libboard_sam9xx5-ek\omnivision_ov2640.h. 8. Added libraries\libboard_sama5d3x-ek\include\gmacb.h, gmacd.h, gmii.h for GMAC support. 9. Added libraries\libboard_sama5d3x-ek\include\sil9022a.h. libnandflash The migration of libnandflash library occurs in: 1. libraries\libnandflash\include\NandFlashDma.h Changed function: uint8_t NandFlashDmaTransferRam2Nand( uint32_t ramAddr, uint32_t size ); uint8_t NandFlashDmaTransferNand2Ram( uint32_t ramAddr, uint32_t size ); to 2. uint8_t NandFlashDmaTransferToNand( uint32_t srcAddr, uint32_t destAddr, uint32_t size ); uint8_t NandFlashDmaTransferFromNand( uint32_t srcAddr, uint32_t destAddr, uint32_t size ); libraries\libnandflash\include\NandFlashOnfi.h 3. Added function: uint8_t NandDisableInternalEcc (void); void NandSetTrimffs(uint8_t enable); uint8_t isNandTrimffs (void); void NandSetTrimPage (uint16_t page); uint16_t NandGetTrimPage (void); libraries\libnandflash\include\NandSpareScheme.h Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 12 4. Added function: uint8_t NandSpareScheme_build4096( struct NandSpareScheme *scheme, uint16_t spareSize, uint8_t eccOffset); Added libraries\libnandflash\include\NandSmc.h. libnorflash SAMA5D3x softpack adds libnorflash library for NOR Flash support. The libnorflash library includes: libraries\libnorflash\include\NorFlashAmd.h libraries\libnorflash\include\NorFlashApi.h libraries\libnorflash\include\NorFlashCFI.h libraries\libnorflash\include\NorFlashCommon.h libraries\libnorflash\include\NorFlashIntel.h. liboweeprom SAMA5D3x softpack adds liboweeprom library for oweeprom support. The liboweeprom library includes: libraries\liboweeprom\include\oweeprom.h. libspiflash The migration of libspiflash library occurs in: libraries\libspiflash\include\at45_spi.h Changed function: uint32_t AT45_Configure( At45* pAt45, Spid *pSpid, uint8_t ucSpiCs ) ; to uint32_t AT45_Configure( At45* pAt45, Spid *pSpid, uint8_t ucSpiCs, uint8_t polling) ; Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 13 4. Revision History Table 4-1. Revision History Doc. Rev Comments Change Request Ref. 11214A First issue — Migrating from SAM9x5-based to SAMA5D3x-based Applications [APPLICATION NOTE] 11214A–ATARM–11-Oct-13 14 Atmel Corporation 1600 Technology Drive Atmel Asia Limited Unit 01-5 & 16, 19F Atmel Munich GmbH Business Campus Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg San Jose, CA 95110 BEA Tower, Millennium City 5 Parkring 4 1-6-4 Osaki, Shinagawa-ku USA 418 Kwun Tong Road D-85748 Garching b. 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