ANM080 Migration from TSC80C31 to TS80C31X2 1. Description Due to market request, to improve specification and to optimize and rationalize the offer of its microcontroller family, Atmel Wireless & Microcontrollers has redesigned the core of its TSC80C31 microcontroller. This application note compares the SFRs, DC characteristics, AC characteristics between TSC80C31 and the new TS80C31X2. It should be also noted that the new TS80C31X2 core includes the programmable clock doubler feature that is described in a specific application note: ANM072. 2. Features Improvement 128b RAM TSC80C31 TS80C31X2 Yes Yes 32 I/Os Yes Yes 2 16 bit-Timers Yes Yes 5 Interrupt Sources Yes Yes 4 priority level interrupt system No Yes Wake up from Power Down by Reset Yes Yes Wake up from Power Down by INT0 & INT1 No Yes UART Yes Yes Enhanced UART modes No Yes Framing error detection No Yes Mulitprocessor communication No Yes X2 Mode No Yes Dual Data Pointer No Yes Power Off Flag No Yes Commercial Temperature Yes Yes Industrial Temperature Yes Yes Asynchronous port reset No Yes Maximum Frequency @ 5V 40 MHz Maximum Frequency @ 3V 20 Mhz 40 MHz X1 Mode 60 MHz eq. X2 Mode 30 MHz X1 Mode 40 MHz eq. X2 Mode X1 mode is the Standard Mode (12 clocks per instruction) X2 mode is a new mode (6 clocks per instruction) Rev. A - May 2, 2000 1 ANM080 3. SFR Mapping Hereafter a SFR mapping comparison table between TSC80C31 and TS80C31X2 TSC80C31 Old Core TS80C31X2 New Core PCON Register (Sfr:87h) PCON Register (Sfr:87h) 7 SMOD 6 - 5 - 4 - 3 GF1 2 GF0 1 PD 0 IDL Reset Value : 000x 0000b 7 6 SMOD SMOD 1 0 5 4 3 2 1 0 - POF GF1 GF0 PD IDL Reset Value : 00x1 0000b Comments : Power On flag , EUART functionality TSC80C31 Old Core TS80C31X2 New Core Reserved Register (Sfr:8Fh) CKCON Register (Sfr:8Fh) 7 6 5 4 3 2 1 0 - - - - - - - X2 Reset Value : xxxx xxx0b Comments : X2 mode TSC80C31 Old Core TS80C31X2 New Core SCON Register (Sfr:98h) SCON Register (Sfr:98h) 7 6 5 4 3 2 SM0 SM1 SM2 REN TB8 RB8 Reset Value : 0000 0000b 1 0 7 6 5 4 3 2 1 0 FE/ SM0 SM1 SM2 REN TB8 RB8 TI RI Reset Value : 0000 0000b Comments : EUART : Framing Error TSC80C31 Old Core TS80C31X2 New Core Reserved (Sfr:0A2h) AUXR1 Register (Sfr:0A2h) 7 6 5 4 3 2 1 0 - - - - GF3 0 - DPS Reset Value : xxxx x0x0b Comments : Dual DPTR 2 Rev. A - May 2, 2000 ANM080 TSC80C31 Old Core TS80C31X2 New Core Reserved (Sfr:0A9h) SADDR Register (Sfr:0A9h) Reset Value : 0000 0000b 7 6 5 4 3 2 1 0 Comments : EUART : Multiprocessor communication TSC80C31 Old Core TS80C31X2 New Core Reserved (Sfr:0B7h) IPH Register (Sfr:0B7h) 7 6 5 4 3 2 1 0 - - - PSH PT1H PX1H PT0H PX0H 1 0 Reset Value : xxx0 0000b Comments : 4 level priority interrupt TSC80C31 Old Core TS80C31X2 New Core Reserved (Sfr:0B9h) SADEN Register (Sfr:0B9h) 7 6 5 4 3 2 Reset Value : 0000 0000b Comments : EUART Multi processor communication All other registers are identical 4. DC Parameters Vcc = 5V +/-10% ; T = -40 to +85˚C ; T= 0 to 70˚C Symbol Parameters TSC80C31 Min VOL2 IPD Output Low Voltage ALE, PSEN Power Down Current Max TS80C31X2 Min Unit Comments Max Iol Iol Iol Iol Iol Iol = = = = = = 100 A TSC80C31 200 A TS80C31X2 1.6 mA TSC80C31 3.2 mA TS80C31X2 3.5 mA TSC80C31 7.0 mA TS80C31X2 0.3 0.3 V 0.45 0.45 V 1.0 1.0 V 30 50 µA Vcc = 2.0V to 5.5V Unit Comments Vcc = 2.7V to 5.5 V +/-10% ; T = -40 to +85˚C ; T= 0 to 70˚C Symbol Parameters TSC80C31 Min IPD Power Down Current Rev. A - May 2, 2000 Max 30 30 TS80C31X2 Min Max 50 30 µA Vcc = 2.0V to 5.5V Vcc = 2.0V to 3.3V 3 ANM080 5. AC Parameters 5.1. TS80C31X2 (M Version) 5.1.1. External Program Memory Characteristics TSC80C31 Symbol t t t t t t t t t LHLL AVLL LLAX LLIV LLPL PLPH PLIV PXIX PXIZ t AVIV t PLAZ Parameter Cond. TS80C31X2-Mxx 16 20 25 16 20 25 Unit MHz MHz MHz MHz MHz MHz ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in input instruction hold after PSEN Input instruction float after PSEN Min Min Min Max Min Min Max Min Max 110 40 35 185 45 165 125 0 50 90 30 35 170 40 130 110 0 45 70 20 35 130 30 100 85 0 35 115 47 47 220 52 167 147 0 55 90 35 35 170 40 130 110 0 43 70 25 25 130 30 100 80 0 33 ns ns ns ns ns ns ns ns ns Address to valid instruction in PSEN low to address float Max Max 230 10 210 10 170 8 272 10 210 10 160 10 ns ns 5.1.2. External Data Memory Characteristics TSC80C31 Symbol t t t t t t t t t t t t t t t t 4 RLRH WLWH RLDV RHDX RHDZ LLDV AVDV LLWL LLWL AVWL QVWX WHQX QVWH TRLAZ WHLH WHLH Parameter RD pulse width WR pulse width RD Low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to to WR High RD low to address float RD or WR high to ALE high RD or WR high to ALE high Cond. Min Min Max Min Max Max Max Min Max Min Min Min Min Min Min Max TS80C31X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 340 340 240 0 90 435 480 150 250 180 35 40 380 0 35 90 270 270 210 0 90 370 400 135 170 180 35 35 325 0 35 60 210 210 175 0 80 290 320 120 130 140 30 30 250 0 25 45 355 355 287 0 105 460 502 162 212 225 52 52 422 0 47 77 280 280 225 0 80 360 390 125 175 175 40 40 335 0 35 65 220 220 175 0 60 280 300 95 145 135 30 30 265 0 25 55 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev. A - May 2, 2000 ANM080 5.1.3. Serial Port Timing - Shift register TSC80C31 Symbol t t t t t XLXL QVXH XHQX XHDX XHDV Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock edge Input data hold after clock rinsing edge Clock rising edge to input data valid Cond. Min Min Min Min Max TS80C31X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 750 563 63 0 563 600 480 90 0 450 480 380 65 0 350 750 575 105 0 492 600 450 80 0 367 480 350 60 0 267 Unit ns ns ns ns ns 5.2. TS80C31X2 (L Version) 5.2.1. External Program Memory Characteristics TSC80C31 Symbol t t t t t t t t t t t LHLL AVLL LLAX LLIV LLPL PLPH PLIV PXIX PXIZ AVIV PLAZ Parameter ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float Cond. Min Min Min Max Min Min Max Min Max Max Max TS80C31X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 110 40 35 185 45 165 125 0 50 230 10 90 30 35 170 40 130 110 0 45 210 10 70 20 35 130 30 100 85 0 35 170 8 110 42 42 215 47 162 142 0 47 267 10 85 30 30 165 35 125 105 0 35 205 10 65 20 20 125 25 95 75 0 25 155 10 Unit ns ns ns ns ns ns ns ns ns ns ns 5.2.2. External Data Memory Characteristics TSC80C31 Symbol t t t t t t t t t t t t t t t t RLRH WLWH RLDV RHDX RHDZ LLDV AVDV LLWL LLWL AVWL QVWX WHQX QVWH TRLAZ WHLH WHLH Parameter RD pulse width WR pulse width RD Low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to to WR High RD low to address float RD or WR high to ALE high RD or WR high to ALE high Rev. A - May 2, 2000 Cond. Min Min Max Min Max Max Max Min Max Min Min Min Min Min Min Max TS80C31X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 340 340 240 0 90 435 480 150 250 180 35 40 380 0 35 90 270 270 210 0 90 370 400 135 170 180 35 35 325 0 35 60 210 210 175 0 80 290 320 120 130 140 30 30 250 0 25 45 350 350 282 0 100 455 497 157 217 220 47 47 417 0 42 82 275 275 220 0 75 355 385 120 180 170 35 35 330 0 30 70 215 215 170 0 55 275 295 90 150 130 25 25 260 0 20 60 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 5 ANM080 5.2.3. Serial Port Timing - Shift register TSC80C31 Symbol t t t t t XLXL QVXH XHQX XHDX XHDV Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock edge Input data hold after clock rinsing edge Clock rising edge to input data valid Cond. Min Min Min Min Max TS80C31X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 750 563 63 0 563 600 480 90 0 450 480 380 65 0 350 750 575 105 0 492 600 450 80 0 367 480 350 60 0 267 Unit ns ns ns ns ns 5.3. TS80C31X2 (V Version) 5.3.1. External Program Memory Characteristics TSC80C31 Symbol t t t t t t t t t t t LHLL AVLL LLAX LLIV LLPL PLPH PLIV PXIX PXIZ AVIV PLAZ Parameter ALE pulse width Address valid to ALE low Address hold after ALE low ALE low to valid instruction in ALE low to PSEN low PSEN pulse width PSEN low to valid instruction in input instruction hold after PSEN Input instruction float after PSEN Address to valid instruction in PSEN low to address float Cond. Min Min Min Max Min Min Max Min Max Max Max TS80C31X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 70 20 35 130 30 100 85 0 35 170 8 60 15 35 100 25 80 65 0 30 130 6 40 9 30 70 15 65 45 0 20 80 5 72 27 27 138 32 105 95 0 35 170 10 58 20 20 111 25 85 75 0 28 136 10 42 12 12 78 17 60 50 0 20 95 10 Unit ns ns ns ns ns ns ns ns ns ns ns 5.3.2. External Data Memory Characteristics TSC80C31 Symbol t t t t t t t t t t t t t t t t 6 RLRH WLWH RLDV RHDX RHDZ LLDV AVDV LLWL LLWL AVWL QVWX WHQX QVWH TRLAZ WHLH WHLH Parameter RD pulse width WR pulse width RD Low to valid data in Data hold after RD Data float after RD ALE low to valid data in Address to valid data in ALE low to RD or WR low ALE low to RD or WR low Address valid to WR low or RD low Data valid to WR transition Data hold after WR Data valid to to WR High RD low to address float RD or WR high to ALE high RD or WR high to ALE high Cond. Min Min Max Min Max Max Max Min Max Min Min Min Min Min Min Max TS80C31X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 210 210 175 0 80 290 320 120 130 140 30 30 250 0 25 45 180 180 135 0 70 235 260 90 115 115 20 20 215 0 20 40 100 100 90 0 45 150 180 60 95 65 10 10 160 0 15 35 225 225 177 0 65 285 310 100 140 140 32 32 270 0 30 50 185 185 143 0 51 231 250 80 120 113 25 25 223 0 23 43 135 135 102 0 35 165 175 55 95 80 17 17 165 0 15 35 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Rev. A - May 2, 2000 ANM080 5.3.3. Serial Port Timing - Shift register TSC80C31 Symbol t t t t t XLXL QVXH XHQX XHDX XHDV Parameter Serial port clock cycle time Output data setup to clock rising edge Output data hold after clock edge Input data hold after clock rinsing edge Clock rising edge to input data valid Rev. A - May 2, 2000 Cond. Min Min Min Min Max TS80C31X2-Mxx 16 20 25 16 20 25 MHz MHz MHz MHz MHz MHz 480 380 65 0 350 400 300 50 0 300 250 170 35 0 200 480 350 60 0 267 400 283 46 0 200 300 200 30 0 117 Unit ns ns ns ns ns 7 ANM080 6. Packages VQFP44 TQFP44 PQFP44 F1 PQFP44 F2 PQFP44 F2 PQFP44 F1 VFQP44 TQFP44 8 Min Max Min Max Min Max Min Max A C D D1 E E1 e f J L N1 N2 1.90 2.40 2.00 2.40 1.6 1.20 0.10 0.20 0.10 0.20 0.10 0.20 0.09 0.20 12.10 12.50 13.65 14.15 11.90 12.10 12.00 9.90 10.10 9.90 10.1 9.90 10.10 10.00 12.10 12.50 13.65 14.15 11.90 12.10 12.00 9.90 10.10 9.90 10.10 9.90 10.10 10.00 0.80 0.25 0.45 0.20 0.40 0.35 0.00 0.20 0.00 0.30 0.05 0.05 0.15 0.35 0.65 0.65 0.95 0.45 0.75 0.45 0.75 11 11 11 11 11 11 11 11 0.80 0.80 0.80 0.30 0.45 Rev. A - May 2, 2000 ANM080 7. Cross Reference if -xx stands for -12, -16, -20, -25, -30, -36, -40 then * = -M if -xx stands for -44, then * = -V if -xx stands for -L16 or -L20, then * = -L A: PDIP40 B: PLCC44 Old ATMEL part New ATMEL part TSC80C31-xxCA TS80C31X2*CA TSC80C31-xxCB TS80C31X2*CB TS80C31X2-MCB C: PQFP44 F1 E: VQFP44 TSC80C31-xxCC TS80C31X2*CC TSC80C31-xxCD TS80C31X2*CE V : 40 MHz@5V X1 TSC80C31-xxCE TS80C31X2*CE TSC80C31-xxCF TS80C31X2*CE TSC80C31-xxCG No equivalent L : 30 [email protected] X1 TSC80C31-xxCH No equivalent 20 [email protected] X2 TSC80C31-xxCI No equivalent TSC80C31-xxIA TS80C31X2*IA A: PDIP40 TSC80C31-xxIB TS80C31X2*IB B: PLCC44 TSC80C31-xxIC TS80C31X2*IC TSC80C31-xxID TS80C31X2*IE TSC80C31-xxIE TS80C31X2*IE TSC80C31-xxIF TS80C31X2*IE TSC80C31-xxIG No equivalent 16: 16MHz TSC80C31-xxIH No equivalent 20: 20 MHz C: Commercial TSC80C31-xxII No equivalent 25: 25MHz 0 to 70oC TSC80C31-xxA* No equivalent 33: 33MHz I: Imdustrial TSC80C31-xxM* No equivalent 40: 40MHz -45 to 85oC (1) 30 MHz@5V X2 M : 40 MHz@5V X1 (1) 20MHz@5V X1 TS80C31-16CB (1) C: Commercial 0 to 70oC I: Imdustrial -45 to 85oC C: PQFP44 F1 D: PQFP44 F2 E: VQFP44 (1) 12: 12MHz F: TQFP44 (1) See packages 8. Bibliography TSC80C31/TSC80C51 datasheet Rev. E (14 Jan. 97). TS80C31X2 datasheet Rev. B (Aug. 1999). Rev. A - May 2, 2000 9