View detail for ATFEE560

Atmel ATFEE560
Multi-Chip Rad-Hard Modules:
Reprogrammable FPGA matrix (ATF280) (x2)
EEPROM Memory (AT69170) (x2)
DATASHEET
Features

Non Volatile Rad Hard Reprogrammable FPGA
 ATF280 SRAM-based FPGA
 AT69170 Serial EEPROM

2x SRAM-based FPGA designed for Space use - ATF280
 560K equivalent ASIC gates
 28,800 cells ( two 3-input LUT or one 4-input LUT, one DFF)
 Unlimited reprogrammability
 SEE-hardened (Configuration RAM, DPRAM, DFF, I/O buffers)
 Rad Hard by Design - No need for mitigation techniques during design

Available DPRAM ressources in the ATF280
 230,400 bits of distributed RAM
 Organized in 32x4 blocks of DPRAM
 Independent of Logic Cells
 Single/Dual port capability

Reset System
 Individual reset on each FPGA
 Possibility to reset simultaneously both FPGAs

Clock System
 2 global clocks shared between both FPGAs
 6 global clocks and 2 fast clocks on FPGA 1
 6 global clocks and 2 fast clocks on FPGA 2

Flexible serial configuration
 Integrated 4Mbits serial non volatile memory
 On chip redundant configuration memory
 Designed to store Field Programmable Gate Arrays Configurations
 In-System Programming (ISP) via Two-Wire Interface
 Master/Slave configuration capability

Configuration Integrity Check
 Check of the data during FPGA application download
 Self Integrity Check (CSIC) of the configuration during FPGA operation

User IOs
 Cold-sparing and PCI-compliant I/Os:
 24 General Purpose IOs internally shared by both FPAGs and externally
accessible
 131 General Purpose IOs internally shared by both FPAGs
 107 General Purpose IOs only for FPGA1
41041BAERO09/15
 146 General Purpose IOs only for FPGA2
 4 LVDS transmitters on FPGA2
 4 LVDS receivers on FPGA2

Performance
 50MHz system performance
 10ns 32X4 DPRAM access time

Operating range



Voltages
 1.65V to 1.95V (Core)
 3V to 3.6V (Clustered I/Os)
Temperature
 - 55°C to +125°C
Radiation performance
 Total dose tested up to 60 krads (Si)
 AT69170, TID tested up to 60 krads (unbiased)
 ATF280, TID tested up to 300 krads
 No single event latch-up below a LET of 95 MeV/mg/cm2


ESD better than 2000V for I/O and better than 1000V for LVDS
Quality grades
 QML-Q or V
Description
The ATFEE560 is a radiation-hardened reprogrammable FPGA, especially designed for
space applications. For low-power consumption applications, the ATFEE560 is a new
device offering many advantages.
The ATFEE560 relies on Atmel ATF280 space qualified SRAM based FPGA together with
the Atmel AT69170 serial configuration EEPROM memory.
The ATFEE560 features an innovative built-in SEU protection, which eliminates the need
for Triple-Module-Redundancy (TMR). Its re-programmability makes multiple design
iterations possible. Moreover, post-programming burn-in is not necessary.
With the integration of redundant serial programming eeproms inside the package, the
ATFEE560 is perfectly suited for application requiring small footprint.
The Development Kit lets to evaluate the ATFEE560 quickly and economically, running
simple demonstrations as well as your complete applications. Throughout your
development, from concept to final integration, Atmel provides the tools and support to
help you successfully integrate your application into the ATFEE560.
The ATFEE560 is available in MQFP352 package and features 277 standard I/Os and 8
LVDS I/Os (4 Rx and 4Tx) for the user application.
Table 1.
ATFEE560 Summary
Function
ATFEE560
Available ASIC Gates (50% typ. routable)
2x 280K / 560K
RAM Bits
2x 115 200 / 230 400
Core Cells
2x 14 400 / 28 800
I/O
277
LVDS (Rx/Tx)
4 Rx / 4 Tx
ATFEE560 [DATASHEET]
41041BAERO09/15
2
ATFEE560 Overview
IO_FPGA1
[105:0]
Mode
FPGA1
Reset
FPGA1
M2
M1
M0
Figure 2.
RESETN
FPGA_1
Mode
Internally shared
IO[130:0]
Cascading
Interface
NVM_2
INIT
CON
CCLK
D0
Internally shared
IO[23:0]
Serial Cfg Interface
CSOUT
DATA
CLK
/CE
/RESET_OE
External access of
shared IO[23:0]
INIT
CON
CCLK
D0
CS0
Internally shared
IO[23:0]
Cascading
Interface
Internally shared
IO[130:0]
READY
SER_EN
Serial Cfg Interface
Mode
M2
M1
M0
NVM_1
RESETN
Mode
FPGA2
FPGA2
ILVDS[3:0]
ILVDSn[3:0]
OLVDS[3:0]
OLVDSn[3:0]
Reset
FPGA2
READY
SER_EN
IO_FPGA2
[144:0]
INIT_F2
INIT_F1
CON
CCLK
D0
FPGA_2
References


ATF280 Datasheet – ref : doc7750
AT69170 Datasheet – ref : doc41069
ATFEE560 [DATASHEET]
41041BAERO09/15
3
Table of Contents
1. Glossary............................................................................................. 5
2. Dies connections ................................................................................ 6
2.1
2.2
PINOUT ............................................................................................................ 6
2.1.1
FPGA1 ............................................................................................. 6
2.1.1.1
General Purpose IOs ........................................................ 6
2.1.1.2
Supply ............................................................................... 7
2.1.1.3
Configuration IOs .............................................................. 7
2.1.2
FPGA2 ............................................................................................. 8
2.1.2.1
General Purpose IOs ........................................................ 8
2.1.2.2
LVDS ............................................................................... 9
2.1.2.3
Supply ............................................................................. 10
2.1.2.4
Configuration IOs ............................................................ 10
2.1.3
Pins shared by both FPGAs.............................................................. 10
2.1.3.1
General Purpose Ios ....................................................... 10
2.1.3.2
Configuration IOs ............................................................ 11
2.1.4
NVM_1 and NVM_2 .......................................................................... 12
2.1.4.1
Configuration IOs ............................................................ 12
2.1.4.2
Supply ............................................................................. 12
2.1.5
Pins shared by both memories and both FPGA ................................ 12
2.1.6
JTAG
........................................................................................... 13
IOs from both FPGAs connected internally ..................................................... 13
3. Configuration Download ................................................................... 15
3.1
3.2
3.3
Master serial mode – Mode 0 .......................................................................... 15
Slave serial mode – mode 1 ............................................................................ 16
Available ATFEE560 configurations ................................................................ 16
3.3.1
FPGA1 master – FPGA2 slave ......................................................... 16
3.3.2
FPGA1 slave – FPGA2 slave............................................................ 19
4. Ordering Information ........................................................................ 20
4.1
4.2
ATFEE560FF Ordering Codes ........................................................................ 20
ATFEE560 Evaluation Kit Ordering Codes ..................................................... 20
5. Revision History ............................................................................... 21
ATFEE560 [DATASHEET]
41041BAERO09/15
4
1.
Glossary
FPGA
Field Programmable Gate Array
POR
Power On Reset
SRAM
Static Random Access Memory
SEU
Single Event Upset
CSIC
Configuration Self Internal Checker
TWI
Two wire Interface
ATFEE560 [DATASHEET]
41041BAERO09/15
5
2.
Dies connections
The aim here is to describe all the IO connections for each die implemented in the ATFEE560 ( 2x ATF280 and 2x
AT69170). The serial programmation mode has been privileged due to the limited number of pakages pins.
Both FPGA have three connection types for their General Purpose IOs, here after their descriptions and their number:

24 General Purpose IOs internally shared by both FPAGs and externally accessible

131 General Purpose IOs internally shared by both FPAGs

107 General Purpose IOs dedicated to FPGA1 and 146 General Purpose IOs dedicated to FPGA2 (including
INIT signals)
Each FPGA and each non-volatile memory has a dedicated supply.
2.1
PINOUT
2.1.1
FPGA1
2.1.1.1 General Purpose IOs
Table 2-1.
FPGA1, General Purpose IOs
IO
MQFP352
IO
MQFP352
IO
MQFP352
IO
MQFP352
IO1_GCK1
IO5
IO7
IO11
IO13
IO17
IO19
IO23
IO25
IO27
IO31
IO33
IO37
IO39
IO43
IO45
IO47
IO51
IO53
IO57
IO61_FCK1
IO63
10
11
12
13
14
15
16
17
18
19
20
21
22
25
26
27
28
29
30
31
32
33
IO79
IO83
IO85
IO87
IO93
IO97
IO99
IO103
IO105
IO111
IO125
IO127
IO131
IO133
IO137
IO139
IO143
IO145
IO147
IO151
IO153
IO157
39
40
41
42
43
44
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
IO173
IO175
IO177
IO180_FCK2
IO185
IO187
IO191
IO193
IO197
IO199
IO203
IO205
IO207
IO213
IO217
IO219
IO223
IO227
IO231
IO233
IO237
IO240_GCK2
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
92
93
94
95
96
IO259_LDC (*)
IO263
IO265_HDC (*)
IO267
IO273
IO277
IO279
IO283
IO480_GCK4
IO722_GCK7
IO917
IO919
IO923
IO925
IO927
IO931
IO937
IO939
IO943
IO945
IO947
IO951
103
104
105
106
108
109
110
113
114
116
135
136
137
138
139
140
141
142
143
144
145
146
IO65
34
IO159
63
IO245
98
IO953
147
ATFEE560 [DATASHEET]
41041BAERO09/15
6
IO67
IO71
IO73
35
36
37
IO163
IO165
IO167
64
65
66
IO247
IO251
IO253
99
100
101
IO77
38
IO171
69
IO257
102
IO960
IO303_INIT (*)
IO547_CS0 (*)
149
150
267
(*) : this general purpose IO is a configuration IO during configuration download
2.1.1.2 Supply
Table 2-2.
FPGA1, supply
GROUND
MQFP352
VDD = 1,8V
MQFP352
VCC = 3,3V
MQFP352
GND
1
VDD
2
VCC
24
GND
23
VDD
46
VCC
68
GND
45
VDD
88
VCC
112
GND
67
VDD
90
GND
87
VDD
134
GND
89
VDD
352
GND
111
GND
133
GND
156
2.1.1.3 Configuration IOs
Table 2-3.
FPGA1, configuration IOs
Configuration IO name
MQFP352
M0
M1
M2
IO259_LDC
IO265_HDC
IO303_INIT
IO547_CS0
RESETN
7
8
9
103
105
150
267
342
ATFEE560 [DATASHEET]
41041BAERO09/15
7
2.1.2
FPGA2
2.1.2.1 General Purpose IOs
Table 2-4.
FPGA2, General purpose IOs
IO
MQFP352
IO
MQFP352
IO
MQFP352
IO
MQFP352
IO1_GCK1
IO399
IO403
IO405
IO407
IO411
IO413
IO417
IO419
IO423
IO425
IO427
IO303_INIT
(*)
IO433
IO437
IO439
IO443
IO445
IO447
IO453
IO457
IO459
IO463
IO465
IO467
IO471
IO473
153
163
164
165
166
167
168
169
170
171
172
173
IO507
IO511
IO513
IO517
IO519
IO523
IO525
IO527
IO531
IO533
IO537
IO539
205
206
207
208
209
210
211
212
213
214
215
216
IO625
IO639
IO643
IO645
IO647
IO651
IO653
IO658_FCK4
IO661
IO665
IO667
IO671
256
257
258
259
260
261
262
268
269
270
271
272
IO757
IO759
IO763
IO765
IO767
IO771
IO773
IO777
IO779
IO783
IO785
IO787
300
301
302
303
304
305
306
307
308
311
312
313
174
179
180
181
182
183
184
185
186
187
188
189
190
191
192
IO543_FCK3
IO545
IO551
IO553
IO557
IO559
IO563
IO565
IO567
IO571
IO573
IO577
IO579
IO583
IO585
217
218
220
223
224
225
226
227
228
229
230
231
232
233
234
273
274
275
276
277
278
279
280
281
282
283
284
285
286
289
IO791
IO793
IO797
IO799
IO803
IO805
IO807
IO811
IO813
IO817
IO819
IO823
IO825
IO831
IO833
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
IO477
IO480_GCK4
IO482_GCK5
IO485
IO487
193
194
195
196
197
IO591
IO605
IO607
IO611
IO613
235
244
245
246
249
IO673
IO677
IO679
IO683
IO685
IO687
IO691
IO693
IO697
IO699
IO703
IO705
IO707
IO711
IO717
IO720_GCK6_CSOUTN
(*)
IO722_GCK7
IO725
IO733
IO737
290
291
292
293
294
IO847
IO851
IO853
IO857
IO859
329
330
333
334
335
ATFEE560 [DATASHEET]
41041BAERO09/15
8
IO491
IO493
IO497
IO503
198
201
202
203
IO617
IO619
IO623
IO627
250
251
252
254
IO739
IO745
IO747
IO751
295
296
297
298
IO505
204
IO633
255
IO753
299
IO863
IO865
IO960_GCK8_
336
337
338
(*) : this general purpose IO is also a configuration IO during configuration download
2.1.2.2 LVDS
Table 2-5.
FPGA2, LVDS IO
LVDS IOs
MQFP352
LVDS_Vref
ILVDS3
ILVDS3N
ILVDS4
ILVDS4N
OLVDS3
OLVDS3N
OLVDS4
OLVDS4N
ILVDS5
ILVDS5N
ILVDS6
ILVDS6N
OLVDS5
OLVDS5N
OLVDS6
OLVDS6N
LVDS_Vref
6
154
155
157
158
159
160
161
162
236
237
238
239
240
241
242
243
345
ATFEE560 [DATASHEET]
41041BAERO09/15
9
2.1.2.3 Supply
Table 2-6.
FPGA2 supply
GROUND
MQFP352
VDD = 1,8V
MQFP352
VCC = 3,3V
MQFP352
GND
199
VDD
176
VCC
200
GND
221
VDD
178
VCC
248
GND
247
VDD
222
VCC
288
GND
263
VDD
264
GND
265
VDD
266
GND
287
VDD
310
GND
309
GND
331
GND
351
2.1.2.4 Configuration IOs
Table 2-7.
2.1.3
FPGA2, configuration IOs
Configuration IO name
MQFP352
IO303_INIT
IO720_GCK6_CSOUTN
M0
M1
M2
RESETN
174
290
347
348
349
343
Pins shared by both FPGAs
2.1.3.1 General Purpose Ios
24 General purpose IOs are shared by both FPGAs and externally accessible.
Table 2-8.
General purpose IO shared by both FPGAs
FPGA1
FPGA2
MQFP352
IO225_OTSN
IO241_GCK3
IO271
IO225_OTSN
IO241_GCK3
IO637
91
97
107
ATFEE560 [DATASHEET]
41041BAERO09/15
10
IO655_CHECKN
IO825
IO847
IO851
IO853
IO857
IO859
IO873
IO891
IO893
IO897
IO899
IO903
IO905
IO907
IO911
IO913
IO545
IO713_D0
IO720_GCK6_CSOUTN
IO482_GCK5
IO655_CHECKN
IO351
IO385
IO387
IO393
IO345
IO397
IO343
IO339
IO383
IO379
IO377
IO373
IO337
IO365
IO367
IO371
IO175
IO713_D0
IO547_CS0
IO240_GCK2
115
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
148
151
219
253
2.1.3.2 Configuration IOs
Table 2-9.
Configuration IOs shared by both FPGAs
FPGA1
FPGA2
MQFP352
IO225_OTSN
IO655_CHECKN
IO713_D0
IO720_GCK6_CSOUTN (*)
IO225_OTSN
IO655_CHECKN
IO713_D0
IO547_CS0 (*)
91
115
151
219
CON
CON
350
CCLK
CCLK
344
(*) : These configuration I/Os are connected to insure proper cascading when the FPGA1 is in master mode and
FPGA2 in slave mode
ATFEE560 [DATASHEET]
41041BAERO09/15
11
2.1.4
NVM_1 and NVM_2
2.1.4.1 Configuration IOs
Table 2-10. Memories, configuration IOs
NVM_1
NVM_2
MQFP352
OE
OE
150
DATA
DATA
151
CLK
CLK
344
CE
CE
350
EN
EN
339
READY
READY
340
2.1.4.2 Supply
Table 2-11. Memories supply
NVM_1
NVM_2
MQFP352
GND
175
VDD = 3,3V
332
GND
177
VDD = 3,3V
152
The power pins are used to select NVM_1 or NVM_2 as configuration memory. The supplied memory download the
configuration data for both FPGAs. The other memory is in spare.
2.1.5
Pins shared by both memories and both FPGA
Table 2-12. Configuration IOs shared by both memories and both FPGAs
FPGA1
FPGA2
INIT
NVM_1
NVM_2
MQFP352
OE
OE
150
D0
D0
DATA
DATA
151
CCLK
CCLK
CLK
CLK
344
CON
CON
CE
CE
350
ATFEE560 [DATASHEET]
41041BAERO09/15
12
2.1.6
JTAG
The JTAG feature of the ATFEE560 is done by chaining the JTAG of both FPGAs internally.
TRST, TMS and TCK input pins are shared between both FPGAs.
Caution:
Due to ATF280 JTAG non functionality, use of the JTAG IOs is not possible. To avoid any misfunction
of the ATFEE560, it is required to apply the following polarities on each JTAG IOs.
Table 2-13. JTAG IOs
FPGA1
FPGA2
MQFP352
Polarity
TCK
TCK
341
VCC or pull-up
TRST
TRST
346
VCC or pull-up
TMS
TMS
5
VCC or pull-up
3
VCC or pull-up
4
Left unconnected
TDI
TDO
2.2
IOs from both FPGAs connected internally
131 General purpose IOs are shared by both FGPAs but only connected internally
Table 2-14. IOs connected internally
FPGA1
FPGA2
IDS_label
FPGA1
FPGA2
IDS_label
FPGA1
FPGA2
IDS_label
IO393
IO397
IO399
IO403
IO405
IO407
IO411
IO413
IO417
IO419
IO423
IO425
IO427
IO431
IO433
IO437
IO439
IO443
IO327
IO325
IO323
IO319
IO317
IO313
IO311
IO307
IO305
IO299
IO297
IO293
IO291
IO287
IO285
IO283
IO279
IO277
N14
IO533
IO537
IO539
IO543
IO551
IO553
IO557
IO559
IO563
IO565
IO567
IO571
IO573
IO577
IO579
IO583
IO585
IO591
IO187
IO185
IO180
IO177
IO171
IO167
IO165
IO163
IO159
IO157
IO153
IO151
IO147
IO145
IO143
IO139
IO137
IO133
G6
IO687
IO691
IO693
IO697
IO699
IO703
IO705
IO707
IO711
IO717
IO725
IO727
IO731
IO733
IO737
IO739
IO743
IO745
IO33
IO31
IO27
IO25
IO23
IO19
IO17
IO13
IO11
IO7
IO5
IO957
IO953
IO951
IO947
IO945
IO943
IO939
G14
N13
K14
M13
L14
L13
H14
L12
J13
P11
K13
L11
P13
K11
M10
H12
N10
G11
K5
K6
K4
E8
F10
F8
C8
G8
F9
D7
J11
E7
H11
F7
F6
H8
E6
E10
G12
B10
B13
A11
C13
F14
D13
E13
H6
G5
G7
F5
E4
B5
D5
A8
ATFEE560 [DATASHEET]
41041BAERO09/15
13
IO445
IO447
IO453
IO457
IO459
IO463
IO465
IO467
IO471
IO473
IO477
IO485
IO487
IO491
IO493
IO497
IO503
IO505
IO507
IO511
IO513
IO517
IO519
IO273
IO271
IO267
IO265
IO263
IO259
IO257
IO253
IO251
IO247
IO245
IO237
IO233
IO231
IO227
IO431
IO223
IO219
IO217
IO213
IO207
IO205
IO203
IO131
IO127
IO125
IO111
IO105
IO103
IO99
IO97
IO93
IO87
IO85
IO83
IO79
IO77
IO73
IO71
IO67
IO63
IO61
IO57
IO53
IO51
IO47
G10
F4
IO605
IO607
IO611
IO613
IO617
IO619
IO623
IO625
IO627
IO633
IO637
IO639
IO643
IO645
IO647
IO651
IO653
IO658
IO661
IO665
IO667
IO671
IO673
IO523
IO199
E9
IO677
IO45
F13
IO525
IO197
L1
IO679
IO43
A10
IO527
IO193
C9
IO683
IO39
F12
IO531
IO191
L2
IO685
IO37
B11
N9
M9
N12
L10
N11
P10
M11
K12
K10
F11
J9
J7
P3
J4
J5
J3
G4
H4
H5
J6
G3
D9
D6
H10
J10
G9
C7
H9
E11
J8
C6
D10
G13
C11
H13
D12
A12
B12
E5
E12
H7
D11
J12
A13
IO747
IO751
IO753
IO757
IO759
IO763
IO765
IO767
IO771
IO773
IO777
IO779
IO783
IO785
IO787
IO791
IO793
IO797
IO799
IO803
IO805
IO807
IO811
IO937
IO931
IO927
IO925
IO923
IO919
IO917
IO913
IO911
IO907
IO905
IO903
IO899
IO897
IO893
IO891
IO887
IO885
IO883
IO879
IO873
IO871
IO867
A9
D4
B8
C4
C10
D3
B9
B4
A7
D2
B7
C2
B6
B3
C5
B2
A5
C1
A4
A3
D1
A2
E3
ATFEE560 [DATASHEET]
41041BAERO09/15
14
3.
Configuration Download
Configuration is the process by which a design is loaded into an ATF280 FPGA. The ATF280 device is a SRAM based
FPGA, this leads to an unlimited reprogrammability capability.
It is possible to configure either the entire device or only a portion of the device. Sections can be configured while others
continue to operate undisturbed.
The ATF280 supports an auto-configuring Master serial mode, two Slave serial modes and two Slave parallel
modes.The following table summarizes the ATF280 configuration modes:
Configuration Download Mode
Mode
Description
M2
M1
M0
CCLK
Data
0
Master serial
0
0
0
Output
Serial
1
Slave serial
0
0
1
Input
Serial
7
Slave serial
1
1
1
Input
Serial
2
Slave parallel
0
1
0
Input
8/16 bits Word
6
Slave parallel
1
1
0
Input
8/16 bits Word
The ATFEE560 supports only the serial mode and more particularly Mode0 and Mode1.
3.1
Master serial mode – Mode 0
Mode 0 is a master mode. The Master Mode is auto-configuring; that is, after power-on-reset (POR) and the clearing of
configuration memory, it self-initiates configuration. The Master Mode uses an internal oscillator to provide CCLK for
clocking the external EEPROMs (configurators) which contain the configuration data. CCLK also drives the downstream
devices (Slaves) in the configuration cascade chain. Master Serial Mode clocks and receives data from an EEPROM
Serial Configuration Memory. After auto-configuration is complete, re-configuration can be initiated manually by the
user.
In this mode, the ATF280 is coupled to a serial EEPROM and managed automatically the whole configuration download
phase. The automatic configuration download always starts after a Power-On reset or a Manual Reset. The following
synoptic shows the required interface to be used for automatic configuration download purpose in mode 0.
Figure 3-1. ATF280 automatic configuration download in mode 0
M0
M1
M2
ATF280
FPGA
Vss
CCLK
IO713_D0
CON
IO303_INIT
IO259_LDC
IO265_HDC
CLK
DATA
/CE
/RESET_OE
Serial
EEPROM
READY
RESETn
ATFEE560 [DATASHEET]
41041BAERO09/15
15
3.2
Slave serial mode – mode 1
In slave mode, configuration is always initiated by another device. Data is applied to the device on the rising edge of
CCLK. In Slave Serial Mode, the device receives serial configuration data.
In mode 1, the ATF280 is coupled to a serial EEPROM and shall be externally driven for configuration download
purpose. The following synoptic shows the required interface to be used for configuration download purpose in mode 1.
Figure 3-2. ATF280 FPGA environment : configuration download in mode 1
Vcc
M0
M1
M2
Vss
ATF280
FPGA
CCLK
IO713_D0
CON
IO303_INIT
IO259_LDC
IO265_HDC
CLK
DATA
/CE
/RESET_OE
Serial
EEPROM
READY
IO547_CS0
RESETn
Start configuration
download
User applies a low logic level
before starting configuration
download
3.3
Reset EEPROM
counters
External Component to
start Configuration
Download
Available ATFEE560 configurations
The following choices has been done to implement both FPGAs in the product :
3.3.1

The FPGA 1 can be master (mode 0) or slave (mode 1).

The FPGA 2 can be only slave (mode 1).

FPGA1 in master mode : FPGA1 and FPGA2 are cascaded
FPGA1 master – FPGA2 slave
Table 3-1.
Configuration Mode selection
FPGA1
FPGA2
M0
0
1
M1
0
0
M2
0
0
CCLK
output
input
ATFEE560 [DATASHEET]
41041BAERO09/15
16
Figure 3-3. ATFEE560 connections overview
ATFEE560
FPGA1
FPGA2
M0
M1
M2
M0
M1
M2
NVM_1 or NVM_2
CSOUT
CCLK
D(0)
RESETN
INIT
CON
CS0
CCLK
D(0)
CON
INIT
RESETN
ERROR
DETECTION LOGIC
CLK
DATA
CE
RESET_OE
READY
SER_EN
PROGRAMMER
Both FPGA are cascaded (CR2 of configuration register activate for both FPGA). FPGA1 initiates the bitstream
download and provides the clock to the FPGA2 and the selected memory: At the end of its configuration (F1_CON at
‘1’), FPGA1 activate its CSOUT IO which is connected to the FPGA2 CS0 IO. Then FPGA2 drives its CON IO to
indicate to FPGA1 that it has to provide always the clock until the end of FPGA2 configuration (F2_CON at ‘1)’.
Cascade bitstream is formed by simple concatenation of FPGA1 bitstream and FPGA2 bitstream.
ATFEE560 [DATASHEET]
41041BAERO09/15
17
F1_RESETN
F1_CON
F1_INIT
F1_CSOUT
F2_CSO
F2_CON
F1 Bitstream
D0 / DATA
F2 Bitstream
Figure 3-4. Sequence of the events
To prevent corrupted FPGA1 programmation due to possible shift between both INIT signals (see the following figure),
both FPGA INIT shall not be connected.
VDD
CCLK Master
INIT Master
T0
T1
INIT Slave
T0'
Figure 3-5. Possible shift between INIT signals
If the INIT signal are connected, the INIT slave pulse will activate the Memory reset and therefore this will corrupt the
master FPGA (FPGA1) programmation.
ATFEE560 [DATASHEET]
41041BAERO09/15
18
3.3.2
FPGA1 slave – FPGA2 slave
Table 3-2.
Configuration mde selection
FPGA1
FPGA2
M0
1
1
M1
0
0
M2
0
0
CCLK
input
input
Figure 3-6. ATFEE560 connections overview
Both FPGA are in slave, the configuration is always initiated by an other device. This external component will provide
mainly CCLK/CLK and will manage both CS0 signals to select The FPGA to configure.
Bitstream in the memory will be a concatenation of both FPGA bitstream. This concatenation will be built based on the
CS0 management.
ATFEE560 [DATASHEET]
41041BAERO09/15
19
4.
Ordering Information
4.1
ATFEE560FF Ordering Codes
Atmel Ordering Code
Package
Type
ATFEE560FF-ZB-E
CQFP352
25°C
Engineering Samples
ATFEE560FF-ZB-SV (1)
CQFP352
-55°C / +125°C
QMLV equivalent
CQFP352
-55°C / +125°C
QMLQ equivalent
ATFEE560FF-ZB-MQ
Notes:
4.2
(1)
Temperature Range
Quality Level
1. QML Part Number pending DLA certification
ATFEE560 Evaluation Kit Ordering Codes
Atmel Ordering Code
ATFEE560-EK
Description
Evaluation Kit for ATFEE560
ATFEE560 [DATASHEET]
41041BAERO09/15
20
5.
Revision History
Doc. Rev.
Date
Comments
41041A
11/2014
Initial document release
41041B
09/2015
[Features]:
- Radiation data updated
[LVDS]:
- Missing IOs added
[JTAG]:
- JTAG chapter added to the PINOUT description
[Ordering information]:
- Part numbers updated
ATFEE560 [DATASHEET]
41041BAERO09/15
21
Atmel Corporation
Atmel Asia Limited
Atmel Munich GmbH
Atmel Japan G.K.
1600 Technology Drive
Unit 01-5 & 16, 19F
Business Campus
16F Shin-Osaki Kangyo Bldg.
San Jose, CA 95110
BEA Tower, Millennium City 5
Parkring 4
1-6-4 Osaki, Shinagawa-ku
USA
418 Kwun Tong Road
D-85748 Garching b. Munich
Tokyo 141-0032
Tel: (+1)(408) 441-0311
Kwun Tong, Kowloon
GERMANY
JAPAN
Fax: (+1)(408) 487-2600
HONG KONG
Tel: (+49) 89-31970-0
Tel: (+81)(3) 6417-0300
www.atmel.com
Tel: (+852) 2245-6100
Fax: (+49) 89-3194621
Fax: (+81)(3) 6417-0370
Fax: (+852) 2722-1369
© 2012 Atmel Corporation. All rights reserved. / Rev.: 41041BAERO09/15
Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its
subsidiaries. Other terms and product names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this
document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES
NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF
INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no
representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time
without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in,
automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.
ATFEE560 [DATASHEET]
41041BAERO09/15
22