ATF697FF Rad-Hard 32 bit SPARC V8 Reconfigurable Processor DATASHEET Features SPARC V8 High Performance Low-power 32-bit processor core AT697F Sparc v8 processor LEON2-FT 1.0.9.16.1 compliant 8 Register Windows Advanced Architecture 5 Stage Pipeline 32 kbyte 4-way associative instruction cache 16 kbyte 2-way associative data cache Integrated 32/64-bit IEEE 754 Floating-point Unit Reconfigurable Unit ATF697FF SRAM FPGA 280K equivalent ASIC gates 14400 cells Unlimited reprogrammability SEE hardened cells No need for Triple Modular Redundancy (TMR) FreeRAM™ 115200 Bits of Distributed RAM 32x4 RAM blocks organization Independent of logic cells Single/Dual Port capability Flexible Configuration modes Master/Slave Capability Serial Capability Flexible clock management 8 Global Clocks 1 Fast Clock Configuration Security Management Check of the data during FPGA configuration Self Integrity Check (SIC) of the configuration during FPGA operation Flexible Memory Interface PROM Controller SRAM Controller SDRAM Controller Timers Two 32-bit Timers Watchdog Timer 41000D−AERO03/14 Two 8-bit UARTs Interrupt Controller with 8 External Programmable Inputs General Purpose Interface 32 Parallel I/O Interface 140 Configurable Cold Sparing and PCI Compliant I/Os 4 LVDS transceivers and 4 LVDS receivers Debug and Test Facilities Debug Support Unit (DSU) for Trace and Debug Four Hardware Watchpoints Operating range Voltages 3.3V +/0.30V for I/O 1.8V +/0.15V for Core 1.25V +/0.15V for LVDS refrence Temperature -55°C to 125°C Clocks: Processor : 0 MHz up to 100 MHz Reconfigurable Unit : 0 MHz up to 50 MHz Performance: 86MIPS (Dhrystone 2.1) 23MFLOPS (Whetstone) Package MQFPT 352 Mass: 30g Radiation performances: RHA capability of 100 krad (Si) according to the MIL-STD-883 method 1019. No single event latch up below a LET threshold of of 60 MeV.cm2/mg at 125°C Evaluation kit including ATF697FF evaluation board ATF697FF sample ATF697FF [DATASHEET] 2 41000D−AERO03/14 Description ATF697FF is a multichip module integrating a 32 bit RISC processor together with a reconfigurable unit. The processor implementation is the European Space Agency (ESA) SPARC V8 LEON2 fault tolerant model also known as AT697F for the Atmel standalone chip. The reconfigurable unit is based on the Atmel 280kgates radiation hardened SRAMbased reprogrammable FPGA also known as ATF697FF. Both the processor unit and the reconfigurable units are manufactured using the Atmel 0.18µm rad-hard AT58KRHA CMOS technology. The two dies have been especially designed for space application by implementing hardened cells, on-chip concurrent transient and permanent error detection and correction and permanent self integrity check mechanism. By executing powerful instructions in a single clock cycle, the processor unit achieves throughputs around 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. The configurable unit offers a patented distributed 10 ns SEU hardened SRAM capability where the RAM can be used without losing logic resources. Multiple independent, synchronous or asynchronous, dual port or single port RAM functions (FIFO, scratch pad, etc.) can be created using Atmel’s macro generator tool. They are organized by blocks of 32x4 bits. ATF697FF contains an on-chip Integer Unit (IU), a Floating Point Unit (FPU), separate instruction and data caches, hardware multiplier and divider, interrupt controller, debug support unit with trace buffer, two 32-bit timers, Parallel and Serial interfaces, a Watchdog, a reconfigurable unit, a flexible Memory Controller and a 280 Kgates of reconfigurable unit. The configurable unit embeds 8 global clocks, 2 high speed clocks, 4 LVDS interface and 140 cold sparing and PCI compliant programmable I/Os dedicated to the application needs. The communication between the processor and the reconfigurable unit is performed by three different means: the internal PCI interface, GPIO and the EBI interface. ATF697FF only requires memory to be added to form a complete on-board computer. ATF697FF [DATASHEET] 3 41000D−AERO03/14 Table of Contents 1. Pin description ................................................................................... 9 1.1 1.2 1.3 1.4 1.5 1.6 1.7 System Interface ............................................................................................... 9 Clock Interface ................................................................................................ 10 Memory Interface ............................................................................................ 11 1.3.1 PROM ........................................................................................... 11 1.3.2 SRAM ........................................................................................... 11 1.3.3 I/O ........................................................................................... 12 1.3.4 SDRAM ........................................................................................... 12 Input / Output .................................................................................................. 12 LVDS Input Output .......................................................................................... 12 DSU Interface.................................................................................................. 13 Power Supply .................................................................................................. 13 2. Architecture ...................................................................................... 14 2.1 2.2 2.3 2.4 2.5 2.6 Integer Unit ..................................................................................................... 14 2.1.1 Program Counters ............................................................................ 16 2.1.2 Windowed Register File .................................................................... 17 2.1.3 Arithmetic & Logic Unit...................................................................... 18 Floating-Point Unit........................................................................................... 18 Memory Mapping ............................................................................................ 19 Fault Tolerance ............................................................................................... 19 2.4.1 Triple Modular Redundancy .............................................................. 19 2.4.2 Clock-Tree Skew .............................................................................. 20 2.4.3 Register File SEU Protection ............................................................ 20 2.4.4 Cache Parity ..................................................................................... 20 Operating Modes............................................................................................. 21 2.5.1 Reset Mode ...................................................................................... 21 2.5.2 Execute Mode ................................................................................... 21 2.5.3 Error Mode ........................................................................................ 21 2.5.4 Idle Mode .......................................................................................... 21 2.5.5 Debug Mode ..................................................................................... 21 Architecture of the reconfigurable unit............................................................. 22 2.6.1 FPGA Core ....................................................................................... 22 2.6.2 Configuration Logic ........................................................................... 23 2.6.3 User I/O ........................................................................................... 25 2.6.4 LVDS I/O........................................................................................... 25 2.6.5 Clock ........................................................................................... 25 3. Flexible memory interface ................................................................ 26 3.1 3.2 3.3 3.4 3.5 Overview ......................................................................................................... 26 PROM Interface .............................................................................................. 27 3.2.1 Overview ........................................................................................... 27 3.2.2 Read Access..................................................................................... 27 3.2.3 Write Access ..................................................................................... 28 3.2.4 Wait-States ....................................................................................... 28 3.2.5 Write Protection ................................................................................ 29 Memory-Mapped I/O ....................................................................................... 30 3.3.1 Overview ........................................................................................... 30 3.3.2 Interface Enable ................................................................................ 30 3.3.3 Read Access..................................................................................... 30 3.3.4 Write Access ..................................................................................... 31 3.3.5 Wait-States ....................................................................................... 31 3.3.6 Data Bus Width ................................................................................. 31 RAM Interface ................................................................................................. 31 3.4.1 SRAM Interface ................................................................................ 32 3.4.2 SDRAM Interface .............................................................................. 36 Write Protection............................................................................................... 37 3.5.1 Start/End Address Scheme............................................................... 37 ATF697FF [DATASHEET] 4 41000D−AERO03/14 3.6 3.7 3.5.2 Tag/Mask Address Scheme .............................................................. 38 3.5.3 Mixed Protection Schemes ............................................................... 40 BRDY* -Controlled Access .............................................................................. 40 Memory Mapped Reconfigurable Unit ............................................................. 43 4. EDAC management ......................................................................... 45 4.1 4.2 4.3 4.4 4.5 Overview ......................................................................................................... 45 EDAC Capability Mapping ............................................................................... 45 4.2.1 PROM Protection .............................................................................. 45 4.2.2 RAM Protection ................................................................................. 45 Operation ........................................................................................................ 45 4.3.1 Hamming Code ................................................................................. 46 4.3.2 Write Access ..................................................................................... 46 4.3.3 Read Access..................................................................................... 46 4.3.4 Correctable Error .............................................................................. 46 4.3.5 Uncorrectable Error........................................................................... 46 EDAC on 8-bit Memories ................................................................................ 47 EDAC Testing ................................................................................................. 48 4.5.1 EDAC testing overview ..................................................................... 48 4.5.2 Write Test ......................................................................................... 48 4.5.3 Read Test ......................................................................................... 48 5. Bus exception .................................................................................. 49 6. CACHES .......................................................................................... 50 6.1 6.2 6.3 6.4 6.5 Overview ......................................................................................................... 50 Operation ........................................................................................................ 50 6.2.1 Disabled Mode .................................................................................. 50 6.2.2 Enabled Mode ................................................................................... 50 6.2.3 Frozen Mode ..................................................................................... 50 6.2.4 Parity Protection ............................................................................... 51 Instruction Cache ............................................................................................ 51 6.3.1 Overview ........................................................................................... 51 6.3.2 Cache Control ................................................................................... 51 6.3.3 Operation .......................................................................................... 51 Data Cache ..................................................................................................... 52 6.4.1 Overview ........................................................................................... 52 6.4.2 Cache Control ................................................................................... 52 6.4.3 Operation .......................................................................................... 52 6.4.4 Error Reporting ................................................................................. 53 Diagnostic Cache Access ............................................................................... 53 7. Traps and Interrupts ......................................................................... 55 7.1 7.2 7.3 7.4 Overview ......................................................................................................... 55 Synchronous Traps ......................................................................................... 55 Traps Description ............................................................................................ 56 Asynchronous Traps / Interrupts ..................................................................... 57 7.4.1 Operation .......................................................................................... 57 7.4.2 Interrupts List .................................................................................... 57 7.4.3 I/O Interrupts ..................................................................................... 58 8. TIMER 60 8.1 8.2 8.3 Prescaler ......................................................................................................... 60 Timer 1 & Timer 2 ........................................................................................... 61 Watchdog ........................................................................................................ 62 9. UART 63 9.1 Overview ......................................................................................................... 63 9.1.1 Data Frame ....................................................................................... 63 9.1.2 Baud-Rate......................................................................................... 64 ATF697FF [DATASHEET] 5 41000D−AERO03/14 9.2 9.1.3 External Clock................................................................................... 64 9.1.4 Double Buffering ............................................................................... 64 9.1.5 Hardware Flow-Control ..................................................................... 64 9.1.6 Noise Filtering ................................................................................... 65 Operation ........................................................................................................ 65 9.2.1 Transmitter Operation ....................................................................... 65 9.2.2 Receiver Operation ........................................................................... 65 9.2.3 Interrupt Generation .......................................................................... 66 9.2.4 Loop-Back Mode ............................................................................... 66 10. GPIO 10.1 10.2 10.3 67 Processor General Purpose Interface ............................................................. 67 10.1.1 GPI as a 32-bit I/O Port..................................................................... 67 10.1.2 GPI Alternate Functions .................................................................... 68 Reconfigurable Unit General Purpose Interface .............................................. 69 10.2.1 Direction Configuration ..................................................................... 70 10.2.2 Pull-up/Pull-down .............................................................................. 70 10.2.3 Output Configuration ......................................................................... 70 10.2.4 Input Configuration ........................................................................... 71 LVDS Interfaces .............................................................................................. 72 11. ATF697FF reconfigurable unit: ......................................................... 73 11.1 11.2 11.3 11.4 Operating Modes / Lifephases ........................................................................ 73 11.1.1 Power-On Reset ............................................................................... 74 11.1.2 Manual Reset.................................................................................... 75 11.1.3 Mode Sampling ................................................................................. 76 11.1.4 Idle 77 11.1.5 Configuration Download.................................................................... 78 11.1.6 Run 78 Configuration Download .................................................................................. 80 11.2.1 Serial Configuration .......................................................................... 81 11.2.2 Master Mode – Mode 0 ..................................................................... 84 11.2.3 Slave Modes ..................................................................................... 90 Configuration Integrity Management ............................................................. 109 11.3.1 Check function ................................................................................ 109 11.3.2 Self Integrity Checker function ........................................................ 112 TM FreeRam .................................................................................................... 115 12. Internal communication .................................................................. 117 12.1 12.2 12.3 12.4 Introduction ................................................................................................... 117 EBI sharing ................................................................................................... 117 GPIO sharing ................................................................................................ 117 PCI sharing ................................................................................................... 117 12.4.1 Internal PCI interface: pin description ............................................. 117 12.4.2 Internal PCI arbiter .......................................................................... 119 12.4.3 PCI pheripheral (ATF697FF processor’s side) ................................ 120 12.4.4 PCI Interface ................................................................................... 126 12.4.5 To launch an internal PCI transaction between the processor and the reconfigurable unit .......................................................................... 128 13. Clock system.................................................................................. 129 13.1 13.2 13.3 Clock: processor part .................................................................................... 129 13.1.1 Overview ......................................................................................... 129 13.1.2 PCI Clock ........................................................................................ 129 13.1.3 CPU Clock ...................................................................................... 129 13.1.4 Fault-Tolerance & Clock ................................................................. 131 Clock: reconfigurable unit part....................................................................... 133 13.2.1 Global Clock ................................................................................... 134 13.2.2 Fast Clock ....................................................................................... 134 Reset System: reconfigurable unit part ......................................................... 134 ATF697FF [DATASHEET] 6 41000D−AERO03/14 14. Debug interface: DSU .................................................................... 136 14.1 14.2 14.3 14.4 14.5 Overview ....................................................................................................... 136 Debug Support Unit....................................................................................... 136 14.2.1 DSU Breakpoint .............................................................................. 137 14.2.2 Time Tag......................................................................................... 137 14.2.3 Trace Buffer .................................................................................... 138 14.2.4 DSU Memory Map .......................................................................... 139 14.2.5 Debug Operations ........................................................................... 141 14.2.6 DSU Trap ........................................................................................ 141 DSU Communication Link ............................................................................. 141 14.3.1 Data Frame ..................................................................................... 141 14.3.2 Commands ..................................................................................... 142 14.3.3 Clock Generation ............................................................................ 142 Booting from DSU ......................................................................................... 143 JTAG ........................................................................................................... 143 15. Register Description ....................................................................... 144 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 15.10 15.11 15.12 15.13 Integer Unit Registers ................................................................................... 145 Floating-Point Unit Registers ........................................................................ 152 Memory Interface Registers .......................................................................... 155 System Registers .......................................................................................... 163 Caches Register............................................................................................ 166 Idle Register .................................................................................................. 168 Timer Registers ............................................................................................. 169 UART Registers ............................................................................................ 173 Interrupt Registers......................................................................................... 178 General Purpose Interface Registers ............................................................ 181 PCI Registers ................................................................................................ 185 DSU Registers .............................................................................................. 203 Reconfigurable unit register description ........................................................ 210 16. Packaging information.................................................................... 213 16.1 16.2 Packaging drawing: MQFPT352 ................................................................... 213 Pin mapping: MQFPT352 .............................................................................. 214 17. Electrical characteristics ................................................................. 219 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 Absolute maximum ratings ............................................................................ 219 DC characteristics ......................................................................................... 220 17.2.1 DC characteristics ........................................................................... 220 17.2.2 LVDS AC/DC characteristics .......................................................... 222 Cold sparing .................................................................................................. 224 Power sequencing......................................................................................... 224 17.4.1 Global sequencing .......................................................................... 224 17.4.2 ATF697FF reconfigurable unit : Power-On Management ............... 224 Power Consumption ...................................................................................... 226 17.5.1 Power consumption of processor part............................................. 226 17.5.2 Power consumption of reconfigurable unit ...................................... 226 AC Characteristics ........................................................................................ 226 17.6.1 Natural Skew .................................................................................. 226 17.6.2 Maximum Skew .............................................................................. 228 17.6.3 Timing Derating .............................................................................. 230 AC parameters (reconfigurable unit) ............................................................. 231 Timing diagram ............................................................................................. 236 17.8.1 Diagram List.................................................................................... 236 17.8.2 Reset ......................................................................................... 236 17.8.3 Clock ......................................................................................... 237 17.8.4 PROM ......................................................................................... 238 17.8.5 SRAM ......................................................................................... 243 17.8.6 SDRAM ......................................................................................... 248 ATF697FF [DATASHEET] 7 41000D−AERO03/14 17.8.7 I/O ......................................................................................... 250 18. Ordering Information ...................................................................... 253 18.1 18.2 ATF697FF ordering codes ............................................................................ 253 ATF697FF Evaluation Kit Ordering codes ..................................................... 253 19. Revision History ............................................................................. 253 ATF697FF [DATASHEET] 8 41000D−AERO03/14 1. Pin description 1.1 System Interface PROC_RESET* Processor reset (input) When asserted, this asynchronous active low input immediately halts and resets the processor and all on-chip peripherals. The processor restarts execution after the 5th rising edge of the clock after PROC_RESET* was deasserted. FPGA_RESET* reconfigurable unit reset (input) FPGA_RESET* is the manual reset of the FPGA. This function reset the configuration download logic. FPGA_RESET* is internally pulled up to VCC and is active at a low level. Each time FPGA_RESET* is activated, the FPGA enters Manual Reset lifephase. ERROR* Processor error (open-drain output with pull-up) This active low output is asserted when the processor is halted in error mode. WDOG* Watchdog timeout (open-drain output with pull-up) This active low output is asserted when the watchdog timer has expired and remains asserted until the watchdog timer is reloaded with a non-null value. BEXC* Bus exception (input) This active low input is sampled simultaneously with the data during an access to the external memory. If asserted, a memory error is generated. M0, M1, M2 reconfigurable unit configuration mode (Input) [CFG] The configuration mode pins are used to define the configuration settings of the ATF697FF reconfiguration unit. ATF697FF reconfiguration unit samples the configuration mode pins each time a configuration clear cycle is ended. Caution: The mode pins should not be changed during power-on-reset or manual reset. CCLK – Reconfigurable unit configuration clock (bi-directional) CCLK function provides the clock signal used by the configuration logic. Depending on the mode used for configuration download procedure, CCLK function is configured as input or output. For slave mode, the CCLK is configured as an input whereas for master mode, it is configured as an output. When configured in input mode, CCLK is pulled up to VCC with an internal resistor D0 Configuration Data Bus LSB (Input/Output) D0 is used to transfer configuration data from or to the FPGA configuration SRAM. D0 is used for serial mode configuration. INIT (Input/Output) INIT is used as an error indicator regarding configuration logic. INIT is a bidirectional open drain I/O pulled up to VCC with an internal resistor. CON Configuration Status Indicator (Input/Output) CON is the FPGA configuration start and status pin. It is a bidirectional open drain I/O pulled up to VCC with an internal resistor. HDC High During Configuration (output) HDC indicates that the configuration download is on-going. HDC is an output and is polarized to a high logic level during the configuration. LDC Low During Configuration (output) ATF697FF [DATASHEET] 9 41000D−AERO03/14 LDC indicates that the configuration download is on-going. LDC is an output and is polarized to a low logic level during the configuration. CS0* Configuration Chip Select (Input/Output) CS0* is an active low chip select used during configuration. It is only available configuration download slave serial mode 1 CSOUT Configuration Cascade Output (Output) CSOUT is the configuration pin used to enable the downstream device in an FPGA cascade chain. CHECK* Configuration Check (Input/Output) CHECK* pin is used to enable the CHECK function when combined with a configuration download start. OTS* Dual Use Tri State (Input) OTS* pin is used to tri-state all the FPGA pins configured as user I/Os. 1.2 Clock Interface CLK Processor reference clock (input) This input provides a reference to generate the internal clock used by the processor and the internal peripherals. BYPASS Processor PLL bypass (input with pull-down) This active high input is used to bypass the internal PLL. When asserted, the processor is directly clocked from the external reference clock. When de-asserted, the processor receives its clock from the internal PLL. This signal shall be kept static and free from glitches while the processor is operating, as it is not sampled internally. Changing the signal shall only be performed while the processor is under reset otherwise the processor’s behavior is not predictable. LOCK PLL lock (output) When asserted, this active high output indicates the PLL of the processor is locked at a frequency corresponding to four times the frequency of the external processor reference clock. Caution: this signal is de-asserted as soon as the PLL unlocks. SKEW[1:0] Clock tree skew (input with pull-down) These input signals are used to programme the skew on the internal triplicated clock trees. These signals shall be kept static and free from glitches while the processor is operating, as they are not sampled internally. Changing these signals shall only be performed while the processor is under reset otherwise the processor’s behavior is not predictable. GCK1 -GCK8 Global clock (input) 8 differential global clocks are available on the reconfigurable unit. FCK3 – FCK4 Fast clock (input) 1 fast clock is available on the reconfigurable unit part. (The 2 pins are multiplexed all together). ATF697FF [DATASHEET] 10 41000D−AERO03/14 1.3 Memory Interface A[27:0] Address bus (output) The lower 28 bits of the 32 bit address bus carry instruction or data addresses during a fetch or a load/store operation to the external memory. The address of the last external memory access remains on the address bus whenever the current access can be made out of the internal cache. D[31:0] Data bus (bi-directional) The 32-bit bi-directional data bus serves as the interface between the processor and the external memory. The data bus is only driven by the processor during the execution of integer & floating-point store instructions and the store cycle of atomic-load-store instructions. It is kept in high impedance otherwise. However: only D[31:24] are used during an access to an 8-bit area D[15:0] are used as part of the general-purpose I/O interface whenever all the memory areas (ROM, SRAM & I/O) are 8-bit wide and the SDRAM interface is not enabled CB[7:0] Check bits (bi-directional) These signals carry the EDAC checkbits1 during a write access to the external memory and are kept in high impedance otherwise. This applies whatever the EDAC activation or not. Note: 1. While only 7 bits are useful for EDAC protection, CB[7] is implemented to enable programming of FLASH memories and takes the value of MCFG3.tcb[7]. OE* Output enable (output) This active low output is asserted during a read access to the external memory. It can be used as an output enable signal when accessing PROM & I/O devices. READ Read enable (output) This active high output is asserted during a read access to the external memory. It can be used as a read enable signal when accessing PROM & I/O devices. WRITE* Write enable (output) This active low output is asserted during a write-access to the external memory. It can be used as a write enable signal when accessing PROM & I/O devices. RWE*[3:0] PROM & SRAM byte write-enable (output) These active low outputs provide individual write strobes for each byte-lane on the data bus: RWE*[0] controls D[31:24], RWE*[1] controls D[23:16], RWE*[2] controls D[15:8] and RWE*[3] controls D[7:0], and they are set according to the transaction width (word/half-word/byte) and the bus width set for the respective area. BRDY* Bus ready (input) When driven low, this input indicates to the processor that the current memory access can be terminated on the next rising clock edge. When driven high, this input indicates to the processor that it must wait and not end the current access. 1.3.1 PROM ROMS*[1:0] PROM chip-select (output) These active low outputs provide the chip-select signals for decoding the PROM area. ROMS*[0] is asserted when the lower half of the PROM area is accessed (0x00000000 0x0FFFFFFF), while ROMS* [1] is asserted when the upper half is accessed (0x10000000 0x1FFFFFFF). 1.3.2 SRAM RAMS*[4:0] SRAM chip-select (output) ATF697FF [DATASHEET] 11 41000D−AERO03/14 These active low outputs provide the chip-select signals for decoding five SRAM banks. RAMOE*[4:0] SRAM output enable (output) These active low signals provide an output enable signal for each SRAM bank. 1.3.3 I/O IOS* I/O select (output) This active low output provides the chip-select signal for decoding the memory mapped I/O area. 1.3.4 SDRAM SDCLK SDRAM clock (output) This signal provides a reference clock for SDRAM memories. It is a copy of the processor internal clock. SDCS*[1:0] SDRAM chip select (output) These active low outputs provide the chip select signals for decoding two SDRAM banks. SDRAS* SDRAM row address strobe (output) This active low output provides the RAS signal (Row Access Strobe) for SDRAM devices. SDCAS* SDRAM column address strobe (output) This active low output provides the CAS signal (Column Access Strobe) for SDRAM devices. SDWE* SDRAM write strobe (output) This active low output provides the write strobe for SDRAM devices. SDDQM[3:0] SDRAM data mask (output) These active high outputs provide the DQM strobe (Data Mask) for SDRAM devices. 1.4 Input / Output GPIO[15:0] – General Purpose Input Output (bi-directional) These bi-directional signals can be used as general-purpose inputs or outputs to control external devices. Some of these signals have an alternate function and also serve as inputs or outputs for internal peripherals. Half of them are used as an internal mean of communication. IOx Programmable I/O (Input/Output) The programmable IOs are dedicated to user’s application. Each programmable IO can independently be configured as input, output or bidirectional IO. 1.5 LVDS Input Output OLVDSx LVDS Driver (Output) OLVDSx where ‘x’ is the LVDS channel: A1, A2, B1 or B2 OLVDSxN Complementary LVDS Driver (Output) OLVDSxN where ‘x’ is the LVDS channel A1, A2, B1 or B2 ILVDSx LVDS Receiver (Input) ILVDSx where ‘x’ is the LVDS channel A1, A2, B1 or B2 ILVDSxN Complementary LVDS Receiver( Input) ILVDSxN where ‘x’ is the LVDS channel A1, A2, B1 or B2 LVDS_REF_A reference voltage for LVDSA1 and LVDSA2 (1V25) ATF697FF [DATASHEET] 12 41000D−AERO03/14 1.6 LVDS_REF_B reference voltage for LVDSB1 and LVDSB2 (1V25) DSU Interface DSUEN DSU enable (input) When asserted, this synchronous active high input enables the DSU unit. If de-asserted, the DSU trace buffer will continue to operate but the processor will not enter debug mode. This signal is meant for debug purpose and shall be driven low in the final application. DSURX DSU receiver (input) This input provides the serial data stream to the DSU communication link receiver. This signal is meant for debug purpose and shall be driven low in the final application. DSUTX DSU transmitter (output) This output provides the serial data stream from the DSU communication link transmitter. DSUACT DSU active (output) This active high output is asserted when the processor is in debug mode and controlled by the DSU. DSUBRE DSU break enable (input) A low-to-high transition on this synchronous input signals a break condition and is used to set the processor into debug mode (see "Debug Support Unit" later in this document for specific use). This signal is meant for debug purpose and shall be driven low in the final application. 1.7 Power Supply PROC_VCC33 I/O power (supply) Power supply for the I/O pins of the processor. FPGA_VCC33 IO power (supply) Power supply for the I/O pins of the reconfigurable unit. PROC_VDD18 Processor Core power (supply) Power supply for the core of processor. FPGA_VDD18 FPGA Core power (supply) Power supply for the core of reconfigurable unit. VSS I/O ground (supply) Ground supply. PROC_VDD_PLL processor PLL power supply Power supply for the PLL. PROC_VSS_PLL processor PLL ground supply Ground supply for the PLL. ATF697FF [DATASHEET] 13 41000D−AERO03/14 2. Architecture ATF697FF is made of two separate units mounted on the same chip. The ATF697FF processor embeds an IU, and FPU and several pheripherals including 2 32-bits timers, 1 watchdog, 16 GPIO, 2 UART interfaces, 1 PCI interface, an interrupt controller, a debug support unit controller and a flexible memory controller. The reconfigurable unit chip is made of a symmetrical array of identical cells, which are totally reconfigurable. Figure 2-1. ATF697FF architecture overview 2.1 Integer Unit The ATF697FF processor integer unit is based on the LEON2-FT architecture, it implements the SPARC integer instruction-set defined in the SPARC Architecture Manual version 8. ATF697FF [DATASHEET] 14 41000D−AERO03/14 Figure 2-2. Integer Unit Architecture To execute instructions at a rate approaching one instruction per clock cycle, the IU employs a five-stage instruction pipeline that permits parallel execution of multiple instructions. Fetch The instruction is fetched from the instruction cache is enabled and available or the fetch is forwarded to the memory controller. Decode The instruction is placed in the instruction register and decoded. The operands are read from the register file and/or from immediate data and the next instruction computed CALL/Bicc target addresses are generated. Execute Arithmetic, logical and shift operations are performed and the result saved in temporary registers. Memory and JMPL/RETT target address are generated. Pending traps are prioritized and internal traps are taken, if any. Memory On a memory load instruction, data is read from the data cache if enabled and available or the read is forwarded to the memory controller. On a memory store instruction, store data is always forwarded to the memory controller and any matching data cache entry is invalidated if enabled. Write The result of any arithmetic, logical, shift or memory/cache read operation is written back to the register file. All five stages operate in parallel, working on up to five different instructions at a time. A basic "single-cycle" instruction enters the pipeline and completes in five cycles. By the time it reaches the write stage, four more instructions have entered and are moving through the pipeline behind it. So, after the first five cycles, a single-cycle instruction exits the pipeline and a single-cycle instruction enters the pipeline on every cycle. ATF697FF [DATASHEET] 15 41000D−AERO03/14 Of course, a "single-cycle" instruction actually takes five cycles to complete, but they are called single cycle because with this type of instruction the processor can complete one instruction per cycle after the initial five-cycle delay. Table 2-1. Instruction Cycles Jump and Link (JMPL) 2 Load Double-Word (LDD) 2 Store Single-Word (ST) 2 Store Double-Word (STD) 3 Integer Multiply (SMUL/UMUL/SMULcc/UMULcc) 5 Integer Divide (SDIV/UDIV/SDIVcc/UDIVcc) 35 Taken Trap (Ticc) 4 Atomic Load/Store (LDSTUB) 3 All other IU instructions 1 Single-Precision Multiply (FMULS) 161 Double-Precision Multiply (FMULD) 211 Single-Precision Divide (FDIVS) 201 Double-Precision Divide (FDIVD) 361 Single-Precision Square-Root (FSQRTS) 371 Double-Precision Square-Root (FSQRTD) 651 Single-Precision Absolute Value (FABS) 21 Single-Precision Move (FMOVS) 21 Single-Precision Negate (FNEGS) 21 Convert Single to Double-Precision (FSTOD) 21 All other arithmetic FPU instructions 71 Note: 2.1.1 Cycles per instruction (assuming cache hit and no load interlock) 1. This value is to be considered "typical". As the execution of FPU operations is operand-dependent, the true execution time can be lower or higher than mentioned. Program Counters The Program Counter (PC) contains the address of the instruction currently being executed by the Integer Unit, and the next Program Counter (nPC) holds the address (PC + 4) of the next instruction to be executed (assuming there is no control transfer and a trap does not occur). The nPC is necessary to implement delayed control transfers, wherein the instruction that immediately follows a control transfer may be executed before control is transferred to the target address. Having both the PC and nPC available to the trap handler allows a trap handler to choose between retrying the instruction causing the trap (after the trap condition has been eliminated) or resuming program execution after the trap causing instruction. ATF697FF [DATASHEET] 16 41000D−AERO03/14 2.1.2 Windowed Register File The ATF697FF processor contains a 136×32 register file divided into 8 overlapping windows, each window providing a working registers set at a time. Working registers are used for normal operations and are called r registers. The 136 registers are 32-bits wide and are divided into a set of 8 global registers and a set of 128 window registers grouped into 8 sets of 24 r registers called windows. At any given time, a program can access 32 active r registers (r0 to r31): 8 (common) global registers (r0 to r7) and 24 window registers (r8 to r31) that are divided by software convention into 8 ins, 8 locals and 8 outs: The first 8 globals (r0 to r7) are also called g registers (g0 to g7), they usually hold common data to all functions (as a special case, r0/g0 always returns the value 0 when read and discards the value written to it) The next 8 ins (r8 to r15) are also called i registers (i0 to i7), they usually are the input parameters of a function The next 8 locals (r16 to r23) are also called l registers (l0 to l7), they usually are scratch registers that can be used for anything within a function The last 8 outs (r24 to r31) are also called o registers (o0 to o7), they usually are the return parameters of a function The register file can be viewed as a circular stack, with the highest window joined to the lowest. Note that each window shares its ins and outs with adjacent windows: outs from a previous window are the ins of the current window and the outs of the current window are the ins of the next window. Figure 2-3. Circular Stack of Overlapping Windows The register file implementation is based on two dual-port RAMs. The first dual-port RAM provides the first operand of a SPARC instruction while the second dual-port RAM provides the second operand unless an immediate value is needed. When applicable, the result of the instruction is written back into the register file, so the two dual-port RAMs always have equal contents. When one function calls another, the calling function can choose to execute a SAVE instruction. This instruction decrements an internal counter, the current window pointer (CWP), shifting the register window downward. The caller’s out registers then become the calling function’s in registers and the calling function gets a new set of local and out registers for its own use. Only the pointer changes because the registers and return address do not need to be stored on a stack. The RESTORE/RETT instructions acts in the opposite way The Window Invalid Mask register (WIM) is controlled by supervisor software and is used by the hardware to determine whether a window overflow or underflow trap is to be generated by a SAVE, RESTORE or RETT instruction. ATF697FF [DATASHEET] 17 41000D−AERO03/14 When a SAVE, RESTORE or RETT instruction is executed, the current value of the CWP is compared against the WIM register. If the SAVE, RESTORE, or RETT instruction would cause the CWP to point to an “invalid” register set, a window_overflow or window_underflow trap is caused. 2.1.3 Arithmetic & Logic Unit The high-performance ALU operates in direct connection with all the 32 working registers. Within a single clock cycle, a 32-bit arithmetic operation between two working registers or between a working register and an immediate value is executed. 2.1.3.1 State Register The Processor State Register (PSR) contains fields that report the status of the processor operations or control processor operations. Instructions that modify its fields include SAVE, RESTORE, Ticc, RETT and any instruction that modifies the condition code fields (icc). Any hardware or software action that generates a trap will also modify some of its fields. A global interrupt management is provided: traps and interrupts (asynchronous traps) can be enabled/disabled and interrupts level response can be fine tuned. 2.1.3.2 Instruction Set ATF697FF processor SPARC instructions fall into six functional categories: load/store, arithmetic/logical/ shift, control transfer, read/write control register, floating-point and miscellaneous. Please refer to the SPARC V8 Architecture Manual for further details. 2.1.3.3 Multiply instructions The ATF697FF processor fully supports the SPARC V8 multiply instructions (UMUL, SMUL, UMULcc and SMULcc). The multiply instructions perform a 32×32-bit integer multiply producing a 64-bit result. SMUL and SMULcc perform signed multiply while UMUL and UMULcc performs unsigned multiply. UMULcc and SMULcc also set the condition codes to reflect the result. The Y register holds the most-significant half of the 64-bit result. 2.1.3.4 Divide Instructions The ATF697FF processor fully supports the SPARC V8 divide instructions (UDIV, SDIV, UDIVcc and SDIVcc). The divide instructions perform a 64×32 bit divide and produce a 32-bit result. SDIV and SDIVcc perform signed multiply while UDIV and UDIVcc performs unsigned divide. UDIVcc and SDIVcc also set the condition codes to reflect the result. Rounding and overflow detection is performed as defined in the SPARC V8 standard. The Y register holds the mostsignificant half of the 64-bit divided value. 2.2 Floating-Point Unit The ATF697FF processor floating-point unit is based on the MEIKO core and implements the SPARC floating-point instruction-set defined in the SPARC Architecture Manual version 8. The FPU interface is integrated into the IU pipeline and does not implement a floating-point queue1, so the IU is stopped during the execution of floating-point instructions. Note: 1. This means the qne bit in the FSR register is always zero and any attempts to execute the STDFQ instruction will generate an FPU_exception trap (0x08). The ATF697FF processor contains a 32×32 register file for floating-point operations, refered to as f registers (f0 to f31). These registers are 32-bits wide and can be concatenated to support 64-bits double-words (extended precision instructions and format are not supported). The whole 32 registers set is available at all time for any floating-point operation. Integer and single-precision data require a single 32-bit f register. Double-precision data require 64-bit of storage and occupy an even-odd pair of adjacent registers. ATF697FF [DATASHEET] 18 41000D−AERO03/14 2.3 Memory Mapping The 32-bit addressable memory space is divided into 6 areas, each area being allocated to a specific device type and externally or internally decoded accordingly: Table 2-2. Memory Mapping Address Range Area Device Select Signals 0x00000000 0x1FFFFFFF PROM1 2 2 0x20000000 0x3FFFFFFF 2.4 I/O 1 1 2 0x40000000 0x7FFFFFFF RAM 0x80000000 0x8FFFFFFF REGISTER1 0x90000000 0x9FFFFFFF DSU1 0xA0000000 0xFFFFFFFF PCI1 5 (SRAM) + 2 (SDRAM) n/a (internal) see PCI/cPCI specification Note: 1. Area is equally accessible in User & Supervisor mode on read & write access Note: 2. Write protection may apply if enabled on the area Fault Tolerance The processor has been especially designed for radiation-hardened applications. To prevent erroneous operations from single event transient (SET) and single event upset (SEU) errors, the ATF697FF processor implements a set of protection features including: 2.4.1 Full triple modular redundancy (TMR) architecture Programmable skews on the clock trees EDAC protection on IU and FPU register files EDAC protection on external memory interface Parity protection on instruction and data caches Triple Modular Redundancy To protect against SEU errors (Single Event Upset), each on-chip register is implemented using triple modular redundancy (TMR). This means that any SEU register error is automatically removed within one clock cycle while the output of the register maintains the correct (glitch-free) value. Moreover, an independent clock tree is used for each of the three registers making up one TMR module. This feature protects against SET errors (Single Event Transient) in the clock tree, to the expense of increased routing. The CPU clock and the PCI clock are built as three-clock trees. The same triplication is applied to the CPU reset and to the PCI reset as well. ATF697FF [DATASHEET] 19 41000D−AERO03/14 Figure 2-4. TMR Register with Separate Clock-Tree 2.4.2 Clock-Tree Skew Optionally, a skew can be applied between each of the three branches of the clock trees in order to provide additional SET protection. 2.4.3 Register File SEU Protection To prevent erroneous operations from SEU errors in the IU and FPU register file, each register is protected using a 7-bit EDAC checksum. Checking of the EDAC bits is done every time a fetched register value is used in an instruction. If a correctable error is detected, the erroneous data is corrected before being used. At the same time, the corrected register value is also written back to the register file. A correction operation incurs a delay 4 clock cycles, but has no other software visible impact. If an uncorrectable error is detected, a register_hardware_error trap (0x20) is generated. 2.4.4 Cache Parity The cache parity mechanism is transparent to the user, but in case of a cache parity error, a cache miss is generated and an access to external memory is perfomed to reload the cache entry, implying some delay. ATF697FF [DATASHEET] 20 41000D−AERO03/14 2.5 Operating Modes 2.5.1 Reset Mode The processor asynchronously enters reset mode as soon as the PROC_RESET* signal is asserted. It synchronously exits reset mode on the 5th rising edge of the SDCLK signal after the PROC_RESET* signal has been deasserted. While in reset mode, the IU, the FPU and all the peripherals are halted. The processor disables traps (PSR.et = 0), sets the supervisor mode (PSR.s = 1) and sets the program counter to location zero (PC = 0 & nPC = 4). Other IU, FPU and peripheral registers are initialized as well (see "Register Description"). On exit from reset mode, the processor enters execute mode. 2.5.2 Execute Mode In execute mode, the processor fetches instructions and executes them in the IU (Integer Unit) or the FPU (FloatingPoint Unit). Please refer to "The SPARC Architecture Manual Version 8" for further information. 2.5.3 Error Mode The processor enters error mode when a synchronous trap must occur while traps are disabled (PSR.et = 0). This essentially means that a trap which cannot be ignored occured while another trap is being serviced. In order for that synchronous trap to be serviced, the processor goes through the normal operation of a trap, including setting the trap-type bits (TBR.tt) to identify the trap type. It then enters error mode, halts and asserts the ERROR* signal. The only way to leave error mode is to assert the PROC_RESET* signal, which forces the processor into reset mode. All information placed in the IU, FPU and all peripherals registers from the last execute mode (the trap operation) remains unchanged unless stated otherwise (see "Register Description"). The code executed upon exit from reset mode can examine the trap type of the synchronous trap and the IU, FPU and all peripherals registers and deal with the information they contain accordingly. 2.5.4 Idle Mode While in execute mode, the processor may enter idle mode in software. Entry into idle mode is initiated by writing any value to the idle register (IDLE) and made effective on the next load instruction (caution). While in idle mode, the IU stops fetching instructions and is kept into a minimal activity. All other peripherals operate as nominal. Caution: In order to avoid any unwanted side-effect (idle entry not on the foreseen load instruction), the load instruction shall immediately follow the write operation to the idle regis ter, Idle mode is terminated as soon as an unmasked interrupt is pending (ITP.ipend) with an interrupt number of 15 or greater than the current processor interrupt level (PSR.pil). Then the processor directly goes through the normal operation of servicing the interrupt. 2.5.5 Debug Mode Caution: This section is for information purpose only. Caution: As its name clearly states, the Debug Support Unit (DSU) is exclusively meant for debugging purpose. None of the DSU features shall ever be used in the final application where the DSU shall be turned into an inactive state (DSUEN, DSUBRE and DSURX tied to a permanent low level). As a special case when the DSU is enabled (DSUEN signal asserted), debug mode is entered when specific conditions are met (see "Debug Support Unit" and "Register Description" chapters later in this document). In debug mode, the processor pipeline is held and the processor is controlled by the DSU so all processor registers, caches memories and even external peripherals can be accessed. ATF697FF [DATASHEET] 21 41000D−AERO03/14 2.6 Architecture of the reconfigurable unit The ATF697FF reconfigurable unit architecture is developed to provide the highest levels of performance, functional density and design flexibility in an FPGA. The cells in the Atmel array are small, efficient and can implement any pair of Boolean functions of (the same) three inputs or any single Boolean function of four inputs. The cell’s small size leads to arrays with large numbers of cells, greatly multiplying the functionality in each cell. A simple, high-speed busing network provides fast, efficient communication over medium and long distances. Here is an overview of the internal architecture of the ATF697FF reconfigurable unit: Figure 2-5. ATF697FF reconfigurable unit Architecture Overview ATF697FF – Reconfigurable Unit POR User I/O FPGA Core Configuration SRAM Configuration control Boundary Scan Controller 2.6.1 LVDS Interface Differential Clocks Configuration Self Internal Checker Configuration Load Checker FPGA Core At the heart of the Atmel reconfigurable unit architecture is a symmetrical array of identical cells. The array is continuous from one edge to the other, except for bus repeaters spaced every four cells. At the intersection of each repeater row and column is a 32 x 4 RAM block accessible by adjacent buses. Figure 2-6. Core device overview ATF697FF [DATASHEET] 22 41000D−AERO03/14 The following figure depicts the reconfigurable unit cell which is a highly configurable logic block based around two 3input LUTs (8 x 1 ROM), and which can be combined to produce one 4-input LUT. This means that any cell can implement two functions of 3 inputs or one function of 4 inputs. Figure 2-7. ATF697FF reconfigurable unit Core Cell Every cell includes a register element, a D-type flip-flop, with programmable clock and reset polarities. The initialization of the register is also programmable. It can be either SET or RESET. The flip-flop can be used to register the output of one of the LUT. It can also be exploited in conjunction with the feedback path element to implement a complete ripple counter stage in a single cell. The registered or unregistered output of each LUT can be feedback within the cell and treated as another input. This allows, for example, a single counter stage to be implemented within one cell without using external routing resources for the feedback connection. There is also a 2-to-1 multiplexer in every cell, and an upstream AND gate in the “front end” of the cell. This AND gate is an important feature in the implementation of efficient array multipliers as the product and carry terms can both be generated within a single logic cell. The cell flexibility makes the ATF697FF reconfigurable unit architecture well suited for most of the digital design application areas. 2.6.2 Configuration Logic The ATF697FF reconfigurable unit embeds the configuration logic function which is responsible of the configuration download. The configuration download is the operation by which the FPGA configuration SRAM is written in order to load the FPGA application. The configuration download operation is fully detailed in Configuration Download section of this document. The configuration logic is based on the 5 modules highlighted in the following figure. ATF697FF [DATASHEET] 23 41000D−AERO03/14 Figure 2-8. Configuration Logic Highlight ATF697FF – Reconfigurable Unit POR User I/O FPGA Core Configuration SRAM Configuration control Boundary Scan Controller LVDS Interface Differential Clocks Configuration Self Internal Checker Configuration Load Checker 2.6.2.2 POR The POR module is an analogic structure which senses the rise of the FPGA_VDD18 Power Supply. While FPGA_VDD18 is under the POR threshold, all the FPGA logic is maintained in a reset state. Once, the FPGA_VDD18 rises above the POR threshold, all the FPGA logic is activated (leaves reset state) and the FPGA enters in Power-On Reset lifephase. 2.6.2.3 Configuration Control The Configuration Control module is the main module of the configuration logic. It interfaces directly the POR module in order to manage the Power-On Reset lifephase. It also manages the configuration SRAM module and is capable to access SRAM cells in read or write mode. It drives the external configuration interface signals used to manage the configuration download. To finish, the configuration control is interconnected with the Configuration Load Checker module to ensure the integrity of the communication protocol. 2.6.2.4 Configuration SRAM The configuration SRAM module is made of a large set of SRAM memory points distributed through the whole FPGA. The configuration SRAM is fully cleared during the Power-On Reset and Manual Reset lifephases. It is written during Configuration Download lifephase with the bitstream data in order to configure the FPGA matrix. The configuration SRAM can also be read for integrity verification when using special function such as CHECK function or CSIC function. Refer to Configuration Integrity Management section for detailed description of those functions. 2.6.2.5 Configuration Load Checker The Configuration Load Checker module is responsible of the protection of the configuration download link. During the Configuration Download lifephase it manages the errors which are protocol relevant and informs the configuration control module of any error in such a way that the configuration control module can drive the appropriate error status signals to inform the system that an error occurred during the configuration. 2.6.2.6 Configuration Self Internal Checker The Configuration Self Internal Checker module is responsible of the integrity of the data during the Run lifephase. Once the configuration SRAM is written with the appropriate data, the ATF697FF reconfigurabale unit is capable to check all its effective configuration data and to notify the user in case of errors inside the configuration SRAM. This mechanism is useful to detect SEU that occur on the configuration SRAM. ATF697FF [DATASHEET] 24 41000D−AERO03/14 2.6.3 User I/O The ATF697FF reconfigurable unit features up to 150 general purpose IO for end user application. Each IO can be individually adjusted to the application needs thanks to its extensive configurability. All the IOs are cold sparing, have PCI compliance capability… Please refer to the General Purpose Interface section for detailed information on the User IOs. 2.6.4 LVDS I/O The ATF697FF reconfigurable unit provides a 200MHz LVDS interface with cold sparing feature. This interface can be used for high speed communication between the FPGA and its peripherals in order to exchange large amount of data. Please refer to the LVDS Interface section for detailed information on the LVDS IOs 2.6.5 Clock Please refer to the Clock section for detailed information on clock system implemented on the ATF697FF reconfigurable unit. ATF697FF [DATASHEET] 25 41000D−AERO03/14 3. Flexible memory interface 3.1 Overview The ATF697FF processor provides a direct memory interface to PROM, memory mapped I/O, asynchronous static ram (SRAM) and synchronous dynamic ram (SDRAM) devices. Figure 3-1. Memory Interface Overview Note: 1 1. WRITE* and RWE* [3:0]present redundant information and they can be used in PROM and SRAM areas. The memory controller decodes a 2 GB address space and performs chip-select decoding for two PROM banks, one I/O bank, five SRAM banks and two SDRAM banks. Table 3-1. Memory Controller Address Map Address Range Size Area 0x00000000 0x1FFFFFFF 512M PROM 0x20000000 0x3FFFFFFF 512M I/O 0x40000000 0x7FFFFFFF 1G SRAM and/or SDRAM The memory data bus width can be configured for either 8-bit or 32-bit access, independently for PROM, memorymapped I/O and SRAM. A fixed 32-bit wide data bus is required for SDRAM. EDAC protection is available for PROM, SRAM and SDRAM memories (CB[7:0] are always driven on a write access in 32-bit mode even when EDAC is not activated). ATF697FF [DATASHEET] 26 41000D−AERO03/14 To improve the bandwidth of the memory bus, accesses to consecutive addresses can be performed in burst mode. Burst transfers will be generated when the memory controller is accessed using a burst request from the internal bus. These includes instruction cache-line fills, double-word loads and double-word stores. The memory interface is controlled through 3 memory configuration registers: MCFG1 is dedicated to PROM and I/O configuration MCFG2 & MCFG3 are dedicated to SRAM and SDRAM configuration 3.2 PROM Interface 3.2.1 Overview The memory controller allows addressing of up to 512 MB of PROM in two banks. PROM memory access control is performed using dedicated chip selects (ROMS* [1:0]) and common output enable (OE*), read (READ) and write (WRITE*) signals. PROM banks map as follows: ROMS* [0] decodes the 256 MB lower half of the PROM area (0x00000000 0x0FFFFFFF) ROMS* [1] decodes the 256 MB upper half of the PROM area (0x10000000 0x1FFFFFFF) The PROM interface is controlled in the memory configuration registers (MCFG1 and MCFG3): 3.2.2 data bus width1 can be 8-bit or 32-bit (MCFG1.prwdh) wait-states2 can be programmed for read access (MCFG1.prrws) and write access (MCFG1.prwws) write can be enabled/disabled (MCFG1.prwen) EDAC protection3 can be enabled/disabled (MCFG3.pe) read/write access can be BRDY* -controlled (MCFG1.pbrdy) synchronously/asynchronously4 (MCFG1.abrdy) Note: 1. Upon reset, the PROM data bus width is automatically configured from the value read on the GPIO[1:0] pins. By driving GPIO[1:0] appropriately during reset, it is possible to set the PROM data bus width on boot. Note: 2. Upon reset, the PROM wait-states are set to the maximum value to allow booting on even the slowest memory. Note: 3. Upon reset, the PROM EDAC protection is automatically configured from the value read on the GPIO[2] pin. Note: 4. Asynchronous BRDY* -control feature common to PROM, SRAM and I/O interfaces. Read Access A PROM read access consists in two data cycles. ATF697FF [DATASHEET] 27 41000D−AERO03/14 Figure 3-2. PROM Read Access (no wait-states) 3.2.3 Write Access A PROM write access consists in an address lead-in cycle, a data write cycle and an address lead-out cycle. The write operation is strobed by the WRITE* signal. Figure 3-3. PROM Write Access (no wait-states) 3.2.4 Wait-States For application accessing slow PROM memories, the memory controller allows to insert wait-states during a PROM read access (MCFG1.prrws) and write access (MCFG1.prwws). Up to 30 wait-states can be inserted in steps of 2 (number of wait-states is twice the programmed value). ATF697FF [DATASHEET] 28 41000D−AERO03/14 Figure 3-4. PROM Read Access with 2 Wait-States (MCFG1.prrws=1) PROM read/write access can further be stretched when even more delay is needed (see "BRDY* -Controlled Access" later in this chapter"). 3.2.5 Write Protection PROM write access is disabled after reset and shall be enabled (MCFG1.prwen = 1) before any write access is attempted. Otherwise the write access is cancelled and a write_error trap (0x2B) is taken. Data Bus Width When configured for 32-bit PROM (MCFG1.prwdh = 00), D[31:0] shall be connected to the memory device(s). CB[7:0] shall be connected as well if EDAC protection is activated (MCFG3.pe = 1). To support applications with limited memory and/or limited performance requirements, the PROM area can be configured for 8-bit operations. When configured for 8-bit PROM (MCFG1.prwdh = 00), D[31:24] shall be connected to the memory device(s). Figure 3-5. 8-bit PROM Interface Since an IU load operation is always performed on a word basis (32-bit), read access to 8-bit memory is transformed into a burst of 4 read access to retrieve the 4 bytes. If EDAC protection is activated, a 5th byte read access is performed as well to retrieve the checkbits (see "Error Management EDAC" section later in this chapter). During a store operation, only the necessary bytes are written if EDAC protection is not activated. Caution: When EDAC protection is activated, only a full word write operation shall be performed (5 bytes). ATF697FF [DATASHEET] 29 41000D−AERO03/14 3.3 Memory-Mapped I/O 3.3.1 Overview The memory controller allows addressing a single memory-mapped I/O area. I/O memory access control is performed using a dedicated chip select (IOS* ) and common output enable (OE* ), read (READ) and write (WRITE* ) signals. No EDAC protection is available in this area. IOS* decodes a fixed 512 MB1 area (0x20000000 0x3FFFFFFF). The I/O interface is controlled in the memory configuration registers (MCFG1): 3.3.2 interface can be enabled/disabled (MCFG1.ioen) data bus width can be 8-bit or 32-bit (MCFG1.iowdh)2 wait-states can be programmed for read and write access (MCFG1.iows) read/write access can be BRDY* -controlled (MCFG1.iobrdy) synchronously/asynchronously3 (MCFG1.abrdy) Note: 1. The upper 256 MB area (0x30000000 0x3FFFFFFF) is a shadow of the lower 256 MB area (0x20000000 0x2FFFFFFF) because of the 28 bits address bus limitation. Note: 2. The I/O area shall only be accessed with load/store instructions of a size matching the configured bus width (LDUB/LDSB/STB when in 8-bit mode and LD/ST when in 32-bit mode). Note: 3. Asynchronous BRDY* -control feature common to PROM, SRAM and I/O interfaces. Interface Enable The I/O interface shall be enabled (MCFG1.ioen) before any read or write access is attempted, otherwise the access is cancelled and: 3.3.3 an instruction_access_exception trap (0x01) is generated if an instruction fetch is in progress a data_access_exception trap (0x09) is generated if a data load is in progress a write_error trap (0x2B) is generated if a data store is in progress Read Access An I/O read access consists in a address lead-in cycle (the IOS* signal is delayed by one clock cycle to provide a stable address for sampling), two data cycles and an address lead-out-cycle. Figure 3-6. I/O Read Access (no wait-states) ATF697FF [DATASHEET] 30 41000D−AERO03/14 3.3.4 Write Access An I/O write access consists in an address lead-in cycle, a data write cycle and an address lead-out cycle. The write operation is strobed by the WRITE* signal. Figure 3-7. I/O Write Access (no wait-states) 3.3.5 Wait-States For application accessing slow I/O devices, the memory controller allows to insert wait-states during an I/O read /write access (MCFG1.iows). Up to 15 wait-states can be inserted. An I/O read/write access can further be stretched when even more delay is needed (see "BRDY* -Controlled Access" later in this chapter"). 3.3.6 Data Bus Width When configured for 32-bit I/O (MCFG1.iowdh = 00), D[31:0] shall be connected to the I/O device(s). Only 32-bit load/store instructions (LD, ST) shall be used then. When configured for 8-bit I/O (MCFG1.iowdh = 00), D[31:24] shall be connected to the I/O device(s). Only 8-bit load/store instructions (LDUB, LDSB, STB) shall be used then. Figure 3-8. 8-bit I/O interface 3.4 RAM Interface The memory controller allows to control up to 1 GB of RAM. The global RAM area supports two RAM types: asynchronous static RAM (SRAM) and synchronous dynamic RAM (SDRAM). ATF697FF [DATASHEET] 31 41000D−AERO03/14 3.4.1 SRAM Interface 3.4.1.1 Overview The memory controller allows addressing of up to 768 MB of SRAM in 5 banks. SRAM memory access control is performed using dedicated chip selects (RAMS* [4:0]), output enables (RAMOE* [3:0]) and byte-write enables (RWE* [3:0]) signals. SRAM banks map as follows: RAMS* [0], RAMS* [1], RAMS* [2] and RAMS* [3] decode contiguous banks with a common programmable size (8 KB to 256 MB) at the lower half of the RAM area (from 0x40000000 onwards) RAMS* [4] decodes a fixed 256 MB at the upper half of the RAM area (0x60000000 0x6FFFFFFF) unless the SDRAM interface is enabled The SRAM interface is controlled in the memory configuration registers (MCFG2 and MCFG3): interface can be enabled/disabled (MCFG2.si) data bus width can be 8-bit or 32-bit (MCFG2.ramwdh) bank size can be set from 8 KB to 256 MB (MCFG2.rambs) wait-states can be programmed for read access (MCFG2.ramrws) and write access (MCFG2.ramwws) read-modify-write can be activated for sub-word write operations (MCFG2.ramrmw) EDAC protection1 can be enabled/disabled (MCFG3.re) read/write access can be BRDY* -controlled (MCFG2.rambrdy) synchronously/asynchronously2. (MCFG1.abrdy) Note: 1. EDAC protection activation common to SRAM and SDRAM interfaces. Note: 2. Asynchronous BRDY* -control feature common to PROM, SRAM and I/O interfaces. ATF697FF [DATASHEET] 32 41000D−AERO03/14 Figure 3-9. SRAM Bank Organization Note: 1. When SRAM bank size is set to 256 MB, bank 2 and bank 3 overlap with bank 4. Because priority is given to bank 4, bank 2 and bank 3 control signals are never asserted. Note: 2. When SDRAM is enabled, priority is given to the SDRAM over the SRAM. Any memory access above 0x60000000 is assigned to SDRAM and no SRAM control signal is asserted. 3.4.1.2 Read Access An SRAM read access consists in two data cycles. A dedicated output enable signal is provided for each SRAM bank (RAMOE* []) and is only asserted when that bank is selected. ATF697FF [DATASHEET] 33 41000D−AERO03/14 Figure 3-10. SRAM Read Access (no wait-states) 3.4.1.3 Write Access An SRAM write access consists in an address lead-in cycle, a data write cycle and an address lead-out cycle. Each byte lane has an individual write strobe (RWE*[]) to allow efficient byte and half-word writes. Figure 3-11. SRAM Write Access (no wait-states) Caution: If EDAC protection is activated on the RAM area or a common write strobe is used for the full 32 -bit data, read-modify-write shall be activated (MCFG2.ramrmw) so the EDAC checkbits integrity is preserved on sub-word writes. 3.4.1.4 Wait-States For application accessing slow SRAM memories, the memory controller allows to insert wait-states during an SRAM read access (MCFG2.ramrws) and write access (MCFG2.ramwws). Up to 3 wait-states can be inserted. ATF697FF [DATASHEET] 34 41000D−AERO03/14 Figure 3-12. SRAM Read Access with 1 Wait-State (MCFG2.ramrws = 1) SRAM read/write access to bank 4 (RAMS* [4]) can further be stretched when even more delay is needed (see "BRDY* -Controlled Access" later in this chapter"). 3.4.1.5 Data Bus Width When configured for 32-bit SRAM (MCFG2.ramwdh = 00), D[31:0] shall be connected to the memory device(s). CB[7:0] shall be connected as well if EDAC protection is activated (MCFG3.pe = 1). To support applications with limited memory and/or limited performance requirements, the SRAM area can be configured for 8-bit operations. When configured for 8-bit SRAM (MCFG2.ramwdh = 00), D[31:24] shall be connected to the memory device(s). Figure 3-13. 8-bit SRAM Interface On an 8-bit memory, 32-bit load/store instructions are always performed as a sequence of 4 consecutive memory accesses. If EDAC protection is activated, a 5th byte read access is performed as well to retrieve the checkbits (see "Error Management EDAC" section later in this chapter). During a store operation, only the necessary bytes are written if EDAC protection is not activated. When EDAC protection is activated, the processor will always perform a full-word read-modify-write transaction on any sub-word store operation. ATF697FF [DATASHEET] 35 41000D−AERO03/14 3.4.2 SDRAM Interface 3.4.2.1 Overview The SDRAM controller allows addressing of up to 1 GB of SDRAM in 2 banks. SDRAM memory access control is performed using dedicated chip selects (SDCS* [1:0]), data masks (SDDQM[3:0]), byte-write enables (SDWE* [3:0]) and clock (SDCLK) signals. SDRAM devices shall be 64 Mbit, 256 Mbit or 512 Mbit with 8 to 12 column-address bits, up to 13 row-address bits and exclusively 4 internal data banks. Only 32-bit data bus width is supported. The SDRAMs address bus shall be connected to A[14:2] and the bank address to A[16:15]. Devices with less than 13 address pins should only use the less significant bits of A[14:2]. SDRAM banks map as follows: SDCS* [0] and SDCS* [1] decode 2 contiguous banks with a common programmable size (4 MB to 512 MB) SDCS* [1:0] decode the upper half of the RAM area (0x60000000 0x7FFFFFFF) when the SRAM interface is enabled SDCS* [1:0] decode the lower half of the RAM area (0x40000000 0x5FFFFFFF) when the SRAM interface is disabled The SDRAM interface is controlled in the memory configuration registers (MCFG2 and MCFG3): interface can be enabled/disabled (MCFG2.se) bank size can be set from 4 MB to 512 MB (MCFG2.sdrbs) column size can be set from 256 to 4096 (MCFG2.sdrcls) commands can be sent to the devices (MCFG2.sdrcmd) timings parameters can be set (MCFG2.sdrcas, MCFG2.trp and MCFG2.trfc) auto-refresh can be enabled/disabled (MCFG2.sdrref) and programmed (MCFG3.srcrv) EDAC protection1 2 can be enabled/disabled (MCFG3.re) Note: 1.EDAC protection activation common to SRAM and SDRAM interfaces. Note: 2. Read-modify-write on sub-word operations simultaneously activated with EDAC. 3.4.2.2 Initialization After reset, the SDRAM controller automatically performs an SDRAM initialization sequence. It consists in a PRECHARGE cycle, two AUTO-REFRESH cycles and a LOAD-MODE-REG cycle on both SDRAM banks simultaneously. The controller programs the SDRAM to use page burst on read and single location access on write. 3.4.2.3 Timing Parameters The SDRAM interface parameters can be programmed so read/write access to SDRAM devices is optimized: Table 3-2. SDRAM Programmable Timing Parameters Function Parameter Range Unit Control CAS latency, RAS/CAS delay tCAS, tRCD 23 clocks MCFG2.sdrcas Precharge to activate tRP 23 clocks MCFG2.trp Auto-refresh command period tRFC 3 11 clocks MCFG2.trfc 10 32768 clocks MCFG3.srcrv Auto-refresh interval ATF697FF [DATASHEET] 36 41000D−AERO03/14 3.4.2.4 Refresh The SDRAM controller embeds a refresh module. When enabled (MCFG2.sdrref = 1), it periodically issues an AUTOREFRESH command to both SDRAM banks with a programmable period (MCFG3.srcrv). Depending on the SDRAM device used, the refresh period is typically 7.8 μs or 15.6 μs. The refresh period is calculated as . 3.4.2.5 Commands The SDRAM controller can issue three SDRAM commands (MCFG2.sdrcmd): PRE-CHARGE, AUTO-REFRESH and LOAD-MODE-REG. The command field is cleared after a command has been executed. If the LOAD-MODE-REG command is issued, the programmed CAS delay is used (MCFG2.sdrcas) while remaining fields are fixed (page read burst, single location write and sequential burst). A LOAD-MODE-REG command shall be issued whenever the programmed CAS delay is updated. 3.4.2.6 Read Access A read access consists in several phases: an ACTIVATE command to the desired bank and row a READ command after the programmed CAS delay data read(s) (single or burst with no idle cycles if requested on the internal bus) a PRE-CHARGE command to terminate the access (no bank left open) 3.4.2.7 Write Access A write access consists in several phases: 3.5 an ACTIVATE command to the desired bank and row a WRITE command after the programmed CAS delay data read(s) (single or burst with no idle cycles if requested on the internal bus) a PRE-CHARGE command to terminate the access (no bank left open) Write Protection Two write protection schemes are provided to protect the RAM area against accidental over-writing: the “Start/End Address Scheme” and the “Tag/Mask Address Scheme”. 3.5.1 Start/End Address Scheme Start/End Address scheme protection is implemented as 2 write protection units capable of each controlling supervisor and/or user write access inside/outside of a memory segment of any arbitrary size. each unit n is configured by two write protection registers (WPSTAn and WPSTOn): the unit can be enabled/disabled1 in supervisor mode2 (WPSTOn.su) and in user mode3 (WPSTOn.us) the segment is defined by a START address4 (WPSTAn.start) and an END address4 (WPSTOn.end) protection can be performed inside/outside the segment (WPSTAn.bp) Note: 1. The unit is enabled as soon as one of the two modes is enabled Note: 2. The DSU communication interface has supervisor status when accessing the RAM area Note: 3. The PCI interface (DMA and Target) has user status when accessing the RAM area ATF697FF [DATASHEET] 37 41000D−AERO03/14 Note: 4. Address is a 32-bit word-aligned offset from the start of the RAM area (0x40000000) Figure 3-14. Start/End Address Scheme Protection Overview The protection is based on a segment of any arbitrary size in the RAM address space (4 bytes to 1 GB): 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Write Address Comparison 27 28 29 30 31 field bit num Table 3-3. wor d Most significant write address bits The most significant bits of the write address are simply compared against the START and the END address of the segment (both boundaries included) to determine if the write address is inside the defined segment or in the block (outside of this segment). If the write protection unit is enabled for the current IU mode (user or supervisor) and a block or segment protection error is detected, the write access is cancelled and a write_error trap (0x2B) is generated. 3.5.2 Tag/Mask Address Scheme Tag/Mask address scheme protection is implemented as two write protection units capable of each controlling write access inside/outside of a binary aligned memory segment in the range of 32 KB - 1 GB. Each unit n is configured by a write protection register (WPRn): the unit can be enabled/disabled (WPRn.en) a TAG specifies the 15 most significant bits of the segment address (WPRn.tag) a MASK specifies which bits within the TAG are relevant (WPRn.mask) protection can be performed inside/outside the segment (WPRn.bp) ATF697FF [DATASHEET] 38 41000D−AERO03/14 Figure 3-15. Tag/Mask Address Scheme Protection Overview The protection is based on a segmentation of the RAM address space to define a segment in the range of 32 KB up to 1 GB: field 01 Most significant write address bits 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 Write Address Segmentation 27 28 29 30 31 bit num Table 3-4. 32 KB minimum area The most significant bits of the write address are XORed with the TAG, and the result is then ANDed with the MASK. If the final result is zero, the write address is in the defined segment, otherwise the write address is in the block (outside of this segment). If the write protection unit is enabled and a block or segment protection error is detected, the write access is cancelled and a write_error trap (0x2B) is generated. Figure 3-16. Segment/Block Protection Unit ATF697FF [DATASHEET] 39 41000D−AERO03/14 3.5.3 Mixed Protection Schemes It is possible to simultaneously use the Start/End Address and the Address/Mask write protection schemes. In that case (at least one unit is enabled in each scheme), the following rules applies: 3.6 when all enabled units are configured in block mode, a write_error trap (0x2B) is generated if at least one unit signals a protection error. when at least one enabled unit operates in segment mode, a write_error trap (0x2B) is generated only if all units configured in segment mode signal a protection error. BRDY* -Controlled Access The BRDY* signal can be used to further stretch a read or write access and is enabled separately for the PROM area (MCFG1.pbrdy), the SRAM area decoded by RAMS* [4] (MCFG2.rambrdy) and the I/O area (MCFG1.iobrdy). An access is always performed with at least the pre-programmed number of wait-states specified in the appropriate memory configuration register (MCFG1 & MCFG2), but is further stretched until BRDY* is asserted. Termination of a BRDY* -controlled access can be performed in two different modes: synchronous mode (MCFG1.abrdy = 0): BRDY* is sampled on the rising edge of the clock and shall meet the setup (t19) and hold (t20) timing constraints (see "AC Characterictics"). asynchronous mode (MCFG1.abrdy = 1): BRDY* shall be kept asserted for 1.5 clock cycle so it is guaranteed to meet at least one rising edge of the clock (setup/hold timing constraints do not apply anymore). Data in a read access shall be kept stable until de-assertion of the device select (ROMS* [0]/ ROMS*[1] or RAMS* [4] or IOS* , as appropriate) and output-enable (OE* or RAMOE* [4], as appropriate) signals. The access is terminated on the rising edge of the clock that immediately follows the detection of the asserted BRDY* Figure 3-17. Synchronous BRDY* -Controlled PROM Read Access (MCFG1.abrdy=0) ATF697FF [DATASHEET] 40 41000D−AERO03/14 Figure 3-18. Asynchronous BRDY* -Controlled PROM Read Access (MCFG1.abrdy=1) Figure 3-19. Synchronous BRDY* -Controlled IO Read Access(MCFG1.abrdy=0) Figure 3-20. Asynchronous BRDY* -Controlled IO Read Access (MCFG1.abrdy=1) ATF697FF [DATASHEET] 41 41000D−AERO03/14 Figure 3-21. Asynchronous BRDY* -Controlled SRAM4 Read Access (MCFG1.abrdy=0) Figure 3-22. Asynchronous BRDY* -Controlled SRAM4 Read Access (MCFG1.abrdy=1) ATF697FF [DATASHEET] 42 41000D−AERO03/14 3.7 Memory Mapped Reconfigurable Unit The embedded memory controller shares its interface with the reconfigurable unit so that it is possible to map the reconfigurable unit on the standard address map of th processor unit. All the signals from the PROM, IO and SRAM interface are shared between the two units making possible the use of the reconfigurable unit in any of the memory area supported by the processor. The SDRAM control signals are not made available for the reconfigurable unit. The complete address, data and checkbit buses are shared between the two units with respect to the following assignment: Table 3-5. ATF697 FF pin name IO connexions with the memory interface reconfigur able unit pin name A[0] A[1] A[2] A[3] A[4] A[5] A[6] A[7] A[8] A[9] IO957 IO953 IO951 IO947 IO945 IO943 IO939 IO937 IO931 IO927 D[0] IO5 D[1] IO7 D[2] IO11 D[3] IO13 D[4] IO17 D[5] IO19 D[6] IO23 D[7] IO25 pin direction reconfigur able unit side Input Input Input Input Input Input Input Input Input Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional ATF69 7FF pin name A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] A[19] reconfigur able unit pin name ADDRESS BUS IO925 IO923 IO919 IO917 IO913 IO911 IO907 IO905 IO903 IO899 DATA BUS D[11] IO37 D[12] IO39 D[13] IO43 D[14] IO45 D[15] IO47 D[16] IO51 D[17] IO53 D[18] IO57 pin direction reconfigur able unit side Input Input Input Input Input Input Input Input Input Input Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional ATF697F F pin name reconfigur able unit pin name pin direction reconfigur able unit side A[20] A[21] A[22] A[23] A[24] A[25] A[26] A[27] IO897 IO893 IO891 IO887 IO885 IO883 IO879 IO873 Input Input Input Input Input Input Input Input D[22] IO67 D[23] IO71 D[24] IO73 D[25] IO77 D[26] IO79 D[27] IO83 D[28] IO85 D[29] IO87 ATF697FF [DATASHEET] Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional 43 41000D−AERO03/14 ATF697 FF pin name reconfigur able unit pin name D[8] IO27 D[9] IO31 D[10] IO33 CB[0] IO99 CB[1] IO103 CB[2] IO105 ROMS* [0] ROMS* [1] pin direction reconfigur able unit side Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional Bidirectional IO825 Input IO823 Input IOS* IO807 Input OE* IO805 Input READ IO831 Input WRITE * IO797 Input SDCLK IO351 Input BEXC* IO803 Output BRDY* IO799 Output Caution: ATF69 7FF pin name D[19] D[20] D[21] CB[3] CB[4] CB[5] RAMS* [0] RAMS* [1] RAMS* [2] RAMS* [3] RAMS* [4] RWE*[ 0] RWE*[ 1] RWE*[ 2] RWE*[ 3] reconfigur able unit pin name pin direction reconfigur able unit side Bidirectional BiIO63 directional BiIO65 directional CHECKBIT BUS BiIO111 directional BiIO125 directional BiIO127 directional CONTROL SIGNALS IO611 IO857 Input IO853 Input IO851 Input IO847 Input IO833 Input IO819 Input IO817 Input IO813 Input IO811 Input ATF697F F pin name reconfigur able unit pin name D[30] IO93 D[31] IO97 CB[6] IO131 CB[7] IO133 RAMOE *[0] RAMOE *[1] RAMOE *[2] RAMOE *[3] RAMOE *[4] pin direction reconfigur able unit side Bidirectional Bidirectional Bidirectional Bidirectional IO871 Input IO867 Input IO865 Input IO863 Input IO859 Input Warning: These shared IO have to be correctly configurated to avoid signal reflexions and damages on the IO of the ATF697FF component. In particular, severals outputs on the same IO should not be configurated in output at the same time. ATF697FF [DATASHEET] 44 41000D−AERO03/14 4. EDAC management 4.1 Overview The ATF697FF processor implements on-chip error detection and correction (EDAC). It can correct any single-bit error and detect double-bit errors in a 32-bit word. 4.2 EDAC Capability Mapping EDAC is available on PROM, SRAM and SDRAM memory areas. Table 4-1. External Memory EDAC Capability Address Range Area 0x00000000 0x1FFFFFFF PROM 0x20000000 0x3FFFFFFF I/O 0x40000000 0x7FFFFFFF SRAM SDRAM 4.2.1 EDAC Protected 8 bits yes 32 bits yes All no 8 bits yes 32 bits yes 32 bits yes PROM Protection When EDAC is activated on the PROM area1 (MCFG3.pe = 1), error detection and correction is performed on every instruction fetch and data load in that area. Note: 4.2.2 1. Upon reset, EDAC on the PROM area is automatically configured from the value read on the GPIO[2] pin. By driving GPIO[2] high during reset, it is possible to enable EDAC on PROM on boot. RAM Protection When EDAC is activated on the RAM area1 instruction fetch and data load in that area. (MCFG3.re = 1), error detection and correction is performed on every Note: 1. When EDAC is enabled on the RAM area, read-modify-write on the SRAM (MCFG2.ramrmw) shall be enabled as well so the integrity of the EDAC checkbits is preserved on sub-word writes. Note: 2. Activating EDAC on the RAM area automatically enables read-modify-write on sub-word writes to the SDRAM. Caution: 4.3 2 The RAM area shall always be initialized with 32-bit word writes prior to EDAC activation so further sub-word writes (performed as 32-bit read-modify-write atomic operations) always successfully pass the initial read & check step (see "Read Access"). Operation When enabled, the EDAC operates on every access to the external memory. ATF697FF [DATASHEET] 45 41000D−AERO03/14 4.3.1 Hamming Code For each word, a 7-bit checksum is generated according to the following equations: CB0 = D0 ^ D4 ^ D6 ^ D7 ^ D8 ^ D9 ^ D11 ^ D14 ^ D17 ^ D18 ^ D19 ^ D21 ^ D26 ^ D28 ^ D29 ^ D31 CB1 = D0 ^ D1 ^ D2 ^ D4 ^ D6 ^ D8 ^ D10 ^ D12 ^ D16 ^ D17 ^ D18 ^ D20 ^ D22 ^ D24 ^ D26 ^ D28 CB2 D0 ^ D3 ^ D4 ^ D7 ^ D9 ^ D10 ^ D13 ^ D15 ^ D16 ^ D19 ^ D20 ^ D23 ^ D25 ^ D26 ^ D29 ^ D31 CB3 D0 ^ D1 ^ D5 ^ D6 ^ D7 ^ D11 ^ D12 ^ D13 ^ D16 ^ D17 ^ D21 ^ D22 ^ D23 ^ D27 ^ D28 ^ D29 CB4 = D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D14 ^ D15 ^ D18 ^ D19 ^ D20 ^ D21 ^ D22 ^ D23 ^ D30 ^ D31 CB5 = D8 ^ D9 ^ D10 ^ D11 ^ D12 ^ D13 ^ D14 ^ D15 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 CB6 = D0 ^ D1 ^ D2 ^ D3 ^ D4 ^ D5 ^ D6 ^ D7 ^ D24 ^ D25 ^ D26 ^ D27 ^ D28 ^ D29 ^ D30 ^ D31 4.3.2 Write Access When the processor performs a write access to an EDAC protected memory, it also outputs the 7-bit EDAC checkbits on the CB[6:0] pins (CB[7] always driven low unless EDAC testing is enabled). 4.3.3 Read Access When the processor performs a read access to an EDAC protected memory, the checkbits read together with the data are compared against checkbits generated by the EDAC from the same read data. Any discrepancy yields an error and a syndrome is computed to further qualify the error as correctable (single-bit error) or uncorrectable (double-bit error). 4.3.4 Correctable Error A single-bit error qualifies as a correctable error. The correction is performed on-the-fly inside the processor during the current access and no timing penalty is incurred. The correctable error event is reported in the fail address register (FAILAR) and in the fail status register (FAILSR). If unmasked, interrupt 1 (trap 0x11) is generated. The single-bit error remains in memory until a software-initiated rewrite is performed at the faulty memory location. 4.3.5 Uncorrectable Error A double-bit error qualifies as an uncorrectable error: an instruction_access_exception trap (0x01) is generated if an instruction fetch is in progress a data_access_exception trap (0x09) is generated if a data load is in progress ATF697FF [DATASHEET] 46 41000D−AERO03/14 Figure 4-1. EDAC overview 4.4 EDAC on 8-bit Memories EDAC protection on 8-bit memories can be performed as well. CB[7:0] is not used and the EDAC checkbits are stored in the upper part of the 8-bit memory bank where the protected data reside. When EDAC is enabled: an instruction fetch or a data load is performed as a burst of 4 read access to retrieve the 4 bytes and a 5th read access to retrieve the checkbits any word and sub-word store can be performed in RAM only byte store shall be performed in PROM The protected memory bank is partitioned as follows: lower 80% of the memory bank available as program or data memory upper 20% of the memory bank allocated to the EDAC checkbits (a maximum of 4 unusable bytes before the checkbit area) Accessing the EDAC checkbits is performed as follows: start address from the topmost byte in the same memory bank (no bank size information needed) addrcheckbits = addrbank-top ((addrdata addrbank-start) / 4) checkbits bytes allocated downwards (address bits inversion technique used) Figure 4-2. 8-bit EDAC-Protected Memory Organization ATF697FF [DATASHEET] 47 41000D−AERO03/14 4.5 EDAC Testing Operation of the EDAC can be bypassed for testing purpose and is controlled in a memory configuration register (MCFG3). 4.5.1 EDAC testing overview 4.5.2 Write Test When EDAC write bypass is enabled (MCFG3.wb = 1), the test checkbits (MCFG3.tcb) replace the EDAC generated checkbits during a data store. 4.5.3 Read Test When EDAC read diagnostic is enabled (MCFG3.rb = 1), the test checkbits (MCFG3.tcb) are updated1 with the read checkbits during a data load or an instruction fetch. Note: 1.The EDAC test routine shall be executed entirely from the instruction cache (when activated) or from an area without EDAC activated and different from the one being accessed. Otherwise the checkbits read during instruction fetch will overwrite those from the area to be tested. ATF697FF [DATASHEET] 48 41000D−AERO03/14 5. Bus exception A PROM, SRAM or I/O read/write access error can be signalled to the processor by asserting the BEXC* signal which is sampled together with the read/written data, if enabled in the memory controller (MCFG1.bexc = 1): an instruction_access_exception trap (0x01) is generated if an instruction fetch is in progress a data_access_exception trap (0x09) is generated if a data load is in progress a write_error trap (0x2B) is generated if a data store is in progress ATF697FF [DATASHEET] 49 41000D−AERO03/14 6. CACHES 6.1 Overview The ATF697FF processor implements a Harvard architecture with separate instruction and data bus, each connected to an independent cache controller. In order to improve the speed performance of the processor, multi-way caches are used to provide a faster access to instructions and data. The PROM and RAM areas, which represent most of the external memory areas, can be cached. Table 6-1. 6.2 Caching Capability Address Range Area Cacheability 0x00000000 0x1FFFFFFF PROM Cacheable 0x20000000 0x3FFFFFFF I/O Non-cacheable 0x40000000 0x7FFFFFFF RAM Cacheable 0x80000000 0x8FFFFFFF Registers Non-cacheable 0x90000000 0x9FFFFFFF DSU Non-cacheable 0xA0000000 0xFFFFFFFF PCI Non-cacheable Operation An associative cache is organized in sets, each set being divided into cache lines. Each line has a cache tag associated with it consisting of a tag field and a valid field with one valid bit for each 4-byte cache data sub-block. The cache replacement policy used for both instruction and data caches is based on the LRU algorithm: new entries are allocated in a cache until the cache is full, then least recently used entries are replaced with new entries not already present in the cache. A cache always operates in one of the three modes: disabled, enabled or frozen. 6.2.1 Disabled Mode No cache operation is performed and fetch/load requests are passed directly to the memory controller. 6.2.2 Enabled Mode On a cache miss to a cacheable location, the fetch/load request is passed to the memory controller and the corresponding tag and data line are updated with the retrieved instruction/data. Otherwise, the instruction/data is directly retrieved from the cache and forwarded to the IU/FPU. 6.2.3 Frozen Mode The cache is accessed as if it was enabled, but no new line is allocated on a cache miss. If the freeze-on-interrupt feature is activated, the corresponding cache is automatically frozen when an asynchronous interrupt is taken. This can be beneficial in real-time system to allow a more accurate calculation of worst-case execution time for an interrupt service routine (ISR). Execution of the interrupt handler will not evict any cache line so when control is returned to the interrupted task, the cache state is identical to what it was before the interrupt. If a cache was frozen by an interrupt, it can only be enabled again in software. This is typically done at the end of the interrupt service routine before control is returned to the interrupted task. ATF697FF [DATASHEET] 50 41000D−AERO03/14 6.2.4 Parity Protection Cache tag/data error protection is implemented using two parity bits per tag and per 4-byte data sub-block. The tag parity is generated from the tag value, the valid bits and the tag address. By including the tag address, it is also possible to detect errors in the cache ram address decoding logic. Similarly, the data subblock parity is derived from the subblock address and the sub-block data. The parity bits are written simultaneously with the associated tag or sub-block and checked on each access. The two parity bits correspond to the parity of odd and even tag/data bits. If a tag parity error is detected during a cache access, a cache miss is generated and the tag/data is automatically updated. All valid bits except the one corresponding to the newly loaded data are cleared. Each tag error is reported in the cache tag error counter, which is incremented until the maximum count is reached. If a data sub-block parity error occurs, a miss is also generated but only the failed sub-block is updated with fetched/loaded data. Each error is reported in the cache data error counter, which is incremented until the maximum count is reached. 6.3 Instruction Cache 6.3.1 Overview The ATF697FF processor instruction cache is implemented as a 4-way associative cache of 32 KB, organized in 4 sets of 8 KB. Each instruction cache set is divided into cache lines of 32 bytes (8 instructions). Each line has a cache tag associated with it consisting of a tag field and a valid bit field per instruction. 6.3.2 Cache Control The instruction cache operation is controlled in the cache control register (CCR): 6.3.3 operating mode is reported and can be changed (CCR.ics) cache can be frozen on interrupts (CCR.if) cache flush can be initiated (CCR.fi) pending cache flush is reported (CCR.ip) burst fetch is reported and can be activated (CCR.ib) up to 3 cache tag/data errors are reported in counters (CCR.ite and CCR.ide), which shall be cleared to register new events Operation 6.3.3.1 Instruction Fetch On an instruction cache fetch-miss to a cacheable location, an instruction (4 bytes) is loaded into the cache from external memory. 6.3.3.2 Burst Fetch If instruction burst fetch is enabled in the cache control register (CCR.ib = 1), the cache line is filled from main memory starting at the missed address and until the end of the line. At the same time, the instructions are forwarded to the IU (streaming). If the IU cannot accept the streamed instructions due to internal dependencies or a multi-cycle instruction, the IU is halted until the line fill is completed. If the IU executes a control transfer instruction during the cache line fill (Bicc/CALL/ JMPL/RETT/Ticc), the cache line fill is terminated on the next fetch. If instruction burst fetch is enabled, instruction streaming is enabled even when the cache is disabled. In this case, the fetched instructions are only forwarded to the IU and the cache is not updated. ATF697FF [DATASHEET] 51 41000D−AERO03/14 6.3.3.3 Cache Flush The instruction cache is flushed by executing the FLUSH instruction, or by activating the instruction cache flush in the cache control register (CCR.fi = 1). The flush operation takes one clock cycle per cache line and set. The IU is not halted during the cache flush but the cache behaves as if it was disabled. When the flush operation is completed, the cache resumes the state (disabled, enabled or frozen) indicated in the cache control register (CCR.ics). 6.3.3.4 Error reporting If a memory access error occurs during a line fill with the IU halted, the corresponding valid bit in the cache tag is not set. If the IU later fetches an instruction from the failed address, a cache miss will occur, triggering a new access to the failed address. If the error remains, an instruction_access_error trap (0x01) is generated. 6.4 Data Cache 6.4.1 Overview The ATF697FF processor data cache is implemented as a 2-way associative cache of 16 KB, organized in 2 sets of 8 KB. Each data cache set is divided into cache lines of 16 bytes (4 words). Each line has a cache tag associated with it consisting of a tag field and a valid bit field per word. 6.4.2 Cache Control The data cache operation is controlled in the cache control register (CCR): 6.4.3 operating mode is reported and can be changed (CCR.dcs) cache can be frozen on interrupts (CCR.df) cache flush can be initiated (CCR.fd) pending cache flush is reported (CCR.dp) cache snooping can be activated (CCR.ds) up to 3 cache tag/data errors are reported in counters (CCR.dte and CCR.dde), which shall be cleared to register new events Operation 6.4.3.1 Data Load On a data cache read-miss to a cacheable location, 1 word of data (4 bytes) is loaded into the cache from external memory. 6.4.3.2 Data Store The write policy for stores is write-through with update on write-hit and no-allocate on write-miss. An internal write buffer of three 32-bit words is used to temporarily hold store data until it is effectively written into the external device. For halfword and byte stores, the stored data is replicated into proper byte alignment for writing to a word-addressed device before being loaded into the write buffer. The write buffer is emptied prior to a load-miss/cache-fill sequence to avoid any stale data from being read into the data cache. 6.4.3.3 Cache Flush The data cache is flushed by executing the FLUSH instruction, or by activating the data cache flush in the cache control register (CCR.fd = 1). ATF697FF [DATASHEET] 52 41000D−AERO03/14 The flush operation takes one clock cycle per cache line and set. The IU is not halted during the cache flush but the cache behaves as if it was disabled. When the flush operation is completed, the cache resumes the state (disabled, enabled or frozen) indicated in the cache control register (CCR.dcs). 6.4.3.4 Cache Snooping The data cache can perform snooping on the internal bus. When snooping is enabled (CCR.ds = 1), the data cache controller monitors write accesses performed either by the PCI DMA controller, or by the PCI target controller or by the DSU communication module. When a write access is performed to a cacheable memory location, the corresponding cache line is invalidated in the data cache if present. Cache snooping has no overhead and does not affect performance. 6.4.4 Error Reporting If a memory access error occurs during a data load, the corresponding valid bit in the cache tag is set and a data_access_error trap (0x09) is generated. Since the processor executes in parallel with the write buffer, a write error may not cause an exception to the store instruction. Depending on memory and cache activity, the external memory write access may not occur until several clock cycles after the store instructions has completed. If a write error occurs, the currently executing instruction will take a write_error trap (0x2B). Caution: 6.5 The write_error trap handler shall flush the data cache since a write hit would update the cache while the memory would keep the old value due the write error. Diagnostic Cache Access Tags and data in the instruction and data cache can be accessed through ASI address space by executing LDA and STA instructions (only the least-significant nibble of the ASI field -ASI[3:0]-is used for mapping to the alternate address space). Address bits making up the cache offset are used to index the tag to be accessed while the least significant bits of the bits making up the address tag are used to index the cache set. The following table summarizes the ASI allocation on the ATF697FF processor. Table 6-2. ASI Usage ASI Usage 0x0, 0x1, 0x2, 0x3 Force cache miss (replace if cacheable) 0x4, 0x7 Force cache miss (update on hit) 0x5 Flush instruction cache 0x6 Flush data cache 0x8 User instruction (replace if cacheable) 0x9 Supervisor instruction (replace if cacheable) 0xA User data (replace if cacheable) 0xB Supervisor data (replace if cacheable) 0xC Instruction cache tags 0xD Instruction cache data 0xE Data cache tags ATF697FF [DATASHEET] 53 41000D−AERO03/14 ASI Usage 0xF Data cache data Note: Please refer to "The SPARC Architecture Manual Version 8" document for detailed information on ASI usage. The tags can be directly read/written by executing an LDA/STA instruction with ASI=0xC for instruction cache tags and ASI=0xE for data cache tags. The cache line and the cache set are indexed by the address bits making up the cache offset and the least significant bits of the address bits making up the address tag. Similarly, the data sub-blocks are read/written by executing an LDA/STA instruction with ASI=0xD for instruction cache data and ASI=0xF for data cache data.. Note: Diagnostic cache access is not possible during a cache flush operation and will cause a data_exception trap (0x09) if attempted. ATF697FF [DATASHEET] 54 41000D−AERO03/14 7. Traps and Interrupts 7.1 Overview The ATF697FF processor supports two types of traps: synchronous traps asynchronous traps also called interrupts. Synchronous traps are caused by the hardware responding to a particular instruction. They occur during the instruction that caused them. Asynchronous traps occur when an external event interrupts the processor. They are not related to any particular instruction and occur between the execution of instructions. A trap is a vectored transfer of control to the supervisor through a special trap table that contains the first four instructions of each trap handler. The trap base address (TBR) of the table is established by the supervisor and the displacement, within the table, is determined by the trap type. A trap causes the current window pointer to advance to the next register window and the hardware to write the program counters (PC & nPC) into two registers of the new window. 7.2 Synchronous Traps The ATF697FF processor follows the general SPARC trap model. The table below shows the implemented traps and their individual priority. Table 7-1. Trap Overview Trap Trap Type Priority Description reset n/a1 1 Power-on reset write_error 0x2B 2 Write buffer error instruction_access_exception 0x01 3 Error during instruction fetch Edac uncorrectable error during instruction fetch illegal_instruction 0x02 5 UNIMP or other un-implemented instruction privileged_instruction 0x03 4 Execution of privileged instruction in user mode fp_disabled 0x04 FP instruction while FPU disabled 6 Co-processor instruction while co-processor disabled 7 Instruction or data watchpoint match cp_disabled 0x24 watchpoint_detected 0x0B window_overflow 0x05 window_underflow 0x06 register_hardware_error 0x20 9 Register file uncorrectable EDAC error mem_address_not_aligned 0x07 10 Memory access to un-aligned address fp_exception 0x08 11 FPU exception 8 SAVE into invalid window RESTORE into invalid window ATF697FF [DATASHEET] 55 41000D−AERO03/14 Trap Trap Type Priority Description data_access_exception 0x09 13 Access error during load or store instruction tag overflow 0x0A 14 Tagged arithmetic overflow divide_exception 0x2A 15 Divide by zero trap_instruction 0x80 0xFF 16 Software trap instruction (Ticc) Note: 7.3 1. The reset trap is a special case of the external asynchronous trap type: the trap type field of the trap base register (TBR.tt) is never modified so if the processor goes to error mode, a post-mortem can later be conducted on what caused the error, if any. Traps Description reset A reset trap occurs immediately after the PROC_RESET* signal is deasserted. write_error An error exception occurred on a data store to memory. instruction_access_exception A blocking error exception occurred on an instruction access. illegal_instruction An attempt was made to execute an instruction with an unimplemented opcode, or an UNIMP instruction, or an instruction that would result in illegal processor state. privileged_instruction An attempt was made to execute a privileged instruction while not in supervisor mode (PSR.s = 0). fp_disabled An attempt was made to execute an FPU instruction while the FPU is not enabled. cp_disabled An attempt was made to execute a co-processor instruction (there is no co-processor). watchpoint_detected An instruction fetch memory address or load/store data memory address matched the contents of an active watchpoint register. window_overflow A SAVE instruction attempted to cause the current window pointer (CWP) to point to an invalid window in the window invalid mask register (WIM). window_underflow A RESTORE or RETT instruction attempted to cause the current window pointer (CWP) to point to an invalid window in the window invalid mask register (WIM). register_hardware_error An error exception occurred on a read only register access. A register file uncorrectable error was detected. mem_address_not_aligned A load/store instruction would have generated a memory address that was not properly aligned according to the instruction, or a JMPL or RETT instruction would have generated a non-word-aligned address. fp_exception An FPU instruction generated an IEEE-754_exception and its corresponding trap enable mask bit (FSR.tem) was set, or the FPU instruction was unimplemented, or the FPU instruction did not complete, or there was a sequence or hardware error in the FPU. The type of floating-point exception is encoded in the FPU state register (FSR.ftt). data_access_exception A blocking error exception occurred on a load/store data access. EDAC uncorrectable error. tag_overflow A tagged arithmetic instruction was executed, and either arithmetic overflow occurred or at least one of the tag bits of the operands was non zero. trap_division_by_zero An integer divide instruction attempted to divide by zero. trap_instruction A software instruction (Ticc) was executed and the trap condition evaluated to true. ATF697FF [DATASHEET] 56 41000D−AERO03/14 When multiple synchronous traps occur at the same cycle (i.e hardware errors), the highest priority trap is taken and lower priority traps are ignored. 7.4 Asynchronous Traps / Interrupts The ATF697FF processor handles up to 15 interrupts. The interrupt controller is used to prioritize and propagate interrupts requests from internal peripherals and external devices to the IU. Figure 7-1. Interrupt Controller Block Diagram 7.4.1 Operation Interrupts are controlled in the interrupt mask and priority register (ITMP): interrupts requests can be masked (ITMP.imask) so they will not trigger an interrupt interrupt requests can have a low/high priority level (ITMP.ilevel) When an interrupt request is generated, the corresponding bit is set in the interrupt pending register (ITP.ipend[]) only if the interrupt is not masked (ITMP.imask[] = 0). Then all pending interrupts are forwarded to the priority selector. The pending interrupt (ITP.ipend[]) with the highest number on the high priority level (ITMP.ilevel[] = 1) is selected and forwarded to the IU. If no pending interrupt exists with a high priority level, the pending interrupt with the highest number on the low priority level (ITMP.ilevel[] = 0) is selected and forwarded to the IU. Interrupts can also be forced by setting the corresponding bit in the interrupt force register (ITF.iforce[] = 1). Forcing is effective only if the corresponding interrupt is not masked (ITMP.imask[] = 0). A forced interrupt never shows up as pending. Pending interrupts can be cleared by setting the appropriate bit in the interrupt clear register (ITC.iclear[] = 1). When the IU acknowledges an interrupt, the corresponding pending bit is automatically cleared (ITP.ipend[] = 0) unless it was forced in the interrupt force register (ITF.iforce[] = 1). If the interrupt was forced, the IU acknowledgement rather clears the force bit (ITF.iforce[] = 0). 7.4.2 Interrupts List The following table presents the interrupts assignment: ATF697FF [DATASHEET] 57 41000D−AERO03/14 Table 7-2. 7.4.3 Interrupt Overview Interrupt Trap Type Source 15 0x1F I/O interrupt 71 14 0x1E PCI 13 0x1D I/O interrupt 6 12 0x1C I/O interrupt 5 11 0x1B DSU trace buffer 10 0x1A I/O interrupt 4 9 0x19 Timer 2 8 0x18 Timer 1 7 0x17 I/O interrupt 3 6 0x16 I/O interrupt 3 5 0x15 I/O interrupt 1 4 0x14 I/O interrupt 0 3 0x13 UART 1 2 0x12 UART 2 1 0x11 Hardware error2 Note: 1. Interrupt 15 cannot be filtered by the processor interrupt level in the IU (PSR.pil) and shall be used with care. Note: 2. Interrupt 1 is triggered each time a new hardware error is reported (FAILAR.hed) so the application ultimately knows about any hardware error that was detected (bus exception, write protection error, EDAC correctable and uncorrectable external memory error, PCI initiator error or PCI target error). I/O Interrupts As an alternate function of the general purpose interface, the ATF697FF processor can handle interrupts from external devices. Up to 8 external interrupts can be programmed at the same time. The external interrupts are assigned to interrupt 4, 5, 6, 7, 10, 12, 13 and 15. There are two registers for configuring I/O interrupts: IO interrupt 0, 1, 2 and 3 are controlled by IOIT1 IO interrupt 4, 5, 6 and 7 are controlled by IOIT2 Each I/O interrupt is controlled through 4 parameters in the appropriate configuration register (n = 1 & x in [0:3] or n = 2 & x in [4:7]): the interrupt can be enabled or disabled (IOITn.enx) the interrupt source can be chosen among GPIO[15:0] and D[15:0]1(IOITn.iselx) the interrupt can be level-triggered2 or edge-triggered2 (IOITn.lex) the interrupt polarity can be high/low2 when level-triggered or rising/falling2 when edge-triggered (IOITn.plx) Note: 1. D[15:0] can be used as part of the general-purpose I/O interface only when all the memory areas (ROM, SRAM & I/O) are 8-bit wide and the SDRAM interface is not enabled. ATF697FF [DATASHEET] 58 41000D−AERO03/14 Note: 2. Whatever the chosen trigger mode, the I/O inputs are sampled on the rising edge of the system clock. If generated synchronously, the signal driving the I/O interrupt shall meet the required setup and hold constraints (see "Electrical Characteristics"). If generated asynchronously, the signal driving the I/O interrupt shall be maintained for a minimum of 1.5 clock cycles so at least 1 active sample can be made. The following table summarizes the I/O interrupt trigger configurations. Table 7-3. I/O Interrupt Trigger Configuration IOITn.lex IOITn.plx Trigger 0 0 low level 0 1 high level 1 0 falling edge 1 1 rising edge ATF697FF [DATASHEET] 59 41000D−AERO03/14 8. TIMER The timer unit implements two 32-bit timers, one 32-bit watchdog and one 10-bit shared prescaler. 8.1 Prescaler The prescaler is an internal device shared by the two timers and the watchdog. Figure 8-1. Prescaler Block Diagram The prescaler operation is controlled by two registers (SCAC and SCAR): the prescaler is always enabled the counter (SCAC.cnt) is clocked by the system clock and decremented on each clock cycle the counter is reloaded from the prescaler reload register (SCAR.rl) after it underflows and a tick pulse is generated for the two timers and the watchdog after reset, the prescaler counter & reload registers are initialized to the minimum division rate The effective division rate is therefore equal to the prescaler reload register value + 1. The two timers and the watchdog share the same decrementer, so the minimum possible prescaler division rate is 4 to allow processing of the two timers and the watchdog. ATF697FF [DATASHEET] 60 41000D−AERO03/14 8.2 Timer 1 & Timer 2 Timer1 and Timer2 are two general purpose 32-bit timers. They share the same decrementer with the watchdog. Figure 8-2. Timer 1/2 Block Diagram Each timer n operation is controlled by a dedicated set of timer control registers (TIMCTRn, TIMRn and TIMCn): a timer can be enabled/disabled (TIMCTRn.en) the counter (TIMCn.cnt) is decremented each time the prescaler generates a tick pulse the counter can be manually loaded (TIMCTRn.ld) from the reload register (TIMCTRn.rv) the counter can be configured to stop or to automatically reload (TIMRn.rl) after it underflows Each time a timer underflows, a timer-dedicated interrupt is generated (ITP.ipend[]) if unmasked in the interrupt mask and priority register (ITMP.mask[]). ATF697FF [DATASHEET] 61 41000D−AERO03/14 8.3 Watchdog The watchdog is a specific 32-bit timer (decrementer shared with Timer1 and Timer2). Figure 8-3. Watchdog Block Diagram The watchdog is accessible through a single watchdog register (WDG): the watchdog is always enabled the counter (WDG.cnt) is decremented each time the prescaler generates a tick pulse unless it has reached zero the WDOG* signal is asserted when the counter expires at zero (no other internal event generated) the counter never underflows and shall be refreshed by directly reloading a value into the counter after reset, the watchdog counter is initialized to the maximum possible value1 Note: 1. Considering the prescaler is initialized to the minimum value after a reset (a division rate of 4), the watchdog will expire after (232 1)×4 cycles, unless later programmed otherwise. The watchdog can be used to generate a system reset on expiration by directly connecting the WDOG* open-drain output pin to the PROC_RESET* pin. ATF697FF [DATASHEET] 62 41000D−AERO03/14 9. UART The Universal Asynchronous Receiver and Transmitter (UART) is a highly flexible serial communication module. The ATF697FF processor implements two uarts: UART1 and UART2. UARTs on the processor are defined as alternate functions of the general purpose interface (GPI). 9.1 Overview Each UART n operates independently and is fully controlled by a set of 4 registers: a control register (UACn) a status register (UASn) a scaler register (UASCAn) a data register (UADn) Figure 9-1. UART Block Diagram 9.1.1 Data Frame A data frame consists in a start bit, 8 data bits, an optional parity bit and a stop bit. Figure 9-2. Data Frames Parity in a data frame is controlled as follows: the parity can be enabled or disabled (UACn.pe) ATF697FF [DATASHEET] 63 41000D−AERO03/14 when enabled (UACn.pe = 1), the parity can be even or odd (UACn.ps) When even (UACn.ps = 1), the parity bit is generated such as the number of 1s in the data and the parity is even. When odd (UACn.ps = 0), the parity bit is generated such as the number of 1s is odd. 9.1.2 Baud-Rate The internal baud-rate generator requires a clock source to operate, which can either be internal or external (UACn.ec). 9.1.2.1 Internal Clock When configured for internal clock (UACn.ec = 0), the UART baud-rate comes from a programmable 12-bits scaler controlled by a configuration register (UASCAn): the scaler is enabled only when the UART transmitter (UACn.te = 0) and/or the UART receiver (UACn.re = 0) are enabled when enabled (UACn.te = 1 and/or UACn.re = 1), the scaler counter is clocked by the system clock and decremented on each clock cycle the scaler counter is reloaded from the scaler reload register (UASCAn.rv) after it underflows and a UART tick is generated for the transmitter and the receiver (tick frequency is 8 times the desired baud-rate) The following equations shall be used to calculate the scaler value or the baudrate value based on the clock frequency: variable description: 9.1.3 sdclkfreq: internal clock frequency baudrate: targeted/resulting baud rate scalerrv: resulting/targeted scaler reload value External Clock When configured for an external clock (UACn.ec = 1), the UART scaler is bypassed and GPIO[3] directly provides the UART tick to the transmitter and the receiver (tick frequency is 8 times the desired baud-rate). The external clock frequency shall be 8 times the desired baud-rate. When configured for an external clock source, the clock high and low time on GPIO[3] shall each be longer than the period of the internal system clock (so proper sampling is achieved). 9.1.4 Double Buffering Each UART performs double-buffering (a holding register and a shift register) on the transmitter and the receiver to optimize the data transfer in both directions (no transmitter stopped waiting for reload, no data loss on receiver overrun). 9.1.5 Hardware Flow-Control Each UART n can perform hardware flow-control to further optimize and secure data transfer in both directions: hardware flow-control can be enabled or disabled (UACn.fl) when enabled (UACn.fl = 1) together with the transmitter (UACn.te = 1), no new data transmit is initiated until the clear-to-send input pin (CTSn) is asserted (data transmission is not interrupted is deasserted in the middle of the transmission) when enabled (UACn.fl = 1) together with the receiver (UACn.re = 1), the request-to-send output pin (RTSn) is asserted as long as new data can be received ATF697FF [DATASHEET] 64 41000D−AERO03/14 9.1.6 Noise Filtering The serial input is shifted through an 8-bit filter which changes output only when all bits in the filter have the same value, effectively forming a low-pass filter with a cut-off frequency of 1/8 system clock. 9.2 Operation 9.2.1 Transmitter Operation UART n transmitter is first configured as follows: the transmitter shall be enabled (UACn.te = 1) the transmitter serial-output pin (TXn) shall be enabled on the general-purpose interface by configuring the appropriate pin to output mode (GPIO[15] for UART1 and GPIO [11] for UART2) if flow-control is enabled (UACn.fl = 1), the transmitter clear-to-send pin (CTSn) shall be enabled on the generalpurpose interface by configuring the appropriate pin to input mode (GPIO[12] for UART1 and GPIO[8] for UART2) When ready to transmit, data written to the transmitter holding register (UADn.rtd) is transferred into the transmitter shift register and converted to a serial data frame on the transmitter serial output pin (TXn). Following the transmission of the stop bit, the transmitter serial data output remains high and the transmitter shift register empty flag is asserted (UASn.ts = 1) if no new data is available in the transmitter holding register. Transmission resumes and the transmitter shift register empty flag is deasserted (UASn.ts = 0) when new data is loaded in the transmitter holding register (UADn.rtd). 9.2.2 Receiver Operation UART n receiver is first configured as follows: the receiver shall be enabled (UACn.re = 1) the receiver serial-input pin (RXn) shall be enabled on the general-purpose interface by configuring the appropriate pin (GPIO[14] for UART1 and GPIO[10] for UART2) to input mode if flow-control is enabled (UACn.fl = 1), the receiver request-to-send pin (RTSn) shall be enabled on the generalpurpose interface by configuring the appropriate pin (GPIO[13] for UART1 and GPIO[9] for UART2) to output mode The receiver constantly looks for the high to low transition of a start bit on the receiver serial data input pin (RXn). If a transition is detected, the state of the serial input is sampled a half-bit later for confirmation and a valid start bit is assumed if the serial input is still low, otherwise the search for a valid start bit continues. Then the receiver continues to sample the serial input at one bit time intervals (at the theoretical centre of the bit) until the proper number of data bits and optionally the parity bit have been assembled and one stop bit has been detected. The data is transferred to the receiver holding register and the data ready flag is asserted (UASn.dr = 1) by the end of the reception if no error was detected. Otherwise, no data ready flag is asserted and the error is reported in the appropriate flag: a parity error (UASn.pe = 1) occurs when parity is enabled (UACn.pe = 1) and the received parity does not match the selected parity configuration (UACn.ps) a framing error (UASn.fe = 1) occurs when the received stop bit is a 0 rather than a 1 a break received (UASn.br = 1) occurs when the received data and the stop bit are all 0s an overrun error (UASn.ov = 1) occurs when the holding register already contains an un-read data Caution: The errors bits are never cleared by the receiver and shall be cleared in software so new errors can later be detected. Reading the UART data register (UADn.rtd) empties the receiver holding register and deasserts the data ready flag (UASn.dr = 0). ATF697FF [DATASHEET] 65 41000D−AERO03/14 9.2.3 Interrupt Generation Each UART n can be configured to generate an interrupt each time a byte has been received and/or is about to be sent: transmitter interrupt can be enabled/disabled (UACn.ti) receiver interrupt can be enabled/disabled (UACn.ri) Note: When enabled (UACn.ti = 1), the transmitter issues an interrupt when the transmitter holding register is emptied (transfer into the transmitter shift register for sending). When enabled (UACn.ri = 1), the receiver issues an interrupt after serial data has been received (data made ready into the receiver holding register or errors reported). The interrupt is made effective (ITP.ipend[3] for UART1 and ITP.ipend[2] for UART2) only if unmasked in the interrupt mask and priority register (ITP.imask[3] for UART1 and ITP.imask[2] for UART2). 9.2.4 Loop-Back Mode Each UART n can be configured in loop-back mode (UACn.lb) for testing purpose. When enabled1(UACn.lb = 1), the transmitter serial-output2 is internally connected to the receiver serial-input3 and the receiver request-to send output4 is internally connected to the transmitter clear-to-send input5. Note: 1. In loop-back mode, the corresponding general-purpose I/O pins need not be configured since all the connections are directly performed internally. Note: 2. If the transmitter is enabled and the corresponding general purpose I/O pin (TXn) is configured as an output, a constant 1 is output instead of the programmed I/O data. Note: 3. No parity error or framing error or break received can be generated since the transmitter and the receiver both share the same parity and baud-rate configuration. Note: 4. If flow-control is enabled and the corresponding general purpose I/O pin (RTSn) is configured as an output, a constant 1 is output instead of the programmed I/O data. Note: 5. No overrun error can be generated if flow-control is enabled. ATF697FF [DATASHEET] 66 41000D−AERO03/14 10. GPIO 10.1 Processor General Purpose Interface The general purpose interface (GPI) consists in a partially bit-wise programmable 32-bit I/O port with alternate facilities. 10.1.1 GPI as a 32-bit I/O Port The port is split in two parts the lower 16-bits are accessible via the GPIO[15:0] pins while the upper 16-bits are accessible via D[15:0] and can only be used when all the external memory areas (ROM, SRAM and I/O) are in 8-bit mode (see “8-bit PROM and SRAM Access”). If the SDRAM controller is enabled, the upper 16-bits cannot be used. 10.1.1.1 Lower 16-bits Operation The lower 16 bits of the I/O port can be individually programmed as output or input, they are accessible through GPIO[15:0]. Each pin n in GPIO[15:0] is controlled by two registers (IODIR and IODAT): the pin can be configured as an input or an output (IODIR.piodir[n]) when configured as an input (IODIR.piodir[n] = 0), the bit value in the data register (IODAT.piodat[n]) continuously reflects the pin value when configured as an output (IODIR.piodir[n] = 1), the bit value in the data register (IODAT.piodat[n]) is continuously output on the pin Figure 10-1. I/O Port Block Diagram GPIO[15:0] 10.1.1.2 Upper 16-bits Operation The upper 16 bits of the I/O port can only be configured as outputs or inputs on a byte basis. D[15:8] is referenced as the medium byte while D[7:0] is referenced as the lower byte. Each byte in D[15:0] is controlled by 2 registers (IODIR and IODAT): the whole byte can be configured as an input or an output (IODIR.meddir and IODIR.lowdir) when configured as an input (IODIR.meddir = 0 and/or IODIR.lowdir = 0), the byte value in the data register (IODAT.meddat and IODAT.lowdat) continuously reflects the corresponding pins byte value when configured as an output (IODIR.meddir = 1 and/or IODIR.lowdir = 1), the byte value in the data register (IODAT.meddat and IODAT.lowdat) is continuously output on the corresponding byte pins ATF697FF [DATASHEET] 67 41000D−AERO03/14 Figure 10-2. I/O Port Block Diagram D[15:0] 10.1.2 GPI Alternate Functions Most GPI pins have alternate functions in addition to being general I/O. Facilities like serial communication link, interrupt input and configuration are made available through these functions. The following table summarizes the assignement of the alternate functions. Table 10-1. GPI alternate functions GPI port pin Alternate function GPIO[15] TXD1 UART1 transmitter data13 GPIO[14] RXD1 UART1 receiver data24 GPIO[13] RTS1 UART1 request-to-send145 GPIO[12] CTS1 UART1 clear-to-send235 GPIO[11] TXD2 UART2 transmitter data13 GPIO[10] RXD2 UART2 receiver data24 GPIO[9] RTS2 UART2 request-to-send145 GPIO[8] CTS2 UART2 clear-to-send235 GPIO[3] EXTCLK Use as alternative UART clock2 GPIO[2] PROM EDAC enable Enable EDAC protection on boot6 GPIO[1:0] PROM width Defines PROM data bus width on boot6 Note: 1. The corresponding GPI port pin shall be configured in output mode so the UART output signal is effective on that pin. Note: 2. The corresponding GPI port pin shall be configured in input mode so the UART input signal is effective on that pin. Note: 3.The corresponding UART transmitter shall be enabled Note: 4.The corresponding UART receiver shall be enabled Note: 5.Flow-control shall be enabled on the corresponding UART Note: 6.Pin is sampled during reset and can be used as a general purpose I/O pin after reset ATF697FF [DATASHEET] 68 41000D−AERO03/14 In addition to these alternate functions, each GPI interface pin can be configured as an interrupt input to catch interrupts from external devices. Up to eight interrupts can be configured on the GPI interface by programming the I/O interrupt registers (IOIT1 and IOIT2). For a detailed description about the external interrupts configuration, please refer to the “Traps and Interrupts” section. The GPIO0 to GPIO7 are shared internally between the processor and the reconfigurable unit and are also connected externally. The GPIO8 to GPIO15 are only connected to the processor. Caution: 10.2 Warning: The shared IOs have to be correctly configurated to avoid signal reflexions and damages on the IO of the ATF697FF component. In particular, severals outputs on the same IO should not be configurated in output at the same time. Reconfigurable Unit General Purpose Interface The ATF697FF reconfigurable unit provides a full set of highly configurable general purpose IOs. For some of the FPGA IOs, the general purpose function of the IO is multiplexed with other functions such as mentioned in the Pin Description section. Please refer to the Pin Description section for details on the multiplexed functions of each IO. It must be noted that while the configuration logic controls dual-use I/O pins during the configuration download lifephase, the configuration logic does not control the general purpose configuration. Figure 10-3. Dual Use I/O principle Caution: The user must be cautioned to avoid possible system problems with the use of dual-use I/O pins. For example, turning off the internal pull-up resistor for the open drain INIT pin would not apply the weak High required of an open drain driver. Conversely, disabling the pull -up and enabling the pull-down of the HDC pin might be a good idea, since the user may then actually see the pin go Low at the end of configuration. Dual-use pins share input buffers. It should be noted that even when the configuration has claimed a pin for its own purposes, the user input buffer is still fully functional. This implies that any user logic tied to the input buffers of the pins in question will remain operational. Each programmable I/O can be configured as input, output or bi-directional. When configured as input an optional Schmitt trigger can be enabled on the I/O. When configured as output, optional PCI compatibility can be enabled. It is also possible to select the output buffer drive to optimize the performance of an interface in the application. In addition, the ATF697FF reconfigurable unit provides pull-up and pull-down capability on each I/O. ATF697FF [DATASHEET] 69 41000D−AERO03/14 Here is an overview of the IO structure. Figure 10-4. ATF697FF reconfigurable unit I/O structure Vcc DRIVE Rst Pull-Up TRI-STATE OCLK From FPGA Core Pad To FPGA Core Pull-Down TTL/CMOS SCHMITT Rst DELAY ICLK Gnd The following section presents all the possible configurations available for a programmable I/O. 10.2.1 Direction Configuration Each of the general purpose IO can be individually configured in one of the following direction: Input, Output, Bidirectional. 10.2.2 Pull-up/Pull-down Each pad has a programmable pull-up and pull-down attached to it. This supplies a weak “1” or “0” level to the pad pin. When all other drivers are off, this control will dictate the signal level of the pad pin. The pull-up and pull-down configuration is independent from any other configuration of the pad. The consequence is that it is possible to use the pull-up/pull-down configuration together with any of the other IO configuration. The pull-up/pull-down configuration is available both for inputs and outputs. Caution: By default, when an IO is not configured in the application bitstream of the FPGA, the IO pull -up is activated 10.2.3 Output Configuration The ATF697FF reconfigurable unit proposes a full set of configuration for the output management. Here are the descriptions for all the available settings. 10.2.3.1 Standard Configuration In standard configuration, the IOs in output mode support a tri-state configuration. It is then possible to drive low level (logical 0) high level (logical 1) high impedance (logical Z) 10.2.3.2 Open Source When configured in open source mode the IOs configured in output can only support ATF697FF [DATASHEET] 70 41000D−AERO03/14 high level (logical 1) high impedance (logical Z) Note: In such a configuration, it is possible to drive a weak “0” by using the internal pull-down capability of the driver 10.2.3.3 Open Drain When configured in open drain mode the IOs configured in output can only support low level (logical 0) high impedance (logical Z) Note: In such a configuration, it is possible to drive a weak “1” by using the internal pull-up capability of the driver 10.2.3.4 Output drive On the ATF697FF reconfigurable unit , the output drive of each I/O configured in output is programmable. The drive capability is dependent upon the settings of the drive parameter inside the bitstream of the FPGA (FAST, MEDIUM and SLOW). Three values are available for configuration of the drive for each output: FAST When configured in FAST mode, the output buffer is capable to drive a high level of current. Such drive capability leads to fast slew rate whatever is the load on the pin Note: In this mode, the current drive is compliant with the PCI specification. MEDIUM When configured in MEDIUM mode, the output buffer is capable to drive an intermediate level of current. SLOW When configured in SLOW mode, the output buffer is capable to drive a small level of current. Such drive capability leads to slow slew rate as soon as the load is important. SLOW configuration yields to standard buffer usage. Table 10-2. Drive Capability for VCC = 3.3V VCC=3.3V Config SLOW MEDIUM FAST Caution: IOH (mA) Worst Case 4 10 14 Typical 8 17 22 IOL (mA) Worst Case 4 10 14 Typical 9 23 28 When no modification is performed by the user on the IDS software, the default configuration of the drive for the I/Os is FAST. 10.2.4 Input Configuration 10.2.4.1 Schmitt A Schmitt trigger circuit can be enabled on the inputs. The Schmitt trigger is a regenerative comparator circuit that adds 0.8V hysteresis to the input. This effectively improves the rise and fall times (leading and trailing edges) of the incoming signal and can be useful for filtering out noise. 10.2.4.2 Delays The input buffer can be programmed to include four different intrinsic delays as specified in the AC timing characteristics. This feature is useful for meeting data hold requirements for the input signal. ATF697FF [DATASHEET] 71 41000D−AERO03/14 10.3 LVDS Interfaces The ATF697FF provides 16 pairs of LVDS IOs that comply with the EIA-644 standard requirements. The basic LVDS interface consists in a single differential link interconnected between a transmiter and a receiver. Such a link requires a termination resistor on the receiver side to allow high frequency transfer usage. The nominal resistor value for the termination resistor 100 ohms. Figure 10-5. LVDS basic interface The LVDS I/Os embedded on the ATF697FF are composed of 4 LVDS transceiver (Tx) pairs, 4 receivers (Rx) pairs together with the reference voltages (LVDS_REF_A and LVDS_REF_B). that must be connected to an accurate 1.25V voltage to give references to the transceivers and to the receivers. They are spread in 2 clusters, each one consisting in 2x transceivers 2x receivers 1x reference voltage. Figure 10-6. LVDS bidirectional communication principle The LVDS_REF_B is the reference voltage for LVDSB1 and LVDSB2. The LVDS_REF_A is the reference voltage for LVDSA1 and LVDSA2. ATF697FF [DATASHEET] 72 41000D−AERO03/14 11. ATF697FF reconfigurable unit: 11.1 Operating Modes / Lifephases The ATF697FF reconfigurable unit behaves following a deterministic life cycle. The complete life cycle of the FPGA refers to an optimized number of lifephases that are summarized in the following life cycle. Figure 11-1. ATF697FF reconfigurable unit: Life Cycle diagram Manual Reset Power On Reset Power-On Reset Manual Reset FPGA Booting Clear Cycle Ended Mode Sampling Other mode than Mode 0 sampled Mode 0 sampled Idle Configuration Download Configuration Download Ended Configuration Download Started by CON driving Run For some of the FPGA IOs, the general purpose function of the IO is multiplexed with other functions such as configuration function, clock function… as mentioned in the Pin Description section. For the multiplexed IOs, the function that is activated at a given time is directly dependent from the lifephase currently executed. In each of the lifephase description here after, the multiplexed IO function availability is presented. ATF697FF [DATASHEET] 73 41000D−AERO03/14 11.1.1 Power-On Reset 11.1.1.1 Description This Power-On Reset lifephase occurs when power is first applied to the part. The FPGA initiates a complete clearing of its internal configuration SRAM (configuration clear cycle) prior entering in Mode Sampling lifephase. Before performing the configuration clear cycle, the power supply is sensed until the threshold voltage is reached then the internal logic activates. In order to ensure the power supply stability to erase properly each configuration SRAM point, the ATF697FF reconfigurable unit loops and perform configuration clear cycle during hardcoded silicon timing. 11.1.1.2 Pin Function Availability Table 11-1. Pin Function during Power-On Reset ATF697FF reconfigurable unit Pin names Lifephase = Power-On Reset FPGA_RESET* M0, M1, M2 IO303_INIT CON CCLK IO713_D0 IO259_LDC IO265_HDC IO547_CS0 IO720_GCK6_CSOUT IO655_CHECK* IO225_OTS* IOx IOx_GCKy IOx_FCKy [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 Notes: 1. During Power-On Reset lifephase, the ATF697FF reconfigurable unit configuration SRAM is not configured, all GPIO functions remain in input with pull-up (by default). ATF697FF [DATASHEET] 74 41000D−AERO03/14 11.1.2 Manual Reset 11.1.2.1 Description This Manual Reset lifephase occurs when the RESET function is activated by the user. The FPGA initiates a configuration clear cycle prior entering Mode Sampling lifephase when RESET function is released. As power supplies are already stable, the configuration clear cycle is done once and takes a time which depends of the silicon intrinsic speed and the size of the FPGA matrix. 11.1.2.2 Pin Function Availability Table 11-2. Pin Function during Manual Reset ATF697FF reconfigurable unit Pin names Lifephase = Manual Reset FPGA_RESET* M0, M1, M2 IO303_INIT CON CCLK IO713_D0 IO259_LDC IO265_HDC IO547_CS0 IO720_GCK6_CSOUT IO655_CHECK* IO225_OTS* IOx IOx_GCKy IOx_FCKy [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 Notes: 1. During Manual Reset lifephase, the ATF697FF reconfigurable unit configuration SRAM is not configured, all GPIO functions remain in input with pull-up (by default). ATF697FF [DATASHEET] 75 41000D−AERO03/14 11.1.3 Mode Sampling 11.1.3.1 Description This Mode Sampling lifephase is entered each time the FPGA has performed either Power-On-Reset or Manual Reset lifephases. In this state, the FPGA starts to drive the configuration logic interface approprietaly and samples the mode pins. Depending on the values sampled through the mode pins, the ATF697FF reconfigurable unit can be configured in the following modes: Mode 0: Master Serial Mode Mode 1: Slave Serial Mode with the use of a chip select input Mode 7: Slave Serial Mode These modes directly affect the Configuration Download lifephase and lead to five different contexts for these these lifephase. 11.1.3.2 Pin Function Availability Table 11-3. Pin Function Mode Sampling ATF697FF reconfigurable unit Pin names Lifephase = Mode Sampling FPGA_RESET* M0, M1, M2 IO303_INIT CON CCLK IO713_D0 IO259_LDC IO265_HDC IO547_CS0 IO720_GCK6_CSOUT IO655_CHECK* IO225_OTS* IOx IOx_GCKy IOx_FCKy [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 Notes: 1. During Manual Reset lifephase, the ATF697FF reconfigurable unit configuration SRAM is not configured, all GPIO functions remained in input with pull-up (by default). ATF697FF [DATASHEET] 76 41000D−AERO03/14 11.1.4 Idle 11.1.4.1 Description This Idle lifephase is entered when the FPGA does no activitie. The FPGA enters in this state after Mode Sampling state when configured in slave mode. In Idle state, the configuration logic interface is released. 11.1.4.2 Pin Function Availability Table 11-4. Pin Function during Idle ATF697FF reconfigurable unit Pin names Lifephase = Idle FPGA_RESET* M0, M1, M2 IO303_INIT CON CCLK IO713_D0 IO259_LDC IO265_HDC IO547_CS0 IO720_GCK6_CSOUT IO655_CHECK* IO225_OTS* IOx IOx_GCKy IOx_FCKy [CFG] [CFG] [GPIO]1 [CFG] [CFG] [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 [GPIO]1 Notes: 1. During Idle lifephase, the ATF697FF reconfigurable unit configuration SRAM is not configured, all GPIO functions remained in input with pull-up (by default). ATF697FF [DATASHEET] 77 41000D−AERO03/14 11.1.5 Configuration Download 11.1.5.1 Description This Configuration Download lifephase from a system point of view is a sequence of event managed by the FPGA in order to ensure the configuration of its internal SRAM. This lifephase is entered after Mode Samping state when configured in master mode. Else the FPGA enters this lifephase after Idle state when an external master triggers the start of configuration download (could be either in slave or master mode). Five different contexts are defined for this lifephase regarding the mode sampled in Mode Sampling. 11.1.5.2 Pin Function Availability Table 11-5. Pin Function during Configuration Download ATF697FF reconfigurable unit Pin names Lifephase = Configuration Download Mode 0 Mode 1 Mode 7 FPGA_RESET* M0, M1, M2 IO303_INIT CON CCLK IO713_D0 IO259_LDC IO265_HDC IO547_CS0 IO720_GCK6_CSOUT IO655_CHECK* IO225_OTS* IOx IOx_GCKy IOx_FCKy [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [GPIO]1 [CFG] or [GPIO]2 [CFG] or [GPIO]2 [CFG] or [GPIO]2 [GPIO]1 [GPIO]1 [GPIO]1 [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] or [GPIO]3 [CFG] or [GPIO]3 [CFG] or [GPIO]3 [GPIO]1 [GPIO]1 [GPIO]1 [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [CFG] [GPIO]1 [CFG] or [GPIO]3 [CFG] or [GPIO]3 [CFG] or [GPIO]3 [GPIO]1 [GPIO]1 [GPIO]1 Note: 1. If entering Configuration lifephase from Idle then the ATF697FF reconfigurable unit configuration SRAM is not configured: all GPIO functions remained in input with pull-up (by default). Else if entering Configuration lifephase from Run then the ATF697FF reconfigurable unit configuration SRAM is already configured: all GPIO functions remained in their configured state. Note: 2. IO720_GCK6_CSOUT, IO655_CHECK* and IO225_OTS* are configured in [CFG] function during configuration download if the appropriate function is activated (respectively cascading mode, CHECK function, Output Tri-State) (Refer to bitstream configuration for more details) Note: 3. IO720_GCK6_CSOUT, IO655_CHECK* & IO225_OTS* are configurated in [CFG] function during configuration download if the appropriate function is activated (respectively cascading mode, CHECK function, Output tri state). 11.1.6 Run 11.1.6.1 Description The Run lifephase is the operating state of the FPGA and is design dependent. It means that in this lifephase, the loaded design runs and its own lifephases are taken into account. ATF697FF [DATASHEET] 78 41000D−AERO03/14 11.1.6.2 Pin Function Availability Table 11-6. Pin Function during Run ATF697FF reconfigurable unit Pin names Lifephase = Run Nominal OTS CSIC Free Run oscillator FPGA_RESET* M0, M1, M2 IO303_INIT CON CCLK IO713_D0 IO259_LDC IO265_HDC IO547_CS0 IO720_GCK6_CSOUT IO655_CHECK* IO225_OTS* IOx IOx_GCKy IOx_FCKy [CFG] [CFG] [GPIO] [CFG] [CFG] [GPIO] [GPIO] [GPIO] [GPIO] [GPIO]or[CLOCK] [GPIO] [GPIO] [GPIO] [GPIO]or[CLOCK] [GPIO]or[CLOCK] [CFG] [CFG] [GPIO] [CFG] [CFG] [GPIO] [GPIO] [GPIO] [GPIO] [GPIO]or[CLOCK] [GPIO] [CFG] [GPIO] [GPIO]or[CLOCK] [GPIO]or[CLOCK] [CFG] [CFG] [CFG] [CFG] [CFG] [GPIO] [GPIO] [GPIO] [GPIO] [GPIO]or[CLOCK] [GPIO] [GPIO] [GPIO] [GPIO]or[CLOCK] [GPIO]or[CLOCK] [CFG] [CFG] [GPIO] [CFG] [CFG]1 [GPIO] [GPIO] [GPIO] [GPIO] [GPIO]or[CLOCK] [GPIO] [GPIO] [GPIO] [GPIO]or[CLOCK] [GPIO]or[CLOCK] Notes: 1. When using the Free Run Oscillator in mode 0 only (refer to Register section about CR13), the CCLK pin is output as clock signal. The user shall take care of this at system level. ATF697FF [DATASHEET] 79 41000D−AERO03/14 11.2 Configuration Download Configuration is the process by which a design is loaded into an ATF697FF reconfigurable unit. The ATF697FF reconfigurable unit is a SRAM based FPGA, this leads to an unlimited reprogrammability capability. It is possible to configure either the entire device or only a portion of the device. Sections can be configured while others continue to operate undisturbed. The architecture of the ATF697FF reconfigurable unit leads to a maximum bitstream size of 2.5M bits. It is possible to store configuration bit-streams of the ATF697FF reconfigurable unit in one single 4Mbit EEPROM. Full configuration takes only milliseconds. Partial configuration takes even less time and is a function of design density. Configuration data is transferred to the device in one of the five modes supported by the ATF697FF reconfigurable unit. Three dedicated input pins M0, M1 and M2 are used to determine the configuration mode. The ATF697FF reconfigurable unit supports an auto-configuring Master serial mode and two Slave serial modes. The following table summarizes the ATF697FF reconfigurable unit configuration modes: Table 11-7. Configuration Mode Overview Configuration Download Mode Mode Description M2 M1 M0 CCLK Data 0 1 7 Master serial Slave serial Slave serial 0 0 1 0 0 1 0 1 1 Output Input Input Serial Serial Serial ATF697FF [DATASHEET] 80 41000D−AERO03/14 11.2.1 Serial Configuration 11.2.1.1 Bitstream Structure The configuration bitstream for the ATF697FF reconfigurable unit consists in a flexible structured set of data that allows configuration of the FPGA structure but also protection of the configuration data link. The following table shows the global structure of a bitstream for ATF697FF reconfigurable unit. Table 11-8. ATF697FF reconfigurable unit Bitstream structure Bitstream decomposition Description Null byte Preamble Configuration Registers Sub Zone CR3 CR2 CR1 CR0 4 Start Address Stop Address Data Start Address Stop Address Data Start Address Stop Address Data Start Address Stop Address Data Start Address Stop Address Data 2 3 3 Data Size 3 3 Data Size 3 3 Data Size 3 3 1 3 3 1 1 Number of Windows Data Window1 Data Window2 Data WindowN 1 Checksum Recurrent Checksum 2 Postamble Zone Size (byte) 1 1 Note: 1. N could be at least 1, at maximum 65535. Note: 2. Optional: the Recurrent Cheksum is integrated to the bitstream by IDS by activating the appropriate option (CR8 in configuration Register) ATF697FF [DATASHEET] 81 41000D−AERO03/14 Null Byte The “null byte” is always present in the ATF697FF reconfigurable unit bitstreams. It is used by the configuration download state machine as a download protocol start indicator. Its value is always “00000000”. Preamble The “preamble” is always present in the ATF697FF reconfigurable unit bitstreams. It is used by the configuration download state machine for verifying that the bitstream proposed on the configuration link is well suited for ATF697FF reconfigurable unit FPGA type. Its value is always set to “10110111” Configuration Register The configuration register is made of four eight-bit wide registers used to configure the FPGA embedded functions. These register allows configuration of FPGA functions such as clock configuration, IO configuration… options. For the details on the configuration register options content, please refer to the Registers section. The configuration registers are always present in the ATF697FF reconfigurable unit bitstreams. Number of Windows The number of windows section provides the exact number of windows used in the bitstream to be downloaded. Its value is computed by the FPGA Integrated Design System development tool and is fully dependent from the content of the FPGA application. The number of windows is always present in an ATF697FF reconfigurable unit bitstream. Data Window The windows are the zones used to configure the different internal applicative structures of the FPGA. Each window is e made of the following elements: A “Start Address” which is a 24 bits word (3 bytes). It is used to identify the starting point of the FPGA configuration SRAM mapping to be written A “Stop Address” which is a 24 bits word (3 bytes). It is used to delimit the end of the window, thus defining the number of data to be written in the configuration SRAM The “Data” section which contains the configuration data for the configuration memory itself. It is fully dependent upon the application being downloaded. The ATF697FF bitstream always embeds a minimum of one data windows. Checksum Window The FPGA Integrated Design System development tool calculates a checksum for each generated bitstream in order to provide the capability to secure the transfer of the data during configuration download. The checksum generated is one byte computed by data accumulation over the configuration registers data and the data of all the windows that precede the checksum window. The checksum window is used to store this checksum into the FPGA at a defined location. That is why the checksum window is made of: A “Start Address” which is a 24 bits word (3 bytes). This address defines the location where the checksum will be written in the FPGA. ATF697FF [DATASHEET] 82 41000D−AERO03/14 A “Stop Address” which is a 24 bits word (3 bytes) to delimit the end of the window, The “Checksum Data” The checksum window is always present in an ATF697FF bitstream. Recurrent Checksum The FPGA Integrated Design System development tool is capable to calculate a recurrent checksum for each generated bitstream. The recurrent checksum is different from the simple checksum. It is used for self integrity checking. The recurrent checksum is computed by data accumulation over the configuration registers data and the data of all the windows that precede the recurrent checksum window. The “Recurrent Checksum” window is made of the following elements: The “Start Address” which is a 24 bits word (3 bytes) to access the Recurrent Checksum location in the FPGA The “Stop Address” which is a 24 bits word (3 bytes) to delimit the end of the window The “Recurrent Checksum Data” The recurrent checksum window is optional. It is only available when the recurrent checksum function is activated in the bitstream. For details on the recurrent checksum function usage, please refer to the Self Integrity Checker function section. Postamble The “postamble” is always present in the ATF697FF reconfigurable unit bitstreams. It is used by the configuration download state machine as a download protocol stop indicator indicating the end of the transfer. Its value is always “10110111”. ATF697FF [DATASHEET] 83 41000D−AERO03/14 11.2.2 Master Mode – Mode 0 Mode 0 is a master mode. The Master Mode is auto-configuring; that is, after power-on-reset (POR) and the clearing of configuration memory, it self-initiates configuration. The Master Mode uses an internal oscillator to provide CCLK for clocking the external EEPROMs (configurators) which contain the configuration data. CCLK also drives the downstream devices (Slaves) in the configuration cascade chain. Master Serial Mode clocks and receives data from an EEPROM Serial Configuration Memory. After auto-configuration is complete, re-configuration can be initiated manually by the user. In this mode, the ATF697FF reconfigurable unit is coupled to a serial EEPROM and managed automatically the whole configuration download phase. The automatic configuration download always starts after a Power-On reset or a Manual Reset. The following synoptic shows the required interface to be used for automatic configuration download purpose in mode 0. Figure 11-2. ATF697FF reconfigurable unit automatic configuration download in mode 0 CCLK IO713_D0 CON IO303_INIT IO259_LDC ATF697FFIO265_HDC M0 M1 M2 Vss CLK DATA /CE /RESET_OE Serial EEPROM Reconfigurable unit READY RESETn 11.2.2.1 Configuration Download from Power-On Reset in mode 0 The chronogram described here after presents the sequence of ATF697FF reconfigurable unit from a Power-On Reset until Run. This is the global overview of ATF697FF reconfigurable unit automatic configuration download after a PowerOn Reset. ATF697FF [DATASHEET] 84 41000D−AERO03/14 Figure 11-3. ATF697FF reconfigurable unit Configuration Download from Power-On Reset (1) (2) Notes: (3) 1. This line shows the different lifephase viewable in life cycle diagram described in OperatingModes / Lifephases section, 2. “Rising” means here the rising of power supplies line, 3. “CCE” means Clear Cycle End. [Power-On-Reset]: During the Power-On Reset lifephase, the ATF697FF reconfigurable unit starts to drive the signal regarding the configuration download interfaces as defined below. The end of this lifephase is marked by the rising edge of IO303_INIT pin: M0, M1, M2. these signals are inputs and not used, CCLK: this signal is internally pulled-up, IO713_D0: this signal is internally pulled-up, CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up until the end of the Clear Cycle operation (CCE). At this time, IO303_INIT is driven to a low logic level during approximatively 1 us, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which has no effect during the Power-On Reset lifephase. [Mode Sampling]: During the Mode Sampling lifephase, the ATF697FF reconfigurable unit continues to drive the signal regarding configuration download interfaces. In addition, Mode Pins (M0, M1, M2) are sensed: M0, M1, M2. these signals are inputs and sensed to determine the used mode. If mode 0 is sampled (as shown in the figure above), the automatic configuration download starts. CCLK: this signal is internally pulled-up, ATF697FF [DATASHEET] 85 41000D−AERO03/14 IO713_D0: this signal takes the value ouput by the EEPROM (first bit of the EEPROM), CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Configuration Download]: During the Configuration Download lifephase, the ATF697FF reconfigurable unit continues to drive the signal regarding configuration download interfaces, this lifephase starts when CCLK pin is ouput: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is output as clock source for the serial EEPROM memory. At each rising edge of CCLK, the EEPROM memory outputs a new bit while the ATF697FF senses the previous bit. By default, the CCLK frequency toggles at a frequency of approximatively 900 KHz. IO713_D0: this signal is sampled by the FPGA at each rising edge of CCLK. It is the DATA ouput of the EEPROM memory, CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up and is used as an error monitoring pin. Refer to Data Link Protection section for serial configuration, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Run]: Once configured, the ATF697FF reconfigurable unit enters in Run lifephase. In this lifephase, the loaded application runs and its own lifephases are taken into account. This lifephase is entered few CCLK cycles after the ATF697FF reconfigurable unit has sensed the postamble, it then releases the configuration interface signals and all multiplexed signals are set to their GPIO function: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is an input with pull-up and is not used anymore, IO713_D0: this signal becomes a User I/O and takes its application configuration, CON: this signal is released to a high logic level, IO303_INIT: this signal becomes a User I/O and takes its application configuration, IO259_LDC: this signal becomes a User I/O and takes its application configuration, IO265_HDC: this signal becomes a User I/O and takes its application configuration, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. ATF697FF [DATASHEET] 86 41000D−AERO03/14 11.2.2.2 Configuration Download from Manual Reset in mode 0 The chronogram described here after presents the sequence of ATF697FF reconfigurable unit from a Manual Reset until Run. This is the global overview of ATF697FF reconfigurable unit automatic configuration download after a Manual Reset. Figure 11-4. ATF697FF reconfigurable unit: Configuration Download from Manual Reset (2) (1) (3) Notes: 1. This line shows the different lifephase viewable in life cycle diagram described in OperatingModes / Lifephases section, 2. “MS” means Mode Sampling lifephase, 3. “CCE” means Clear Cycle End. [Manual Reset]: During the Manual Reset lifephase, the ATF697FF reconfigurable unit starts to drive the signal regarding the configuration download interfaces as defined below. This phase is entered when the FPGA_RESET* pin is activated. The end of this lifephase is marked by the rising edge of IO303_INIT pin. During Manual Reset lifephase, the Clear Cycle operation (ended by CCE in the figure above) starts immediately and is performed in approximatively 2 ms. If the FPGA_RESET* pin is activated during less than the 2 ms required for the Clear Cycle operation, the ATF697FF reconfigurable unit remains in Manual Reset until CCE time: M0, M1, M2. these signals are inputs and not used, CCLK: this signal is internally pulled-up, IO713_D0: this signal is internally pulled-up, CON: this signal is driven to a low logic level, IO303_INIT: this signal is driven low until the FPGA_RESET* pin is released, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which is active during Manual Reset lifephase. [Mode Sampling]: During the Mode Sampling lifephase, the ATF697FF reconfigurable unit continues to drive the signal regarding configuration download interfaces. In addition, Mode Pins (M0, M1, M2) are sensed: M0, M1, M2. these signals are inputs and sensed to determine the used mode. If mode 0 is sampled (as shown in the figure above), the automatic configuration download starts. ATF697FF [DATASHEET] 87 41000D−AERO03/14 CCLK: this signal is internally pulled-up, IO713_D0: this signal takes the value ouput by the EEPROM (first bit of the EEPROM), CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Configuration Download]: During the Configuration Download lifephase, the ATF697FF reconfigurable unit continues to drive the signal regarding configuration download interfaces, this lifephase starts when CCLK pin is ouput: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is output as clock source for the serial EEPROM memory. At each rising edge of CCLK, the EEPROM memory outputs a new bit while the ATF697FF reconfigurable unit senses the previous bit. By default, the CCLK frequency toggles at a frequency of approximatively 900 KHz. IO713_D0: this signal is sampled by the FPGA at each rising edge of CCLK. It is the DATA ouput of the EEPROM memory, CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up and is used as an error monitoring pin Refer to Data Link Protection section for serial configuration, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Run]: Once configured, the ATF697FF reconfigurable unit enters in Run lifephase. In this lifephase, the loaded application runs and its own lifephases are taken into account. This lifephase is entered few CCLK cycles after the ATF697FF reconfigurable unit has sensed the postamble, it then releases the configuration interface signals and all multiplexed signals are set to their GPIO function: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is an input with pull-up and is not used anymore, IO713_D0: this signal becomes a User I/O and takes its application configuration, CON: this signal is released to a high logic level, IO303_INIT: this signal becomes a User I/O and takes its application configuration, IO259_LDC: this signal becomes a User I/O and takes its application configuration, IO265_HDC: this signal becomes a User I/O and takes its application configuration, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. 11.2.2.3 Restart of Configuration Download in mode 0 In mode 0, it is possible to restart the configuration download phase without proceding to a FPGA reboot (Power-On reset or Manual Reset). For this, it is required to use an external component in order to trig the start of the configuration download. The following synoptic shows the required signal to be used for restart of configuration download purpose in mode 0. ATF697FF [DATASHEET] 88 41000D−AERO03/14 Figure 11-5. ATF697FF reconfigurable unit restart configuration download in mode 0 CCLK IO713_D0 CON IO303_INIT IO259_LDC ATF697FFIO265_HDC M0 M1 M2 Vss CLK DATA /CE /RESET_OE Reconfigurable unit Serial EEPROM READY RESETn Start configuration download Reset EEPROM counters External Component to start Configuration Download The chronogram described here after presents the sequence of ATF697FF reconfigurable unit from a Run until Run. This is the global overview of ATF697FF reconfigurable unit restart of configuration download when in Run. Figure 11-6. ATF697FF reconfigurable unit : Restart of Configuration Download in mode 0 [Run]: In Run liefphase, the multiplexed pin of the ATF697FF reconfigurable unit are in their GPIO function and as configured by the already loaded application. This lifephase is exiting to enter in Configuration Download as soon as the CON pin is driven to a low logic level by an external master: M0, M1, M2. these signals remain inputs and are not used anymore (Mode is already sampled), CCLK: this signal is an input with pull-up and is not used, IO713_D0: this signal remains a User I/O, CON: this signal is released to a high logic level by the ATF697FF reconfigurable unit itself, ATF697FF [DATASHEET] 89 41000D−AERO03/14 IO303_INIT: this signal remains a User I/O, IO259_LDC: this signal remains a User I/O, IO265_HDC: this signal remains a User I/O, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Configuration Download]: During the Configuration Download lifephase, the ATF697FF reconfigurable unit starts to drive the signal regarding configuration download interfaces, this lifephase starts when CON is lowered by an external master component: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is output as clock source for the serial EEPROM memory. At each rising edge of CCLK, the EEPROM memory outputs a new bit while the ATF697FF reconfigurable unit senses the previous bit. By default, the CCLK frequency toggles at a frequency of approximatively 900 KHz. IO713_D0: this signal is sampled by the FPGA at each rising edge of CCLK. It is the DATA ouput of the EEPROM memory, CON: this signal shall be first maintained to a low logic level by an external master component. The configuration download starts immediately and CCLK is directly output. Once the ATF697FF reconfigurable unit has sampled the CON pin to low during three CCLK periods, it starts to drive the CON pin to a low logic level. Then the external master component shall release the CON signal, IO303_INIT: this signal is internally pulled-up and is used as an error monitoring pin. Refer to Data Link Protection section for serial configuration, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Run]: Once configured, the ATF697FF reconfigurable unit enters in Run lifephase. In this lifephase, the loaded application runs and its own lifephases are taken into account. This lifephase is entered few CCLK cycles after the ATF697FF reconfigurable unit has sensed the postamble, it then releases the configuration interface signals and all multiplexed signals are set to their GPIO function: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is an input with pull-up and is not used anymore, IO713_D0: this signal becomes a User I/O and takes its application configuration, CON: this signal is released to a high logic level, IO303_INIT: this signal becomes a User I/O and takes its application configuration, IO259_LDC: this signal becomes a User I/O and takes its application configuration, IO265_HDC: this signal becomes a User I/O and takes its application configuration, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. 11.2.3 Slave Modes In slave modes, configuration is always initiated by an external signal. Data is applied to the device on the rising edge of CCLK. In Slave Serial Mode, the device receives serial configuration data. CCLK is not generated in slave modes. ATF697FF [DATASHEET] 90 41000D−AERO03/14 11.2.3.1 Mode 1 The mode 1 is one of the Slave Serial Mode configuration download. In this mode, the ATF697FF reconfigurable unit is coupled to a serial EEPROM and shall be externally driven for configuration download purpose. The following synoptic shows the required interface to be used for configuration download purpose in mode 1. Figure 11-7. ATF697FF reconfigurable unit FPGA environment : configuration download in mode 1 Vcc M0 M1 M2 Vss CCLK IO713_D0 CON IO303_INIT ATF697FF IO259_LDC IO265_HDC Reconfigurable CLK DATA /CE /RESET_OE Serial EEPROM unit READY IO547_CS0 RESETn Start configuration download User applies a low logic level before starting configuration download Reset EEPROM counters External Component to start Configuration Download Power-On Reset in mode 1 The chronogram described here after presents the sequence of ATF697FF reconfigurable unit from a Power-On Reset until Idle. This is the global overview of ATF697FF reconfigurable unit Power-On Reset sequence. At the end of this sequence, the ATF697FF reconfigurable unit remains unconfigured and is ready for configuration download in slave mode. ATF697FF [DATASHEET] 91 41000D−AERO03/14 Figure 11-8. ATF697FF reconfigurable unit Power-On Reset in mode 1 (1) (2) Notes: 1. This line shows the different lifephase viewable in life cycle diagram described in OperatingModes / Lifephases section, 2. “CCE” means Clear Cycle End. [Power-On-Reset]: During the Power-On Reset lifephase, the ATF697FF reconfigurable unit starts to drive the signal regarding the configuration download interfaces as defined below. The end of this lifephase is marked by the rising edge of IO303_INIT pin: M0, M1, M2. these signals are inputs and not used, CCLK: this signal is internally pulled-up, IO713_D0: this signal is internally pulled-up, CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up until the end of the Clear Cycle operation (CCE). At this time, IO303_INIT is driven to a low logic level during approximatively 1 us, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, IO547_CS0: this signal is internally pulled-up, FPGA_RESET* : this signal is an input which has no effect during the Power-On Reset lifephase. [Mode Sampling]: During the Mode Sampling lifephase, the ATF697FF reconfigurable unit continues to drive the signal regarding configuration download interfaces. In addition, Mode Pins (M0, M1, M2) are sensed: ATF697FF [DATASHEET] 92 41000D−AERO03/14 M0, M1, M2. these signals are inputs and sensed to determine the used mode. If mode 0 is sampled (as shown in the figure above), the automatic configuration download starts. CCLK: this signal is internally pulled-up, IO713_D0: this signal takes the value ouput by the EEPROM (first bit of the EEPROM), CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, IO547_CS0: this signal is internally pulled-up, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Idle]: During the Idle lifephase, the ATF697FF reconfigurable unit continues releases the configuration download interface, this lifephase starts when CON and IO303_INIT pins are released: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is internally pulled-up, IO713_D0: this signal takes its GPIO function and is internally pulled-up, CON: this signal is released to a high logic level, IO303_INIT: this signal takes its GPIO function and is internally pulled-up. Refer to Data Link Protection section for serial configuration, IO259_LDC: this signal takes its GPIO function and is internally pulled-up, IO265_HDC: this signal takes its GPIO function and is internally pulled-up, IO547_CS0: this signal takes its GPIO function and is internally pulled-up, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. ATF697FF [DATASHEET] 93 41000D−AERO03/14 Manual Reset in mode 1 The chronogram described here after presents the sequence of ATF697FF reconfigurable unit from a Manual Reset until Idle. This is the global overview of ATF697FF reconfigurable unit Manual Reset sequence. At the end of this sequence, the ATF697FF reconfigurable unit remains unconfigured and is ready for configuration download in slave mode. Figure 11-9. ATF697FF reconfigurable unit : Manual Reset in mode 1 (1) (3) Notes: (2) 1. This line shows the different lifephase viewable in life cycle diagram described in OperatingModes / Lifephases section, 2. “MS” means Mode Sampling lifephase, 3. “CCE” means Clear Cycle End. [Manual Reset]: During the Manual Reset lifephase, the ATF697FF reconfigurable unit starts to drive the signal regarding the configuration download interfaces as defined below. This phase is entered when the FPGA_RESET* pin is activated. The end of this lifephase is marked by the rising edge of IO303_INIT pin. During Manual Reset lifephase, the Clear Cycle operation (ended by CCE in the figure above) starts immediately and is performed in approximatively 2 ms. If the FPGA_RESET* pin is activated during less than the 2 ms required for the Clear Cycle operation, the ATF697FF reconfigurable unit remains in Manual Reset until CCE time: M0, M1, M2. these signals are inputs and not used, CCLK: this signal is internally pulled-up, IO713_D0: this signal is internally pulled-up, ATF697FF [DATASHEET] 94 41000D−AERO03/14 CON: this signal is driven to a low logic level, IO303_INIT: this signal is driven low until the FPGA_RESET* pin is released, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, IO547_CS0: this signal is internally pulled-up, FPGA_RESET* : this signal is an input which is active during Manual Reset lifephase. [Mode Sampling]: During the Mode Sampling lifephase, the ATF697FF reconfigurable unit continues to drive the signal regarding configuration download interfaces. In addition, Mode Pins (M0, M1, M2) are sensed: M0, M1, M2. these signals are inputs and sensed to determine the used mode. If mode 0 is sampled (as shown in the figure above), the automatic configuration download starts. CCLK: this signal is internally pulled-up, IO713_D0: this signal takes the value ouput by the EEPROM (first bit of the EEPROM), CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, IO547_CS0: this signal is internally pulled-up, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Idle]: During the Idle lifephase, the ATF697FF reconfigurable unit continues releases the configuration download interface, this lifephase starts when CON and IO303_INIT pins are released: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is internally pulled-up, IO713_D0: this signal takes its GPIO function and is internally pulled-up, CON: this signal is released to a high logic level, IO303_INIT: this signal takes its GPIO function and is internally pulled-up. Refer to Data Link Protection section for serial configuration, IO259_LDC: this signal takes its GPIO function and is internally pulled-up, IO265_HDC: this signal takes its GPIO function and is internally pulled-up, IO547_CS0: this signal takes its GPIO function and is internally pulled-up, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. ATF697FF [DATASHEET] 95 41000D−AERO03/14 Configuration Download in mode 1 The chronogram described here after presents the sequence of ATF697FF reconfigurable unit from Run or Idle until Run. This is the global overview of ATF697FF reconfigurable unit Configuration Download sequence in mode 1. At the end of this sequence, the ATF697FF reconfigurable unit is configured and the loaded application runs. Figure 11-10. ATF697FF reconfigurable unit: Configuration Download in mode 1 [Run]: In Run lifephase, the multiplexed pin of the ATF697FF reconfigurable unit are in their GPIO function and as configured by the already loaded application. This lifephase is exiting to enter in Configuration Download as soon as the CON pin is driven to a low logic level by an external master: M0, M1, M2. these signals remain inputs and are not used anymore (Mode is already sampled), CCLK: this signal is an input with pull-up and is not used, IO713_D0: this signal remains a User I/O, CON: this signal is released to a high logic level by the ATF697FF reconfigurable unit itself, IO303_INIT: this signal remains a User I/O, IO259_LDC: this signal remains a User I/O, IO265_HDC: this signal remains a User I/O, IO547_CS0: this signal remains a User I/O, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Configuration Download]: During the Configuration Download lifephase, the ATF697FF reconfigurable unit starts to drive the signal regarding configuration download interfaces, this lifephase starts when CON is lowered by an external master component: M0, M1, M2. these signals remain inputs and are not used anymore, ATF697FF [DATASHEET] 96 41000D−AERO03/14 CCLK: this signal is an input and shall be provided by the external master component as clock source for the serial EEPROM memory and the ATF697FF reconfigurable unit. At each rising edge of CCLK, the EEPROM memory outputs a new bit while the ATF697FF reconfigurable unit senses the previous bit. IO713_D0: this signal is sampled by the FPGA at each rising edge of CCLK. It is the DATA ouput of the EEPROM memory, CON: this signal shall be first maintained to a low logic level by an external master component. The configuration download starts immediately and CCLK is directly output. Once the ATF697FF reconfigurable unit has sampled the CON pin to low during three CCLK periods, it starts to drive the CON pin to a low logic level. Then the external master component shall release the CON signal, IO303_INIT: this signal is internally pulled-up and is used as an error monitoring pin. Refer to Data Link Protection section for serial configuration, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, IO547_CS0: this signal shall be driven low during the whole configuration download lifephase, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Run]: Once configured, the ATF697FF reconfigurable unit enters in Run lifephase. In this lifephase, the loaded application runs and its own lifephases are taken into account. This lifephase is entered few CCLK cycles after the ATF697FF reconfigurable unit has sensed the postamble, it then releases the configuration interface signals and all multiplexed signals are set to their GPIO function: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is an input with pull-up and is not used anymore, IO713_D0: this signal becomes a User I/O and takes its application configuration, CON: this signal is released to a high logic level, IO303_INIT: this signal becomes a User I/O and takes its application configuration, IO259_LDC: this signal becomes a User I/O and takes its application configuration, IO265_HDC: this signal becomes a User I/O and takes its application configuration, IO547_CS0: this signal becomes a User I/O and takes its application configuration, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. ATF697FF [DATASHEET] 97 41000D−AERO03/14 11.2.3.2 Mode 7 The mode 7 is one of the Slave Serial Mode configuration download. In this mode, the ATF697FF reconfigurable unit is coupled to a serial EEPROM and shall be externally driven for configuration download purpose. The following synoptic shows the required signal to be used for configuration download purpose in mode 7. Figure 11-11. ATF697FF reconfigurable unit A environment : configuration download in mode 7 Vcc CCLK IO713_D0 CON IO303_INIT IO259_LDC ATF697FFIO265_HDC M0 M1 M2 CLK DATA /CE /RESET_OE Reconfigurable unit Serial EEPROM READY RESETn Start configuration download Reset EEPROM counters External Component to start Configuration Download Power-On Reset in mode 7 The chronogram described here after presents the sequence of ATF697FF reconfigurable unit from a Power-On Reset until Idle. This is the global overview of ATF697FF reconfigurable unit Power-On Reset sequence. At the end of this sequence, the ATF697FF reconfigurable unit remains unconfigured and is ready for configuration download in slave mode. ATF697FF [DATASHEET] 98 41000D−AERO03/14 Figure 11-12. ATF697FF reconfigurable unit Power-On Reset in mode 7 (1) (2) Notes: 1. This line shows the different lifephase viewable in life cycle diagram described in OperatingModes / Lifephases section, 2. “CCE” means Clear Cycle End. [Power-On-Reset]: During the Power-On Reset lifephase, the ATF697FF reconfigurable unit starts to drive the signal regarding the configuration download interfaces as defined below. The end of this lifephase is marked by the rising edge of IO303_INIT pin: M0, M1, M2. these signals are inputs and not used, CCLK: this signal is internally pulled-up, IO713_D0: this signal is internally pulled-up, CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up until the end of the Clear Cycle operation (CCE). At this time, IO303_INIT is driven to a low logic level during approximatively 1 us, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which has no effect during the Power-On Reset lifephase. [Mode Sampling]: During the Mode Sampling lifephase, the ATF697FF reconfigurable unit continues to drive the signal regarding configuration download interfaces. In addition, Mode Pins (M0, M1, M2) are sensed: M0, M1, M2. these signals are inputs and sensed to determine the used mode. If mode 0 is sampled (as shown in the figure above), the automatic configuration download starts. ATF697FF [DATASHEET] 99 41000D−AERO03/14 CCLK: this signal is internally pulled-up, IO713_D0: this signal takes the value ouput by the EEPROM (first bit of the EEPROM), CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Idle]: During the Idle lifephase, the ATF697FF reconfigurable unit continues releases the configuration download interface, this lifephase starts when CON and IO303_INIT pins are released: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is internally pulled-up, IO713_D0: this signal takes its GPIO function and is internally pulled-up, CON: this signal is released to a high logic level, IO303_INIT: this signal takes its GPIO function and is internally pulled-up. Refer to Data Link Protection section for serial configuration, IO259_LDC: this signal takes its GPIO function and is internally pulled-up, IO265_HDC: this signal takes its GPIO function and is internally pulled-up, IO547_CS0: this signal takes its GPIO function and is internally pulled-up, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. ATF697FF [DATASHEET] 100 41000D−AERO03/14 Manual Reset in mode 7 The chronogram described here after presents the sequence of ATF697FF reconfigurable unit from a Manual Reset until Idle. This is the global overview of ATF697FF reconfigurable unit Manual Reset sequence. At the end of this sequence, the ATF697FF reconfigurable unit remains unconfigured and is ready for configuration download in slave mode. Figure 11-13. ATF697FF reconfigurable unit: Manual Reset in mode 7 (1) (3) Notes: (2) 1. This line shows the different lifephase viewable in life cycle diagram described in OperatingModes / Lifephases section, 2. “MS” means Mode Sampling lifephase, 3. “CCE” means Clear Cycle End. [Manual Reset]: During the Manual Reset lifephase, the ATF697FF reconfigurable unit starts to drive the signal regarding the configuration download interfaces as defined below. This phase is entered when the FPGA_RESET* pin is activated. The end of this lifephase is marked by the rising edge of IO303_INIT pin. During Manual Reset lifephase, the Clear Cycle operation (ended by CCE in the figure above) starts immediately and is performed in approximatively 2 ms. If the FPGA_RESET* pin is activated during less than the 2 ms required for the Clear Cycle operation, the ATF697FF reconfigurable unit remains in Manual Reset until CCE time: M0, M1, M2. these signals are inputs and not used, CCLK: this signal is internally pulled-up, IO713_D0: this signal is internally pulled-up, ATF697FF [DATASHEET] 101 41000D−AERO03/14 CON: this signal is driven to a low logic level, IO303_INIT: this signal is driven low until the FPGA_RESET* pin is released, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which is active during Manual Reset lifephase. [Mode Sampling]: During the Mode Sampling lifephase, the ATF697FF reconfigurable unit continues to drive the signal regarding configuration download interfaces. In addition, Mode Pins (M0, M1, M2) are sensed: M0, M1, M2. these signals are inputs and sensed to determine the used mode. If mode 0 is sampled (as shown in the figure above), the automatic configuration download starts. CCLK: this signal is internally pulled-up, IO713_D0: this signal takes the value ouput by the EEPROM (first bit of the EEPROM), CON: this signal is driven to a low logic level, IO303_INIT: this signal is internally pulled-up, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET*: this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Idle]: During the Idle lifephase, the ATF697FF reconfigurable unit continues releases the configuration download interface, this lifephase starts when CON and IO303_INIT pins are released: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is internally pulled-up, IO713_D0: this signal takes its GPIO function and is internally pulled-up, CON: this signal is released to a high logic level, IO303_INIT: this signal takes its GPIO function and is internally pulled-up. Refer to Data Link Protection section for serial configuration, IO259_LDC: this signal takes its GPIO function and is internally pulled-up, IO265_HDC: this signal takes its GPIO function and is internally pulled-up, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. ATF697FF [DATASHEET] 102 41000D−AERO03/14 Configuration Download in mode 7 The chronogram described here after presents the sequence of ATF697FF reconfigurable unit from Run or Idle until Run. This is the global overview of ATF697FF reconfigurable unit Configuration Download sequence in mode 1. At the end of this sequence, the ATF697FF reconfigurable unit is configured and the loaded application runs. Figure 11-14. ATF697FF reconfigurable unit: Configuration Download in mode 7 [Run]: In Run lifephase, the multiplexed pin of the ATF697FF reconfigurable unit are in their GPIO function and as configured by the already loaded application. This lifephase is exiting to enter in Configuration Download as soon as the CON pin is driven to a low logic level by an external master: M0, M1, M2. these signals remain inputs and are not used anymore (Mode is already sampled), CCLK: this signal is an input with pull-up and is not used, IO713_D0: this signal remains a User I/O, CON: this signal is released to a high logic level by the ATF697FF reconfigurable unit itself, IO303_INIT: this signal remains a User I/O, IO259_LDC: this signal remains a User I/O, IO265_HDC: this signal remains a User I/O, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Configuration Download]: During the Configuration Download lifephase, the ATF697FF reconfigurable unit starts to drive the signal regarding configuration download interfaces, this lifephase starts when CON is lowered by an external master component: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is an input and shall be provided by the external master component as clock source for the serial EEPROM memory and the ATF697FF reconfigurable unit. At each rising edge of CCLK, the EEPROM memory outputs a new bit while the ATF697FF reconfigurable unit senses the previous bit. ATF697FF [DATASHEET] 103 41000D−AERO03/14 IO713_D0: this signal is sampled by the FPGA at each rising edge of CCLK. It is the DATA ouput of the EEPROM memory, CON: this signal shall be first maintained to a low logic level by an external master component. The configuration download starts immediately and CCLK is directly output. Once the ATF697FF reconfigurable unit has sampled the CON pin to low during three CCLK periods, it starts to drive the CON pin to a low logic level. Then the external master component shall release the CON signal, IO303_INIT: this signal is internally pulled-up and is used as an error monitoring pin. Refer to Data Link Protection section for serial configuration, IO259_LDC: the Low During Configuration is driven to a low logic level, IO265_HDC: the High During Configuration is driven to a high logic level, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. [Run]: Once configured, the ATF697FF reconfigurable unit enters in Run lifephase. In this lifephase, the loaded application runs and its own lifephases are taken into account. This lifephase is entered few CCLK cycles after the ATF697FF reconfigurable unit has sensed the postamble, it then releases the configuration interface signals and all multiplexed signals are set to their GPIO function: M0, M1, M2. these signals remain inputs and are not used anymore, CCLK: this signal is an input with pull-up and is not used anymore, IO713_D0: this signal becomes a User I/O and takes its application configuration, CON: this signal is released to a high logic level, IO303_INIT: this signal becomes a User I/O and takes its application configuration, IO259_LDC: this signal becomes a User I/O and takes its application configuration, IO265_HDC: this signal becomes a User I/O and takes its application configuration, FPGA_RESET* : this signal is an input which immediately reset the configuration logic to a Manual Reset lifephase. ATF697FF [DATASHEET] 104 41000D−AERO03/14 11.2.3.3 Data Link Protection The ATF697FF reconfigurable unit is capable to secure the mechanism involved during the configuration download in order to prevent wrong configuration of the FPGA. The following schematic represents an overview of the system made by the FPGA and a serial EEPROM memory. The highlighted modules show where the protection of the configuration download link takes place. Figure 11-15. ATF697FF reconfigurable unit Configuration Download Link ATF697FF reconfigurable unit AT69170E POR EEPROM Core User I/O FPGA Core Configuration SRAM Configuration control Memory Controller Boundary Scan Controller LVDS Interface Differential Clocks Configuration Self Internal Checker Configuration Load Checker Serializer POR TWI Interface Checksum Two kinds of errors are managed during the configuration: Low Level Errors Such protection is used to warranty that the communication protocol on the FPGA serial communication link is correctly handled all along the configuration process. In addition, the low level error management ensures that no erroneous access to the FPGA configuration SRAM will be attempted. When detected, the low level results in “Aborting Download”. This means that all the steps from a configuration download are not performed. The consequence is that the bitstream is partially loaded and can result in an unoperating FPGA, Checksum Errors This protection is used at the end of the configuration download to verify that there were no corruptions of the data stream during the transfer. When detected, the checksum error results in “Finishing download”. This means that all the steps from a nominal configuration download are executed until entering in Run lifephase. The error detection mechanism follows the flow chart presented here after. ATF697FF [DATASHEET] 105 41000D−AERO03/14 Figure 11-16. Management of configuration download link protection Initial conditions Downloading Increment Address Checksum accumulation Yes Low Level Error ? No No Checksum Address ? Yes Compare Checksums Drive INIT to low Checksums mismatch ? No Yes Drive INIT to low Finishing Download Aborting Download Download Finished Low level Errors management These errors have the highest priority and terminate by a configuration download abort. They are managed in the same way whatever is the used serial mode (Mode 0, 1 or 7). The low level errors are detected in case of bad values regarding the following elements: “Preamble” mismatch different from “10110111” “Start Address” mismatch if the start address of a window is corrupted, “Stop Address” mismatch if the stop address of a window is corrupted, “Postamble” mismatch different from “11100111”. In case of low level error, INIT is driven low during one CCLK clock period few clock cycles after the byte in default. Then, INIT is released and CON is released. The configuration download is so finished. ATF697FF [DATASHEET] 106 41000D−AERO03/14 Figure 11-17. ATF697FF reconfigurable unit Preamble mismatch behavior in mode 0 Checksum Errors management During the generation of an application bitstream, a checksum is computed with a specific algorithm by IDS tool and stored in the bitstream checksum zone. This checksum is the reference for checksum error management. All along the configuration download, the “configuration load checker” calculates on-the-fly a checksum byte by accumulating all effective data of the downloaded bitstream with a hardcoded algorithm. Once the FPGA configuration reaches the checksum zone, it compares the reference downloaded checksum together with the checksum accumulated during the configuration download. In case of mismatched values, INIT is driven low to notify that errors occur during the download procedure. All data loaded in the FPGA configuration SRAM will be taken into account by the FPGA parts. On ATF697FF reconfigurable unit, the checksum window is addressed as follow and is one byte sized: Start Address: Byte0 = 0x00000000, Byte 1 = 0x00000000, Byte 2 = 0x11000000, Stop Address: Byte0 = 0x00000000, Byte 1 = 0x00000000, Byte 2 = 0x11000000 ATF697FF [DATASHEET] 107 41000D−AERO03/14 Figure 11-18. ATF697FF reconfigurable unit Checksum error behavior in mode 0 ATF697FF [DATASHEET] 108 41000D−AERO03/14 11.3 Configuration Integrity Management While the download of the bit-stream from the EEPROM (or configuration master) to the FPGA is checked through communication link protection, the ATF697FF reconfigurable unit also provides the features for verification of the configuration once the FPGA configuration is finished. Two services are provided to manage the integrity of the configuration. 11.3.1 Check function The ATF697FF reconfigurable unit, through the configuration logic embeds a feature called CHECK function. This feature, if activated, is useable at any time when the FPGA is in Run phase. It provides a strong mechanism to ensure that loaded data are the same than the EEPROM source one. 11.3.1.1 Description The following schematic represents an overview of the system made by the FPGA and a serial EEPROM memory. The highlighted modules show where the CHECK function takes place: The FGPA could be either in Mode 0, 1 or 7 for serial mode, The EEPROM has a serial interface for serial mode, The EEPROM interface is compliant with the interface required by the ATF697FF reconfigurable unit, The result of CHECK function reflets any differences between Configuration SRAM of ATF697FF reconfigurable unit and EEPROM memory content. Figure 11-19. ATF697FF RECONFIGURABLE UNIT : CHECK function overview CHECK ATF697FF reconfigurable unit AT69170E POR EEPROM Core User I/O FPGA Core Configuration SRAM Configuration control Memory Controller Boundary Scan Controller LVDS Interface Differential Clocks Configuration Self Internal Checker Configuration Load Checker Serializer POR TWI Interface ATF697FF [DATASHEET] 109 41000D−AERO03/14 The CHECK function obeys to the following workflow: Figure 11-20. ATF697FF reconfigurable unit CHECK function workflow Initial conditions: Entering in Configuration Download phase CHECKN is set to LOW Checking Increment Address Low Level Error ? Yes Read Data == incoming data? Yes No Drive INIT to low No No Drive INIT to low Postamble ? Yes Finishing CHECK Aborting CHECK CHECK Finished To verify the data, the ATF697FF reconfigurable unit uses the CHECK function in parallel to a configuration download. The use of CHECK function is optional and can be bypassed by the user (Refer to Register Chapter for more details). The differences between a nominal configuration download and a CHECK function is described below: When performing a configuration download, the “configuration control” module addresses the SRAM point and writes them as defined in the EEPROM bitstream, When performing a CHECK function, the “configuration control” module addresses the SRAM point, read them and compare their content to the value defined in the EEPROM bitstream, The “configuration load checker” module manages the protocol errors (low level errors) in the same way than for a configuration download, but checksums are not taken into account. The following synoptics shows the required interface of ATF697FF reconfigurable unit for the use of CHECK function in serial modes. For each of these cases, the required interface is strictly the same than the one required for the configuration download but with the use of IO655_CHECK* pin. ATF697FF [DATASHEET] 110 41000D−AERO03/14 11.3.1.2 Serial Modes Figure 11-21. CHECK function in serial modes Mode 0 Mode 1 Mode 7 M0 M1 M2 CCLK IO713_D0 CON IO303_INIT IO259_LDC ATF697FFIO265_HDC CLK DATA /CE /RESET_OE Reconfigurable unit READY IO655_CHECKN IO547_CS0 RESETn User applies a low logic level before starting configuration download Caution: Serial EEPROM Start configuration download Reset EEPROM counters External Component to start Configuration Download In serial mode, the required interface for CHECK function is the same than for configuration download. It means that for Mode 1, the IO547_CS0 shall be used in parallel to the IO655_CHECK* pin when starting the configuration download (dotted line in figure above). 11.3.1.3 Behavior The use of CHECK function is done by launching in Run lifephase a configuration download while IO655_CHECK* pin is externally driven to a low logic level. Figure 11-22. ATF697FF reconfigurable unit CHECK function without error ATF697FF [DATASHEET] 111 41000D−AERO03/14 Figure 11-23. ATF697FF reconfigurable unit CHECK function with error Caution: It shall be noticed that in case of error detected during a CHECK function, two kinds of errors are possible: Low Level Error: the error that are protocol relevant and which bring the IO303_INIT to be driven low after some CCLK periods, CHECK comparison mismatch: the signature is a drive to low of the IO303_INIT two CCLK periods after the byte in default. 11.3.2 Self Integrity Checker function The ATF697FF reconfigurable unit, through the configuration logic embeds a feature called CSIC (for Configuration Self Integrity Checker). This feature, if activated, is useable in Run phase. It provides a strong mechanism to ensure the retention of the loaded data. 11.3.2.1 Description The following schematic represents an overview of the modules involved in the CSIC function: ATF697FF [DATASHEET] 112 41000D−AERO03/14 Figure 11-24. ATF697FF reconfigurable unit CSIC Overview CSIC ATF697FF – Reconfigurable Unit AT69170E POR EEPROM Core User I/O Configuration SRAM FPGA Core Configuration control Memory Controller Boundary Scan Controller LVDS Interface Differential Clocks Configuration Self Internal Checker Configuration Load Checker Serializer POR TWI Interface The CSIC function obeys to the following workflow: Figure 11-25. ATF697FF reconfigurable unit CSIC workflow Initial conditions: Entering Run phase SRAM Address reset Increment Address Checking Recurrent Checksum accumulation No SRAM Address reset Recurrent Checksum Address ? Compare Recurrent Checksums Yes Recurrent Checksums mismatch ? No Yes Drive INIT to low CSIC aborted The following points described how the CSIC function could be used and how it works: The CSIC function is not mode dependent and is activated with the bit CR8 of the configuration register (Refer to Register Chapter for more details), The bitstream will contain a window called “Recurrent Checksum” with a stored byte calculated by the IDS Software during the bitstream generation, The ATF697FF reconfigurable unit will calculate cyclically by the used of loaded data the value of this Recurrent Checksum and will compare the result with the one stored in the “Recurrent Checksum” window, ATF697FF [DATASHEET] 113 41000D−AERO03/14 In mode 0 (the only master mode), the CSIC function requires the activation of the bit CR13 of the configuration register (Refer to Register Chapter for more details). The continuous CCLK option is mandatory to clock the CSIC function, Caution: In all other modes (1 and 7), the CCLK shall be provided continuously after the configuration download by an external clock source. This continuous CCLK input is mandatory to clock the CSIC function, Caution: CCLK will toggle during all the time of the Run phase. CCLK shall not be stop during all the time of the Run phase. When CSIC function is used, the IO303_INIT pin remains in [CFG] function and is released to a high logic level while no error is detected. If a bit flips, it will bring the calculated recurrent checksum to be different from the stored recurrent checksum. The result will be a drive to low logic level of the IO303_INIT until a Power-On Reset or a Manual Reset and the bitstream will continue to work. Caution: IO303_INIT will remain in [CFG] function during all the time of Run phase and shall be taken into account at system level. 11.3.2.2 Behavior Figure 11-26. CSIC function behavior on error ATF697FF [DATASHEET] 114 41000D−AERO03/14 11.4 FreeRamTM The ATF697FF treconfigurable unit offers 115Kbits of dual-port RAM called FreeRAMTM. The FreeRAMTM is made of 32 x 4 dual-ported RAM blocks and dispersed throughout the array as shown in the figure hereafter. This FreeRAMTM is SEU hardened. A 4-bit Input Data Bus connects to four horizontal local buses distributed over four sector rows. A 4-bit Output Data Bus connects to four horizontal local buses distributed over four sector rows. A 5-bit Input Address Bus connects to five vertical express buses in same column. A 5-bit Output Address Bus connects to five vertical express buses in same column. Ain (input address) and Aout (output address) alternate positions in horizontally aligned RAM blocks. For the left-most RAM blocks, Aout is on the left and Ain is on the right. For the right-most RAM blocks, Ain is on the left and Aout is tied off, thus it can only be configured as a single port. For single-ported RAM, Ain is the READ/WRITE address port and Din is the (bi-directional) data port. TM Figure 11-27. FreeRam Block Interface Reading and writing of the 10ns 32 x 4 dual-port FreeRAMTM are independent of each other. Reading the 32 x 4 dualport RAM is completely asynchronous. Latches on Write Address, Write Enable and Data In are transparent: when load is logic 1, data flows through when load is logic 0, data is latched. Figure 11-28. RAM logic - Detailed The latches are used to synchronize Write Address, Write Enable Not, and Din signals for a synchronous RAM. Each bit in the 32 x 4 dual-port RAM is also a transparent latch. The front-end latch and the memory latch together form an edge-triggered flip flop. When a nibble is (Write) addressed and LOAD is logic 1 and WE is logic 0, data flows through the bit. When a nibble is not (Write) addressed or LOAD is logic 0 or WE is logic 1, data is latched in the nibble. ATF697FF [DATASHEET] 115 41000D−AERO03/14 The two CLOCK muxes are controlled together; they both select CLOCK (for a synchronous RAM) or they both select “1” (for an asynchronous RAM). CLOCK is obtained from the clock for the sector-column immediately to the left and immediately above the RAM block. ATF697FF [DATASHEET] 116 41000D−AERO03/14 12. Internal communication 12.1 Introduction The ATF697FF reconfigurable processor embeds a full set of internal connectivity for control/command and data management between the two units: 12.2 The complete external bus interface (EBI) is output from the ATF697FF device and also interconnected between the two units, allowing the use of the reconfigurable unit as a ‘standard memory’ mapped peripheral. The processor Host/Satellite PCI 2.2 compliant interface is shared between the two units has described here after A simple set of general purpose IO is also shared. EBI sharing Please refer to section “Memory Mapped Reconfigurable Unit” for details. 12.3 GPIO sharing The GPIO0 to GPIO7 are shared internally between the processor and the reconfigurable unit. They are connected externally as well. Here there is a table which summarizes the internal connexions for the GPIO part. Table 12-1. GPIO internal pin assignement 12.4 ATF697FF pin name (processor side) ATF697FF pin name (reconfigurable unit side) ATF697FF pin direction (ATF697FF reconfigurable unit side) GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 IO233 IO237 IO331 IO333 IO337 IO339 IO343 IO345 Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional PCI sharing 12.4.1 Internal PCI interface: pin description 12.4.1.1 PCI system PCI_CLK PCI clock (input) This signal provides timing for all transactions on the PCI bus. All other PCI signals, except PCI_RST*, are sampled on the rising edge of PCI_CLK and all other timing parameters are defined with respect to this edge. PCI_RST* PCI Reset (input) ATF697FF [DATASHEET] 117 41000D−AERO03/14 This active low input is used to bring PCI-specific registers, sequencers and signals to a consistent state. When asserted, it immediately halts and resets the PCI interface. The PCI interface resumes execution after the 5 th rising edge of the PCI_CLK clock after PCI_RST* was de-asserted. SYSEN* System Enable (input) This active low input is used to configure the PCI interface as the Host-Bridge for the PCI bus (also called the SystemController in a CompactPCI-compliant environment). If de-asserted, the PCI interface is configured as a satellite on the PCI bus. This signal shall be kept static and free from glitches while the processor is operating, as it is not sampled internally. Changing the signal shall only be performed while the processor is under reset otherwise the processor’s behavior is not predictable. 12.4.1.2 PCI Address & Data A/D[31:0] PCI Address Data (bi-directional) Address and Data are multiplexed on the same PCI pins. During the address phase, A/D[31:0] contain a physical address (32 bits). For I/O, this is a byte address; for configuration and memory, it is a 32-bit address. During data phases, A/D[7:0] contain the least significant byte and A/D[31:24] contain the most significant byte. C/BE*[3:0] PCI Bus Command and Byte Enables (bi-directional) During the address phase of a transaction, C/BE*[3:0] define the bus command. During the data phase, C/BE*[3:0]are used as Byte Enables. The Byte Enables are valid for the entire data phase. PAR Parity (bi-directional) This signal is even parity across A/D[31:0] and C/BE*[3:0](the number of “1”s on A/D[31:0], C/BE*[3:0]and PAR equals an even number). The master drives PAR for address and write data phases; the PCI target drives PAR for read data phases. 12.4.1.3 PCI Interface Control FRAME* Cycle PCI_FRAME (bi-directional) This signal is driven by the current master to indicate the beginning and duration of an access. FRAME* is asserted to indicate a bus transaction is beginning. While FRAME* is asserted, data transfers continue. When FRAME* is deasserted, the transaction is in the final data phase or has completed. IRDY* Initiator Ready (bi-directional) This signal indicates the initiating agent’s ability to complete the current data phase of the transaction. IRDY* is used in conjunction with IRDY*. During a write, IRDY* indicates that valid data is present on A/D[31:0]. During a read, it indicates the master is prepared to accept data. TRDY* Target Ready (bi-directional) This signal indicates the target agent’s (selected device’s) ability to complete the current data phase of the transaction. TRDY* is used in conjunction with IRDY*. During a read, TRDY* indicates that valid data is present on A/D[31:0]. During a write, it indicates the target is prepared to accept data. STOP* Stop (bi-directional) This signal indicates the current target is requesting the master to stop the current transaction. LOCK* Lock (bi-directional) This signal indicates an atomic operation to a bridge that may require multiple transactions to complete. IDSEL Initialization Device Select (input) Initialization Device Select is used as a chip select during configuration read and write transactions. ATF697FF [DATASHEET] 118 41000D−AERO03/14 DEVSEL* Device Select (bi-directional) When actively driven, indicates the driven device has decoded its address as the target of the current access. As an input, DEVSEL* indicates whether any device on the bus has been selected. 12.4.1.4 PCI Arbitration REQ* PCI bus request (output) This signal indicates to the arbiter that this agent desires use of the bus. This is a point-to-point signal. Every master has its own REQ* which is tri-stated while PCI reset is asserted. GNT* PCI Bus Grant (input) This signal indicates to the agent that access to the bus has been granted. This is a point-to-point signal. Every master has its own GNT* which is ignored while PCI reset is asserted. 12.4.1.5 PCI Error Reporting PERR* Parity Error (bi-directional) This signal is only for the reporting of data parity errors during all PCI transactions except a Special Cycle. The PERR* pin is sustained tri-state and must be driven active by the agent receiving data two clocks following the data when a data parity error is detected. The minimum duration of PERR* is one clock for each data phase that a data parity error is detected. SERR* System Error (open-drain bi-directional) This signal is for reporting address parity errors, data parity errors on the special cycle command, or any other system error where the result will be catastrophic. SERR* is pure open drain and is actively driven for a single PCI clock by the agent reporting the error. 12.4.2 Internal PCI arbiter The embedded PCI arbiter enables the arbitration of up to 4 PCI agents (numbered from 0 to 3). A round-robin algorithm is implemented as arbitration policy. Since the PCI interface arbitration logic is not connected internally to the PCI arbiter, the REQ* /GNT* signals shall be connected externally to one of the AREQ* []/AGNT* [] pairs of the arbiter so the PCI interface is arbitered amongst the other agents on the bus. The PCI interface can also be operated with an external PCI arbiter, thus not using the internal arbiter (the AREQ* [3:0] input signals shall then be tied to a high level). 12.4.2.1 Operation An agent on the PCI bus requests the bus by driving low one of the AREQ* [] signal. When the arbiter determines the bus can be granted to an agent, it drives low the corresponding AGNT* [] signal. The agent is only granted the PCI bus for one transaction. An agent willing further access to the bus shall continue to assert its AREQ* [] line and wait to be granted the bus again. 12.4.2.2 Policy The arbitration policy is based on a round-robin algorithm with two nested priority loops. A high priority loop is defined as level 0, a low priority loop is defined as level 1 Agents 0,1 and 2 can be individually configured to operate either on level 0 or on level 1 in the PCI Arbiter register (PCIA), whereas agent 3 operates on the fixed level 1 (low priority). ATF697FF [DATASHEET] 119 41000D−AERO03/14 Operation The arbitration is performed by checking the AREQ* [3:0] signals one after the other. In the first place, only agents with level 0 (high priority) are considered. If an agent asserts its AREQ* [] signal and the bus is not already granted, the corresponding AGNT*[] signal is driven low to grant the agent the bus. After a complete round-turn in level 0, a complete turn is done in level 1. The following figure illustrates the operation of the arbiter: Figure 12-1. Arbiter Operation Considering only agents submitting a request at the same time, the odds for being granted the bus can be summarized as follows: All agents in the same level have equal probability of grant All agents in level 1 have the same cumulated probability of grant as a single agent in level 0 Re-arbitration Re-arbitration occurs as soon as a transfer is finished and a new request is made (the PCI arbiter has internal knowledge of the FRAME* signal) or when no agent is requesting the bus anymore (leading to bus parking). Caution: No re-arbitration occurs during a transfer. Long bursts of one agent, even if assigned a low priority, can therefore significantly deteriorate the bandwidth available for other agents, especially the ones assigned a high priority. Caution: In time critical systems, splitting long bursts into smaller chunks shall be considered as a way to favor re-arbitration more often. Bus Parking As long as no bus request is active, the bus always remains granted (parked) to the last owner until another agent requests the bus. After reset, the bus is automatically granted (parked) to agent 0. 12.4.3 PCI pheripheral (ATF697FF processor’s side) 12.4.3.1 Overview The PCI interface implementation is compliant with the PCI specification revision 2.2. It is a high performance 32-bit bus interface with multiplexed address and data lines. It is intended for use as an internal interconnect mechanism between the processor and the reconfigurable unit. The PCI interface has initiator (master) and target capability, and data transfer can be in transmit or in receive direction from the processor to the reconfigurable unit. The PCI bus can be operated at a frequency up to 33 MHz independently of the processor and the reconfigurable unit clock. The PCI clock domain and the processor clock domain are fully decoupled, allowing the others clocks to be faster, equal or slower than the PCI clock. Data transfer is through 4 synchronizing data FIFOs of 8 words each: MXMT: master/initiator-transmit-FIFO (from initiator to target) ATF697FF [DATASHEET] 120 41000D−AERO03/14 MRCV: master-receive-FIFO (from target to initiator) TXMT: target-transmit-FIFO (from target to initiator) TRCV: target-receive-FIFO (from initiator to target) Depending on the configuration mode, the lower part of the PCI configuration registers can be accessed either locally in the register address space (address 0x80000100 to 0x80000144) or by another PCI device via the PCI bus with PCI configuration cycles and the IDSEL signal (the AT697 can never access its own configuration registers via the PCI bus). The upper part of the PCI configuration registers (0x80000148 to 0x80000178) and the PCI arbiter register PCIA (0x80000280) can only be accessed locally through the register address space. The configuration mode is selected by a hardware bootstrap on the SYSEN* pin. The following two modes are available: Host-Bridge (SYSEN* = 0) In host-bridge mode, the PCI registers at address 0x80000100 to 0x80000144 are only accessible locally by the processor, but not through the PCI bus. The host-bridge is sometimes also called System Controller, it controls other satellite devices through PCI configuration commands. Satellite (SYSEN* = 1) In satellite mode, the lower part of the processor PCI registers can be written and read by another PCI device (the hostbridge) using PCI configuration cycles, whereas the local registers addresses 0x80000100 to 0x80000144 are readonly. The state of the SYSEN* pin is available internally (PCIIS.sys) to enable a boot software to load the appropriate driver(s). Some other features are supported by this interface like: Target lock Target zero-latency fast back-to-back transfers Zero wait-state burst mode transfers Memory read line/multiple Memory write and invalidate Delayed read Flexible error reporting by polling 12.4.3.2 PCI Initiator (Master) PCI initiator transactions are issued by the processor either as memory-mapped load/store instructions or as DMAassisted data transfers between the PCI bus and the local memory. Load/store instructions to a memory address in the PCI area (0xA0000000 0xFFFFFFFF) are automatically translated by the interface into the appropriate PCI transaction. Any PCI address outside of this range can only be accessed via a DMA-assisted data transfer. The PCI initiator (memory-mapped or DMA-assisted) is enabled by setting bits PCISC.com2 and PCIIC.mod. Memory-Mapped Access Instructions of different width (byte, half-word, word or double-word) can be performed for each address of the PCI address range. The three least-significant bits of the address (A/D[2:0]) are used to determine which PCI byte-enable signals (C/BE*[3:0]) should be active during the transaction. According to the SPARC architecture, big-endian mapping is implemented where the most significant byte standing at the lower address (0x..00) and the least significant byte standing to the upper address (0x..03). ATF697FF [DATASHEET] 121 41000D−AERO03/14 Writing a byte to a PCI word-aligned address (A/D[1:0] = 00) results in the byte-enable pattern (C/BE*[3:0]= 0111) indicating the most significant byte lane (A/D [31:24]) of the PCI data bus is selected. For all sub-word load instructions using a PCI memory command, the byte enables are all-0s, assuming reading more bytes than necessary has no side effects on a prefetchable target. Non-prefetchable targets where exact read byteenables are required should be accessed with PCI I/O commands. Byte, half-word and word size load/store instructions are translated into a single word PCI transaction with the appropriate byte-enable pattern, while a double-word load/store instruction are translated into a 2-word burst PCI transaction. The following table presents the mapping between instructions and PCI byte enables generated for memory write and I/O read/write commands: 1. Table 12-2. Byte-Enable vs Instruction Bit Width 8 16 32 64 Instruction LDSB, LDUB, STB LDSH, LDUH, STH LD, ST LDD, STD Ai[2:0]=0004 0111 0011 Ai[1:0]=014 1011 n/a3 n/a Ai[1:0]=104 1101 1100 n/a Ai[1:0]=114 1110 n/a3 n/a Ai[2:0]=1004 0000 00002 n/a3 3 n/a 3 3 n/a 3 n/a 3 3 Note: 1.PCI byte-enables signals are active low (C/BE*[3:0]) Note: 2.Operation is performed as a single data burst transaction Note: 3.Improperly aligned access is cancelled and causes a mem_address_not_aligned trap (0x07) Note: 4.Ai is the source/destination memory address referenced by the load/store instruction Command Type The PCI command type to be used for memory-mapped transactions is set in PCIIC.cmd to one of IO-read/write, memory-read/write (default after reset), configuration-read/write(caution) or memory-read-line/write-invalidate. Memory commands are issued on the PCI bus with the 2 least significant bits of the address cleared (A/D [1:0] = 00) to indicate the linear incrementing mode is being used. Configuration(caution) and I/O commands are issued on the PCI bus with the address unchanged. Caution: Configuration transactions shall only be generated in host-bridge mode (SYSEN* pin tied to a low level). Operation 1. To engage memory-mapped transactions on the PCI interface: 2. Enable PCI initiator mode (PCISC.com2 = 1) and memory-mapped transactions (PCIIC.mod = 1). 3. Clear the PCI interrupt pending register (PCIITP = 0xF0). 4. In interrupt-assisted operation, enable any of the 4 possible PCI interrupt sources: SERR* asserted (PCIITE.SERR* = 1), initiator parity error (PCIITE.iper = 1), initiator fatal error (PCIITE.ife = 1) and/or initiator internal error (PCIITE.iier = 1). Interrupts shall be enabled as well in the processor (PSR.et = 1 and PSR.pil < 14) and the interrupt controller (ITMP.imask[14] = 1). ATF697FF [DATASHEET] 122 41000D−AERO03/14 5. The interrupt service routine (ISR) shall check the PCI interface status: SERR* asserted (PCIITP.SERR* = 1), initiator parity error (PCIITP.iper = 1), initiator fatal error (PCIITP.ife = 1) or initiator internal error (PCIITP.iier = 1) and clear each bit in software by rewriting a 1 as appropriate so further events can be detected. 6. Select the appropriate PCI command type (PCIIC.cmd). 7. Execute a load/store instruction on a local memory address mapped in the PCI address range (0xA0000000 to 0xFFFFFFFF). 8. If not using interrupts, check the PCI interface status: SERR* asserted (PCIITP.SERR* = 1), initiator parity error (PCIITP.iper = 1), initiator fatal error (PCIITP.ife = 1) and/or initiator internal error (PCIITP.iier = 1) then clear each bit as appropriate (in software by rewriting a 1) so further events can be detected. 9. Repeat steps 5 to 6 as many times as needed. 10. Repeat steps 4 to 7 as many times as needed with a new PCI command type. Limitations The following PCI features are not supported: PCI interrupt acknowledge, special cycles and memory read-multiple 64-bit addressing and Dual Address Cycles (DAC) Cacheline wrap mode with memory commands PCI power management. Master fast back-to-back transactions Direct Memory Access A DMA controller is available to perform data transfers between the local memory and a remote target on the PCI bus. The processor needs only initiate the transfer by programming the DMA controller. Once programmed, the DMA controller is fully autonomous and performs data transfers in the background while the processor is running. Interrupts are provided for synchronization. The DMA controller only performs word transfers with all 4 PCI byte-lanes enabled (C/BE*[3:0]= 0000). Operation To engage DMA-assisted transactions on the PCI interface: 1. 2. 3. 4. 5. 6. 7. 8. Enable PCI initiator mode (PCISC.com2 = 1) and DMA-assisted transactions (PCIIC.mod = 1). Clear the PCI interrupt pending register (PCIITP = 0xF0). In interrupt-assisted operation, enable any of the 5 possible PCI interrupts sources: DMA transfer finished (PCIITE.dmaf = 1), SERR* asserted (PCIITE.PCI_SERR = 1), initiator parity error (PCIITE.iper = 1), initiator fatal error (PCIITE.ife = 1) and/or initiator internal error (PCIITE.iier = 1). Interrupts shall be enabled as well in the processor (PSR.et = 1 and PSR.pil < 14) and the interrupt controller (ITMP.imask[14] = 1). The interrupt service routine (ISR) shall check the PCI interface status: DMA transfer finished (PCIITP.dmaf = 1), SERR* asserted (PCIITP.SERR* = 1), initiator parity error (PCIITP.iper = 1), initiator fatal error (PCIITP.ife = 1) and/or initiator internal error (PCIITP.iier = 1) then clear each bit as appropriate (in software by rewriting a 1) so further events can be detected. Define the start address in the PCI address space (PCISA). Define in a single write operation the PCI command and the number of words to be transferred (PCIDMA.cmd and PCIDMA.wcnt, 1 to 255 words). At this point for PCI read-based transactions, the PCI interface starts pre-fetching data from the PCI remote target. Define the start address in local memory (PCIDMAA). At this point, data transfer starts in local memory. Wait (interrupt or poll) for the transfer to finish (PCIITP.dmaf = 1). ATF697FF [DATASHEET] 123 41000D−AERO03/14 9. If not using interrupts, check the PCI interface status: SERR* asserted (PCIITP.SERR* = 1), initiator parity error (PCIITP.iper = 1), initiator fatal error (PCIITP.ife = 1) and/or initiator internal error (PCIITP.iier = 1) then clear each bit as appropriate (in software by rewriting a 1) so further events can be detected. 10. Repeat steps 4 to 8 as many times as needed. Limitations The following limitations shall be considered when using the DMA controller: Memory-mapped access and DMA are mutually exclusive: any load/store instruction to the PCI area in local memory (0xA0000000 0xFFFFFFFF) during a DMA transfer will stall the processor until the DMA transfer is completed. Moreover, a PCI memory-mapped access (like in an interrupt service routine) which occurs during the initiate procedure of the DMA transfer (between steps 3 to 5) will cause a deadlock requiring a reset of the processor. The application shall ensure the atomicity of steps 4 to 6. A wrong DMA initialization sequence may cause the DMA state machine to lock and report an error (PCIITP.iier = 1). The PCI interface shall then be reset (PCIIC = 0xFFFFFFFF). A DMA transfer cannot cross a 256 words aligned segment boundary in local memory. If the combination of the start address (PCISA) and the number of words to be transferred (PCIDMA.wcnt) is to cross that boundary, the DMA controller will terminate the transfer by the end of the segment (PCIITP.dmaf = 1), flush the FIFOs and report an error (PCIITP.iier = 1). A DMA transfer cannot operate within the PCI memory-mapped address range in local memory. If the local address of a DMA transfer lies in the PCI memory-mapped address range (0xA0000000 0xFFFFFFFF), the DMA controller will cancel the transfer and report an error (PCIITP.iier = 1). Configuration Access to a PCI target configuration address space requires the target device to be selected at its IDSEL pin. In many systems, the IDSEL pins of the satellite devices are directly connected to one of the A/D [31:11] signals. Memory-Mapped Because of the local memory address range limitation (0xA0000000 to 0xFFFFFFFF), the remote target IDSEL signal shall only be connected to lines from A/D [29:11]. This allows up to 19 PCI targets to be configured: the target connected to A/D [29] is selected with address 0xE0000xxx, A/D [28] with address 0xD0000xxx, A/D [27] with address 0xC8000xxx, A/D [26] with address 0xC4000xxx and so on. DMA-Assisted Any target connected to A/D [31:11] can be configured with the DMA controller. 12.4.3.3 PCI Target PCI target transactions originate from remote PCI initiators (masters) to the PCI interface. The processor needs only configure the interface by programming the target controller. Once programmed, the target controller is fully autonomous and performs data transfers in the background while the processor is running. Interrupts are provided for synchronization. Interface Setup The target interface is programmed as follows1: Enable/Disable1. parity error checks on the PCI interface (PCISC.com6). Enable/Disable12 remote access to target I/O Space (PCISC.com0). Enable/Disable12 remote access to target Memory Space (PCISC.com1). If enabled, set1 the base address to each 16 MB target memory area in the PCI address space (MBAR1.badr & MBAR2.badr) and in local memory (PCITPA.tpa1 & PCITPA.tpa2). ATF697FF [DATASHEET] 124 41000D−AERO03/14 If enabled, set1 the base address to the 1024 bytes target I/O area in the PCI address space (IOBAR3.badr). Base address in local memory is not programmable (PCITPA.tpa3) and is mapped to the AT697 configuration registers (0x80000000 0x80000400). Enable/Disable the storage in local memory of remote data received with PCI parity error (PCITSC.rfpe). If disabled, data received with a parity error will be discarded. Note: 1.The PCI configuration registers with writable bits (PCISC, PCIBHLC, MBAR1, MBAR2, IOBAR3, PCILI, PCIRT & PCICW) can only be programmed by the processor when in Host-Bridge mode (SYSEN* = 0), while they can only be programmed by the remote host-bridge when in Satellite mode (SYSEN* = 1). Note: 2.The other PCI target registers (PCITSC & PCITPA) are always and only accessible by the processor. Note: 3.At least one of target Memory Space (PCISC.com1) and target I/O Space (PCISC.com0) shall be enabled for target operation Caution: If the PCI target is to share any data with the processor while the data cache is active ( CCR.dcs = 01 or 11), care shall be taken to first enable the data cache snooper (CCR.ds = 1) or flush the data cache (CCR.fd = 1) when appropriate. Caution: If the PCI target is to provide any instruction to the processor to execute while the instruction cache is active (CCR.ics = 01 or 11), care shall be taken to flush the instruction cache (CCR.fi = 1) when appropriate. Limitations The following limitations shall be considered when using the PCI target: The PCI target cannot operate within the PCI memory-mapped address range in local memory. If the programmed target local address (PCITPA) lies in the PCI memory-mapped address range (0xA0000000 0xFFFFFFFF), the target controller will cancel the transfer and report an error (PCIITP.tier = 1). Target read transactions assume the target space to be prefetchable (reading from an address does not alter the data) and target Memory Read and I/O Read commands are generally prefetched. The target controller prefetches up to 8 words into the transmit FIFO once the target read address is available. After the last required data word is transferred to the PCI interface, the FIFO is automatically flushed to discard any unused prefetched data. This behavior shall be considered if a non-prefetchable device (like a UART) is to be read through the PCI target interface. The interface supports the following PCI write byte-enable patterns (C/BE*[3:0]): single-byte (0111, 1011, 1101 & 1110), half-word (0011 & 1100), word (0000) and ignore-data (1111, frequently used as a dummy write cycle). A data received with any other byte-enable pattern is discarded and an error is reported (PCIITP.tber = 1). Delayed-Read As specified in the PCI standard, delayed-read functionality is implemented as follows: When a read request was retried (because data from local memory is not available yet), the interface remains locked for any other target read (targeting different addresses). The initiator of the original read is expected to later repeat the request to the same address. A delayed-read can however be interrupted by one or more PCI write accesses. The PCI standard requires each write command to be processed first so to prevent a system lock-up. Meanwhile, the interface prefetches read-data from local memory into the target-transmit FIFO (TXMT). When the read request is repeated (after the interfering write, if any), the requested data is available in the FIFO and the delayed-transfer completes normally. ATF697FF [DATASHEET] 125 41000D−AERO03/14 12.4.3.4 PCI Error Reporting Parity check, parity error signal (PERR*) and system error signal SERR*) are implemented as foreseen by the PCI standard. They can be controlled in the combined PCI Command & Status register (PCISC). In addition, PCI initiator and PCI target error conditions and status information are always reported1 in PCIITP (PCI Interrupt Pending). If also enabled in PCIITE (PCI Interrupt Enable), each error condition or status information set by the PCI core in PCIITP will trigger the PCI interrupt (ITP.ipend[14] = 1) if enabled in the interrupt controller (ITMP.imask[14] = 1). Interrupts shall then be enabled as well in the processor (PSR.et = 1 and PSR.pil < 14) so the event can be handled. For testing purpose, the error condition and status information can also be forced in PCIITP by setting the corresponding bit in PCIITF (PCI Interrupt Force). Note: 1. These bits are never cleared in hardware and shall be cleared in software (by rewriting a 1) so new events can later be registered. Status information of the various data FIFOs and state machines is available in PCIIS (PCI Initiator Status) and PCITSC (PCI Target Status). It is recommended to check these registers for idle state when configuring the PCI interface and before performing any transaction. Non-nominal values may indicate a previous transaction was not properly completed and spurious data possibly remains in the FIFOs. In such a case, the PCI initiator interface shall be reset (PCIIC = 0xFFFFFFFF) and/or the PCI target interface shall be reset (PCITSC.cs = 0xF), its FIFOs flushed (PCITSC.xfe = 1 and/or PCITSC.rfe = 1) and the transaction aborted (PCITSC.xff = 1). 12.4.3.5 PCI Data Rate During PCI initiator and target transfers, the interface tries PCI burst transactions whenever possible to approach the theoretical PCI data rate (~1 Gbit/s at 33 MHz). However, the exact scheduling of PCI transactions depends on so many factors (clock ratio between PCI and processor, PCI bus traffic, PCI arbitration, processor internal bus activity, wait-states on external memory & I/O peripherals...) there is no guarantee for a sustained burst. The effective data rate may even be far below the theoretical performance in some specific situations. For a reasonable performance: the processor clock frequency should be at least 3 times the PCI clock frequency processor accesses to slow devices (IO or memory with high wait-states) should be minimized 12.4.3.6 Disabling the PCI In applications where the PCI function is not used, the PCI_CLK and the PCI_RST* pin shall be tied to a low level. As a consequence, all bidirectional PCI pins including the bus request pin REQ* are tri-stated so they shall be driven to a valid high/low level with a pull-up/down to prevent them from floating. When the PCI arbiter is not used, the AREQ*[3:0]input signals shall be tied to a high level. 12.4.4 PCI Interface The whole PCI signals shared between the ATF697FF processor and the ATF697FF reconfigurable unit are listed next. ATF697FF [DATASHEET] 126 41000D−AERO03/14 Table 12-3. PCI interface shared signals Processor Pin name Reconfigurable unit Pin Name Reconfigurable unit Pin direction Processor Pin name Reconfigurable unit Pin Name A/D[0] A/D[1] A/D[2] A/D[3] A/D[4] A/D[5] IO137 IO139 IO143 IO145 IO147 IO151 Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional A/D[30] A/D [31] AGNT*[0] AGNT*[1] AGNT*[2] AGNT*[3] IO227 IO231 IO245 IO247 IO251 IO253 A/D[6] IO153 Bi-directional AREQ*[0] IO257 A/D[7] IO157 Bi-directional AREQ*[1] IO263 A/D[8] IO159 Bi-directional AREQ*[2] IO267 A/D[9] IO163 Bi-directional AREQ*[3] IO271 A/D[10] A/D[11] A/D[12] A/D[13] A/D[14] A/D[15] A/D[16] A/D[17] A/D[18] A/D[19] A/D[20] A/D[21] A/D[22] A/D[23] A/D[24] A/D[25] A/D[26] A/D[27] A/D[28] A/D[29] IO165 IO167 IO171 IO173 IO175 IO177 IO180 IO185 IO187 IO191 IO193 IO197 IO199 IO203 IO205 IO207 IO213 IO217 IO219 IO223 Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional Bi-directional C/BE*[0] C/BE*[1] C/BE*[2] C/BE*[3] PCI_CLK DEVSEL* FRAME* GNT* SYSEN* IDSEL IRDY* LOCK* PAR PERR* REQ* PCI_RST* SERR* STOP* TRDY* IO273 IO277 IO279 IO283 IO285 IO287 IO291 IO293 IO297 IO299 IO305 IO307 IO311 IO313 IO317 IO319 IO323 IO325 IO327 Caution: Reconfigurable unit Pin direction Bi-directional Bi-directional Input, pull up enable Input, pull up enable Input, pull up enable Input, pull up enable Output, pull up enable Output, pull up enable Output, pull up enable Output, pull up enable Bi-directional Bi-directional Bi-directional Bi-directional Output Bi-directional Bi-directional Output Output Output Bi-directional Bi-directional Bi-directional Bi-directional Input Output Bi-directional Bi-directional Bi-directional Warning: These shared IO have to be correctly configurated to avoid signal reflexions and damages on the IOs of the ATF697FF component. ATF697FF [DATASHEET] 127 41000D−AERO03/14 12.4.5 To launch an internal PCI transaction between the processor and the reconfigurable unit The IO285 signal should be configurated in output and generate the 33 MHz PCI_CLK clock. The whole PCI agents should be configured as Host bridge or as Satellite: To configure the processor as a HOST, IO297 should be in output mode, driven at ‘0’. The reconfigurable unit is configurated in SATELLITE, as returns. To configure the processor as a SATELLITE, IO297 should be in output mode, driven at ‘1’. The reconfigurable unit is configurated in HOST, as returns. The HOST should launch an identification to determine the other agents existing on the PCI bus. The HOST should program the configuration space of the PCI satellite device. At this state, the network is configurated. The initiator could now launch a transaction in memory mapped (MM) or in Direct Memory Access (DMA) mode on the PCI bus. The target will respond to the PCI transaction. ATF697FF [DATASHEET] 128 41000D−AERO03/14 13. Clock system 13.1 Clock: processor part 13.1.1 Overview The ATF697FF processor operates two clocks domains: the CPU clock and the PCI clock. The following figure presents the clock system of the processor and its distribution. Figure 13-1. Clock Distribution Note: The PLL is powered-down when the BYPASS signal is asserted. 13.1.2 PCI Clock The PCI clock is dedicated to the PCI Interface. It is used in particular by the PCI wrapper that shares its activity between the two clock domains. 13.1.2.1 External Clock The PCI interface and its associated wrapper can only be driven from an external clock. The PCI clock shall be connected to the PCI_CLK pin of the PCI interface. This input shall be driven at a frequency in the range of 0 up to 33 MHz. 13.1.3 CPU Clock The CPU clock is routed to the parts of the system concerned with operation of the SPARC core. Examples of such modules are the CPU core itself, the register files... The CPU clock is also used by the majority of the I/O modules like Timers, Memory controller, Interrupt Controller, with the exception of the PCI Interface. ATF697FF [DATASHEET] 129 41000D−AERO03/14 The CPU clock is driven either directly by an external oscillator or by the internal PLL. 13.1.3.1 External Clock To drive the device directly from an external clock source, the CLK input shall be driven by an external clock generator while the BYPASS pin is driven high. In that way, the CPU clock is the direct representation of the clock applied to CLK. When the external CPU clock source is selected, the clock input can be driven at a frequency in the range of 0 MHz up to 100 MHz. 13.1.3.2 PLL The CPU clock can be issued from the internal PLL. Overview The PLL contains a phase/frequency detector, charge pump, voltage control oscillator, low-pass filter, lock detector and divider. Figure 13-2. PLL Block Diagram The PLL implemented is configured in hardware to provide an internal clock frequency of four times the frequency of the input clock. PLL control The PLL control is performed in hardware through dedicated pins. The following table presents the assignement and functions of the PLL control pins. Table 13-1. PLL Ports Description Pin name Function LOCK The PLL is locked and delivers the expected internal clock CLK External clock input ATF697FF [DATASHEET] 130 41000D−AERO03/14 Pin name Function BYPASS Bypass the internal PLL and directly drive the internal clock from CLK Operation To drive the device from the internal PLL, the CLK input shall be driven by an external clock generator while the BYPASS pin is driven low. That way, the CPU clock frequency is four times the frequency of the clock applied to CLK. When the PLL is enabled, the CLK clock input shall be driven at a frequency in the range of 18 MHz up to 25 MHz. 13.1.4 Fault-Tolerance & Clock To protect against SEU errors (Single Event Upset), each on-chip register is implemented using triple modular redundancy (TMR). Moreover, an independent clock tree is used for each of the three registers making up one TMR module. This feature protects against SET errors (Single Event Transient) in the clock tree, to the expense of increased routing. The CPU clock and the PCI clock are built as three-clock trees. To prevent erroneous operations from single event upset (SEU) errors and single event upset (SEU), the ATF697FF processor is based on full triple modular redundancy (TMR) architecture. Figure 13-3. TMR structure Such architecture is based on a fully triplicated clock distribution (CLK1, CLK2 and CLK3). In that way, each one of the PCI clock and the cpu clock are build as three-clock trees. 13.1.4.1 Skew To prevent the processor from corruption by SET errors (Single Event Transient), skew can be programmed on the clock trees. The two dedicated pins SKEW[1:0] are used to control the skew on the clock trees. Here is a short description of the skew implementation: ATF697FF [DATASHEET] 131 41000D−AERO03/14 Figure 13-4. CPU clock tree overview Three configurations are available: natural skew (SKEW[1:0] = 00), this is the standard clock-tree as routed internally medium skew (SKEW[1:0] = 01), the 3 clock-trees are shifted away in time one from each other maximum skew (SKEW[1:0] = 10), the 3 clock-trees are further shifted away in time Table 13-2. SKEW Assignements SKEW[1:0] DELAY Comments CLK1 -> CLK2 CLK1 -> CLK3 00 natural natural natural skew 01 D1 D3 medium skew 10 D1 + D2 D3 + D4 maximum skew 11 reserved (shall not be used) Note: Medium skew and maximum skew configurations improve SET protection but lead to reduced operating performance: maximum clock frequency is reduced and timings are slower than when configured for natural skew (see "Electrical Characteristics"). ATF697FF [DATASHEET] 132 41000D−AERO03/14 Clock: reconfigurable unit part The ATF697FF reconfigurable unit clock system consists in a fully SET hardened clocking scheme. It provides user with two types of clock 8 Global Clocks 1 Fast Clocks : FCK3 – FCK4 (the both clocks are multiplexed.) Each column of an array has a “Column Clock mux” and a “Sector Clock mux”. The Column Clock mux is at the top of every column of an array and the Sector Clock mux is at every four cells. The Column Clock mux is selected from one of the eight Global Clock buses. The clock provided to each sector column of four cells is inverted, non-inverted or tied off to “0”, using the Sector Clock mux to minimize the power consumption in a sector that has no clocks. The clock can either come from the Column Clock or from the Plane 4 express bus. The extreme-right Column Clock mux has two additional multiplexed inputs as well, FCK3 and FCK4, to provide fast clocking to I/Os. The register in each cell is triggered on a rising clock edge by default. Before configuration at power-up, constant “0” is provided to each register’s clock pins. After configuration at power-up, the registers either set or reset, depending on the user’s choice. The clocking scheme is designed to allow efficient use of multiple clocks with low clock skew, both within a column and across the core cell array. Refer to Registers section about GCK and FCK activation or deactivation using IDS tools. All GCK and FCK lines are activated by default. Figure 13-5. FPGA Clock repartition by column R O W S N …………... N-1 NORTH …………... …………... …………... …………... …………... …………... …………... 2 …………... 1 …………... W E S T …………... …………... N-1 N E A S T …………... …………... 2 …………... 1 …………... 13.2 COLUMNS SOUTH ATF697FF [DATASHEET] 133 41000D−AERO03/14 GCK1 GCK2 GCK3 GCK4 GCK5 GCK6 GCK7 GCK8 FCK3 FCK4 GCK1 GCK2 GCK3 GCK4 GCK5 GCK6 GCK7 GCK8 GCK6 GCK7 GCK8 FCK1 FCK2 GCK1 GCK2 GCK3 GCK4 GCK5 Figure 13-6. Column Clocking Overview Mux Mux Mux Clock Column 1 Clock Column N Clock Column 13.2.1 Global Clock Each of the eight dedicated Global Clock buses is connected to one of the dual-use Global Clock pins. Any clocks used in the design should use global clocks where possible. These signals are distributed across the top edge of the FPGA along special high-speed buses. Global Clock signals can be distributed throughout the overall FPGA with less than 1 ns skew. This can be done by using Assign Pin Locks command in the IDS software to lock the clocks to the Global Clock locations. 13.2.2 Fast Clock The fast clocks are used to provide fast clocking on the first/last stage of a structure close to the pad of the devices. They are only accessible on the far east/west area of the FPGA. There are 2 Fast Clocks inputs (FCK3 FCK4) on the ATF697FF. Even the derived clocks can be routed through the Global network. Access points are provided in the corners of the array to route the derived clocks into the global clock network. On the extreme east of the device, FCK3 and FCK4 inputs are internally multiplexed. This allows use of a fast clocking for the east-side I/Os. FCK3 and FCK4 are multiplexed: only one of these two FCKs can be used at a time. The IDS software tools handle derived clocks to global clock connections automatically if used. 13.3 Reset System: reconfigurable unit part The ATF697FF reconfigurable unit reset scheme is essentially the same as the clock scheme except that there is only one differential Global Reset. A dedicated Global Set/Reset bus can be driven by any User I/O, except those used for clocking (Global Clocks or Fast Clocks). Like the clocking scheme, set/reset scheme is SET hardened. The automatic placement tool will choose the reset net with the most connections to use the global resources. You can change this by using an RSBUF component in your design to indicate the global reset. Additional resets will use the express bus network. The Global Set/Reset is distributed to each column of the array. Like Sector Clock mux, there is Sector Set/Reset mux at every four cells. Each sector column of four cells is set/reset by a Plane 5 express bus or Global Set/Reset using the Sector Set/Reset mux (Figure 10). The set/reset provided to each sector column of four cells is either inverted or noninverted using the Sector Reset mux. The function of the Set/Reset input of a register is determined by a configuration bit in each cell. The Set/Reset input of a register is active low (logic 0) by default. Setting or Resetting of a register is asynchronous. Before configuration on power-up, a logic 1 (a high) is provided by each register (i.e., all registers are set at power-up). ATF697FF [DATASHEET] 134 41000D−AERO03/14 Figure 13-7. Set/Reset ATF697FF [DATASHEET] 135 41000D−AERO03/14 14. 14.1 Debug interface: DSU Caution: This chapter is for information purpose only. Caution: As its name clearly states, the Debug Support Unit is exclusively meant for debugging purpose. None of the DSU features shall ever be used in the final application where the DSU shall be turned into an inactive state (DSUEN, DSURX and DSUBRE tied to a permanent low level). Overview The ATF697FF processor includes a hardware debug support unit to aid in software debugging in the final application. The support is provided through two modules: a debug support unit (DSU) and a debug communication link (DCL). The DSU can put the processor in debug mode, allowing read/write access to all processor registers and cache memories. The DSU also contains a trace buffer which stores executed instructions or data transfers on the internal bus. The debug communications link implements a simple read/write protocol and uses standard asynchronous UART communications. Figure 14-1. Debug Support Unit and Communication Link It is possible to debug the processor through any master on the internal bus. The PCI interface is build in as a master on the internal bus. All debug features are available from any PCI master. 14.2 Debug Support Unit The debug support unit is used to control the trace buffer and the processor debug mode. The DSU master occupies a 2 MB address space on the internal bus. Through this address space, any other masters like PCI can access the processor registers and the contents of the trace buffer. The DSU control registers can be accessed at any time, while the processor registers and caches can only be accessed when the processor has entered debug mode. The trace buffer can be accessed only when tracing is disabled or completed. In debug mode, the processor pipeline is held and the processor is controlled by the DSU. Debug mode can only be entered when the debug support unit is enabled through an external pin (DSUEN). Driving the DSUEN pin high enables the debug support unit. Entering debug mode occurs on the following events (provided the appropriate setup was performed, see notes): executing a breakpoint instruction (ta 1)1 ATF697FF [DATASHEET] 136 41000D−AERO03/14 integer unit hardware breakpoint/watchpoint hit (trap 0x0B)2 rising edge of the external break signal (DSUBRE) 2 setting the break-now bit (DSUC.bn = 1)2 a trap that would cause the processor to enter error mode3 occurrence of any, or a selection of traps as defined in the DSU control register4 after a single-step operation5 DSU breakpoint hit6 instead of entering Error Mode7 Note: 1.Only after the break-on-S/W-breakpoint was set (DSUC.bs = 1) Note: 2.Only after the break-on-IU-watchpoint was set (DSUC.bw = 1) Note: 3.Only after the break-on-error-traps was set (DSUC.bz = 1) Note: 4.Only after the break-on-trap was set (DSUC.bx = 1) Note: 5.Only after the single-step was set (DSUC.ss = 1) Note: 6.Only after the break-on-DSU-breakpoint was set (DSUC.bd = 1) Note: 7.Only after the break-on-error was set (DSUC.be = 1) When debug mode is entered, the following actions are taken: PC and nPC are saved in temporary registers (accessible by the debug unit) an output signal (DSUACT) is asserted to indicate the debug state the timer unit is (optionally) stopped to freeze the ATF697FF processor timers and watchdog The instruction that caused the processor to enter debug mode is not executed, and the processor state is kept unmodified. Execution is resumed by clearing the break-now bit (DSUC.bn = 0) or by de-asserting DSUEN. The timer unit will be re-enabled and execution will continue from the saved PC and nPC. Debug mode can also be entered after the processor has entered error mode, for instance when an application has terminated and halted the processor. The error mode can be cleared and the processor restarted at any address. 14.2.1 DSU Breakpoint The DSU contains two breakpoint registers for matching either internal bus addresses or executed processor instructions. A breakpoint hit is typically used to freeze the trace buffer, but can also put the processor in debug mode. Freeze operation can be delayed by programming the trace buffer delay counter (DSUC.dcnt) to a non-zero value. In this case, the trace buffer delay counter value (DSUC.dcnt) is decremented for each additional trace until it reaches zero, after which the trace buffer is frozen. If the break on trace freeze bit is set (DSUC.bt = 1), the DSU forces the processor into debug mode when the trace buffer is frozen. Note: Due to pipeline delays, up to 4 additional instruction can be executed before the processor is placed in debug mode. A mask register is associated with each breakpoint, allowing breaking on a block of addresses. Only address bits with the corresponding mask bit set to ‘1’ are compared during breakpoint detection. 14.2.2 Time Tag The DSU implements a time tag counter. The time tag counter is incremented each clock as long as the processor is running. The counter is stopped when the processor enters debug mode, and restarted when execution is resumed. The time tag counter is stored in the trace as an execution time reference. ATF697FF [DATASHEET] 137 41000D−AERO03/14 14.2.3 Trace Buffer The trace buffer consists in a circular buffer that stores the executed instructions and/or the internal bus data transfers. The size of the trace buffer is 512 lines of 16 bytes. The trace buffer operation is controlled through the DSU control register (DSUC) and the trace buffer control register (TBCTL). When the processor enters debug mode, tracing is suspended. The trace buffer can contain the executed instructions, the transfers on the internal bus or both (mixed-mode). The trace buffer control register (TBCTL) contains an instruction trace index counter (TBCTL.icnt) and an internal bus trace index counter (TBCTL.bcnt) that store the address of the trace buffer location that will be written on next trace. Since the buffer is circular, they actually point to the oldest entry in the buffer. The index counters are automatically incremented after each stored trace entry. The trace buffer operation is controlled as follows: Tracing can be globally enabled/disabled (DSUC.te) Instruction tracing can be enabled/disabled (TBCTL.ti) Internal bus tracing can be enabled/disabled (TBCTL.ta) Internal bus trace freeze on entry into debug mode can be enabled/disabled (TBCTL.af) 14.2.3.1 Instruction trace When instruction tracing is enabled (TBCTL.ti = 1), one instruction is stored per line in the trace buffer with the exception of multi-cycle instructions. Multi-cycle instructions can be entered two or three times in the trace buffer: For store instructions, bits [95.64] correspond to the store address on the first entry and to the stored data on the second entry (and third in case of STD). Bit 126 is set logical one on the second and third entry to indicate this. A double load (LDD) is entered twice in the trace buffer, with bits [95.64] containing the loaded data. Multiply and divide instructions are entered twice, but only the last entry contains the result. Bit 126 is set for the second entry. For FPU operation producing a double-precision result, the first entry contains the most-significant 32 bits of the results in bits [63:32] while the second entry contains the least-significant 32 bits in bits [63:32]. Table 14-1. Instruction Trace Buffer Line Allocation Bits Name 127 Instruction hit 126 Multi-cycle instruction Set to ‘1’ on the second and third instance of a multi-cycle instruction (LDD, ST or FPop) 125:96 Time tag counter The value of the DSU time tag counter 95:64 Load/Store parameters Instruction result, store address or store data 63:34 Program counter Program counter (2 lsb bits removed since they are always zero) 33 Instruction trap Set to ‘1’ if traced instruction trapped 32 Processor error mode Set to ‘1’ if the traced instruction caused processor error mode 31:0 Opcode Instruction opcode Note: Definition breakpoint Set to ‘1’ if a DSU instruction breakpoint hit occurred. When a trace is frozen, a watchpoint_detected trap (0x0B) is generated. ATF697FF [DATASHEET] 138 41000D−AERO03/14 14.2.3.2 Bus Trace When internal bus tracing is enabled (TBCTL.ta = 1), one internal bus operation is stored per line in the trace buffer. Table 14-2. Internal Bus Trace Buffer Line Allocation Bits Name Definition 127 AHB breakpoint hit Set to ‘1’ if a DSU AHB breakpoint hit occurred. 126 - Unused 125:96 DSU counter The value of the DSU counter 95:92 IRL Processor interrupt request input 91:88 PIL Processor interrupt level (PSR.pil) 87:80 Trap type Processor trap type (PSR.tt) 79 Hwrite AHB HWRITE* 78:77 Htrans AHB HTRANS 76:74 Hsize AHB HSIZE 73:71 Hburst AHB HBURST 70:67 Hmaster AHB HMASTER 66 Hmastlock AHB HMASTLOCK 65:64 Hresp AHB HRESP 63:32 Load/Store data AHB HRDATA or HWDATA 31:0 Load/Store address AHB HADDR 14.2.3.3 Mixed Trace In mixed mode, the buffer is divided in two halves, with instructions stored in the lower half and bus transfers in the upper half. The most-significant bit of the internal bus trace index counter is then automatically kept high, while the most-significant bit of the instruction trace index counter is kept low. 14.2.4 DSU Memory Map Table 14-3. DSU Map Address Register 0x90000000 DSU control register 0x90000004 Trace buffer control register 0x90000008 Time tag counter 0x90000010 AHB break address 1 0x90000014 AHB mask 1 0x90000018 AHB break address 2 ATF697FF [DATASHEET] 139 41000D−AERO03/14 0x9000001C AHB mask 2 0x90010000 0x9001FFFC Trace buffer 0x9001...0 Trace bits 127 96 0x9001...4 Trace bits 95 64 0x9001...8 Trace bits 63 32 0x9001...C Trace bits 31 0 0x90020000 0x9003FFFC IU/FPU register file 0x90080000 0x900FFFFC IU special purpose registers 0x90080000 Y register 0x90080004 PSR register 0x90080008 WIM register 0x9008000C TBR register 0x90080010 PC register 0x90080014 nPC register 0x90080018 FSR register 0x9008001C DSU trap register 0x90080040 ASR16 0x90080060 0x9008007C ASR24 ASR31 0x90100000 0x9013FFFC Instruction cache tags 0x90140000 0x9017FFFC Instruction cache data 0x90180000 0x901BFFFC Data cache tags 0x901C0000 0x901FFFFC Data cache data The IU/FPU registers address depends on the number of register windows implemented. The registers are accessed at the following addresses (WINDOWS = total number of implemented SPARC register windows = 8, 0 ≤ window < WINDOWS): %on: 0x90020000 + (((window × 64) + 32 + 4×n) mod (WINDOWS × 64)) %ln: 0x90020000 + (((window × 64) + 64 + 4×n) mod (WINDOWS × 64)) %in: 0x90020000 + (((window × 64) + 96 + 4×n) mod (WINDOWS × 64)) %gn: 0x90020000 + (WINDOWS × 64) + 128 + 4×n %fn: 0x90020000 + (WINDOWS × 64) + 4×n ATF697FF [DATASHEET] 140 41000D−AERO03/14 14.2.5 Debug Operations 14.2.5.1 Instruction Breakpoints To insert instruction breakpoints, the breakpoint instruction (ta 1) should be used. This will leave the four IU hardware breakpoints free to be used as data watchpoints. Since cache snooping is only perfomed on the data cache, the instruction cache must be flushed after the insertion or removal of breakpoints. To minimize the influence on execution, it is enough to clear the corresponding instruction cache tag (which is accessible through the DSU). The DSU hardware breakpoints should only be used to freeze the trace buffer, and not for software debugging since there is a 4-cycle delay from the breakpoint hit before the processor enters the debug mode. 14.2.5.2 Single Stepping When single-stepping is enabled (TBCTL.ss = 1), clearing the break-now bit (TBCTL.bn = 0) resumes processor execution for one instruction and then automatically re-enters debug mode. 14.2.6 DSU Trap The DSU trap register (DTR) consists in a read-only register that indicates which SPARC trap type caused the processor to enter debug mode. When debug mode is forced by asserting the break-now bit (TBCTL.bn = 1), a watchpoint_detected trap (0x0B) is generated. 14.3 DSU Communication Link DSU communication link consists of a UART connected to the internal bus as a master. Figure 14-2. DSU Communication Link Block Diagram A simple communication protocol is supported to transmit access parameters and data. A link command consist of a control byte, followed by a 32-bit address, followed by optional write data. If the DSU link response is enabled (DSUC.lr = 1), a response byte is sent after each read/write access. If disabled, a write access does not return any response, while a read access only returns the read data. 14.3.1 Data Frame A DSU data frame consists in a start bit, 8 data bits and a stop bit.. Figure 14-3. DSU UART Data Frame ATF697FF [DATASHEET] 141 41000D−AERO03/14 14.3.2 Commands Through the communication link, a read or write transfer can be generated to any address on the internal bus. A response byte is can optionally be sent when the processor goes from execution mode to debug mode. Block transfers can be performed be setting the length field to n-1, where n denotes the number of transferred words. For write accesses, the control byte and address is sent once, followed by the number of data words to be written. The address is automatically incremented after each data word. For read accesses, the control byte and address is sent once and the corresponding number of data words is returned. Figure 14-4. DSU Command 14.3.3 Clock Generation The UART contains an 16-bit down-counting scaler to generate the desired baud-rate. The scaler counter is clocked by the system clock and generates a UART tick each time it underflows. The counter is reloaded with the value of the UART scaler reload register (DSUUR.rv) after each underflow. The resulting UART tick frequency is 8 times the desired baud-rate. If not programmed in software, the baud-rate is automatically discovered. This is done by searching for the shortest period between two falling edges of the received data (corresponding to two bit periods). When three identical two-bit periods has been found, the corresponding scaler reload value is latched into the reload register (DSUUR.rv), the baudrate locked bit is set (DSUUC.bl = 1) and the UART is enabled (DSUUC.uen = 1). If the baud-rate locked bit is cleared in software (DSUUC.bl = 0), the baud-rate discovery process is restarted. The baud-rate discovery is also restarted when a break is detected on the serial line by the receiver, allowing to change the baud-rate from the external transmitter. For proper baud-rate detection, a break followed by the value 0x55 should be transmitted to the receiver. The best scaler value for manually programming the baudrate can be calculated as follows: scalerrv sdclk freq 1 baudrate 8 sdclk freq baudrate 8 scalerrv 1 ATF697FF [DATASHEET] 142 41000D−AERO03/14 14.4 Booting from DSU By asserting DSUEN and DSUBRE at reset time, the processor will directly enter debug mode without executing any instructions. The system can then be initialized from the communication link, and applications can be downloaded and debugged. Additionally, external (flash) PROMs for standalone booting can be re-programmed. 14.5 JTAG The processor part and the reconfigurable unit part embed the JTAG functionality. However, the JTAG functionality is not accessible on the ATF697FF due to the product implementation. Caution: In order to completely deactivate the JTAG functionality for the final application, the following steps shall be performed: The pin 94 shall be connected to VSS. The pin 131 shall be connected to VSS. The pin 133 shall be connected to VSS. The pin 134 shall be connected to VSS. In the configuration register of the reconfigurable unit, the CR5 bit field shall be set at ‘1’. ATF697FF [DATASHEET] 143 41000D−AERO03/14 15. Register Description Table 15-1. Register Legend Address: Bit Number 0x01010101 31 30 29 28 27 26 25 24 23 ... ... ... ... 9 8 7 6 5 4 3 2 1 0 field name field reserved access type r = read-only w = write-only r/w = read & write x = undefined or non affected by reset p = depends on the value of one or more external pins default value after reset 0 100 1 bit Note: All registers are equally accessible in user and supervisor mode. Note: Reserved fields usually are read-only (unless specified otherwise) and writing them usually has no side effects (unless specified otherwise) but should better be done with their default value for compatibility with possible use of the field in future revisions of the product. Note: Writing to read-only fields or registers has no effect. ATF697FF [DATASHEET] 144 41000D−AERO03/14 Integer Unit Registers 15.1 0000 Bit Number Mnemonic Description 31..28 impl Implementation Implementation or class of implementations of the architecture. 27..24 ver 23 n 22 z 21 v c 13 ec 12 ef x x x x r/w 1 x 0 0 1 2 3 4 5 xxxx 0000 s et x r 6 x 8 0000 00 9 10 r/w pil 11 14 15 16 17 18 r r / w r 20 r/w r / w reserved ps c 7 v 12 z ef n 13 icc 19 20 21 22 23 24 25 ver ec impl 26 27 28 29 30 31 Table 15-2. Processor State Register PSR cwp r r/w 00 xxx Version Identify one or more particular implementations or is a readable and writable state field whose properties are implementation-dependent. Negative Indicates whether the 32-bit 2’s complement ALU result was negative for the last instruction that modified the icc field (1 = negative, 0 = not negative). Zero Indicates whether the 32-bit ALU result was zero for the last instruction that modified the icc field (1 = zero, 0 = nonzero). Overflow Indicates whether the ALU result was within the range of (was representable in) 32-bit 2’s complement notation for the last instruction that modified the icc field (1 = overflow, 0 = no overflow) Carry Indicates whether a 2’s complement carry out (or borrow) occurred for the last instruction that modified the icc field. Carry is set on addition if there is a carry out of bit 31: Carry is set on subtraction if there is borrow into bit 31 (1 = carry/borrow, 0 = no carry/borrow). Enable Coprocessor Determines whether the implementation-dependent coprocessor is enabled (1 = enabled, 0 = disabled). If disabled, a coprocessor instruction will trap. Although this bit is marked as read/write, this implementation has no coprocessor and will always behave as the coprocessor is permanently disabled. Enable Floating-Point Determines whether the FPU is enabled (1 = enabled, 0 = disabled). If disabled, a floatingpoint instruction will trap. ATF697FF [DATASHEET] 145 41000D−AERO03/14 Bit Number Mnemonic Description 11..8 pil Processor Interrupt Level Identify the interrupt level above which the processor will accept an interrupt. Interrupt 15 is not maskable (NMI) in the IU and is always accepted whatever the current processor interrupt level (however, interrupt masking is still possible in ITMP). 7 s Supervisor Determines whether the processor is in supervisor or user mode (1 = supervisor mode, 0 = user mode). 6 ps Previous Supervisor Contains the value of the s bit at the time of the most recent trap. 5 et 4..0 cwp Enable Traps Determines whether traps are enabled (1 = traps enabled, 0 = traps disabled). A trap automatically resets it to 0. When 0, an interrupt request is ignored and an exception trap causes the IU to halt execution and enter error-mode. Current Window Pointer A counter that identifies the current window into the r registers. The hardware decrements cwp on traps & SAVE instructions and increments it on RESTORE & RETT instructions (modulo 8). Note: This TMR-protected register can be safely read after power-up without prior initialization. However, bits unaffected by the reset operation will have an undetermined value. Note: This register is read and written using the priviledged RDPSR and WRPSR instructions. 7 6 5 4 3 2 1 0 w6 w5 w4 w3 w2 w1 w0 reserved w7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 15-3. Window Invalid Mask Register WIM x x x r 0 0 0 0 Bit Number 0<n<7 0 0 0 0 0 0 0 0 r/w 0 0 0 0 0 0 0 0 0 0 0 0 x x x x x Mnemonic Description wn Window n Invalid Mask Determines whether a window overflow or underflow trap is to be generated on an invalid-marked window by a SAVE, RESTORE, or RETT instruction (1 = invalid, 0 = valid). Note: This TMR-protected register can be safely read after power-up without prior initialization. However, bits unaffected by the reset operation will have an undetermined value. Note: This register is read and written using the priviledged RDWIM and WRWIM instructions. ATF697FF [DATASHEET] 146 41000D−AERO03/14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 15-4. Multiply/Divide Register Y y r/w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Bit Number 31..0 Mnemonic Description y Y Register Contains the most significant word of the double-precision product of an integer multiplication, as a result of either an integer multiply instruction (SMUL, SMULcc, UMUL, UMULcc), or of a routine that uses the integer multiply step instruction (MULScc). Also holds the most significant word of the double-precision dividend for an integer divide instruction (SDIV, SDIVcc, UDIV, UDIVcc). Note: This TMR-protected register can be safely read after power-up without prior initialization. However, bits unaffected by the reset operation will have an undertermined value. Note: This register is read and written using the non-priviledged RDY and WRY instructions. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 15-5. Trap Base Register TBR tba tt reserved r/w r r xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 Bit Number Mnemonic Description 31..12 tba Trap Base Address The most-significant 20 bits of the trap table address. 11..4 tt Trap Type Written by the hardware when a trap occurs (except for an external reset request), and retains its value until the next trap. It provides an offset into the trap table. Note: This TMR-protected register can be safely read after power-up without prior initialization. However, bits unaffected by the reset operation will have an undetermined value. Note: This register is read and written using the priviledged RDTBR and WRTBR instructions. ATF697FF [DATASHEET] 147 41000D−AERO03/14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 15-6. Program Counter PC pc 0x00000000 Bit Number 31..0 Mnemonic Description pc Program Counter Contains the address of the instruction currently being executed by the IU. When a trap occurs, it is saved into a local register (l1). When returning from the trap, the local register is copied back. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 15-7. Next Program Counters nPC npc 0x00000004 Bit Number 31..0 Mnemonic Description npc Next Program Counter Holds the address of the next instruction to be executed by the IU (assuming a trap does not occur). When a trap occurs, it is saved into a local register (l2). When returning from the trap, the local register is copied back. Table 15-8. Watch Point Address Registers ASR24, ASR26, ASR28 and ASR30 1 0 2 reserve d 3 waddr i f r/w r r / w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx 0 0 ATF697FF [DATASHEET] 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 %asr24, %asr26, %asr28, %asr30 26 27 28 29 30 31 Address: 148 41000D−AERO03/14 Bit Number Mnemonic Description 31..2 waddr Watchpoint Address Defines the address range to be watched. 0 if Hit on Instruction Fetch If set, enables hit generation on instruction fetch. Note: These TMR-protected registers can be safely read after power-up without prior initialization. However, bits unaffected by the reset operation will have an undetermined value. Note: These non-priviledged registers are read and written using the RDASR and WRASR instructions. Table 15-9. Watch Point Mask Registers ASR25, ASR27, ASR29 and ASR31 1 0 dl ds 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 %asr25, %asr27, %asr29, %asr31 26 27 28 29 30 31 Address: r/w r / w r / w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx 0 0 wmask Bit Number Mnemonic Description 31..2 wmask Watchpoint Address Mask Defines which bits are to be compared to the matching watchpoint address (0 = comparison disabled, 1 = comparison enabled). 1 dl Hit on Data Load If set, enables hit generation on data load. 0 ds Hit on Data Store If set, enables hit generation on data store. Note: These TMR-protected registers can be safely read after power-up without prior initialization. However, bits unaffected by the reset operation will have an undetermined value. Note: These non-priviledged registers are read and written using the RDASR and WRASR instructions. ATF697FF [DATASHEET] 149 41000D−AERO03/14 Table 15-10. Register File Protection Control Register ASR16 r/w r/w xxxx xxxx xxxx xxxx xxxx xxx x xxxx xx 2 0 r di tcb 1 cnt te reserved 3 4 5 6 8 7 9 10 11 12 13 14 16 15 17 18 20 19 21 22 23 24 25 26 %asr16 27 28 29 30 31 Address: r r / / w w 0 0 Bit Number Mnemo nic Description 11..9 cnt Error Counter. Incremented each time a register correction is performed (but saturates at 111). 8..2 tcb Test Checkbits If the test mode is enabled, the destination register checksum is XORed with this field before being written to the register file. 1 te Test Enable If set, errors can be inserted in the register file to test the EDAC protection function. 0 di Disable Checking If set, disables the register-file checking function. Note: This TMR-protected register can be safely read after power-up without prior initialization. However, bits unaffected by the reset operation will have an undetermined value. Note: This non-priviledged register is read and written using the RDASR and WRASR instructions. 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 15-11. Working Registers rn (0 < n < 31) rn r/w(caution) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Caution: These EDAC-protected registers will come uninitialized after power-up so each register in each window shall be first initialized before it can be safely read. Reading an uninitialized register may trigger a single-bit or a double-bit error in an undeterministic manner. ATF697FF [DATASHEET] 150 41000D−AERO03/14 Table 15-12. Window Registers Type in local out global Name Definition Window Absolute i7 r31 return address i6 r30 frame pointer i5 r29 incoming parameter register 5 i4 r28 incoming parameter register 4 i3 r27 incoming parameter register 3 i2 r26 incoming parameter register 2 i1 r25 incoming parameter register 1 i0 r24 incoming parameter register 0 l7 r23 local register 7 l6 r22 local register 6 l5 r21 local register 5 l4 r20 local register 4 l3 r19 local register 3 l2 r18 nPC (for RETT) l1 r17 PC (for RETT) l0 r16 local register 0 o7 r15 temp o6 r14 stack pointer o5 r13 outgoing parameter register 5 o4 r12 outgoing parameter register 4 o3 r10 outgoing parameter register 3 o2 r11 outgoing parameter register 2 o1 r9 outgoing parameter register 1 o0 r8 outgoing parameter register 0 g7 r7 global register 7 g6 r6 global register 6 g5 r5 global register 5 g4 r4 global register 4 g3 r3 global register 3 g2 r2 global register 2 g1 r1 global register 1 ATF697FF [DATASHEET] 151 41000D−AERO03/14 Type Name g0 15.2 Definition r0 global register 0 always 0x00000000 Floating-Point Unit Registers Bit Number Mnemonic xxx 00 xx ofc nvc nxa dza ufa x 2 3 4 5 6 7 8 9 nva ofa x x x r/w x x x x x Description Rounding Direction Selects the rounding direction for floating-point results according to ANSI/IEEE Standard 7541985 (00 = to nearest, 01 = to zero, 10 = to +∞, 11 = to -∞). Trap Enable Mask Enable bits for each of the five floating-point exceptions that can be indicated in the current_exception field (cexc). If a floating-point operate instruction generates one or more exceptions and the corresponding mask bit is 1, an fp_exception trap is caused. A value of 0 prevents that exception type from generating a trap. ns Non Standard Floating-Point Not implemented, always reads as 0. 19..17 ver FPU Version Number aexc r/w x 0 000 cexc ufc 00 22 9..5 10 r tem fcc 11 r 27..23 11..10 12 r rd ftt 13 r 31..30 16..14 14 15 16 17 18 19 20 0 x r nxc x fcc 1 x ftt aexc dzc x ver reserved x 21 22 r r/w reserved 23 nxm 25 26 24 dzm 00 ufm xx ofm r n s tem nvm r/w 27 28 29 rd reserved 30 31 Table 15-13. FPU Status Register FSR Floating-Point Trap Type After a floating-point exception occurs, this field encodes the type of floating-point exception until an STFSR or another FPop is executed. Floating-Point Condition Codes Updated by the floating-point compare instructions (FCMP and FCMPE). The floating-point conditional branch instruction (FBfcc) bases its control transfer on this field. Accrued Floating-Point Exceptions Accumulate IEEE-754 floating-point exceptions while fp_exception traps are disabled using the tem field. After an FPop completes, the tem and cexc fields are logically ANDed together. If the result is nonzero, an fp_exception trap is generated; otherwise, the new cexc field is ORed into this field. Thus, while traps are masked, exceptions are accumulated in this field. ATF697FF [DATASHEET] 152 41000D−AERO03/14 Bit Number 4..0 Mnemonic Description cexc Current Floating-Point Exceptions Indicate that one or more IEEE-754 floating-point exceptions were generated by the most recently executed FPop instruction. The absence of an exception causes the corresponding bit to be cleared. Note: This TMR-protected register can be safely read after power-up without prior initialization. However, bits unaffected by the reset operation will have an undetermined value. Note: This register is read and written using the non-priviledged LDFSR and STFSR instructions. Table 15-14. Floating-Point Trap Types ftt Trap Type Definition ftt Name Description 0 none No trap. 1 IEEE_754_exception An IEEE_754_exception floating-point trap type indicates that a floating-point exception occurred that conforms to the ANSI/IEEE Standard 754-1985. The exception type is encoded in the cexc field. 2 reserved reserved 3 reserved reserved 4 sequence_error A sequence_error indicates one of three abnormal error conditions in the FPU, all caused by erroneous supervisor software: An attempt was made to execute a floating-point instruction when the FPU was not able to accept one. This type of sequence_error arises from a logic error in supervisor software that has caused a previous floating-point trap to be incompletely serviced (for example, the floating-point queue was not emptied after a previous floating-point exception). An attempt was made to execute a STDFQ instruction when the floating-point deferredtrap queue (FQ) was empty, that is, when FSR.qne = 0. (Note that generation of sequence_error is recommended, but not required in this case) 5 reserved reserved 6 reserved reserved 7 reserved reserved Table 15-15. Floating-Point Condition Code fcc fcc Field Definition fcc Description 0 frs1 = frs2 1 frs1 < frs2 ATF697FF [DATASHEET] 153 41000D−AERO03/14 fcc Description 2 frs1 > frs2 3 frs1 ? frs2 Indicates an unordered relation, which is true if either frs1 or frs2 is a signaling NaN or quiet NaN Note: frs1 and frs2 correspond to the single, double, or quad values in the f registers specified by an instruction’s rs1 and rs2 fields. Note that fcc is unchanged if FCMP or FCMPE generate an IEEE_754_exception trap. Table 15-16. Floating-Point Exception Fields aexc / cexc The accrued and current exception fields and the trap enable mask assume the following definitions of the floating-point exception conditions. Table 15-17. Exception Fields Aexc Mnemonic Cexc Mnemonic Name nva nvc Invalid ofa ofc Overflow ufa ufc Underflow dza dzc Div_by_zero X÷0, where X is subnormal or normalized. Note that 0 ÷ 0 does not set the dzc bit. 1 = division-by-zero, 0 = no division-by-zero. nxa nxc Inexact The rounded result of an operation differs from the infinitely precise correct result. 1 = inexact result, 0 = exact result. Description An operand is improper for the operation to be performed (1 = invalid operand, 0 = valid operand(s)). Examples: 0 ÷ 0, ∞ ∞ are invalid. The rounded result would be larger in magnitude than the largest normalized number in the specified format (1 = overflow, 0 = no overflow). The rounded result is inexact and would be smaller in magnitude than the smallest normalized number in the indicated format (1 = underflow, 0 = no underflow). Underflow is never indicated when the correct unrounded result is zero. if ufm = 0: The ufc and ufa bits will be set if the correct unrounded result of an operation is less in magnitude than the smallest normalized number and the correctly-rounded result is inexact. These bits will be set if the correct unrounded result is less than the smallest normalized number, but the correct rounded result is the smallest normalized number. nxc and nxa are always set as well. if ufm = 1. An IEEE_754_exception trap will occur if the correct unrounded result of an operation would be smaller than the smallest normalized number. A trap will occur if the correct unrounded result would be smaller than the smallest normalized number, but the correct rounded result would be the smallest normalized number. ATF697FF [DATASHEET] 154 41000D−AERO03/14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 15-18. Floating-point Registers fn (0 < n < 31) fn r/w(caution) xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Caution: 15.3 These EDAC-protected registers come uninitialized after power-up so each register shall be first initialized before it can be safely read. Reading an uninitialized register may trigger a single -bit or a double-bit error in an undeterministic manner. Memory Interface Registers Table 15-19. Memory Configuration Register 1 MCFG1 1111 1111 0 pp 1 0 2 prrws 0 3 000 0000 4 r/w 5 r/w 6 prwws r/w 7 r 8 prwdh r r / w 9 10 reserved 12 13 14 15 16 17 11 0 prwen xxxx reserved r/w r / w 18 0 19 0 ioen 0 20 xx 21 r 22 r / w iows 24 reserved r/w r / w 23 25 bexc 0 26 0 0x80000000 iobrdy 0 27 29 abrdy r / w 28 30 pbrdy r r / w iowdh 31 reserved Address: Bit Number Mnemonic Description 30 pbrdy PROM area bus-ready enable. If set, a PROM access will be extended until BRDY* is asserted. 29 abrdy Asynchronous bus ready If set, the BRDY* input can be asserted asynchronously to the system clock, provided it is at least 1.5 clock cycles long. Termination of the access after assertion of BRDY* will be delayed by at least one clock cycle. 28..27 iowdh I/O bus width Defines the bus width of the I/O area (00 = 8, 10 = 32). 26 iobrdy IO area bus ready enable If set, an IO access will be extended until BRDY* is asserted 25 bexc Bus error enable for RAM, PROM and IO access If set, the assertion of the BEXC* will generate an error response on the internal bus and causes a trap (0x01, 0x09, 0x2B) depending on the access type. ATF697FF [DATASHEET] 155 41000D−AERO03/14 Bit Number Mnemonic Description 23..20 iows I/O waitstates Defines the number of waitstates during I/O accesses (0000 = 0, 0001 = 1, 0010 = 2,..., 1111 = 15). 19 ioen I/O area enable 0 = read and write access to I/O area is disabled 1 = read and write access to I/O area is enabled. 11 prwen PROM write enable If set, enables write cycles to the PROM area. prwdh PROM width Defines the bus width of the PROM area (00 = 8, 1X = 32). During reset, the PROM width is set with the value read on GPIO[1:0]. 7..4 prwws PROM write waitstates Defines the number of waitstates during PROM write cycles (0000 = 0, 0001 = 2,... 1111 = 30). During reset, the PROM write waitstates is set to the maximum to allow booting. 3..0 prrws PROM read waitstates Defines the number of waitstates during PROM read cycles (0000 = 0, 0001 = 2,... 1111 = 30). During reset, the PROM read waitstates is set to the maximum to allow booting. 9..8 Note: In 8-bit PROM mode, the last 20% of each PROM bank are used to store the EDAC checksums when EDAC is enabled and cannot be used to store instructions or data. Table 15-20. Memory Configuration Register 2 MCFG2 r r / w r / w r/w r r / w r / w r/w r/w r/w 0 1 111 1 000 10 00 0000 0 0 xxxx 0 x x xx xx xx ATF697FF [DATASHEET] 156 41000D−AERO03/14 0 ramrws r/w 1 ramwws r/w 2 ramwdh r/w 3 6 ramrmw r / w 4 7 rambrdy r/w 5 8 reserved r / w 9 10 rambs 11 13 si 12 14 se 15 16 17 18 19 20 sdrcmd 21 22 sdrcls 23 24 sdrbs 25 26 r / w sdrcas 27 28 reserved trfc 30 trp 29 31 0x80000004 sdrref Address: Bit Number Mnemonic Description 31 sdrref SDRAM refresh If set, the SDRAM refresh is enabled. 30 trp SDRAM tRP timing tRP is equal to 2 or 3 system clocks (0 or 1). 29..27 trfc SDRAM tRFC timing tRFC is equal to 3 + field-value system clocks. 26 sdrcas SDRAM CAS delay Selects 2 or 3 cycle CAS delay (0 or 1). When changed, a LOAD-COMMAND-REGISTER command must be issued at the same time. Also sets RAS/CAS delay (tRCD). sdrbs SDRAM banks size Defines the banks size for SDRAM chip selects: 000 = 4 MB, 001 = 8 MB, 010 = 16 MB .... 111 = 512 MB. sdrcls SDRAM column size 00 = 256, 01 = 512, 10 = 1024, 11 = 4096 when sdrbs = 111, 2048 otherwise 20..19 sdrcmd SDRAM command Writing a non-zero value generates an SDRAM command: 01 = PRECHARGE, 10 = AUTO-REFRESH, 11 = LOAD-COMMAND-REGISTER. The field is reset after command has been executed. 14 se SDRAM enable If set, the SDRAM controller is enabled. 13 si SRAM disable If set together with se (SDRAM enable), the static ram access is disabled. 12..9 rambs SRAM bank size Defines the size of each ram bank (0000 = 8 KB, 0001 = 16 KB... 1111 = 256 MB). 7 rambrdy SRAM area bus ready enable If set to 1, a RAM access to RAM bank 4 (RAMS* [4]) is extended until BRDY* is asserted. 6 ramrmw Read-modify-write on the SRAM Enables read-modify-write cycles on sub-word writes to areas with common write strobe and/or EDAC protection. 5..4 ramwdh SRAM bus width Defines the bus with of the SRAM area (00 = 8, 1X = 32). 25..23 22..21 ATF697FF [DATASHEET] 157 41000D−AERO03/14 Bit Number Mnemonic Description 3..2 ramwws SRAM write waitstates Defines the number of waitstates during SRAM write cycles (00 = 0, 01 = 1, 10 = 2, 11 = 3). 1..0 ramrws SRAM read waitstates Defines the number of waitstates during SRAM read cycles (00 = 0, 01 = 1, 10 = 2, 11 = 3). Table 15-21. Memory Configuration Register 3 MCFG3 xxx xxxx xxxx xxxx 0 0 x p xxxx xxxx Bit Number Mnemonic Description 31:30 rfc Register file check bits Indicates how many checkbits are used for the register file (11 = 7 bits) 27 me Memory EDAC Indicates if a memory EDAC is present 26..12 srcrv SDRAM refresh counter reload value The period between each AUTO-REFRESH command tREFRESH = ((reload value) + 1) ÷ SDCLKfrequency. 11 wb EDAC diagnostic write bypass When set, replace the EDAC checkbits with tcb on a store operation. 10 rb EDAC diagnostic read When set, update tcb with the EDAC checkbits on instruction fetch or data load operation. is calculated as ATF697FF [DATASHEET] 158 41000D−AERO03/14 0 1 srcrv 1 00 2 11 3 r/w 4 8 pe r/w r / w 5 9 re r r / w 6 10 rb r r / w 7 11 wb 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 r r / w me 28 29 0x80000008 tcb rfc reserved 30 31 Address: follows: Bit Number Mnemonic Description 9 re RAM EDAC enable When set, enables EDAC protection on the RAM area: SRAM read-modify-write on sub-word operation shall be enabled as well (MCFG2.ramrmw = 1)in order to maintain EDAC protection integrity SDRAM read-modify-write on sub-word operations is simultaneously activated with EDAC on RAM Memory shall be initialized before EDAC activation. 8 pe PROM EDAC enable When set, enables EDAC protection on the PROM area. During reset, this bit is initialized with the value of GPIO[2]. tcb Test checkbits This field replaces the normal checkbits during store operations when wb is set. It is also loaded with the memory checkbits during instruction fetch and data load operations when rb is set. 7..0 Table 15-22. Write Protection Register 1 WPR1 Bit Number Mnemonic Description 31 en Enable. If set, write protection is enabled. 30 bp Block Protect If set, block protect mode is selected rather than segment allow mode. 29..15 tag Address Tag The tag is XORed with the same bits in the write address. 14..0 mask Address Mask The mask is applied on the result of the tag/address XOR operation. ATF697FF [DATASHEET] 159 41000D−AERO03/14 0 xxx xxxx xxxx xxxx 1 xx xxxx xxxx xxxx x 2 x 3 0 4 r/w mask 5 r/w 6 r / w 7 r / w 8 tag 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 bp 29 31 0x8000001C en Address: Table 15-23. Write Protection Register 2 WPR2 Bit Number Mnemonic Description 31 en Enable. If set, write protection is enabled. 30 bp Block Protect If set, block protect mode is selected rather than segment allow mode. 29..15 tag Address Tag The tag is XORed with the same bits in the write address. 14..0 mask Address Mask The mask is applied on the result of the tag/address XOR operation. 0 1 2 xxx xxxx xxxx xxxx 2 xx xxxx xxxx xxxx x 3 x 4 0 3 r/w mask 5 r/w 6 r / w 7 r / w 8 tag 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 30 bp 29 31 0x80000020 en Address: Table 15-24. Write Protection Start Address 1 WPSTA1 1 0 bp reserved r r/w r / w r 00 xxxx xxxx xxxx xxxx xxxx xxxx xxxx x 0 ATF697FF [DATASHEET] 4 5 6 7 8 start reserved 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x800000D0 26 27 28 29 30 31 Address: 160 41000D−AERO03/14 Bit Number Mnemonic Description 29..2 start Start Address Segment starts from this address (included, 2 null least-significants bits omitted). 1 bp Block protect If set, block protect mode is selected rather than segment allow mode. Table 15-25. Write Protection End Address 1 WPSTO1 xxxx xxxx xxxx xxxx xxxx xxxx xxxx 2 3 4 5 6 8 7 9 0 00 su r/w 1 r us end 10 11 12 13 14 16 15 17 18 20 19 21 22 23 25 24 26 27 28 29 30 0x800000D4 reserved 31 Address: r r / / w w 0 Bit Number Mnemonic Description 29..2 end End Address Segment finishes at this address (included, 2 null least-significants bits omitted). 1 us User Mode If set, write protection is active in User Mode (PSR.s = 0). 0 su Supervisor Mode If set, write protection is active in Supervisor Mode (PSR.s = 1). 0 Table 15-26. Write Protection Start Address 2 WPSTA2 1 0 bp reserved 2 3 start r r/w r / w r 00 xxxx xxxx xxxx xxxx xxxx xxxx xxxx x 0 ATF697FF [DATASHEET] 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x800000D8 reserved 31 Address: 161 41000D−AERO03/14 Bit Number Mnemonic Description 29..2 start Start Address Segment starts from this address (included, 2 null least-significants bits omitted). 1 bp Block protect If set, block protect mode is selected rather than segment allow mode. Table 15-27. Write Protection End Address 2 WPSTO2 1 0 us su 2 3 4 5 6 7 8 end r r/w r / w r / w 00 xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0 0 reserved 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x800000DC 26 27 28 29 30 31 Address: Bit Number Mnemonic Description 29..2 end End Address Segment finishes at this address (included, 2 null least-significants bits omitted). 1 us User Mode If set, write protection is active in User Mode (PSR.s = 0). 0 su Supervisor Mode If set, write protection is active in Supervisor Mode (PSR.s = 1). ATF697FF [DATASHEET] 162 41000D−AERO03/14 15.4 System Registers Table 15-28. Product Configuration Register – PCR r r r r r r r r r r r 0 1 1 100 0 00111 011 11 011 10 1 1 1 1 01 01 01 fpu pci wpr t 0x7077BBD5 Bit Number Mnemonic Description 31 mmu Memory Management Unit 0 = not present 30 dsu Debug Support Unit 1 = present 29 sdrctrl SDRAM Controller 1 = present 28..26 wtpnt IU Watchpoints 100 = 4 watchpoints 25 imac UMAC/SMAC instructions 0 = not implemented 24..20 nwin IU Register File Windows 00111 = 8 windows 19..17 icsz Instruction Cache Set Size (2icsz KB) 011 = 8 KB (× 4 ways = 32 KB total) 16..15 ilsz Instruction Cache Line Size (2ilsz instructions) 11 = 8 instructions 14..12 dcsz Data Cache Set Size (2dcsz KB) 011 = 8 KB (× 2 ways = 16 KB total) 11..10 dlsz Data Cache Line Size (2dlsz words) 10 = 4 words 9 divinst UDIV/SDIV instructions 1 = implemented 8 mulinst UMUL/SMUL instructions 1 = implemented 0 r 1 r 2 r dlsz 3 r dcsz 4 7 wdog memst at r ilsz 5 8 mulinst r icsz 6 9 nwin divinst 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 wtpnb imac 26 29 sdrctrl 27 30 dsu 28 31 0x80000024 mmu Address: ATF697FF [DATASHEET] 163 41000D−AERO03/14 Bit Number Mnemonic Description 7 wdog Watchdog 1 = implemented 6 memstat Memory Status and Address Failing Register 1 = implemented 5..4 fpu FPU Type 01 = MEIKO 3..2 pci PCI Core Type 01 = InSilicon 1..0 wprt Write Protection 01 = implemented Table 15-29. Fail Address Register – FAILAR 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x8000000C 26 27 28 29 30 31 Address: hea r1/w2 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Bit Number Mnemonic Description 31:0 hea Hardware Error Address Identifies the address of the failed access. Note: 1. Read value is only valid when a hardware error was detected (FAILSR.hed = 1) and is not relevant otherwise (unpredictable value). Note: 2. Written value is always discarded when no hardware error is detected (FAILSR.hed = 0). ATF697FF [DATASHEET] 164 41000D−AERO03/14 Table 15-30. Fail Status Register – FAILSR r / w 2 0000 0000 0000 0000 0000 00 Bit Number x hem r / w 0 1 2 3 4 7 het 1 5 8 hed r 6 9 10 11 12 13 14 15 eed reserved 16 17 18 19 20 21 22 23 24 25 0x80000010 26 27 28 29 30 31 Address: hes r3/w4 2 0 x xxxx xxx Mnemonic Description eed EDAC-correctable Error Detected Set when an EDAC-correctable memory error is detected1 (register-file EDAC errors are handled separately). This bit is never cleared in hardware and shall be cleared in software so a new error can be registered2. This bit shall also be cleared before the EDAC is activated. 8 hed Hardware Error Detected Set when a hardware error is detected (bus exception, write protection error, EDAC correctable and uncorrectable external memory error, PCI initiator error or PCI target error). This bit is never cleared in hardware and shall be cleared in software so a new hardware error can be registered and the hardware error-related fields updated2. 7 het Hardware Error Type3 Identifies the type of the failed access (0 = write, 1 = read). 9 6..3 hem 2..0 hes Hardware Error Module3 Identifies the module impacted by the failed access (0000 = IU/FPU, 0001 = PCI Initiator, 0010 = PCI Target, 0011 = DSU Communication Module). Hardware Error Size3 Identifies the size of the failed access (000 = byte, 001 = half-word, 010 = word, 011 = doubleword). Note: 1. Bit might be updated even when a hardware error was already detected (FAILSR.hed = 1). Note: 2. These bits shall be cleared as soon as possible after the error was detected so no subsequent hardware error is missed after the initial detection. Moreover, the register read-and-clear operation shall be best performed by mean of a SWAP instruction so to minimize even further the time from read to clear. Note: 3. Read value is only valid when a hardware error was detected (FAILSR.hed = 1) and is not relevant otherwise (unpredictable value). Note: 4. Written value is always discarded while no hardware error is detected (FAILSR.hed = 0). ATF697FF [DATASHEET] 165 41000D−AERO03/14 Caches Register 15.5 Table 15-31. Cache Control Register – CCR r/w r/w r / w r / w r/w r/w 10 xx 0 0 0 xx xx xx xx x x 00 00 Bit Number Mnemonic Description 31..30 drepl Data cache replacement policy 11 = Least Recently Used (LRU) 29..28 irepl Instruction cache replacement policy 11 = Least Recently Used (LRU) isets Instruction cache associativity Number of ways in the instruction cache. 11 = 4 way associative 25..24 dsets Data cache associativity Number of ways in the data cache. 01 = 2 way associative 23 ds Data cache snoop enable If set, will enable data cache snooping. 22 fd Flush data cache If set, will flush the data cache. Always reads as zero. 21 fi Flush Instruction cache If set, will flush the instruction cache. Always reads as zero. 20..19 cpc Cache parity bits Indicates how many parity bits are used to protect the caches. 10 = 2 parity bits 18..17 cptb Cache parity test bits These bits are XOR’ed to the data and tag parity bits during diagnostic writes. 16 ib Instruction burst fetch This bit enables burst fill during instruction fetch. 27..26 ATF697FF [DATASHEET] 166 41000D−AERO03/14 0 ics r/w 1 dcs r/w 2 4 if r 3 5 df r 6 r / w 7 dde r/w 8 r 9 dte 10 11 ide 12 ite 13 14 dp 17 18 19 20 15 0 ip 0 16 0 ib 01 cptb 11 r / w w w cpc 11 21 11 fi r 22 r fd r 23 r ds 24 25 dsets 26 27 isets 28 29 irepl 30 0x80000014 drepl 31 Address: Bit Number Mnemonic Description 15 ip Instruction cache flush pending This bit is set while an instruction cache flush operation is in progress. 14 dp Data cache flush pending This bit is set while a data cache flush operation is in progress. 13..12 ite Instruction cache tag error counter This field is incremented1 every time an instruction cache tag parity error is detected. 11..10 ide Instruction cache data error counter This field is incremented1 each time an instruction cache data sub-block parity error is detected. 9..8 dte Data cache tag error counter This field is incremented1 every time a data cache tag parity error is detected. 7..6 dde Data cache data error counter This field is incremented1 each time an instruction cache data sub-block parity error is detected 5 df Data Cache Freeze on Interrupt If set, the data cache will automatically be frozen when an asynchronous interrupt is taken. if Instruction Cache Freeze on Interrupt If set, the instruction cache will automatically be frozen when an asynchronous interrupt is taken. dcs Data Cache State X0 = disabled 01 = frozen 11 = enabled ics Instruction Cache State X0 = disabled 01 = frozen 11 = enabled. 4 3..2 1..0 Note: 1. The counter saturates at 11 (3 events) and shall be cleared in software so new events can later be registered. ATF697FF [DATASHEET] 167 41000D−AERO03/14 15.6 Idle Register Table 15-32. Idle Register – IDLE 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000018 26 27 28 29 30 31 Address: idle w n/a Bit Number 31..0 Mnemonic Description idle A write to this register followed by a load access will cause the system to enter idle mode. This a write-only register (written value is not relevant), the value returned by a read is not relevant. ATF697FF [DATASHEET] 168 41000D−AERO03/14 15.7 Timer Registers Table 15-33. Timer 1 Counter Register TIMC1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000040 26 27 28 29 30 31 Address: cnt r/w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Bit Number Mnemonic Description 31..0 cnt Timer 1 counter value A read access gives the current decounting value of the timer. Table 15-34. Timer 1 Reload Register TIMR1 3 3 0 4 4 1 5 5 2 6 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000044 26 27 28 29 30 31 Address: rv r/w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Bit Number Mnemonic Description 31..0 rv Timer 1 reload value A write access programs the reload value of TIMC1. Table 15-35. Timer 1 Control Register TIMCTR1 r 1 0 en reserved rl 2 ld 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000048 26 27 28 29 30 31 Address: r/w 0000 0000 0000 0000 0000 0000 0000 0 0 ATF697FF [DATASHEET] 169 41000D−AERO03/14 x 0 Bit Number Mnemonic Description 2 ld Load counter If set, the timer counter register is loaded with the reload value. Always reads as 0. 1 rl Reload counter If set, the counter is automatically reloaded with the reload value after each underflow. If cleared, the timer is single-shot. 0 en Enable counter Enables the timer when set. Table 15-36. Watchdog Register – WDG 2 1 0 2 1 0 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 0x8000004C 27 28 29 30 31 Address: cnt r/w 1111 1111 1111 1111 1111 1111 1111 1111 Bit Number Mnemo nic Description 31..0 cnt Watchdog counter value. A write access programs the new value of the watchdog counter. A read access gives the current decounting value of the watchdog counter. Table 15-37. Timer 2 Counter Register TIMC2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000050 26 27 28 29 30 31 Address: cnt r/w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx ATF697FF [DATASHEET] 170 41000D−AERO03/14 Bit Number Mnemonic Description 31..0 cnt Timer 2 counter value A read access gives the current decounting value of the timer. Table 15-39. Timer 2 Reload Register TIMR2 3 3 0 4 4 1 5 5 2 6 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000054 26 27 28 29 30 31 Address: rv r/w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Bit Number Mnemonic Description 31..0 rv Timer 2 reload value A write access programs the reload value of TIMC2. Table 15-40. Timer 2 Control Register TIMCTR2 r 0 en r/w 0000 0000 0000 0000 0000 0000 0000 0 Bit Number 1 reserved rl 2 ld 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Address= 0x80000058 26 27 28 29 30 31 Address: 0 x 0 Mnemonic Description ld Load counter If set, the timer counter register is loaded with the reload value. Always reads as 0. 1 rl Reload counter If set, the counter is automatically reloaded with the reload value after each underflow. If cleared, the timer is single-shot. 0 en Enable counter Enables the timer when set. 2 ATF697FF [DATASHEET] 171 41000D−AERO03/14 Table 15-41. Prescaler Counter Register – SCAC 00 0000 0000 Bit Number Mnemonic Description 9..0 cnt Prescaler counter value A read access gives the current decounting value of the prescaler. 0 0000 0000 0000 0000 00 0 r/w 1 r 1 cnt 2 reserved 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Address= 0x80000060 26 27 28 29 30 31 Address: Table 15-42. Prescaler Reload Register – SCAR Bit Number 9..0 Note: 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000064 26 27 28 29 30 31 Address: reserved rv r r/w 0000 0000 0000 0000 00 00 0000 00001 Mnemonic Description rv Prescaler reload value A write access programs the reload value of the prescaler. A read access gives the reload value of the prescaler. The effective division rate is (rv + 1).1 1.As a special case, reload values 0 & 1 yield a division rate of 4, reload value 2 yields a division-rate of 6 ATF697FF [DATASHEET] 172 41000D−AERO03/14 15.8 UART Registers Table 15-43. UART 1 Data Register UAD1 Bit Number 7..0 reserved rtd r r/w 0000 0000 0000 0000 0000 0000 xxxx xxxx Mnemonic Description rtd Received/Transmit Data on the UART A read access provides the last received 8-bit data A write access initiates the transmission of the 8-bit data 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000070 26 27 28 29 30 31 Address: Table 15-44. UART 1 Status Register UAS1 6 5 4 3 2 1 0 fe pe ov br th ts dr reserved 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000074 26 27 28 29 30 31 Address: r r/w 0000 0000 0000 0000 0000 0000 0 0 0 Bit Number Mnemonic Description 6 fe Framing error1. Indicates that a framing error was detected. 5 pe Parity error1. Indicates that a parity error was detected. 4 ov Overrun1. Indicates that one or more character have been lost due to overrun. 3 br Break received1. Indicates that a BREAK has been received. 2 th Transmitter hold register empty Indicates that the transmitter hold register is empty. ATF697FF [DATASHEET] 0 r 0 173 41000D−AERO03/14 1 1 0 Bit Number Mnemonic Description 1 ts Transmitter shift register empty Indicates that the transmitter shift register is empty. 0 dr Data ready Indicates that new data is available in the receiver holding register. Note: Once set, these error bits are never cleared by the processor: it is the responsibility of the application to clear them in software so further errors can be detected. Table 15-45. UART 1 Control Register UAC1 3 2 1 0 ri te re 5 pe ti 6 fl 4 7 lb r ps 8 reserved ec 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000078 26 27 28 29 30 31 Address: x x 0 0 r/w 0000 0000 0000 0000 0000 0000 0 x 0 x Bit Number Mnemonic Description 8 ec External Clock If set, the UART will be directly clocked from GPIO[3] (no scaler). 7 lb Loop back If set, RX will be internally connected to TX (with no external activity). 6 fl Flow control If set, enables hardware flow-control using CTS and/or RTS. 5 pe Parity enable If set, enables parity generation and checking. 4 ps Parity select 0 = even parity 1 = odd parity 3 ti Transmitter interrupt enable If set, enables generation of transmitter interrupt. 2 ri Receiver interrupt enable If set, enables generation of receiver interrupt. 1 te Transmitter enable If set, enables the UART transmitter. 0 re Receiver enable If set, enables the UART receiver. ATF697FF [DATASHEET] x 174 41000D−AERO03/14 Table 15-46. UART 1 Scaler Register UASCA1 Mnemonic Description 7..0 rv UART scaler reload value 0 Bit Number 0 xxxx xxxx xxxx 1 0000 0000 0000 0000 0000 1 r/w 2 r 2 rv 3 reserved 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x8000007C 26 27 28 29 30 31 Address: Table 15-47. UART 2 Data Register UAD2 Bit Number 7..0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000080 26 27 28 29 30 31 Address: reserved rtd r r/w 0000 0000 0000 0000 0000 0000 xxxx xxxx Mnemonic Description rtd Received or Transmitted Data on the UART A read access provides the last received 8-bit data A write access initiates transmission of the 8-bit data ATF697FF [DATASHEET] 175 41000D−AERO03/14 Table 15-48. UART 2 Status Register UAS2 6 5 4 3 2 1 0 pe ov br th ts dr reserved fe 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000084 26 27 28 29 30 31 Address: r r/w 0000 0000 0000 0000 0000 0000 0 0 0 0 Bit Number Mnemonic Description 6 fe Framing error1. Indicates that a framing error was detected. 5 pe Parity error1. indicates that a parity error was detected. 4 ov Overrun1. Indicates that one or more character have been lost due to overrun. 3 br Break received1. Indicates that a BREAK has been received. 2 th Transmitter hold register empty Indicates that the transmitter hold register is empty. 1 ts Transmitter shift register empty Indicates that the transmitter shift register is empty. 0 dr Data ready Indicates that new data is available in the receiver holding register. Note: r 0 1 1 0 Once set, these error bits are never cleared by the processor: it is the responsibility of the application to clear them in software so further errors can be detected. Table 15-49. UART 2 Control Register UAC2 2 1 0 ri te re 5 pe 3 6 fl ti 0000 0000 0000 0000 0000 0000 4 7 lb r ps 8 9 10 11 12 13 14 ec reserved 15 16 17 18 19 20 21 22 23 24 25 0x80000088 26 27 28 29 30 31 Address: x x 0 0 r/w 0 x 0 x ATF697FF [DATASHEET] x 176 41000D−AERO03/14 Bit Number Mnemonic Description 8 ec External Clock If set, the UART will be directly clocked from GPIO[3] (no scaler). 7 lb Loop back If set, RX will be internally connected to TX (with no external activity). 6 fl Flow control If set, enables hardware flow-control using CTS and/or RTS. 5 pe Parity enable If set, enables parity generation and checking. 4 ps Parity select Selects parity polarity 0 = even parity 1 = odd parity 3 ti Transmitter interrupt enable If set, enables generation of transmitter interrupt. 2 ri Receiver interrupt enable If set, enables generation of receiver interrupt. 1 te Transmitter enable If set, enables the UART transmitter. 0 re Receiver enable If set, enables the UART receiver. Table 15-50. UART 2 Scaler Register UASCA2 reserved rv r r/w 0000 0000 0000 0000 0000 xxxx xxxx xxxx Bit Number Mnemonic Description 7..0 rv UART scaler reload value ATF697FF [DATASHEET] 177 41000D−AERO03/14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x8000008C 26 27 28 29 30 31 Address: 15.9 Interrupt Registers Table 15-51. Interrupt Mask and Priority Register – ITMP Bit Number 31..16 15..0 6 5 4 3 2 1 0 I/O2 I/O1 I/O0 UART1 UART2 AMBA reserved 7 I/O3 Timer1 Timer2 I/O4 DSU I/O5 I/O6 PCI I/O7 reserved AMBA UART2 UART1 I/O0 I/O1 imask I/O2 I/O3 Timer1 Timer2 I/O4 DSU I/O5 I/O6 PCI I/O7 ilevel 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000090 26 27 28 29 30 31 Address: r/w r r/w r xxxx xxxx xxxx xxx 0 0000 0000 0000 000 0 Mnemonic Description ilevel Interrupt Level 0 = low priority interrupt 1 = high priority interrupt High-priority interrupts are always serviced before low-priority interrupts. imask Interrupt Mask Indicates whether an interrupt is masked or enabled 0 = interrupt masked 1 = interrupt enabled Table 15-52. Interrupt Pending Register – ITP 6 5 4 3 2 1 0 I/O2 I/O1 I/O0 UART1 UART2 AMBA reserved 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000094 26 r 0000 0000 0000 0000 I/O3 Timer1 Timer2 I/O4 DSU I/O5 I/O6 reserved PCI ipend1. I/O7 27 28 29 30 31 Address: r/w x x x x x x x x r x x x ATF697FF [DATASHEET] x x 178 41000D−AERO03/14 x x 0 Bit Number 15..0 Mnemonic Description ipend Interrupt Pending Indicates whether an interrupt is pending1 1 = interrupt pending2 0 = interrupt not pending Note: 1. When the IU acknowledges the interrupt, the corresponding pending bit is automatically cleared unless it was forced (see ITF). Note: 2. Forced interrupts never show up as pending. Table 15-54. Interrupt Force Register – ITF 6 5 4 3 2 1 0 I/O2 I/O1 I/O0 UART1 UART2 AMBA reserved 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000098 26 27 28 29 30 31 Address: r 15..0 I/O3 r/w 0000 0000 0000 0000 Bit Number Timer1 Timer2 I/O4 DSU I/O5 I/O6 I/O7 reserved PCI iforce1. x x x x x x x r x x Mnemonic Description iforce Interrupt Force Indicates whether an interrupt is being forced.1 1 = interrupt forced2. 0 = interrupt not forced x x x x x x 0 Note: 1. When the IU acknowledges the interrupt, only the corresponding force bit is automatically cleared if it was forced. Note: 2. Forcing is effective only if the corresponding interrupt is unmasked. Table 15-55. Interrupt Clear Register – ITC 6 5 4 3 2 1 0 I/O2 I/O1 I/O0 UART1 UART2 AMBA reserved 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 r I/O3 Timer1 Timer2 I/O4 DSU I/O5 I/O6 reserved PCI iclear I/O7 25 0x8000009C 26 27 28 29 30 31 Address: w r ATF697FF [DATASHEET] 179 41000D−AERO03/14 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 xxxx xxxx xxxx xxxx x x x x x x x x x x x x x x x x Bit Number Mnemonic Description 15..0 iclear Interrupt Clear If written with a 1, clears the corresponding bit(s) in the interrupt pending register. The value returned by a read is not relevant, this is a write-only register. ATF697FF [DATASHEET] 180 41000D−AERO03/14 15.10 General Purpose Interface Registers Table 15-56. I/O Port Data Register – IODAT meddat lowdat piodat r/w r/w r/w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Bit Number Mnemonic Description 31..24 meddat1. D[15:8] bus value 23..16 lowdat1. D[7:8] bus value 15..0 piodat GPIO[15:0] port value Note: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x800000A0 26 27 28 29 30 31 Address: 1.These bits are only accessible as I/O ports when all areas (ROM, RAM and I/O) of the memory bus are in 8bit mode (see “8-bit PROM and SRAM access”) and the SDRAM controller is not enabled. Table 15-57. I/O Port Direction Register – IODIR piodir[15:0] Bit Number Mnemonic Description 17 meddir1 D[15:8] port direction (see note). 1 = output 0 = input 16 lowdir1 D[7:0] port direction (see note) 1 = output 0 = input ATF697FF [DATASHEET] 181 41000D−AERO03/14 0 1 2 0000 0000 0000 0000 3 0 4 0 5 0000 0000 0000 00 6 r/w 7 r / w 8 r / w 9 10 11 12 13 14 16 lowdir 15 17 meddir 18 19 r reserved 20 21 22 23 24 25 0x800000A4 26 27 28 29 30 31 Address: Bit Number Mnemonic Description 15..0 piodir GPIO[15:0] port direction 1 = output 0 = input These bits are only accessible as I/O ports when all areas (ROM, RAM and I/O) of the memory bus are in 8-bit mode (see “8-bit PROM and SRAM access”) and the SDRAM controller is not enabled. Note: Table 15-58. I/O Port Interrupt Register IOIT1 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 le3 pl3 isel3 en2 le2 pl2 isel2 en1 le1 pl1 isel1 en0 le0 pl0 0x800000A8 en3 Address: isel0 r r r / / / w w w r/w r r r / / / w w w 0 x r/w x x xxxx r r r / / / w w w 0 x x r/w x xxxx r r r / / / w w w 0 x x r/w x xxxx 0 x x Bit Number Mnemonic Description 31 en3 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 30 le3 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. x xxxx Polarity If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). I/O port select. The value of this field defines which I/O port (0 31) should generate parallel I/O port interrupt 3. 29 pl3 28..24 isel3 23 en2 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 22 le2 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. 21 pl2 20..16 isel2 Polarity If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). I/O port select. The value of this field defines which I/O port (0 31) should generate parallel I/O port interrupt 2. ATF697FF [DATASHEET] 182 41000D−AERO03/14 Bit Number Mnemonic Description 15 en1 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 14 le1 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. 13 pl1 12..8 isel1 7 en0 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 6 le0 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. 5 pl0 4..0 isel0 Polarity If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). I/O port select. The value of this field defines which I/O port (0 31) should generate parallel I/O port interrupt 1. Polarity If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). I/O port select. The value of this field defines which I/O port (0 31) should generate parallel I/O port interrupt 0. Table 15-59. I/O Port Interrupt Register IOIT2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 le7 pl7 isel7 en6 le6 pl6 isel6 en5 le5 pl5 isel5 en4 le4 pl4 0x800000AC en7 Address: isel4 r r r / / / w w w r/w r r r / / / w w w r/w r r r / / / w w w r/w r r r / / / w w w r/w 0 x x x xxxx 0 x x x xxxx 0 x x x xxxx 0 x x Bit Number Mnemonic Description 31 en7 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 30 le7 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. ATF697FF [DATASHEET] x xxxx 183 41000D−AERO03/14 Bit Number Mnemonic 29 pl7 28..24 isel7 23 en6 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 22 le6 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. 21 pl6 20..16 isel6 15 en5 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 14 le5 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. Description Polarity If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). I/O port select. The value of this field defines which I/O port (0 31) should generate parallel I/O port interrupt 7. Polarity If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). I/O port select. The value of this field defines which I/O port (0 31) should generate parallel I/O port interrupt 6. Polarity If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). I/O port select. The value of this field defines which I/O port (0 31) should generate parallel I/O port interrupt 5. 13 pl5 12..8 isel5 7 en4 Enable. If set, the corresponding interrupt will be enabled, otherwise it will be masked. 6 le4 Level/edge triggered. If set, the interrupt will be edge-triggered, otherwise level sensitive. 5 pl4 4..0 isel4 Polarity If set, the corresponding interrupt will be active high (or edge-triggered on positive edge). Otherwise, it will be active low (or edge-triggered on negative edge). I/O port select. The value of this field defines which I/O port (0 31) should generate parallel I/O port interrupt 4. ATF697FF [DATASHEET] 184 41000D−AERO03/14 15.11 PCI Registers The PCI registers are located between 0x80000100 and 0x800002FC. Within this range, any address not shown in the following list shall neither be written nor read. Table 15-60. PCI Device Identification Register 1 PCIID1 device id vendor id r r 0x1202 0x1438 Bit Number Mnemonic Description 31..16 device id This field identifies the particular device. 15..0 vendor id This field identifies the manufacturer of the device (ATMEL). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 0x80000100 27 28 29 30 31 Address: Table 15-61. PCI Status & Command Register – PCISC Bit Number 31 2 1 0 com1 com0 r / r w r / w r / r w r / w r / w com10 com2 0 3 0 com3 0 4 0 r com4 0 r 5 1 r com5 1 r 6 1 r com6 23 22 21 20 19 18 17 16 15 14 13 12 11 10 stat7 stat6 stat5 stat4 stat3 1 r 7 24 stat8 1 r r / w com7 26 25 stat10_ 9 r / w 8 27 stat11 r / w com8 28 stat12 r / w 9 29 stat13 r / w com9 30 stat14 r / w reserve d 31 0x80000104 stat15 Address: 1 1 1 01 0 1 0 0 0 0 0000 0000 0 0 Mnemonic Description stat15 PCI Bus Parity Error Status 1 = PERR* asserted (set even if parity checking is disabled) 0 = PERR* not asserted This bit shall be cleared by writing a 1 (0 has no effect). 0 r r / w r r / w 1 1 0 0 0 0 ATF697FF [DATASHEET] 1 1 1 0 0 0 0 185 41000D−AERO03/14 Bit Number Mnemonic Description stat14 PCI Interface System Error Status 1 = PCI interface asserted SERR* 0 = PCI interface does not assert SERR* This bit shall be cleared by writing a 1 (0 has no effect). stat13 Initiator Interface Termination Status 1 = initiator transaction terminated with Master Abort 0 = initiator transaction successfully terminated (if any) This bit shall be cleared by writing a 1 (0 has no effect). stat12 Remote Target Termination Status 1 = initiator transaction terminated with Target Abort 0 = initiator transaction successfully terminated (if any) This bit shall be cleared by writing a 1 (0 has no effect). 27 stat11 Target Interface Termination Status 1 = remote initiator transaction terminated with Target Abort 0 = remote initiator transaction successfully terminated (if any) This bit shall be cleared by writing a 1 (0 has no effect). 26..25 stat10_9 Target Interface Selection Timing 01 = DEVSEL* is asserted with medium timing 30 29 28 Initiator Interface Parity Error Status 1 = initiator interface asserted PERR* on a read transaction or observed PERR on a write transaction and Parity Error Response is enabled (bit 6) 0 = initiator interface has not asserted nor observed PERR* on a transaction (if any), or Parity Error Response is disabled (bit 6) This bit shall be cleared by writing a 1 (0 has no effect). Target Interface Fast Back-to-Back Capability 1 = the target is capable of accepting fast back-to-back transactions when the transactions are not to the same agent 24 stat8 23 stat7 22 stat6 User definable features (reserved) 21 stat5 66 MHz Capability 0 = not capable 20 stat4 Power Management Capability 0 = no New Capabilities linked list is available at offset 34h, value at that location is not relevant 19 stat3 PCI Interrupt Status (reserved, no PCI interrupts) 10 com10 Interrupt Command (reserved, no PCI interrupts) com9 Initiator Interface Fast Back-to-Back Control2 1 = initiator is allowed to generate fast back-to-back transactions to different targets 0 = initiator shall only generate fast back-to-back transactions to the same target com8 System Error Pin Control 1 = assert SERR* 0 = do no assert SERR* Address parity errors are reported only if this bit and bit 6 are 1. 9 8 ATF697FF [DATASHEET] 186 41000D−AERO03/14 Bit Number Mnemonic Description 7 com7 Address/Data Stepping Control (reserved, not applicable) 6 com6 Parity Error Response Control 1 = take the normal action when a parity error is detected 0 = set the PCI Bus Parity Error Status bit (bit 31) when an error is detected but do not assert PERR* and continue normal operation 5 com5 VGA Palette Snooping (reserved, not applicable) 4 com4 Memory Write-and-Invalidate Control 1 = initiator may generate the Memory Write and Invalidate command 0 = use the Memory Write command instead 3 com3 Special Cycles Control (reserved, not applicable) 2 com2 PCI Initiator Control 1 = PCI initiator enabled 0 = PCI initiator disabled3. com1 Target Memory Command Response Control 1 = target interface is allowed to respond to Memory Space accesses 0 = target interface does not respond to Memory Space accesses com0 Target I/O Command Response Control 1 = target interface is allowed to respond to I/O Space accesses 0 = target interface does not respond to I/O Space accesses 1 0 Note: 1. Read-only bit in PCI Satellite mode (SYSEN* = 1), reflects what the remote Host-Bridge sees and controls when driving the PCI interface through PCI configuration transactions. Note: 2. Whatever the value of this bit, the PCI interface does not allow to generate fast back-to-back transactions. Caution: 3. a memory-mapped PCI transaction shall not be initiated while the PCI initiator is disabled or the processor will stall. ATF697FF [DATASHEET] 187 41000D−AERO03/14 Table 15-62. PCI Device Identification 2 PCIID2 Bit Number Mnemonic 31..8 class code 7..0 revision id class code revision id r r 0x0B4000 0x02 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000108 26 27 28 29 30 31 Address: Description The Class Code register is read-only and is used to identify the generic function of the device and, in some cases, a specific register-level programming interface. The register is broken into three byte-size fields. The upper byte (at offset 0Bh) is a base class code which broadly classifies the type of function the device performs. The middle byte (at offset 0Ah) is a subclass code which identifies more specifically the function of the device. The lower byte (at offset 09h) identifies a specific register-level programming interface (if any) so that device independent software can interact with the device. The value 0x0B4000 commonly stands for a processor device. This register specifies a device specific revision identifier. The value is chosen by the vendor. Zero is an acceptable value. This field should be viewed as a vendor defined extension to the Device ID. bist header type latency timer 1. r r r/w 0000 0000 0000 0000 0000 00 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Table 15-63. PCI Bist & Header Type & Latency & Cacheline Size Register – PCIBHLC Address= 0x8000010C cacheline size r r/w1. 00 0000 0000 Bit Number Mnemonic Description 31..24 bist Built-In Self Test (BIST) A value of 0 indicates there is no support for this feature. 23..16 header type Header Type A value of 0 indicates this is a single-function interface which implements type 00h Configuration Space Header. 15..8 latency timer Latency Timer Specifies the value of the latency timer for this bus master (in units of PCI bus clocks). ATF697FF [DATASHEET] 188 41000D−AERO03/14 Bit Number 7..0 Mnemonic Description cacheline size Cacheline Size Specifies the system cacheline size (in units of 32-bit words). Used by master devices to determine whether to use Read, Read Line or Read Multiple commands for accessing memory. Used by slave devices that want to allow memory bursting using cacheline wrap addressing mode to know when a burst sequence wraps to the beginning of the cacheline. Read-only bit in PCI Satellite mode (SYSEN* = 1), reflects what the remote Host-Bridge sees and controls when driving the PCI interface through PCI configuration transactions. Table 15-64. Memory Base Address Register 1 MBAR1 0 msi 1 2 type 3 pref 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000110 26 27 28 29 30 31 Address: r/w1. r r r r 0000 0000 0000 0000 0000 0000 0000 1 00 0 badr Bit Number Mnemonic Description 31..4 badr Base Address (least-significant null nibble omitted) Pointer to a 16 MB address space. 3 pref 2..1 type 0 msi Note: Prefetchable 1 = there are no side effects on reads: the device returns all bytes on reads regardless of the byte enables. Type 00 = the base register is 32 bits wide and mapping can be done anywhere in the 32-bit Memory Space. Memory Space Indicator 0 = the base address maps into Memory Space. 1. Read-only bit in PCI Satellite mode (SYSEN* = 1), reflects what the remote Host-Bridge sees and controls when driving the PCI interface through PCI configuration transactions. ATF697FF [DATASHEET] 189 41000D−AERO03/14 Table 15-65. Memory Base Address Register 2 MBAR2 0 msi 1 2 type 3 pref 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000114 26 27 28 29 30 31 Address: r/w1. r r r r 0000 0000 0000 0000 0000 0000 0000 1 00 0 badr Bit Number Mnemonic Description 31..4 badr Base Address (least-significant null nibble omitted) Pointer to a 16 MB address space. 3 pref 2..1 type 0 msi Note: Prefetchable 1 = there are no side effects on reads: the device returns all bytes on reads regardless of the byte enables. Type 00 = the base register is 32 bits wide and mapping can be done anywhere in the 32-bit Memory Space. Memory Space Indicator 0 = the base address maps into Memory Space. 1. Read-only bit in PCI Satellite mode (SYSEN* = 1), reflects what the remote Host-Bridge sees and controls when driving the PCI interface through PCI configuration transactions. Table 15-66. IO Base Address Register 3 IOBAR3 0 1 2 reserve d iosi 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000118 26 27 28 29 30 31 Address: badr r/w1. r r r 0000 0000 0000 0000 0000 00 0000 0000 0 1 ATF697FF [DATASHEET] 190 41000D−AERO03/14 Bit Number Mnemonic Description 31..2 badr Base Address (2 least-significant null bits omitted) Pointer to a 1 KB address space. 0 iosi I/O Space Indicator 1 = the base address maps into I/O Space. 1. Read-only bit in PCI Satellite mode (SYSEN* = 1), reflects what the remote Host-Bridge sees and controls when driving the PCI interface through PCI configuration transactions. Note: Table 15-68. Subsystem Identification Register – PCISID svi Subsystem Vendor ID 0 15..0 0 Subsystem ID 1 sid 1 31..16 2 Description 2 Mnemonic 3 Bit Number 3 0x1438 4 0x0001 4 r 5 r 5 svi 6 sid 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x8000012C 26 27 28 29 30 31 Address: Table 15-69. PCI Latency Interrupt Register – PCILI 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x8000013C 26 27 28 29 30 31 Address: max_lat min_gnt int_pin int_line r r r r/w1. 0000 0000 0000 0000 0000 0000 0000 0000 ATF697FF [DATASHEET] 191 41000D−AERO03/14 Bit Number Mnemonic Description 31..24 max_lat Maximum Latency Specifies how often the processor needs to gain access to the PCI bus. (in units of 0.25 microseconds assuming a 33 MHz clock). A value of 0 indicates there are no major requirements for this setting. 23..16 min_gnt Minimum Grant Specifies how long a burst period is needed (in units of 0.25 μs assuming a 33 MHz clock). A value of 0 indicates there are no major requirements for this setting. 15..8 int_pin Interrupt Pin Indicates which interrupt pin the processor uses. Value not relevant (PCI interrupts are not implemented). 7..0 int_line Interrupt Line Specifies which input of the system interrupt controller the interrupt pin is connected to. Value not relevant (PCI interrupts are not implemented). Note: 1. Read-only bit in PCI Satellite mode (SYSEN* = 1), reflects what the remote Host-Bridge sees and controls when driving the PCI interface through PCI configuration transactions. Table 15-71. PCI Initiator Retry & TRDY* – PCIIRT reserved retry trdy r r/w1. r/w1. 0 0x80 0x80 Bit Number Mnemonic Description 15..8 retry Maximum number of retries the PCI initiator attempts. 7..0 trdy Maximum number of PCI clock cycles the PCI initiator waits for TRDY* . Note: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000140 26 27 28 29 30 31 Address: 1. Read-only bit in PCI Satellite mode (SYSEN* = 1), reflects what the remote Host-Bridge sees and controls when driving the PCI interface through PCI configuration transactions. ATF697FF [DATASHEET] 192 41000D−AERO03/14 Table 15-72. PCI Configuration Byte-Enable – PCICBE Bit Number 3..0 reserved ben r r/w 0000 0000 0000 0000 0000 0000 0000 0000 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000144 26 27 28 29 30 31 Address: Mnemonic Description ben Byte write enables to the PCI configuration registers (0x80000100 to 0x80000140): 0 = enabled 1 = disabled A byte enable pattern, once programmed, applies to all subsequent writes until it is changed. Each of the 4 bits is assigned to one 8-bit lane: bit ben[3] is applied to Byte 3, the most-significant byte (MSB) bit ben[2] is applied to Byte 2 bit ben[1] is applied to Byte 1 bit ben[0] is applied to Byte 0, the least-significant byte (LSB) Table 15-73. PCI Initiator Start Address – PCISA stad r/w xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx Bit Number Mnemonic Description 31..0 stad PCI start address for PCI initiator transactions in DMA mode. ATF697FF [DATASHEET] 193 41000D−AERO03/14 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000148 26 27 28 29 30 31 Address: Table 15-74. PCI DMA Configuration Register – PCIDMA wcnt r r / w r/w r/w 0000 0000 0000 0000 000 0 xxxx xxxx xxxx 0 1 2 3 4 5 6 7 8 9 10 11 12 cmd reserved Bit Number 13 reserve d 14 15 16 17 18 19 20 21 22 23 24 25 0x80000150 26 27 28 29 30 31 Address: Mnemonic Description 11..8 cmd Command PCI command to use in transaction. Please refer to section 3.1.1 "Command Definition" of the PCI 2.2 specification for command details. 7..0 wcnt Word Count Number of words to transfer during the DMA burst (1 to 255). Note: Writing to this register effectively initiates the PCI transfer when the PCI core is configured for DMA mode. Table 15-75. PCI Initiator Status Register – PCIIS Mnemonic Description 12 sys SYSEN* Pin Status 0 = Host mode 1 = Satellite mode 11..8 dmas DMA State (0000 = idle) r r r r r r p 0000 0 0 1 1 0000 194 0 r 41000D−AERO03/14 1 4 rfe 2 5 xfe cs ATF697FF [DATASHEET] 3 6 xff 8 9 10 11 12 13 14 15 16 17 Bit Number 7 0000 0000 0000 0000 000 dmas act r sys reserved 18 19 20 21 22 23 24 25 0x80000154 26 27 28 29 30 31 Address: Bit Number Mnemonic Description 7 act PCI Initiator Active 1 = a PCI data transfer is on-going or has been requested 0 = no PCI data transfer on-going or requested 6 xff MXMT Transmit FIFO Full 1 = transmit FIFO full 0 = transmit FIFO not full 5 xfe MXMT Transmit FIFO Empty 1 = transmit FIFO empty 0 = transmit FIFO not empty 4 rfe MRCV Receive FIFO Full 1 = receive FIFO empty 0 = receive FIFO not empty 3..0 cs Controller State (0000 = idle) Table 15-76. PCI Initiator Configuration – PCIIC 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000158 26 27 28 29 30 31 Address: Bit Number r 0000 0000 0000 0000 0000 0000 reserved mod reserved cmd w1 r/w r r / w 01 00000 0 Mnemonic Description 7..6 cmd Most-significant bits of the PCI command used in memory-mapped PCI transactions2: 00 = I/O read or I/O write 01 = Memory Read or Memory Write 10 = Configuration Read or Configuration Write 11 = Memory Read Line or Memory Write and Invalidate 0 mod PCI Interface Mode 1 = Memory-Mapped / DMA3 0 = PCI initiator disabled ATF697FF [DATASHEET] 195 41000D−AERO03/14 Note: 1. Writing the whole register with all-1s (0xFFFFFFFF) resets the interface: flush FIFOs, reset byte-enables, reset command to Memory Read/Write and terminate any memory-mapped transaction; any active DMA burst is terminated with an initiator internal error (PCIITP.iier = 1). Note: 2. The least-significant bits depend on the instruction type that initiated the memory-mapped PCI transaction (load = 10, store = 11). Caution: 3. a memory-mapped PCI transaction shall not be initiated while the PCI initiator is disabled (PCISC.com2 = 0) or the processor will stall. Table 15-77. PCI Target Page Address Register – PCITPA tpa1 reserved tpa2 reserved r/w r r/w r 0x40 0x00 0x90 0x00 Bit Number Mnemonic 31..24 tpa1 15..8 tpa2 tpa33. n/a 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x8000015C 26 27 28 29 30 31 Address: Description Target Page Address for MBAR1 Specifies the most significant byte of the local memory address1 where the PCI target Memory Base Address Register 1 is mapped (defaults to the RAM area). Target Page Address for MBAR2 Specifies the most significant byte of the local memory address2 where the PCI target Memory Base Address Register 2 is mapped (defaults to the DSU area). Target Page Address for IOBAR3 The most significant 22 bits of the local memory address3 where the PCI target IO Base Address Register 3 is mapped in local memory (defaults to the REGISTER area). This value is not exposed and is not programmable (built-in, 1000000000000000000000). Note: 1. Assuming TPA1 is the full 32-bit address: TPA1 = tpa1 *224. TPA1 is a pointer to a 16 Mbytes area. Note: 2. Assuming TPA2 is the full 32-bit address: TPA2 = tpa2* 224. TPA2 is a pointer to a 16 Mbytes area. Note: 3. Assuming TPA3 is the full 32-bit address: TPA3 = tpa3*210 = 0x80000000. TPA3 is a pointer to a 1024 bytes / 256 words area. ATF697FF [DATASHEET] 196 41000D−AERO03/14 Table 15-78. PCI Target Status and Control Register – PCITSC r 0000 0000 0000 0000 0000 000 Bit Number Mnemonic 8 dlrd 7 rfpe r/w1. 1 r w w w / 1 1 1 w 0 0 0000 0 1 1 Description Delayed Read Automatically asserted by the PCI core during a long delayed read to prevent the on-going read from being overwritten by a subsequent write request (information provided for debug purpose only). This bit is cleared by writing a 1 (a 0 has no effect). TRCV Receive FIFO parity error 0 = Do not save data with parity error 1 = Ignore any parity error and save data anyway (generation of the perr status bit and assertion of a parity error interrupt is not affected) xff TXMT Transmit FIFO Full 1 = transmit FIFO full 0 = transmit FIFO not full Writing this bit with a 1 ends the transaction with a target abort (a 0 has no effect). xfe TXMT Transmit FIFO Empty 1 = transmit FIFO empty 0 = transmit FIFO not empty Writing this bit with a 1 flushes the transmit FIFO (a 0 has no effect). 4 rfe TRCV Receive FIFO Empty 1 = receive FIFO empty 0 = receive FIFO not empty Writing this bit with a 1 flushes the receive FIFO (a 0 has no effect). 3..0 cs Controller State (0000 = idle) Writing this nibble with all-1s (0xF) resets the state machine (any other value has no effect). 6 5 Note: 0 4 rfe 1 5 xfe r/ 2 6 xff r/ cs 7 rfpe r/ r / w 3 8 9 10 11 12 13 14 dld reserved 15 16 17 18 19 20 21 22 23 24 25 0x80000160 26 27 28 29 30 31 Address: 1. This (group of) bit(s) has a specific action when written with a (group of) 1(s). ATF697FF [DATASHEET] 197 41000D−AERO03/14 Table 15-79. PCI Interrupt Enable Register – PCIITE 6 5 4 3 2 1 0 ifer iper tier tber tper serr 7 8 reserved dm af iier 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000164 26 27 28 29 30 31 Address: 0 0 0 r r/w 0000 0000 0000 0000 0000 0000 Bit Number 0 Mnemonic Description dmaf DMA finished1 1 = enable 0 = mask iier Initiator internal error1 1 = enable 0 = mask ifer Initiator fatal error1 1 = enable 0 = mask iper Initiator parity error1 1 = enable 0 = mask tier Target internal error1 1 = enable 0 = mask tber Target byte-enable error1 1 = enable 0 = mask 1 tper Target parity error1 1 = enable 0 = mask 0 serr SERR* signal asserted on the PCI bus1 1 = enable 0 = mask 7 6 5 4 3 2 Note: 0 0 0 0 1. See the corresponding field in PCIITP for a complete description. ATF697FF [DATASHEET] 198 41000D−AERO03/14 Table 15-80. PCI Interrupt Pending Register – PCIITP 6 5 4 3 2 1 0 ifer iper tier tber tper serr 7 8 reserved dm af iier 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000168 26 27 28 29 30 31 Address: 0 0 0 r/w1 r 0000 0000 0000 0000 0000 0000 Bit Number 7 6 5 4 3 2 1 0 0 0 0 0 0 Mnemonic Description dmaf DMA finished 1 = pending 0 = not pending iier Initiator internal error2. 1 = pending 0 = not pending The PCI initiator internally faced a situation that prevented normal completion of the programmed transaction. ifer Initiator fatal error 1 = pending 0 = not pending The PCI initiator reported an address parity error or a transaction abort. iper Initiator parity error 1 = pending 0 = not pending The PCI initiator reported data with parity error on a read or write transaction. tier Target internal error3. 1 = pending 0 = not pending The PCI target internally faced a situation that prevented normal completion of the programmed transaction. tber Target byte-enable error 1 = pending 0 = not pending The PCI target received data with unsupported byte-enables. tper Target parity error 1 = pending 0 = not pending The PCI target received data with parity error. serr SERR* signal asserted on the PCI bus 1 = pending 0 = not pending ATF697FF [DATASHEET] 199 41000D−AERO03/14 Note: 1. Each bit is cleared when written with a 1 (writing a 0 has no effect). Note: 2. An initiator internal error is reported on the following events: initiator busy or not ready (already active DMA transfer), local memory 1 KB address boundary reached (DMA), attempt to transfer data to/from the PCI mapped-address area (DMA), invalid data read or written (timeout), interface reset during an active DMA transfer... Note: 3. A target internal error is reported on the following events: invalid data read or written (timeout). Table 15-81. PCI Interrupt Force Register – PCIITF 6 5 4 3 2 1 0 ifer iper tier tber tper serr 7 8 dm af iier reserved 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x8000016C 26 27 28 29 30 31 Address: r 0000 0000 0000 0000 0000 0000 Bit Number 7 6 5 4 3 2 1 1 r1/w2 r1. 0 Mnemonic Description dmaf DMA finished3 1 = forced 0 = cleared4. iier Initiator internal error3 1 = forced 0 = cleared4. ifer Initiator fatal error3 1 = forced 0 = cleared4. iper Initiator parity error3. 1 = forced 0 = cleared4. tier Target internal error3. 1 = forced 0 = cleared4. tber Target byte-enable error3. 1 = forced 0 = cleared4. tper Target parity error3. 1 = forced 0 = cleared4. 0 0 ATF697FF [DATASHEET] 0 / w 0 0 200 41000D−AERO03/14 0 0 Bit Number 0 Mnemonic Description serr SERR* asserted on the PCI bus3. 1 = forced 0 = not forced Note: 1. This is a write-only register, reading this register always yields the contents of PCIITP. Note: 2. A PCI interrupt is generated on the write operation itself. Note: 3. See the corresponding field in PCIITP for a complete description. Note: 4. Writing a 0 clears the corresponding bit in PCIITP rather than not forcing it. Table 15-82. PCI DMA Address Register – PCIDMAA 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000178 26 27 28 29 30 31 Address: addr Bit Number 31..0 r/w r xxxx xxxx xxxx xxxx xxxx xxxx xxxx xx 00 Mnemonic Description addr When written, defines the start address of a DMA burst in local memory and initiates the DMA burst. When read, provides the current or last address of the latest DMA burst. During a DMA burst, this register is automatically incremented (+4) with each word transferred until the programmed burst count or the end of a 1 KB segment is reached, whichever comes first. Table 15-83. PCI Arbiter Register – PCIA 3 2 1 0 p3 p2 p1 p0 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x80000280 26 27 28 29 30 31 Address: r r r / w r / w r / w 0000 0000 0000 0000 0000 0000 0000 1 1 reserved ATF697FF [DATASHEET] 201 41000D−AERO03/14 1 1 Bit Number Mnemonic Description 3 p3 Round robin priority level for agent 3 2 p2 Round robin priority level for agent 2 1 p1 Round robin priority level for agent 1 0 p0 Round robin priority level for agent 0 ATF697FF [DATASHEET] 202 41000D−AERO03/14 15.12 DSU Registers Caution: This section is provided for information purpose only. Caution: As its name clearly states, the Debug Support Unit is exclusively meant for debugging purpose. None of the DSU features shall ever be used in the final application where the DSU shall be turned into an inactive state (DSUEN, DSURX and DSUBRE tied to a permanent low level). Table 15-84. DSU Control Register – DSUC r r/w 000 x xxxx xxxx 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 lr ss pe ee eb dm de bz bx bd bn bs bw be ft bt dm te dcnt re reserv ed dr 0x90000000 31 30 29 28 27 26 25 24 23 22 21 20 19 Address: r r r r w / / / / r w w w w 0 0 0 0 0 r r r r r r r r r r r r r r / / / / / / / / / / / / w w w w w w w w w w w w p p 0 0 p p 0 p 0 p p 0 0 x 0 Bit Number Mnemonic Description 28..20 dcnt Trace buffer delay counter re Reset error mode If set, will clear the error mode in the processor. This is a write-only bit, always reads as a 0. 18 dr Debug mode response If set, the DSU communication link will send a response word when the processor enters debug mode 17 lr Link response If set, the DSU communication link will send a response word after an AHB transfer. 16 ss Single step If set, the processor will execute one instruction and then return to debug mode. 15 pe Processor error mode returns 1 on read when processor is in error mode else return 0. 14 ee Value of the DSUEN signal (read-only) 13 eb Value of the DSUBRE signal (read-only) 12 dm Debug mode If set, indicates the processor has entered debug mode (read-only). 19 ATF697FF [DATASHEET] 203 41000D−AERO03/14 Bit Number Mnemonic Description de Delay counter enable If set, the trace buffer delay counter will decrement for each stored trace. This bit is set automatically when an DSU breakpoint is hit and the delay counter is not equal to zero. 10 bz Break on error traps If set, will force the processor into debug mode on all but the following traps: priviledged_instruction, fpu_disabled, window_overflow, window_underflow, asynchronous_interrupt, ticc_trap. During reset, this bit is initialized with the value of the DSUBRE signal. 9 bx Break on trap If set, will force the processor into debug mode when any trap occurs. 8 bd Break on DSU breakpoint If set, will force the processor into debug mode when an DSU breakpoint is hit. During reset, this bit is initialized with the value of the DSUBRE signal. 11 7 bn 6 bs 5 bw Break now If set, will force the processor into debug mode provided bit 5 (bw) is also set. If cleared, the processor will resume execution. During reset, this bit is initialized with the value of the DSUBRE signal. Break on S/W breakpoint If set, will force the processor into debug mode when a breakpoint instruction (ta 1) is executed. Break on IU watchpoint If set, debug mode will be forced on a IU watchpoint (trap 0xb). During reset, this bit is initialized with the value of the DSUBRE signal. Break on error If set, will force the processor into debug mode when the processor would have entered error mode. During reset, this bit is initialized with the value of the DSUBRE signal. Freeze timers If set, the scaler in the timer unit will be stopped during debug mode to preserve the time for the software application. 4 be 3 ft 2 bt Break on trace freeze If set, will generate a DSU break condition on trace freeze. 1 dm Delay counter mode In mixed tracing mode, setting this bit will cause the delay counter to decrement on AHB traces. If reset, the delay counter will decrement on instruction traces 0 te Trace enable. If set, the trace buffer is enabled. ATF697FF [DATASHEET] 204 41000D−AERO03/14 Table 15-85. Trace Buffer Control Register – TBCTL x xxxx xxxx 000 x xxxx xxxx Bit Number Mnemonic Description 26 af AHB trace buffer freeze If set, the trace buffer will be frozen when the processor enters debug mode. 25 ta Trace AHB enable 24 ti Trace instruction enable 20..12 bcnt AHB trace index counter 8..0 icnt Instruction trace index counter 0 000 0 x 1 x 1 x 2 r/w 2 r 3 r/w 4 r 5 icnt 6 reserve d 7 bcnt 8 reserve d 9 10 11 12 13 14 15 16 17 18 19 20 t i r / w 000000 21 t a r / w r 22 24 a f r / w reserved 23 25 0x90000004 26 27 28 29 30 31 Address: Table 15-86. Time Tag Counter – TTC cnt r r/w 00 00 0000 0000 0000 0000 0000 0000 0000 Bit Number Mnemonic Description 29..0 cnt Counter value ATF697FF [DATASHEET] 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 0x90000008 reserved 31 Address: 205 41000D−AERO03/14 Table 15-87. Break Address Register 1 BAD1 1 0 reserved ex r/w r w xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x90000010 26 27 28 29 30 31 Address: 0 adr Bit Number Mnemonic Description 31..2 adr Breakpoint address (32-bit aligned address, hence the 2 omitted LSB) 0 ex Enables break on executed instruction This is a write-only bit, always reads as a 0. Table 15-88. Break Mask Register 1 BMA1 1 0 ld st r/w r/w r / w xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x90000014 26 27 28 29 30 31 Address: 0 msk Bit Number Mnemonic Description 31..2 msk Breakpoint Address Mask (32-bit aligned address, hence the 2 omitted LSB) 1 ld Enables break on AHB load 0 st Enables break on AHB write ATF697FF [DATASHEET] 206 41000D−AERO03/14 Table 15-89. Break Address Register 2 BAD2 1 0 reserved ex r/w r w xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x90000018 26 27 28 29 30 31 Address: 0 adr Bit Number Mnemonic Description 31..2 adr Breakpoint address (32-bit aligned address, hence the 2 omitted LSB) 0 ex Enables break on executed instruction This is a write-only bit, always reads as a 0. Table 15-90. Break Mask Register BMA2 1 0 ld st r/w r/w r / w xx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x9000001C 26 27 28 29 30 31 Address: 0 msk Bit Number Mnemonic Description 31..2 msk Breakpoint Address Mask (32-bit aligned address, hence the 2 omitted LSB) 1 ld Enables break on AHB load 0 st Enables break on AHB write ATF697FF [DATASHEET] 207 41000D−AERO03/14 Table 15-91. DSU UART Status Register – DSUUS 6 5 4 3 2 1 0 fe reserved ov br th ts dr 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x800000C4 26 27 28 29 30 31 Address: r r / w r r / w r / w r r r 0000 0000 0000 0000 0000 0000 0 0 0 0 0 1 1 0 reserved Bit Number Mnemonic Description 6 fe Framing error Indicates that a framing error was detected. 4 ov Overrun Indicates that one or more character have been lost due to overrun. 2 th Transmitter hold register empty Indicates that the transmitter hold register is empty. 1 ts Transmitter shift register empty Indicates that the transmitter shift register is empty. 0 dr Data ready Indicates that new data is available in the receiver holding register. Table 15-92. DSU UART Control Register – DSUUC 1 0 bl uen 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x800000C8 26 27 28 29 30 31 Address: r r / w r / w 0000 0000 0000 0000 0000 0000 0000 00 0 0 reserved ATF697FF [DATASHEET] 208 41000D−AERO03/14 Bit Number Mnemonic Description 1 bl Baud-rate locked Automatically set when the baud rate is locked. 0 uen UART enable If set, enables both the receiver and the transmitter. Table 15-94. DSU UART Scaler Reload Register – DSUUR reserved ab rv r r/w r/w 0000 0000 0000 00 0 1 2 3 4 5 6 11 1111 1111 1111 1111 Bit Number Mnemonic Description 17..16 ab Scaler reload value 15..0 rv Scaler reload value Note: 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 0x800000CC 26 27 28 29 30 31 Address: The following equations shall be used to calculate the scaler value or the baudrate value based on the clock frequency: sdclk freq 1 baudrate 8 sdclk freq baudrate 8 scalerrv 1 scalerrv ATF697FF [DATASHEET] 209 41000D−AERO03/14 15.13 Reconfigurable unit register description The ATF697FF reconfigurable unit (AT40K series) devices have a 32-bit control register that is written at the beginning of a configuration download. These bits control various configuration sequence parameters. All bits are set to 0 during a configuration clear cycle. In parallel modes, byte 0 is loaded first. In serial modes, bit-31 is loaded first. The control register settings are made in the FPGA Designer IDS Software Options section: Go to the Options menu on the IDS (Figaro) main window and select Options. Choose AT40K Bitstream from the topics list1. IDS uses names "B0" ~ "B31" for "CR0" ~ "CR31" for the Control Register. Caution: Table 15-95. Control Registers Byte 3 Byte 2 Byte 1 Byte 0 CR31 CR23 CR15 CR7 CR30 CR22 CR14 CR6 CR29 CR21 CR13 CR5 CR28 CR20 CR12 CR4 CR27 CR19 CR11 CR3 CR26 CR18 CR10 CR2 CR25 CR17 CR9 CR1 CR24 CR16 CR8 CR0 CR0 – Mode 6 Address Counter 0 = Reset Address Counter 1 = Retain Address Counter CR0 controls the value of the Mode 6 device’s memory address counter after each configuration sequence. The default resets the address up-counter to 000000 after each configuration download is completed. When this bit is set, the memory address counter retains its last value. This allows multiple designs to be stored sequentially in an external memory device for use in reconfigurable systems. Caution: The mode 6 is not avialable in the ATF697FF product. Hence, the CR0 shall be always set to 0. CR1 Not used (ignored) CR2 Cascading 0 = Enable Cascading 1 = Disable Cascading CR2 controls the operation of the dual-function I/O CSOUT. When CR2 is set, the CSOUT pin is not used by the configuration during downloads. CR3 Check 0 = Check Function enabled 1 = Check Function disabled CR3 controls the operation of the CHECK pin and enables the Check Function. When CR3 is set, the CHECK pin is not used by the configuration during downloads. CR4 Memory Lockout 0 = Memory Lockout disabled 1 = Memory Lockout enabled ATF697FF [DATASHEET] 210 41000D−AERO03/14 CR4 is the Security Flag and controls the writing and checking of configuration memory during any subsequent configuration download. When CR4 is set, any subsequent configuration download initiated by the user, whether a normal download or a CHECK function download, causes the INIT pin to immediately activate. CON is released, and no further configuration activity takes place. The download sequence during which CR4 is set is NOT affected. The Control Register write is also prohibited, so bit CR4 may only be cleared by a power-on-reset or manual reset. CR5 JTAG 0 = JTAG enable 1 = JTAG disable Caution: The JTAG is not avialable in the ATF697FF product. Hence, the CR5 shall be always set to ‘1’. CR6 – OTS 0 = OTS disabled 1 = OTS enabled Setting CR6 makes the OTS pin an input which controls the global tri-state control for all user I/O. CR7 – Parallel bus width 0 = 8-bit data access 1 = 16-bit (Wide) data access CR7 is the Wide data control bit. Setting this bit immediately enables bits D8:D15 of the configuration interface as inputs for all parallel modes (2 and 6). All writes and checks of configuration memory are subsequently performed by 16 bits. CR7 is ignored in serial modes (0, 1 and 7). Caution: The parrallel modes are not avialable in the ATF697FF product. Hence, CR7 is ignored. CR8 Recurrent checksum 0 = no recurrent checksum 1 = activates the recurrent checksum If configured in Master mode 0, it is mandatory to activate CR13 bit when using CR8 bit in order to clock the CSIC feature. For all other modes, CCLK shall be provided from the external. CR9 Function bad_state 0 = no function bad_state 1 = enables the function bad_state during the FPGA configuration CR10 Not used (ignored) CR11 Not used (ignored) CR12 Not used (ignored) CR13 – CCLK operation 0 = CCLK normal operation 1 = CCLK continues after configuration Setting bit CR13 allows the CCLK pin to continue to run after configuration download is completed. This bit is valid for Master Mode only. CR14/CR15 – CCLK Frequency 00 = 1 MHz ATF697FF [DATASHEET] 211 41000D−AERO03/14 01 = 4 MHz 10 = 8 MHz 11 = 16 MHz Bits CR14 and CR 15 speed up the internal oscillator and allow the Master Mode to drive CCLK at 1, 4, 8 or 16 MHz. As soon as the values of these bits are sampled by the FPGA, the CCLK frequency is increased consequently. CR16/CR23 – GCK enable 0 = GCK 0:7 always enabled 1 = GCK 0:7 disabled during configuration download. Setting CR16:C23 allows the user to disable the input buffers driving the global clocks. The clock buffers are enabled and disabled synchronously with the rising edge of the respective GCLK signal, and stop in a High (“1”) state. Setting one of these bits disables the appropriate GCLK input buffer only and has no effect on the connection from the input buffer to the FPGA array. CR24/CR27 – FCK enable 0 = FCK 0:3 always enabled 1 = FCK 0:3 disabled during configuration download. Setting CR24.C27 allows the user to disable the input buffers driving the fast clocks. The clock buffers are enabled and disabled synchronously with the rising edge of the respective FCLK signal, and stop in a High (“1”) state. Setting one of these bits disables the appropriate FCLK input buffer only and has no effect on the connection from the input buffer to the FPGA array. CR28 Reserved Caution: must be '0' CR29 Not used (ignored) CR30 – Global Set/Reset 0 = Global set/reset normal 1 = Global set/reset active (Low) during configuration CR30 allows the Global set/reset hold the core DFFs in set/reset during any configuration download. The Global set/reset net is released at the end of configuration download on the rising edge of CON. CR31 – IO tristate 0 = Disable I/O tri-state 1 = I/O tri-state during configuration CR31 forces all user defined I/O pins to go tri-state during configuration download. tri-state is released at the end of configuration download on the rising edge of CON. ATF697FF [DATASHEET] 212 41000D−AERO03/14 16. 16.1 Packaging information Packaging drawing: MQFPT352 ATF697FF [DATASHEET] 213 41000D−AERO03/14 Pin mapping: MQFPT352 16.2 Pin Number Pin Name Pin Number Pin Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 IO482_GCK5 IO487 IO493 IO497 IO503 IO505 IO507 IO511 IO513 IO517 IO519 IO523 IO525 IO527 IO531 IO533 FPGA_VDD18 VSS IO537 IO539 IO543_FCK3 IO545 IO547_CS0* IO551 IO553 IO557 IO559 IO563 IO565 IO567 IO571 IO573 FPGA_VCC33 VSS IO577 FPGA_VDD18 IO579 IO583 IO585 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 CB[7] D[0] D[1] D[2] D[3] D[4] D[5] PROC_VDD18 VSS D[6] D[7] D[8] D[9] D[10] D[11] D[12] D[13] D[14] D[15] D[16] D[17] D[18] D[19] PROC_VDD18 VSS D[20] D[21] D[22] D[23] D[24] D[25] D[26] D[27] D[28] D[29] D[30] D[31] SDCAS* SDCLK ATF697FF [DATASHEET] 214 41000D−AERO03/14 Pin Number Pin Name Pin Number Pin Name 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 IO591 IO593_ILVDSB1 IO594_ILVDSB1N IO597_ILVDSB2 IO598_ILVDSB2N LVDS_REF_B IO599_OLVDSB1 IO600_OLVDSB1N IO603_OLVDSB2 IO604_OLVDSB2N VSS IO605 IO607 IO611 IO613 IO617 IO619 IO623 IO625 IO627 IO633 IO637 IO639 IO643 IO645 FPGA_VCC33 VSS IO647 IO651 IO653 IO655_CHECK* IO658_FCK4 IO661 IO665 IO667 IO673 IO679 IO685 IO671 IO677 IO683 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 PROC_VCC33 VSS SDCS*[0] SDCS*[1] SDDQM[0] SDDQM[1] SDDQM[2] SDDQM[3] SDRAS* SDWE* A[0] A[1] A[2] A[3] A[4] A[5] PROC_VDD18 VSS A[6] A[7] A[8] A[9] A[10] A[11] A[12] A[13] A[14] A[15] A[16] A[17] A[18] A[19] PROC_VDD18 VSS A[20] A[21] A[22] A[23] A[24] A[25] A[26] ATF697FF [DATASHEET] 215 41000D−AERO03/14 Pin Number Pin Name Pin Number Pin Name 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 FPGA_VDD18 VSS IO687 IO693 IO691 IO697 IO699 IO703 IO705 IO707 IO711 IO713_D0 IO717 Reserved1 IO720_GCK6_CSOUT IO722_GCK7 FPGA_VDD18 VSS IO725 CCLK IO727 IO731 IO733 IO737 IO739 IO743 IO745 IO747 IO751 IO753 IO757 IO759 FPGA_VCC33 VSS IO763 IO765 IO767 IO771 IO773 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 A[27] GPIO[0] GPIO[1] GPIO[2] GPIO[3] GPIO[4] GPIO[5] FPGA_VDD18 VSS GPIO[6] GPIO[7] GPIO[8] GPIO[9] GPIO[10] GPIO[11] GPIO[12] GPIO[13] GPIO[14] GPIO [15] PROC_VDD_PLL PROC_VSS_PLL IO225_OTS* IO240_GCK2 PROC_VCC33 VSS IO241_GCK3 IO259_LDC IO265_HDC IO303_INIT IO353_ILVDSA1 IO354_ILVDSA1N IO357_ILVDSA2 IO358_ILVDSA2N LVDS_REF_A IO359_OLVDSA1 IO360_OLVDSA1N IO363_OLVDSA2 IO364_OLVDSA2N IO365 1 Please refer to JTAG section. ATF697FF [DATASHEET] 216 41000D−AERO03/14 Pin Number Pin Name Pin Number Pin Name 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 IO777 IO779 IO783 IO785 IO787 IO791 IO793 IO1_GCK1 IO960_GCK8 FPGA_VDD18 VSS Reserved1 Reserved1 Reserved1 Reserved1 BEXC* SKEW [0] SKEW [1] DSURX DSUTX DSUEN DSUBRE DSUACT BYPASS CLK PROC_VCC33 VSS LOCK PROC_RESET* ERROR* WDOG* M1 M0 M2 WRITE* READ ROMS*[0] ROMS*[1] BRDY* 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 FPGA_VDD18 VSS IO367 IO371 IO373 IO377 IO379 IO383 IO385 IO387 IO397 IO393 IO399 IO403 IO405 IO407 FPGA_VCC33 VSS IO411 IO413 IO417 IO419 IO423 IO425 IO427 IO431 IO433 IO437 IO439 IO443 IO445 IO447 FPGA_VDD18 VSS IO453 IO457 IO459 IO463 IO465 1 Please refer to JTAG section. ATF697FF [DATASHEET] 217 41000D−AERO03/14 Pin Number Pin Name Pin Number Pin Name 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 OE* IOS* FPGA_VDD18 VSS RWE*[0] RWE*[1] RWE*[2] RWE*[3] RAMOE*[0] RAMOE*[1] RAMOE*[2] RAMOE*[3] RAMOE*[4] RAMS*[0] RAMS*[1] RAMS*[2] RAMS*[3] RAMS*[4] FPGA_VDD18 VSS CB[0] CB[1] CB[2] CB[3] CB[4] CB[5] CB [6] 344 345 346 347 348 349 350 351 352 IO467 IO471 IO473 IO477 CON IO480_GCK4 IO485 IO491 FPGA_RESET* Caution: The bottom pads are used only for manufacturing purpose. Caution: They bottom pads be left unconnected for end user application. Caution: It is recommended not to have routing under the pad area. ATF697FF [DATASHEET] 218 41000D−AERO03/14 17. Electrical characteristics 17.1 Absolute maximum ratings Operating Temperature .............................................................................. -55 °C to +125 °C Storage Temperature .................................................................................. -65 °C to +150 °C Maximum junction temperature (TJ) ............................................................................ 175°C Thermal resistance junction to case (Rjc) ................................................................0.54°C/W Voltage on Core ............................................................................................ -0.3 V to + 2.0 V Voltage on I/O .............................................................................................. -0.3 V to + 4:0 V DC current PROC_VCC33 (PROC_VDD18) and PROC_VSS33 (PROC_VSS18) Pins…….200 mA Input Voltage on I/O pins with respect to Ground ........................................... -0.5 V to +4 V DC current per I/O pins ................................................................................................ 40 mA ESD (HBM)…………………………………………….………………………….………………….(class 2) 2000 to 3999 V (CDM).....................................................(class C4) (750<CDM ESD sensitivity level <1000 V) Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ATF697FF [DATASHEET] 219 41000D−AERO03/14 17.2 DC characteristics 17.2.1 DC characteristics The external shared pins are A[0:27], D[0:31], ROMS[0:1],IOS,RAMS[0:4],RAMOE[0:4], OE, WRITE, READ, SDCLK, BEXC, BRDY, RWE[0:3] & GPIO[0:7]. Table 17-1. DC characteristics Symbol PROC_VCC33 PROC_VDD18 PROC_VDD_PLL FPGA_VCC33 FPGA_VDD18 IIL IIH IOZL Parameter I/O Power Supply Voltage Core Power Supply Voltage PLL power supply I/O power supply voltage Core Power Supply Voltage Min Typ Max Unit 3.0 3.3 3.6 V 1.65 1.8 1.95 V 1.65 1.8 1.95 V 3.0 3.3 3.6 V 1.65 1.8 1.95 V Low Level Input Leakage Current -1 1 uA -600 -20 uA -1 1 uA 20 600 uA -1 1 uA High Level Input Leakage Current Output leakage current tristate (low level applied) -600 -20 uA Test Conditions Vin =PROC_VSS33 FPGA_VSS33 Vin =PROC_VSS33 FPGA_VSS33 With pull up Vin = PROC_VCC33 (max) FPGA_VCC33 (max) Vin = PROC_VCC33 (max) FPGA_VCC33 (max) With pull down Vin =PROC_VSS33 FPGA_VSS33 Vin =PROC_VSS33 FPGA_VSS33 With pull up ATF697FF [DATASHEET] 220 41000D−AERO03/14 Output leakage current tristate (high level applied) IOZH VIL CMOS Low Level Input Voltage VIH CMOS High Level Input Voltage VOL Low Level Output Voltage VOH High Level Output Voltage Vcsth1 ColdSparing Supply Voltage Threshold for CMOS ICCSb2 Standby Current IICS Cold sparing leakeage input current -1 1 uA 20 600 uA -0.3 70%VCC 30% VCC 4 0.4 PROC_VCC33-0.4 FPGA_VCC33-0.4 -1 V VCC=PROC_VCC33 = FPGA_VCC33 V VCC=PROC_VCC33 = FPGA_VCC33 V V 0.5 Vin = PROC_VCC33 (max) FPGA_VCC33 (max) Vin = PROC_VCC33 (max) FPGA_VCC33 (max) With V 5 mA 1 µA Vin = PROC_VCC33 FPGA_VCC33 IOL = 2, 4, 8, 10 & 14 mA Vin = PROC_VCC33 FPGA_VCC33 IOH = 2, 4, 8, 10 & 14 mA Ileakage < 4 μA VCC33= PROC_VCC33(max) FPGA_VCC33(max) no clock active VCC33 = PROC_VSS FPGA_VSS Vin = PROC_VSS to PROC_VCC33 (max) FPGA_VSS to FPGA_VCC33(max) ATF697FF [DATASHEET] 221 41000D−AERO03/14 Cold sparing leakeage output current IOCS VCC33 = PROC_VSS FPGA_VSS -1 1 Note: 1. This value is not tested and for information only Note: 2: This measurement is done with PROC On and FPGA off. Vin = PROC_VSS to PROC_VCC33 (max) FPGA_VSS to FPGA_VCC33(max) µA 17.2.2 LVDS AC/DC characteristics Table 17-2. LVDS Driver DC/ AC Characteristics Symbol |VOD| VOS |ΔVOD| |ΔVOS| Parameter Output differential voltage Output offset voltage Change in VOD between "0" and "1" Change in VOS between "0" and "1" ISA, ISB Output current ISAB Output current F Max. Clock Tfall Trise Tp Tsk1 Tsk2 Maximum operating frequency Clock signal duty cycle Fall time 80-20% Rise time 20-80% Propagation delay Duty cycle skew Channel to channel skew (same edge) Test Condition Min Max Units Comments Rload = 100 247 454 mV see Figure below Rload = 100 1125 1375 mV see Figure below Rload = 100 0 50 mV – Rload = 100 0 50 mV – 1 6.2 mA 2.6 4.8 mA – VCC = 3.3V ± 0.3V – 200 MHz Consumption 20.9 mA Max. frequency 45 55 % – Rload = 100 Rload = 100 Rload = 100 Rload = 100 445 445 1120 0 838 841 2120 80 ps ps ps ps see Figure below see Figure below see Figure below – Rload = 100 0 50 ps – Drivers shorted to ground or VCC Drivers shorted together ATF697FF [DATASHEET] 222 41000D−AERO03/14 Figure 17-1. Test Termination Measurments Figure 17-2. Rise and Fall time measurements Table 17-3. LVDS Receiver DC/ AC Characteristics Symbol VCM Parameter Input differential voltage Input offset range Tp Propagation delay Tskew Duty distortion VID cycle Test Condition Min Max Units Comments - 200 600 mV – - Cout = 50 pF, VDD = 3.3V ± 0.3V 400 2000 mV – 0.7 2.4 Ns – Cout = 50 pF - 500 ps – ATF697FF [DATASHEET] 223 41000D−AERO03/14 17.3 Cold sparing Cold sparing capability of the IOs allows to be electricaly connected to a bus while its power supply remains in the range [VSS-300mV/VSS+300mV], this without any risk of damage for the device. Cold-sparing allows a redundant spare to be electrically connected but unpowered until needed. For applications requiring high reliability, the capability to use of a redundant device is a key feature. Cold sparing availability on the ATF697FF makes the product especially suitable for high reliability systems. The cold sparing feature is available for: All the General Purpose Ios of the reconfigurable part All the LVDS Ios of the reconfigurable part All the inputs of the processor part They present a high input impedance when unpowered [VSS-300mV / VSS+300mV] and exhibit a negligible leakage current if exposed to a non-null input voltage at that time. Remarks: All the internal PCI pins are required to be clamped to both the ground and power rails to comply with the PCI Specification. However, they are cold-sparing as the clamp to PROC_VCC33 is removed when unpowered (and clamped to VCC33 when powered). The clamp to PROC_VSS33 is always present whatever the power condition. 17.4 Power sequencing 17.4.1 Global sequencing The ATF697FF is based on Atmel ATC18RHA 0.18 µm CMOS process. When the ATF697FF needs to be powered "on/off" while other circuits in the application are still powered, the recommended power “on/off” sequence is: power-up: first power PROC_VCC33 (I/O) & FPGA_VCC33 (I/O), and then power PROC_VDD18 (Core) & FPGA_VDD18 (Core). power-down: first unpower PROC_VDD18 (Core) & FPGA_VDD18 (Core), and then unpower PROC_VCC33 (I/O) & FPGA_VCC33 (I/O). It is also recommended to stop all activity during these phases as a bi-directional could be in an undetermined state (input or output mode) and create bus contention. 17.4.2 ATF697FF reconfigurable unit : Power-On Management ATF697FF reconfigurable unit has an inrush current during power-up phase that need to be considered with care by the board designer in order to adjust his power consumption budget. This inrush current is due to indeterminate states of configuration memory cells not already initialized which create an excessive leakage current. The ATF697FF reconfigurable unit design has been optimized in order to rminimize the leakage causing the inrush current. ATF697FF [DATASHEET] 224 41000D−AERO03/14 Figure 17-3. Inrush current The following table shows the ATF697FF reconfigurable unit inrush characteristics Table 17-4. Inrush Current VDD=1.8V 125°C 90°C 25°C -30°C -55°C IVDD (A) Worst Case 2 2 2 2 2 Typical 1.8 1.7 1.7 1.6 1.5 Since the inrush current can reach more than 1.8A, we recommend users to dimension their power supply in order to be able to provide at least 2 Amps peak current. ATF697FF [DATASHEET] 225 41000D−AERO03/14 17.5 Power Consumption 17.5.1 Power consumption of processor part The power consumption is the sum of three basic contributions: P = PCore + PI/O + PPCI PCore represents the contribution of the internal activity. PI/O represents the contribution of the IO pads (except the PCI bus) and associated output load current . PPCI represents the contribution of the PCI pads and associated output load current. Table 17-5. Power Dissipation Conditions Typical1. Worst-Case2 Power (in W) PCore PI/O PPCI PCore PI/O PPCI 0.5 0.2 0.1 0.7 0.3 0.2 Note: 1. Typical conditions: 25°C, 1.8V core, 3.3V I/O, 100 MHz, high I/O and core activity. Note: 2. Worst-case conditions: -55°C, 1.95 V core, 3.6V I/O, 100 MHz, high I/O and core activity. 17.5.2 Power consumption of reconfigurable unit The worst case consumption for the reconfigurable unit part is during power on. Please see the corresponding section for details. 17.6 AC Characteristics The ATF697FF implements a single event transient (SET) protection mechanism. The influence of this protection is reflected by the timing figures presented in the following tables. The following tables show the timing figures for the natural and maximum skew conditions. 17.6.1 Natural Skew 17.6.1.1 Test Conditions Natural Skew Temperature range: -55°C to 125°C Voltage range: I/O: 3.3V ± 0.30V Core: 1.8V ± 0.15V Output load: 50 pF Voltage threshold Test condition: Vcc/2 ATF697FF [DATASHEET] 226 41000D−AERO03/14 Table 17-6. AC Characteristics Natural Skew Parameter Min (ns) t1 10 t1_p 1 40 Max (ns) Reference edge (‘+’ for rising edge) Comment CLK period with PLL disabled 50 CLK period with PLL enabled t2 4.5 CLK low or high pulse width PLL disabled t2_p 18 CLK low or high pulse width PLL enabled t3 10 SDCLK period t4 3 t5 8 SDCLK output delay PLL disabled 10.00E+07 PLL setup time CLK PROC_RESET* low pulse width2 t6 1*t3 t10 1.5 8 A[27:0] output delay SDCLK + t11 2 8.5 D[31:0] and CB[7:0] output delay SDCLK + t12 4 D[31:0] and CB[7:0] setup time SDCLK + t13 0 t14 0 9 t15 1 7 OE* , READ and WRITE* output delay SDCLK + t16 2 5.5 ROMS* [1:0] output delay SDCLK + t17 1.5 6 RAMS* [4:0], RAMOE* [4:0] and RWE* [3:0]output delay SDCLK + t18 2 5.5 IOS* output delay SDCLK + t19 5 BRDY* setup time SDCLK + t20 0 BRDY* hold time SDCLK + t21 2 8 SDCAS* output delay SDCLK + t22 1.5 8.5 SDCS* [1:0], SDRAS* , SDWE* and SDDQM [3:0]output delay SDCLK + t23 4.5 BEXC* setup time SDCLK + t24 0 BEXC* hold time SDCLK + t25 1.5 GPIO[15:0] output delay SDCLK + t26 5 GPIO[15:0] setup time SDCLK + t27 0 GPIO[15:0] hold time during load SDCLK + 10 D[31:0] and CB[7:0] hold time during load/fetch D[31:0] and CB[7:0] hold time during write3. SDCLK + SDCLK + ATF697FF [DATASHEET] 227 41000D−AERO03/14 t28 2.5 GPIO[15:0] hold time during write3 SDCLK + Note: 1 Not tested, guaranteed by design. Note: 2. Although the processor is being reset asynchronously, this timing is a minimum requirement to guarantee a proper reset of the processor: a glitch of any shorter duration may lead to an unpredictable behavior. Note: 3. The given timing indicates when the buffer is not driving any level on the bus. This timing is independent of the capacitive load. 17.6.2 Maximum Skew 17.6.2.1 Test Conditions Maximum Skew Programmed Temperature range: -55°C to 125°C Voltage range: I/O: 3.3V ± 0.30V Core: 1.8V ± 0.15V Output load: 50pF Voltage threshold Test condition: Vcc/2 ATF697FF [DATASHEET] 228 41000D−AERO03/14 Table 17-7. AC Characteristics Maximum Skew Min Max (ns) (ns) Parameter Reference edge Comment (‘+’ for rising edge) t1 t1_p 1 12 48 t2 5.4 CLK low or high pulse width PLL disabled t2_p 21 CLK low or high pulse width PLL enabled t3 10 SDCLK period t4 3 t5 50 CLK period with PLL disabled CLK period with PLL enabled 8 SDCLK output delay PLL disabled 10.00E+07 PLL setup time CLK PROC_RESET* low pulse width1. t6 1*t3 t10 t11 t12 1.5 2 4 t13 0 t14 1 11 t15 1 t16 9 9.5 A[27:0] output delay D[31:0] and CB[7:0] output delay D[31:0] and CB[7:0] setup time D[31:0] and CB[7:0] hold time during load/fetch D[31:0] and CB[7:0] hold time during write2. SDCLK + SDCLK + SDCLK + 7.5 OE* , READ and WRITE* output delay SDCLK + 2 8 SDCLK + t17 1.5 7 ROMS* [1:0] output delay RAMS* [4:0], RAMOE* [4:0] and RWE* [3:0]output delay t18 2 7 IOS* output delay SDCLK + t19 t20 t21 5 0 2 10 SDCLK + SDCLK + SDCLK + t22 1.5 9.5 t23 t24 t25 4.5 0 1.5 BRDY* setup time BRDY* hold time SDCAS* output delay SDCS* [1:0], SDRAS* , SDWE* and SDDQM [3:0]output delay BEXC* setup time BEXC* hold time GPIO[15:0] output delay t26 5 GPIO[15:0] setup time SDCLK + t27 0 GPIO[15:0] hold time during load SDCLK + t28 2.5 GPIO[15:0] hold time during write2 SDCLK + 11 SDCLK + SDCLK + SDCLK + SDCLK + SDCLK + SDCLK + SDCLK + ATF697FF [DATASHEET] 229 41000D−AERO03/14 Note: 1. Although the processor is being reset asynchronously, this timing is a minimum requirement to guarantee a proper reset of the processor: a glitch of any shorter duration may lead to an unpredictable behavior. Note: 2. The given timing applies when the buffer is not driving any level on the bus. This timing is independent of the capacitive load. 17.6.3 Timing Derating The timing figures change with the capacitance load on each pin. The following table summarizes the timing derating versus the capacitance load in the whole process / voltage / temperature range. Table 17-8. Timing Derating (ns/pF above 50pF) Signal A[27:0] CB[7:0] D[31:0] DSUACT DSUTX ERROR* IOS* LOCK OE* PIO[15:0] RAMOE*[4:0] RAMS*[4:0] READ ROMS*[1:0] RWE*[3:0] SDCAS* SDCLK SDCS*[1:0] SDDQM[3:0] SDWE* SRAS* WDOG* WRITE* Min 0.019 0.019 0.019 0.078 0.078 0.019 0.019 0.039 0.019 0.039 0.019 0.019 0.019 0.019 0.019 0.039 0.019 0.039 0.039 0.039 0.039 0.019 0.039 Max 0.053 0.051 0.051 0.214 0.214 0.053 0.053 0.107 0.053 0.106 0.053 0.053 0.053 0.053 0.053 0.107 0.053 0.107 0.107 0.107 0.107 0.053 0.107 The values provided in this table are not tested, they are for information only. Caution: The hypothesis taken for this calculation is to only consider the 2 two dies which constitue ATF697FF product. ATF697FF [DATASHEET] 230 41000D−AERO03/14 17.7 AC parameters (reconfigurable unit) All the timings are given at the worst case corner. All input I/O characteristics measured from V IH of 50% of VCC at the pad (CMOS threshold) to the internal V IH of 50% of VCC. All output I/O characteristics are measured as the average of T PDLH and TPDHL to the pad VIH of 50% of VCC. Maximum times for clock input buffers and internal drivers are measured for rising edge delays only. Clocks and Reset Input buffers are measured from a V IH of 1.5V at the input pad to the internal V IH of 50% of VCC. All the values provided here after are simulation values. They are not measured on production environment. Table 17-9. Propagation Delay characteristics Cell Function Parameter Path Value Units Notes IO propagation delay propagation 1 propagation 3 propagation 5 delay from pad to q, no extra Input 3.3V tPD pad -> q 3.6 ns Input 3.3V tPD pad -> q 3.7 ns Input 3.3V tPD pad -> q 4.1 ns Input 3.3V tPD pad -> q 4.6 ns Output, 3.3V, slow tPD a -> pad 7.1 ns propagation delay from a to pad, 40 pF load Output, medium tPD a -> pad 6.2 ns propagation delay from a to pad, 40 pF load Output, 3.3V, fast tPD a -> pad 6.0 ns propagation delay from a to pad, 40 pF load Output, 3.3V, slow tPD oe -> pad 8.2 ns propagation delay from oe to pad, 40 pF load Output, medium tPD oe -> pad 7.4 ns propagation delay from oe to pad, 40 pF load tPD oe -> pad 7.1 ns propagation delay from oe to pad, 40 pF load 3.3V, 3.3V, Output, 3.3V, fast delay from pad to q, extra delay delay from pad to q, extra delay delay from pad to q, extra delay Table 17-10. Clock – Set/Reset AC characteristics Function Parameter Path Value Units Notes Global Clocks and Set/Reset GCK Input pad at 3.3V tPD pad -> clk 9.5 ns FCK Input pad at 3.3V tPD pad -> clk 8 ns Reset Input pad at 3.3V tPD pad -> sn | rn 10 ns delay from GCKx global clock pad to flop on the rising edge clock delay from FCKx fast clock pad to flop on the rising edge clock. Warning: Flops must be placed on first or last column of the matrix delay from any pad to the set/reset flop pin ATF697FF [DATASHEET] 231 41000D−AERO03/14 GCK input pad to output pad (3.3V, fast) tPD pad -> pad 22 ns FCK input pad to output pad (3.3V,fast) tPD pad -> pad 20 ns TM Table 17-11. FreeRam delay from GCKx global clock pad to an output pad loaded at 40pF Warning: flop is placed close to the output pad delay from FCKx fast clock pad to an output pad loaded at 40pF Warning: Flops must be placed on first or last column of the matrix AC characteristics – Asynchronous mode Async RAM Write TWEL, TWEH we 1.7 ns we min pulse width high or low Write TAWS we -> ain | a 4.2 ns setup time of address input before low transition at the we input Write TAWH we -> ain | a 1.7 ns hold time of address input before high transition at the we input Write TDS we -> din | d 0 ns setup time of data input before rising transition at the we input Write TDH we -> din | d 0 ns hold time of data input before rising transition at the we input Write /Read TDD din -> dout 6.4 ns propagation delay between din and dout on double port ram when ain = aout Read TAD ain -> dout 4.9 ns propagation delay from ain to dout Read TOZX oe -> dout 2.9 ns propagation delay from oe to dout for a transition from z to 0|1 Read TOXZ oe -> dout 2.9 ns propagation delay from oe to dout for a transition from 0|1 to z Figure 17-4. Single-port Write/Read ATF697FF [DATASHEET] 232 41000D−AERO03/14 Figure 17-5. Dual-port Write with Read Figure 17-6. Dual-port Read TM Table 17-12. FreeRam AC characteristics – Synchronous mode Sync RAM Write tCLKL, tCLKH clk 1.2 ns ck min pulse width high or low Write tWCS clk -> we 2.7 ns setup time of we input before active transition at the clk input Write tWCH clk -> we 0 ns hold time of we input before active transition at the clk input Write tACS clk -> ain | a 3.2 ns setup time of adress input before active transition at the clk input Write tACH clk -> ain | a 3.3 ns hold time of adress input before active transition at the clk input Write tDCS clk -> din | d 1.5 ns setup time of data input before active transition at the clk input Write tDCH clk -> din | d 0 ns hold time of data input before active transition at the clk input Write/Read tCD clk -> dout 5.8 ns propagation delay from clk to dout ATF697FF [DATASHEET] 233 41000D−AERO03/14 Sync RAM Read tAD aout -> dout 4.9 ns propagation delay from aout to dout Read tOZX oe -> dout 2.9 ns propagation delay from oe to dout for a transition from z to 0|1 Read tOXZ oe -> dout 2.9 ns propagation delay from oe to dout for a transition from 0|1 to z Figure 17-7. Single-port Write/Read ATF697FF [DATASHEET] 234 41000D−AERO03/14 Figure 17-8. Dual-port Write with Read Figure 17-9. Dual-port Read ATF697FF [DATASHEET] 235 41000D−AERO03/14 17.8 Timing diagram 17.8.1 Diagram List Reset Sequence Clock Input without PLL Clock Input with PLL Fetch, Read and Write from/to 32-bit PROM 0 wait-states Fetch, Read and Write from/to 32-bit PROM 2n wait-states Fetch, Read and Write from/to 32-bit PROM 2n wait-states + sync. BRDY* Fetch from 8-bit PROM with EDAC disabled 2n wait-states Word Write to 8-bit PROM with EDAC disabled 2n wait-states Byte and Half-Word Write to 8-bit PROM with EDAC disabled 2n wait-states Fetch from 8-bit PROM with EDAC enabled 2n wait-states Fetch, Read and Write from/to 32-bit SRAM 0 wait-states Fetch, Read and Write from/to 32-bit SRAM n wait-states Fetch, Read and Write from/to 32-bit SRAM with Instruction Burst 0 wait-states Fetch, Read and Write from/to 32-bit SRAM with Instruction Burst n wait-states Burst of SRAM Fetches with Instruction Cache and Burst enabled 0 wait-states Burst of SRAM Fetches with Instruction Cache and Burst enabled n wait-states SDRAM Read (or Fetch) with Precharge Burst Length = 1; CL = 3 SDRAM Write with Precharge Burst Length = 1; CL = 3 Fetch from ROM, Read and Write from/to 32-bit I/O 0 wait-states Fetch from ROM, Read and Write from/to 32-bit I/O n wait-states Fetch from ROM, Read and Write from/to 32-bit I/O n wait-states + sync. BRDY* The timing diagrams with fetch, read and/or write operations were generated using specific instruction sequences. Considering the complex nature of the interactions within the processor (IU pipeline, memory-controller, instruction cache...), the signals waveforms found in a final application may possibly exhibit slight functional cycle variations over the proposed timing diagrams. Source code for the timing diagrams is available on request. 17.8.2 Reset Figure 17-10. Reset Sequence ATF697FF [DATASHEET] 236 41000D−AERO03/14 17.8.3 Clock Figure 17-11. Clock Input without PLL Figure 17-12. Clock Input with PLL ATF697FF [DATASHEET] 237 41000D−AERO03/14 17.8.4 PROM Figure 17-13. Fetch, Read and Write from 32-bit PROM 0 wait-states Figure 17-14. Fetch, Read and Write from 32-bit PROM 2n wait-states ATF697FF [DATASHEET] 238 41000D−AERO03/14 Figure 17-15. Fetch, Read and Write from 32-bit PROM 2n wait-states + BRDY* ATF697FF [DATASHEET] 239 41000D−AERO03/14 Figure 17-16. Fetch from 8-bit PROM with EDAC disabled 2n wait-states Figure 17-17. Word Write to 8-bit PROM with EDAC disabled 2n wait-states ATF697FF [DATASHEET] 240 41000D−AERO03/14 Figure 17-18. Byte and Half-Word Write to 8-bit PROM with EDAC disabled 2n wait-states ATF697FF [DATASHEET] 241 41000D−AERO03/14 Figure 17-19. Fetch from 8-bit PROM with EDAC enabled 2n wait-states ATF697FF [DATASHEET] 242 41000D−AERO03/14 17.8.5 SRAM Figure 17-20. Fetch, Read and Write from/to 32-bit SRAM 0 wait-states ATF697FF [DATASHEET] 243 41000D−AERO03/14 Figure 17-21. Fetch, Read and Write from/to 32-bit SRAM n wait-states ATF697FF [DATASHEET] 244 41000D−AERO03/14 Figure 17-22. Fetch, Read and Write from/to 32-bit SRAM with Instruction Burst 0 wait-states ATF697FF [DATASHEET] 245 41000D−AERO03/14 Figure 17-23. Fetch, Read and Write from/to 32-bit SRAM with Instruction Burst n wait-states ATF697FF [DATASHEET] 246 41000D−AERO03/14 Figure 17-24. Burst of SRAM Fetches with Instruction Cache and Burst enabled 0 wait-states Figure 17-25. Burst of SRAM Fetches with Instruction Cache and Burst enabled n wait-states ATF697FF [DATASHEET] 247 41000D−AERO03/14 17.8.6 SDRAM Figure 17-26. SDRAM Read (or Fetch) with Precharge Burst length = 1; CL = 3 ATF697FF [DATASHEET] 248 41000D−AERO03/14 Figure 17-27. SDRAM Write with Precharge Burst length = 1; CL = 3 ATF697FF [DATASHEET] 249 41000D−AERO03/14 17.8.7 I/O Figure 17-28. Fetch from ROM, Read and Write from/to 32-bit I/O 0 wait-states ATF697FF [DATASHEET] 250 41000D−AERO03/14 Figure 17-29. Fetch from ROM, Read and Write from/to 32-bit I/O n wait-states ATF697FF [DATASHEET] 251 41000D−AERO03/14 Figure 17-30. Fetch from ROM, Read and Write from/to 32-bit I/O n wait-states + sync. BRDY* ATF697FF [DATASHEET] 252 41000D−AERO03/14 18. Ordering Information 18.1 ATF697FF ordering codes Atmel Ordering Code Supply Voltage (core /Ios) Temperature Range Packaging Quality flow ATF697FF-ZA-E ATF697FF-ZA-MQ ATF697FF-ZA-SV 1.8 V/3.3 V 1.8 V/3.3 V 1.8 V/3.3 V +25 °C -55 °C, +125 °C -55 °C, +125 °C MQFPT352 MQFPT352 MQFPT352 Engineering samples QMLQ QMLV 18.2 ATF697FF Evaluation Kit Ordering codes Atmel Code Ordering ATF697-EK 19. Packaging Description MQFPT352 Evaluation Kit for ATF697FF in MQFPT352 Revision History Doc. Rev. Date Comments A 04/2012 B 07/2013 C 11/2013 D 02/2014 Initial document release Change the reconfigurable unit documentation sections Add ordering code for evaluations kits. Add JTAG section Add characterization value for ATF697FF Correct radiation value Change JTAG default configuration process Change OTS to OTS* signal name Change T5 timing Remove dedicated power feature for LVDS Signal TDO in table17-8 Timing derating removed ATF697FF [DATASHEET] 253 41000D−AERO03/14 Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel: (+1)(408) 441-0311 Fax: (+1)(408) 487-2600 www.atmel.com Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel: (+852) 2245-6100 Fax: (+852) 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel: (+49) 89-31970-0 Fax: (+49) 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg. 1-6-4 Osaki, Shinagawaku Tokyo 141-0032 JAPAN Tel: (+81)3. 6417-0300 Fax: (+81)3. 6417-0370 © 2014 Atmel Corporation. All rights reserved. / Rev.: 41000D−AERO03/14 Atmel®, Atmel logo and combinations thereof, Enabling Unlimited Possibilities®, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.