PIC24FJXXXGA0XX PIC24FJXXXGA0XX Flash Programming Specification 1.0 DEVICE OVERVIEW This document defines the programming specification for the PIC24FJXXXGA0XX family of 16-bit microcontroller devices. This programming specification is required only for those developing programming support for the PIC24FJXXXGA0XX family. Customers using only one of these devices should use development tools that already provide support for device programming. The Enhanced In-Circuit Serial Programming (Enhanced ICSP) protocol uses a faster method that takes advantage of the programming executive, as illustrated in Figure 2-1. The programming executive provides all the necessary functionality to erase, program and verify the chip through a small command set. The command set allows the programmer to program the PIC24FJXXXGA0XX devices without having to deal with the low-level programming protocols of the chip. This specification includes programming specifications for the following devices: FIGURE 2-1: • PIC24FJ16GA002 • PIC24FJ96GA006 • PIC24FJ16GA004 • PIC24FJ96GA008 • PIC24FJ32GA002 • PIC24FJ96GA010 • PIC24FJ32GA004 • PIC24FJ128GA006 • PIC24FJ48GA002 • PIC24FJ128GA008 • PIC24FJ48GA004 • PIC24FJ128GA010 PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™ PIC24FJXXXGA0XX Programmer Programming Executive • PIC24FJ64GA002 On-Chip Memory • PIC24FJ64GA004 • PIC24FJ64GA006 • PIC24FJ64GA008 • PIC24FJ64GA010 2.0 PROGRAMMING OVERVIEW OF THE PIC24FJXXXGA0XX FAMILY This specification is divided into major sections that describe the programming methods independently. Section 4.0 “Device Programming – Enhanced ICSP” describes the Run-Time Self-Programming (RTSP) method. Section 3.0 “Device Programming – ICSP” describes the In-Circuit Serial Programming method. There are two methods of programming the PIC24FJXXXGA0XX family of devices discussed in this programming specification. They are: 2.1 • In-Circuit Serial Programming™ (ICSP™) • Enhanced In-Circuit Serial Programming (Enhanced ICSP) All devices in the PIC24FJXXXGA0XX family are dual voltage supply designs: one supply for the core and peripherals and another for the I/O pins. A regulator is provided on-chip to alleviate the need for two external voltage supplies. The ICSP programming method is the most direct method to program the device; however, it is also the slower of the two methods. It provides native, low-level programming capability to erase, program and verify the chip. © 2008 Microchip Technology Inc. Power Requirements All of the PIC24FJXXXGA0XX devices power their core digital logic at a nominal 2.5V. To simplify system design, all devices in the PIC24FJXXXGA0XX family incorporate an on-chip regulator that allows the device to run its core logic from VDD. DS39768D-page 1 PIC24FJXXXGA0XX The regulator provides power to the core from the other VDD pins. A low-ESR capacitor (such as tantalum) must be connected to the VDDCORE pin (Figure 2-2 and Figure 2-3). This helps to maintain the stability of the regulator. The specifications for core voltage and capacitance are listed in Section 7.0 “AC/DC Characteristics and Timing Requirements”. FIGURE 2-3: CONNECTIONS FOR THE ON-CHIP REGULATOR (28/44-PIN DEVICES) Regulator Enabled (DISVREG tied to VSS): 3.3V PIC24FJXXXGA0XX FIGURE 2-2: CONNECTIONS FOR THE ON-CHIP REGULATOR (64/80/100-PIN DEVICES) VDD DISVREG VDDCORE/VCAP Regulator Enabled (ENVREG tied to VDD): CEFC (10 μF typ) VSS 3.3V PIC24FJXXXGA0XX VDD Regulator Disabled (DISVREG tied to VDD): ENVREG 2.5V(1) VDDCORE/VCAP CEFC (10 μF typ) 3.3V(1) PIC24FJXXXGA0XX VDD VSS DISVREG VDDCORE/VCAP Regulator Disabled (ENVREG tied to ground): 2.5V(1) VSS 3.3V(1) PIC24FJXXXGA0XX VDD ENVREG VDDCORE/VCAP VSS Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJXXXGA0XX VDD DISVREG VDDCORE/VCAP Regulator Disabled (VDD tied to VDDCORE): VSS 2.5V(1) PIC24FJXXXGA0XX VDD ENVREG VDDCORE/VCAP Note 1: These are typical operating voltages. Refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for the full operating ranges of VDD and VDDCORE. VSS Note 1: These are typical operating voltages. Refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for the full operating ranges of VDD and VDDCORE. DS39768D-page 2 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 2.2 Program Memory Write/Erase Requirements 2.3 The pin diagrams for the PIC24FJXXXGA0XX family are shown in the following figures. The pins that are required for programming are listed in Table 2-1 and are shown in bold letters in the figures. Refer to the appropriate device data sheet for complete pin descriptions. The Flash program memory on the PIC24FJXXXGA0XX devices has a specific write/erase requirement that must be adhered to for proper device operation. The rule is that any given word in memory must not be written more than twice before erasing the page in which it is located. Thus, the easiest way to conform to this rule is to write all the data in a programming block within one write cycle. The programming methods specified in this specification comply with this requirement. Note: Pin Diagrams Writing to a location multiple times without erasing is not recommended. TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING) During Programming Pin Name MCLR Pin Name Pin Type MCLR P Pin Description Programming Enable ENVREG ENVREG I Enable for On-Chip Voltage Regulator DISVREG(1) DISVREG I Disable for On-Chip Voltage Regulator VDD and AVDD(2) VDD P Power Supply VSS and AVSS(2) VSS P Ground VDDCORE P Regulated Power Supply for Core PGC I Primary Programming Pin Pair: Serial Clock PGD1 PGD I/O Primary Programming Pin Pair: Serial Data PGC2 PGC I Secondary Programming Pin Pair: Serial Clock PGD2 PGD I/O Secondary Programming Pin Pair: Serial Data VDDCORE PGC1 Legend: I = Input, O = Output, P = Power Note 1: Applies to 28 and 44-pin devices only. 2: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground (AVSS). © 2008 Microchip Technology Inc. DS39768D-page 3 PIC24FJXXXGA0XX Pin Diagrams MCLR RA0 RA1 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 RB2 RB3 VSS RA2 RA3 RB4 RA4 VDD PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PIC24FJXXGA002 28-Pin PDIP, SSOP, SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS RB15 RB14 RB13 RB12 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 VCAP/VDDCORE DISVREG RB9 RB8 RB7 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6 RA1 RA0 MCLR VDD Vss RB15 RB14 28-Pin QFN(1) 28 27 26 25 24 23 22 1 21 2 20 3 19 4 PIC24FJXXGA002 18 5 17 6 16 7 15 8 9 10 11 12 13 14 RB13 RB12 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 VCAP/VDDCORE DISVREG RB9 RB4 RA4 VDD PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6 RB7 RB8 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 RB2 RB3 VSS RA2 RA3 Legend: Note 1: DS39768D-page 4 RPx represents remappable peripheral pins. The bottom pad of QFN packages should be connected to VSS. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6 PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 44-Pin QFN(1) PIC24FJXXGA004 33 32 31 30 29 28 27 26 25 24 23 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 RA10 RA7 RB14 RB15 AVSS AVDD MCLR RA0 RA1 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 RB9 RC6 RC7 RC8 RC9 DISVREG VCAP/VDDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 RB12 RB13 Legend: Note 1: RPx represents remappable peripheral pins. The bottom pad of QFN packages should be connected to VSS. © 2008 Microchip Technology Inc. DS39768D-page 5 PIC24FJXXXGA0XX Pin Diagrams (Continued) 44 43 42 41 40 39 38 37 36 35 34 RB8 RB7 PGC3/EMUC3/RP6/SCL1/CN24/PMD6/RB6 PGD3/EMUD3/RP5/SDA1/CN27/PMD7/RB5 VDD VSS RC5 RC4 RC3 RA9 RA4 44-Pin TQFP PIC24FJXXGA004 33 32 31 30 29 28 27 26 25 24 23 RB4 RA8 RA3 RA2 VSS VDD RC2 RC1 RC0 RB3 RB2 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 RA10 RA7 RB14 RB15 AVSS AVDD MCLR RA0 RA1 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 RB9 RC6 RC7 RC8 RC9 DISVREG VCAP/VDDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 RB12 RB13 Legend: DS39768D-page 6 RPx represents remappable peripheral pins. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Pin Diagrams (Continued) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RE4 RE3 RE2 RE1 RE0 RF1 RF0 ENVREG VCAP/VDDCORE RD7 RD6 RD5 RD4 RD3 RD2 RD1 64-Pin TQFP RE5 RE6 RE7 RG6 RG7 RG8 MCLR RG9 VSS VDD RB5 RB4 RB3 RB2 PGC1/EMUC1/VREF-/AN1/CN3/RB1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24FJXXGA006 PIC24FJXXXGA006 48 RC14 47 46 45 44 43 42 41 40 RC13 39 38 37 RC12 VDD RG2 36 35 34 33 RG3 RF6 RD0 RD11 RD10 RD9 RD8 Vss RC15 RF2 RF3 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 AVDD AVSS RB8 RB9 RB10 RB11 VSS VDD RB12 RB13 RB14 RB15 RF4 RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0 1 © 2008 Microchip Technology Inc. DS39768D-page 7 PIC24FJXXXGA0XX Pin Diagrams (Continued) 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 RE4 RE3 RE2 RE1 RE0 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE RD7 RD6 RD5 RD4 RD13 RD12 RD3 RD2 RD1 80-Pin TQFP RE5 RE6 RE7 RC1 RC3 RG6 RG7 RG8 MCLR RG9 VSS VDD RE8 RE9 RB5 RB4 RB3 RB2 PGC1/EMUC1/AN1/CN3/RB1 2 3 4 5 6 7 8 9 10 11 12 PIC24FJXXGA008 PIC24FJXXXGA008 13 14 15 16 17 18 19 20 RC14 RC13 RD0 RD11 RD10 RD9 RD8 RA15 RA14 VSS RC15 RC12 VDD RG2 RG3 RF6 RF7 RF8 RF2 RF3 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS RB8 RB9 PMA13/CVREF/AN10/RB10 RB11 VSS VDD RB12 RB13 RB14 RB15 RD14 RD15 RF4 RF5 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 PGD1/EMUD1/AN0/CN2/RB0 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 DS39768D-page 8 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX Pin Diagrams (Continued) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 RE4 RE3 RE2 RG13 RG12 RG14 RE1 RE0 RA7 RA6 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE RD7 RD6 RD5 RD4 RD13 RD12 RD3 RD2 RD1 100-Pin TQFP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC24FJXXGA010 PIC24FJXXXGA010 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS RC14 RC13 RD0 RD11 RD10 RD9 RD8 RF2 RA14 VSS RC15 RC12 VDD TDO TDI RA3 RA2 RG2 RG3 RF6 RF7 RF8 RF2 RF3 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 RA10 AVDD AVSS RB8 RB9 RB10 RB11 VSS VDD RA1 RF13 RF12 RB12 RB13 RB14 RB15 VSS VDD RD14 RD15 RF4 RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 RG15 VDD RE5 RE6 RE7 RC1 RC2 RC3 RC4 RG6 RG7 RG8 MCLR PRG9 VSS VDD RA0 RE8 RE9 RB5 RB4 RB3 RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0 © 2008 Microchip Technology Inc. DS39768D-page 9 PIC24FJXXXGA0XX 2.4 Memory Map The program memory map extends from 000000h to FFFFFEh. Code storage is located at the base of the memory map and supports up to 44K instruction words (about 128 Kbytes). Table 2-3 shows the program memory size and number of erase and program blocks present in each device variant. Each erase block, or page, contains 512 instructions, and each program block, or row, contains 64 instructions. Locations 800000h through 8007FEh are reserved for executive code memory. This region stores the programming executive and the debugging executive. The programming executive is used for device programming and the debugging executive is used for in-circuit debugging. This region of memory can not be used to store user code. The last two implemented program memory locations are reserved for the device Configuration registers. TABLE 2-2: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJXXXGA0XX DEVICES Device Figure 2-4 shows the memory map PIC24FJXXXGA0XX family variants. TABLE 2-3: Device for the CODE MEMORY SIZE User Memory Write Erase Address Limit Blocks Blocks (Instruction Words) PIC24FJ16GA 002BFEh (5.5K) 88 11 PIC24FJ32GA 0057FEh (11K) 176 22 PIC24FJ48GA 0083FEh (16.5K) 264 33 PIC24FJ64GA 00ABFEh (22K) 344 43 PIC24FJ96GA 00FFFEh (32K) 512 64 PIC24FJ128GA 0157FEh (44K) 688 86 Configuration Word Addresses 1 2 PIC24FJ16GA 002BFEh 002BFCh PIC24FJ32GA 0057FEh 0057FCh PIC24FJ48GA 0083FEh 0083FCh PIC24FJ64GA 00ABFEh 00ABFCh PIC24FJ96GA 00FFFEh 00FFFCh PIC24FJ128GAGA 0157FEh 0157FCh DS39768D-page 10 Locations, FF0000h and FF0002h, are reserved for the Device ID registers. These bits can be used by the programmer to identify what device type is being programmed. They are described in Section 6.1 “Device ID”. The Device ID registers read out normally, even after code protection is applied. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX FIGURE 2-4: PROGRAM MEMORY MAP 000000h User Flash Code Memory (44031 x 24-bit) User Memory Space Configuration Words (2 x 24-bit) 0157FAh(1) 0157FCh(1) 0157FEh(1) 015800h(1) Reserved 7FFFFEh 800000h Executive Code Memory (1024 x 24-bit) Diagnostic and Calibration Words (8 x 24-bit) 8007EEh 8007F0h Configuration Memory Space 800800h Reserved Device ID (2 x 16-bit) Reserved Note 1: FEFFFEh FF0000h FF0002h FF0004h FFFFFEh The address boundaries for user Flash code memory are device dependent (see Table 2-3). © 2008 Microchip Technology Inc. DS39768D-page 11 PIC24FJXXXGA0XX 3.0 DEVICE PROGRAMMING – ICSP FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW ICSP mode is a special programming protocol that allows you to read and write to PIC24FJXXXGA0XX device family memory. The ICSP mode is the most direct method used to program the device; note, however, that Enhanced ICSP is faster. ICSP mode also has the ability to read the contents of executive memory to determine if the programming executive is present. This capability is accomplished by applying control codes and instructions, serially to the device, using pins, PGCx and PGDx. Start Enter ICSP™ Perform Chip Erase In ICSP mode, the system clock is taken from the PGCx pin, regardless of the device’s oscillator Configuration bits. All instructions are shifted serially into an internal buffer, then loaded into the Instruction Register (IR) and executed. No program fetching occurs from internal memory. Instructions are fed in 24 bits at a time. PGDx is used to shift data in and PGCx is used as both the serial shift clock and the CPU execution clock. Note: Program Memory Verify Program Program Configuration Bits During ICSP operation, the operating frequency of PGCx must not exceed 10 MHz. Verify Configuration Bits Exit ICSP 3.1 Overview of the Programming Process Figure 3-1 shows the high-level overview of the programming process. After entering ICSP mode, the first action is to Chip Erase the device. Next, the code memory is programmed, followed by the device Configuration registers. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. Then, program the code-protect Configuration bits, if required. Done 3.2 ICSP Operation Upon entry into ICSP mode, the CPU is Idle. Execution of the CPU is governed by an internal state machine. A 4-bit control code is clocked in using PGCx and PGDx, and this control code is used to command the CPU (see Table 3-1). The SIX control code is used to send instructions to the CPU for execution, and the REGOUT control code is used to read data out of the device via the VISI register. TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE 4-Bit Mnemonic Control Code 0000b SIX Shift in 24-bit instruction and execute. 0001b REGOUT Shift out the VISI (0784h) register. 0010b-1111b N/A DS39768D-page 12 Description Reserved. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 3.2.1 SIX SERIAL INSTRUCTION EXECUTION Coming out of Reset, the first 4-bit control code is always forced to SIX and a forced NOP instruction is executed by the CPU. Five additional PGCx clocks are needed on start-up, resulting in a 9-bit SIX command instead of the normal 4-bit SIX command. The SIX control code allows execution of the PIC24FJXXXGA0XX family assembly instructions. When the SIX code is received, the CPU is suspended for 24 clock cycles, as the instruction is then clocked into the internal buffer. Once the instruction is shifted in, the state machine allows it to be executed over the next four PGC clock cycles. While the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see Figure 3-2). FIGURE 3-2: After the forced SIX is clocked in, ICSP operation resumes as normal. That is, the next 24 clock cycles load the first instruction word to the CPU. Note: To account for this forced NOP, all example code in this specification begin with a NOP to ensure that no data is lost. SIX SERIAL EXECUTION P1 1 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4 PGCx P4 P3 P4A P1A P1B P2 PGDx 0 0 0 0 Execute PC – 1, Fetch SIX Control Code 0 0 0 0 0 LSB X X X X X X X X X X 24-Bit Instruction Fetch Only for Program Memory Entry X X X X MSB 0 0 0 0 Execute 24-Bit Instruction, Fetch Next Control Code PGDx = Input 3.2.1.1 Differences Between Execution of SIX and Normal Instructions There are some differences between executing instructions normally and using the SIX ICSP command. As a result, the code examples in this specification may not match those for performing the same functions during normal device operation. The important differences are: • Two-word instructions require two SIX operations to clock in all the necessary data. Examples of two-word instructions are GOTO and CALL. • Two-cycle instructions require two SIX operations. The first SIX operation shifts in the instruction and begins to execute it. A second SIX operation – which should shift in a NOP to avoid losing data – provides the CPU clocks required to finish executing the instruction. Examples of two-cycle instructions are table read and table write instructions. • The CPU does not automatically stall to account for pipeline changes. A CPU stall occurs when an instruction modifies a register that is used for Indirect Addressing by the following instruction. © 2008 Microchip Technology Inc. During normal operation, the CPU automatically will force a NOP while the new data is read. When using ICSP, there is no automatic stall, so any indirect references to a recently modified register should be preceded by a NOP. For example, the instructions, mov #0x0,W0 and mov [W0],W1, must have a NOP inserted between them. If a two-cycle instruction modifies a register that is used indirectly, it will require two following NOPs: one to execute the second half of the instruction and a second to stall the CPU to correct the pipeline. Instructions such as tblwtl [W0++],[W1] should be followed by two NOPs. • The device Program Counter (PC) continues to automatically increment during ICSP instruction execution, even though the Flash memory is not being used. As a result, the PC may be incremented to point to invalid memory locations. Invalid memory spaces include unimplemented Flash addresses and the vector space (locations 0x0 to 0x1FF). If the PC points to these locations, the device will reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the PC to a safe space. The optimal method to accomplish this is to perform a GOTO 0x200. DS39768D-page 13 PIC24FJXXXGA0XX 3.2.2 REGOUT SERIAL INSTRUCTION EXECUTION Note 1: After the contents of VISI are shifted out, the PIC24FJXXXGA0XX device maintains PGDx as an output until the first rising edge of the next clock is received. The REGOUT control code allows for data to be extracted from the device in ICSP mode. It is used to clock the contents of the VISI register, out of the device, over the PGDx pin. After the REGOUT control code is received, the CPU is held Idle for 8 cycles. After these 8 cycles, an additional 16 cycles are required to clock the data out (see Figure 3-3). 2: Data changes on the falling edge and latches on the rising edge of PGCx. For all data transmissions, the Least Significant bit (LSb) is transmitted first. The REGOUT code is unique because the PGDx pin is an input when the control code is transmitted to the device. However, after the control code is processed, the PGDx pin becomes an output as the VISI register is shifted out. FIGURE 3-3: 1 REGOUT SERIAL EXECUTION 2 3 4 1 2 7 8 1 2 3 4 5 6 11 12 13 14 15 16 1 2 3 4 PGCx P4 PGDx 1 0 0 0 Execute Previous Instruction, CPU Held in Idle Fetch REGOUT Control Code PGDx = Input DS39768D-page 14 P4A P5 LSb 1 2 3 4 ... 10 11 12 13 14 MSb Shift Out VISI Register<15:0> PGDx = Output 0 0 0 0 No Execution Takes Place, Fetch Next Control Code PGDx = Input © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 3.3 Entering ICSP Mode The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0001’ (more easily remembered as 4D434851h in hexadecimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. As shown in Figure 3-4, entering ICSP Program/Verify mode requires three steps: 1. 2. 3. MCLR is briefly driven high, then low. A 32-bit key sequence is clocked into PGDx. MCLR is then driven high within a specified period of time and held. Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as Program/Verify mode is to be maintained. An interval of at least time, P19 and P7, must elapse before presenting data on PGDx. Signals appearing on PGCx before P7 has elapsed will not be interpreted as valid. The programming voltage applied to MCLR is VIH, which is essentially VDD in the case of PIC24FJXXXGA0XX devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGDx. FIGURE 3-4: On successful entry, the program memory can be accessed and programmed in serial fashion. While in ICSP mode, all unused I/Os are placed in the high-impedance state. ENTERING ICSP™ MODE P6 P19 P14 MCLR P7 VIH VIH VDD Program/Verify Entry Code = 4D434851h 0 b31 PGDx 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 1 b0 PGCx P18 © 2008 Microchip Technology Inc. P1A P1B DS39768D-page 15 PIC24FJXXXGA0XX 3.4 Flash Memory Programming in ICSP Mode 3.4.1 PROGRAMMING OPERATIONS Flash memory write and erase operations are controlled by the NVMCON register. Programming is performed by setting NVMCON to select the type of erase operation (Table 3-2) or write operation (Table 3-3) and initiating the programming by setting the WR control bit (NVMCON<15>). In ICSP mode, all programming operations are self-timed. There is an internal delay between the user setting the WR control bit and the automatic clearing of the WR control bit when the programming operation is complete. Please refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for information about the delays associated with various programming operations. TABLE 3-2: NVMCON ERASE OPERATIONS NVMCON Value Erase Operation 404Fh Erase all code memory, executive memory and Configuration registers (does not erase Unit ID or Device ID registers). 4042h Erase a page of code memory or executive memory. TABLE 3-3: NVMCON WRITE OPERATIONS NVMCON Value Write Operation 4003h Write a Configuration Word register. 4001h Program 1 row (64 instruction words) of code memory or executive memory. 3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE The WR bit (NVMCON<15>) is used to start an erase or write cycle. Setting the WR bit initiates the programming cycle. All erase and write cycles are self-timed. The WR bit should be polled to determine if the erase or write cycle has been completed. Starting a programming cycle is performed as follows: BSET 3.5 Erasing Program Memory The procedure for erasing program memory (all of code memory, data memory, executive memory and code-protect bits) consists of setting NVMCON to 404Fh and executing the programming cycle. A Chip Erase can erase all of user memory or all of both the user and configuration memory. A table write instruction should be executed prior to performing the Chip Erase to select which sections are erased. When this table write instruction is executed: • If the TBLPAG register points to user space (is less than 0x80), the Chip Erase will erase only user memory. • If TBLPAG points to configuration space (is greater than or equal to 0x80), the Chip Erase will erase both user and configuration memory. If configuration memory is erased, the internal oscillator Calibration Word, located at 0x807FE, will be erased. This location should be stored prior to performing a whole Chip Erase and restored afterward to prevent internal oscillators from becoming uncalibrated. Figure 3-5 shows the ICSP programming process for performing a Chip Erase. This process includes the ICSP command code, which must be transmitted (for each instruction), Least Significant bit first, using the PGCx and PGDx pins (see Figure 3-2). Note: Program memory must be erased before writing any data to program memory. FIGURE 3-5: CHIP ERASE FLOW Start Write 404Fh to NVMCON SFR Set the WR bit to Initiate Erase Delay P11 + P10 Time Done NVMCON, #WR DS39768D-page 16 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX TABLE 3-4: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Set the NVMCON to erase all program memory. 0000 0000 2404FA 883B0A MOV MOV #0x404F, W10 W10, NVMCON Step 3: Set TBLPAG and perform dummy table write to select what portions of memory are erased. 0000 0000 0000 0000 0000 0000 200000 880190 200000 BB0800 000000 000000 MOV MOV MOV TBLWTL NOP NOP #<PAGEVAL>, W0 W0, TBLPAG #0x0000, W0 W0,[W0] BSET NOP NOP NVMCON, #WR Step 4: Initiate the erase cycle. 0000 0000 0000 A8E761 000000 000000 Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 © 2008 Microchip Technology Inc. GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP DS39768D-page 17 PIC24FJXXXGA0XX 3.6 Writing Code Memory The procedure for writing code memory is the same as the procedure for writing the Configuration registers, except that 64 instruction words are programmed at a time. To facilitate this operation, working registers, W0:W5, are used as temporary holding registers for the data to be programmed. Table 3-5 shows the ICSP programming details, including the serial pattern with the ICSP command code which must be transmitted, Least Significant bit first, using the PGCx and PGDx pins (see Figure 3-2). In Step 1, the Reset vector is exited. In Step 2, the NVMCON register is initialized for programming a full row of code memory. In Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. (The upper byte of the starting destination address is stored in TBLPAG and the lower 16 bits of the destination address are stored in W7.) In Step 5, eight TBLWT instructions are used to copy the data from W0:W5 to the write latches of code memory. Since code memory is programmed 64 instruction words at a time, Steps 4 and 5 are repeated 16 times to load all the write latches (Step 6). After the write latches are loaded, programming is initiated by writing to the NVMCON register in Steps 7 and 8. In Step 9, the internal PC is reset to 200h. This is a precautionary measure to prevent the PC from incrementing into unimplemented memory when large devices are being programmed. Lastly, in Step 10, Steps 3-9 are repeated until all of code memory is programmed. FIGURE 3-6: PACKED INSTRUCTION WORDS IN W<0:5> 15 8 7 W0 LSW0 To minimize the programming time, A packed instruction format is used (Figure 3-6). W1 W2 LSW1 In Step 4, four packed instruction words are stored in working registers, W0:W5, using the MOV instruction, and the Read Pointer, W6, is initialized. The contents of W0:W5 (holding the packed instruction word data) are shown in Figure 3-6. W3 LSW2 TABLE 3-5: Command (Binary) W4 0 MSB1 MSB0 MSB3 W5 MSB2 LSW3 SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Set the NVMCON to program 64 instruction words. 0000 0000 24001A 883B0A MOV MOV #0x4001, W10 W10, NVMCON Step 3: Initialize the Write Pointer (W7) for TBLWT instruction. 0000 0000 0000 200xx0 880190 2xxxx7 MOV MOV MOV #<DestinationAddress23:16>, W0 W0, TBLPAG #<DestinationAddress15:0>, W7 Step 4: Load W0:W5 with the next 4 instruction words to program. 0000 0000 0000 0000 0000 0000 DS39768D-page 18 2xxxx0 2xxxx1 2xxxx2 2xxxx3 2xxxx4 2xxxx5 MOV MOV MOV MOV MOV MOV #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX TABLE 3-5: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED) Data (Hex) Description Step 5: Set the Read Pointer (W6) and load the (next set of) write latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0300 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 CLR W6 NOP TBLWTL [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTL [W6++], NOP NOP TBLWTL [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTL [W6++], NOP NOP [W7] [W7++] [++W7] [W7++] [W7] [W7++] [++W7] [W7++] Step 6: Repeat Steps 4 and 5, sixteen times, to load the write latches for 64 instructions. Step 7: Initiate the write cycle. 0000 0000 0000 A8E761 000000 000000 BSET NOP NOP NVMCON, #WR Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP Step 9: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 10: Repeat Steps 3-9 until all code memory is programmed. © 2008 Microchip Technology Inc. DS39768D-page 19 PIC24FJXXXGA0XX FIGURE 3-7: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at <Addr> N=N+1 No All bytes written? Yes N=1 LoopCount = LoopCount + 1 Start Write Sequence and Poll for WR bit to be Cleared No All locations done? Yes Done DS39768D-page 20 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 3.7 Writing Configuration Words The PIC24FJXXXGA0XX family configuration is stored in Flash Configuration Words at the end of the user space program memory and in multiple register Configuration Words located in the test space. These registers reflect values read at any Reset from program memory locations. The values can be changed only by programming the content of the corresponding Flash Configuration Word and resetting the device. The Reset forces an automatic reload of the Flash stored configuration values by sequencing through the dedicated Flash Configuration Words and transferring the data into the Configuration registers. To change the values of the Flash Configuration Word once it has been programmed, the device must be Chip Erased, as described in Section 3.5 “Erasing Program Memory”, and reprogrammed to the desired value. It is not possible to program a ‘0’ to ‘1’, but they may be programmed from a ‘1’ to ‘0’ to enable code protection. Table 3-7 shows the ICSP programming details for programming the Configuration Word locations, including the serial pattern with the ICSP command code which must be transmitted, Least Significant bit first, using the PGCx and PGDx pins (see Figure 3-2). © 2008 Microchip Technology Inc. In Step 1, the Reset vector is exited. In Step 2, the NVMCON register is initialized for programming of code memory. In Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. The TBLPAG register must be loaded with the following: • 96 and 64 Kbyte devices – 00h • 128 Kbyte devices – 01h To verify the data by reading the Configuration Words after performing the write in order, the code protection bits initially should be programmed to a ‘1’ to ensure that the verification can be performed properly. After verification is finished, the code protection bit can be programmed to a ‘0’ by using a word write to the appropriate Configuration Word. TABLE 3-6: Address DEFAULT CONFIGURATION REGISTER VALUES Name Default Value Last Word CW1 7FFFh(1) Last Word – 2 CW2 FFFFh Note 1: CW1<15> is reserved and must be programmed to ‘0’. DS39768D-page 21 PIC24FJXXXGA0XX TABLE 3-7: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction. 0000 2xxxx7 MOV <CW2Address15:0>, W7 Step 3: Set the NVMCON register to program CW2. 0000 0000 24003A 883B0A MOV MOV #0x4003, W10 W10, NVMCON Step 4: Initialize the TBLPAG register. 0000 0000 200xx0 880190 MOV MOV <CW2Address23:16>, W0 W0, TBLPAG Step 5: Load the Configuration register data to W6. 0000 2xxxx6 MOV #<CW2_VALUE>, W6 Step 6: Write the Configuration register data to the write latch and increment the Write Pointer. 0000 0000 0000 0000 000000 BB1B86 000000 000000 NOP TBLWTL NOP NOP W6, [W7++] Step 7: Initiate the write cycle. 0000 0000 0000 A8E761 000000 000000 BSET NOP NOP NVMCON, #WR Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP Step 9: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 10: Repeat Steps 5-9 to write CW1. DS39768D-page 22 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 3.8 Reading Code Memory Reading from code memory is performed by executing a series of TBLRD instructions and clocking out the data using the REGOUT command. Table 3-8 shows the ICSP programming details for reading code memory. In Step 1, the Reset vector is exited. In Step 2, the 24-bit starting source address for reading is loaded into the TBLPAG register and W6 register. The upper byte of the starting source address is stored in TBLPAG and the lower 16 bits of the source address are stored in W6. TABLE 3-8: Command (Binary) To minimize the reading time, the packed instruction word format that was utilized for writing is also used for reading (see Figure 3-6). In Step 3, the Write Pointer, W7, is initialized. In Step 4, two instruction words are read from code memory and clocked out of the device, through the VISI register, using the REGOUT command. Step 4 is repeated until the desired amount of code memory is read. SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. 0000 0000 0000 200xx0 880190 2xxxx6 MOV MOV MOV #<SourceAddress23:16>, W0 W0, TBLPAG #<SourceAddress15:0>, W6 Step 3: Initialize the Write Pointer (W7) to point to the VISI register. 0000 0000 207847 000000 MOV NOP #VISI, W7 Step 4: Read and clock out the contents of the next two locations of code memory, through the VISI register, using the REGOUT command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 BA0B96 000000 000000 <VISI> 000000 BADBB6 000000 000000 BAD3D6 000000 000000 <VISI> 000000 BA0BB6 000000 000000 <VISI> 000000 TBLRDL [W6], [W7] NOP NOP Clock out contents of VISI register NOP TBLRDH.B [W6++], [W7++] NOP NOP TBLRDH.B [++W6], [W7--] NOP NOP Clock out contents of VISI register NOP TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register NOP Step 5: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 6: Repeat Steps 4 and 5 until all desired code memory is read. © 2008 Microchip Technology Inc. DS39768D-page 23 PIC24FJXXXGA0XX 3.9 Reading Configuration Words The procedure for reading configuration memory is similar to the procedure for reading code memory, except that 16-bit data words are read (with the upper byte read being all ‘0’s) instead of 24-bit words. Since there are two Configuration registers, they are read one register at a time. TABLE 3-9: Command (Binary) Table 3-9 shows the ICSP programming details for reading the Configuration Words. Note that the TBLPAG register must be loaded with 00h for 96 Kbyte and below devices and 01h for 128 Kbyte devices (the upper byte address of configuration memory), and the Read Pointer, W6, is initialized to the lower 16 bits of the Configuration Word location. SERIAL INSTRUCTION EXECUTION FOR READING ALL CONFIGURATION MEMORY Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG, the Read Pointer (W6) and the Write Pointer (W7) for TBLRD instruction. 0000 0000 0000 0000 0000 200xx0 880190 2xxxx7 207847 000000 MOV MOV MOV MOV NOP <CW2Address23:16>, W0 W0, TBLPAG <CW2Address15:0>, W6 #VISI, W7 Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the VISI register using the REGOUT command. 0000 0000 0000 0001 0000 BA0BB6 000000 000000 <VISI> 000000 TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register NOP Step 4: Repeat Step 3 again to read Configuration Word 1. Step 5: Reset device internal PC. 0000 0000 DS39768D-page 24 040200 000000 GOTO NOP 0x200 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 3.10 Verify Code Memory and Configuration Word The verify step involves reading back the code memory space and comparing it against the copy held in the programmer’s buffer. The Configuration registers are verified with the rest of the code. The verify process is shown in the flowchart in Figure 3-8. Memory reads occur a single byte at a time, so two bytes must be read to compare against the word in the programmer’s buffer. Refer to Section 3.8 “Reading Code Memory” for implementation details of reading code memory. Note: Because the Configuration registers include the device code protection bit, code memory should be verified immediately after writing if code protection is enabled. This is because the device will not be readable or verifiable if a device Reset occurs after the code-protect bit in CW1 has been cleared. FIGURE 3-8: VERIFY CODE MEMORY FLOW 3.11 Reading the Application ID Word The Application ID Word is stored at address 8005BEh in executive code memory. To read this memory location, you must use the SIX control code to move this program memory location to the VISI register. Then, the REGOUT control code must be used to clock the contents of the VISI register out of the device. The corresponding control and instruction codes that must be serially transmitted to the device to perform this operation are shown in Table 3-10. After the programmer has clocked out the Application ID Word, it must be inspected. If the Application ID has the value, BBh, the programming executive is resident in memory and the device can be programmed using the mechanism described in Section 4.0 “Device Programming – Enhanced ICSP”. However, if the Application ID has any other value, the programming executive is not resident in memory; it must be loaded to memory before the device can be programmed. The procedure for loading the programming executive to memory is described in Section 5.4 “Programming the Programming Executive to Memory”. 3.12 Exiting ICSP Mode Exiting Program/Verify mode is done by removing VIH from MCLR, as shown in Figure 3-9. The only requirement for exit is that an interval, P16, should elapse between the last clock and program signals on PGCx and PGDx before removing VIH. Start Set TBLPTR = 0 FIGURE 3-9: EXITING ICSP™ MODE P16 Read Low Byte with Post-Increment P17 VIH MCLR Read High Byte with Post-Increment VDD VIH PGDx Does Word = Expect Data? Yes No No Failure, Report Error PGCx PGD = Input All code memory verified? Yes Done © 2008 Microchip Technology Inc. DS39768D-page 25 PIC24FJXXXGA0XX TABLE 3-10: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W0) for TBLRD instruction. 0000 0000 0000 0000 0000 0000 0000 0000 200800 880190 205BE0 207841 000000 BA0890 000000 000000 MOV MOV MOV MOV NOP TBLRDL NOP NOP #0x80, W0 W0, TBLPAG #0x5BE, W0 #VISI, W1 [W0], [W1] Step 3: Output the VISI register using the REGOUT command. 0001 0000 DS39768D-page 26 <VISI> 000000 Clock out contents of the VISI register NOP © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 4.0 DEVICE PROGRAMMING – ENHANCED ICSP This section discusses programming the device through Enhanced ICSP and the programming executive. The programming executive resides in executive memory (separate from code memory) and is executed when Enhanced ICSP Programming mode is entered. The programming executive provides the mechanism for the programmer (host device) to program and verify the PIC24FJXXXGA0XX devices using a simple command set and communication protocol. There are several basic functions provided by the programming executive: • • • • • After the programming executive has been verified in memory (or loaded if not present), the PIC24FJXXXGA0XX family can be programmed using the command set shown in Table 4-1. FIGURE 4-1: Start Enter Enhanced ICSP™ Perform Chip Erase Read Memory Erase Memory Program Memory Blank Check Read Executive Firmware Revision Program Memory The programming executive performs the low-level tasks required for erasing, programming and verifying a device. This allows the programmer to program the device by issuing the appropriate commands and data. Table 4-1 summarizes the commands. A detailed description for each command is provided in Section 5.2 “Programming Executive Commands”. TABLE 4-1: COMMAND SET SUMMARY Command Description SCHECK Verify Program Program Configuration Bits Verify Configuration Bits Exit Enhanced ICSP Sanity Check READC Read Device ID Registers READP Read Code Memory PROGP Program One Row of Code Memory and Verify PROGW Program One Word of Code Memory and Verify QBLANK Query if the Code Memory is Blank QVER Query the Software Version The programming executive uses the device’s data RAM for variable storage and program execution. After the programming executive has run, no assumptions should be made about the contents of data RAM. 4.1 HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW Overview of the Programming Process Figure 4-1 shows the high-level overview of the programming process. After entering Enhanced ICSP mode, the programming executive is verified. Next, the device is erased. Then, the code memory is programmed, followed by the configuration locations. Code memory (including the Configuration registers) is then verified to ensure that programming was successful. © 2008 Microchip Technology Inc. Done 4.2 Confirming the Presence of the Programming Executive Before programming can begin, the programmer must confirm that the programming executive is stored in executive memory. The procedure for this task is shown in Figure 4-2. First, In-Circuit Serial Programming mode (ICSP) is entered. Then, the unique Application ID Word stored in executive memory is read. If the programming executive is resident, the Application ID Word is BBh, which means programming can resume as normal. However, if the Application ID Word is not BBh, the programming executive must be programmed to executive code memory using the method described in Section 5.4 “Programming the Programming Executive to Memory”. Section 3.0 “Device Programming – ICSP” describes the ICSP programming method. Section 3.11 “Reading the Application ID Word” describes the procedure for reading the Application ID Word in ICSP mode. DS39768D-page 27 PIC24FJXXXGA0XX FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE 4.3 Entering Enhanced ICSP Mode As shown in Figure 4-3, entering Enhanced ICSP Program/Verify mode requires three steps: 1. 2. 3. Start Enter ICSP™ Mode The MCLR pin is briefly driven high, then low. A 32-bit key sequence is clocked into PGDx. MCLR is then driven high within a specified period of time and held. The programming voltage applied to MCLR is VIH, which is essentially VDD in the case of PIC24FJXXXGA0XX devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGDx. Read the Application ID from Address 807F0h Is Application ID BBh? The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as 4D434850h in hexadecimal format). The device will enter Program/Verify mode only if the key sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. No Yes Prog. Executive is Resident in Memory Prog. Executive must be Programmed Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as Program/Verify mode is to be maintained. An interval of at least time P19 and P7 must elapse before presenting data on PGDx. Signals appearing on PGDx before P7 has elapsed will not be interpreted as valid. Finish On successful entry, the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state. FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE P6 P14 MCLR P19 P7 VIH VIH VDD Program/Verify Entry Code = 4D434850h PGDx 0 b31 1 b30 0 b29 0 b28 1 ... b27 0 b3 0 b2 0 b1 0 b0 PGCx P18 DS39768D-page 28 P1A P1B © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 4.4 Blank Check FIGURE 4-4: FLOWCHART FOR PROGRAMMING CODE MEMORY The term “Blank Check” implies verifying that the device has been successfully erased and has no programmed memory locations. A blank or erased memory location is always read as ‘1’. Start The Device ID registers (FF0002h:FF0000h) can be ignored by the Blank Check since this region stores device information that cannot be erased. The device Configuration registers are also ignored by the Blank Check. Additionally, all unimplemented memory space should be ignored by the Blank Check. BaseAddress = 00h RemainingCmds = 688 Send PROGP Command to Program BaseAddress The QBLANK command is used for the Blank Check. It determines if the code memory is erased by testing these memory regions. A ‘BLANK’ or ‘NOT BLANK’ response is returned. If it is determined that the device is not blank, it must be erased before attempting to program the chip. 4.5 4.5.1 Is PROGP response PASS? Code Memory Programming Yes PROGRAMMING METHODOLOGY Code memory is programmed with the PROGP command. PROGP programs one row of code memory starting from the memory address specified in the command. The number of PROGP commands required to program a device depends on the number of write blocks that must be programmed in the device. A flowchart for programming code memory is shown in Figure 4-4. In this example, all 44K instruction words of a PIC24FJ128GA device are programmed. First, the number of commands to send (called ‘RemainingCmds’ in the flowchart) is set to 688 and the destination address (called ‘BaseAddress’) is set to ‘0’. Next, one write block in the device is programmed with a PROGP command. Each PROGP command contains data for one row of code memory of the PIC24FJXXXGA0XX device. After the first command is processed successfully, ‘RemainingCmds’ is decremented by 1 and compared with 0. Since there are more PROGP commands to send, ‘BaseAddress’ is incremented by 80h to point to the next row of memory. No RemainingCmds = RemainingCmds – 1 BaseAddress = BaseAddress + 80h No Are RemainingCmds ‘0’? Yes Finish Failure Report Error On the second PROGP command, the second row is programmed. This process is repeated until the entire device is programmed. No special handling must be performed when a panel boundary is crossed. © 2008 Microchip Technology Inc. DS39768D-page 29 PIC24FJXXXGA0XX 4.5.2 PROGRAMMING VERIFICATION After code memory is programmed, the contents of memory can be verified to ensure that programming was successful. Verification requires code memory to be read back and compared against the copy held in the programmer’s buffer. The READP command can be used to read back all of the programmed code memory. Alternatively, you can have the programmer perform the verification after the entire device is programmed using a checksum computation. 4.6 4.6.1 Configuration Bits Programming OVERVIEW The PIC24FJXXXGA0XX family has Configuration bits stored in the last two locations of implemented program memory (see Table 2-2 for locations). These bits can be set or cleared to select various device configurations. There are three types of Configuration bits: system operation bits, code-protect bits and unit ID bits. The system operation bits determine the power-on settings for system level components, such as oscillator and Watchdog Timer. The code-protect bits prevent program memory from being read and written. The register descriptions for the CW1 and CW2 Configuration registers are shown in Table 4-2. TABLE 4-2: PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION Bit Field Register (1) CW2<2> I2C1 Pin Mapping bit 1 = Default location for SCL1/SDA1 pins 0 = Alternate location for SCL1/SDA1 pins DEBUG CW1<11> Background Debug Enable bit 1 = Device will reset in User mode 0 = Device will reset in Debug mode FCKSM1:FCKSM0 CW2<7:6> Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled FNOSC2:FNOSC0 CW2<10:8> Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRCDIV) oscillator with postscaler 110 = Reserved 101 = Low-Power RC (LPRC) oscillator 100 = Secondary (SOSC) oscillator 011 = Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRCPLL) oscillator with postscaler and PLL 000 = Fast RC (FRC) oscillator I2C1SEL Description FWDTEN CW1<7> Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled; clearing the SWDTEN bit in the RCON register will have no effect) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) GCP CW1<13> General Segment Code-Protect bit 1 = User program memory is not code-protected 0 = User program memory is code-protected GWRP CW1<12> General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected ICS CW1<8> ICD Communication Channel Select bit 1 = Communicate on PGC2/EMUC2 and PGD2/EMUD2 0 = Communicate on PGC1/EMUC1 and PGD1/EMUD1 Note 1: 2: Available on 28 and 44-pin packages only. Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher. DS39768D-page 30 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX TABLE 4-2: Bit Field (1) PIC24FJXXXGA0XX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register Description ICS CW1<8> ICD Pin Placement Select bit 11 = ICD EMUC/EMUD pins are shared with PGC1/PGD1 10 = ICD EMUC/EMUD pins are shared with PGC2/PGD2 01 = ICD EMUC/EMUD pins are shared with PGC3/PGD3 00 = Reserved; do not use IESO CW2<15> Internal External Switchover bit 1 = Two-Speed Start-up enabled 0 = Two-Speed Start-up disabled IOL1WAY(1) CW2<4> IOLOCK Bit One-Way Set Enable bit 0 = The OSCCON<IOLOCK> bit can be set and cleared as needed (provided an unlocking sequence is executed) 1 = The OSCCON<IOLOCK> bit can only be set once (provided an unlocking sequence is executed). Once IOLOCK is set, this prevents any possible future RP register changes JTAGEN CW1<14> JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled OSCIOFNC CW2<5> OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin SOSCSEL1: SOSCSEL0(2) CW2<12:11> Secondary Oscillator Power Mode Select bits 11 = Default (high drive strength) mode 01 = Low-Power (low drive strength) mode x0 = Reserved; do not use POSCMD1: POSCMD0 CW2<1:0> Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode WDTPOST3: WDTPOST0 CW1<3:0> Watchdog Timer Prescaler bit 1111 = 1:32,768 1110 = 1:16,384 . . . 0001 = 1:2 0000 = 1:1 WDTPRE CW1<4> Watchdog Timer Postscaler bit 1 = 1:128 0 = 1:32 WINDIS CW1<6> Windowed WDT bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode; FWDTEN must be ‘1’ CW2<14:13> Voltage Regulator Standby Mode Wake-up Time Select bits 11 = Default regulator wake time used 01 = Fast regulator wake time used x0 = Reserved; do not use WUTSEL1: WUTSEL0(2) Note 1: 2: Available on 28 and 44-pin packages only. Available only on 28 and 44-pin devices with a silicon revision of 3042h or higher. © 2008 Microchip Technology Inc. DS39768D-page 31 PIC24FJXXXGA0XX 4.6.2 PROGRAMMING METHODOLOGY 4.6.4 CODE-PROTECT CONFIGURATION BITS Configuration bits may be programmed a single byte at a time using the PROGW command. This command specifies the configuration data and Configuration register address. When Configuration bits are programmed, any unimplemented or reserved bits must be programmed with a ‘1’. CW1 Configuration register controls code protection for the PIC24FJXXXGA0XX family. Two forms of code protection are provided. One form prevents code memory from being written (write protection) and the other prevents code memory from being read (read protection). Two PROGW commands are required to program the Configuration bits. A flowchart for Configuration bit programming is shown in Figure 4-5. GWRP (CW1<12>) controls write protection and GCP (CW1<13>) controls read protection. Protection is enabled when the respective bit is ‘0’. Note: 4.6.3 If the General Segment Code-Protect bit (GCP) is programmed to ‘0’, code memory is code-protected and can not be read. Code memory must be verified before enabling read protection. See Section 4.6.4 “Code-Protect Configuration Bits” for more information about code-protect Configuration bits. PROGRAMMING VERIFICATION After the Configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful. Verification requires the Configuration bits to be read back and compared against the copy held in the programmer’s buffer. The READP command reads back the programmed Configuration bits and verifies that the programming was successful. DS39768D-page 32 Erasing sets GWRP and GCP to ‘1’, which allows the device to be programmed. When write protection is enabled (GWRP = 0), any programming operation to code memory will fail. When read protection is enabled (GCP = 0), any read from code memory will cause a 0h to be read, regardless of the actual contents of code memory. Since the programming executive always verifies what it programs, attempting to program code memory with read protection enabled also will result in failure. It is imperative that both GWRP and GCP are ‘1’ while the device is being programmed and verified. Only after the device is programmed and verified should either GWRP or GCP be programmed to ‘0’ (see Section 4.6 “Configuration Bits Programming”). Note: Bulk Erasing in ICSP mode is the only way to reprogram code-protect bits from an ON state (‘0’) to an Off state (‘1’). © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX FIGURE 4-5: CONFIGURATION BIT PROGRAMMING FLOW Start ConfigAddress = 0157FCh(1) Send PROGW Command Is PROGW response PASS? No Yes ConfigAddress = ConfigAddress + 2 No Is ConfigAddress 0157FEh?(1) Yes Failure Report Error Finish Note 1: 4.7 Configuration Word addresses for PIC24FJ128GA devices are shown. Refer to Table 2-2 for others. Exiting Enhanced ICSP Mode Exiting Program/Verify mode is done by removing VIH from MCLR, as shown in Figure 4-6. The only requirement for exit is that an interval, P16, should elapse between the last clock and program signals on PGCx and PGDx before removing VIH. FIGURE 4-6: EXITING ENHANCED ICSP™ MODE P16 P17 VIH MCLR VDD VIH PGDx PGCx PGDx = Input © 2008 Microchip Technology Inc. DS39768D-page 33 PIC24FJXXXGA0XX 5.0 THE PROGRAMMING EXECUTIVE 5.1 Programming Executive Communication FIGURE 5-2: P1 1 The programmer and programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave. PGCx All communication is initiated by the programmer in the form of a command. Only one command at a time can be sent to the programming executive. In turn, the programming executive only sends one response to the programmer after receiving and processing a command. The programming executive command set is described in Section 5.2 “Programming Executive Commands”. The response set is described in Section 5.3 “Programming Executive Responses”. PGDx 5.1.1 COMMUNICATION INTERFACE AND PROTOCOL The Enhanced ICSP interface is a 2-wire SPI, implemented using the PGCx and PGDx pins. The PGCx pin is used as a clock input pin and the clock source must be provided by the programmer. The PGDx pin is used for sending command data to, and receiving response data from, the programming executive. Data transmits to the device must change on the rising edge and hold on the falling edge. Data receives from the device must change on the falling edge and hold on the rising edge. All data transmissions are sent to the Most Significant bit (MSb) first, using 16-bit mode (see Figure 5-1). FIGURE 5-1: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA RECEIVED FROM DEVICE P1 1 2 3 4 5 6 11 12 13 14 15 16 PGCx P1A P3 P1B P2 PGDx MSb 14 13 12 11 ... 5 4 3 PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE 2 1 LSb 2 3 4 5 6 11 12 13 14 P1A 15 16 P3 P1B P2 MSb 14 13 12 11 ... 5 4 3 2 1 LSb Since a 2-wire SPI is used, and data transmissions are half duplex, a simple protocol is used to control the direction of PGDx. When the programmer completes a command transmission, it releases the PGDx line and allows the programming executive to drive this line high. The programming executive keeps the PGDx line high to indicate that it is processing the command. After the programming executive has processed the command, it brings PGDx low for 15 μsec to indicate to the programmer that the response is available to be clocked out. The programmer can begin to clock out the response 23 μsec after PGDx is brought low, and it must provide the necessary amount of clock pulses to receive the entire response from the programming executive. After the entire response is clocked out, the programmer should terminate the clock on PGCx until it is time to send another command to the programming executive. This protocol is shown in Figure 5-3. 5.1.2 SPI RATE In Enhanced ICSP mode, the PIC24FJXXXGA0XX family devices operate from the internal Fast RC oscillator (FRCDIV), which has a nominal frequency of 8 MHz. This oscillator frequency yields an effective system clock frequency of 4 MHz. To ensure that the programmer does not clock too fast, it is recommended that a 4 MHz clock be provided by the programmer. 5.1.3 TIME-OUTS The programming executive uses no Watchdog Timer or time-out for transmitting responses to the programmer. If the programmer does not follow the flow control mechanism using PGCx, as described in Section 5.1.1 “Communication Interface and Protocol”, it is possible that the programming executive will behave unexpectedly while trying to send a response to the programmer. Since the programming executive has no time-out, it is imperative that the programmer correctly follow the described communication protocol. As a safety measure, the programmer should use the command time-outs identified in Table 5-1. If the command time-out expires, the programmer should reset the programming executive and start programming the device again. DS39768D-page 34 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX FIGURE 5-3: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL Host Transmits Last Command Word 1 2 Programming Executive Processes Command Host Clocks Out Response 1 15 16 2 15 16 1 2 15 16 PGCx PGDx MSB X X X LSB 1 P8 P20 The programming executive command set is shown in Table 5-1. This table contains the opcode, mnemonic, length, time-out and description for each command. Functional details on each command are provided in Section 5.2.4 “Command Descriptions”. 5.2.1 All programming executive commands have a general format consisting of a 16-bit header and any required data for the command (see Figure 5-4). The 16-bit header consists of a 4-bit opcode field, which is used to identify the command, followed by a 12-bit command length field. 15 12 When 24-bit instruction words are transferred across the 16-bit SPI interface, they are packed to conserve space using the format shown in Figure 5-5. This format minimizes traffic over the SPI and provides the programming executive with data that is properly aligned for performing table write operations. 15 PACKED INSTRUCTION WORD FORMAT 8 7 0 LSW1 MSB2 MSB1 LSW2 LSWx: Least Significant 16 bits of instruction word MSBx: Most Significant Bytes of instruction word COMMAND FORMAT 11 PACKED DATA FORMAT FIGURE 5-5: COMMAND FORMAT FIGURE 5-4: PGCx = Input PGDx = Output 5.2.2 Programming Executive Commands MSB X X X LSB P21 PGCx = Input (Idle) PGDx = Output PGCx = Input PGDx = Input 5.2 MSB X X X LSB 0 P9 0 Opcode Length Note: Command Data First Word (if required) • • Command Data Last Word (if required) The command opcode must match one of those in the command set. Any command that is received which does not match the list in Table 5-1 will return a “NACK” response (see Section 5.3.1.1 “Opcode Field”). The command length is represented in 16-bit words since the SPI operates in 16-bit mode. The programming executive uses the command length field to determine the number of words to read from the SPI port. If the value of this field is incorrect, the command will not be properly received by the programming executive. © 2008 Microchip Technology Inc. 5.2.3 When the number of instruction words transferred is odd, MSB2 is zero and LSW2 can not be transmitted. PROGRAMMING EXECUTIVE ERROR HANDLING The programming executive will “NACK” all unsupported commands. Additionally, due to the memory constraints of the programming executive, no checking is performed on the data contained in the programmer command. It is the responsibility of the programmer to command the programming executive with valid command arguments or the programming operation may fail. Additional information on error handling is provided in Section 5.3.1.3 “QE_Code Field”. DS39768D-page 35 PIC24FJXXXGA0XX TABLE 5-1: Opcode PROGRAMMING EXECUTIVE COMMAND SET Mnemonic Length (16-bit words) Time-out 1 ms Sanity check. Read an 8-bit word from the specified Device ID register. Description 0h SCHECK 1 1h READC 3 1 ms 2h READP 4 1 ms/row 3h RESERVED N/A N/A This command is reserved. It will return a NACK. 4h PROGC 4 5 ms Write an 8-bit word to the specified Device ID registers. 5h PROGP 99 5 ms Program one row of code memory at the specified address, then verify.(1) 7h RESERVED N/A N/A This command is reserved. It will return a NACK. 8h RESERVED N/A N/A This command is reserved. It will return a NACK. 9h RESERVED N/A N/A This command is reserved. It will return a NACK. Ah QBLANK 3 TBD Query if the code memory is blank. Read N 24-bit instruction words of code memory starting from the specified address. Bh QVER 1 1 ms Query the programming executive software version. Dh PROGW 4 5 ms Program one instruction word of code memory at the specified address, then verify. Legend: TBD = To Be Determined Note 1: One row of code memory consists of (64) 24-bit words. Refer to Table 2-3 for device-specific information. 5.2.4 COMMAND DESCRIPTIONS All commands supported by the programming executive are described in Section 5.2.5 “SCHECK Command” through Section 5.2.12 “QVER Command”. 5.2.5 SCHECK COMMAND 15 12 11 0 Opcode Length Field Description Opcode 0h Length 1h DS39768D-page 36 The SCHECK command instructs the programming executive to do nothing but generate a response. This command is used as a “Sanity Check” to verify that the programming executive is operational. Expected Response (2 words): 1000h 0002h Note: This instruction is not required programming but is provided development purposes only. for for © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 5.2.6 15 READC COMMAND 12 11 5.2.7 8 7 Opcode 0 15 12 11 8 7 Opcode Length N READP COMMAND 0 Length N Addr_MSB Reserved Addr_LS Addr_MSB Addr_LS Field Description Field Description Opcode 1h Length 3h Opcode 2h N Number of 8-bit Device ID registers to read (max. of 256) Length 4h N Number of 24-bit instructions to read (max. of 32768) Reserved 0h Addr_MSB MSB of 24-bit source address Addr_LS Least Significant 16 bits of 24-bit source address Addr_MSB MSB of 24-bit source address Addr_LS Least Significant 16 bits of 24-bit source address The READC command instructs the programming executive to read N or Device ID registers, starting from the 24-bit address specified by Addr_MSB and Addr_LS. This command can only be used to read 8-bit or 16-bit data. When this command is used to read Device ID registers, the upper byte in every data word returned by the programming executive is 00h and the lower byte contains the Device ID register value. Expected Response (4 + 3 * (N – 1)/2 words for N odd): 1100h 2+N Device ID Register 1 ... Device ID Register N Note: Reading unimplemented memory will cause the programming executive to reset. Please ensure that only memory locations present on a particular device are accessed. The READP command instructs the programming executive to read N 24-bit words of code memory, including Configuration Words, starting from the 24-bit address specified by Addr_MSB and Addr_LS. This command can only be used to read 24-bit data. All data returned in response to this command uses the packed data format described in Section 5.2.2 “Packed Data Format”. Expected Response (2 + 3 * N/2 words for N even): 1200h 2 + 3 * N/2 Least significant program memory word 1 ... Least significant data word N Expected Response (4 + 3 * (N – 1)/2 words for N odd): 1200h 4 + 3 * (N – 1)/2 Least significant program memory word 1 ... MSB of program memory word N (zero padded) Note: © 2008 Microchip Technology Inc. Reading unimplemented memory will cause the programming executive to reset. Please ensure that only memory locations present on a particular device are accessed. DS39768D-page 37 PIC24FJXXXGA0XX 5.2.8 PROGC COMMAND 15 12 11 5.2.9 8 7 Opcode 0 15 12 11 8 7 Opcode Length Reserved PROGP COMMAND 0 Length Reserved Addr_MSB Addr_MSB Addr_LS Addr_LS Data D_1 D_2 Field Opcode ... Description D_96 4h Length 4h Reserved 0h Field Description Addr_MSB MSB of 24-bit destination address Opcode 5h Addr_LS Least Significant 16 bits of 24-bit destination address Length 63h Reserved 0h Data 8-bit data word Addr_MSB MSB of 24-bit destination address The PROGC command instructs the programming executive to program a single Device ID register located at the specified memory address. Addr_LS Least Significant 16 bits of 24-bit destination address D_1 16-bit data word 1 After the specified data word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. D_2 16-bit data word 2 Expected Response (2 words): 1400h 0002h ... 16-bit data word 3 through 95 D_96 16-bit data word 96 The PROGP command instructs the programming executive to program one row of code memory, including Configuration Words (64 instruction words), to the specified memory address. Programming begins with the row address specified in the command. The destination address should be a multiple of 80h. The data to program to memory, located in command words, D_1 through D_96, must be arranged using the packed instruction word format shown in Figure 5-5. After all data has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 1500h 0002h Note: DS39768D-page 38 Refer to Table 2-3 for code memory size information. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 5.2.10 PROGW COMMAND 15 12 11 5.2.11 8 7 Opcode 0 Length Data_MSB 15 QBLANK COMMAND 12 11 Opcode 0 Length Addr_MSB PSize_MSW Addr_LS PSize_LSW Data_LS Field Field Description Description Opcode Ah Dh Length 3h Length 4h PSize Reserved 0h Length of program memory to check in 24-bit words plus one (max. of 49152) Opcode Addr_MSB MSB of 24-bit destination address Addr_LS Least Significant 16 bits of 24-bit destination address Data_MSB MSB of 24-bit data Data_LS Least Significant 16 bits of 24-bit data The QBLANK command queries the programming executive to determine if the contents of code memory and code-protect Configuration bits (GCP and GWRP) are blank (contain all ‘1’s). The size of code memory to check must be specified in the command. The PROGW command instructs the programming executive to program one word of code memory (3 bytes) to the specific memory address. The Blank Check for code memory begins at 0h and advances toward larger addresses for the specified number of instruction words. After the word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. QBLANK returns a QE_Code of F0h if the specified code memory and code-protect bits are blank; otherwise, QBLANK returns a QE_Code of 0Fh. Expected Response (2 words): 1600h 0002h Expected Response (2 words for blank device): 1AF0h 0002h Expected Response (2 words for non-blank device): 1A0Fh 0002h Note: © 2008 Microchip Technology Inc. QBLANK does not check the system operation Configuration bits, since these bits are not set to ‘1’ when a Chip Erase is performed. DS39768D-page 39 PIC24FJXXXGA0XX 5.2.12 5.3.1 QVER COMMAND 15 12 11 0 Opcode Length Field Description Opcode Bh Length 1h All programming executive responses have a general format consisting of a two-word header and any required data for the command. 15 12 11 Opcode Expected Response (2 words): 1BMNh (where “MN” stands for version M.N) 0002h Programming Executive Responses The programming executive sends a response to the programmer for each command that it receives. The response indicates if the command was processed correctly. It includes any required response data or error data. The programming executive response set is shown in Table 5-2. This table contains the opcode, mnemonic and description for each response. The response format is described in Section 5.3.1 “Response Format”. TABLE 5-2: Opcode PROGRAMMING EXECUTIVE RESPONSE OP CODES Mnemonic Description 1h PASS Command successfully processed 2h FAIL Command unsuccessfully processed 3h NACK DS39768D-page 40 Command not known 8 7 Last_Cmd 0 QE_Code Length The QVER command queries the version of the programming executive software stored in test memory. The “version.revision” information is returned in the response’s QE_Code using a single byte with the following format: main version in upper nibble and revision in the lower nibble (i.e., 23h means version 2.3 of programming executive software). 5.3 RESPONSE FORMAT D_1 (if applicable) ... D_N (if applicable) Field Description Opcode Response opcode Last_Cmd Programmer command that generated the response QE_Code Query code or error code. Length Response length in 16-bit words (includes 2 header words) D_1 First 16-bit data word (if applicable) D_N Last 16-bit data word (if applicable) 5.3.1.1 Opcode Field The opcode is a 4-bit field in the first word of the response. The opcode indicates how the command was processed (see Table 5-2). If the command was processed successfully, the response opcode is PASS. If there was an error in processing the command, the response opcode is FAIL and the QE_Code indicates the reason for the failure. If the command sent to the programming executive is not identified, the programming executive returns a NACK response. 5.3.1.2 Last_Cmd Field The Last_Cmd is a 4-bit field in the first word of the response and indicates the command that the programming executive processed. Since the programming executive can only process one command at a time, this field is technically not required. However, it can be used to verify that the programming executive correctly received the command that the programmer transmitted. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 5.3.1.3 QE_Code Field The QE_Code is a byte in the first word of the response. This byte is used to return data for query commands and error codes for all other commands. When the programming executive processes one of the two query commands (QBLANK or QVER), the returned opcode is always PASS and the QE_Code holds the query response data. The format of the QE_Code for both queries is shown in Table 5-3. TABLE 5-3: Query QE_Code FOR QUERIES QE_Code QBLANK 0Fh = Code memory is NOT blank F0h = Code memory is blank QVER 0xMN, where programming executive software version = M.N (i.e., 32h means software version 3.2) When the programming executive processes any command other than a query, the QE_Code represents an error code. Supported error codes are shown in Table 5-4. If a command is successfully processed, the returned QE_Code is set to 0h, which indicates that there was no error in the command processing. If the verify of the programming for the PROGP or PROGC command fails, the QE_Code is set to 1h. For all other programming executive errors, the QE_Code is 2h. © 2008 Microchip Technology Inc. TABLE 5-4: QE_Code FOR NON-QUERY COMMANDS QE_Code Description 0h No error 1h Verify failed 2h Other error 5.3.1.4 Response Length The response length indicates the length of the programming executive’s response in 16-bit words. This field includes the 2 words of the response header. With the exception of the response for the READP command, the length of each response is only 2 words. The response to the READP command uses the packed instruction word format described in Section 5.2.2 “Packed Data Format”. When reading an odd number of program memory words (N odd), the response to the READP command is (3 * (N + 1)/2 + 2) words. When reading an even number of program memory words (N even), the response to the READP command is (3 * N/2 + 2) words. DS39768D-page 41 PIC24FJXXXGA0XX 5.4 Programming the Programming Executive to Memory 5.4.1 OVERVIEW If it is determined that the programming executive is not present in executive memory (as described in Section 4.2 “Confirming the Presence of the Programming Executive”), it must be programmed into executive memory using ICSP, as described in Section 3.0 “Device Programming – ICSP”. TABLE 5-5: Command (Binary) Storing the programming executive to executive memory is similar to normal programming of code memory. Namely, the executive memory must be erased, and then the programming executive must be programmed 64 words at a time. Erasing the last page of executive memory will cause the FRC oscillator calibration settings and device diagnostic data in the Diagnostic and Calibration Words, at addresses 8007F0h to 8007FEh, to be erased. In order to retain this calibration, these memory locations should be read and stored prior to erasing executive memory. They should then be reprogrammed in the last words of program memory. This control flow is summarized in Table 5-5. PROGRAMMING THE PROGRAMMING EXECUTIVE Data (Hex) Description Step 1: Exit Reset vector and erase executive memory. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize pointers to read Diagnostic and Calibration Words for storage in W6-W13. 0000 0000 0000 0000 0000 200800 880190 207F00 2000C2 000000 MOV MOV MOV MOV NOP #0x80, W0 W0, TBLPAG #0x07F0, W1 #0xC, W2 Step 3: Repeat this step 8 times to read Diagnostic and Calibration Words, storing them in W registers, W6-W13. 0000 0000 0000 BA1931 000000 000000 TBLRDL NOP NOP [W1++].[W2++] Step 4: Initialize the NVMCON to erase executive memory. 0000 0000 240420 883B00 MOV MOV #0x4042, W0 W0, NVMCON Step 5: Initialize Erase Pointers to first page of executive and then initiate the erase cycle. 0000 0000 0000 0000 0000 0000 0000 0000 00000 0000 200800 880190 200001 000000 BB0881 000000 000000 A8E761 000000 000000 MOV MOV MOV NOP TBLWTL NOP NOP BSET NOP NOP #0x80, W0 W0, TBLPAG #0x0, W1 W1, [W1] NVMCON, #15 Step 6: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0001 0000 DS39768D-page 42 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO NOP MOV MOV NOP Clock out NOP 0x200 NVMCON, W2 W2, VISI contents of the VISI register. © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX TABLE 5-5: Command (Binary) PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Data (Hex) Description Step 7: Repeat Steps 5 and 6 to erase the second page of executive memory. The W1 Pointer should be incremented by 400h to point to the second page. Step 8: Initialize TBLPAG and NVMCON to write stored diagnostic and calibration as single words. Initialize W1 and W2 as Write and Read Pointers to rewrite stored Diagnostic and Calibration Words. 0000 0000 0000 0000 0000 0000 0000 200800 880190 240031 883B01 207F00 2000C2 000000 MOV MOV MOV MOV MOV MOV NOP #0x80, W0 W0, TBLPAG #0x4003, W1 W1, NVMCON #0x07F0, W1 #0xC, W2 Step 9: Perform write of a single word of calibration data and initiate single-word write cycle. 0000 0000 0000 0000 0000 0000 BB18B2 000000 000000 A8E761 000000 000000 TBLWTL NOP NOP BSET NOP NOP [W2++], [W1++] NVMCON, #15 Step 10: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B00 883C20 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W0 MOV W0, VISI NOP Clock out contents of VISI register. NOP Step 11: Repeat steps 9-10 seven more times to program the remainder of the Diagnostic and Calibration Words back into program memory. Step 12: Initialize the NVMCON to program 64 instruction words. 0000 0000 240010 883B00 MOV MOV #0x4001, W0 W0, NVMCON Step 13: Initialize TBLPAG and the Write Pointer (W7). 0000 0000 0000 0000 200800 880190 EB0380 000000 MOV MOV CLR NOP #0x80, W0 W0, TBLPAG W7 Step 14: Load W0:W5 with the next four words of packed programming executive code and initialize W6 for programming. Programming starts from the base of executive memory (800000h) using W6 as a Read Pointer and W7 as a Write Pointer. 0000 0000 0000 0000 0000 0000 2<LSW0>0 2<MSB1:MSB0>1 2<LSW1>2 2<LSW2>3 2<MSB3:MSB2>4 2<LSW3>5 © 2008 Microchip Technology Inc. MOV MOV MOV MOV MOV MOV #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 #<LSW2>, W3 #<MSB3:MSB2>, W4 #<LSW3>, W5 DS39768D-page 43 PIC24FJXXXGA0XX TABLE 5-5: Command (Binary) PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Data (Hex) Description Step 15: Set the Read Pointer (W6) and load the (next four write) latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0300 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 CLR W6 NOP TBLWTL [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTL [W6++], NOP NOP TBLWTL [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTH.B [W6++], NOP NOP TBLWTL [W6++], NOP NOP [W7] [W7++] [++W7] [W7++] [W7] [W7++] [++W7] [W7++] Step 16: Repeat Steps 14-15, sixteen times, to load the write latches for the 64 instructions. Step 17: Initiate the programming cycle. 0000 0000 0000 A8E761 000000 000000 BSET NOP NOP NVMCON, #15 Step 18: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. 0000 0000 0000 0000 0000 0001 0000 040200 000000 803B02 883C22 000000 <VISI> 000000 GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP Step 19: Reset the device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 20: Repeat Steps 14-19 until all 16 rows of executive memory have been programmed. On the final row, make sure to initialize the write latches at the Diagnostic and Calibration Words locations with 0xFFFFFF to ensure that the calibration is not overwritten. DS39768D-page 44 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 5.4.2 PROGRAMMING VERIFICATION After the programming executive has been programmed to executive memory using ICSP, it must be verified. Verification is performed by reading out the contents of executive memory and comparing it with the image of the programming executive stored in the programmer. TABLE 5-6: Command (Binary) Reading the contents of executive memory can be performed using the same technique described in Section 3.8 “Reading Code Memory”. A procedure for reading executive memory is shown in Table 5-6. Note that in Step 2, the TBLPAG register is set to 80h, such that executive memory may be read. The last eight words of executive memory should be verified with stored values of the Diagnostic and Calibration Words to ensure accuracy. READING EXECUTIVE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 000000 040200 000000 NOP GOTO NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. 0000 0000 0000 200800 880190 EB0300 MOV MOV CLR #0x80, W0 W0, TBLPAG W6 Step 3: Initialize the Write Pointer (W7) to point to the VISI register. 0000 0000 207847 000000 MOV NOP #VISI, W7 Step 4: Read and clock out the contents of the next two locations of executive memory through the VISI register using the REGOUT command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 BA0B96 000000 000000 <VISI> 000000 BADBB6 000000 000000 BAD3D6 000000 000000 <VISI> 000000 BA0BB6 000000 000000 <VISI> 000000 TBLRDL [W6], [W7] NOP NOP Clock out contents of VISI register NOP TBLRDH.B [W6++], [W7++] NOP NOP TBLRDH.B [++W6], [W7--] NOP NOP Clock out contents of VISI register NOP TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register NOP Step 5: Reset the device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 Step 6: Repeat Steps 4 and 5 until all desired code memory is read. © 2008 Microchip Technology Inc. DS39768D-page 45 PIC24FJXXXGA0XX 6.0 DEVICE DETAILS 6.1 Device ID TABLE 6-1: DEVICE IDs Device DEVID PIC24FJ16GA002 0444h The Device ID region of memory can be used to determine mask, variant and manufacturing information about the chip. The Device ID region is 2 x 16 bits and it can be read using the READC command. This region of memory is read-only and can also be read when code protection is enabled. PIC24FJ16GA004 044Ch PIC24FJ32GA002 0445h PIC24FJ32GA004 044Dh PIC24FJ48GA002 0446h PIC24FJ48GA004 044Eh Table 6-1 shows the Device ID for each device, Table 6-2 shows the Device ID registers and Table 6-3 describes the bit field of each register. PIC24FJ64GA002 0447h PIC24FJ64GA004 044Fh PIC24FJ64GA006 0405h TABLE 6-2: PIC24FJ64GA008 0408h PIC24FJ64GA010 040Bh PIC24FJ96GA006 0406h PIC24FJ96GA008 0409h PIC24FJ96GA010 040Ch PIC24FJ128GAGA006 0407h PIC24FJ128GAGA008 040Ah PIC24FJ128GAGA010 040Dh PIC24FJXXXGA0XX DEVICE ID REGISTERS Bit Address Name 15 FF0000h DEVID FF0002h DEVREV TABLE 6-3: Bit Field FAMID<7:0> 14 13 12 11 — 10 9 8 7 6 5 4 FAMID<7:0> — 2 1 0 DEV<5:0> MAJRV<2:0> — DOT<2:0> DEVICE ID BIT DESCRIPTIONS Register DEVID Description Encodes the family ID of the device DEV<5:0> DEVID Encodes the individual ID of the device MAJRV<2:0> DEVREV Encodes the major revision number of the device DOT<2:0> DEVREV Encodes the minor revision number of the device DS39768D-page 46 3 © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 6.2 Checksum Computation Checksums for the PIC24FJXXXGA0XX family are 16 bits in size. The checksum is calculated by summing the following: • Contents of code memory locations • Contents of Configuration registers TABLE 6-4: CHECKSUM COMPUTATION Read Code Protection Device PIC24FJ16GA002 PIC24FJ16GA004 PIC24FJ32GA002 PIC24FJ32GA004 PIC24FJ48GA002 PIC24FJ48GA004 PIC24FJ64GA002 PIC24FJ64GA004 PIC24FJ64GA006 PIC24FJ64GA008 PIC24FJ64GA010 PIC24FJ96GA006 PIC24FJ96GA008 PIC24FJ96GA010 Legend: Note: Table 6-4 describes how to calculate the checksum for each device. All memory locations are summed, one byte at a time, using only their native data size. More specifically, Configuration registers are summed by adding the lower two bytes of these locations (the upper byte is ignored), while code memory is summed by adding all three bytes of code memory. Checksum Computation Erased Checksum Value Checksum with 0xAAAAAA at 0x0 and Last Code Address Disabled CFGB + SUM(0:02BFB) 0xBB5A 0xB95C Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:02BFB) 0xBB5A 0xB95C Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:057FB) 0x795A 0x775C Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:057FB) 0x795A 0x775C Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:083FB) 0x375A 0x355C Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:083FB) 0x375A 0x355C Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0ABFB) 0xFB5A 0xF95C Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0ABFB) 0xFB5A 0xF95C Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0ABFB) 0xFACC 0xF8CE Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0ABFB) 0xFACC 0xF8CE Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0ABFB) 0xFACC 0xF8CE Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0FFFB) 0x7CCC 0x7ACE Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0FFFB) 0x7CCC 0x7ACE Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0FFFB) 0x7CCC 0x7ACE Enabled 0 0x0000 0x0000 Description Byte sum of locations, a to b inclusive (all 3 bytes of code memory) Configuration Block (masked), 64/80/100-Pin Devices = Byte sum of (CW1 & 0x7DDF + CW2 & 0x87E3) 28/44-Pin Devices = Byte sum of (CW1 & 0x7FDF + CW2 & 0xFFF7) CW1 address is last location of implemented program memory; CW2 is (last location – 2). Item SUM[a:b] CFGB = = © 2008 Microchip Technology Inc. DS39768D-page 47 PIC24FJXXXGA0XX TABLE 6-4: CHECKSUM COMPUTATION (CONTINUED) Read Code Protection Device PIC24FJ128GAGA006 PIC24FJ128GAGA008 PIC24FJ128GAGA010 Legend: Note: Checksum Computation Erased Checksum Value Checksum with 0xAAAAAA at 0x0 and Last Code Address Disabled CFGB + SUM(0:0157FB) 0xF8CC 0xF6CE Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0157FB) 0xF8CC 0xF6CE Enabled 0 0x0000 0x0000 Disabled CFGB + SUM(0:0157FB) 0xF8CC 0xF6CE Enabled 0 0x0000 0x0000 Description Byte sum of locations, a to b inclusive (all 3 bytes of code memory) Configuration Block (masked), 64/80/100-Pin Devices = Byte sum of (CW1 & 0x7DDF + CW2 & 0x87E3) 28/44-Pin Devices = Byte sum of (CW1 & 0x7FDF + CW2 & 0xFFF7) CW1 address is last location of implemented program memory; CW2 is (last location – 2). Item SUM[a:b] CFGB DS39768D-page 48 = = © 2008 Microchip Technology Inc. PIC24FJXXXGA0XX 7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS Standard Operating Conditions Operating Temperature: 0°C to +70°C. Programming at +25°C is recommended. Param Symbol No. Characteristic Min Max Units VDDCORE + 0.1 3.60 V D111 VDD Supply Voltage During Programming D112 IPP Programming Current on MCLR — 5 μA D113 IDDP Supply Current During Programming — 2 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V Conditions Normal programming(1,2) D080 VOL Output Low Voltage — 0.4 V IOL = 8.5 mA @ 3.6V D090 VOH Output High Voltage 3.0 — V IOH = -3.0 mA @ 3.6V D012 CIO Capacitive Loading on I/O pin (PGDx) — 50 pF To meet AC specifications D013 CF Filter Capacitor Value on VCAP 4.7 10 μF Required for controller core P1 TPGC Serial Clock (PGCx) Period 100 — ns P1A TPGCL Serial Clock (PGCx) Low Time 40 — ns P1B TPGCH Serial Clock (PGCx) High Time 40 — ns P2 TSET1 Input Data Setup Time to Serial Clock ↑ 15 — ns P3 THLD1 Input Data Hold Time from PGCx ↑ 15 — ns P4 TDLY1 Delay Between 4-Bit Command and Command Operand 40 — ns P4A TDLY1A Delay Between 4-Bit Command Operand and Next 4-Bit Command 40 — ns P5 TDLY2 Delay Between Last PGCx ↓ of Command Byte to First PGCx ↑ of Read of Data Word 20 — ns P6 TSET2 VDD ↑ Setup Time to MCLR ↑ 100 — ns P7 THLD2 Input Data Hold Time from MCLR ↑ 25 — ms P8 TDLY3 Delay Between Last PGCx ↓ of Command Byte to PGDx ↑ by Programming Executive 12 — μs P9 TDLY4 Programming Executive Command Processing Time 40 — μs P10 TDLY6 PGCx Low Time After Programming 400 — ns P11 TDLY7 Chip Erase Time 400 — ms P12 TDLY8 Page Erase Time 40 — ms P13 TDLY9 Row Programming Time 2 — ms P14 TR MCLR Rise Time to Enter ICSP™ mode — 1.0 μs P15 TVALID Data Out Valid from PGCx ↑ 10 — ns P16 TDLY10 Delay Between Last PGCx ↓ and MCLR ↓ 0 — s P17 THLD3 MCLR ↓ to VDD ↓ 100 — ns P18 TKEY1 Delay from First MCLR ↓ to First PGCx ↑ for Key Sequence on PGDx 40 — ns P19 TKEY2 Delay from Last PGCx ↓ for Key Sequence on PGDx to Second MCLR ↑ 1 — ms P20 TDLY11 Delay Between PGDx ↓ by Programming Executive to PGDx Driven by Host 23 — µs P21 TDLY12 Delay Between Programming Executive Command Response Words 8 — ns Note 1: 2: VDDCORE must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See Section 2.1 “Power Requirements” for more information. (Minimum VDDCORE allowing Flash programming is 2.25V.) VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. © 2008 Microchip Technology Inc. DS39768D-page 49 PIC24FJXXXGA0XX NOTES: DS39768D-page 50 © 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. 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