dsPIC33EPXXGS202 FAMILY dsPIC33EPXXGS202 Family Flash Programming Specification 1.0 DEVICE OVERVIEW This document defines the programming specification for the dsPIC33EPXXGS202 16-bit Digital Signal Controller (DSC) family. This programming specification is required only for those developing programming support for the following devices: • dsPIC33EP16GS202 • dsPIC33EP32GS202 Topics covered include: • • • • • • • • Section 1.0 “Device Overview” Section 2.0 “Programming Overview” Section 3.0 “Device Programming – ICSP” Section 4.0 “Device Programming – Enhanced ICSP” Section 5.0 “The Programming Executive” Section 6.0 “Device ID” Section 7.0 “Checksum Computation” Section 8.0 “AC/DC Characteristics and Timing Requirements” 2.0 PROGRAMMING OVERVIEW There are two methods of programming that are discussed in this programming specification: • In-Circuit Serial Programming™ (ICSP™) • Enhanced In-Circuit Serial Programming The ICSP programming method is the most direct method to program the device; it is also the slower of the two methods. It provides native, low-level programming capability to erase, program and verify the device. The Enhanced In-Circuit Serial Programming (Enhanced ICSP) protocol uses a faster method that takes advantage of the Programming Executive (PE), as illustrated in Figure 2-1. The Programming Executive provides all the necessary functionality to erase, program and verify the chip through a small command set. The command set allows the programmer to program the dsPIC33EPXXGS202 family devices without having to deal with the low-level programming protocols of the chip. FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™ dsPIC33EPXXGS202 Programmer Programming Executive On-Chip Memory This specification is divided into two major sections that describe the programming methods independently. Section 3.0 “Device Programming – ICSP” describes the In-Circuit Serial Programming method. Section 4.0 “Device Programming – Enhanced ICSP” describes the Enhanced In-Circuit Serial Programming (ICSP) method. 2014-2015 Microchip Technology Inc. DS70005192B-page 1 dsPIC33EPXXGS202 FAMILY 2.1 Required Connections Figure 2-2 and Table 2-1). This helps to maintain the stability of the regulator. The specifications for core voltage and capacitance are listed in Section 8.0 “AC/ DC Characteristics and Timing Requirements”. These devices require specific connections for programming to take place. These connections include power, VCAP, MCLR and one programming pin pair (PGEDx/PGECx). Table 2-1 describes these connections (refer to the specific device data sheet for pin descriptions and power connection requirements). 2.2 FIGURE 2-2: 3.3V Power Requirements dsPIC33EPXXGS202 VDD All devices in the dsPIC33EPXXGS202 family power their core digital logic at a nominal 1.8V. All devices in the dsPIC33EPXXGS202 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. AVDD VCAP CEFC (10 F typ) VSS AVSS The regulator provides power to the core from the other VDD pins. A low-ESR capacitor (such as ceramic or tantalum) must be connected to the VCAP pin (see TABLE 2-1: CONNECTIONS FOR THE ON-CHIP REGULATOR PINS USED DURING PROGRAMMING Pin Name Pin Type Pin Description MCLR I Programming Enable VDD and AVDD(1) VSS and AVSS(1) P Power Supply(1) P Ground(1) VCAP P CPU Logic Filter Capacitor Connection PGECx I Programming Pin Pair: Serial Clock PGEDx I/O Programming Pin Pair: Serial Data Legend: I = Input O = Output P = Power Note 1: All power supply and ground pins must be connected, including AVDD and AVSS. DS70005192B-page 2 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 2.3 Pin Diagrams 2.3.1 All devices in the dsPIC33EPXXGS202 family have three separate pairs of programming pins, labeled as PGEC1/PGED1, PGEC2/PGED2 and PGEC3/PGED3. Any one of these pin pairs may be used for device programming by either ICSP or Enhanced ICSP. Unlike voltage supply and ground pins, it is not necessary to connect all three pin pairs to program the device. However, the programming method must use both pins of the same pair. Figure 2-3 shows the pin diagrams for the dsPIC33EPXXGS202 family. The pins that are required for programming are listed in Table 2-1 and are indicated in bold text in the figures. Refer to the appropriate device data sheet for complete pin descriptions. FIGURE 2-3: PGECx AND PGEDx PIN PAIRS PIN DIAGRAMS 28-Pin SSOP/SOIC 1 28 AVDD RA0 2 AVSS RA1 RA2 3 4 27 26 25 24 RB0 5 RB9 RB10 VSS 6 7 RB1 9 RB2 10 11 23 22 21 RA3 RA4 RB14 RB13 RB12 RB11 20 VCAP 19 VSS 18 PGEC1 PGEC2 VDD 12 17 13 PGED3 14 16 15 PGED1 RB5 PGEC3 PGED2 Pin 8 dsPIC33EP16GS202 dsPIC33EP32GS202 MCLR Complete Pin Functions 11 PGED2/AN8/AAN1/ANN1/INT0/RP35/RB3 12 PGEC2/ADTRG31/RP36/RB4 14 PGED3/RP40/RB8 15 PGEC3/RP47/RB15 17 PGED1/TDI/AN10/SCL1/RP38/RB6 18 PGEC1/AN11/SDA1/RP39/RB7 Legend: Bold indicates pins used in device programming; the complete list of functions associated with programming/ emulation pins is shown in the accompanying table. 2014-2015 Microchip Technology Inc. DS70005192B-page 3 dsPIC33EPXXGS202 FAMILY FIGURE 2-4: PIN DIAGRAMS PGEC1 VSS RB11 VCAP RB14 RB13 RB12 28-Pin QFN-S 6x6 mm 28-Pin UQFN 6x6 mm 28-Pin UQFN 4x4 mm 21 20 19 18 17 16 15 RA4 RA3 AVss AVDD MCLR RA0 RA1 22 23 24 dsPIC33EP16GS202 25 dsPIC33EP32GS202 26 27 28 14 13 12 11 10 9 8 PGED1 RB5 PGEC3 PGED3 VDD PGEC2 PGED2 Pin VSS RB1 RB2 RA2 RB0 RB9 RB10 1 2 3 4 5 6 7 Complete Pin Functions 8 PGED2/AN8/AAN1/ANN1/INT0/RP35/RB3 9 PGEC2/ADTRG31/RP36/RB4 11 PGED3/RP40/RB8 12 PGEC3/RP47/RB15 14 PGED1/TDI/AN10/SCL1/RP38/RB6 15 PGEC1/AN11/SDA1/RP39/RB7 Legend: Bold indicates pins used in device programming; the complete list of functions associated with programming/ emulation pins is shown in the accompanying table. DS70005192B-page 4 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 2.4 Program Memory Write/Erase Requirements The Flash program memory on dsPIC33EPXXGS202 devices has a specific write/erase requirement that must be adhered to for proper device operation. The rule is that any given word in memory must not be written without first erasing the page in which it is located. Thus, the easiest way to conform to this rule is to write all the data in a programming block within one write cycle. The programming methods specified in this document comply with this requirement. Note: 2.5 A program memory bit can programmed from ‘1’ to ‘0’ only. be Memory Map The Flash program memory map extends from 000000h to FFFFFEh. Code memory is located at the start of the memory map. The last locations of implemented code memory are reserved for the device Configuration bits. Table 2-2 lists the code memory size, the size of the erase blocks and the number of erase blocks present in each device variant. Locations, 800000h through 800BFE, are reserved for executive code memory. This region stores the Programming Executive and the debugging executive. The Programming Executive is used for device programming and the debugging executive is used for in-circuit debugging. This region of memory cannot be used to store user code. See Section 5.0 “The Programming Executive” for more information. The special latches used for device programming are located in the memory from FA0000h through FA0002h. See Section 3.7 “Writing Code Memory”. 2014-2015 Microchip Technology Inc. Locations, FF0000h and FF0002h, are reserved for the Device ID Word registers. These bits can be used by the programmer to identify which device type is being programmed. They are described in Section 6.0 “Device ID”. The Device ID registers read out normally, even after code protection is applied. The locations, 800F80h through 800FFEh, are a One-Time-Programmable (OTP) memory area. The OTP Words can be used for storing product information, such as serial numbers, system manufacturing dates, manufacturing lot numbers and other application-specific information. They are described in Section 2.6.3 “OTP (One-Time-Programmable) Memory”. Figure 2-5 through Figure 2-6 show a generic memory map for all devices. See the “Memory Organization” chapter in the specific device data sheet for more information. TABLE 2-2: CODE MEMORY SIZE Device Family User Memory Limit (Instruction Word) Write Blocks/ No. of Rows Erase Blocks/ No. of Pages dsPIC33EP16GS202 2BFE (5632) 88 11 dsPIC33EP32GS202 57FE (11264) 176 22 Note: One page is equal to 512 instruction words. One row is equal to 64 instruction words. DS70005192B-page 5 dsPIC33EPXXGS202 FAMILY FIGURE 2-5: PROGRAM MEMORY MAP FOR dsPIC33EP16GS202 DEVICES Code Memory Space 0x000000 Code Flash Memory (5312 Instruction) Device Configuration 0x002B7E 0x002B80 0x02BFE 0x002C00 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Executive Code Memory Configuration Memory Space Reserved UDID Reserved OTP Memory 0x800BFE 0x800C00 0x800EFE 0x800F00 0x800F08 0x800F0A 0x800F80 0x800FFE 0x801000 Reserved Write Latches Reserved DEVID Reserved 0xF9FFFE 0xFA0000 0xFA0002 0xFA0004 0xFEFFFE 0xFF0000 0xFF0002 0xFF0004 0xFFFFFE Note: Memory areas are not shown to scale. DS70005192B-page 6 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY FIGURE 2-6: PROGRAM MEMORY MAP FOR dsPIC33EP32GS202 DEVICES Code Memory Space 0x000000 Code Flash Memory (10944 Instructions) Device Configuration 0x00577E 0x005780 0x0057FE 0x005800 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Executive Code Memory Reserved UDID Configuration Memory Space Reserved 0x800BFE 0x800C00 0x800EFE 0x800F00 0x800F08 0x800F0A 0x800F80 OTP Memory 0x800FFE 0x801000 Reserved 0xF9FFFE 0xFA0000 Write Latches 0xFA0002 0xFA0004 Reserved 0xFEFFFE 0xFF0000 DEVID Reserved 0xFF0002 0xFF0004 0xFFFFFE Note: Memory areas are not shown to scale. 2014-2015 Microchip Technology Inc. DS70005192B-page 7 dsPIC33EPXXGS202 FAMILY 2.6 2.6.1 Configuration Bits 2.6.2 OVERVIEW The devices implement an intermediate security feature defined by the FSEC register. The Boot Segment (BS) is the highest privileged segment and the General Segment (GS) is the lowest privileged segment. The total user code memory can be split into BS or GS. The size of the segments is determined by the BSLIM<12:0> bits. The relative location of the segments within user space does not change, such that the BS (if present) occupies the memory area just after the Interrupt Vector Table (IVT) and the GS occupies the space just after BS. The Configuration bits are stored in the last page location of implemented program memory. These bits can be set or cleared to select various device configurations. There are two types of Configuration bits: system operation bits and code-protect bits. The system operation bits determine the power-on settings for system-level components, such as the oscillator and the Watchdog Timer. The code-protect bits prevent program memory from being read and written. Table 2-3 lists the Configuration register address range for each device. Table 2-4 provides the Configuration registers map. Refer to the “Special Features” chapter in the specific device data sheet for more information. Some Configuration bits are reserved and must always be programmed to the value defined in Table 2-4. TABLE 2-3: CODE-PROTECT CONFIGURATION BITS The Configuration Segment (or CS) is a small segment (less than a page, typically just one row) within the code memory address space that contains all user configuration data. CONFIGURATION WORD ADDRESSES Device FSEC FBSLIM FOSCSEL FOSC FWDT FPOR FICD FDEVOPT FALTREG dsPIC33EP16GS202 0x2B8C 0x2B90 0x2B98 0x2B9C 0x2BA0 0x2BA4 0x2BA8 0x2BAC 0x2BB0 dsPIC33EP32GS202 0x578C 0x5790 0x5798 0x579C 0x57A0 0x57A4 0x57A8 0x57AC 0x57B0 DS70005192B-page 8 2014-2015 Microchip Technology Inc. 2014-2015 Microchip Technology Inc. TABLE 2-4: Register Name CONFIGURATION REGISTERS MAP Bits 23-16 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 — CSS2 CSS1 CSS0 CWRP GSS1 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GSS0 GWRP — BSEN BSS1 BSS0 BWRP FSEC — AIVTDIS — — FBSLIM — — — — Reserved — r(2) — — — — — — FOSCSEL — — — — — — — — FOSC — — — — — — — FWDT — — — — — — — WDTPS2 WDTPS1 FPOR — — — — — — — — — — — — — — — — r(1) FICD — — — — — — — — — r(1) — JTAGEN — — — ICS1 ICS0 FDEVOPT — — — — — — — — — — — — — — r(1) — PWMLOCK FALTREG — — — — — — — — — CTXT22 CTXT21 CTXT20 — CTXT12 CTXT11 CTXT10 BSLIM<12:0> Note 1: This bit is reserved and must be programmed as ‘1’. 2: This bit is reserved and must be programmed as ‘0’. PLLKEN WDTWIN1 WDTWIN0 — — — — — — — — IESO — — — — FNOSC2 FNOSC1 FNOSC0 FCKSM0 IOL1WAY — — FCKSM1 WINDIS FWDTEN1 FWDTEN0 WDTPRE WDTPS3 OSCIOFNC POSCMD1 POSCMD0 WDTPS0 DS70005192B-page 9 dsPIC33EPXXGS202 FAMILY Legend: — = unimplemented bit, read as ‘1’; r = Reserved bit — — dsPIC33EPXXGS202 FAMILY TABLE 2-5: dsPIC33EPXXGS202 FAMILY CONFIGURATION BITS DESCRIPTION Bit Field Register Description BWRP FSEC Boot Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected BSS<1:0> FSEC Boot Segment Code Flash Protection Level bits 11 = No protection (other than BWRP write protection) 10 = Standard security 0x = High security BSEN FSEC Boot Segment Control bit 1 = Boot Segment is not enabled 0 = Boot Segment size is determined by the BSLIM<12:0> bits GWRP FSEC General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected GSS<1:0> FSEC General Segment Code Flash Protection Level bits 11 = No protection (other than GWRP write protection) 10 = Standard security 0x = High security CWRP FSEC Configuration Segment Write-Protect bit 1 = Configuration Segment is not write-protected 0 = Configuration Segment is write-protected CSS<2:0> FSEC Configuration Segment Code Flash Protection Level bits 111 = No protection (other than CWRP write protection) 110 = Standard security 10x = Enhanced security 0xx = High security BSLIM<12:0> FBSLIM FNOSC<2:0> FOSCSEL AIVTDIS IESO POSCMD<1:0> DS70005192B-page 10 FSEC FOSCSEL FOSC Boot Segment Code Flash Page Address Limit bits Contains the page address of the first active General Segment page. The value to be programmed is the inverted page address, such that programming additional ‘0’s can only increase the Boot Segment size (i.e., 0x1FFD = 2 Pages or 1024 Instruction Words). Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) Oscillator with Postscaler 110 = Internal Fast RC (FRC) Oscillator with Divide-by-16 101 = LPRC Oscillator 100 = Reserved 011 = Primary (XT, HS, EC) Oscillator with PLL 010 = Primary (XT, HS, EC) Oscillator 001 = Internal Fast RC (FRC) Oscillator with PLL 000 = FRC Oscillator Alternate Interrupt Vector Table Disable bit 1 = Disables AIVT 0 = Enables AIVT Two-Speed Oscillator Start-up Enable bit 1 = Starts up device with FRC, then automatically switches to the user-selected oscillator source when ready 0 = Starts up device with the user-selected oscillator source Primary Oscillator Mode Select bits 11 = Primary Oscillator is disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY TABLE 2-5: Bit Field dsPIC33EPXXGS202 FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register Description OSCIOFNC FOSC OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is the clock output 0 = OSC2 is the general purpose digital I/O pin IOL1WAY FOSC Peripheral Pin Select Configuration bit 1 = Allows only one reconfiguration 0 = Allows multiple reconfigurations FCKSM<1:0> FOSC Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled PLLKEN FOSC PLL Lock Wait Enable bit 1 = Clock switches to the PLL source, will wait until the PLL lock signal is valid 0 = Clock switch will not wait for PLL lock WDTPS<3:0> FWDT Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 WDTPRE FWDT Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 FWDTEN<1:0> FWDT Watchdog Timer Enable bits 11 = WDT is enabled in hardware 10 = WDT is controlled via the SWDTEN bit 01 = WDT is enabled only while device is active and disabled in Sleep; SWDTEN bit is disabled 00 = WDT and SWDTEN are disabled WINDIS FWDT Watchdog Timer Window Enable bit 1 = Watchdog Timer is in Non-Window mode 0 = Watchdog Timer is in Window mode WDTWIN<1:0> FWDT Watchdog Timer Window Select bits 11 = WDT window is 25% of the WDT period 10 = WDT window is 37.5% of the WDT period 01 = WDT window is 50% of the WDT period 00 = WDT Window is 75% of the WDT period ICS<1:0> FICD ICD Communication Channel Select bits 11 = Communicates on PGEC1 and PGED1 10 = Communicates on PGEC2 and PGED2 01 = Communicates on PGEC3 and PGED3 00 = Reserved, do not use PWMLOCK FDEVOPT 2014-2015 Microchip Technology Inc. PWM Lock Enable bit 1 = Certain PWM registers may only be written after a key sequence 0 = PWM registers may be written without a key sequence DS70005192B-page 11 dsPIC33EPXXGS202 FAMILY TABLE 2-5: dsPIC33EPXXGS202 FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register CTXT1<2:0> FALTREG Specifies the Alternate Working Register Set #1 Association with Interrupt Priority Level (IPL) bits 111 = Not assigned 110 = Alternate Register Set #1 assigned to IPL Level 7 101 = Alternate Register Set #1 assigned to IPL Level 6 100 = Alternate Register Set #1 assigned to IPL Level 5 011 = Alternate Register Set #1 assigned to IPL Level 4 010 = Alternate Register Set #1 assigned to IPL Level 3 001 = Alternate Register Set #1 assigned to IPL Level 2 000 = Alternate Register Set #1 assigned to IPL Level 1 CTXT2<2:0> FALTREG Specifies the Alternate Working Register Set #2 Association with Interrupt Priority Level (IPL) bits 111 = Not assigned 110 = Alternate Register Set #2 assigned to IPL Level 7 101 = Alternate Register Set #2 assigned to IPL Level 6 100 = Alternate Register Set #2 assigned to IPL Level 5 011 = Alternate Register Set #2 assigned to IPL Level 4 010 = Alternate Register Set #2 assigned to IPL Level 3 001 = Alternate Register Set #2 assigned to IPL Level 2 000 = Alternate Register Set #2 assigned to IPL Level 1 2.6.3 Description OTP (ONE-TIME-PROGRAMMABLE) MEMORY The dsPIC33EPXXGS202 family devices contain 32 One-Time-Programmable (OTP) Words, located at addresses, 800F80h through 800FFEh. The OTP Words can be utilized by the user for storing checksum, code revisions, product information, such as serial DS70005192B-page 12 numbers, system manufacturing dates, manufacturing lot numbers and other application-specific information. These words can only be written once. Note: The OTP area is not cleared by any erase command. This memory can be written only once. 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 3.0 DEVICE PROGRAMMING – ICSP ICSP mode is a special programming protocol that allows you to read and write to the device memory of the dsPIC33EPXXGS202 devices. The ICSP mode is the most direct method used to program the device, which is accomplished by applying control codes and instructions, serially to the device, using the PGECx and PGEDx pins. ICSP mode also has the ability to read the contents of the executive memory to determine if the Programming Executive is present, and to write the Programming Executive to executive memory if it is missing and then, Enhanced ICSP mode will be used. In ICSP mode, the system clock is taken from the PGECx pin, regardless of the device’s Oscillator Configuration bits. All instructions are shifted serially into an internal buffer, then loaded into the Instruction Register (IR) and executed. No program fetching occurs from internal memory. Instructions are fed in 24 bits at a time. PGEDx is used to shift data in, and PGECx is used as both the serial shift clock and the CPU execution clock. Note 1: During ICSP operation, the operating frequency of PGECx must not exceed 5 MHz. 2: ICSP mode is slower than Enhanced ICSP mode for programming. 3.1 Overview of the Programming Process FIGURE 3-1: HIGH-LEVEL ICSP™ PROGRAMMING FLOW Start Enter ICSP™ Perform Bulk Erase of Code Memory Program Code Memory, Configuration Words and OTP Words Verify Code Memory, Configuration Words and OTP Words Program Code-Protect Configuration Bits Exit ICSP End Figure 3-1 shows the high-level overview of the programming process. After entering ICSP mode, the first action is to Bulk Erase the code memory. Next, the code memory is programmed, followed by the device Configuration bits. Code memory (including the Configuration bits) is then verified to ensure that programming was successful. Then, programming the code-protect Configuration bits can be done if required. 2014-2015 Microchip Technology Inc. DS70005192B-page 13 dsPIC33EPXXGS202 FAMILY 3.2 Entering ICSP Mode Note: As shown in Figure 3-2, entering ICSP Program/Verify mode requires three steps: The key sequence is a specific 32-bit pattern, ‘0100 1101 0100 0011 0100 1000 0101 0001’ (more easily remembered as 4D434851h in hexadecimal). The device will enter ICSP mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. MCLR is briefly driven high, then low (P21). A 32-bit key sequence is clocked into PGEDx. The interval of at least P18 must elapse before presenting the key sequence on PGEDx. MCLR is held low during a specified period, P19, and then driven high. After a P7 + 5 * P1 delay, five clock pulses must be generated on the PGECx pin. 1. 2. 3. 4. FIGURE 3-2: P6 If a capacitor is present on the MCLR pin, the high time for entering ICSP mode can vary. On successful entry, the program memory can be accessed and programmed in serial fashion. ENTERING ICSP™ MODE P21 P19 P14 VDD P7 P1 * 5 VDD VDD MCLR Program/Verify Entry Code = 4D434851h PGEDx 0 b31 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 1 b0 PGECx 1 P18 3.3 ICSP Operation Upon entry into ICSP mode, the CPU is Idle. Execution of the CPU is governed by an internal state machine. A 4-bit control code must be clocked in using PGECx and PGEDx, and this control code is used to command the CPU (see Table 3-1). The SIX control code is used to send instructions to the CPU for execution and the REGOUT control code is used to read data out of the device through the VISI register. DS70005192B-page 14 2 3 4 5 P1A P1B TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE 4-Bit Mnemonic Control Code 0000 SIX 0001 REGOUT 0010-1111 N/A Description Shift in 24-bit instruction and execute. Shift out the VISI register. Reserved. 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 3.3.1 SIX SERIAL INSTRUCTION EXECUTION cycles. While the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see Figure 3-4). The SIX control code allows execution of the PIC24F family assembly instructions. When the SIX code is received, the CPU is suspended for 24 clock cycles, as the instruction is then clocked into the internal buffer. Once the instruction is shifted in, the state machine allows it to be executed over the next four PGC clock FIGURE 3-3: Note: Data bits on PGEDx are latched on the rising edge of the PGECx clock. SIX SERIAL EXECUTION P1 1 2 3 4 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4 PGECx P4 P3 P2 PGEDx 0 0 0 0 LSb X P4A P1A P1B X X X Execute PC – 1, Fetch SIX Control Code X X X X X X 24-Bit Instruction Fetch X X X X MSb 0 0 0 0 Execute 24-Bit Instruction, Fetch Next Control Code PGEDx = Input 3.3.1.1 Differences Between Execution of SIX and a Normal Instruction There are some differences between executing instructions normally and using the ICSP SIX command. As a result, the code examples in this specification may not match those for performing the same functions during normal device operation. The important differences are: • Two-word instructions require two SIX operations to clock in all of the necessary data. Examples of two-word instructions are GOTO and CALL. • Two-cycle instructions require two SIX operations to complete. The first SIX operation shifts in the instruction and begins to execute it. A second SIX operation, which should shift in a NOP to avoid losing data, provides the CPU clocks required to finish executing the instruction. Examples of two-cycle instructions are Table Read (TBLRD) and Table Write (TBLWT) instructions. • The CPU does not automatically stall to account for pipeline changes. For example, the instructions, MOV #0x0,W0, followed by, MOV[W0], W1, must have a NOP inserted in between. If a two-cycle instruction modifies a register, which is used indirectly, it will require two following NOPs: one to execute the second half of the instruction and the other NOP stalls the CPU to correct the pipeline. For example, instructions such as, TBLWTL [W0++], [W1], should be followed by 2 NOPs. • The device Program Counter (PC) continues to automatically increment during ICSP instruction execution, even though the Flash memory is not being used. As a result, the PC may be incremented so that it points to invalid memory locations. Examples of invalid memory spaces are unimplemented Flash addresses or the vector space (location: 0x0 to 0x1FF). If the PC points to these locations, the device will reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the PC to a safe space. The optimal method of achieving this is to perform a “GOTO 0x200” instruction. A CPU stall occurs when an instruction modifies a register that is used for Indirect Addressing by the instruction immediately following the CPU stall. During normal operation, the CPU will automatically force a NOP while the new data is read. While using ICSP, there is no automatic stall, so any indirect references to a recently modified register should be proceeded with a NOP. 2014-2015 Microchip Technology Inc. DS70005192B-page 15 dsPIC33EPXXGS202 FAMILY 3.3.2 REGOUT SERIAL INSTRUCTION EXECUTION The REGOUT code is unique as the PGEDx pin is an input when the control code is transmitted to the device. However, after the control code is processed, the PGEDx pin becomes an output as the VISI register is shifted out. The REGOUT control code allows for data to be extracted from the device in ICSP mode. It is used to clock the contents of the VISI register, out of the device, over the PGEDx pin. After the REGOUT control code is received, the CPU is held Idle for 8 cycles. After these 8 cycles, an additional 16 cycles are required to clock the data out (see Figure 3-4). Note 1: After the contents of VISI are shifted out, the dsPIC33EPXXGS202 devices maintain PGEDx as an output until the first rising edge of the next clock is received. 2: Data changes on the falling edge and latches on the rising edge of PGECx. For all data transmissions, the Least Significant bit (LSb) is transmitted first. FIGURE 3-4: REGOUT SERIAL EXECUTION 1 2 3 4 1 2 7 8 1 2 3 4 5 6 11 12 13 14 15 16 1 2 3 4 PGECx P4 PGEDx 1 0 0 PGEDx = Input DS70005192B-page 16 LSb 1 0 Execute Previous Instruction, Fetch REGOUT Control Code P4A P5 CPU Held in Idle 2 3 4 ... 10 11 12 13 14 MSb Shift Out VISI Register<15:0> PGEDx = Output 0 0 0 0 No Execution Takes Place, Fetch Next Control Code PGEDx = Input 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 3.4 Flash Memory Programming in ICSP Mode 3.4.1 PROGRAMMING OPERATIONS Flash memory write and erase operations are controlled by the NVMCON register. Programming is performed by setting NVMCON to select the type of erase operation (Table 3-2) or write operation (Table 3-3) and initiating the programming by setting the WR control bit (NVMCON<15>). The PGECx clock is required to complete the programming operation. The WR control bit is cleared by hardware when the operation is finished. Refer to Section 8.0 “AC/DC Characteristics and Timing Requirements” for detailed information about the maximum time required for various programming operations. TABLE 3-2: NVMCON Value For protection against accidental operations, the erase/ write initiation sequence must be written to the NVMKEY register to allow any erase or program operation to proceed. The two instructions following the start of the programming sequence should be NOPs. To start an erase or write sequence, the following steps must be completed: 1. 2. 3. 4. Write 55h to the NVMKEY register. Write AAh to the NVMKEY register. Set the WR bit in the NVMCON register. Execute three NOP instructions. The WR bit can be polled to generate enough clock cycles for the programming operation and to determine if the erase or write cycle has been completed. Erase Operation Bulk Erase of user memory only (does not erase Device ID, Programming Executive memory and OTP Words). 4003h Page erase of program or Programming Executive memory. TABLE 3-3: 4001h STARTING AND STOPPING A PROGRAMMING CYCLE NVMCON ERASE OPERATIONS 400Eh NVMCON Value 3.4.2 NVMCON WRITE OPERATIONS Write Operation Double-word programming operation. 2014-2015 Microchip Technology Inc. DS70005192B-page 17 dsPIC33EPXXGS202 FAMILY REGISTER 3-1: R/SO-0(1) NVMCON: NONVOLATILE MEMORY CONTROL REGISTER (REFERENCE ONLY) R/W-0(1) WR WREN R/W-0(1) WRERR R/W-0 NVMSIDL U-0 (2) U-0 — R/W-0 — RPDF (6) R/W-0 URERR(6) bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0(1) R/W-0(1) — — — — NVMOP3(3,4) NVMOP2(3,4) R/W-0(1) R/W-0(1) NVMOP1(3,4) NVMOP0(3,4) bit 7 bit 0 Legend: SO = Settable Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 WR: Write Control Bit(1) 1 = Initiates a Flash memory program or erase operation; the operation is self-timed and the bit is cleared by hardware once the operation is complete 0 = The program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enables Flash program or erase operations 0 = Inhibits Flash program or erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt, or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12 NVMSIDL: NVM Stop in Idle Control bit(2) 1 = Discontinues primary Flash operation when the device enters Idle mode 0 = Continues primary Flash operation when the device enters Idle mode bit 11-10 Unimplemented: Read as ‘0’ bit 9 RPDF: Row Programming Data Format Control bit(6) 1 = Row data to be stored in RAM is in a compressed format 0 = Row data to be stored in RAM is in an uncompressed format bit 8 URERR: Row Programming Data Underrun Error Flag bit(6) 1 = Row programming operation has been terminated due to a data underrun error 0 = No data underrun has occurred bit 7-4 Unimplemented: Read as ‘0’ Note 1: 2: 3: 4: 5: 6: These bits can only be reset on a POR. If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay (TVREG) before Flash memory becomes operational. All other combinations of NVMOP<3:0> are unimplemented. Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress. Two adjacent words on a 4-word boundary are programmed during execution of this operation. Not used in ICSP™ mode. DS70005192B-page 18 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY REGISTER 3-1: NVMCON: NONVOLATILE MEMORY CONTROL REGISTER (REFERENCE ONLY) (CONTINUED) NVMOP<3:0>: NVM Operation Select bits(1,3,4) 1111 = Reserved 1110 = User memory Bulk Erase operation 1101 = Reserved 1100 = Reserved 1011 = Reserved 1010 = Reserved 1001 = Reserved 1000 = Reserved 0111 = Reserved 0101 = Reserved 0100 = Reserved 0011 = Memory Page Erase operation 0010 = Memory Row Program operation(6) 0001 = Memory Double-Word operation(5) 0000 = Reserved bit 3-0 Note 1: 2: 3: 4: 5: 6: These bits can only be reset on a POR. If this bit is set, there will be minimal power savings (IIDLE), and upon exiting Idle mode, there is a delay (TVREG) before Flash memory becomes operational. All other combinations of NVMOP<3:0> are unimplemented. Execution of the PWRSAV instruction is ignored while any of the NVM operations are in progress. Two adjacent words on a 4-word boundary are programmed during execution of this operation. Not used in ICSP™ mode. 2014-2015 Microchip Technology Inc. DS70005192B-page 19 dsPIC33EPXXGS202 FAMILY 3.5 Erasing Program Memory FIGURE 3-5: BULK ERASE FLOW The procedure for erasing the entire code memory is shown in Figure 3-5. Table 3-4 provides the ICSP programming process for erasing the program memory. Note: Program memory must be erased before writing any data to program memory. Start Write 400Eh to NVMCON SFR Set the WR bit to Initiate Erase Poll the WR bit until it is Cleared End TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR BULK ERASE OF CODE MEMORY Command (Binary) Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Set the NVMCON register to erase all user program memory. 0000 0000 0000 0000 2400EA 88394A 000000 000000 MOV MOV NOP NOP #0x400E, W10 W10, NVMCON MOV MOV MOV MOV BSET NOP NOP NOP #0x55, W1 W1, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Step 3: Initiate the erase cycle. 0000 0000 0000 0000 0000 0000 0000 0000 200551 883971 200AA1 883971 A8E729 000000 000000 000000 DS70005192B-page 20 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY TABLE 3-4: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR BULK ERASE OF CODE MEMORY (CONTINUED) Data (Hex) Description Step 4: Generate clock pulses for the code memory Bulk Erase operation to complete until the WR bit is clear. 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 — 3.6 000000 803940 000000 887C40 000000 <VISI> 000000 000000 000000 040200 000000 000000 000000 — NOP MOV NVMCON, W0 NOP MOV W0, VISI NOP Clock out contents of VISI register. NOP NOP NOP GOTO 0x200 NOP NOP NOP Repeat until the WR bit is clear. Page Erase The process for erasing a page is shown in Figure 3-6. Note: For Page Erase operations, the NVMCON value must be modified as per Table 3-2. The NVMADR/U registers must point to any of the locations of the page to be erased. FIGURE 3-6: PAGE ERASE FLOW Start Write 4003h to NVMCON SFR Set the WR bit to Initiate Erase Poll the WR bit until it is Cleared End 2014-2015 Microchip Technology Inc. DS70005192B-page 21 dsPIC33EPXXGS202 FAMILY TABLE 3-5: SERIAL INSTRUCTION EXECUTION FOR ERASING A PAGE OF CODE MEMORY Command (Binary) Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Set the NVMADRU/NVMADR register pair to point to the correct page to be erased. 0000 0000 0000 0000 2xxxx3 2xxxx4 883953 883964 MOV MOV MOV MOV #DestinationAddress<15:0>, W3 #DestinationAddress<23:16>, W4 W3, NVMADR W4, NVMADRU Step 3: Set the NVMCON register to erase the first page of executive memory. 0000 0000 0000 0000 24003A 88394A 000000 000000 MOV MOV NOP NOP #0x4003, W10 W10, NVMCON MOV MOV MOV MOV BSET NOP NOP NOP #0x55, W1 W1, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Step 4: Initiate the erase cycle. 0000 0000 0000 0000 0000 0000 0000 0000 200551 883971 200AA1 883971 A8E729 000000 000000 000000 Step 5: Generate clock pulses for the Page Erase operation to complete until the WR bit is clear. 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 — 000000 803940 000000 887C40 000000 <VISI> 000000 000000 000000 040200 000000 000000 000000 — DS70005192B-page 22 NOP MOV NVMCON, W0 NOP MOV W0, VISI NOP Clock out contents of VISI register. NOP NOP NOP GOTO 0x200 NOP NOP NOP Repeat until the WR bit is clear. 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 3.7 Writing Code Memory FIGURE 3-7: Figure 3-8 provides a high-level description of the method for writing to code memory. 15 Two-word writes program code memory with two instruction words at a time. Two words must be loaded into the write latches, located at the FA0000h address, and the destination address should be loaded to the NVMADR and NVMADRU registers. Next, the write cycle should be started and the WR bit must be checked for the sequence to be complete. This process continues for all the data to be programmed. Table 3-6 provides the ICSP programming details. 8 7 0 LSW1 MSB2 MSB1 LSW2 LSWx: Least Significant 16 bits of instruction word MSBx: Most Significant Byte of instruction word Note: The data loaded into the programming latches must be in the packed format, as shown in Figure 3-7. FIGURE 3-8: PACKED INSTRUCTION WORD FORMAT When the number of instruction words transferred is odd, MSB2 is zero and LSW2 cannot be transmitted. PROGRAM CODE MEMORY FLOW Start Configure Device for Writes Programming Using Two Write Latches Load Two Words into Write Latches Increment Write Pointer Initiate Write Sequence and Poll WR bit to be Cleared All Data Written? No Yes End 2014-2015 Microchip Technology Inc. DS70005192B-page 23 dsPIC33EPXXGS202 FAMILY TABLE 3-6: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY: TWO-WORD LATCH WRITES Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Initialize the TBLPAG register for writing to the latches. 0000 0000 200FAC 8802AC MOV MOV #0xFA, W12 W12, TBLPAG Step 3: Load W0:W2 with the next two packed instruction words to program. 0000 0000 0000 2xxxx0 2xxxx1 2xxxx2 MOV MOV MOV #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 Step 4: Set the Read Pointer (W6) and Write Pointer (W7), and load the (next set of) write latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0300 000000 EB0380 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB0B96 000000 000000 CLR NOP CLR NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL.W NOP NOP W6 W7 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6], [W7] Step 5: Set the NVMADRU/NVMADR register pair to point to the correct address. 0000 0000 0000 0000 2xxxx3 2xxxx4 883953 883964 MOV MOV MOV MOV #DestinationAddress<15:0>, W3 #DestinationAddress<23:16>, W4 W3, NVMADR W4, NVMADRU Step 6: Set the NVMCON register to program two instruction words. 0000 0000 0000 0000 0000 24001A 000000 88394A 000000 000000 DS70005192B-page 24 MOV NOP MOV NOP NOP #0x4001, W10 W10, NVMCON 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY TABLE 3-6: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR PROGRAMMING CODE MEMORY: TWO-WORD LATCH WRITES (CONTINUED) Data (Hex) Description Step 7: Initiate the write cycle. 0000 0000 0000 0000 0000 0000 0000 0000 200551 883971 200AA1 883971 A8E729 000000 000000 000000 MOV MOV MOV MOV BSET NOP NOP NOP #0x55, W1 W1, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Step 8: Generate clock pulses for the program operation to complete until the WR bit is clear. 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 — 000000 803940 00000 887C40 000000 <VISI> 000000 000000 000000 040200 000000 000000 000000 — NOP MOV NVMCON, W0 NOP MOV W0, VISI NOP Clock out contents of VISI register. NOP NOP NOP GOTO 0x200 NOP NOP NOP Repeat until the WR bit is clear. Step 9: Repeat Steps 3-8 until all code memory is programmed. 2014-2015 Microchip Technology Inc. DS70005192B-page 25 dsPIC33EPXXGS202 FAMILY 3.8 Writing Configuration Bits The code protection can be enabled by programming ‘0’ in the code protection Configuration bits. In order to verify the data by reading the Configuration bits after performing the write, the code protection bits should initially be programmed to a ‘1’ to ensure that the verification can be performed properly. After verification is finished, the code protection bits can be programmed to a ‘0’ by using a word write to the appropriate Configuration register. The procedure for writing Configuration bits is similar to the procedure for writing code memory, except that only two 24-bit words can be programmed at a time. To change the values of the Configuration bits once they have been programmed, the device must be erased, as described in Section 3.5 “Erasing Program Memory”, and reprogrammed to the desired value. Table 3-7 provides the ICSP programming details for writing the Configuration bits. TABLE 3-7: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION WORDS Command (Binary) Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Initialize the TBLPAG register for writing to the latches. 0000 0000 200FAC 8802AC MOV MOV #0xFA, W12 W12, TBLPAG Step 3: Load W0:W1 with the next two Configuration Words to program. 0000 0000 0000 0000 2xxxx0 2xxxx1 2xxxx2 2xxxx3 MOV MOV MOV MOV #<Config1 #<Config1 #<Config2 #<Config2 lower upper lower upper word word word word data>, data>, data>, data>, W0 W1 W2 W3 Step 4: Set the Write Pointer (W3) and load the write latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0300 000000 BB0B00 000000 000000 BB9B01 000000 000000 BB0B02 000000 000000 BB9B03 000000 000000 CLR NOP TBLWTL NOP NOP TBLWTH NOP NOP TBLWTL NOP NOP TBLWTH NOP NOP W6 W0, [W6] W1, [W6++] W2, [W6] W3, [W6++] Step 5: Set the NVMADRU/NVMADR register pair to point to the correct Configuration Word address. 0000 0000 0000 0000 2xxxx4 2xxxx5 883954 883965 DS70005192B-page 26 MOV MOV MOV MOV #DestinationAddress<15:0>, W4 #DestinationAddress<23:16>, W5 W4, NVMADR W5, NVMADRU 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY TABLE 3-7: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION WORDS (CONTINUED) Data (Hex) Description Step 6: Set the NVMCON register to program two instruction words. 0000 0000 0000 0000 0000 24001A 000000 88394A 000000 000000 MOV NOP MOV NOP NOP #0x4001, W10 MOV MOV MOV MOV BSET NOP NOP NOP NOP NOP #0x55, W1 W1, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR W10, NVMCON Step 7: Initiate the write cycle. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 200551 883971 200AA1 883971 A8E729 000000 000000 000000 000000 000000 Step 8: Generate clock pulses for the program operation to complete until the WR bit is clear. 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 — 000000 803940 000000 887C40 000000 <VISI> 000000 000000 000000 040200 000000 000000 000000 — NOP MOV NVMCON, W0 NOP MOV W0, VISI NOP Clock out contents of VISI register. NOP NOP NOP GOTO 0x200 NOP NOP NOP Repeat until the WR bit is clear. Step 9: Repeat Steps 3-8 until all Configuration registers are programmed. 2014-2015 Microchip Technology Inc. DS70005192B-page 27 dsPIC33EPXXGS202 FAMILY 3.9 Writing OTP Words 3.11 The procedure for writing to the OTP Words is similar to the procedure for writing to user program memory, except that the OTP Words can only be written once. It is not possible to program a ‘0’ to a ‘1’, but the OTP Words may be programmed from a ‘1’ to a ‘0’. See Figure 2-5 and Figure 2-6 for the locations of the OTP Words. OTP memory must be written, one double-word at a time. 3.10 Reading OTP Words Reading Code Memory Reading from code memory is performed by executing a series of TBLRD instructions and clocking out the data using the REGOUT command. Table 3-8 provides the ICSP programming details for reading code memory. To minimize reading time, the same packed data format that the write procedure uses is utilized. See Section 3.7 “Writing Code Memory” for more details on the packed data format. The procedure for reading OTP Words is similar to the procedure for reading program Flash memory. Since there are multiple OTP Words, they are read one at a time. TABLE 3-8: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction. 0000 0000 0000 200xx0 8802A0 2xxxx6 DS70005192B-page 28 MOV MOV MOV #<SourceAddress23:16>, W0 W0, TBLPAG #<SourceAddress15:0>, W6 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY TABLE 3-8: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED) Data (Hex) Description Step 3: Initialize the Write Pointer (W7) and store the next four locations of code memory to W0:W5. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0380 000000 BA1B96 000000 000000 000000 000000 000000 BADBB6 000000 000000 000000 000000 000000 BADBD6 000000 000000 000000 000000 000000 BA1BB6 000000 000000 000000 000000 000000 BA1B96 000000 000000 000000 000000 000000 BADBB6 000000 000000 000000 000000 000000 BADBD6 000000 000000 000000 000000 000000 BA0BB6 000000 000000 000000 000000 000000 CLR NOP TBLRDL NOP NOP NOP NOP NOP TBLRDH.B NOP NOP NOP NOP NOP TBLRDH.B NOP NOP NOP NOP NOP TBLRDL NOP NOP NOP NOP NOP TBLRDL NOP NOP NOP NOP NOP TBLRDH.B NOP NOP NOP NOP NOP TBLRDH.B NOP NOP NOP NOP NOP TBLRDL NOP NOP NOP NOP NOP 2014-2015 Microchip Technology Inc. W7 [W6], [W7++] [W6++], [W7++] [++W6], [W7++] [W6++], [W7++] [W6], [W7++] [W6++], [W7++] [++W6], [W7++] [W6++], [W7] DS70005192B-page 29 dsPIC33EPXXGS202 FAMILY TABLE 3-8: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED) Data (Hex) Description Step 4: Output W0:W5 using the VISI register and REGOUT command. 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 887C40 000000 <VISI> 000000 887C41 000000 <VISI> 000000 887C42 000000 <VISI> 000000 887C43 000000 <VISI> 000000 887C44 000000 <VISI> 000000 887C45 000000 <VISI> 000000 MOV W0, VISI NOP Clock out contents of VISI register. NOP MOV W1, VISI NOP Clock out contents of VISI register. NOP MOV W2, VISI NOP Clock out contents of VISI register. NOP MOV W3, VISI NOP Clock out contents of VISI register. NOP MOV W4, VISI NOP Clock out contents of VISI register. NOP MOV W5, VISI NOP Clock out contents of VISI register. NOP Step 5: Reset the device internal PC. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 6: Repeat Steps 3-5 until all desired code memory is read. DS70005192B-page 30 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 3.12 Reading Configuration Registers The procedure for reading Configuration bits is similar to the procedure for reading code memory. Since there are multiple Configuration Words, they are read one at a time. TABLE 3-9: Command (Binary) Table 3-9 provides the ICSP programming details for reading the Configuration bits. SERIAL INSTRUCTION EXECUTION FOR READING CONFIGURATION WORDS Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Initialize the TBLPAG register, the Write Pointer (W7)and the Read Pointer (W6) for the TBLRD instruction. 0000 0000 0000 0000 200xx0 20F887 8802A0 2xxxx6 MOV MOV MOV MOV #<Address23:16>, W0 #<VISI>, W7 W0, TBLPAG #<Address15:0>, W6 Step 3: Store the Configuration register and send the contents of the VISI register. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 000000 BA8B96 000000 000000 000000 000000 000000 <VISI> BA0B96 000000 000000 000000 000000 000000 <VISI> NOP TBLRDH [W6], [W7] NOP NOP NOP NOP NOP Clock out contents of VISI register. TBLRDL [W6], [W7] NOP NOP NOP NOP NOP Clock out contents of VISI register. Step 4: Repeat Steps 1-3 until all Configuration registers are read. 2014-2015 Microchip Technology Inc. DS70005192B-page 31 dsPIC33EPXXGS202 FAMILY 3.13 Verify Code Memory and Configuration Bits The verify step involves reading back the code memory space and comparing it against the copy held in the programmer’s buffer. The Configuration Words are verified with the rest of the code. The verify process is shown in Figure 3-9. The lower word of the instruction is read, and then the lower byte of the upper word is read and compared against the instruction stored in the programmer’s buffer. Refer to Section 3.11 “Reading Code Memory” for implementation details of reading code memory. Note: Because the Configuration Words include the device code protection bit, code memory should be verified immediately after writing if code protection is to be enabled. This is because the device will not be readable or verifiable if a device Reset occurs after the code-protect bit has been cleared. 3.14 Exiting ICSP Mode Exiting Program/Verify mode is done by removing VDD from MCLR, as shown in Figure 3-10. The only requirement for exit is that an interval, P16, should elapse between the last clock, and the program signals on PGECx and PGEDx before removing VDD. FIGURE 3-10: EXITING ICSP™ MODE P16 P17 VDD MCLR VDD VDD PGEDx PGECx PGEDx = Input FIGURE 3-9: VERIFY CODE MEMORY FLOW Start Read Low Word with Post-Increment Read High Byte with Post-Increment Does Instruction Word = Expected Data? No Yes No All Code Memory Verified? Yes End DS70005192B-page 32 Failure Report Error 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 4.0 DEVICE PROGRAMMING – ENHANCED ICSP This section discusses programming the device through Enhanced ICSP and the Programming Executive. The Programming Executive resides in executive memory (separate from code memory) and is executed when Enhanced ICSP Programming mode is entered. The Programming Executive provides the mechanism for the programmer (host device) to program and verify the dsPIC33EPXXGS202 devices using a simple command set and communication protocol. There are several basic functions provided by the Programming Executive: • • • • Read Memory Erase Memory Program Memory Blank Check The Programming Executive performs the low-level tasks required for erasing, programming and verifying a device. This allows the programmer to program the device by issuing the appropriate commands and data. A detailed description for each command is provided in Section 5.2 “Programming Executive Commands”. Note: The PE uses the device’s data RAM for variable storage and program execution. After running the PE, no assumptions should be made about the contents of data RAM. FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW Start Confirm Presence of Programming Executive Enter Enhanced ICSP™ Mode Erase Program Memory Program Memory, Configuration Words and OTP Words Verify Program Memory, Configuration Words and OTP Words Program Code-Protect Configuration Bits Exit Enhanced ICSP 4.1 Overview of the Programming Process End Figure 4-1 shows the high-level overview of the programming process. First, it must be determined if the Programming Executive is present in executive memory, then the Enhanced ICSP mode is entered. The program memory is then erased, and the program memory and Configuration Words are programmed and verified. Last, the code-protect Configuration bits are programmed (if required) and Enhanced ICSP mode is exited. 2014-2015 Microchip Technology Inc. DS70005192B-page 33 dsPIC33EPXXGS202 FAMILY 4.2 Confirming the Presence of the Programming Executive Before programming can begin, the programmer must confirm that the Programming Executive is stored in executive memory. The procedure for this task is shown in Figure 4-2. First, In-Circuit Serial Programming (ICSP) mode is entered. Then, the unique Application ID Word stored in executive memory is read. If the Programming Executive is resident, the correct Application ID Word, 0xDF, is read and programming can resume as normal. However, if the Application ID Word is not present, the PE must be programmed to executive code memory using the method described in Section 5.0 “The Programming Executive”. Section 3.0 “Device Programming – ICSP” describes the ICSP programming method. Section 4.3 “Reading the Application ID Word” describes the procedure for reading the Application ID Word in ICSP mode. FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE Start Enter ICSP™ Mode Check the Application ID by Reading Address, 800BFEh Is Application ID Present? Yes No Prog. Executive must be Programmed Exit ICSP Mode Enter Enhanced ICSP Mode Sanity Check End DS70005192B-page 34 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 4.3 Reading the Application ID Word The Application ID Word is stored at the address, 800BFEh, in executive code memory. To read this memory location you must use the SIX control code to move this program memory location to the VISI register. Then, the REGOUT control code must be used to clock the contents of the VISI register out of the device. The corresponding control and instruction codes that must be serially transmitted to the device to perform this operation are provided in Table 4-1. TABLE 4-1: Command (Binary) After the programmer has clocked out the Application ID Word, it must be inspected. If the Application ID has the value, 0xDF, the Programming Executive is resident in memory and the device can be programmed using the mechanism described in Section 4.0 “Device Programming – Enhanced ICSP”. However, if the Application ID has any other value, the Programming Executive is not resident in memory; it must be loaded into memory before the device can be programmed. The procedure for loading the Programming Executive to memory is described in Section 5.0 “The Programming Executive”. SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Initialize the TBLPAG register and the Read Pointer (W0) for the TBLRD instruction. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 200800 8802A0 20BFE0 20F881 000000 BA0890 000000 000000 000000 000000 000000 MOV MOV MOV MOV NOP TBLRDL NOP NOP NOP NOP NOP #0x80, W0 W0, TBLPAG #0xBFE, W0 #VISI, W1 [W0], [W1] Step 3: Output the VISI register using the REGOUT command. 0001 <VISI> Clock out contents of VISI register. 2014-2015 Microchip Technology Inc. DS70005192B-page 35 dsPIC33EPXXGS202 FAMILY 4.4 Entering Enhanced ICSP Mode 4.5 As shown in Figure 4-3, entering Enhanced ICSP Program/Verify mode requires three steps: 1. 2. 3. The MCLR pin is briefly driven high, then low. A 32-bit key sequence is clocked into PGEDx. An interval of at least P18 must elapse before presenting the key sequence on PGEDx. MCLR is held within a specified period of time, then driven high. The key sequence is a specific 32-bit pattern, ‘0100 1101 0100 0011 0100 1000 0101 0000’ (more easily remembered as 4D434850h in hexadecimal format). The device will enter Program/Verify mode only if the key sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. Blank Check The term, “Blank Check”, implies verifying that the device has been successfully erased and has no programmed memory locations. A blank or erased memory location is always read as ‘1’. The Device ID registers (FF0000h:FF0002h) can be ignored by the Blank Check since this region stores device information that cannot be erased. Additionally, all unimplemented memory space and Calibration registers should be ignored by the Blank Check. The QBLANK command is used for the Blank Check. It determines if the code memory is erased by testing these memory regions. A ‘BLANK’ or ‘NOT BLANK’ response is returned. If it is determined that the device is not blank, it must be erased before attempting to program the chip. Once the key sequence is complete, VDD must be applied to MCLR and held at that level for as long as Program/ Verify mode is to be maintained. An interval time of at least time, P19, P7 and P1 * 5, must elapse before presenting data on PGEDx. Signals appearing on PGEDx before P7 has elapsed will not be interpreted as valid. FIGURE 4-3: P6 P14 ENTERING ENHANCED ICSP™ MODE P21 P19 VDD MCLR VDD PGEDx P7 P1 * 5 VDD Program/Verify Entry Code = 4D434850h 0 b31 1 b30 0 b29 0 b28 1 ... b27 0 b3 0 b2 0 b1 0 b0 PGECx P18 DS70005192B-page 36 P1A P1B 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 4.6 4.6.1 Code Memory Programming FIGURE 4-5: FLOWCHART FOR MULTIPLE WORD PROGRAMMING PROGRAMMING METHODOLOGY There are two commands that can be used for programming code memory when utilizing the Programming Executive. The PROG2W command programs and verifies two 24-bit instruction words into the program memory, starting at the specified address. The second and faster command, PROGP, allows up to sixty-four 24-bit instruction words to be programmed and verified into program memory, starting at the specified address. See Section 5.0 “The Programming Executive” for a full description of each of these commands. Start BaseAddress = 0h RemainingCmds = 176 Send PROGP Command to Program BaseAddress Figure 4-4 and Figure 4-5 show the programming methodology for the PROG2W and PROGP commands. In both instances, 11264 instruction words of the dsPIC33EPXXGS202 devices are programmed. FIGURE 4-4: Is PROGP Response PASS? FLOWCHART FOR DOUBLE-WORD PROGRAMMING Yes RemainingCmds = RemainingCmds – 1 Start BaseAddress = 0h RemainingCmds = 5632 BaseAddress = BaseAddress + 80h No Send PROG2W Command to Program BaseAddress Is RemainingCmds ‘0’? Yes End Is PROG2W Response PASS? No No Failure Report Error Yes RemainingCmds = RemainingCmds – 1 BaseAddress = BaseAddress + 04h No Is RemainingCmds ‘0’? Yes End 2014-2015 Microchip Technology Inc. Failure Report Error DS70005192B-page 37 dsPIC33EPXXGS202 FAMILY 4.7 Configuration Bits Programming The Configuration bits are programmed one at a time using the PROG2W command. This command specifies the configuration data and address. When Configuration bits are programmed, any unimplemented bits must be programmed with a ‘1’. Multiple PROG2W commands are required to program all Configuration bits. A flowchart for Configuration bit programming is shown in Figure 4-6. FIGURE 4-6: CONFIGURATION BIT PROGRAMMING FLOW Start 4.8 Programming Verification After the code memory is programmed, the contents of the memory should be verified to ensure that the programming was successful. Verification requires code memory to be read back and compared against the copy held in the programmer’s buffer. The READP command can be used to read back all the programmed code memory and Configuration Words. Alternatively, the programmer can perform the verification after the entire device is programmed using a checksum computation. See Section 7.0 “Checksum Computation” for more information on calculating the checksum. 4.9 Exiting Enhanced ICSP Mode Exiting Program/Verify mode is done by removing VDD from MCLR, as shown in Figure 4-7. The only requirement for exit is that an interval, P16, should elapse between the last clock, and program signals on PGECx and PGEDx, before removing VDD. Send PROG2W Command FIGURE 4-7: Is PROG2W Response PASS? No EXITING ENHANCED ICSP™ MODE P16 P17 VDD Yes MCLR ConfigAddress = ConfigAddress + 04h No Last Configuration Word? VDD VDD PGEDx Yes End Failure Report Error PGECx PGEDx = Input DS70005192B-page 38 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 5.0 Note: 5.1 THE PROGRAMMING EXECUTIVE FIGURE 5-1: The Programming Executive can be obtained from each device page on the Microchip web site: www.microchip.com. P1 1 PGECx Programming Executive Communication PGEDx 4 5 6 11 12 13 14 P1A 15 16 P3 MSb 14 13 12 11 ... 5 4 3 2 1 LSb Since a 2-wire SPI is used, and data transmissions are bidirectional, a simple protocol is used to control the direction of PGEDx. When the programmer completes a command transmission, it releases the PGEDx line and allows the PE to drive this line high. The PE keeps the PGEDx line high to indicate that it is processing the command. After the PE has processed the command, it brings PGD low (P9b) to indicate to the programmer that the response is available to be clocked out. The programmer can begin to clock out the response after a maximum wait (P9b) and the programmer must provide the necessary amount of clock pulses to receive the entire response from the PE. COMMUNICATION INTERFACE AND PROTOCOL The ICSP/Enhanced ICSP interface is a 2-wire SPI, implemented using the PGECx and PGEDx pins. The PGECx pin is used as a clock input pin and the clock source must be provided by the programmer. The PGEDx pin is used for sending command data to, and receiving response data from, the PE. After the entire response is clocked out, the programmer should terminate the clock on PGECx until it is time to send another command to the Programming Executive. This protocol is shown in Figure 5-2. 5.1.2 For Enhanced ICSP, all serial data is transmitted on the falling edge of PGECx and latched on the rising edge of PGECx. All data transmissions are sent to the MSb first using 16-bit mode (see Figure 5-1). FIGURE 5-2: 3 P2 All communication is initiated by the programmer in the form of a command. Only one command at a time can be sent to the Programming Executive. In turn, the PE only sends one response to the programmer after receiving and processing a command. The PE command set is described in Section 5.2 “Programming Executive Commands”. The response set is described in Section 5.3 “Programming Executive Responses”. Note: 2 P1B The programmer and Programming Executive have a master-slave relationship, where the programmer is the master programming device and the Programming Executive is the slave. 5.1.1 PROGRAMMING EXECUTIVE SERIAL TIMING SPI RATE In Enhanced ICSP mode, the dsPIC33EPXXGS202 devices operate from the Internal Fast RC Oscillator (FRC), which has a nominal frequency of 7.3728 MHz. This oscillator frequency yields an effective system clock frequency of 3.6864 MHz. To ensure that the programmer does not clock too fast, it is recommended that a 1.8432 MHz clock be provided by the programmer. PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL Host Transmits Last Command Word 1 2 Programming Executive Processes Command 15 16 Host Clocks Out Response 1 2 15 16 1 2 15 16 PGECx PGEDx MSB X X X LSB P8 PGECx = Input PGEDx = Input Note: 1 0 P9a P9b PGECx = Input (Idle) PGEDx = Output MSB X X X LSB MSB X X X LSB PGECx = Input PGEDx = Output A delay of 25 ms is required between commands. 2014-2015 Microchip Technology Inc. DS70005192B-page 39 dsPIC33EPXXGS202 FAMILY 5.1.3 TIME-OUTS The Programming Executive uses no Watchdog Timer or time-out for transmitting responses to the programmer. If the programmer does not follow the flow control mechanism using PGECx, as described in Section 5.1.1 “Communication Interface and Protocol”, it is possible that the Programming Executive will behave unexpectedly while trying to send a response to the programmer. Since the PE has TABLE 5-1: Opcode no time-out, it is imperative that the programmer correctly follows the described communication protocol. As a safety measure, the programmer should use the command time-outs identified in Table 5-1. If the command time-out expires, the programmer should reset the PE and start programming the device again. PROGRAMMING EXECUTIVE COMMAND SET Mnemonic Length (16-bit words) Time-out 1 1 ms Description 0x0 SCHECK 0x1 Reserved N/A N/A — 0x2 READP 4 1 ms/row Read ‘N’ 24-bit instruction words of the user Flash memory, Configuration Word or Device ID register, starting from the specified address. 0x3 PROG2W 6 5 ms 0x4 Reserved N/A N/A This command is reserved; it will return a NACK. 0x5 PROGP 99 5 ms Program 64 words of program memory at the specified starting address, then verify. 0x6 Reserved N/A N/A This command is reserved; it will return a NACK. 0x7 ERASEB 0x8 Reserved 0x9 ERASEP 0xA Reserved 0xB 0xC 0xD Reserved 0xE QBLANK 1 125 ms N/A N/A Sanity check. Program a double instruction word of code memory at the specified address and verify. Bulk Erase user memory. This command is reserved; it will return a NACK. 3 25 ms N/A N/A QVER 1 1 ms Query the Programming Executive software version. CRCP 5 1s Perform a CRC-16 on the specified range of memory. DS70005192B-page 40 N/A N/A 5 700 ms Command to erase a page. This command is reserved; it will return a NACK. This command is reserved; it will return a NACK. Query to check whether the code memory is blank. 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 5.2 Programming Executive Commands 5.2.2 The Programming Executive command set is shown in Table 5-1. This table contains the opcode, mnemonic, length, time-out and description for each command. Functional details on each command are provided in the command descriptions (see Section 5.2.4 “Command Descriptions”). 5.2.1 When 24-bit instruction words are transferred across the 16-bit SPI interface, they are packed to conserve space using the format shown in Figure 3-7. This format minimizes traffic over the SPI and provides the Programming Executive with data that is properly aligned for performing Table Write operations. FIGURE 5-4: COMMAND FORMAT All Programming Executive commands have a general format, consisting of a 16-bit header and any required data for the command (see Figure 5-3). The 16-bit header consists of a 4-bit opcode field, which is used to identify the command, followed by a 12-bit command length field. FIGURE 5-3: 15 PACKED DATA FORMAT 0 Opcode 8 7 0 LSW1 MSB2 MSB1 LSW2 LSWx: Least Significant 16 bits of instruction word MSBx: Most Significant Byte of instruction word COMMAND FORMAT 12 11 15 PACKED INSTRUCTION WORD FORMAT Length Note: Command Data First Word (if required) When the number of instruction words transferred is odd, MSB2 is zero and LSW2 cannot be transmitted. • • Command Data Last Word (if required) The command opcode must match one of those in the command set. Any command that is received which does not match the list in Table 5-1 will return a “NACK” response (see Section 5.3.1.1 “Opcode Field”). The command length is represented in 16-bit words since the SPI operates in 16-bit mode. The Programming Executive uses the command length field to determine the number of words to read from the SPI port. If the value of this field is incorrect, the command will not be properly received by the Programming Executive. 2014-2015 Microchip Technology Inc. 5.2.3 PROGRAMMING EXECUTIVE ERROR HANDLING The Programming Executive will “NACK” all unsupported commands. Additionally, due to the memory constraints of the Programming Executive, no checking is performed on the data contained in the programmer command. It is the responsibility of the programmer to command the Programming Executive with valid command arguments or the programming operation may fail. Additional information on error handling is provided in Section 5.3.1.3 “QE_Code Field”. DS70005192B-page 41 dsPIC33EPXXGS202 FAMILY 5.2.4 COMMAND DESCRIPTIONS 5.2.4.2 All commands supported by the Programming Executive are described in Section 5.2.4.1 “SCHECK Command” through Section 5.2.4.9 “QBLANK Command”. 5.2.4.1 12 11 12 11 Length COMMAND DESCRIPTION Field Description Opcode 0x0 Length 0x1 0 Length N Addr_MSB Addr_LS Table 5-2 provides the description for the SCHECK command. TABLE 5-2: 8 7 Opcode Reserved 0 Opcode The SCHECK command instructs the Programming Executive to do nothing but generate a response. This command is used as a “Sanity Check” to verify that the Programming Executive is operational. Expected Response (2 words): 0x1000 0x0002 Note: 15 SCHECK Command 15 READP Command This instruction is not required for programming but is provided for development purposes only. Table 5-3 provides the description for the READP command. TABLE 5-3: COMMAND DESCRIPTION Field Description Opcode 0x2 Length 0x4 N Number of 24-bit instructions to read (maximum of 32768) Reserved 0x0 Addr_MSB MSB of 24-bit source address Addr_LS Least Significant 16 bits of 24-bit source address The READP command instructs the Programming Executive to read N 24-bit words of code memory, Flash Configuration Words or Device ID registers, starting from the 24-bit address specified by Addr_MSB and Addr_LS. This command can only be used to read 24-bit data. All data returned in response to this command uses the packed data format described in Section 5.2.2 “Packed Data Format”. Expected Response (2 + 3 * N/2 words for N even): 0x1200 2 + 3 * N/2 Least Significant Program Memory Word 1 ... Least Significant Data Word N Expected Response (4 + 3 * (N – 1)/2 words for N odd): 0x1200 4 + 3 * (N – 1)/2 Least Significant Program Memory Word 1 ... MSB of Program Memory Word N (zero-padded) Note 1: Reading unimplemented memory will cause the Programming Executive to reset. Please ensure that only memory locations present on a particular device are accessed. 2: When the READP command is used to read Device ID registers, the upper byte (bits<23:16>) of each word returned by the Programming Executive should be ignored. DS70005192B-page 42 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 5.2.4.3 PROG2W Command 15 12 11 5.2.4.4 8 7 Opcode 0 15 12 11 8 7 Opcode Length Reserved PROGP Command Reserved Addr_MSB D_1 DataL_LS D_2 DataL_MSB ... DataH_LS Table 5-4 provides the description for the PROG2W command. TABLE 5-4: COMMAND DESCRIPTION Field Description Opcode 0x3 Length 0x6 Addr_MSB Addr_LS Addr_LS DataH_MSB 0 Length D_N Table 5-5 provides the description for the PROGP command. TABLE 5-5: COMMAND DESCRIPTION Field Description Opcode 0x5 DataL_MSB MSB of 24-bit data for low instruction word Length 0x63 Reserved 0x0 DataH_MSB MSB of 24-bit data for high instruction word Addr_MSB MSB of 24-bit destination address Addr_LS Least Significant 16 bits of 24-bit destination address Addr_MSB MSB of 24-bit destination address Addr_LS Least Significant 16 bits of 24-bit destination address D_1 16-bit Data Word 1 Least Significant 16 bits of 24-bit data for low instruction word D_2 16-bit Data Word 2 ... 16-bit Data Word 3 through 95 D_96 16-bit Data Word 96 DataL_LS DataH_LS Least Significant 16 bits of 24-bit data for high instruction word The PROG2W command instructs the Programming Executive to program two instruction words of code memory (6 bytes) to the specified memory address. After the words have been programmed to code memory, the Programming Executive verifies the programmed data against the data in the command. Expected Response (2 words): 0x1300 0x0002 The PROGP command instructs the Programming Executive to program one row of code memory (64 instruction words) to the specified memory address. Programming begins with the row address specified in the command. The destination address should be a multiple of 0x80. The data to program the memory, located in command words, D_1 through D_96, must be arranged using the packed instruction word format illustrated in Figure 5-4. After all data has been programmed to code memory, the Programming Executive verifies the programmed data against the data in the command. Expected Response (2 words): 0x1500 0x0002 Note: 2014-2015 Microchip Technology Inc. Refer to Table 2-2 for code memory size information. DS70005192B-page 43 dsPIC33EPXXGS202 FAMILY 5.2.4.5 ERASEB Command 15 12 11 5.2.4.7 8 7 0 Opcode Length QVER Command 15 12 11 0 Opcode Length Table 5-6 provides the description for the ERASEB command. Table 5-8 provides the description for the QVER command. TABLE 5-6: COMMAND DESCRIPTION TABLE 5-8: Field Description Field Opcode 0x7 Length 0x1 Expected Response (2 words): 0x1700 0x0002 5.2.4.6 ERASEP Command 15 12 11 8 7 Opcode 0 Length Addr_MSB NUM_PAGES 0xB 0x1 The QVER command queries the version of the Programming Executive software stored in test memory. The “version.revision” information is returned in the response’s QE_Code, using a single byte with the following format: main version in upper nibble and a revision in the lower nibble (i.e., 0x23 means Version 2.3 of the Programming Executive software). Expected Response (2 words): 0x1BMN (where “MN” stands for version M.N) 0x0002 5.2.4.8 CRCP Command 15 12 11 Addr_MSB Addr_LSW Reserved COMMAND DESCRIPTION Description 0 Length Reserved Table 5-7 provides the description for the ERASEP command. Field 8 7 Opcode Addr_LS TABLE 5-7: Description Opcode Length The ERASEB command instructs the Programming Executive to perform a Bulk Erase of the user Flash memory. COMMAND DESCRIPTION Size_MSB Size_LSW Opcode 0x9 Table 5-9 provides the description for the CRCP command. Length 0x3 TABLE 5-9: COMMAND DESCRIPTION NUM_PAGE S Up to 255 Field Description Addr_MSB Most Significant Byte of the 24-bit address Addr_LS Least Significant 16 bits of the 24-bit address Opcode Length Addr_MSB Addr_LSW Size Ch 5h Most Significant Byte of 24-bit address Least Significant 16 bits of 24-bit address Number of 24-bit locations (address range divided by 2) The ERASEP command instructs the Programming Executive to Page Erase [NUM_PAGES] of code memory. The code memory must be erased at an “even” 512 instruction word address boundary. Expected Response (2 words): 0x1900 0x0002 The CRCP command performs a CRC-16 on the range of memory specified. This command can substitute for a full chip verify. Data is shifted in a packed method as shown in Figure 5-4, byte-wise, Least Significant Byte (LSB) first. Example: CRC-CCITT-16 with test data of “123456789” becomes 29B1h Expected Response (3 words): QE_Code: 0x1C00 Length: 0x0003 CRC Value: 0xXXXX DS70005192B-page 44 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 5.2.4.9 5.3 QBLANK Command 15 12 11 0 Opcode Length Reserved Size_MSB Size_LSW Reserved Addr_MSB Addr_LSW Table 5-10 provides the description for the QBLANK command. TABLE 5-10: Programming Executive Responses COMMAND DESCRIPTION Field Description Opcode 0xE Length 0x5 Size Length of program memory to check (in 24-bit words) + Addr_MS Addr_MSB Most Significant Byte of the 24-bit address Addr_LSW Least Significant 16 bits of the 24-bit address The QBLANK command queries the Programming Executive to determine if the contents of code memory are blank (contains all ‘1’s). The size of code memory to check must be specified in the command. The Blank Check for code memory begins at [Addr] and advances toward larger addresses for the specified number of instruction words. The Programming Executive sends a response to the programmer for each command that it receives. The response indicates if the command was processed correctly. It includes any required response data or error data. The Programming Executive response set is shown in Table 5-11. This table contains the opcode, mnemonic and description for each response. The response format is described in Section 5.3.1 “Response Format”. TABLE 5-11: Opcode Mnemonic PASS Command successfully processed 0x2 FAIL Command unsuccessfully processed 0x3 NACK Command not known 5.3.1 RESPONSE FORMAT All Programming Executive responses have a general format, consisting of a two-word header and any required data for the command. 15 12 11 Opcode The QBLANK command does not check the system operation Configuration bits, since these bits are not set to ‘1’ when a Chip Erase is performed. 2014-2015 Microchip Technology Inc. 8 7 0 Last_Cmd QE_Code Length D_1 (if applicable) Expected Response (2 words for blank device): 0x1EF0 0x0002 Note: Description 0x1 QBLANK returns a QE_Code of F0h if the specified code memory is blank; otherwise, QBLANK returns a QE_Code of 0Fh. Expected Response (2 words for non-blank device): 0x1E0F 0x0002 PROGRAMMING EXECUTIVE RESPONSE OPCODES ... D_N (if applicable) Table 5-12 provides the description of the response format. TABLE 5-12: Field RESPONSE FORMAT DESCRIPTION Description Opcode Response opcode Last_Cmd Programmer command that generated the response QE_Code Query code or error code Length Response length in 16-bit words (includes 2 header words) D_1 First 16-bit data word (if applicable) D_N Last 16-bit data word (if applicable) DS70005192B-page 45 dsPIC33EPXXGS202 FAMILY 5.3.1.1 Opcode Field The opcode is a 4-bit field in the first word of the response. The opcode indicates how the command was processed (see Table 5-11). If the command was processed successfully, the response opcode is PASS. If there was an error in processing the command, the response opcode is FAIL and the QE_Code indicates the reason for the failure. If the command sent to the Programming Executive is not identified, the Programming Executive returns a NACK response. 5.3.1.2 TABLE 5-14: Last_Cmd Field The Last_Cmd is a 4-bit field in the first word of the response and indicates the command that the Programming Executive processed. Since the Programming Executive can only process one command at a time, this field is technically not required. However, it can be used to verify that the Programming Executive correctly received the command that the programmer transmitted. 5.3.1.3 When the Programming Executive processes any command other than a query, the QE_Code represents an error code. Supported error codes are shown in Table 5-14. If a command is successfully processed, the returned QE_Code is set to 0x0, which indicates that there is no error in the command processing. If the verify of the programming for the PROGW command fails, the QE_Code is set to 0x1. For all other Programming Executive errors, the QE_Code is 0x02. QE_Code Field The QE_Code is a byte in the first word of the response. This byte is used to return data for query commands and error codes for all other commands. When the Programming Executive processes one of the two query commands (QBLANK or QVER), the returned opcode is always PASS and the QE_Code holds the query response data. The format of the QE_Code for both queries is shown in Table 5-13. TABLE 5-13: QE_Code FOR QUERIES Query QE_Code FOR NON-QUERY COMMANDS QE_Code 0x0 Description No error 0x1 Verify failed 0x2 Other error 5.3.1.4 Response Length The response length indicates the length of the Programming Executive’s response in 16-bit words. This field includes the 2 words of the response header. With the exception of the response for the read commands, the length of each response is only 2 words. The response to the READP commands uses the packed instruction word format, described in Section 5.2.2 “Packed Data Format”. When reading an odd number of program memory words (N odd), the response to the READP command is (3 * (N + 1)/2 + 2) words. When reading an even number of program memory words (N even), the response to the READP command is (3 * N/2 + 2) words. QE_Code QBLANK 0x0F = Code memory is NOT blank 0xF0 = Code memory is blank QVER 0xMN, where Programming Executive Software Version = M.N (i.e., 0x32 means Software Version 3.2) DS70005192B-page 46 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 5.4 Note: 5.4.1 Programming the Programming Executive to Memory The Programming Executive can be obtained from each device page on the Microchip web site: www.microchip.com. OVERVIEW If it is determined that the Programming Executive is not present in the executive memory (as described in Section 4.2 “Confirming the Presence of the Programming Executive”), the Programming Executive must be programmed to executive memory. 5.4.2 ERASING EXECUTIVE MEMORY The procedure for erasing each page of executive memory is similar to that of erasing program memory and is shown in Figure 3-6. It consists of setting NVMCON to 4003h and then executing the programming cycle. Table 5-15 shows the ICSP programming process for erasing the executive code memory. Note: The Programming Executive memory must always be erased before it is programmed, as described in Figure 5-5. Figure 5-5 shows the high-level process of programming the Programming Executive into executive memory. First, the ICSP mode must be entered and the executive memory must be erased. Then, the Programming Executive is programmed and verified. Finally, ICSP mode is exited. FIGURE 5-5: HIGH-LEVEL PROGRAMMING EXECUTIVE PROGRAM FLOW Start Enter ICSP™ Mode Page Erase All Pages in Executive Memory Program the Programming Executive Read/Verify the Programming Executive Exit ICSP Mode End 2014-2015 Microchip Technology Inc. DS70005192B-page 47 dsPIC33EPXXGS202 FAMILY TABLE 5-15: SERIAL INSTRUCTION EXECUTION FOR ERASING ALL PAGES OF EXECUTIVE MEMORY Command (Binary) Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Set the NVMADRU/NVMADR register pair to point to the correct page of executive memory to be erased. 0000 0000 0000 0000 2xxxx3 2xxxx4 883953 883964 MOV MOV MOV MOV #DestinationAddress<15:0>, W3 #DestinationAddress<23:16>, W4 W3, NVMADR W4, NVMADRU Step 3: Set the NVMCON register to erase the first page of executive memory. 0000 0000 0000 0000 24003A 88394A 000000 000000 MOV MOV NOP NOP #0x4003, W10 W10, NVMCON MOV MOV MOV MOV BSET NOP NOP NOP #0x55, W1 W1, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Step 4: Initiate the erase cycle. 0000 0000 0000 0000 0000 0000 0000 0000 200551 883971 200AA1 883971 A8E729 000000 000000 000000 Step 5: Generate clock pulses for the Page Erase operation to complete until the WR bit is clear. 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 — 000000 803940 000000 887C40 000000 <VISI> 000000 000000 000000 040200 000000 000000 000000 — NOP MOV NVMCON, W0 NOP MOV W0, VISI NOP Clock out contents of VISI register. NOP NOP NOP GOTO 0x200 NOP NOP NOP Repeat until the WR bit is clear. Step 6: Repeat Steps 2-5 for all pages of executive memory. DS70005192B-page 48 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 5.4.3 PROGRAM THE PROGRAMMING EXECUTIVE Table 5-16 provides the ICSP programming processes for PE memory. To minimize programming time, the same packed data format that the PE uses is utilized. See Section 5.2 “Programming Executive Commands” for more details on the packed data format. Storing the PE to executive memory is similar to normal programming of code memory. The executive memory must first be erased and then programmed using two-word writes (two instruction words). The control flow for this method is summarized in Figure 5-6. FIGURE 5-6: PROGRAMMING EXECUTIVE PROGRAM FLOW Start Configure Device for Writes Programming Using 2 Write Latches Load Two Words into Write Latches Increment Write Pointer Initiate Write Sequence and Poll WR bit to be Cleared All Data Written? No Yes End 2014-2015 Microchip Technology Inc. DS70005192B-page 49 dsPIC33EPXXGS202 FAMILY TABLE 5-16: PROGRAMMING THE PROGRAMMING EXECUTIVE (TWO-WORD LATCH WRITES) Command (Binary) Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Initialize the TBLPAG register for writing to the latches. 0000 0000 200FAC 8802AC MOV MOV #0xFA, W12 W12, TBLPAG Step 3: Load W0:W2 with the next two packed instruction words to program. 0000 0000 0000 2xxxx0 2xxxx1 2xxxx2 MOV MOV MOV #<LSW0>, W0 #<MSB1:MSB0>, W1 #<LSW1>, W2 Step 4: Set the Read Pointer (W6) and the Write Pointer (W7), and load the write latches. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0300 000000 EB0380 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB0B96 000000 000000 CLR NOP CLR NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL.W NOP NOP W6 W7 [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6], [W7] Step 5: Set the NVMADRU/NVMADR register pair to point to the correct row. 0000 0000 0000 0000 2xxxx3 2xxxx4 883953 883964 MOV MOV MOV MOV #DestinationAddress<15:0>, W3 #DestinationAddress<23:16>, W4 W3, NVMADR W4, NVMADRU Step 6: Set the NVMCON register to program two instruction words. 0000 0000 0000 0000 0000 24001A 000000 88394A 000000 000000 DS70005192B-page 50 MOV NOP MOV NOP NOP #0x4001, W10 W10, NVMCON 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY TABLE 5-16: Command (Binary) PROGRAMMING THE PROGRAMMING EXECUTIVE (TWO-WORD LATCH WRITES) (CONTINUED) Data (Hex) Description Step 7: Initiate the write cycle. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 200551 883971 200AA1 883971 A8E729 000000 000000 000000 000000 000000 MOV MOV MOV MOV BSET NOP NOP NOP NOP NOP #0x55, W1 W1, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Step 8: Wait for program operation to complete and make sure the WR bit is clear. 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 — 000000 803940 000000 887C40 000000 <VISI> 000000 000000 000000 040200 000000 000000 000000 — NOP MOV NVMCON, W0 NOP MOV W0, VISI NOP Clock out contents of VISI register. NOP NOP NOP GOTO 0x200 NOP NOP NOP Repeat until the WR bit is clear. Step 9: Repeat Steps 3-8 until all code memory is programmed. 2014-2015 Microchip Technology Inc. DS70005192B-page 51 dsPIC33EPXXGS202 FAMILY 5.4.4 READING EXECUTIVE MEMORY Reading from executive memory is performed by executing a series of TBLRD instructions and clocking out the data using the REGOUT command. To minimize reading time, the same packed data format that the PE uses is utilized. See Section 5.2 “Programming Executive Commands” for more details on the packed data format. Table 5-17 provides the ICSP programming details for reading executive memory. TABLE 5-17: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 2: Initialize the TBLPAG register and the Read Pointer (W6) for the TBLRD instruction. 0000 0000 0000 200xx0 8802A0 2xxxx6 DS70005192B-page 52 MOV MOV MOV #<SourceAddress23:16>, W0 W0, TBLPAG #<SourceAddress15:0>, W6 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY TABLE 5-17: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED) Data (Hex) Description Step 3: Initialize the Write Pointer (W7) and store the next four locations of code memory to W0:W5. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EB0380 000000 BA1B96 000000 000000 000000 000000 000000 BADBB6 000000 000000 000000 000000 000000 BADBD6 000000 000000 000000 000000 000000 BA1BB6 000000 000000 000000 000000 000000 BA1B96 000000 000000 000000 000000 000000 BADBB6 000000 000000 000000 000000 000000 BADBD6 000000 000000 000000 000000 000000 BA0BB6 000000 000000 000000 000000 000000 CLR NOP TBLRDL NOP NOP NOP NOP NOP TBLRDH.B NOP NOP NOP NOP NOP TBLRDH.B NOP NOP NOP NOP NOP TBLRDL NOP NOP NOP NOP NOP TBLRDL NOP NOP NOP NOP NOP TBLRDH.B NOP NOP NOP NOP NOP TBLRDH.B NOP NOP NOP NOP NOP TBLRDL NOP NOP NOP NOP NOP 2014-2015 Microchip Technology Inc. W7 [W6], [W7++] [W6++], [W7++] [++W6], [W7++] [W6++], [W7++] [W6], [W7++] [W6++], [W7++] [++W6], [W7++] [W6++], [W7] DS70005192B-page 53 dsPIC33EPXXGS202 FAMILY TABLE 5-17: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY (CONTINUED) Data (Hex) Description Step 4: Output W0:W5 using the VISI register and REGOUT command. 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 0000 0000 0001 0000 887C40 000000 <VISI> 000000 887C41 000000 <VISI> 000000 887C42 000000 <VISI> 000000 887C43 000000 <VISI> 000000 887C44 000000 <VISI> 000000 887C45 000000 <VISI> 000000 MOV W0, VISI NOP Clock out contents of VISI register. NOP MOV W1, VISI NOP Clock out contents of VISI register. NOP MOV W2, VISI NOP Clock out contents of VISI register. NOP MOV W3, VISI NOP Clock out contents of VISI register. NOP MOV W4, VISI NOP Clock out contents of VISI register. NOP MOV W5, VISI NOP Clock out contents of VISI register. NOP Step 5: Reset the device internal PC. 0000 0000 0000 0000 0000 0000 0000 000000 000000 000000 040200 000000 000000 000000 NOP NOP NOP GOTO NOP NOP NOP 0x200 Step 6: Repeat Steps 3-5 until all desired code memory is read. DS70005192B-page 54 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 5.4.5 PROGRAMMING VERIFICATION FIGURE 5-7: The verification is performed by reading back the executive memory space and comparing it against the copy held in the programmer’s buffer. The verification process is shown in Figure 5-7. The lower word of the instruction is read, and then the lower byte of the upper word is read and compared against the instruction stored in the programmer’s buffer. Refer to Section 5.4.4 “Reading Executive Memory” for implementation details of reading executive memory. VERIFY PROGRAMMING EXECUTIVE MEMORY FLOW Start Set TBLPAG = 0 Read Low Word with Post-Increment Read High Byte with Post-Increment Does Instruction Word = Expected Data? No Yes No All Executive Memory Verified? Yes End 2014-2015 Microchip Technology Inc. Failure Report Error DS70005192B-page 55 dsPIC33EPXXGS202 FAMILY 6.0 DEVICE ID Table 6-1 lists the Device ID for each device. Table 6-2 lists the Device ID registers. The Device ID region of memory can be used to determine variant and manufacturing information about the chip. This region of memory is read-only and can also be read when code protection is enabled. TABLE 6-1: DEVICE IDs Device DEVID dsPIC33EP16GS202 0x6D01 dsPIC33EP32GS202 0x6D11 TABLE 6-2: Address Silicon Revision 0x4001 A1 DEVICE ID REGISTERS Name FF0000h DEVID FF0002h DEVREV 6.1 DEVREV Bit 15 14 13 12 11 Unique Device Identifier (UDID) All dsPIC33EPXXGS202 family devices are individually encoded during final manufacturing with a Unique Device Identifier or UDID. The UDID cannot be erased by a Bulk Erase command or any other user-accessible means. This feature allows for manufacturing traceability of Microchip Technology devices in applications where this is a requirement. It may also be used by the application manufacturer for any number of things that may require unique identification, such as: • Tracking the device • Unique serial number • Unique security key DS70005192B-page 56 10 9 8 7 6 5 4 3 2 1 0 DEVID Value DEVREV Value The UDID comprises five 24-bit program words. When taken together, these fields form a unique 120-bit identifier. The UDID is stored in five read-only locations, located between 0x800F00 and 0x800F08 in the device configuration space. Table 6-3 lists the addresses of the Device Identifier Words and shows their contents. TABLE 6-3: UDID ADDRESSES UDID Address Description UDID1 0x800F00 UDID Word 1 UDID2 0x800F02 UDID Word 2 UDID3 0x800F04 UDID Word 3 UDID4 0x800F06 UDID Word 4 UDID5 0x800F08 UDID Word 5 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY 7.0 CHECKSUM COMPUTATION Checksums for devices are 16 bits in size. The checksum is calculated by summing the following: All memory locations, including Configuration Words, are summed by adding all three bytes of each memory address. For certain Configuration Words, a read mask is used to ignore the bits which are reserved. • Contents of code memory locations • Contents of Configuration Words Table 7-1 is an example of the checksum calculation for the dsPIC33EP32GS202 devices. TABLE 7-1: CHECKSUM COMPUTATION EXAMPLE Device Read Code Protection Checksum Computation Disabled CFGB + SUM(0x000000:0x00577E) Reads of program memory return Enabled 0x0000 dsPIC33EP32GS202 Erased Value Value with 0xAAAAAA at 0x0 and Last Code Address 0xC2ED(1,2) 0xC0EF(1,2) 0x0000 0x0000 Item Description: SUM(a:b) = Byte sum of locations, a to b inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked) = Byte sum of ((FSEC & 0x008FEF) + (FBSLIM & 0x001FFF) + (FOSCSEL & 0x000087) + (FOSC & 0x0001E7) + (FWDT & 0x0003FF) + (FPOR & 0x000001) + (FICD & 0x0000A3) + (FDEVOPT & 0x000005) + (FALTREG & 0x000077) + (Reserved & 0x008000)) Note 1: For the checksum computation example, the Configuration bits are set to the recommended default value. 2: For the checksum computation example with read code protection disabled, the Configuration bits are set to the recommended default value, which is 0xFFFFFF for most Configuration registers. 2014-2015 Microchip Technology Inc. DS70005192B-page 57 dsPIC33EPXXGS202 FAMILY 8.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS Table 8-1 lists the AC/DC characteristics and timing requirements. TABLE 8-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS Standard Operating Conditions Operating Temperature: -40ºC to +85ºC. Programming at +25ºC is recommended. Param. Symbol No. Characteristic Min. Max. Units 3.60 V D111 VDD Supply Voltage During Programming 3.00 D113 IDDP Supply Current During Programming — 10 mA D114 IPEAK Instantaneous Peak Current During Start-up — 200 mA D031 VIL Input Low Voltage VSS 0.2 VDD V D041 VIH Input High Voltage 0.8 VDD VDD V D080 VOL Output Low Voltage — 0.4 V D090 VOH Output High Voltage 2.4 — V D012 CIO Capacitive Loading on I/O Pin (PGEDx) — 50 pF P1 TPGC Serial Clock (PGECx) Period (ICSP™) 200 — ns P1 TPGC Serial Clock (PGECx) Period (Enhanced ICSP) 500 — ns P1A TPGCL Serial Clock (PGECx) Low Time (ICSP) 80 — ns P1A TPGCL Serial Clock (PGECx) Low Time (Enhanced ICSP) 200 — ns P1B TPGCH Serial Clock (PGECx) High Time (ICSP) 80 — ns P1B TPGCH Serial Clock (PGECx) High Time (Enhanced ICSP) 200 — ns P2 TSET1 Input Data Setup Time to Serial Clock 15 — ns P3 THLD1 Input Data Hold Time from PGECx 15 — ns P4 TDLY1 Delay Between 4-Bit Command and Command Operand 40 — ns P4A TDLY1A Delay Between Command Operand and Next 4-Bit Command 40 — ns P5 TDLY2 Delay Between Last PGECx of Command to First PGECx of Read of Data Word 20 — ns P6 TSET2 VDD Setup Time to MCLR 100 — ns P7 THLD2 Input Data Hold Time from MCLR 50 — ms P8 TDLY3 Delay Between Last PGECx of Command Byte to PGEDx by PE 12 — s Note 1: 2: 3: Conditions Normal Programming(1) VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. Time depends on the FRC accuracy and the value of the FRC Oscillator Tuning register. Refer to the “Electrical Characteristics” chapter in the specific device data sheet. This time applies to Program Memory Words, Configuration Words and User ID Words. DS70005192B-page 58 2014-2015 Microchip Technology Inc. dsPIC33EPXXGS202 FAMILY TABLE 8-1: AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS (CONTINUED) Standard Operating Conditions Operating Temperature: -40ºC to +85ºC. Programming at +25ºC is recommended. Param. Symbol No. Characteristic Min. Max. Units Conditions P9A TDLY4 Programming Executive Command Processing Time 10 — s P9B TDLY5 Delay Between PGEDx by Programming Executive to PGEDx Released by Programming Executive 15 23 s P10 TDLY6 PGECx Low Time After Programming 400 — ns P11 TDLY7 Bulk Erase Time — 70 ms P12 TDLY8 Page Erase Time — — ms See Note 2 P13 TDLY9 Row Programming Time — — ms See Note 2 P13a TDLY10 Double-Word Programming Time — — s See Notes 2 and 3 P14 TR MCLR Rise Time to Enter ICSP mode — 1.0 s P15 TVALID Data Out Valid from PGECx 10 — ns P16 TDLY10 Delay Between Last PGECx and MCLR P17 THLD3 MCLR to VDD P18 TKEY1 P19 TKEY2 P21 TMCLRH MCLR High Time Note 1: 2: 3: 0 — s 100 — ns Delay from First MCLR to First PGECx for Key Sequence on PGEDx 1 — ms Delay from Last PGECx for Key Sequence on PGEDx to Second MCLR 25 — ns — 500 s See Note 2 VDD must also be supplied to the AVDD pins during programming. AVDD and AVSS should always be within ±0.3V of VDD and VSS, respectively. Time depends on the FRC accuracy and the value of the FRC Oscillator Tuning register. Refer to the “Electrical Characteristics” chapter in the specific device data sheet. This time applies to Program Memory Words, Configuration Words and User ID Words. 2014-2015 Microchip Technology Inc. DS70005192B-page 59 dsPIC33EPXXGS202 FAMILY APPENDIX A: REVISION HISTORY Revision A (July 2014) Original version of this programming specification created for the dsPIC33EPXXGS202 device family. Revision B (April 2015) Updated Figure 2-5, Figure 2-6, Table 2-4, Table 2-5, Table 7-1 and Table 8-1. Added numerous minor typographical edits throughout the document. DS70005192B-page 60 2014-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2014-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-63277-344-9 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2014-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. 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