RT9181

RT9181
150mA LDO Regulator with PGOOD
General Description
Features
The RT9181 is a low dropout voltage regulator with an
output 2% accuracy and supply a continuous 150mA
current within operating range from a +3V to +5.5V input.
The power good function monitors the output voltage
and indicates by pulling low the power good output (open
drain).
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Low Dropout Voltage Regulator
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Up to 150mA Output Current
Power Good (PGOOD) Function
Chip Enable/Shutdown Function
μA
Load Independent, Low Quiescent Current, 160μ
Current Limiting and Thermal Protection
Under Voltage Lockout (UVLO)
Low Variation Due to Load and Line Regulation
Output Stable with Low ESR Capacitors
SOT-23-5 Package
RoHS Compliant and 100% Lead (Pb)-Free
The RT9181 requires a small output capacitor with low
ESR for stabilizing output voltage. The device also
minimizes output overshoot during power up.
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The RT9181 uses an internal P-MOSFET as the pass
device, which consumes 160μA supply current
independent of load and dropout conditions. The EN pin
controls the output and consumes no input bias current.
Other features include current limiting, over temperature
protection, and under voltage lockout.
Ordering Information
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Applications
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Processor Power-Up Sequencing
Laptop, Notebook, and Palmtop Computers
Pin Configurations
RT9181-
(TOP VIEW)
Package Type
B : SOT-23-5
Lead Plating System
P : Pb Free
G : Green (Halogen Free and Pb Free)
VOUT
PGOOD
5
4
2
3
VIN GND EN
SOT-23-5
Output Voltage
Default : 1.2V
18 : 1.8V
Note :
Typical Application Circuit
Richtek products are :
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RoHS compliant and compatible with the current require10K
ments of IPC/JEDEC J-STD-020.
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
For marking information, contact our sales representative
directly or through a Richtek distributor located in your
area.
DS9181-16 April 2011
VIN
CIN
1uF
+
`
1
Chip Enable
3
VIN
PGOOD
EN
VOUT
GND
2
4
PGOOD
5
VOUT
COUT
1uF
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RT9181
Function Block Diagram
VIN
Shutdown
Control
EN
Undervoltage
Lockout
Current
Limit
Thermal
Control
Gate
Control
VREF
+
VOUT
-
Output Voltage
Detection
GOOD
Delay
Timer
PGOOD
Fault
Power Good
Control
GND
Functional Pin Description
Pin Name
Pin Function
VIN
Power Input Voltage
GND
Ground
EN
Chip Enable (Active High)
PGOOD
Power Good Indicator
VOUT
Output Voltage
Timing Diagram
90% max of VOUT (normal)
VPGOODH
VPGOODL
85% min of VOUT (normal)
tD (PG) 2.0ms typ.
VOUT
PGOOD
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DS9181-16 April 2011
RT9181
Absolute Maximum Ratings
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(Note 1)
Supply Input Voltage, VIN ------------------------------------------------------------------------------------------ 7V
Enable Input Voltage ------------------------------------------------------------------------------------------------ 7V
Power Good Output Voltage --------------------------------------------------------------------------------------- 7V
Power Dissipation, PD @ TA = 25°C
SOT-23-5 --------------------------------------------------------------------------------------------------------------- 0.4W
Package Thermal Resistance (Note 2)
SOT-23-5, θJA --------------------------------------------------------------------------------------------------------- 250°C/W
Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------- 260°C
Storage Temperature Range --------------------------------------------------------------------------------------- −65°C to 150°C
ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ------------------------------------------------------------------------------------------------ 200V
Recommended Operating Conditions
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(Note 4)
Supply Input Voltage ------------------------------------------------------------------------------------------------ 3V to 5.5V
Enable Input Voltage ------------------------------------------------------------------------------------------------ 0V to 5.5V
Junction Temperature Range -------------------------------------------------------------------------------------- −40°C to 110°C
Electrical Characteristics
(VIN = 5V, CIN = COUT = 1μF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Min
Typ
Max
−1.5
--
1.5
IOUT = 0.1mA, TA = 0°C to 70°C (Note 4)
−2
--
+2
ILIM
RLOAD = 1Ω
160
300
--
mA
IQ
IOUT = 0mA
90
160
250
μA
ΔV LINE
V IN = 3V to 5.5V, IOUT = 0.1mA
−0.3
--
+0.3
%
ΔV LOAD
IOUT = 0.1mA to 150mA
--
1.5
+3
%
Logic-Low
VIL
V IN = 3V to 5.5V, Shutdown
--
--
0.8
Logic-High
VIH
V IN = 3V to 5.5V, Enable
2.0
--
--
Output Voltage Accuracy
Current Limit
Quiescent Current
(Note 5)
Line Regulation
Load Regulation
EN Threshold
(Note 6)
ΔV OUT
Test Conditions
IOUT = 25mA
Unit
%
V
EN Input Bias Current
EN = GND or V IN
0
--
100
nA
Shutdown Current
EN = GND
0
0.01
1
μA
VPGOODL
Output falls % of VOUT (power NOT good)
85
--
--
%
VPGOODH
Output reaches % of VOUT, start delay
timer (power good)
--
--
90
%
VIN = 3.3V, IOL = 2mA, RDSON(max) = 75Ω
0
--
0.15
V
1
2
5
ms
--
1
--
%
Power Good Low Threshold
Power Good High Threshold
Power Good Output Logic Low VOL
Delay Time to Power Good
tD(PGOOD) See timing diagram
Power Up Overshoot
VPGOODL
Maximum voltage overshoot allowed on
output during power-up
To be continued
DS9181-16 April 2011
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RT9181
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Thermal Shutdown Temperature
T SD
110
140
--
°C
Thermal Shutdown Hysteresis
ΔT SD
--
20
--
°C
Power Supply Rejection Rate
PSRR
--
−62
--
dB
f = 100Hz, COUT = 1μF
Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θ JA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 3. Devices are ESD sensitive. Handling precaution recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Quiescent, or ground current, is the difference between input and output currents. It is defined by IQ = IIN - IOUT under no
load condition (IOUT = 0mA). The total current drawn from the supply is the sum of the load current plus the ground pin
current.
Note 6. Regulation is measured at constant junction temperature by using a 20ms current pulse. Devices are tested for load
regulation in the load range from 0.1mA to 150mA.
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DS9181-16 April 2011
RT9181
Typical Operating Characteristics
Output Voltage vs. Supply Voltage
1.210
1.205
1.205
Output Voltage (V)
Output Voltage (V)
Output Voltage vs. Temperature
1.210
1.200
1.195
1.200
1.195
VIN = 5V
IOUT = 0.1mA
IOUT = 0.1mA
1.190
1.190
-20
0
20
40
60
80
3.0
3.5
Current Limit vs. Temperature
4.5
5.0
5.5
6.0
Current Limit vs. Supply Voltage
400
400
350
350
Current Limit (mA)
Current Limit (mA)
4.0
Supply Voltage (V)
Temperature (°C)
300
250
300
250
VIN = 5V
200
200
-20
0
20
40
60
80
3
3.5
Temperature (°C)
4.5
5
5.5
6
Supply Voltage (V)
Quiescent Current vs. Supply Voltage
Quiescent Current vs. Temperature
180
180
175
175
Quiescent Current (uA)
Quiescent Current (uA)
4
170
165
160
155
170
165
160
155
VIN = 5V
150
3.0
150
3.5
4.0
4.5
5.0
Supply Voltage (V)
DS9181-16 April 2011
5.5
6.0
-20
0
20
40
60
80
Temperature (°C)
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RT9181
Line Transient Response
VIN = 4.5 to 5.5V
COUT = 1uF
IO = 10mA
40
Output Voltage
Deviation (mV)
Output Voltage
Deviation (mV)
Line Transient Response
20
0
2
0
-2
≈
≈
5.5
4.5
Input Voltage
Deviation (V)
-20
Input Voltage
Deviation (V)
VIN = 4.5 to 5.5V
COUT = 1uF
IO = 150mA
4
≈
≈
5.5
4.5
RT9181-18
RT9181-18
Time (1ms/Div)
Time (1ms/Div)
PGOOD Delay Time vs. Temperature
VIN = 5V
CIN = COUT = 1uF
IO = 5 to 150mA
100
50
0
-50
Load
Current (mA)
3.0
≈
≈
200
100
PGOOD
Delay
Time
(ms)
PG Delay
Time
(ms)
Output Voltage
Deviation (mV)
Load Transient Response
0
2.5
2.0
1.5
1.0
0.5
VIN = 5V
RT9181-18
0.0
-20
Time (1ms/Div)
0
20
40
60
80
Temperature (°C)
PGOOD Delay Time vs. Supply Voltage
UVLO Response at Power Up
Input
Voltage (V)
2.50
2.00
1.50
4
2
0
≈
≈
1.5
Output
Voltage (V)
PGOOD
Delay
Time
(ms)
PG Delay
Time
(ms)
3.00
1.00
0.50
1
0.5
0
COUT = 1uF
0.00
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Time (5ms/Div)
Supply Voltage (V)
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DS9181-16 April 2011
0
-5
≈
≈
1.2V
0.5
0
VIN = 5V
COUT = 1uF
Time (25us/Div)
DS9181-16 April 2011
(V)
PGOOD Voltage
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PGOOD Response vs. VOUT
Output Voltage
(V)
(V)
PGOOD Response at Power Down
Output Voltage
(V)
PGOOD Voltage
RT9181
10
5
0
≈
2ms
delay
≈
1
0.5
0
VIN = 5V
Time (1ms/Div)
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RT9181
Application Information
EN
Current Limit and Thermal Protection
The RT9181 is enabled by driving the EN input high, and
shutdown by pulling the input low. If this feature is not to
be used, the EN input should be tied to VIN to keep the
regulator enabled at all times (the EN input must not be
The RT9181 includes a current limit structure which
monitor and control the pass transistor's gate voltage
limiting the guaranteed maximum output current to
160mA minimum.
left floating).
Internal P-Channel Pass Transistor
The RT9181 features a P-Channel MOSFET pass
transistors. It provides several advantages over similar
designs using PNP pass transistors, including longer
battery life. The P-Channel MOSFET requires no base
drive, which reduces quiescent current considerably.
PNP-based regulators waste considerable current in
dropout when the pass transistor saturates, They also
use high base-drive currents under large loads. The
RT9181 does not suffer from these problems and
consume only 160μA of quiescent current whether in
dropout, light-load, or heavy-load applications.
Power Good
The power good output is an open-drain output. It is
designed essentially to work as a power-on reset
generator once the regulated voltage was up or a fault
condition. The output of the power good drives low when
a fault condition occurs. The power good output come
back up once the output has reached 90% of its nominal
value and a 2ms (typ.) delay has passed. See Timing
Diagram. The output voltage level will be drooped at the
fault conditions including current limit, thermal shutdown,
or shutdown and triggers the PGOOD detector to alarm
a fault condition. This output is fed into an on-board delay
circuitry that drives the open drain transistor to indicate
a fault.
Because at shutdown mode, a fault condition occurs by
pulling the PGOOD output low, it will sink a current from
the open drain and the external power. Selecting a
suitable pulling resistance will be well to control this
dissipated power.
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Thermal-overload protection limits total power dissipation
in the RT9181. When the junction temperature exceeds
TJ = +140°C, the thermal sensor signals the shutdown
logic turning off the pass transistor and allowing the IC to
cool. The thermal sensor will turn the pass transistor on
again after the IC's junction temperature cools by 20°C,
resulting in a pulsed output during continuous thermaloverload conditions. Thermal-overloaded protection is
designed to protect the RT9181 in the event of fault
conditions. Do not exceed the recommended maximum
junction-temperature rating of TJ = +110°C for continuous
operation. The output can be shorted to ground for and
indefinite amount of time without damaging the part by
cooperation of current limit and thermal protection.
Operating Region and Power Dissipation
The maximum power dissipation of RT9181 depends on
the thermal resistance of the case and circuit board, the
temperature difference between the die junction and
ambient air, and the rate of air flow. The power dissipation
across the device is
P = IOUT (VIN
− VOUT)
The GND pin of the RT9181 performs the dual function
of providing an electrical connection to ground and
channeling heat away, Connect the GND pin to ground
using a large pad or ground plane.
Capacitor Selection and Regulator Stability
Like any low-dropout regulator, the external capacitors used
with the RT9181 must be carefully selected for regulator
stability and performance. Using a capacitor whose value
is ≥ 1μF on the RT9181 input and the amount of capacitance
can be increased without limit. The input capacitor must
be located a distance of not more than 0.5" from the input
pin of the IC and returned to a clean analog ground.
DS9181-16 April 2011
RT9181
Any good quality ceramic or tantalum can be used for this
capacitor. The capacitor with larger value and lower ESR
(equivalent series resistance) provides better PSRR and
line-transient response.
The output capacitor must meet both requirements for
minimum amount of capacitance and ESR in all LDO
applications. The RT9181 is designed specifically to work
with low-ESR ceramic output capacitor in space-saving
and performance consideration. Using a ceramic
capacitor whose value is at least 1μF with ESR is > 5mΩ
on the RT9181 output ensures stability. The RT9181 still
works well with output capacitor of other types due to the
wide stable ESR range. Output capacitor of larger
capacitance can reduce noise and improve load-transient
response, stability, and PSRR. The output capacitor
should be located not more than 0.5" from the VOUT pin
of the RT9181 and returned to a clean analog ground.
Reverse Current Path
The power transistor used in the RT9181 has an inherent
diode connected between each regulator input and output
(see Figure 1). If the output is forced above the input by
more than a diode-drop, this diode will become forward
biased and current will flow from the VOUT terminal to
VIN. This diode will also be turned on by abruptly stepping
the input voltage to a value below the output voltage. To
prevent regulator mis-operation, a Schottky diode could
be used in the applications where input/output voltage
conditions can cause the internal diode to be turned on
(see Figure 2). As shown, the Schottky diode is
connected in parallel with the internal parasitic diode and
prevents it from being turned on by limiting the voltage
drop across it to about 0.3V @ 100mA to prevent damage
to the part.
Note that some ceramic dielectrics exhibit large
capacitance and ESR variation with temperature. It may
be necessary to use 2.2μF or more to ensure stability at
temperatures below -10°C in this case. Also, tantalum
capacitors, 2.2μF or more may be needed to maintain
capacitance and ESR in the stable region for strict
application environment.
Tantalum capacitors maybe suffer failure due to surge
current when it is connected to a low-impedance source
of power (like a battery or very large capacitor). If a
tantalum capacitor is used at the input, it must be
guaranteed to have a surge current rating sufficient for
the application by the manufacturer.
Load-Transient Considerations
Figure 1
VIN
VOUT
Figure 2
The RT9181 load-transient response graphs show two
components of the output response: a DC shift from the
output impedance due to the load current change, and
the transient response. The DC shift is quite small due
to the excellent load regulation of the IC. Typical output
voltage transient spike for a step change in the load
current from 0mA to 50mA is tens mV, depending on the
ESR and ESL of the output capacitor. Increasing the
output capacitor's value and decreasing the ESR and ESL
attenuates the overshoot.
DS9181-16 April 2011
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RT9181
Outline Dimension
H
D
L
B
C
b
A
A1
e
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.889
1.295
0.035
0.051
A1
0.000
0.152
0.000
0.006
B
1.397
1.803
0.055
0.071
b
0.356
0.559
0.014
0.022
C
2.591
2.997
0.102
0.118
D
2.692
3.099
0.106
0.122
e
0.838
1.041
0.033
0.041
H
0.080
0.254
0.003
0.010
L
0.300
0.610
0.012
0.024
SOT-23-5 Surface Mount Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
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DS9181-16 April 2011