30 V, 7.5 MHz, Low Bias Current, Single-Supply, RRO, Precision Op Amp ADA4622-2 Data Sheet PIN CONFIGURATION Next generation of the AD822 Wide bandwidth: 8 MHz typical High slew rate: +23 V/µs/−18 V/µs typical Low input bias current: ±10 pA maximum at TA = 25°C Low offset voltage A grade: ±0.8 mV maximum at TA = 25°C B grade: ±0.35 mV maximum at TA = 25°C Low offset voltage drift A grade: ±2 µV/°C typical, ±15 µV/°C maximum B grade: ±2 µV/°C typical, ±5 µV/°C maximum Input voltage range includes Pin V− Rail-to-rail output Input electromagnetic interference (EMI) filters 90 dB typical at f = 1000 MHz and f = 2400 MHz Industry-standard package and pinouts OUT A 1 8 V+ –IN A 2 ADA4622-2 7 OUT B +IN A 3 TOP VIEW (Not to Scale) 6 –IN B 5 +IN B V– 4 13502-001 FEATURES Figure 1. 8-Lead MSOP (RM Suffix) Pin Configuration (See the Pin Configurations and Function Descriptions Section for Additional Pin Configurations) APPLICATIONS High output impedance sensor interfaces Photodiode sensor interfaces Transimpedance amplifiers ADC drivers Precision filters and signal conditioning GENERAL DESCRIPTION The ADA4622-2 is the next generation of the AD822 singlesupply, rail-to-rail output (RRO), precision junction field effect transistors (JFET) input op amp. The ADA4622-2 includes many improvements that make it desirable as an upgrade without compromising the flexibility and ease of use that makes the AD822 useful for a wide variety of applications. The input voltage range includes the negative supply and the output swings rail-to-rail. Input EMI filters are added to increase the signal robustness in the face of closely located switching noise sources. The speed in terms of bandwidth and slew rate is increased along with a strong output drive to improve settling time performance and enable the device to drive the inputs of modern single-ended, successive approximation register (SAR) analog-to-digital converters (ADCs). Rev. A Voltage noise is reduced; broadband noise is reduced by 25% and 1/f is reduced by half while keeping the supply current the same as the AD822. DC precision in the ADA4622-2 improved from the AD822 with half the offset and a maximum thermal drift specification added to the ADA4622-2. The commonmode rejection ratio (CMRR) is improved from the AD822 to make the ADA4622-2 more suitable when used in noninverting gain and difference amplifier configurations. The ADA4622-2 is specified for operation over the extended industrial temperature range of −40°C to +125°C and operates from 5 V to 30 V with specifications at +5 V, ±5 V, and ±15 V. The ADA4622-2 is available in 8-lead SOIC, 8-lead MSOP, and 8-lead LFCSP packages. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. 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Technical Support www.analog.com ADA4622-2 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Typical Performance Characteristics ........................................... 11 Applications ....................................................................................... 1 Theory Of Operation ..................................................................... 23 Pin Configuration ............................................................................. 1 Input Characteristics .................................................................. 23 General Description ......................................................................... 1 Output Characteristics............................................................... 24 Revision History ............................................................................... 2 Applications Information .............................................................. 25 Specifications..................................................................................... 3 Recommended Power Solution ................................................ 25 Electrical Characteristics, VSY = ±15 V ...................................... 3 Maximum Power Dissipation ................................................... 25 Electrical Characteristics, VSY = ±5 V ........................................ 5 Second-Order Low-Pass Filter.................................................. 25 Electrical Characteristics, VSY = 5 V .......................................... 7 Wideband Photodiode Preamplifier ........................................ 25 Absolute Maximum Ratings ............................................................ 9 Peak Detector .............................................................................. 28 Thermal Resistance ...................................................................... 9 Outline Dimensions ....................................................................... 29 ESD Caution .................................................................................. 9 Ordering Guide .......................................................................... 30 Pin Configurations and Function Descriptions ......................... 10 REVISION HISTORY 2/16—Rev. 0 to Rev. A Added 8-Lead LFCSP .................................................................Universal Changes to General Description Section............................................ 1 Changes to Settling Time to 0.1% Parameter and Settling Time to 0.01% Parameter, Table 1 .............................................................4 Changes to Table 5 .............................................................................9 Added Pin Configurations and Function Descriptions Section, Figure 2, Figure 3, Table 6, Figure 4, and Table 7; Renumbered Sequentially ...................................................................................... 10 Changes to Figure 9.......................................................................... 11 Changes to Input Characteristics Section ....................................... 23 Changes to Recommended Power Solution Section ..................... 25 Changes to Wideband Photodiode Preamplifier Section .............. 26 Change to Figure 85 ......................................................................... 26 Change to Figure 86 ......................................................................... 27 Updated Outline Dimensions ......................................................... 29 Changes to Ordering Guide............................................................. 30 10/15—Revision 0: Initial Version Rev. A | Page 2 of 30 Data Sheet ADA4622-2 SPECIFICATIONS ELECTRICAL CHARACTERISTICS, VSY = ±15 V Supply voltage (VSY) = ±15 V, common-mode voltage (VCM) = output voltage (VOUT) = 0 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage A Grade Symbol Test Conditions/Comments Min Typ Max Unit 0.04 ±0.8 ±2 ±0.35 ±0.8 ±1 mV mV mV mV mV ±15 ±5 ±10 ±1.5 µV/°C µV/°C pA nA pA pA nA V VOS −40°C < TA < +125°C B Grade 0.04 −40°C < TA < +125°C Offset Voltage Match Offset Voltage Drift A Grade B Grade Input Bias Current ΔVOS/ΔT −40°C < TA < +125°C −40°C < TA < +125°C ±2 ±2 2 IB −40°C < TA < +125°C VCM = V− Input Offset Current −15 IOS ±10 ±0.5 (V+) − 1 −40°C < TA < +125°C Input Voltage Range Common-Mode Rejection Ratio A Grade IVR CMRR B Grade Large Signal Voltage Gain Input Capacitance Input Resistance OUTPUT CHARACTERISTICS Output Voltage High Low AVO CINDM CINCM RDIFF RCM VOH VOL Output Current Short-Circuit Current IOUT ISC Closed-Loop Output Impedance ZOUT (V−) − 0.2 VCM = V− to (V+) − 3 V −40°C < TA < +125°C VCM = V− to (V+) − 3 V −40°C < TA < +125°C RL = 10 kΩ, VOUT = −14.5 V to +14.5 V −40°C < TA < +125°C RL = 1 kΩ, VOUT = −14 V to +14 V −40°C < TA < +125°C Differential mode Common mode Differential mode Common mode 84 81 87 85 117 109 102 93 ISOURCE = 1 mA −40°C < TA < +125°C ISOURCE = 15 mA −40°C < TA < +125°C ISINK = 1 mA −40°C < TA < +125°C ISINK = 15 mA −40°C < TA < +125°C VDROPOUT < 1 V Sourcing Sinking f = 1 kHz, gain (AV) = 1 AV = 10 AV = 100 50 100 700 900 Rev. A | Page 3 of 30 100 dB dB dB dB dB dB dB dB pF pF Ω Ω 100 122 110 0.4 3.6 1013 1013 30 500 45 315 20 42 −51 0.1 0.4 3 65 120 450 750 mV mV mV mV mV mV mV mV mA mA mA Ω Ω Ω ADA4622-2 Parameter POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier Data Sheet Symbol Test Conditions/Comments Min Typ PSRR VSY = ±4 V to ±18 V −40°C < TA < +125°C 87 81 103 ISY 665 −40°C < TA < +125°C DYNAMIC PERFORMANCE Slew Rate SR Gain Bandwidth Product Unity-Gain Crossover −3 dB Bandwidth Phase Margin Settling Time to 0.1% GBP UGC −3 dB ФM tS Settling Time to 0.01% tS EMI REJECTION RATIO f = 1000 MHz f = 2400 MHz NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion + Noise Bandwidth (BW) = 80 kHz BW = 500 kHz MATCHING SPECIFICATIONS Maximum Offset Voltage over Temperature Offset Voltage Temperature Drift Input Bias Current CROSSTALK EMIRR eN p-p eN iN THD + N VOUT = ±12.5 V, RL = 2 kΩ, load capacitor (CL) = 100 pF, AV = 1 Low to high transition High to low transition AV = 100 AV = 1 AV = 1 VIN = 10 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 VIN = 10 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 VIN = 100 mV p-p 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 1 kHz AV = 1, f = 10 Hz to 20 kHz, input voltage (VIN) = 7 V rms at 1 kHz RL = 5 kΩ, VIN = 20 V p-p f = 1 kHz f = 100 kHz Rev. A | Page 4 of 30 Unit 700 725 dB dB µA µA 23 −18 8 7 15.5 53 1.5 V/µs V/µs MHz MHz MHz Degrees µs 2 µs 90 90 dB dB 0.75 30 15 12.5 12 0.8 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz fA/√Hz 0.0003 0.00035 % % 0.5 mV 2.5 0.5 CS Max −112 −72 5 µV/°C pA dB dB Data Sheet ADA4622-2 ELECTRICAL CHARACTERISTICS, VSY = ±5 V VSY = ±5 V, VCM = VOUT = 0 V, TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage A Grade Symbol Test Conditions/Comments Min Typ Max Unit 0.04 ±0.8 ±2 ±0.35 ±0.8 ±1 mV mV mV mV mV ±15 ±5 ±10 ±1.5 µV/°C µV/°C pA nA pA pA nA V VOS −40°C < TA < +125°C B Grade 0.04 −40°C < TA < +125°C Offset Voltage Match Offset Voltage Drift A Grade B Grade Input Bias Current ΔVOS/ΔT −40°C < TA < +125°C −40°C < TA < +125°C ±2 ±2 2 IB −40°C < TA < +125°C VCM = V− Input Offset Current −5 IOS ±10 ±0.5 (V+) − 1 −40°C < TA < +125°C Input Voltage Range Common-Mode Rejection Ratio A Grade IVR CMRR B Grade Large Signal Voltage Gain Input Capacitance Input Resistance OUTPUT CHARACTERISTICS Output Voltage High Low AVO CINDM CINCM RDIFF RCM VOH VOL Output Current Short-Circuit Current IOUT ISC Closed-Loop Output Impedance ZOUT (V−) − 0.2 VCM = V− to (V+) − 3 V −40°C < TA < +125°C VCM = V− to (V+) − 3 V −40°C < TA < +125°C RL = 10 kΩ, VOUT = −4.4 V to +4.4 V −40°C < TA < +125°C RL = 1 kΩ, VOUT = −4.4 V to +4.4 V −40°C < TA < +125°C Differential mode Common mode Differential mode Common mode 75 73 78 75 113 105 100 91 ISOURCE = 1 mA −40°C < TA < +125°C ISOURCE = 15 mA −40°C < TA < +125°C ISINK = 1 mA −40°C < TA < +125°C ISINK = 15 mA −40°C < TA < +125°C VDROPOUT < 1 V Sourcing Sinking f = 1 kHz, AV = 1 AV = 10 AV = 100 50 100 700 900 Rev. A | Page 5 of 30 91 dB dB dB dB dB dB dB dB pF pF Ω Ω 91 118 105 0.4 3.6 1013 1013 30 490 45 315 20 31 −40 0.1 0.4 4 65 120 450 750 mV mV mV mV mV mV mV mV mA mA mA Ω Ω Ω ADA4622-2 Parameter POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier Data Sheet Symbol Test Conditions/Comments Min Typ PSRR VSY = ±4 V to ±18 V −40°C < TA < +125°C 87 81 103 ISY 610 −40°C < TA < +125°C DYNAMIC PERFORMANCE Slew Rate SR Gain Bandwidth Product Unity-Gain Crossover −3 dB Bandwidth Phase Margin Settling Time to 0.1% GBP UGC −3 dB ФM tS Settling Time to 0.01% tS EMI REJECTION RATIO f = 1000 MHz f = 2400 MHz NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion + Noise BW = 80 kHz BW = 500 kHz MATCHING SPECIFICATIONS Maximum Offset Voltage over Temperature Offset Voltage Temperature Drift Input Bias Current CROSSTALK EMIRR eN p-p eN iN THD + N VOUT = ±3 V, RL = 2 kΩ, CL = 100 pF, AV = 1 Low to high transition High to low transition AV = 100 AV = 1 AV = 1 VIN = 8 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 VIN = 8 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 VIN = 100 mV p-p 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 1 kHz AV = 1, f = 10 Hz to 20 kHz, VIN = 1.5 V rms at 1 kHz RL = 5 kΩ, VIN = 6 V p-p f = 1 kHz f = 100 kHz Rev. A | Page 6 of 30 Unit 675 700 dB dB µA µA 21 −16 7.8 6.5 10 50 1.5 V/µs V/µs MHz MHz MHz Degrees µs 2 µs 90 90 dB dB 0.75 30 15 12.5 12 0.8 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz pA/√Hz 0.0005 0.0008 % % 0.5 mV 2.5 0.5 CS Max −112 −72 5 µV/°C pA dB dB Data Sheet ADA4622-2 ELECTRICAL CHARACTERISTICS, VSY = 5 V VSY = 5 V, VCM = 0 V, VOUT = VSY/2, TA = 25°C, unless otherwise noted. Table 3. Parameter INPUT CHARACTERISTICS Offset Voltage A Grade Symbol Test Conditions/Comments Min Typ Max Unit 0.04 ±0.8 ±2 ±0.35 ±0.8 ±1 mV mV mV mV mV ±15 ±5 ±10 ±1.5 ±10 ±0.5 (V+) − 1 µV/°C µV/°C pA nA pA nA V VOS −40°C < TA < +125°C B Grade 0.04 −40°C < TA < +125°C Offset Voltage Match Offset Voltage Drift A Grade B Grade Input Bias Current ΔVOS/ΔT −40°C < TA < +125°C −40°C < TA < +125°C ±2 ±2 2 IB −40°C < TA < +125°C Input Offset Current IOS Input Voltage Range Common-Mode Rejection Ratio A Grade IVR CMRR −40°C < TA < +125°C B Grade Large Signal Voltage Gain Input Capacitance Input Resistance OUTPUT CHARACTERISTICS Output Voltage High Low AVO CINDM CINCM RDIFF RCM VOH VOL Output Current Short-Circuit Current IOUT ISC Closed-Loop Output Impedance ZOUT POWER SUPPLY Power Supply Rejection Ratio Supply Current per Amplifier PSRR (V−) − 0.2 VCM = V− to (V+) − 3 V −40°C < TA < +125°C VCM = V− to (V+) − 3 V −40°C < TA < +125°C RL = 10 kΩ to V−, VOUT = 0.2 V to 4.6 V −40°C < TA < +125°C RL = 1 kΩ to V−, VOUT = 0.2 V to 4.6 V −40°C < TA < +125°C Differential mode Common mode Differential mode Common mode 70 67 73 70 110 99 96 87 ISOURCE = 1 mA −40°C < TA < +125°C ISOURCE = 15 mA −40°C < TA < +125°C ISINK = 1 mA −40°C < TA < +125°C ISINK = 15 mA −40°C < TA < +125°C VDROPOUT < 1 V Sourcing Sinking f = 1 kHz, AV = 1 AV = 10 AV = 100 50 100 700 900 VSY = 4 V to 15 V −40°C < TA < +125°C 80 74 ISY 87 87 115 104 0.4 3.6 1013 1013 30 500 45 310 Rev. A | Page 7 of 30 65 120 450 750 20 27 −35 0.1 0.6 5 95 600 −40°C < TA < +125°C dB dB dB dB dB dB dB dB pF pF Ω Ω 650 675 mV mV mV mV mV mV mV mV mA mA mA Ω Ω Ω dB dB µA µA ADA4622-2 Parameter DYNAMIC PERFORMANCE Slew Rate Data Sheet Symbol Test Conditions/Comments SR VOUT = 0.5 V to 3.5 V, RL = 2 kΩ, CL = 100 pF, AV = 1 Low to high transition High to low transition AV = 100 AV = 1 AV = 1 Gain Bandwidth Product Unity-Gain Crossover −3 dB Bandwidth Phase Margin Settling Time to 0.1% GBP UGC −3 dB ФM tS Settling Time to 0.01% tS EMI REJECTION RATIO f = 1000 MHz f = 2400 MHz NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density Total Harmonic Distortion + Noise BW = 80 kHz BW = 500 kHz MATCHING SPECIFICATIONS Maximum Offset Voltage over Temperature Offset Voltage Temperature Drift Input Bias Current CROSSTALK EMIRR eN p-p eN iN THD + N VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 VIN = 4 V step, RL = 2 kΩ, CL = 15 pF, AV = −1 VIN = 100 mV p-p 0.1 Hz to 10 Hz f = 10 Hz f = 100 Hz f = 1 kHz f = 10 kHz f = 1 kHz AV = 1, f = 10 Hz to 20 kHz, VIN = 0.5 V rms at 1 kHz Min Typ RL = 5 kΩ, VIN = 3 V p-p f = 1 kHz f = 100 kHz Rev. A | Page 8 of 30 Unit 20 −15 7.2 6 9 50 1.5 V/µs V/µs MHz MHz MHz Degrees µs 2.0 µs 90 90 dB dB 0.75 30 15 12.5 12 0.8 µV p-p nV/√Hz nV/√Hz nV/√Hz nV/√Hz pA/√Hz 0.0025 0.0025 % % 0.5 mV 2.5 0.5 CS Max −112 −72 5 µV/°C pA dB dB Data Sheet ADA4622-2 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Supply Voltage Input Voltage Differential Input Voltage Storage Temperature Range Operating Temperature Range Junction Temperature Range Lead Temperature, Soldering (10 sec) ESD Rating, Human Body Model (HBM) Rating 36 V (V−) − 0.3 V to (V+) + 0.2 V 36 V −65°C to +150°C −40°C to +125°C −65°C to +150°C 300°C 4 kV Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Close attention to PCB thermal design is required. Table 5. Thermal Resistance1 Package Type 8-Lead SOIC 1-Layer JEDEC Board 2-Layer JEDEC Board 8-Lead MSOP 1-Layer JEDEC Board 2-Layer JEDEC Board 8-Lead LFCSP 1-Layer JEDEC Board 2-Layer JEDEC Board 2-Layer JEDEC Board with 2 × 2 Vias 1 θJA Unit 180 120 °C/W °C/W 265 185 °C/W °C/W 272 145 55 °C/W °C/W °C/W Thermal impedance simulated values are based on a JEDEC thermal test board. See JEDEC JESD51. ESD CAUTION Rev. A | Page 9 of 30 ADA4622-2 Data Sheet PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS –IN A 2 ADA4622-2 7 +IN A 3 TOP VIEW (Not to Scale) 6 –IN B 5 +IN B V– 4 ADA4622-2 V+ OUT A 1 OUT B –IN A 2 +IN A 3 V– Figure 2. 8-Lead MSOP Pin Configuration 4 8 V+ 7 OUT B TOP VIEW (Not to Scale) 6 –IN B 5 +IN B 13502-201 8 13502-101 OUT A 1 Figure 3. 8-Lead SOIC Pin Configuration Table 6. 8-Lead SOIC and 8-Lead MSOP Pin Function Descriptions Mnemonic OUT A −IN A +IN A V− +IN B −IN B OUT B V+ Description Output, Channel A Inverting Input, Channel A Noninverting Input, Channel A Negative Supply Voltage Noninverting Input, Channel B Inverting Input, Channel B Output, Channel B Positive Supply Voltage OUT A 1 –IN A 2 +IN A 3 V– 4 8 V+ ADA4622-2 TOP VIEW (Not to Scale) 7 OUT B 6 –IN B 5 +IN B NOTES 1. IT IS RECOMMENDED TO CONNECT THE EXPOSED PAD TO THE V+ PIN. 13502-102 Pin No. 1 2 3 4 5 6 7 8 Figure 4. 8-Lead LFCSP Pin Configuration Table 7. 8-Lead LFCSP Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 EPAD Mnemonic OUT A −IN A +IN A V− +IN B −IN B OUT B V+ EPAD Description Output, Channel A. Inverting Input, Channel A. Noninverting Input, Channel A. Negative Supply Voltage. Noninverting Input, Channel B. Inverting Input, Channel B. Output, Channel B. Positive Supply Voltage. Exposed Pad. It is recommended to connect the exposed pad to the V+ pin. Rev. A | Page 10 of 30 Data Sheet ADA4622-2 TYPICAL PERFORMANCE CHARACTERISTICS TA = 25°C, unless otherwise noted. 20 160 VSY = ±15V 16 NUMBER OF AMPLIFIERS NUMBER OF AMPLIFIERS 18 VCM = 0V VOUT = 0V 140 120 100 80 60 40 14 12 10 8 6 13502–002 0 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 13502-005 4 20 2 0 –10.0 1.00 –7.5 –5.0 –2.5 5.0 7.5 10.0 25 100 VSY = ±5V VCM = 0V VOUT = 0V 90 20 NUMBER OF AMPLIFIERS 80 70 60 50 40 30 15 10 5 13502–003 20 10 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 0 –10.0 1.00 13502-006 NUMBER OF AMPLIFIERS 2.5 Figure 8. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +85°C), VSY = ±15 V Figure 5. Input Offset Voltage (VOS) Distribution, VSY = ±15 V 0 –1.00 0 TCVOS (µV/°C) VOS (mV) –7.5 –5.0 –2.5 0 2.5 5.0 7.5 10.0 TCVOS (µV/°C) VOS (mV) Figure 9. Input Offset Voltage Drift (TCVOS) Distribution (−40°C to +125°C), VSY = ±5 V Figure 6. Input Offset Voltage (VOS) Distribution, VSY = ±5 V 1000 100 VSY = ±15V VCM = 0V VOUT = 2.5V 90 500 70 VOS (µV) 60 50 0 40 30 –500 10 0 –1.00 –0.75 –0.50 –0.25 0 0.25 0.50 0.75 –1000 –15 1.00 –10 –5 0 5 10 15 VCM (V) VOS (mV) Figure 7. Input Offset Voltage (VOS) Distribution, VSY = 5 V 13502-008 20 13502–004 NUMBER OF AMPLIFIERS 80 Figure 10. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±15 V Rev. A | Page 11 of 30 ADA4622-2 Data Sheet 1000 160 VSY = ±5V NUMBER OF AMPLIFIERS 500 VOS (µV) VCM = 0V VOUT = 0V 140 0 120 100 80 60 40 –500 –1000 –5 –4 –3 –2 –1 0 1 2 3 4 0 –3 13502–015 13502-009 20 –2 –1 5 VCM (V) 0 IB (pA) 1 Figure 14. Input Bias Current (IB) Distribution, VSY = ±5 V Figure 11. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = ±5 V 1000 120 VSY = 5V VCM = 0V VOUT = 2.5V NUMBER OF AMPLIFIERS 100 500 VOS (µV) 3 2 0 –500 80 60 40 –1000 0 0.5 1.0 1.5 2.0 2.5 3.0 VCM (V) 3.5 4.0 4.5 0 –3 5.0 13502–016 13502-010 20 –2 –1 0 1 2 3 IB (pA) Figure 12. Input Offset Voltage (VOS) vs. Common-Mode Voltage (VCM), VSY = 5 V Figure 15. Input Bias Current (IB) Distribution, VSY = 5 V 10 160 VSY = ±15V VCM = 0V VOUT = 0V 0 120 IB (pA) 100 80 –10 60 40 –20 20 –2 –1 0 IB (pA) 1 2 Figure 13. Input Bias Current (IB) Distribution, VSY = ±15 V –30 –15 3 13502-017 0 –3 13502–014 NUMBER OF AMPLIFIERS 140 –10 –5 0 5 10 15 VCM (V) Figure 16. Input Bias Current (IB) vs. Input Common-Mode Voltage (VCM), VSY = ±15 V Rev. A | Page 12 of 30 Data Sheet ADA4622-2 4 100 VSY = ±5V VSY = ±5V 10 0 1 –40°C +25°C +85°C +125°C 100m –4 10m 13502-018 –2 –6 –5 –4 –3 –2 –1 0 1 2 3 4 13502–021 VOL (V) IB (pA) 2 1m 5 1µ 10µ 100µ VCM (V) 1m 10m 100m ILOAD (A) Figure 17. Input Bias Current (IB) vs. Input Common-Mode Voltage (VCM), VSY = ±5 V Figure 20. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD) over Temperature, VSY = ±5 V 6 100 VSY = 5V VSY = 5V 4 10 1 0 –40°C +25°C +85°C +125°C VOL (V) IB (pA) 2 –2 100m –4 13502–019 –8 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 13502–022 10m –6 1m 5.0 1µ 10µ 100µ VCM (V) 1m 10m 100m ILOAD (A) Figure 18. Input Bias Current (IB) vs. Input Common-Mode Voltage (VCM), VSY = 5 V Figure 21. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD) over Temperature, VSY = 5 V 100 100 VSY = ±15V VSY = ±15V 10 10 1 100m 10m 10m 13502–020 100m 1m 1µ 10µ –40°C +25°C +85°C +125°C VOH (V) VOL (V) –40°C +25°C +85°C +125°C 100µ 1m 10m 13502–023 1 1m 1µ 100m 10µ 100µ 1m 10m 100m ILOAD (A) ILOAD (A) Figure 19. Output Voltage Low (VOL) to Supply Rail vs. Load Current (ILOAD) over Temperature, VSY = ±15 V Figure 22. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD) over Temperature, VSY = ±15 V Rev. A | Page 13 of 30 ADA4622-2 Data Sheet 10 225 120 180 80 135 60 90 40 45 20 0 –40°C +25°C +85°C +125°C 13502–024 10m 1m 10µ 100µ 1m 10m –45 –20 –90 –40 10 100m 100 1k ILOAD (A) 1M 10M 225 120 10 VSY = ±5V VSY = 5V 100 180 80 135 60 90 40 45 20 0 1 GAIN (dB) –40°C +25°C +85°C +125°C 100m 0 –45 –20 –90 13502–025 10m 1m 1µ –135 100M Figure 26. Open-Loop Gain and Phase vs. Frequency, VSY = ±15 V Figure 23. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD) over Temperature, VSY = ±5 V VOL (V) 100k 10k FREQUENCY (Hz) 10µ 100µ 1m 10m –40 10 100m 100 1k 100k 10k FREQUENCY (Hz) 1M 10M PHASE (Degrees) 1µ 0 13502-028 100m GAIN (dB) VOL (V) 1 13502-027 100 PHASE (Degrees) VSY = ±15V VSY = ±5V –135 100M ILOAD (A) Figure 27. Open-Loop Gain and Phase vs. Frequency, VSY = ±5 V Figure 24. Output Voltage High (VOH) to Supply Rail vs. Load Current (ILOAD) over Temperature, VSY = 5 V 225 120 140 VSY = ±15V VSY = ±5V VSY = 5V 130 100 180 80 135 60 90 40 45 20 0 GAIN (dB) 110 90 80 100 1k 10k 100k 0 –45 –20 –90 –40 10 LOAD RESISTANCE (kΩ) Figure 25. Open-Loop Gain (AVO) vs. Load Resistance 100 1k 100k 10k FREQUENCY (Hz) 1M 10M –135 100M Figure 28. Open-Loop Gain and Phase vs. Frequency, VSY = 5 V Rev. A | Page 14 of 30 13502-029 100 13502–026 GAIN (dB) 120 PHASE (Degrees) VSY = 5V Data Sheet ADA4622-2 60 1000 VSY = ±15V VSY = ±15V 50 100 AV = +100 OUTPUT IMPEDANCE (Ω) GAIN (dB) 40 30 AV = +10 20 10 AV = +1 0 10 GAIN = 100 1 GAIN = 10 0.1 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0.01 10 100M 100 13502-033 –20 10 GAIN = 1 13502-030 –10 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 29. Closed-Loop Gain vs. Frequency, VSY = ±15 V Figure 32. Output Impedance vs. Frequency, VSY = ±15 V 60 1000 VSY = ±5V VSY = ±5V 50 100 AV = +100 OUTPUT IMPEDANCE (Ω) GAIN (dB) 40 30 AV = +10 20 10 AV = +1 0 10 GAIN = 100 1 GAIN = 10 0.1 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0.01 10 100M 100 13502-034 –20 10 GAIN = 1 13502-031 –10 1k 10k 100k 1M 10M FREQUENCY (Hz) Figure 30. Closed-Loop Gain vs. Frequency, VSY = ±5 V Figure 33. Output Impedance vs. Frequency, VSY = ±5 V 60 1000 VSY = 5V VSY = 5V 50 OUTPUT IMPEDANCE (Ω) 30 AV = +10 20 10 AV = +1 0 10 GAIN = 100 1 GAIN = 10 0.1 –20 10 GAIN = 1 100 1k 10k 100k FREQUENCY (Hz) 1M 10M 0.01 10 100M 100 13502-035 –10 13502-032 GAIN (dB) 100 AV = +100 40 1k 10k 100k 1M FREQUENCY (Hz) Figure 31. Closed-Loop Gain vs. Frequency, VSY = 5 V Figure 34. Output Impedance vs. Frequency, VSY = 5 V Rev. A | Page 15 of 30 10M ADA4622-2 Data Sheet 120 120 VSY = ±15V VSY = ±15V 100 100 80 PSRR (dB) CMRR (dB) 80 60 60 +PSRR 40 –PSRR 40 20 20 100 1k 10k 100k 10M 1M –20 10 100M 13502-039 13502-036 0 10 0 100 1k FREQUENCY (Hz) Figure 35. CMRR vs. Frequency, VSY = ±15 V 1M 10M 100M Figure 38. PSRR vs. Frequency, VSY = ±15 V 120 140 VSY = ±5V VSY = ±5V 120 100 100 80 PSRR (dB) CMRR (dB) 100k 10k FREQUENCY (Hz) 80 60 60 +PSRR 40 20 0 0 10 13502-037 20 100 1k 10k 100k 10M 1M –20 10 100M 13502-040 –PSRR 40 100 1k FREQUENCY (Hz) Figure 36. CMRR vs. Frequency, VSY = ±5 V 100k 10k FREQUENCY (Hz) 1M 10M 100M Figure 39. PSRR vs. Frequency, VSY = ±5 V 120 100 VSY = 5V VSY = 5V 100 80 80 PSRR (dB) 40 60 –PSRR 40 20 20 100 1k 10k 100k 1M 10M –20 10 100M FREQUENCY (Hz) Figure 37. CMRR vs. Frequency, VSY = 5 V 13502-041 0 10 0 13502-038 CMRR (dB) +PSRR 60 100 1k 100k 10k FREQUENCY (Hz) 1M Figure 40. PSRR vs. Frequency, VSY = 5 V Rev. A | Page 16 of 30 10M 100M Data Sheet ADA4622-2 15 50 VSY = ±15V VSY = ±15V VIN = ±10V 45 10 40 5 VOLTAGE (V) 30 +OS –OS 25 20 0 –5 15 10 13502-042 –10 5 0 1 10 100 13502-045 OVERSHOOT (%) 35 –15 1000 0 1 2 3 4 5 6 7 8 9 10 TIME (µs) LOAD CAPACITANCE (pF) Figure 41. Small Signal Overshoot (OS) vs. Load Capacitance, VSY = ±15 V Figure 44. Large Signal Transient Response, VSY = ±15 V 4 50 VSY = ±5V 45 40 VSY = ±5V VIN = ±3V 2 VOLTAGE (V) OVERSHOOT (%) 35 30 +OS –OS 25 20 0 15 –2 5 0 1 10 100 13502-046 13502-043 10 –4 1000 0 1 2 3 4 5 6 7 8 9 10 TIME (µs) LOAD CAPACITANCE (pF) Figure 42. Small Signal Overshoot (OS) vs. Load Capacitance, VSY = ±5 V Figure 45. Large Signal Transient Response, VSY = ±5 V 4 60 VSY = 5V 50 VSY = 5V VIN = 0.5V TO 3.5V VOLTAGE (V) OVERSHOOT (%) 3 40 +OS –OS 30 2 20 1 0 1 10 100 13502-047 13502-044 10 0 1000 0 1 2 3 4 5 6 7 8 9 TIME (µs) LOAD CAPACITANCE (pF) Figure 43. Small Signal Overshoot (OS) vs. Load Capacitance, VSY = 5 V Rev. A | Page 17 of 30 Figure 46. Large Signal Transient Response, VSY = 5 V 10 ADA4622-2 Data Sheet 3 0.35 VSY = 5V VIN = 0.2V TO 0.3V 2 VSY = ±2.5V VIN = ±2V 0.30 VOLTAGE (V) VOLTAGE (V) 1 0 0.25 –1 0.20 –3 0 1 2 3 4 5 6 7 8 9 13502-051 13502-048 –2 0.15 10 0 1 2 3 4 5 6 7 8 9 10 TIME (µs) TIME (µs) Figure 47. Large Signal Transient Response, VSY = ±2.5 V Figure 50. Small Signal Transient Response, VSY = 5 V 20 5 4 VSY = ±15V VSY = ±15V VIN = ±50mV p-p 10 –5 0 –10 13502-049 –2 –4 0 1 2 3 4 5 6 7 8 9 –15 10 OUTPUT VOLTAGE (V) 0 0 –10 0 1 2 3 4 5 6 7 8 9 13502-052 INPUT VOLTAGE (V) VOLTAGE (V) 2 –20 10 TIME (µs) TIME (µs) Figure 48. Small Signal Transient Response, VSY = ±15 V Figure 51. Negative Overload Recovery, AV = −10, VSY = ±15 V 4 6 1 VSY = ±5V 1 0 0 1 2 3 4 5 6 7 8 9 10 TIME (µs) 0 3 –1 0 –2 –3 –3 0 1 2 3 4 5 6 7 8 9 –6 10 TIME (µs) Figure 49. Small Signal Transient Response, VSY = ±5 V Figure 52. Negative Overload Recovery, AV = −10, VSY = ±5 V Rev. A | Page 18 of 30 13502-053 INPUT VOLTAGE (V) 2 13502-050 VOLTAGE (V) 3 OUTPUT VOLTAGE (V) VSY = ±5V VIN = ±50mV p-p Data Sheet ADA4622-2 2 0.5 5 0.5 –1.0 –1 –1.5 –2.0 –2 0 1 2 3 4 5 6 7 8 9 –3 10 0 4 –0.5 3 –1.0 2 –1.5 1 –2.0 0 –2.5 2 1 0 5 4 3 7 6 –1 10 9 8 13502-057 0 INPUT VOLTAGE (V) –0.5 OUTPUT VOLTAGE (V) 1 13502-054 INPUT VOLTAGE (V) 0 OUTPUT VOLTAGE (V) VSY = ±2.5V VSY = ±2.5V TIME (µs) TIME (µs) Figure 53. Negative Overload Recovery, AV = −10, VSY = ±2.5 V Figure 56. Positive Overload Recovery, AV = −10, VSY = ±2.5 V 35 5 0.09 10 VSY = ±15V –10 –15 5 0 1 2 3 4 5 6 7 8 9 –5 10 0 0.07 -5 0.06 –10 0.05 –15 0.04 –20 0.03 –25 13502-058 15 INPUT VOLTAGE (V) –5 OUTPUT VOLTAGE (V) 25 13502-055 INPUT VOLTAGE (V) 0 VSY = ±15V VIN = ±5V OUTPUT VOLTAGE (V) 0.08 5 0.02 0 1 2 3 5 4 6 7 8 9 10 TIME (µs) TIME (µs) Figure 54. Positive Overload Recovery, AV = −10, VSY = ±15 V Figure 57. Positive Settling Time, AV = −10, VSY = ±15 V 0.09 8 12 1 VSY = ±5V –3 0 –4 0 1 2 3 4 5 6 7 8 9 –3 10 0.07 –4 0.06 –8 0.05 –12 0.04 –16 0.03 –20 0.02 0 1 2 3 4 5 6 7 8 9 10 TIME (µs) TIME (µs) Figure 55. Positive Overload Recovery, AV = −10, VSY = ±5 V Figure 58. Positive Settling Time, AV = −10, VSY = ±5 V Rev. A | Page 19 of 30 13502-059 3 0 INPUT VOLTAGE (V) –2 OUTPUT VOLTAGE (V) 6 13502-056 INPUT VOLTAGE (V) –1 VSY = ±5V VIN = ±4V OUTPUT VOLTAGE (V) 0.08 4 9 0 ADA4622-2 Data Sheet –2 0.03 –6 0.02 –8 0.01 –10 –12 OUTPUT VOLTAGE (V) –4 0 0 1 2 3 4 5 6 7 8 –0.01 10 9 0.01 VSY = 5V VIN = –0.5V TO –4.5V –4 0 –6 –0.01 –8 –0.02 –10 –0.03 –12 0 1 2 3 TIME (µs) –10 –0.05 –15 –0.06 –20 –0.07 –0.08 3 4 5 6 7 8 9 VOLTAGE NOISE DENSITY (nV/√Hz) –0.04 OUTPUT VOLTAGE (V) –5 13502-061 INPUT VOLTAGE (V) –0.03 2 8 9 –0.04 10 100 –0.02 0 1 7 10 13502-064 VSY = ±15V VIN = ±5V 0 6 Figure 62. Negative Setting Time, AV = −10, VSY = 5 V –0.01 10 –25 5 TIME (µs) Figure 59. Positive Settling Time, AV = −10, VSY = 5 V 5 4 1 1 10 10 TIME (µs) 100 1k 100k 10k FREQUENCY (Hz) Figure 60. Negative Setting Time, AV = −10, VSY = ±15 V 8 Figure 63. Voltage Noise Density, VSY = ±15 V 0 CH1 p-p = 776.0mV VSY = ±5V VIN = ±4V –0.02 –4 –0.03 –8 –0.04 –12 –0.05 –16 –0.06 –20 –0.07 0 1 2 3 4 5 6 7 8 9 1 10 13502-065 0 OUTPUT VOLTAGE (V) –0.01 13502-062 INPUT VOLTAGE (V) 4 CH1 200mV M1.00ms A CH1 –3.80MV TIME (µs) Figure 61. Negative Setting Time, AV = −10, VSY = ±5 V Figure 64. 0.1 Hz to 10 Hz Noise, VSY = ±15 V Rev. A | Page 20 of 30 OUTPUT VOLTAGE (V) 0.04 VSY = 5V VIN = –0.5V TO –4.5V 0.02 13502-063 0 13502-060 INPUT VOLTAGE (V) –2 0.05 INPUT VOLTAGE (V) 0 Data Sheet ADA4622-2 100 1.6 VSY = ±15V 10 1.2 –40°C +25°C +85°C +125°C 1 1 THD + N (%) SUPPLY CURRENT (mA) 1.4 0.8 0.6 0.1 BW = 500kHz 0.01 BW = 80kHz 0.4 13502-066 0 0 ±2 ±4 ±6 ±8 ±10 ±12 ±14 ±16 0.0001 0.001 ±18 13502-069 0.001 0.2 100 VSY VSY VSY VSY 1.5 = +5V = ±2.5V = ±5V = ±15V VSY = ±5V 10 1 1.3 0.1 1.2 0.01 1.1 0.001 –25 –10 5 20 35 50 65 80 95 110 BW = 500kHz BW = 80kHz 0.0001 0.001 125 13502-070 THD + N (%) 1.4 13502-067 SUPPLY CURRENT (mA) 10 Figure 68. THD + Noise vs. Amplitude, VSY = ±15 V 1.6 0.01 0.1 1 10 AMPLITUDE (V rms) TEMPERATURE (°C) Figure 66. Supply Current (ISY) vs. Temperature for Various Supply Voltages Figure 69. THD + Noise vs. Amplitude, VSY = ±5 V 0 100 VSY = ±15V VIN = 20V p-p VSY = 5V –20 10 –40 THD + N (%) 1 –60 –80 0.1 BW = 500kHz 0.01 BW = 80kHz –100 –140 100 1k 10k 100k 0.0001 0.001 13502-071 0.001 –120 13502-068 CHANNEL SEPARATION (dB) 1 AMPLITUDE (V rms) Figure 65. Supply Current (ISY) vs. Supply Voltage (VSY) for Various Temperatures 1.0 –40 0.1 0.01 SUPPLY VOLTAGE (V) 0.01 0.1 1 AMPLITUDE (V rms) FREQUENCY (Hz) Figure 67. Channel Separation vs. Frequency, VSY = ±15 V Figure 70. THD + Noise vs. Amplitude, VSY = 5 V Rev. A | Page 21 of 30 10 ADA4622-2 Data Sheet 0.1 0.1 VSY = 5V VSY = ±15V THD + N (%) THD + N (%) 0.01 0.001 BW = 500kHz 0.01 BW = 500kHz 0.0001 BW = 80kHz 0.00001 10 100 1k 10k 100k Figure 71. THD + Noise vs. Frequency, VSY = ±15 V VSY = ±5V 0.001 BW = 500kHz BW = 80kHz 13502-073 THD + N (%) 0.01 0.00001 100 1k 1k 10k Figure 73. THD + Noise vs. Frequency, VSY = 5 V 0.1 10 100 FREQUENCY (Hz) FREQUENCY (Hz) 0.0001 0.001 10 13502-074 13502-072 BW = 80kHz 10k 100k FREQUENCY (Hz) Figure 72. THD + Noise vs. Frequency, VSY = ±5 V Rev. A | Page 22 of 30 100k Data Sheet ADA4622-2 THEORY OF OPERATION V– R3 ED1 R4 R7 ED2 ED5 R1 +IN x SLEW ENHANCEMENT CIRCUIT Q2 Q1 Q3 C1 R2 J1 –IN x J2 OUT x R5 Q5 Q4 ED3 RR OUTPUT STAGE R6 VBIAS ED4 ED6 IMAGIC CURRENT OUT1 OUT2 R8 R9 R10 13502-075 IN CURRENT MIRROR V+ Figure 74. Simplified Circuit Diagram INPUT CHARACTERISTICS The ADA4622-2 input stage consists of N-channel, JFETs that provide low offset, low noise, and high impedance. The minimum input common-mode voltage extends from −0.2 mV below V− to 1 V less than V+. Driving the input closer to the positive rail causes loss of amplifier bandwidth and increased common-mode voltage error. Figure 75 shows the rounding of the output due to the loss of bandwidth. The input and output are superimposed. 13502-077 1 CH1 1.00V CH2 1.00V M2.00µs A CH1 3.84V Figure 76. No Phase Reversal Because the input stage uses N-channel JFETs, the input current during normal operation is negative. However, the input bias current changes direction as the input voltage approaches V+ due to internal junctions becoming forward biased (see Figure 77). 1 13502-076 4 A CH1 3.00V Figure 75. Bandwidth Limiting due to Headroom Requirements The ADA4622-2 does not exhibit phase reversal for input voltages up to V+. For input voltages greater than V+, a 10 kΩ resistor in series with the noninverting input prevents phase reversal at the expense of higher noise (see Figure 76). 2 1 0 –1 –2 –3 –5 13502-078 M2.00µs INPUT BIAS CURRENT (pA) CH1 1.00V CH2 1.00V 3 –4 –3 –2 –1 0 1 2 3 4 5 COMMON-MODE VOLTAGE (V) Figure 77. Input Bias Current vs. Common-Mode Voltage with ±5 V Supply Rev. A | Page 23 of 30 ADA4622-2 Data Sheet The ADA4622-2 is designed for 12 nV/√Hz wideband input voltage noise density and maintains low noise performance at low frequencies (see Figure 78). This noise performance, along with the low input current as well as low current noise, means that the ADA4622-2 contributes negligible noise for applications with a source resistance greater than 10 kΩ and at signal bandwidths greater than 1 kHz. 100 80 EMIRR (dB) COMPETITOR 1 COMPETITOR 2 ADA4622-2 100k 40 0 10M 13502-080 20 100M 1G FREQUENCY (Hz) 10k Figure 79. EMI Rejection Ratio (EMIRR) vs. Frequency OUTPUT CHARACTERISTICS 100 1k 10k 100k FREQUENCY (Hz) Figure 78. Total Noise vs. Source Resistance Input Overvoltage Protection The ADA4622-2 has internal protective circuitry that allows voltages as high as 0.3 V beyond the supplies applied at the input of either terminal without causing damage. Use a current limiting resistor in series with the input of the ADA4622-2 if the input voltage exceeds 0.3 V beyond the amplifier supply rails. If the overvoltage condition persists for more than a few seconds, the amplifier can be damaged. For higher input voltages, determine the resistor value by VIN − VSY ≤ 10 mA RS where: VIN is the input voltage. VSY is the voltage of either the V+ pin or the V− pin. RS is the series resistor. The ADA4622-2 unique bipolar rail-to-rail output stage swings within 10 mV of the supplies with no external resistive load. The ADA4622-2 approximate output saturation resistance is 24 Ω, sourcing or sinking. Use the output impedance to estimate the output saturation voltage when driving heavier loads. As an example, when driving 5 mA, the saturation voltage from either rail is roughly 120 mV. If the ADA4622-2 output drives hard against the output saturation voltage, it recovers within 1.2 µs of the input, returning to the linear operating region of the amplifier (see Figure 51 and Figure 54). Capacitive Load Drive Capability Direct capacitive loads interact with the effective output impedance of the ADA4622-2 to form an additional pole in the amplifier feedback loop, which causes excessive peaking on the pulse response or loss of stability. The worst case condition is when the device uses a single 5 V supply in a unity-gain configuration. Figure 80 shows the pulse response of the ADA4622-2 driving 500 pF directly. With a very low input bias current of ±1.5 nA maximum up to 125°C, higher resistor values can be used in series with the inputs without introducing large offset errors. A 1 kΩ series resistor allows the ADA4622-2 to withstand 10 V of continuous overvoltage and increases the noise by a negligible amount. A 5 kΩ resistor protects the inputs from voltages as high as 25 V beyond the supplies and adds less than 10 µV to the amplifier offset voltage. EMI Rejection Ratio 1 13502-081 1k 10 13502-079 RESISTANCE (Ω) ADA4622-2 VOLTAGE AND CURRENT NOISE RS NOISE TOTAL NOISE 60 CH1 50.0mV BW Figure 79 shows the electromagnetic interference rejection ratio (EMIRR) vs. frequency for the ADA4622-2. Rev. A | Page 24 of 30 M2.00µs A CH1 108mV Figure 80. Pulse Response with 500 pF Load Capacitance Data Sheet ADA4622-2 APPLICATIONS INFORMATION RECOMMENDED POWER SOLUTION ADP7118 +15V ADP7182 –15V Description DC-to-DC switching regulator with independent positive and negative outputs 20 V, 200 mA, low noise, CMOS LDO regulator −28 V, −200 mA, low noise, linear regulator The maximum power the ADA4622-2 can safely dissipate is limited by the associated rise in junction temperature. For plastic packages, the maximum safe junction temperature is 150°C. If this maximum temperature is exceeded, reduce the die temperature to restore proper circuit operation. Leaving the device in the overheated condition for an extended period can result in device burnout. To ensure proper operation, it is important to observe the Absolute Maximum Ratings and Thermal Resistance specifications. SECOND-ORDER LOW-PASS FILTER Figure 82 shows the ADA4622-2 configured as a second-order, Butterworth, low-pass filter. With the values as shown, the corner frequency equals 200 kHz. Component selection is shown in the following equations: R1 = R2 = User Selected (Typical Values: 10 kΩ to 100 kΩ) C2 VOUT 50pF C4 0.1µF A plot of the filter is shown in Figure 83; greater than 35 dB of high frequency rejection is achieved. MAXIMUM POWER DISSIPATION C1 AD4622-2 –5V Table 8. Recommended Power Management Devices ADP7118 ADP7182 1/2 C1 28pF Figure 82. Second-Order, Butterworth, Low-Pass Filter Figure 81. Power Solution Configuration for the ADA4622-2 Product ADP5070 VIN 50 40 30 20 10 0 –10 –20 –30 13502-084 –16V R2 20kΩ –40 –50 100 1k 10k 100k 1M FREQUENCY (Hz) 10M 100M Figure 83. Frequency Response of the Filter WIDEBAND PHOTODIODE PREAMPLIFIER The ADA4622-2 is an excellent choice for photodiode preamplifier application. The low input bias current minimizes the dc error at the preamplifier output. In addition, the high gain bandwidth product and low input capacitance maximizes the signal bandwidth of the photodiode preamplifier. Figure 84 shows the ADA4622-2 as a current to voltage (I to V) converter with an electrical model of a photodiode. CF 1.414 2πf CUTOFF R1 RF 0.707 2πf CUTOFF R1 – CM IPHOTO CS RSH = + VB VOUT CD 1011Ω CM AD4622-2 Figure 84. Wideband Photodiode Preamplifier Rev. A | Page 25 of 30 13502-085 ADP5070 R1 20kΩ AMPLITUDE (dB) +12V +5V C3 0.1µF 13502-082 +16V C2 56pF 13502-083 The ADA4622-2 can be operated from ±2.5 V to ±15 volt dual supply or 5 V to 30 V single supply.The ADP7118 and ADP7182 are recommended to generate the clean positive and negative rails for the ADA4622-2. Both low dropout regulators (LDOs) are available in fixed output voltage or adjustable output voltage versions. To generate the input voltages for the LDOs, the ADP5070 dc-to-dc switching regulator is recommended. Figure 81 shows the recommended power solution configuration for the ADA4622-2. ADA4622-2 Data Sheet The transimpedance gain of the photodiode preamplifier is described by the following basic transfer function: I PHOTO × RF 1 + sCF RF where IPHOTO is the output current of the photodiode. The parallel combination of RF and CF sets the signal bandwidth (see the I to V gain curve in Figure 86). s refers to the s-plane. Note that RF must be set so the maximum attainable output voltage corresponds to the maximum diode output current, IPHOTO, which allows use of the full output swing. The attainable signal bandwidth with this photodiode preamplifier is a function of RF, the gain bandwidth product (fGBP) of the amplifier, and the total capacitance at the amplifier summing junction, including CS and the amplifier input capacitance, CD and CM. RF and the total capacitance produce a pole with loop frequency (fP). fN = OPEN-LOOP GAIN 1 2πR F C S fX G = R2C1s With the additional pole from the amplifier open-loop response, the two-pole system results in peaking and instability due to an insufficient phase margin (see Figure 85). 1 2 π RF C F G=1 log f fP –45° –90° where fZ is the zero frequency. –135° Setting the zero at the fX frequency maximizes the signal bandwidth with a 45° phase margin. Because fX is the geometric mean of fP and fGBP, it can be calculated by –180° fX = f P × f GBP log f Figure 85. Gain and Phase Plot of the Transimpedance Amplifier Design, Without Compensation Combining these equations, the value of CF that produces fX is defined by CF = fGBP 0° PHASE (°) Adding CF creates a zero in the loop transmission that compensates for the effect of the input pole. This stabilizes the photodiode preamplifier design because of the increased phase margin. Adding CF also sets the signal bandwidth (see Figure 86). The signal bandwidth and the zero frequency are determined by fZ = f GBP (C S + C F ) C F CS 2π × R F × f GBP Rev. A | Page 26 of 30 13502-086 fP = The dominant sources of output noise in the wideband photodiode preamplifier design are the input voltage noise of the amplifier, VNOISE, and the resistor noise due to RF. The gray curve in Figure 86 shows the noise gain over frequencies for the photodiode preamplifier. Calculate the noise bandwidth at the fN frequency by |A| (dB) VOUT = The frequency response in this case shows about 2 dB of peaking and 15% overshoot. Doubling CF and halving the bandwidth results in a flat frequency response with about 5% transient overshoot. Data Sheet ADA4622-2 Increasing CF to 3 pF completely eliminates the peaking. However, increasing CF to 3 pF reduces the bandwidth to 1 MHz. OPEN-LOOP GAIN |A (s)| Table 9 shows the noise sources and total output noise for the photodiode preamplifier, where the preamplifier is configured to have a 45° phase margin for maximum bandwidth and fZ = fX = fN in this case. fX I TO V GAIN fZ 2pF fN G = 1 + CS/CF 49.9kΩ +5V G = RFCS(s) G=1 f fp fGBP 0.1µF –5V VOUT AD4622-2 0.1µF 45° 100Ω 13502-088 90° –5V Figure 87. Photodiode Preamplifier f 0° 3 2 –45° 1 2pF –135° Figure 86. Gain and Phase Plot of the Transimpedance Amplifier Design with Compensation Figure 87 shows the ADA4622-2 configured as a transimpedance photodiode amplifier. The amplifier is used in conjunction with a photodiode detector with an input capacitance of 5 pF. Figure 88 shows the transimpedance response of the ADA4622-2 when IPHOTO is 1 μA p-p. The amplifier has a bandwidth of 2 MHz when it is maximized for a 45° phase margin with CF = 2 pF. Note that with the PCB parasitics added to CF, the peaking is only 0.5 dB and the bandwidth is slightly reduced. –1 3pF –2 –3 –4 –5 13502-089 13502-087 –90° AMPLITUDE (dB) 0 –6 –7 10 100 1k 10k 100k FREQUENCY (Hz) 1M 10M Figure 88. Photodiode Preamplifier Frequency Response Table 9. RMS Noise Contributions of the Photodiode Preamplifier Contributor RF VNOISE Root Sum Square (RSS) Total 1 RMS Noise (μV)1 50.8 Expression 4kT RF f N VNOISE π 2 (C S C M C F C D ) fN CF 2 131.6 141 RF 2 VNOISE2 RMS noise with RF = 50 kΩ, CS = 5 pF, CF = 2 pF, CM = 3.7 pF, and CD = 0.4 pF. Rev. A | Page 27 of 30 100M ADA4622-2 Data Sheet PEAK DETECTOR In this application, D3 and D4 act as unidirectional current switches that open when the output is kept constant in hold mode. A peak detector captures the peak value of a signal and produces an output equal to it. By taking advantage of the dc precision and super low input bias current of the JFET input amplifiers, such as the ADA4622-2, a highly accurate peak detector can be built, as shown in Figure 89. VCC + 2 8 4 – VIN +PEAK ADA4622-2 U2A C4 50pF Feedback from the output of the U2B (positive peak) through R6 limits the output voltage of U2A. After detecting the peak, the output of U2A swings low but is clamped by D2. D3 reverses bias and the common node of D3, D4, and R7 is held to a voltage equal to positive peak by R7. The voltage across D4 is 0 V; therefore, the leakage is small. The bias current of U2B is also small. With almost no leakage, C3 has a long hold time. 5 8 1 D3 1N4148 D4 1N4148 6 C3 1µF R7 10kΩ D2 1N448 ADA4622-2 U2B 7 4 VEE R6 1kΩ Figure 89. Positive Peak Detector 13502-090 3 To detect a positive peak, U2A drives C3 through D3 and drives D4 until C3 is charged to a voltage equal to the input peak value. The ADA4622-2, shown in Figure 89, is a perfect fit for building a peak detector because U2A requires dc precision and high output current during fast peaks and U2B requires low input bias current (IB) to minimize capacitance discharge between peaks. A low leakage and low dielectric absorption capacitor, such as polystyrene or polypropylene, is required for C3. Reversing the diode directions causes the circuit to detect negative peaks. Rev. A | Page 28 of 30 Data Sheet ADA4622-2 OUTLINE DIMENSIONS 5.00 (0.1968) 4.80 (0.1890) 8 4.00 (0.1574) 3.80 (0.1497) 5 1 4 1.27 (0.0500) BSC 0.25 (0.0098) 0.10 (0.0040) 6.20 (0.2441) 5.80 (0.2284) 1.75 (0.0688) 1.35 (0.0532) 0.51 (0.0201) 0.31 (0.0122) COPLANARITY 0.10 SEATING PLANE 0.50 (0.0196) 0.25 (0.0099) 45° 8° 0° 0.25 (0.0098) 0.17 (0.0067) 1.27 (0.0500) 0.40 (0.0157) 012407-A COMPLIANT TO JEDEC STANDARDS MS-012-AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 90. 8-Lead Standard Small Outline Package [SOIC_N] Narrow Body (R-8) Dimensions shown in millimeters and (inches) 3.20 3.00 2.80 8 3.20 3.00 2.80 1 5.15 4.90 4.65 5 4 PIN 1 IDENTIFIER 0.65 BSC 0.95 0.85 0.75 15° MAX 1.10 MAX 0.40 0.25 6° 0° 0.23 0.09 COMPLIANT TO JEDEC STANDARDS MO-187-AA Figure 91. 8-Lead Mini Small Outline Package [MSOP] (RM-8) Dimensions shown in millimeters Rev. A | Page 29 of 30 0.80 0.55 0.40 10-07-2009-B 0.15 0.05 COPLANARITY 0.10 ADA4622-2 Data Sheet 1.84 1.74 1.64 3.10 3.00 SQ 2.90 1.55 1.45 1.35 EXPOSED PAD 0.50 0.40 0.30 0.80 0.75 0.70 1 4 BOTTOM VIEW TOP VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF 0.30 0.25 0.20 PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-229-WEED 12-07-2010-A PIN 1 INDEX AREA SEATING PLANE 0.50 BSC 8 5 Figure 92. 8-Lead Lead Frame Chip Scale Package [LFCSP] 3 mm × 3 mm Body and 0.75 mm Package Height (CP-8-13) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADA4622-2ACPZ-R7 ADA4622-2ACPZ-RL ADA4622-2ARMZ ADA4622-2ARMZ-R7 ADA4622-2ARMZ-RL ADA4622-2ARZ ADA4622-2ARZ-R7 ADA4622-2ARZ-RL ADA4622-2BRZ ADA4622-2BRZ-R7 ADA4622-2BRZ-RL 1 Temperature Range −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C −40°C to +125°C Package Description 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Lead Frame Chip Scale Package [LFCSP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Mini Small Outline Package [MSOP] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] 8-Lead Standard Small Outline Package [SOIC_N] Z = RoHS Compliant Part. ©2015–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13502-0-2/16(A) Rev. A | Page 30 of 30 Package Option CP-8-13 CP-8-13 RM-8 RM-8 RM-8 R-8 R-8 R-8 R-8 R-8 R-8 Branding A3D A3D A3D A3D A3D