AN4640 Application note Peripherals interconnections on STM32F405/7xx, STM32F415/7xx, STM32F42xxx, STM32F43xxx, STM32F446xx and STM32F469/479xx Introduction This application note describes how peripherals of the microcontrollers listed in Table 1 can communicate autonomously without any intervention from the CPU via a network known as Peripherals interconnect matrix. This feature enhances the CPU real-time performance, while at the same time substantially reducing its power consumption. The document begins with the description of the Peripherals interconnect matrix features, then it provides an overview of the peripherals configuration and their interconnections. An example is presented and described in detail. This application note has to be read in conjunction with reference manuals RM0090, RM0386 and RM0390, all available at www.st.com/stm32. Table 1. Applicable devices August 2015 Type Product lines Microcontrollers STM32F405/415 STM32F407/417 STM32F427/437 STM32F429/439 STM32F446 STM32F469/479 DocID027335 Rev 3 1/19 www.st.com 1 Contents AN4640 Contents 1 Module overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 2 Peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 2.3 2.4 2.5 2.6 3 Timers block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.1 From TIM to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.2 From TIM to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.3 From TIM to DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.4 From TIM to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Analog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2.1 From ADC to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 From Temperature sensor to ADC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 From Analog block to DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Clocks block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.3.1 From CSS to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.3.2 From LSE, LSI, RTC to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 System block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.1 From VBAT, VREFIN to ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4.2 From EXTI to Analog block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Communication interfaces block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.1 From SPDIFRX to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.2 From USB block to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.5.3 From ETH block to TIM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5.4 From Communication interfaces to DMA . . . . . . . . . . . . . . . . . . . . . . . . 13 DMA block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.1 Hardware description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.2 Software description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 4 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2/19 DocID027335 Rev 3 AN4640 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Applicable devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Peripherals interconnect matrix for products listed in Table 1 . . . . . . . . . . . . . . . . . . . . . . . 7 Peripherals interconnect configuration detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 DocID027335 Rev 3 3/19 3 List of figures AN4640 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. 4/19 Interconnection of STM32F405/7xx, STM32F415/7xx, STM32F42xxx, STM32F43xxx, STM32F446xxand STM32F469/479xx peripherals . . . . . . . . . . . . . . . . . . . 6 Master / Slave timer overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Master TIM / Slave ADC overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Master TIM / Slave DAC overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SOF connectivity. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 PTP trigger output to TIM2 ITR1 connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Application overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DocID027335 Rev 3 AN4640 1 Module overview Module overview Several peripherals can have direct connections between them, as a matter of fact they can be configured to send or respond to event signals that can be internally routed, directly with other peripherals in the device. The STM32F4 autonomous peripherals include: • Timers: can be internally connected to each other, or can be connected to DMA and to the Analog block. • Analog block: can receive event from timers or can generate event to DMA. • Clocks: can produce event to Timers. • System block: can send event to Analog block. • Communication interfaces block: can generate event to timers or to DMA. DocID027335 Rev 3 5/19 18 Module overview 6/19 An overview of peripheral interconnections for STM32F4 is shown in Figure 1. Figure 1. Interconnection of STM32F405/7xx, STM32F415/7xx, STM32F42xxx, STM32F43xxx, STM32F446xxand STM32F469/479xx peripherals 7LPHUV $QDORJ 95(),1 9%$7 $GYDQFHGFRQWUROWLPHUV 7,0 $'& (;7, 7,0;B%.,1 6WDUWWULJJHU LQMHFWHGJURXS 7,0 'XDO7ULSOH PRGH&RQWURO 6\VWHP 6WDUWWULJJHU UHJXODUJURXS (;7, (;7, 9%$7 7,0B75*2,75[ $'& 7,0[B75*2,75[ 96(16( *HQHUDOSXUSRVHWLPHUV 7,0B&+ DocID027335 Rev 3 7,0 7,0 7,0 $'& 95(),1 7HPSHUDWXUHVHQVRU 7,0 7,0;B75*2 &ORFNV 76(/ '$& '$& &66 /6( '0$ 7,0[B75*2,75[ 86%B62),75[ /6, 7,0[B75*2,75[ 7,0[B&+[ 373,75[ &+ '0$ 7,0[B83 *HQHUDOSXUSRVHWLPHUV 57& 5(4B675($0[ 7,0[B75*2 57& '0$ 7,0 7,0 7,0 7,0 7,0 7,0 63',)5;B)5$0(B6<1& 7,0;B75*2 %DVLFWLPHUV 7,0 7,0 2QO\LQ670)[[[670)[[[DQG670)[[ 63',)5; 63, 6$, 8$57 ,& ,& 86$57 63, (7+ 463, 6$, 8$57 63, 63, 63, 63, 27*+6 ,& 86$57 8$57 ,&)03 86$57 &5<3 +$6+ 27*)6 6',2 86$57 8$57 )0& ,6 ,6 '&0, 1RWLQ670)[[ 2QO\LQ670)[[DQG670)[[ 2QO\LQ670)[[[670)[[[670)[[DQG670)[[ 069 AN4640 2QO\LQ670)[[ &RPPXQLFDWLRQLQWHUIDFHV AN4640 Peripherals interconnect matrix Peripherals in STM32F4 are interconnected by a network named Peripherals interconnect matrix, that makes it possible to directly connect one peripheral to another without waking up the CPU. Depending on peripherals, these interconnections can operate in Run, Sleep and Stop modes. Peripherals that respond to events are called Users, those that send events are called Generators. Both types are listed in Table 2. Table 2. Peripherals interconnect matrix for products listed in Table 1 Users TIM4 TIM5 TIM8 TIM9 TIM11 TIM12 DMA1 DMA2 DAC TIM3 ADC TIM2 Timers Analog 1 TIM1 - X X X - X - - - - X X X X - - TIM2 X - X X X X X - - X - X X X X X TIM3 X X - X X - X - - X - X X X - - TIM4 X X X - X X - - X X - X X X X X TIM5 X - X - - X - - X X - X X X X X TIM6 - - - - - - - - - X - - - - X X TIM7 - - - - - - - - - X - - - - X X TIM8 - X - X X - - - - - X X X X X X TIM10 - - - - - - X - - - - - - - - - TIM11 - - - - - - X - - - - - - - - - TIM13 - - - - - - - - X - - - - - - - TIM14 - - - - - - - - X - - - - - - - 1 - - - - - X - - - - X - X X - - 2 - - - - - - - - - - X - - - - - 3 - - - - - - - - - - X - - - - - 1 - - - - - - - - - X - - - - - - 2 - - - - - - - - - X - - - - - - VSENSE - - - - - - - - - - - X - - - - LSI - - - - X - - - - - - - - - - - LSE - - - - X - - - - - - - - - - - RTC - - - - X - - X - - - - - - - - CSS X - - - - X - - - - - - - - - - Generators ADC Analog DMA TIM1 Timers Clocks 2 Peripherals interconnect matrix DAC DocID027335 Rev 3 2 3 1 2 7/19 18 Peripherals interconnect matrix AN4640 Table 2. Peripherals interconnect matrix for products listed in Table 1 (continued) Users TIM3 TIM4 TIM5 TIM8 TIM9 TIM11 TIM12 DMA1 DMA2 DAC TIM2 ADC OTG FS - X - - - - - - - - - - - - - - OTG HS - X - - - - - - - - - - - - - - SPI1 - - - - - - - - - - X - - - - - SPI2 - - - - - - - - - X - - - - - - SPI3 2 3 1 2 - - - - - - - - - X - - - - - - SPI4 (1) - - - - - - - - - - X - - - - - SPI5 (2) - - - - - - - - - - X - - - - - SPI6(2) CRYP - - - - - - - - - - X - - - - - (3) - - - - - - - - - - X - - - - - (3) - - - - - - - - - - X - - - - - ETH(3) - X - - - - - - - - - - - - - - SPDIFRX(4) - - - - - - - X - X - - - - - - - - - - - - - - - - X - - - - - I2C1 - - - - - - - - - X - - - - - - I2C2 - - - - - - - - - X - - - - - - I2C3 - - - - - - - - - X - - - - - - I2CFMP(4) HASH Communication interfaces Analog 1 Generators QSPI (5) - - - - - - - - - X - - - - - - (3) - - - - - - - - - X - - - - - - (3) - - - - - - - - - X - - - - - - SAI1(1) - - - - - - - - - - X - - - - - (4) - - - - - - - - - - X - - - - - USART1 - - - - - - - - - - X - - - - - USART2 - - - - - - - - - X - - - - - - USART3 - - - - - - - - - X - - - - - - USART6 - - - - - - - - - - X - - - - - UART4 - - - - - - - - - X - - - - - - UART5 - - - - - - - - - X - - - - - - UART7(2) - - - - - - - - - X - - - - - - UART8(2) - - - - - - - - - X - - - - - - DCMI - - - - - - - - - - X - - - - - SDIO - - - - - - - - - - X - - - - - I2S2 I2S3 SAI2 8/19 DMA TIM1 Timers DocID027335 Rev 3 AN4640 Peripherals interconnect matrix Table 2. Peripherals interconnect matrix for products listed in Table 1 (continued) Users Analog TIM3 TIM4 TIM5 TIM8 TIM9 TIM11 TIM12 DMA1 DMA2 DAC TIM2 ADC 1 VBAT - - - - - - - - - - - X - - - - VREFIN - - - - - - - - - - - X - - - - EXTI - - - - - - - - - - - X X X X X Generators System DMA TIM1 Timers 2 3 1 2 1. Only in STM32F42xxx, STM32F43xxx, STM32F446xx and STM32F469/479xx. 2. Only in STM32F42xxx. STM32F43xxx and STM32F469/479xx. 3. Not in STM32F446xx. 4. Only in STM32F446xx. 5. Only in STM32F446xx and STM32F469/479xx. 2.1 Timers block 2.1.1 From TIM to TIM Some of the timers are linked together internally for synchronization or chaining. When one timer is configured in Master mode, it can reset, start, stop or clock the counter of another timer configured in Slave mode. A description of this feature is provided in the “Timer synchronization” section of RM0090, RM0386 and RM0390 reference manuals, while all the possible master/slave connections are described in the “TIMx internal trigger connection” tables of the same documents. The output (from Master) is on signal TIMx_TRGO following a configurable timer event. The input (to slave) is on signals TIMx_ITR0/ITR1/ITR2/ITR3. Figure 2 is an overview of the trigger selection and the Master mode selection blocks. Figure 2. Master / Slave timer overview 0DVWHU7,0 &ORFN 6ODYH7,0 006 606 76 8(9 3UHVFDOHU &RXQWHU 0DVWHU PRGH FRQWURO 75*2 ,75 6ODYH PRGH FRQWURO DocID027335 Rev 3 &.B36& 3UHVFDOHU &RXQWHU 9/19 18 Peripherals interconnect matrix 2.1.2 AN4640 From TIM to ADC As shown in Figure 3, some timers can be used to generate an ADC triggering event. The output (from timer) is on signal TIMx_TRGO or TIMx_CHx event. The input (to ADC) is on signal EXTSEL [3:0], JEXTSEL [3:0]. Figure 3. Master TIM / Slave ADC overview 0DVWHU7,0 6ODYH$'& (;76(/>@ELWV &ORFN 006 8(9 3UHVFDOHU &RXQWHU 0DVWHU PRGH FRQWURO $QDORJWR GLJLWDO FRQYHUWHU 75*2 -(;76(/>@ELWV 7,0[B&+[ 069 ADC synchronization is described in the “Conversion on external trigger and trigger polarity” section of RM0090, RM0386 and RM0390 reference manuals. The connection between timers and ADCs regular and injected channels is described in the “External trigger for regular channels” and “External trigger for injected channels tables” of the same documents. 2.1.3 From TIM to DAC Some timers can be used as triggering event to start a DAC conversion (see Figure 4). The output (from timer) is on signal TIMx_TRGO directly connected to corresponding DAC Inputs. The selection of the input on DAC is provided in the “DAC trigger selection” section of the RM0090, RM0386 and RM0390 reference manuals. Figure 4. Master TIM / Slave DAC overview 0DVWHU7,0 &ORFN 6ODYH'$& 006 8(9 3UHVFDOHU &RXQWHU 76(/;>@ELWV 0DVWHU PRGH FRQWURO 75*2 '$& FRQWURO UHJLVWHU 069 2.1.4 From TIM to DMA Refer to Section 2.6: DMA block. 10/19 DocID027335 Rev 3 AN4640 2.2 Peripherals interconnect matrix Analog block Analog block includes: 2.2.1 • ADC block: three ADCs; • DAC block: two DAC converters; • Temperature sensor Block. From ADC to ADC In multi ADC mode, the start of conversion is triggered alternately or simultaneously by the ADC1 master to the ADC2 and ADC3 slaves, depending on the mode selected by the MULTI[4:0] bits in the ADC_CCR register. This feature is explained in the “Multi ADC mode” section of RM0090, RM0386 and RM0390 reference manuals. 2.2.2 From Temperature sensor to ADC1 On STM32F4xx devices, the temperature sensor is internally connected to the input channel, either ADC1_IN16 or ADC1_IN18 can be used to convert the sensor output voltage into a digital value. The section “Temperature sensor” in the RM0090, RM0386 and RM0390 reference manuals describes the connection between the sensor and the ADC and the procedure to apply in order to read the converted value. 2.2.3 From Analog block to DMA Refer to Section 2.6: DMA block. 2.3 Clocks block System block includes: 2.3.1 • LSE clock; • LSI clock; • Clock security system (CSS); • Real-time clock (RTC). From CSS to TIM CSS can generate system errors in the form of timer break toward timers. The purpose of the break function is to protect power switches driven by PWM signals generated by the timers. The list of possible break sources is given in the “Using the break function (TIM1/TIM8)” section of the RM0090, RM0386 and RM0390 reference manuals. 2.3.2 From LSE, LSI, RTC to TIM External clock (LSE), internal clock (LSI) and RTC wakeup interrupt can be used as input to general-purpose timer (TIM5 channel 4/TIM11 channel 1). DocID027335 Rev 3 11/19 18 Peripherals interconnect matrix AN4640 This feature is described in the following sections of the RM0090, RM0386 and RM0390 reference manuals: 2.4 • “Internal/external clock measurement using TIM5/TIM11”; • “TIM5 option register (TIM5_OR)”; • “TIM11 option register 1 (TIM11_OR)”. System block Power supplies block includes: 2.4.1 • The internal reference voltage VREFINT; • VBAT; • External interrupt/event controller (EXTI). From VBAT, VREFIN to ADC The VBAT channel is connected to channel ADC1_IN18. It can be converted as an injected or regular channel. The VREFINT is connected to ADC1_IN17. Refer to the following sections of the RM0090, RM0386 and RM0390 reference manuals for a description of the interconnection between VBAT, VREFINT and ADC: 2.4.2 • “Channel selection”; • “Battery charge monitoring”. From EXTI to Analog block EXTI can be used to generate an ADC triggering event or to start a DAC conversion. ADC synchronization is described in the “Conversion on external trigger and trigger polarity” section of the RM0090, RM0386 and RM0390 reference manuals, while selection of input triggers on DAC is provided in the “DAC trigger selection” section of the same documents. 2.5 Communication interfaces block 2.5.1 From SPDIFRX to TIM SPDIFRX (SPDIFRX_FRAME_SYNC) is connected to TIM11_CH1 to measure the clock drift of received SPDIFRX frames. This interconnection is explained in the section “TIM11 option register 1 (TIM11_OR)” of the RM0390 reference manual. 2.5.2 From USB block to TIM USB block includes: 12/19 • USB on-the-go full-speed (OTG_FS); • USB on-the-go high-speed (OTG_HS). DocID027335 Rev 3 AN4640 Peripherals interconnect matrix USB (OTG_FS SOF) and USB (OTG HS SOF) can generate a trigger to general-purpose timer (TIM2), as shown in Figure 5. Figure 5. SOF connectivity 670 3$ ,75 62)SXOVHRXWSXWWR H[WHUQDODXGLRFRQWURO 62)SXOVH 7,0 62)JHQ 7,06ODYH 86%0DVWHU 069 The interconnection between USB and TIM2 is described in the “SOF trigger” section of RM0090, RM0386 and RM0390 reference manuals. 2.5.3 From ETH block to TIM The MAC can generate a trigger to general-purpose timer (TIM2). This PTP trigger signal is connected to the TIM2 ITR1 input selectable by software. The connection is enabled through bits 11 and 10 in the TIM2 option register (TIM2_OR). Figure 6. PTP trigger output to TIM2 ITR1 connection (WKHUQHW0$& 373WULJJHU (7+0DVWHU ,75 7,0 7,06ODYH 069 Connection of ETH to TIM2 is described in the section “Precision time protocol (IEEE1588 PTP)” of the RM0090 and RM0386 reference manuals. 2.5.4 From Communication interfaces to DMA Refer to Section 2.6: DMA block. 2.6 DMA block Each stream is associated with a DMA request that can be selected out of 8 possible channel requests. The selection is controlled by the CHSEL[2:0] bits in the DMA_SxCR DocID027335 Rev 3 13/19 18 Peripherals interconnect matrix AN4640 register. The 8 requests from the peripherals (TIM, ADC, SPI, I2C, etc.) are independently connected to each channel and their connection depends on the product implementation. This interconnection is explained in the following tables of RM0090, RM0386 and RM0390 reference manuals: 14/19 • “DMA1 request mapping”; • “DMA2 request mapping”. DocID027335 Rev 3 AN4640 3 Application example Application example The example described in this section will demonstrate how to use the peripherals interconnect matrix on STM32F4 microcontrollers, namely how to set up ADC1 to start single conversions every time TIM 8 overflows. Each time an end of conversion occurs the DMA transfers the converted data from the ADC to memory. This application uses the STM32F4xx HAL API. 3.1 Hardware description Please refer to Figure 7, where the same color scheme of Figure 1 has been used: • TIM 8 peripheral: used to generate an ADC triggering event; • ADC1 peripheral: used in Slave mode; • DMA peripheral: used to transmit data from the slave ADC to the memory. Figure 7. Application overview 7,0JHQHUDWRU $'&XVHUJHQHUDWRU (;76(/>@ELWV 7,0B75*2 7,0 $'& $'&B,1 &+6(/ 5(4B675($0[ '0$XVHU 069 3.2 Software description The ADC1 is configured to convert TIM8 capture compare event ADC channel1. Each time an end of conversion occurs, the DMA transfers, in normal mode, the converted data from ADC1 DR register to the aDST_Buffer[ ] table. /* Enables ADC DMA request after last transfer and enables ADC peripheral*/ HAL_ADC_Start_DMA (&hadc1,(uint32_t*)&aDST_Buffer[0], BUFFER_SIZE); In this example, the system clock is 180 MHz, APB2 = 90 MHz and ADC clock = APB2/2. Since ADC1 clock is 45 MHz and sampling time is set to 3 cycles, the conversion time to 12 bit data is 12 cycles so the total conversion time is (12 + 3) / 45 = 0.33 µs. DocID027335 Rev 3 15/19 18 Table 3. Peripherals interconnect configuration detail Interconnect Code example sMasterConfig.MasterOutputTrigger=TIM_TRGO_UPDATE; TIM8_TRGO sMasterConfig.MasterSlaveMode=TIM_MASTERSLAVEMODE_DISABLE; selection sMasterConfig.MasterOutputTrigger = TIM_TRGO_RESET; HAL_TIMEx_MasterConfigSynchronization(&htim8, &sMasterConfig); ADC1 external trigger source DocID027335 Rev 3 DMA handle Comments Configures the Master TIM to generate a triggering event (TIM_TRGO_UPDATE). hadc1.Init.ExternalTrigConvEdge=ADC_EXTERNALTRIGCONVEDGE_RISING; hadc1.Init.ExternalTrigConv = ADC_EXTERNALTRIGCONV_T8_TRGO; hadc1.Init.DMAContinuousRequests = ENABLE; hadc1.Init.EOCSelection = ENABLE; HAL_ADC_Init(&hadc1); The TIM8_TRGO event triggers conversion for the regular group with rising edge. Since converted regular channel values are stored into a unique data register, the DMA mode is enabled. __HAL_LINKDMA(hadc, DMA_Handle, hdma_adc); Associates the initialized DMA handle to the ADC handle. Application example 16/19 The detail for related code is provided in Table 3. AN4640 AN4640 4 Conclusion Conclusion In this application note a useful complement to datasheets and reference manuals has been described by introducing the Peripherals interconnect matrix. A basic use case has been presented and described in detail. Users can start from it when developing their own solutions based on microcontrollers of the STM32F405/415, STM32F407/417, STM32F427/437, STM32F429/439, STM32F446 and STM32F469/479 lines. DocID027335 Rev 3 17/19 18 Revision history 5 AN4640 Revision history Table 4. Document revision history Date Revision 03-Feb-2015 1 Initial release. 2 Changed document classification from ST Restricted to Public. Updated title of Table 2 and caption of Figure 1. Updated references to RM0090 and RM0390 reference manuals in: – Section 2.1.1: From TIM to TIM; – Section 2.1.2: From TIM to ADC; – Section 2.1.3: From TIM to DAC; – Section 2.2.1: From ADC to ADC; – Section 2.2.2: From Temperature sensor to ADC1; – Section 2.3.1: From CSS to TIM; – Section 2.3.2: From LSE, LSI, RTC to TIM; – Section 2.4.1: From VBAT, VREFIN to ADC; – Section 2.4.2: From EXTI to Analog block; – Section 2.5.1: From SPDIFRX to TIM; – Section 2.5.2: From USB block to TIM; – Section 2.5.3: From ETH block to TIM; – Section 2.6: DMA block. 3 Added product lines STM32F469/479, hence updated: – Introduction and Table 1 on cover page; – Figure 1, Table 2 and its footnotes. Added reference to RM0386 reference manual in Sections 2.1.1, 2.1.2, 2.1.3, 2.2.1, 2.2.2, 2.3.1, 2.3.2 2.4.1, 2.4.2, 2.5.2, 2.5.3 and 2.6. Updated Section 2.5.1: From SPDIFRX to TIM. 19-Mar-2015 17-Aug-2015 18/19 Changes DocID027335 Rev 3 AN4640 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027335 Rev 3 19/19 19