STM32F411xC/E Errata sheet STM32F411xC and STM32F411xE device limitations Silicon identification This errata sheet applies to STMicroelectronics STM32F411xC and STM32F411xE microcontrollers. The STM32F411xC and STM32F411xE devices feature an ARM® 32-bit Cortex®-M4 core with FPU, for which an errata notice is also available (see Section 1 for details). The full list of part numbers is shown in Table 2. The products are identifiable as shown in Table 1: • by the revision code marked below the order code on the device package • by the last three digits of the Internal order code printed on the box label Table 1. Device identification(1) Order code Revision code marked on device(2) STM32F411xC, STM32F411xE “A” 1. The REV_ID bits in the DBGMCU_IDCODE register show the revision code of the device (see the RM0383 STM32F411xx reference manual for details on how to find the revision code). 2. Refer to datasheet for the device marking. Table 2. Device summary Reference October 2014 Part number STM32F411xC STM32F411CC, STM32F411RC, STM32F411VC STM32F411xE STM32F411CE, STM32F411RE, STM32F411VE DocID027036 Rev 1 1/21 www.st.com 1 Contents STM32F411xC/E Contents 1 2 ARM 32-bit Cortex-M4 with FPU limitations . . . . . . . . . . . . . . . . . . . . . . 5 1.1 Cortex-M4 interrupted loads to stack pointer can cause erroneous behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 VDIV or VSQRT instructions might not complete correctly when very short ISRs are used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM32F411xC and STM32F411xE silicon limitations . . . . . . . . . . . . . . 7 2.1 2.2 System limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1.1 Debugging Stop mode and system tick timer . . . . . . . . . . . . . . . . . . . . . 8 2.1.2 Debugging Stop mode with WFE entry . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.3 Wakeup sequence from Standby mode when using more than one wakeup source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1.4 Full JTAG configuration without NJTRST pin cannot be used . . . . . . . . 10 2.1.5 MPU attribute to RTC and IWDG registers could be managed incorrectly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1.6 Delay after an RCC peripheral clock enabling . . . . . . . . . . . . . . . . . . . . 10 2.1.7 PB5 I/O VIN limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.8 PA0 I/O VIN limitation in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1.9 PH1 cannot be used as a GPIO in HSE bypass mode . . . . . . . . . . . . . 11 IWDG peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2.1 2.3 2.4 I2C peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.1 SMBus standard not fully supported . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.2 Start cannot be generated after a misplaced Stop . . . . . . . . . . . . . . . . . 12 2.3.3 Mismatch on the “Setup time for a repeated Start condition” timing parameter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3.4 Data valid time (tVD;DAT) violated without the OVR flag being set . . . . . 13 2.3.5 Both SDA and SCL maximum rise time (tr) violated when VDD_I2C bus higher than ((VDD+0.3) / 0.7) V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 I2S peripheral limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4.1 2.5 2/21 RVU and PVU flags are not reset in STOP mode . . . . . . . . . . . . . . . . . 11 In I2S slave mode, WS level must be set by the external master when enabling the I2S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 USART peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5.1 Idle frame is not detected if receiver clock speed is deviated . . . . . . . . 14 2.5.2 In full duplex mode, the Parity Error (PE) flag can be cleared by writing to the data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 DocID027036 Rev 1 STM32F411xC/E 2.6 2.7 2.8 Contents 2.5.3 Parity Error (PE) flag is not set when receiving in Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5.4 Break frame is transmitted regardless of nCTS input line status . . . . . . 15 2.5.5 nRTS signal abnormally driven low after a protocol violation . . . . . . . . 15 OTG_FS peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.1 Data in RxFIFO is overwritten when all channels are disabled simultaneously . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.2 OTG host blocks the receive channel when receiving IN packets and no TxFIFO is configured . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.6.3 Host channel-halted interrupt not generated when the channel is disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.6.4 Error in software-read OTG_FS_DCFG register values . . . . . . . . . . . . 17 SDIO peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.1 SDIO HW flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.7.2 Wrong CCRCFAIL status after a response without CRC is received . . . 18 2.7.3 Data corruption in SDIO clock dephasing (NEGEDGE) mode . . . . . . . . 18 2.7.4 CE-ATA multiple write command and card busy signal management . . 18 2.7.5 No underrun detection with wrong data transmission . . . . . . . . . . . . . . 18 ADC peripheral limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8.1 3 ADC sequencer modification during conversion . . . . . . . . . . . . . . . . . . 19 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DocID027036 Rev 1 3/21 3 List of tables STM32F411xC/E List of tables Table 1. Table 2. Table 3. Table 4. Table 5. 4/21 Device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Cortex-M4 core limitations and impact on microcontroller behavior . . . . . . . . . . . . . . . . . . . 5 Summary of silicon limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 DocID027036 Rev 1 STM32F411xC/E 1 ARM 32-bit Cortex-M4 with FPU limitations ARM 32-bit Cortex-M4 with FPU limitations An errata notice of the STM32F411xC and STM32F411xE core is available from http://infocenter.arm.com. All the described limitations are minor and related to the revision r0p1-v1 of the Cortex-M4 core. Table 3 summarizes these limitations and their implications on the behavior of STM32F411xC and STM32F411xE devices. Table 3. Cortex-M4 core limitations and impact on microcontroller behavior 1.1 ARM ID ARM category 752770 Cat B Interrupted loads to SP can cause erroneous behavior Minor 776924 Cat B VDIV or VSQRT instructions might not complete correctly when very short ISRs are used Minor ARM summary of errata Impact on STM32F411xC and STM32F411xE Cortex-M4 interrupted loads to stack pointer can cause erroneous behavior Description An interrupt occurring during the data-phase of a single word load to the stack pointer (SP/R13) can cause an erroneous behavior of the device. In addition, returning from the interrupt results in the load instruction being executed an additional time. For all the instructions performing an update of the base register, the base register is erroneously updated on each execution, resulting in the stack pointer being loaded from an incorrect memory location. The instructions affected by this limitation are the following: • LDR SP, [Rn],#imm • LDR SP, [Rn,#imm]! • LDR SP, [Rn,#imm] • LDR SP, [Rn] • LDR SP, [Rn,Rm] Workaround As of today, no compiler generates these particular instructions. This limitation can only occur with hand-written assembly code. Both limitations can be solved by replacing the direct load to the stack pointer by an intermediate load to a general-purpose register followed by a move to the stack pointer. Example: Replace LDR SP, [R0] by LDR R2,[R0] MOV SP,R2 DocID027036 Rev 1 5/21 20 ARM 32-bit Cortex-M4 with FPU limitations 1.2 STM32F411xC/E VDIV or VSQRT instructions might not complete correctly when very short ISRs are used Description On Cortex-M4 with FPU core, 14 cycles are required to execute a VDIV or VSQRT instruction. This limitation is present when the following conditions are met: • A VDIV or VSQRT is executed • The destination register for VDIV or VSQRT is one of s0 - s15 • An interrupt occurs and is taken • The ISR being executed does not contain a floating point instruction • 14 cycles after the VDIV or VSQRT is executed, an interrupt return is executed In this case, if there are only one or two instructions inside the interrupt service routine, then the VDIV or VQSRT instruction does not complete correctly and the register bank and FPSCR are not updated, meaning that these registers hold incorrect out-of-date data. Workaround Two workarounds are applicable: 6/21 • Disable lazy context save of floating point state by clearing LSPEN to 0 (bit 30 of the FPCCR at address 0xE000EF34). • Ensure that every ISR contains more than 2 instructions in addition to the exception return instruction. DocID027036 Rev 1 STM32F411xC/E 2 STM32F411xC and STM32F411xE silicon limitations STM32F411xC and STM32F411xE silicon limitations Table 4 gives quick references to all documented limitations. Legend for Table 4: A = workaround available; N = no workaround available; P = partial workaround available, ‘-’ and grayed = fixed. Table 4. Summary of silicon limitations Links to silicon limitations Section 2.1.1: Debugging Stop mode and system tick timer A Section 2.1.2: Debugging Stop mode with WFE entry A Section 2.1.3: Wakeup sequence from Standby mode when using more than one wakeup source A Section 2.1.4: Full JTAG configuration without NJTRST pin cannot be used A Section 2.1: System limitations Section 2.1.5: MPU attribute to RTC and IWDG registers could be managed incorrectly Section 2.2: IWDG peripheral limitation Section 2.3: I2C peripheral limitations Section 2.4: I2S peripheral limitation Revision A A Section 2.1.6: Delay after an RCC peripheral clock enabling A Section 2.1.7: PB5 I/O VIN limitation A Section 2.1.8: PA0 I/O VIN limitation in Standby mode A Section 2.1.9: PH1 cannot be used as a GPIO in HSE bypass mode N Section 2.2.1: RVU and PVU flags are not reset in STOP mode A Section 2.3.1: SMBus standard not fully supported A Section 2.3.2: Start cannot be generated after a misplaced Stop A Section 2.3.3: Mismatch on the “Setup time for a repeated Start condition” timing parameter A Section 2.3.4: Data valid time (tVD;DAT) violated without the OVR flag being set A Section 2.3.5: Both SDA and SCL maximum rise time (tr) violated when VDD_I2C bus higher than ((VDD+0.3) / 0.7) V A Section 2.4.1: In I2S slave mode, WS level must be set by the external master when enabling the I2S A DocID027036 Rev 1 7/21 20 STM32F411xC and STM32F411xE silicon limitations STM32F411xC/E Table 4. Summary of silicon limitations (continued) Links to silicon limitations Section 2.5.1: Idle frame is not detected if receiver clock speed is deviated N Section 2.5.2: In full duplex mode, the Parity Error (PE) flag can be cleared by writing to the data register A Section 2.5: Section 2.5.3: Parity Error (PE) flag is not set when receiving in USART peripheral Mute mode using address mark detection limitations Section 2.5.4: Break frame is transmitted regardless of nCTS input line status Section 2.6: OTG_FS peripheral limitations N N Section 2.5.5: nRTS signal abnormally driven low after a protocol violation A Section 2.6.1: Data in RxFIFO is overwritten when all channels are disabled simultaneously A Section 2.6.2: OTG host blocks the receive channel when receiving IN packets and no TxFIFO is configured A Section 2.6.3: Host channel-halted interrupt not generated when the channel is disabled A Section 2.6.4: Error in software-read OTG_FS_DCFG register values A Section 2.7.1: SDIO HW flow control N Section 2.7.2: Wrong CCRCFAIL status after a response without CRC is received A Section 2.7: SDIO Section 2.7.3: Data corruption in SDIO clock dephasing peripheral (NEGEDGE) mode limitations Section 2.7.4: CE-ATA multiple write command and card busy signal management Section 2.8: ADC peripheral limitations Revision A N A Section 2.7.5: No underrun detection with wrong data transmission A Section 2.8.1: ADC sequencer modification during conversion A 2.1 System limitations 2.1.1 Debugging Stop mode and system tick timer Description If the system tick timer interrupt is enabled during the Stop mode debug (DBG_STOP bit set in the DBGMCU_CR register), it will wake up the system from Stop mode. Workaround To debug the Stop mode, disable the system tick timer interrupt. 8/21 DocID027036 Rev 1 STM32F411xC/E 2.1.2 STM32F411xC and STM32F411xE silicon limitations Debugging Stop mode with WFE entry Description When the Stop debug mode is enabled (DBG_STOP bit set in the DBGMCU_CR register), this allows software debugging during Stop mode. However, if the application software uses the WFE instruction to enter Stop mode, after wakeup some instructions could be missed if the WFE is followed by sequential instructions. This affects only Stop debug mode with WFE entry. Workaround To debug Stop mode with WFE entry, the WFE instruction must be inside a dedicated function with 1 instruction (NOP) between the execution of the WFE and the Bx LR. Example: __asm void _WFE(void) { WFE NOP BX lr } 2.1.3 Wakeup sequence from Standby mode when using more than one wakeup source Description The various wakeup sources are logically OR-ed in front of the rising-edge detector which generates the wakeup flag (WUF). The WUF needs to be cleared prior to Standby mode entry, otherwise the MCU wakes up immediately. If one of the configured wakeup sources is kept high during the clearing of the WUF (by setting the CWUF bit), it may mask further wakeup events on the input of the edge detector. As a consequence, the MCU might not be able to wake up from Standby mode. Workaround To avoid this problem, the following sequence should be applied before entering Standby mode: Note: • Disable all used wakeup sources, • Clear all related wakeup flags, • Re-enable all used wakeup sources, • Enter Standby mode Be aware that, when applying this workaround, if one of the wakeup sources is still kept high, the MCU enters Standby mode but then it wakes up immediately generating a power reset. DocID027036 Rev 1 9/21 20 STM32F411xC and STM32F411xE silicon limitations 2.1.4 STM32F411xC/E Full JTAG configuration without NJTRST pin cannot be used Description When using the JTAG debug port in debug mode, the connection with the debugger is lost if the NJTRST pin (PB4) is used as a GPIO. Only the 4-wire JTAG port configuration is impacted. Workaround Use the SWD debug port instead of the full 4-wire JTAG port. 2.1.5 MPU attribute to RTC and IWDG registers could be managed incorrectly Description If the MPU is used and the non bufferable attribute is set to the RTC or IWDG memory map region, the CPU access to the RTC or IWDG registers could be treated as bufferable, provided that there is no APB prescaler configured (AHB/APB prescaler is equal to 1). Workaround If the non bufferable attribute is required for these registers, the software could perform a read after the write to guaranty the completion of the write access. 2.1.6 Delay after an RCC peripheral clock enabling Description A delay between an RCC peripheral clock enable and the effective peripheral enabling should be taken into account in order to manage the peripheral read/write to registers. This delay depends on the peripheral mapping: • If the peripheral is mapped on AHB: the delay should be equal to 2 AHB clock cycles after the clock enable bit is set in the hardware register. • If the peripheral is mapped on APB: the delay should be equal to 2 APB clock cycles after the clock enable bit is set in the hardware register. Workarounds 10/21 1. Enable the peripheral clock some time before the peripheral read/write register is required. 2. For AHB peripheral, insert two dummy read operations to the peripheral register. 3. For APB peripheral, insert a dummy read operations to the peripheral register. DocID027036 Rev 1 STM32F411xC/E 2.1.7 STM32F411xC and STM32F411xE silicon limitations PB5 I/O VIN limitation Description If the input voltage (VIN) applied to PB5 exceeds VDD supply voltage, an I/O leakage current, which can impact the product lifetime, is observed. Workaround There is no functional limitation on PB5 pad if VIN does not exceed VDD. 2.1.8 PA0 I/O VIN limitation in Standby mode Description In Standby mode, if the input voltage (VIN) applied to PA0 exceeds VDD supply voltage, an I/O leakage current, which can impact the product lifetime, is observed. Workaround There is no functional limitation on PA0 pad if VIN does not exceed VDD. If the device does not operate in Standby mode, PA0 is 5 V tolerant (FT) thus allowing an input voltage higher than VDD (according to the datasheet specifications). 2.1.9 PH1 cannot be used as a GPIO in HSE bypass mode Description When an external clock is used and the HSE is bypassed, PH1 cannot be used as GPIO. Work around None. 2.2 IWDG peripheral limitation 2.2.1 RVU and PVU flags are not reset in STOP mode Description The RVU and PVU flags of the IWDG_SR register are set by hardware after a write access to the IWDG_RLR and the IWDG_PR registers, respectively. If the Stop mode is entered immediately after the write access, the RVU and PVU flags are not reset by hardware. Before performing a second write operation to the IWDG_RLR or the IWDG_PR register, the application software must wait for the RVU or PVU flag to be reset. However, since the RVU/PVU bit is not reset after exiting the Stop mode, the software goes into an infinite loop and the independent watchdog (IWDG) generates a reset after the programmed timeout period. DocID027036 Rev 1 11/21 20 STM32F411xC and STM32F411xE silicon limitations STM32F411xC/E Workaround Wait until the RVU or PVU flag of the IWDG_SR register is reset before entering the Stop mode. 2.3 I2C peripheral limitations 2.3.1 SMBus standard not fully supported Description The I2C peripheral is not fully compliant with the SMBus v2.0 standard since It does not support the capability to NACK an invalid byte/command. Workarounds A higher-level mechanism should be used to verify that a write operation is being performed correctly at the target device, such as: 2.3.2 1. Using the SMBAL pin if supported by the host 2. the alert response address (ARA) protocol 3. the Host notify protocol Start cannot be generated after a misplaced Stop Description If a master generates a misplaced Stop on the bus (bus error), the peripheral cannot generate a Start anymore. Workaround In the I²C standard, it is allowed to send a Stop only at the end of the full byte (8 bits + acknowledge), so this scenario is not allowed. Other derived protocols like CBUS allow it, but they are not supported by the I²C peripheral. A software workaround consists in asserting the software reset using the SWRST bit in the I2C_CR1 control register. 2.3.3 Mismatch on the “Setup time for a repeated Start condition” timing parameter Description In case of a repeated Start, the “Setup time for a repeated Start condition” (named Tsu;sta in the I²C specification) can be slightly violated when the I²C operates in Master Standard mode at a frequency between 88 kHz and 100 kHz. 12/21 DocID027036 Rev 1 STM32F411xC/E STM32F411xC and STM32F411xE silicon limitations The limitation can occur only in the following configuration: • in Master mode • in Standard mode at a frequency between 88 kHz and 100 kHz (no limitation in Fastmode) • SCL rise time: – If the slave does not stretch the clock and the SCL rise time is more than 300 ns (if the SCL rise time is less than 300 ns, the limitation cannot occur) – If the slave stretches the clock The setup time can be violated independently of the APB peripheral frequency. Workaround Reduce the frequency down to 88 kHz or use the I²C Fast-mode, if supported by the slave. 2.3.4 Data valid time (tVD;DAT) violated without the OVR flag being set Description The data valid time (tVD;DAT, tVD;ACK) described by the I²C standard can be violated (as well as the maximum data hold time of the current data (tHD;DAT)) under the conditions described below. This violation cannot be detected because the OVR flag is not set (no transmit buffer underrun is detected). This limitation can occur only under the following conditions: • in Slave transmit mode • with clock stretching disabled (NOSTRETCH=1) • if the software is late to write the DR data register, but not late enough to set the OVR flag (the data register is written before) Workaround If the master device allows it, use the clock stretching mechanism by programming the bit NOSTRETCH=0 in the I2C_CR1 register. If the master device does not allow it, ensure that the software is fast enough when polling the TXE or ADDR flag to immediately write to the DR data register. For instance, use an interrupt on the TXE or ADDR flag and boost its priority to the higher level. DocID027036 Rev 1 13/21 20 STM32F411xC and STM32F411xE silicon limitations 2.3.5 STM32F411xC/E Both SDA and SCL maximum rise time (tr) violated when VDD_I2C bus higher than ((VDD+0.3) / 0.7) V Description When an external legacy I2C bus voltage (VDD_I2C) is set to 5 V while the MCU is powered from VDD, the internal 5-Volt tolerant circuitry is activated as soon the input voltage (VIN) reaches the VDD + diode threshold level. An additional internal large capacitance then prevents the external pull-up resistor (RP) from rising the SDA and SCL signals within the maximum timing (tr) which is 300 ns in fast mode and 1000 ns in Standard mode. The rise time (tr) is measured from VIL and VIH with levels set at 0.3VDD_I2C and 0.7VDD_I2C. Workaround The external VDD_I2C bus voltage should be limited to a maximum value of ((VDD+0.3) / 0.7) V. As a result, when the MCU is powered from VDD=3.3 V, VDD_I2C should not exceed 5.14 V to be compliant with I2C specifications. 2.4 I2S peripheral limitation 2.4.1 In I2S slave mode, WS level must be set by the external master when enabling the I2S Description In slave mode, the WS signal level is used only to start the communication. If the I2S (in slave mode) is enabled while the master is already sending the clock and the WS signal level is low (for I2S protocol) or is high (for the LSB or MSB-justified mode), the slave starts communicating data immediately. In this case, the master and slave will be desynchronized throughout the whole communication. Workaround The I2S peripheral must be enabled when the external master sets the WS line at: • High level when the I2S protocol is selected. • Low level when the LSB or MSB-justified mode is selected. 2.5 USART peripheral limitations 2.5.1 Idle frame is not detected if receiver clock speed is deviated Description If the USART receives an idle frame followed by a character, and the clock of the transmitter device is faster than the USART receiver clock, the USART receive signal falls too early when receiving the character start bit, with the result that the idle frame is not detected (IDLE flag is not set). 14/21 DocID027036 Rev 1 STM32F411xC/E STM32F411xC and STM32F411xE silicon limitations Workaround None. 2.5.2 In full duplex mode, the Parity Error (PE) flag can be cleared by writing to the data register Description In full duplex mode, when the Parity Error flag is set by the receiver at the end of a reception, it may be cleared while transmitting by reading the USART_SR register to check the TXE or TC flags and writing data to the data register. Consequently, the software receiver can read the PE flag as '0' even if a parity error occurred. Workaround The Parity Error flag should be checked after the end of reception and before transmission. 2.5.3 Parity Error (PE) flag is not set when receiving in Mute mode using address mark detection Description The USART receiver is in Mute mode and is configured to exit the Mute mode using the address mark detection. When the USART receiver recognizes a valid address with a parity error, it exits the Mute mode without setting the Parity Error flag. Workaround None. 2.5.4 Break frame is transmitted regardless of nCTS input line status Description When CTS hardware flow control is enabled (CTSE = 1) and the Send Break bit (SBK) is set, the transmitter sends a break frame at the end of the current transmission regardless of nCTS input line status. Consequently, if an external receiver device is not ready to accept a frame, the transmitted break frame is lost. Workaround None. 2.5.5 nRTS signal abnormally driven low after a protocol violation Description When RTS hardware flow control is enabled, the nRTS signal goes high when data is received. If this data was not read and new data is sent to the USART (protocol violation), the nRTS signal goes back to low level at the end of this new data. DocID027036 Rev 1 15/21 20 STM32F411xC and STM32F411xE silicon limitations STM32F411xC/E Consequently, the sender gets the wrong information that the USART is ready to receive further data. On USART side, an overrun is detected, which indicates that data has been lost. Workaround Workarounds are required only if the other USART device violates the communication protocol, which is not the case in most applications. Two workarounds can be used: • After data reception and before reading the data in the data register, the software takes over the control of the nRTS signal as a GPIO and holds it high as long as needed. If the USART device is not ready, the software holds the nRTS pin high, and releases it when the device is ready to receive new data. • The time required by the software to read the received data must always be lower than the duration of the second data reception. For example, this can be ensured by treating all the receptions by DMA mode. 2.6 OTG_FS peripheral limitations 2.6.1 Data in RxFIFO is overwritten when all channels are disabled simultaneously Description If the available RxFIFO is just large enough to host 1 packet + its data status, and is currently occupied by the last received data + its status and, at the same time, the application requests that more IN channels be disabled, the OTG_FS peripheral does not first check for available space before inserting the disabled status of the IN channels. It just inserts them by overwriting the existing data payload. Workaround Use one of the following recommendations: 2.6.2 1. Configure the RxFIFO to host a minimum of 2 × MPSIZ + 2 × data status entries. 2. The application has to check the RXFLVL bit (RxFIFO non-empty) in the OTG_FS_GINTSTS register before disabling each IN channel. If this bit is not set, then the application can disable an IN channel at a time. Each time the application disables an IN channel, however, it first has to check that the RXFLVL bit = 0 condition is true. OTG host blocks the receive channel when receiving IN packets and no TxFIFO is configured Description When receiving data, the OTG_FS core erroneously checks for available TxFIFO space when it should only check for RxFIFO space. If the OTG_FS core cannot see any space allocated for data transmission, it blocks the reception channel and no data is received. Workaround 16/21 DocID027036 Rev 1 STM32F411xC/E STM32F411xC and STM32F411xE silicon limitations Set at least one TxFIFO equal to the maximum packet size. In this way, the host application, which intends to supports only IN traffic, also has to allocate some space for the TxFIFO. Since a USB host is expected to support any kind of connected endpoint, it is good practice to always configure enough TxFIFO space for OUT endpoints. 2.6.3 Host channel-halted interrupt not generated when the channel is disabled Description When the application enables, then immediately disables the host channel before the OTG_FS host has had time to begin the transfer sequence, the OTG_FS core, as a host, does not generate a channel-halted interrupt. The OTG_FS core continues to operate normally. Workaround Do not disable the host channel immediately after enabling it. 2.6.4 Error in software-read OTG_FS_DCFG register values Description When the application writes to the DAD and PFIVL bitfields in the OTG_FS_DCFG register, and then reads the newly written bitfield values, the read values may not be correct. The values written by the application, however, are correctly retained by the core, and the normal operation of the device is not affected. Workaround Do not read from the OTG_FS_DCFG register’s DAD and PFIVL bitfields just after programming them. 2.7 SDIO peripheral limitations 2.7.1 SDIO HW flow control Description When enabling the HW flow control by setting bit 14 of the SDIO_CLKCR register to ‘1’, glitches can occur on the SDIOCLK output clock resulting in wrong data to be written into the SD/MMC card or into the SDIO device. As a consequence, a CRC error will be reported to the SD/SDIO MMC host interface (DCRCFAIL bit set to ‘1’ in SDIO_STA register). Workaround None. Note: Do not use the HW flow control. Overrun errors (Rx mode) and FIFO underrun (Tx mode) should be managed by the application software. DocID027036 Rev 1 17/21 20 STM32F411xC and STM32F411xE silicon limitations 2.7.2 STM32F411xC/E Wrong CCRCFAIL status after a response without CRC is received Description The CRC is calculated even if the response to a command does not contain any CRC field. As a consequence, after the SDIO command IO_SEND_OP_COND (CMD5) is sent, the CCRCFAIL bit of the SDIO_STA register is set. Workaround The CCRCFAIL bit in the SDIO_STA register shall be ignored by the software. CCRCFAIL must be cleared by setting CCRCFAILC bit of the SDIO_ICR register after reception of the response to the CMD5 command. 2.7.3 Data corruption in SDIO clock dephasing (NEGEDGE) mode Description When NEGEDGE bit is set to ‘1’, it may lead to invalid data and command response read. Workaround None. A configuration with the NEGEDGE bit equal to ‘1’ should not be used. 2.7.4 CE-ATA multiple write command and card busy signal management Description The CE-ATA card may inform the host that it is busy by driving the SDIO_D0 line low, two cycles after the transfer of a write command (RW_MULTIPLE_REGISTER or RW_MULTIPLE_BLOCK). When the card is in a busy state, the host must not send any data until the BUSY signal is de-asserted (SDIO_D0 released by the card). This condition is not respected if the data state machine leaves the IDLE state (Write operation programmed and started, DTEN = 1, DTDIR = 0 in SDIO_DCTRL register and TXFIFOE = 0 in SDIO_STA register). As a consequence, the write transfer fails and the data lines are corrupted. Workaround After sending the write command (RW_MULTIPLE_REGISTER or RW_MULTIPLE_BLOCK), the application must check that the card is not busy by polling the BSY bit of the ATA status register using the FAST_IO (CMD39) command before enabling the data state machine. 2.7.5 No underrun detection with wrong data transmission Description In case there is an ongoing data transfer from the SDIO host to the SD card and the hardware flow control is disabled (bit 14 of the SDIO_CLKCR is not set), if an underrun condition occurs, the controller may transmit a corrupted data block (with wrong data word) without detecting the underrun condition when the clock frequencies have the following relationship: 18/21 DocID027036 Rev 1 STM32F411xC/E STM32F411xC and STM32F411xE silicon limitations [3 x period(PCLK2) + 3 x period(SDIOCLK)] >= (32 / (BusWidth)) x period(SDIO_CK) Workaround Avoid the above-mentioned clock frequency relationship, by: • Incrementing the APB frequency • or decreasing the transfer bandwidth • or reducing SDIO_CK frequency 2.8 ADC peripheral limitations 2.8.1 ADC sequencer modification during conversion Description If an ADC conversion is started by software (writing the SWSTART bit), and if the ADC_SQRx or ADC_JSQRx registers are modified during the conversion, the current conversion is reset and the ADC does not restart a new conversion sequence automatically. If an ADC conversion is started by hardware trigger, this limitation does not apply. The ADC restarts a new conversion sequence automatically. Workaround When an ADC conversion sequence is started by software, a new conversion sequence can be restarted only by setting the SWSTART bit in the ADC_CR2 register. DocID027036 Rev 1 19/21 20 Revision history 3 STM32F411xC/E Revision history Table 5. Document revision history 20/21 Date Revision 20-Oct-2014 1 Changes Initial release. DocID027036 Rev 1 STM32F411xC/E IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID027036 Rev 1 21/21 21