Optimization of ONBCD25 Depletion-Mode NLDMOS24V5V Device Hui Wang, Gennadiy Nemtsev, Yingping Zheng, Christian Kendrick, Guillaume Jenicot* Corp R&D, ON Semiconductor Corp, East Greenwich, RI, USA *Power Technology Centre, ON Semiconductor Belgium BVBA, Oudenaarde, Belgium [email protected] Summary The depletion-mode NLDMOS24V5V (NLDMOSD24V5V) device has been developed and optimized for ONBCD25 – ON Semiconductor’s 0.25um BCD process technology. A novel approach -- separating Vt-adjusting layer (DVTNDLD) from STI -- has been designed, tested, and analyzed to solve a major problem -- Id jumps up as Vds becomes high when Vgs is around Vt. This approach reduces excessive ntype concentration and smoothes out electric field distribution close to the STI corner of the drift region, increases the local junction BV between body and channel/drift region and suppresses the Id-jump. Another novel approach is to add a gap between HVNW and HVPW. With HVPW and device pitch size fixed, the gap size is varied to find the optimal BV and Rdson. In addition, the overlap between LV PWell (SHP) and Poly has been optimized. The optimized device shows state-of-the-art electrical performance, including 50V BV-off and 34 mohm*mm^2 Rdson × area (Rsp) at 5V Vgs, and -2V Vt. Motivation NLDMOSD24V5V device, with maximum operational Vds of 24V and Vgs of 5V, was requested in ONBCD25 platform requiring stringent BV-off (>36V), Vt (-1.95V to -2.25V), and state-of-the-art Rsp. Based on the request and ONBCD25 process architecture, the device structure scheme has been designed, as shown in Fig. 1. One major problem with NLDMOSD24V5V is that Id jumps up as Vds becomes high when Vgs is around Vt, illustrated by the blue curve in Fig. 2. This paper presents the NLDMOSD24V5V structure optimization process, including the approach and solution to the Id-jump problem. Results In typical LV depletion-mode MOS devices, Vt-adjusting layer covers all area under poly 1 . In this work, however, the distance between DVTNDLD and STI was varied to overcome the Id-jump. Separating DVTNDLD from STI would reduce excessive n-type concentration and smooth out electric field distribution close to the STI corner of the drift region, increase the local junction BV between body and channel/drift region, and suppress the Id-jump. Fig. 3 shows the corroboration from simulation results. For typical CMOS processes, NW and PW abutt each other. In this work, a novel approach was used by putting a gap between HVNW and HVPW. The gap size was varied while HVPW and device pitch size were fixed. Additionally, the overlap was varied between LV PWell (SHP) and Poly in the test patterns. After analyzing the silicon results of these test patterns, the optimal device structure was concluded. Fig. 4 plots the test results of Id-jump ratio (ratio of Id at 24V Vds and Id at 5V Vds when Vgs is -2.1V), BV-off, Rsp and Vt for a series of test patterns. Id-jump ratio results show that the test patterns with p1nas greater than 1.05um, i.e., DVTNDLD not overlapping STI, have acceptably small Id-jump. Besides Idjump ratios, Fig. 4 shows that BV-off decreases as b increases because there is less depletion around b region. When b > 0.5um, BV-off can be <40V -- unacceptable. On the other hand, there is a process constraint of b > 0.3um. Therefore, b is limited to 0.4~0.5um. In addition, Fig. 4 demonstrates that for lower Rsp, "a" should be lower, too. However, when a < 0.4um, there can be large Vt variations due to lithography limitations, as shown in Fig. 4. As a result, the optimal “a” can only be 0.4um. Consequently, the optimized structure with best set of BV-off and Rsp is p1nas=1.35um, b=0.4um, and a=0.4um. The TLP results, as shown in Fig. 5, and HCI results are also satisfactory for this chosen device structure. 1 S. Wolf, “Silicon Processing for the VLSI Era”, Vol 2, Lattice Press, p. 322, 1990. Figures Poly PIMP NIMP NLK DVTNDLD p1nas HVNW PBody PBody NIMP NTH K STI SHN SHP a gap 0.8-b b PBL HVPW HVNW NBL Fig. 2: IdVd curves when Vgs is around Vt. Id values are normalized. Blue curve illustrates typical Idjump problem; there is no Id-jump problem in red curve. PSub S tru c tu re A ( iii) d S tr u c tu re B ( iv ) 0. 4 0. 5 0. 4 0. 5 0.6 0. 3 0.4 0. 5 0. 6 0. 4 0. 5 0.6 0. 4 0. 5 0. 3 0. 4 0. 5 0. 6 0.3 0. 4 0 .5 0. 6 0. 4 0. 5 c d 0.3 0.4 0.5 0.6 0.79 0.3 0.4 0.5 1.25 1.35 1.45 0.3 46 0.4 42 0.5 0.6 0.79 0.3 0.4 0.5 1.25 1.35 1.45 a 0.6 b 1.55 p1nas 0. 4 0. 5 0. 4 0. 5 0. 6 0. 3 0. 4 0. 5 0.6 0. 4 0.5 0. 6 0. 4 0. 5 0.3 0. 4 0. 5 0. 6 0. 3 0. 4 0. 5 0. 6 0. 4 0.5 c I d-jum p R a t io S tru c tu re B ( ii) -1.90 -2.00 -2.10 -2.20 -2.30 -2.40 20 -2.50 15 10 5 0 -5 54 -10 50 BV -of f (V ) S tr u c tu re A ( i) VT (V ) Fig. 1: Device cross-section scheme with layer names and structure variables. b = 0.8um - gap. a 0.6 b 1.55 p1nas 38 34 0. 4 0 .5 0. 4 0. 5 0. 6 0 .3 0. 4 0. 5 0.6 0. 4 0.5 0. 6 0 .4 0. 5 0.3 0. 4 0 .5 0. 6 0. 3 0. 4 0. 5 0. 6 0. 4 0.5 30 80 R sp0 75 0.3 0.4 70 0.5 0.6 0.79 0.3 0.4 0.5 1.25 1.35 1.45 a 0.6 b 1.55 p1nas 65 60 0. 4 0.5 0. 4 0.5 0. 6 0. 3 0. 4 0.5 0. 6 0.4 0. 5 0.6 0. 4 0 .5 0. 3 0.4 0. 5 0.6 0. 3 0.4 0. 5 0.6 0. 4 0.5 Fig. 3: Simulated contours. (i) and (ii) shows doping concentrations of Structures A and B. The only difference between 2 structures -- in A, DVTNDLD is separated from STI; in B, overlapped. (iii) and (iv) show electrostatic potentials under same bias conditions with Vgs around Vt. For the same path from Point d to Point c, the difference on voltage drop can be 50% between two structures. 0.3 0.4 0.5 0.79 0.6 0.3 0.4 0.5 1.25 1.35 1.45 a 0. 6 b 1.55 p1nas Fig. 4: Plot of Vt, Id-jump ratio (ratio of Id at 24V Vds and Id at 5V Vds when Vgs is -2.1V), BV-off and Rsp0 (Rsp at 0V Vgs) results versus structure variables. The unit of Rsp0 is mOhm*mm^2. The unit is um for Variables p1nas, b and a. When p1nas > 0.95 um, p1nas = 0.95um + b. Fig. 5: TLP results measured on the optimized device structure.