Quad Precision, High Speed Operational Amplifier OP467 PIN CONFIGURATIONS High slew rate: 170 V/μs Wide bandwidth: 28 MHz Fast settling time: <200 ns to 0.01% Low offset voltage: <500 μV Unity-gain stable Low voltage operation: ±5 V to ±15 V Low supply current: <10 mA Drives capacitive loads OUT A 1 14 OUT D –IN A 2 + 13 –IN D + 12 +IN D +IN A 3 OP467 +IN B 5 + –IN B 6 11 V– 10 +IN C + V+ 4 OUT B 7 9 –IN C 8 OUT C The dc performance of the OP467 includes less than 0.5 mV of offset, a voltage noise density below 6 nV/√Hz, and a total supply current under 10 mA. The common-mode rejection ratio (CMRR) is typically 85 dB. The power supply rejection ratio (PSRR) is typically 107 dB. PSRR is maintained to better than 40 dB with input frequencies as high as 1 MHz. The low offset and drift plus high speed and low noise make the OP467 usable in applications such as high speed detectors and instrumentation. 14 +IN D NC OUT D NC OP467 V+ 6 (TOP VIEW) NC 7 13 V– –IN D –IN A +IN D 17 +IN B 8 12 +IN C 16 V– 15 NC 14 +IN C 11 –IN C 10 OUT C 9 NC NC = NO CONNECT 9 10 11 12 13 –IN C 8 18 NC 5 NC NC +IN A 4 OUT C –IN B 6 OUT B 7 OP467 20 19 –IN B V+ 4 +IN B 5 1 00302-003 15 –IN D 2 NC = NO CONNECT Figure 2. 16-Lead SOIC (S Suffix) Figure 3. 20-Terminal LCC (RC Suffix) V+ +IN OUT –IN V– 00302-004 The internal compensation of the OP467 ensures stable unitygain operation, and it can drive large capacitive loads without oscillation. With a gain bandwidth product of 28 MHz driving a 30 pF load, output slew rate is 170 V/μs, and settling time to 0.01% in less than 200 ns, the OP467 provides excellent dynamic accuracy in high speed data acquisition systems. The channel-to-channel separation is typically 60 dB at 10 MHz. –IN A 2 +IN A 3 3 OUT B The OP467 is a quad, high speed, precision operational amplifier. It offers the performance of a high speed op amp combined with the advantages of a precision op amp in a single package. The OP467 is an ideal choice for applications where, traditionally, more than one op amp was used to achieve this level of speed and precision. 16 OUT D 00302-002 GENERAL DESCRIPTION OUT A 1 OUT A Figure 1. 14-Lead CERDIP (Y Suffix) and 14-Lead PDIP (P Suffix) APPLICATIONS High speed image display drivers High frequency active filters Fast instrumentation amplifiers High speed detectors Integrators Photo diode preamps 00302-001 FEATURES Figure 4. Simplified Schematic The OP467 is specified for operation from ±5 V to ±15 V over the extended industrial temperature range (−40°C to +85°C) and is available in a 14-lead PDIP, a 14-lead CERDIP, a 16-lead SOIC, and a 20-terminal LCC. Contact your local sales office for the MIL-STD-883 data sheet and availability. Rev. * Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©3–20 Analog Devices, Inc. All rights reserved. OP467 TABLE OF CONTENTS Features .............................................................................................. 1 Output Short-Circuit Performance .......................................... 13 Applications ....................................................................................... 1 Unused Amplifiers ..................................................................... 13 General Description ......................................................................... 1 PCB Layout Considerations ...................................................... 13 Pin Configurations ........................................................................... 1 Grounding ................................................................................... 13 Revision History ............................................................................... 2 Power Supply Considerations ................................................... 13 Specifications..................................................................................... 3 Signal Considerations ................................................................ 13 Electrical Characteristics ............................................................. 3 Phase Reversal ............................................................................ 14 Wafer Test Limits .......................................................................... 5 Saturation Recovery Time ......................................................... 14 Absolute Maximum Ratings............................................................ 6 High Speed Instrumentation Amplifier .................................. 14 Thermal Resistance ...................................................................... 6 2 MHz Biquad Band-Pass Filter ............................................... 15 Dice Characteristics ..................................................................... 6 Fast I-to-V Converter ................................................................ 16 ESD Caution .................................................................................. 6 OP467 SPICE Marco-Model ..................................................... 17 Typical Performance Characteristics ............................................. 7 Outline Dimensions ....................................................................... 19 Applications Information .............................................................. 13 Ordering Guide .......................................................................... 20 REVISION HISTORY 4/10—Rev. H to Rev. I Deleted Endnote 2 From Table 1 .................................................... 3 8/09—Rev. G to Rev. H Changes to Table 4 ............................................................................ 6 4/09—Rev. F to Rev. G Changes to Power Supply Considerations Section..................... 13 3/04—Rev. D to Rev. E Changes to TPC 1 ..............................................................................5 Changes to Ordering Guide .............................................................4 Updated Outline Dimensions ....................................................... 16 4/01—Rev. C to Rev. D Footnote added to Power Supply.....................................................2 Footnote added to Max Ratings ......................................................4 Edits to Power Supply Considerations Section........................... 11 5/07—Rev. E to Rev. F Updated Format .................................................................. Universal Changes to General Description .................................................... 1 Changes to Table 1 ............................................................................ 3 Changes to Table 2 ............................................................................ 4 Changes to Table 3 ............................................................................ 5 Updated Outline Dimensions ....................................................... 19 Changes to Ordering Guide .......................................................... 20 Rev. I | Page 2 of 20 OP467 SPECIFICATIONS ELECTRICAL CHARACTERISTICS @ VS = ±15.0 V, TA = 25°C, unless otherwise noted. Table 1. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Conditions Min VOS Input Bias Current IB Input Offset Current IOS Common-Mode Rejection Large Signal Voltage Gain CMR CMR AVO Offset Voltage Drift Bias Current Drift Long-Term Offset Voltage Drift1 ΔVOS/ΔT ΔIB/ΔT ΔVOS/ΔT −40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, −40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, −40°C ≤ TA ≤ +85°C VCM = ±12 V VCM = ±12 V, −40°C ≤ TA ≤ +85°C RL = 2 kΩ RL = 2 kΩ, −40°C ≤ TA ≤ +85°C 80 80 83 77.5 Typ Max Unit 0.2 0.5 1 600 700 100 150 mV mV nA nA nA nA dB dB dB dB μV/°C pA/°C μV 150 150 10 10 90 88 86 3.5 0.2 750 OUTPUT CHARACTERISTICS Output Voltage Swing VO RL = 2 kΩ RL = 2 kΩ, −40°C ≤ TA ≤ +85°C ±13.0 ±12.9 ±13.5 ±13.12 V V POWER SUPPLY Power Supply Rejection Ratio PSRR ±4.5 V ≤ VS ≤ ±18 V −40°C ≤ TA ≤ +85°C VO = 0 V VO = 0 V, −40°C ≤ TA ≤ +85°C 96 86 120 115 8 dB dB mA mA V Supply Current ISY Supply Voltage Range VS DYNAMIC PERFORMANCE Gain Bandwidth Product Slew Rate Full-Power Bandwidth Settling Time Phase Margin Input Capacitance Common Mode Differential NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density 1 GBP SR BWρ tS θ0 eN p-p eN iN ±4.5 AV = +1, CL = 30 pF VIN = 10 V step, RL = 2 kΩ, CL = 30 pF AV = +1 AV = −1 VIN = 10 V step To 0.01%, VIN = 10 V step f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz 125 28 MHz 170 350 2.7 200 45 V/μs V/μs MHz ns Degrees 2.0 1.0 pF pF 0.15 6 0.8 μV p-p nV/√Hz pA/√Hz Long-term offset voltage drift is guaranteed by 1000 hrs. Life test performed on three independent wafer lots at 125°C, with an LTPD of 1.3. Rev. I | Page 3 of 20 10 13 ±18 OP467 @ VS = ±5.0 V, TA = 25°C, unless otherwise noted. Table 2. Parameter INPUT CHARACTERISTICS Offset Voltage Symbol Min VOS Input Bias Current IB Input Offset Current IOS Common-Mode Rejection CMR CMR AVO Large Signal Voltage Gain Conditions −40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, −40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, −40°C ≤ TA ≤ +85°C VCM = ±2.0 V VCM = ±2.0 V, −40°C ≤ TA ≤ +85°C RL = 2 kΩ RL = 2 kΩ, −40°C ≤ TA ≤ +85°C Typ Max Unit 0.3 0.5 1 600 700 100 150 3.5 0.2 mV mV nA nA nA nA dB dB dB dB μV/°C pA/°C 125 150 20 76 76 80 74 Offset Voltage Drift Bias Current Drift OUTPUT CHARACTERISTICS Output Voltage Swing VO RL = 2 kΩ RL = 2 kΩ, −40°C ≤ TA ≤ +85°C ±3.0 ±3.0 ±3.5 ±3.20 V V POWER SUPPLY Power Supply Rejection Ratio PSRR ±4.5 V ≤ VS ≤ ±5.5 V −40°C ≤ TA ≤ +85°C VO = 0 V VO = 0 V, −40°C ≤ TA ≤ +85°C 92 83 107 105 8 dB dB mA mA Supply Current DYNAMIC PERFORMANCE Gain Bandwidth Product Slew Rate Full-Power Bandwidth Settling Time Phase Margin NOISE PERFORMANCE Voltage Noise Voltage Noise Density Current Noise Density ΔVOS/ΔT ΔIB/ΔT 85 80 83 ISY GBP SR BWρ tS θ0 eN p-p eN iN AV = +1 VIN = 5 V step, RL = 2 kΩ, CL = 39 pF AV = +1 AV = −1 VIN = 5 V step To 0.01%, VIN = 5 V step f = 0.1 Hz to 10 Hz f = 1 kHz f = 1 kHz Rev. * | Page 4 of 20 10 12 22 MHz 90 90 2.5 280 45 V/μs V/μs MHz ns Degrees 0.15 7 0.8 μV p-p nV/√Hz pA/√Hz OP467 WAFER TEST LIMITS 1 @ VS = ±15.0 V, TA = 25°C, unless otherwise noted. Table 3. Parameter Offset Voltage Input Bias Current Input Offset Current Input Voltage Range 2 Common-Mode Rejection Ratio Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Range Supply Current Symbol VOS IB IOS Conditions CMRR PSRR AVO VO ISY VCM = ±12 V V = ±4.5 V to ±18 V RL = 2 kΩ RL = 2 kΩ VO = 0 V, RL = ∞ VCM = 0 V VCM = 0 V 1 Limit ±0.5 600 100 ±12 80 96 83 ±13.0 10 Unit mV max nA max nA max V min/max dB min dB min dB min V min mA max Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult sales to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 2 Guaranteed by CMR test. Rev. * | Page 5 of 20 OP467 ABSOLUTE MAXIMUM RATINGS Table 4. −65°C to +175°C −65°C to +150°C −55°C to +125°C −40°C to +85°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL RESISTANCE θJA is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 5. −65°C to +175°C −65°C to +150°C 300°C Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For supply voltages less than ±18 V, the absolute maximum input voltage is equal to the supply voltage. θJA1 94 76 88 78 Package Type 14-Lead CERDIP (Y) 14-Lead PDIP (P) 16-Lead SOIC (S) 20-Terminal LCC (RC) θJC 10 33 23 33 Unit °C/W °C/W °C/W °C/W 1 θJA is specified for the worst-case conditions, that is, θJA is specified for device in socket for CERDIP, PDIP, and LCC packages, and θJA is specified for device soldered in circuit board for the SOIC package. –IN A 2 OUT D DICE CHARACTERISTICS OUT A 1 14 +IN A 3 V+ 13 –IN D 12 +IN D 4 11 V– +IN B 5 6 7 8 9 Figure 5. 0.111 Inch × 0.100 Inch DIE Size, 11,100 sq. mils, Substrate Connected to V+, 165 Transistors ESD CAUTION Rev. * | Page 6 o f 20 –IN C 00302-005 –IN B 10 +IN C OUT C 1 Rating ±18 V ±18 V ±26 V Limited OUT B Parameter 1 Supply Voltage Input Voltage 2 Differential Input Voltage2 Output Short-Circuit Duration Storage Temperature Range 14-Lead CERDIP and 20-Terminal LCC 14-Lead PDIP and 16-Lead SOIC Operating Temperature Range OP467A OP467G Junction Temperature Range 14-Lead CERDIP and 20-Terminal LCC 14-Lead PDIP and 16-Lead SOIC Lead Temperature (Soldering, 60 sec) OP467 TYPICAL PERFORMANCE CHARACTERISTICS 100 80 40 30 20 –90 PHASE –135 0 –180 –10 –20 1k 10k 100k 1M 10M 40 AVCL = +10 20 AVCL = +1 00302-006 10 AVCL = +100 60 00302-009 GAIN IMPEDANCE (Ω) 50 80 PHASE SHIFT (Degrees) 60 OPEN-LOOP GAIN (dB) VS = ±15V TA = 25°C VS = ±15V RL = 1MΩ CL = 30pF 70 0 100 100M 1k 10k 100k 1M FREQUENCY (Hz) FREQUENCY (Hz) Figure 6. Open-Loop Gain, Phase vs. Frequency Figure 9. Closed-Loop Output Impedance vs. Frequency 80 VS = ±15V TA = 25°C 0.3 VS = ±5V 0.2 GAIN ERROR (dB) 40 20 0.1 0.0 VS = ±15V –0.1 –0.2 –0.3 00302-007 0 –20 10k 100k 1M 10M 00302-010 CLOSED-LOOP GAIN (dB) 60 0 100k 100M 3.4 1M 5.8 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 7. Closed-Loop Gain vs. Frequency Figure 10. Gain Error vs. Frequency 25 30 AVCL = –1 25 15 TA = +25°C 10 TA = –55°C 5 0 0 ±5 ±10 ±15 ±20 AVCL = +1 20 15 10 5 0 1k VS = ±15V TA = 25°C RL = 2kΩ 00302-011 MAXIMUM OUTPUT SWING (V) TA = +125°C 00302-008 OPEN-LOOP GAIN (V/mV) 20 10k 100k 1M FREQUENCY (Hz) SUPPLY VOLTAGE (V) Figure 11. Maximum VOUT Swing vs. Frequency Figure 8. Open-Loop Gain vs. Supply Voltage Rev. * | Page 7 of 20 10M OP467 12 60 VS = ±5V TA = 25°C RL = 2kΩ 50 AVCL = +1 OVERSHOOT (%) 8 AVCL = –1 6 4 40 30 20 10k 100k 1M 00302-015 10 2 0 1k 0 10M 200 0 400 FREQUENCY (Hz) 1000 1200 1400 1600 Figure 15. Small Signal Overshoot vs. Load Capacitance 120 60 VS = ±15V TA = 25°C 100 VS = ±15V RL = 2kΩ VVIN = 100mV p-p 50 OVERSHOOT (%) 80 60 40 AVCL = +1 AVCL = –1 40 30 20 10 0 1k 10k 100k 1M 00302-016 20 00302-013 COMMON-MODE REJECTION (V) 800 600 LOAD CAPACITANCE (pF) Figure 12. Maximum VOUT Swing vs. Frequency 0 10M 200 0 400 FREQUENCY (Hz) 1000 1200 1400 1600 Figure 16. Small Signal Overshoot vs. Load Capacitance 120 60 VS = ±15V TA = 25°C 100 VS = ±15V 50 40 30 GAIN (dB) 80 60 40 1000pF 500pF 20 200pF 10000pF 10 0 –10 CIN = NETWORK ANALYZER 00302-014 1k 10k 100k 00302-017 –20 20 0 100 800 600 LOAD CAPACITANCE (pF) Figure 13. Common-Mode Rejection vs. Frequency POWER SUPPLY REJECTION (dB) AVCL = +1 AVCL = –1 00302-012 MAXIMUM OUTPUT SWING (V) 10 VS = ±15V RL = 2kΩ VVIN = 100mV p-p –30 –40 10k 1M 100k 1M 10M 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 14. Power-Supply Rejection vs. Frequency Figure 17. Noninverting Gain vs. Capacitive Loads Rev. * | Page 8 of 20 OP467 4 0 VS = ±15V VS = ±15V VIN = ±5V CL = 50pF 3 –20 2 VOUT ERROR (mV) –30 –40 –50 –60 –70 1 0 –1 –2 –80 1k 10k 1M 100k 10M 00302-021 –90 –100 100 –3 00302-018 CHANNEL SEPARATION (dB) –10 –4 100M 0 100 200 Figure 18. Channel Separation vs. Frequency 500 4 ±5V ≤ VS ≤ 15V VS = ±15V VIN = ±5V CL = 50pF 3 10 2 VOUT ERROR (mV) 8 6 4 1 0 –1 –2 2 0 10 1 100 00302-022 –3 00302-019 INPUT CURRENT NOISE DENSITY (pA/√Hz) 400 Figure 21. Settling Time, Negative Edge 12 –4 1k 0 100 200 FREQUENCY (Hz) 400 500 Figure 22. Settling Time, Positive Edge 20 100 TA = 25°C 00302-020 10 1 10 100 1k 10k 10 5 0 –5 –10 –15 00302-023 INPUT VOLTAGE RANGE (V) 15 1.0 0.1 300 TIME (ns) Figure 19. Input Current Noise Density vs. Frequency VOLTAGE NOISE DENSITY (nV/√Hz) 300 TIME (ns) FREQUENCY (Hz) –20 0 FREQUENCY (Hz) ±5 ±10 ±15 SUPPLY VOLTAGE (V) Figure 20. Voltage Noise Density vs. Frequency Figure 23. Input Voltage Range vs. Supply Voltage Rev. * | Page 9 of 20 ±20 OP467 500 50 40 30 VS = ±15V TA = 25°C 1252 × OP AMPS VS1 = ±15V VS2 = ±5V RL = 10kΩ CL = 50pF 400 VS1 = ±15V 10 300 UNITS 0 200 –10 VS2 = ±5V –20 100 00302-024 –30 –40 –50 10k 100k 1M 10M 0 –100 100M 00302-027 GAIN (dB) 20 –50 0 150 200 250 300 350 400 350 400 4.5 5.0 500 VS = ±5V TA = 25°C 1252 × OP AMPS VS = ±15V TA = 25°C 400 10 8 POSITIVE SWING 300 UNITS OUTPUT SWING (V) 12 100 Figure 27. Input Offset Voltage Distribution Figure 24. Noninverting Gain vs. Supply Voltage 14 50 INPUT OFFSET VOLTAGE (VOS µV) FREQUENCY (Hz) 6 200 NEGATIVE SWING 4 00302-025 0 10 100 1k 0 –100 10k 00302-028 100 2 –50 Figure 25. Output Swing vs. Load Resistance 5 50 100 150 200 250 300 Figure 28. Input Offset Voltage Distribution 500 VS = ±15V TA = 25°C VS = ±15V TA = 25°C 1252 × OP AMPS 400 4 POSITIVE SWING 300 UNITS 3 NEGATIVE SWING 2 200 0 10 100 1k 10k 0 00302-029 100 1 00302-026 OUTPUT SWING (V) 0 INPUT OFFSET VOLTAGE (VOS µV) LOAD RESISTANCE (Ω) 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 TC VOS (µV/°C) LOAD RESISTANCE (Ω) Figure 26. Output Swing vs. Load Resistance Figure 29. TC VOS Distribution Rev. * | Page 10 of 20 4.0 OP467 500 400 VS = ±5V TA = 25°C 1252 × OP AMPS 350 400 VS = ±5V RL = 2kΩ AVCL = +1 SLEW RATE (V/µs) 300 UNITS 300 200 200 +SR 150 100 100 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 –SR 0 –75 5.0 00302-033 50 00302-030 0 250 –50 –25 TC VOS (µV/°C) Figure 30. TC VOS Distribution 29.0 28.0 ФM 45 27.5 25 50 75 27.0 125 100 VS = ±15V RL = 2kΩ AVCL = –1 100 125 500 +SR 450 400 350 300 250 –75 –50 –25 0 25 50 75 TEMPERATURE (°C) Figure 31. Phase Margin and Gain Bandwidth vs. Temperature Figure 34. Slew Rate vs. Temperature 400 400 VS = ±5V RL = 2kΩ AVCL = –1 VS = ±15V RL = 2kΩ AVCL = +1 350 300 –SR 200 +SR 150 +SR 250 200 –SR 150 100 50 50 00302-032 100 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) 0 –75 00302-035 SLEW RATE (V/µs) 300 250 0 –75 125 –SR TEMPERATURE (°C) 350 100 00302-034 50 0 75 550 SLEW RATE (V/µs) VS = ±5V RL = 2kΩ 600 GAIN BANDWIDTH PRODUCT (MHz) 28.5 –25 50 650 00302-031 55 SLEW RATE (V/µs ) PHASE MARGIN (Degrees) GBW –50 25 Figure 33. Slew Rate vs. Temperature 60 40 –75 0 TEMPERATURE (°C) –50 –25 0 25 50 75 TEMPERATURE (°C) Figure 32. Slew Rate vs. Temperature Figure 35. Slew Rate vs. Temperature Rev. * | Page 11 of 20 100 125 OP467 5 6 3 0.1% 4 2 2 1 0 0 –5 –2 –4 –4 0.1% –3 –6 0.1% –8 –10 0 100 VS = ±15V –2 200 300 160 INPUT BIAS CURRENT (nA) 0.1% 200 4 OUTPUT STEP FOR ±5V SUPPLY (V) OUTPUT STEP FOR ±15V SUPPLY (V) 8 00302-036 RF = 5kΩ TA = 25°C –1 400 120 90 40 0 –75 00302-038 10 –50 –25 0 25 50 75 100 125 TEMPERATURE (°C) SETTLING TIME (ns) Figure 36. Output Step vs. Settling Time Figure 38. Input Bias Current vs. Temperature 25 VS = ±15V 10 INPUT OFFSET CURRENT (nA) TA = +125°C TA = +25°C 6 TA = –55°C 4 15 10 5 0 0 ±5 ±10 ±15 ±20 0 –75 00302-039 2 00302-037 SUPPLY CURRENT (mA) 8 20 –50 –25 0 25 50 75 100 TEMPERATURE (°C) SUPPLY VOLTAGE (V) Figure 39. Input Offset Current vs. Temperature Figure 37. Supply Current vs. Supply Voltage Rev. * | Page 12 of 20 125 OP467 APPLICATIONS INFORMATION OUTPUT SHORT-CIRCUIT PERFORMANCE To achieve a wide bandwidth and high slew rate, the OP467 output is not short-circuit protected. Shorting the output to ground or to the supplies may destroy the device. For safe operation, the output load current should be limited so that the junction temperature does not exceed the absolute maximum junction temperature. The maximum internal power dissipation can be calculated by PD = TJ max − TA θ JA where: TJ and TA are junction and ambient temperatures, respectively. PD is device internal power dissipation. θJA is the packaged device thermal resistance given in the data sheet. On the other hand, ceramic chip capacitors have excellent ESR and effective series inductance (ESL) performance at higher frequencies, and because of their small size, they can be placed very close to the device pin, further reducing the stray inductance. Best results are achieved by using a combination of these two capacitors. A 5 μF to 10 μF tantalum parallel capacitor with a 0.1 μF ceramic chip capacitor is recommended. If additional isolation from high frequency resonances of the power supply is needed, a ferrite bead should be placed in series with the supply lines between the bypass capacitors and the power supply. Note that addition of the ferrite bead introduces a new pole and zero to the frequency response of the circuit and could cause unstable operation if it is not selected properly. +VS + 10µF TANTALUM 0.1µF CERAMIC CHIP UNUSED AMPLIFIERS It is recommended that any unused amplifiers in the quad package be connected as a unity-gain follower with a 1 kΩ feedback resistor with noninverting input tied to the ground plain. 10µF TANTALUM PCB LAYOUT CONSIDERATIONS –VS Satisfactory performance of a high speed op amp largely depends on a good PCB layout. To achieve the best dynamic performance, follow the high frequency layout technique. 00302-040 0.1µF CERAMIC CHIP Figure 40. Recommended Power Supply Bypass SIGNAL CONSIDERATIONS GROUNDING A good ground plain is essential to achieve the optimum performance in high speed applications. It can significantly reduce the undesirable effects of ground loops and IR drops by providing a low impedance reference point. Best results are obtained with a multilayer board design with one layer assigned to the ground plain. To maintain a continuous and low impedance ground, avoid running any traces on this layer. POWER SUPPLY CONSIDERATIONS In high frequency circuits, device lead length introduces an inductance in series with the circuit. This inductance, combined with stray capacitance, forms a high frequency resonance circuit. Poles generated by these circuits cause gain peaking and additional phase shift, reducing the phase margin of the op amp and leading to an unstable operation. A practical solution to this problem is to reduce the resonance frequency low enough to take advantage of the power supply rejection of the amplifier. This is easily done by placing capacitors across the supply line and the ground plane as close as possible to the device pin. Because capacitors also have internal parasitic components, such as stray inductance, selecting the right capacitor is important. To be effective, they should have low impedance over the frequency range of interest. Tantalum capacitors are an excellent choice for their high capacitance/size ratio, but their effective series resistance (ESR) increases with frequency making them less effective. Input and output traces need special attention to assure a minimum stray capacitance. Input nodes are very sensitive to capacitive reactance, particularly when connected to a high impedance circuit. Stray capacitance can inject undesirable signals from a noisy line into a high impedance input. Protect high impedance input traces by providing guard traces around them, which also improves the channel separation significantly. Additionally, any stray capacitance in parallel with the input capacitance of the op amp generates a pole in the frequency response of the circuit. The additional phase shift caused by this pole reduces the gain margin of the circuit. If this pole is within the gain range of the op amp, it causes unstable performance. To reduce these undesirable effects, use the lowest impedance where possible. Lowering the impedance at this node places the poles at a higher frequency, far above the gain range of the amplifier. Stray capacitance on the PCB can be reduced by making the traces narrow and as short as possible. Further reduction can be realized by choosing a smaller pad size, increasing the spacing between the traces, and using PCB material with a low dielectric constant insulator (dielectric constant of some common insulators: air = 1, Teflon® = 2.2, and FR4 = 4.7, with air being an ideal insulator). Removing segments of the ground plane directly under the input and output pads is recommended. Rev. * | Page 13 of 20 OP467 Outputs of high speed amplifiers are very sensitive to capacitive loads. A capacitive load introduces a pair of pole and zero to the frequency response of the circuit, reducing the phase margin, leading to unstable operation or oscillation. DLY 9.824µs 100 90 Generally, it is good design practice to isolate the output of the amplifier from any capacitive load by placing a resistor between the output of the amplifier and the rest of the circuits. A series resistor of 10 Ω to 100 Ω is normally sufficient to isolate the output from a capacitive load. 10 The OP467 is internally compensated to provide stable operation and is capable of driving large capacitive loads without oscillation. 5V 5V 00302-042 0% 20ns Figure 42. Saturation Recovery Time, Positive Rail Sockets are not recommended because they increase the lead inductance/capacitance and reduce the power dissipation of the package by increasing the thermal resistance of the leads. If sockets must be used, use Teflon or pin sockets with the shortest possible leads. DLY 4.806µs 100 90 PHASE REVERSAL The OP467 is immune to phase reversal; its inputs can exceed the supply rails by a diode drop without any phase reversal. ΔV1 10 15.8V 0% 5V 5V 00302-043 100 OUTPUT 90 20ns Figure 43. Saturation Recovery Time, Negative Rail HIGH SPEED INSTRUMENTATION AMPLIFIER 10 10V 200µs Figure 41. No Phase Reversal (AV = +1) SATURATION RECOVERY TIME The OP467 has a fast and symmetrical recovery time from either rail. This feature is very useful in applications such as high speed instrumentation and measurement circuits, where the amplifier is frequently exposed to large signals that overload the amplifier. The circuit gain is set by RG. A 2 kΩ resistor sets the circuit gain to 2; for unity gain, remove RG. For any other gain settings, use the following formula G = 2/RG (Resistor Value is in kΩ) RC is used for adjusting the dc common-mode rejection, and CC is used for ac common-mode rejection adjustments. –VIN CC 2kΩ 1kΩ RG 2kΩ 10kΩ 2kΩ OUTPUT 1kΩ 1.9kΩ 10kΩ 5pF RC 200Ω 10T +VIN Figure 44. A High Speed Instrumentation Amplifier Rev. * | Page 14 of 20 00302-044 10V 00302-041 INTPUT 0% The OP467 performance lends itself to a variety of high speed applications, including high speed precision instrumentation amplifiers. Figure 44 represents a circuit commonly used for data acquisition, CCD imaging, and other high speed applications. OP467 2 MHz BIQUAD BAND-PASS FILTER 0.01% 10V STEP VS = ±15V NEG SLOPE The circuit in Figure 48 is commonly used in medical imaging ultrasound receivers. The 30 MHz bandwidth is sufficient to accurately produce the 2 MHz center frequency, as the measured response shows in Figure 49. When the bandwidth of the op amp is too close to the center frequency of the filter, the internal phase shift of the amplifier causes excess phase shift at 2 MHz, which alters the response of the filter. In fact, if the chosen op amp has a bandwidth close to 2 MHz, the combined phase shift of the three op amps causes the loop to oscillate. 2.5mV 00302-045 –2.5mV Figure 45. Instrumentation Amplifier Settling Time to 0.01% for a 10 V Step Input (Negative Slope) Careful consideration must be given to the layout of this circuit as with any other high speed circuit. If the phase shift introduced by the layout is large enough, it can alter the circuit performance, or worse, cause oscillation. 0.01% 10V STEP VS = ±15V POS SLOPE R6 1kΩ C1 50pF R2 2kΩ 2.5mV –2.5mV R1 3kΩ 1/4 OP467 C2 50pF R3 2kΩ R5 2kΩ 1/4 OP467 1/4 OP467 1/4 OP467 VOUT 00302-048 00302-046 2kΩ R4 2kΩ VIN Figure 46. Instrumentation Amplifier Settling Time to 0.01% for a 10 V Step Input (Positive Slope) Figure 48. 2 MHz Biquad Filter +VS + AD9617 2kΩ 1kΩ –10 ERROR TO SCOPE GAIN (dB) –20 –VS 61.9Ω 549Ω –30 00302-049 TO IN-AMP OUTPUT 0 + 00302-047 TO INPUT 2kΩ –40 Figure 47. Settling Time Measurement Circuit 10k 100k 1M 10M FREQUENCY (Hz) Figure 49. Biquad Filter Response Rev. * | Page 15 of 20 100M OP467 +5V C1 10pF 2 1 OUT A OP467 3 +15V 0.1µF 4 OUT B 7 6 OP467 11 5 C2 10pF +10V 0.1µF –15V 1 VDD DAC8408 2 VREF A 3 RFBA +10V DGND 28 VREF C 27 RFBC 26 C3 10pF 4 IOUT 1A IOUT 1C 25 13 5 IOUT 2A/ IOUT 2B IOUT 2C/ IOUT 2D 24 12 6 IOUT 1B IOUT 1D 23 7 RFBB 8 VREF B 9 RFBD 22 DB0 (LSB) DS2 20 DS1 19 11 DB2 R/W 18 12 DB3 A/B 17 13 DB4 (MSB) DB7 16 14 DB5 DB6 15 14 OUT D OP467 8 OUT C 9 VREF D 21 10 DB1 OP467 C4 10pF +10V 10 DIGITAL CONTROL SIGNALS 00302-050 +10V Figure 50. Quad DAC Unipolar Operation FAST I-TO-V CONVERTER 251.0ns The fast slew rate and fast settling time of the OP467 are well suited to the fast buffers and I-to-V converters used in a variety of applications. The circuit in Figure 50 is a unipolar quad DAC consisting of only two ICs. The current output of the DAC8408 is converted to a voltage by the OP467 configured as an I-to-V converter. This circuit is capable of settling to 0.1% within 200 ns. Figure 51 and Figure 52 show the full-scale settling time of the outputs. To obtain reliable circuit performance, keep the traces from the IOUT of the DAC to the inverting inputs of the OP467 short to minimize parasitic capacitance. 100 90 10 2V 260.0ns 50mV 100ns 00302-052 0% Figure 52. Rising Edge Output Settling Time DAC8408 RFB 100 90 DC OFFSET 3pF IOUT 2kΩ I-V OP467 2kΩ AD847 1kΩ 50kΩ 60.4kΩ 10 2V 50mV 100ns 00302-051 0% Figure 53. DAC VOUT Settling Time Circuit Figure 51. Falling Edge Output Settling Time Rev. * | Page 16 of 20 00302-053 604Ω OP467 OP467 SPICE MARCO-MODEL * Node assignments noninverting input inverting input positive supply negative supply output * . SUBCKT OP467 1 2 99 50 27 * * INPUT STAGE * I1 4 10E–3 5 0 CIN 1 2 1E–12 IOS 1 2 5E–9 Q1 5 2 8 QN Q2 6 7 9 QN R3 99 5 185 . 681 R4 99 6 185 . 681 R5 8 4 180 . 508 R6 9 4 180 . 508 EOS 7 1 POLY (1) (14,20) 50E–6 EREF 98 0 (20,0) 1 * * GAIN STAGE AND DOMINANT POLE AT 1.5 kHz * R7 10 98 3 . 714E6 C2 10 98 28 . 571E–12 G1 98 10 (5,6) 5 . 386E–3 V1 99 11 1.6 V2 12 50 1.6 D1 10 11 DX D2 12 10 DX RC 10 28 1 . 4E3 CC 28 27 12E–12 1 * * COMMON-MODE STAGE WITH ZERO AT 1.26 kHz * ECM 13 98 POLY (2) (1, 20) (2,20) 0 0. 5 0 . 5 R8 13 14 1E6 R9 14 98 25 . 119 C3 13 14 126 . 721E–12 * *POLE AT 400E6 * R10 15 98 1E6 C4 15 98 0 . 398E–15 G2 98 15 (10,20) 1E–6 * * OUTPUT STAGE * ISY 99 50 –8 . 183E–3 RMP1 99 20 96 . 429E3 RMP2 20 50 96 . 429E3 RO1 99 26 200 RO2 26 50 200 L1 26 27 1E–7 GO1 26 99 (99,15) 5E–3 GO2 50 26 (15,50) 5E–3 G4 23 50 (15,26) 5E–3 G5 24 50 (26,15) 5E–3 V3 21 26 50 V4 26 22 50 D3 15 21 DX D4 22 15 DX D5 99 23 DX D6 99 24 DX D7 50 23 DY D8 50 24 DY * * MODELS USED * . MODEL QN NPN (BF=33.333E3) . MODEL DX D . MODEL DY D (BV=50) . ENDS OP467 Rev. * | Page 17 of 20 OP467 99 99 99 D5 RMP1 D3 20 15 21 D4 98 RMP2 G4 N– 27 2 26 22 23 CIN 24 D7 D8 1 R02 G5 N+ G02 50 50 Q2 8 R5 RC 28 7 Rev. * | Page 18 of 20 27 C3 R6 4 –+ EOS R7 G1 EREF + – C2 98 13 ECM + – R8 14 R9 D2 12 V2 + – Figure 55. SPICE Macro-Model Input and Gain Stage Figure 54. SPICE Macro-Model Output Stage CC 10 9 I1 50 11 D1 6 Q1 IOS V4 –+ C4 EREF + – 5 R01 L1 15 R10 G2 V3 +– + V1 – R4 R3 G01 00302-054 ISY D6 50 00302-055 99 OP467 OUTLINE DIMENSIONS 0.775 (19.69) 0.750 (19.05) 0.735 (18.67) 14 8 1 7 0.280 (7.11) 0.250 (6.35) 0.240 (6.10) 0.325 (8.26) 0.310 (7.87) 0.300 (7.62) 0.100 (2.54) BSC 0.060 (1.52) MAX 0.210 (5.33) MAX 0.015 (0.38) MIN 0.150 (3.81) 0.130 (3.30) 0.110 (2.79) SEATING PLANE 0.015 (0.38) GAUGE PLANE 0.430 (10.92) MAX 0.005 (0.13) MIN 0.014 (0.36) 0.010 (0.25) 0.008 (0.20) 0.070 (1.78) 0.050 (1.27) 0.045 (1.14) COMPLIANT TO JEDEC STANDARDS MS-001 CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS. Figure 56. 14-Lead Plastic Dual In-Line Package [PDIP] (N-14) P-Suffix Dimensions shown in inches and (millimeters) 0.005 (0.13) MIN 14 1 PIN 1 0.098 (2.49) MAX 8 7 0.310 (7.87) 0.220 (5.59) 0.100 (2.54) BSC 0.785 (19.94) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.320 (8.13) 0.290 (7.37) 0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN SEATING 0.070 (1.78) PLANE 0.030 (0.76) 15° 0° 0.015 (0.38) 0.008 (0.20) CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 57. 14-Lead Ceramic Dual In-Line Package [CERDIP] (Q-14) Y-Suffix Dimensions shown in inches and (millimeters) Rev. I | Page 19 of 20 070606-A 0.022 (0.56) 0.018 (0.46) 0.014 (0.36) 0.195 (4.95) 0.130 (3.30) 0.115 (2.92) OP467 10.50 (0.4134) 10.10 (0.3976) 9 16 7.60 (0.2992) 7.40 (0.2913) 1 8 1.27 (0.0500) BSC 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 0.51 (0.0201) 0.31 (0.0122) 10.65 (0.4193) 10.00 (0.3937) 0.75 (0.0295) 0.25 (0.0098) 2.65 (0.1043) 2.35 (0.0925) SEATING PLANE 45° 8° 0° 1.27 (0.0500) 0.40 (0.0157) 0.33 (0.0130) 0.20 (0.0079) 032707-B COMPLIANT TO JEDEC STANDARDS MS-013- AA CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. Figure 58. 16-Lead Standard Small Outline Package [SOIC_W] Wide Body (RW-16) S-Suffix Dimensions shown in millimeters and (inches) 0.358 (9.09) 0.342 (8.69) SQ 0.358 (9.09) MAX SQ 0.088 (2.24) 0.054 (1.37) 0.200 (5.08) REF 0.100 (2.54) REF 0.015 (0.38) MIN 0.075 (1.91) REF 0.095 (2.41) 0.075 (1.90) 0.011 (0.28) 0.007 (0.18) R TYP 0.075 (1.91) REF 0.055 (1.40) 0.045 (1.14) 19 18 3 20 4 0.028 (0.71) 0.022 (0.56) 1 BOTTOM VIEW 0.050 (1.27) BSC 8 14 13 9 45° TYP 0.150 (3.81) BSC CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN. 022106-A 0.100 (2.54) 0.064 (1.63) Figure 59. 20-Terminal Ceramic Leadless Chip Carrier [LCC] (E-20-1) RC-Suffix Dimensions shown in inches and (millimeters) ORDERING GUIDE Model1 OP467GP OP467GPZ OP467GS OP467GS-REEL OP467GSZ OP467GSZ-REEL OP467ARC/883C OP467AY/883C OP467GBC 1 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C −55°C to +125°C −55°C to +125°C Package Description 14-Lead PDIP 14-Lead PDIP 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 16-Lead SOIC_W 20-Terminal LCC 14-Lead CERDIP Die Z = RoHS Compliant Part. ©1993–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D00302-0-4/10(I) Rev. I | Page 20 of 20 Package Option N-14 N-14 RW-16 RW-16 RW-16 RW-16 E-20-1 Q-14