a Bipolar/JFET, Audio Operational Amplifier OP176* FEATURES Low Noise: 6 nV/√Hz High Slew Rate: 25 V/µs Wide Bandwidth: 10 MHz Low Supply Current: 2.5 mA Low Offset Voltage: 1 mV Unity Gain Stable SO-8 Package PIN CONNECTIONS 8-Lead Narrow-Body SO (S Suffix) NULL 1 8 NC NULL 1 8 NC –IN 2 7 V+ –IN 2 7 V+ +IN 3 6 OUT +IN 3 APPLICATIONS Line Driver Active Filters Fast Amplifiers Integrators 8-Lead Epoxy DIP (P Suffix) OP176 6 OUT OP176 5 NULL V– 4 V– 4 5 OP-482 NULL 200 µV. This allows the OP176 to be used in many dc coupled or summing applications without the need for special selections or the added noise of additional offset adjustment circuitry. GENERAL DESCRIPTION The output is capable of driving 600 Ω loads to 10 V rms while maintaining low distortion. THD + Noise at 3 V rms is a low 0.0006%. The OP176 is a low noise, high output drive op amp that features the Butler Amplifier front-end. This new front-end design combines both bipolar and JFET transistors to attain amplifiers with the accuracy and low noise performance of bipolar transistors, and the speed and sound quality of JFETs. Total Harmonic Distortion plus Noise equals previous audio amplifiers, but at much lower supply currents. The OP176 is specified over the extended industrial (–40°C to +85°C) temperature range. OP176s are available in both plastic DIP and SO-8 packages. SO-8 packages are available in 2500 piece reels. Many audio amplifiers are not offered in SO-8 surface mount packages for a variety of reasons, however, the OP176 was designed so that it would offer full performance in surface mount packaging. Improved dc performance is also provided with bias and offset currents greatly reduced over purely bipolar designs. Input offset voltage is guaranteed at 1 mV and is typically less than *Protected by U.S. Patent No. 5101126. 7 RB4 RB6 RB7 RB5 RB2 RB3 QB6 QB5 QB4 QB7 CB1 R4 QB3 J1 Q1 Z2 2 Q10 J2 Q2 3 QS1 Q9 RS1 R5 6 JB1 CCB QB2 CC2 Q6 Q5 RS2 QS2 Q4 Q3 QS3 Q8 Q11 CF RB1 R3 R1L R1P1 QB1 Z1 CC1 R1A R1P2 R1S 1 R2P1 Q7 R2L QB9 QB8 R2S R2P2 R2A 5 4 Simplified Schematic REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 OP176–SPECIFICATIONS ELECTRICAL CHARACTERISTICS (@ V = ±15.0 V, T = +25°C unless otherwise noted) S Parameter Symbol INPUT CHARACTERISTICS Offset Voltage Offset Voltage Input Bias Current VOS VOS IB Input Offset Current IOS Input Voltage Range Common-Mode Rejection VCM CMRR Large Signal Voltage Gain AVO Offset Voltage Drift ∆VOS/∆T OUTPUT CHARACTERISTICS Output Voltage Swing VO Output Short Circuit Current ISC POWER SUPPLY Power Supply Rejection Ratio PSRR Supply Current ISY Supply Current ISY Supply Voltage Range VS DYNAMIC PERFORMANCE Slew Rate Gain Bandwidth Product SR GBP AUDIO PERFORMANCE THD + Noise Voltage Noise Density Current Noise Density en in A Conditions Min Typ –40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, –40°C ≤ TA ≤ +85°C VCM = 0 V VCM = 0 V, –40°C ≤ TA ≤ +85°C VCM = ± 10.5 V, –40°C ≤ TA ≤ +85°C RL = 2 kΩ RL = 2 kΩ, –40°C ≤ TA ≤ +85°C RL = 600 Ω –10.5 80 250 175 –13.5 –14.8 ± 25 VS = ± 4.5 V to ± 18 V –40°C ≤ TA ≤ +85°C VS = ± 4.5 V to ± 18 V, VO = 0 V, RL = ∞, –40°C ≤ TA ≤ +85°C VS = ± 22 V, VO = 0 V, RL = ∞, –40°C ≤ TA ≤ +85°C 86 80 VIN = 3 V rms, RL = 2 kΩ, f = 1 kHz f = 1 kHz f = 1 kHz Units 1 1.25 350 400 ± 50 ± 100 +10.5 mV mV nA nA nA nA V 106 dB V/mV V/mV V/mV µV/°C 200 5 RL = 2 kΩ, –40°C ≤ TA ≤ +85°C RL = 600 Ω, VS = ± 18 V RL = 2 kΩ Max ± 50 108 ± 4.5 15 +13.5 +14.8 V V mA dB dB 2.5 mA 2.75 ± 22 mA V 25 10 V/µs MHz 0.001 6 0.5 % nV/√Hz pA/√Hz Specifications subject to change without notice. –2– REV. 0 OP176 WAFER TEST LIMITS (@ V = ±15.0 V, T = +25°C unless otherwise noted) S A Parameter Symbol Offset Voltage Input Bias Current Input Offset Current Input Voltage Range1 Common-Mode Rejection Power Supply Rejection Ratio Large Signal Voltage Gain Output Voltage Range VOS IB IOS VCM CMRR PSRR AVO VO Supply Current ISY Conditions VCM = 0 V VCM = 0 V VCM = ± 10.5 V V = ± 4.5 V to ± 18 V RL = 2 kΩ RL = 2 kΩ VS = ± 18.0 V, RL = 600 Ω VS = ± 22.0 V, VO = 0 V, RL = ∞ VS = ± 4.5 V to ± 18 V, VO = 0 V, RL = ∞ Limit Units 1 350 ± 50 ± 10.5 80 86 250 13.5 14.8 2.75 2.5 mV max nA max nA max V min dB min dB min V/mV min V min V min mA max mA max NOTES Electrical tests and wafer probe to the limits shown. Due to variations in assembly methods and normal yield loss, yield after packaging is not guaranteed for standard product dice. Consult factory to negotiate specifications based on dice lot qualifications through sample lot assembly and testing. 1 Guaranteed by CMR test. ABSOLUTE MAXIMUM RATINGS 1 DICE CHARACTERISTICS Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V Input Voltage2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 18 V Differential Input Voltage2 . . . . . . . . . . . . . . . . . . . . . . . ± 7.5 V Output Short-Circuit Duration to GND . . . . . . . . . . Indefinite Storage Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Operating Temperature Range OP176G . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to +85°C Junction Temperature Range P, S Package . . . . . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Lead Temperature Range (Soldering, 60 sec) . . . . . . . +300°C Package Type θJA 3 θJC Units 8-Pin Plastic DIP (P) 8-Pin SOIC (S) 103 158 43 43 °C/W °C/W V– NULL NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 For input voltages greater than ± 7.5 V limit input current to less than 5 mA. 3 θJA is specified for the worst case conditions, i.e., θJA is specified for device in socket for P-DIP packages; θJA is specified for device soldered in circuit board for SOIC package. NULL OUT V+ –IN +IN OP176 Die Size 0.069 × 0.067 Inch, 4,623 Sq. Mils. Substrate (Die Backside) Is Connected to V–. Transistor Count, 26. ORDERING GUIDE Model Temperature Range Package Description Package Option OP176GP OP176GS OP176GSR OP176GBC –40°C to +85°C –40°C to +85°C –40°C to +85°C +25°C 8-Pin Plastic DIP 8-Pin SOIC SO-8 Reel, 2500 Pieces DICE N-8 SO-8 CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the OP176 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. REV. 0 –3– WARNING! ESD SENSITIVE DEVICE OP176–Typical Characteristics AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA AAAAAAAA 120 30 ±V = ±15V MAXIMUM OUTPUT SWING – Volts ±V = ±15V S ≤–40°C ≤ T ≤ +85°C A 100 80 BASED ON 300 OP AMPS 60 40 20 0 0 1 2 3 4 5 OS – µV/°C µt V C 6 R = 2kΩ L 15 10 5 0 1k 10k 1M 10M Figure 4. Maximum Output Swing vs. Frequency 16 16 ΩVS = ±18V, +VOM, RL = 600Ω VS = ±15V TA = +25°C 14 ΩVS = ±18V, –VOM, RL = 600Ω POSITIVE SWING OUTPUT SWING – Volts 15 ΩVS = ±15V, +VOM, RL = 2kΩ 14 ΩVS = ±15V, –VOM, RL = 2kΩ ΩVS = ±15V, +VOM, RL = 600Ω 13 12 NEGATIVE SWING 10 8 6 4 ΩVS = ±15V, –VOM, RL = 600Ω 12 –50 2 0 –25 0 25 50 75 10 100 100 Figure 2. Output Swing vs. Temperature 10k Figure 5. Maximum Output Swing vs. Load Resistance 2.50 300 ±VS = ±15V V = 0V 250 SUPPLY CURRENT – mA CM 200 150 100 2.25 TA = +85°C 2.00 TA = +25°C 1.75 TA = –40°C 50 0 –50 1k ΩLOAD RESISTANCE – Ω TEMPERATURE – °C INPUT BIAS CURRENT – nA 100k FREQUENCY – Hz Figure 1. Input Offset Voltage Drift Distribution @ ± 15 V ABSOLUTE OUTPUT VOLTAGE – V ΩTA = +25°C 20 8 7 S 25 1.50 –25 0 25 50 75 100 0 ±5± ±10± ±15± ±20± ±25± SUPPLY VOLTAGE – V TEMPERATURE – °C Figure 3. Input Bias Current vs. Temperature Figure 6. Supply Current per Amplifier vs. Supply Voltage –4– REV. 0 OP176 80 120 A POWER SUPPLY REJECTION – dB ABSOLUTE OUTPUT CURRENT – mA T = +25°C ±VS = ±15V 70 SINK 60 SOURCE 50 40 30 20 10 0 –50 0 –25 25 50 75 60 –PSRR 40 20 1k 10k FREQUENCY – Hz TEMPERATURE – °C Figure 7. Short Circuit Current vs. Temperature @ ± 15 V 1750 GAIN 90 40 PHASE 135 20 0 180 PHASE MARGIN = 60° 225 –20 PHASE – Degrees 60 OPEN-LOOP GAIN – V/mV 80 ±VS = ±15V ±VO = ±10V 1500 Ω–GAIN, RL = 2kΩ 1250 1000 +GAIN, RL = 2kΩ 750 –GAIN, RL = 600Ω 500 250 –40 –60 1k 10k 100k 1M 10M 0 –50 100M +GAIN, RL = 600Ω –25 0 FREQUENCY – Hz 25 50 75 100 TEMPERATURE – °C Figure 8. Open-Loop Gain & Phase vs. Frequency Figure 11. Open-Loop Gain vs. Temperature 40 50 TA = +25°C VS = ±15V 40 TA = +25°C VS = ±15V 30 ΩIMPEDANCE – Ω 30 20 10 0 –10 AV = +100 20 AV = +10 10 –20 AV = +1 –30 1k 10k 100k 1M FREQUENCY – Hz 10M 0 100 100M 1k 10k 100k 1M FREQUENCY – Hz Figure 9. Closed-Loop Gain vs. Frequency REV. 0 1M 2000 TA = +25°C VS = ±15V RL = >600Ω 100 GAIN – dB 100k Figure 10. Power Supply Rejection vs. Frequency 120 GAIN – dB S 80 0 100 100 ±V = ±15V +PSRR 100 Figure 12. Closed-Loop Output Impedance vs. Frequency –5– OP176 14 65 ±VS = ±15V VS = ±15V 120 PHASE MARGIN – Degrees COMMON-MODE REJECTION – dB TA = +25°C 100 80 60 40 60 12 PHASE 55 10 GAIN 50 8 20 0 100 1k 10k 100k 45 –75 1M –50 –25 0 FRERQUENCY – Hz 50 75 100 6 125 TEMPERATURE – °C Figure 16. Gain Bandwidth Product & Phase Margin vs. Temperature Figure 13. Common-Mode Rejection vs. Frequency 100 50 ±VS = ±15V ΩRL = 2kΩ 80 V 70 AVCL = 1 IN = 100mVp-p NEGATIVE SWING 40 NEGATIVE SLEW RATE SLEW RATE – V/µs 90 OVERSHOOT – % 25 GAIN BANDWIDTH PRODUCT – MHz 140 60 50 POSITIVE SWING 40 30 30 POSITIVE SLEW RATE 20 V = ±15V S R = 2kΩ L 20 SWING = ±10V 10 SLEW WINDOW = ±5V T = +25°C 10 A 0 0 100 200 300 400 500 600 700 LOAD CAPACITANCE – pF 800 900 0 1000 0 400 600 800 1000 1200 1400 1600 1800 2000 LOAD CAPACITANCE – pF Figure 14. Small Signal Overshoot vs. Load Capacitance Figure 17. Slew Rate vs. Load Capacitance 40 35 35 ΩVS = ±15V RL = 2kΩ 30 SLEW RATE – V/µs SR+ AND SR– 20 ±VS = ±15V ΩRL = 2kΩ SR– 30 TA = +25°C 25 SLEW RATE – V/µs 200 15 10 SR+ 25 20 15 10 5 5 0 –50 0 0 0.4 0.8 1.2 1.6 DIFFERENTIAL INPUT VOLTAGE – V 2.0 Figure 15. Slew Rate vs. Differential Input Voltage –25 0 25 50 TEMPERATURE – °C 75 100 Figure 18. Slew Rate vs. Temperature –6– REV. 0 OP176 2.5 25 VS = ±15V ±V = ±15V S TA = +25°C Hz A 20 CURRENT NOISE – pA/ VOLTAGE NOISE – nV/ Hz ΩT = +25°C 15 10 1.5 1.0 0.5 5 0 10 0 10 100 1k FREQUENCY – Hz 10k Figure 19. Voltage Noise Density vs. Frequency 100 1k FREQUENCY – Hz 10k Figure 21. Current Noise Density vs. Frequency AAAAA AA AAAAA AA AAAAA AA AA AAAAAAAAA 100 90 100 90 VOUT (50mV/DIV) VOUT (5V/DIV) 10 10 0% 0% 50mV 100nS 5V 500nS TIME – 500ns/DIV TIME –100ns/DIV Figure 20. Small Signal Transient Response REV. 0 2.0 Figure 22. Large Signal Transient Response –7– OP176 0.1 APPLICATIONS Short Circuit Protection ±VS = ±18V ΩRL = 600Ω The OP176 has been designed with output short circuit protection. The typical output drive current is ± 50 mA. This high output current and wide output swing combine to yield an excellent audio amplifier, even when driving large signals, at low power and in a small package. 0.010 Total Harmonic Distortion Total Harmonic Distortion + Noise (THD + N) of the OP176 is well below 0.001% with any load down to 600 Ω. However, this is dependent upon the peak output swing. In Figure 23 it is seen that the THD + Noise with 3 V rms output is below 0.001%. In the following Figure 24, THD + Noise is below 0.001% for the 10 kΩ and 2 kΩ loads but increases to above 0.01% for the 600 Ω load condition. This is a result of the output swing capability of the OP176. Notice the results in Figure 25, showing THD vs. VIN (V rms). Ω10Vrms Ω5Vrms Ω3Vrms 0.001 Ω1Vrms .0001 20 0.1 100 1k 10k 20k Figure 25. THD + Noise vs. Output Amplitude (V rms) ±VS = ±15V VO = 3Vrms The output of the OP176 is designed to maintain low harmonic distortion while driving 600 Ω loads. However, driving 600 Ω loads with very high output swings results in higher distortion if clipping occurs. 0.010 To attain low harmonic distortion with large output swings, supply voltages may be increased. Figure 26 shows the performance of the OP176 driving 600 Ω loads with supply voltages varying from ± 18 volts to ± 20 volts. Notice that with ± 18 volt supplies the distortion is fairly high, while with ± 20 volt supplies it is a very low 0.0007%. Ω600Ω 0.001 0.1 .0001 20 100 1k 10k 20k ΩRL = 600Ω FIGURE 23. THD + Noise vs. Frequency 0.010 0.1 VO = ±18V ±VS = ±18V VO = 10Vrms 0.001 VO = ±22V 0.010 VO = ±19V 0.0001 20 0.001 VO = ±20V 100 1k 10k 20k Ω600Ω Figure 26. THD + Noise vs. Supply Voltage 10kΩ 2kΩ 0.0001 20 100 1k 10k 20k Figure 24. THD + Noise vs. RLOAD –8– REV. 0 OP176 Noise The voltage noise density of the OP176 is below 6 nV/√Hz from 30 Hz. This enables low noise designs to have good performance throughout the full audio range. Figure 27 shows a typical OP176 with a 1/f corner at 6 Hz. CH A: 80.0 µV FS 10.0 µV /DIV MKR: 15.9 µV/ Hz If the original 5534 socket includes offset nulling circuitry, one would find a 10 kΩ to 100 kΩ potentiometer connected between Pins 1 and 8 with said potentiometer’s wiper arm connected to V+. In order to upgrade the socket to the OP176, this circuit should be removed before inserting the OP176 for its offset nulling scheme uses Pins 1 and 5. Whereas the wiper arm of the 5534 trimming potentiometer is connected to the positive supply, the OP176’s wiper arm is connected to the negative supply. Directly substituting the OP176 into the original socket would inject a large current imbalance into its input stage. In this case, the potentiometer should be removed altogether, or, if nulling is still required, the trimming potentiometer should be rewired to match the nulling circuit as illustrated in Figure 29. +VS \ 0 Hz MKR: 5.4 Hz BW: 50Hz / 300 mHz 7 2 Figure 27. 1/f Noise Corner 4 Figure 29. Offset Voltage Nulling Scheme Input Overcurrent Protection OP37 OP37 OUTPUT 909Ω 100Ω 909Ω 490Ω ΩP1 = 10kΩ VOS TRIM RANGE = ±2mV –VS OP176 4.42kΩ Figure 28. Noise Test Upgrading “5534‘’ Sockets The OP176 is a superior amplifier for upgrading existing designs using the industry standard 5534. In most application circuits, the OP176 can directly replace the 5534 without any modifications to the surrounding circuitry. Like the 5534, the OP176 follows the industry standard, single op amp pinout. The difference between these two devices is the location of the null pins and the 5534’s compensation capacitor. The 5534 normally requires a 22 pF capacitor between Pins 5 and 8 for stable operation. Since the OP176 is internally compensated for unity gain operation, it does not require external compensation. Nevertheless, if the 5534 socket already includes a capacitor, the OP176 can be inserted without removing it. Since the OP176’s Pin 8 is a “NO CONNECT’’ pin, there is no internal connection to that pin. Thus, the 22 pF capacitor would be electrically connected through Pin 5 to the internal nulling circuitry. With the other end left open, the capacitor should have no effect on the circuit. However, to avoid altogether any possibility for noise injection, it is recommended that the 22 pF capacitor be cut out of the circuit entirely. REV. 0 P1 1 For audio applications the noise density is usually the most important noise parameter. For characterization the OP176 is tested using an Audio Precision, System One. The input signal to the Audio Precision must be amplified enough to measure accurately. For the OP176 the noise is gained by approximately 1020 using the circuit shown in Figure 28. Any readings on the Audio Precision must then be divided by the gain. In implementing this test fixture, good supply bypassing is essential. 100Ω 5 3 Noise Testing VOUT 6 OP176 The maximum input differential voltage that can be applied to the OP176 is determined by a pair of internal Zener diodes connected across its inputs. They limit the maximum differential input voltage to ± 7.5 V. This is to prevent emitter-base junction breakdown from occurring in the input stage of the OP176 when very large differential voltages are applied. However, in order to preserve the OP176’s low input noise voltage, internal resistances in series with the inputs were not used to limit the current in the clamp diodes. In small signal applications, this is not an issue; however, in applications where large differential voltages can be inadvertently applied to the device, large transient currents can flow through these diodes. Although these diodes have been designed to carry a current of ± 5 mA, external resistors as shown in Figure 30 should be used in the event that the OP176’s differential voltage were to exceed ± 7.5 V. 1.4kΩ 2 – OP176 1.4kΩ 3 6 + Figure 30. Input Overcurrent Protection –9– OP176 Output Voltage Phase Reversal +15V Since the OP176’s input stage combines bipolar transistors for low noise and p-channel JFETs for high speed performance, the output voltage of the OP176 may exhibit phase reversal if either of its inputs exceeds the specified negative common-mode input voltage. This might occur in some applications where a transducer, or a system, fault might apply very large voltages upon the inputs of the OP176. Even though the input voltage range of the OP176 is ± 10.5 V, an input voltage of approximately –13.5 V will cause output voltage phase reversal. In inverting amplifier configurations, the OP176’s internal 7.5 V clamping diodes will prevent phase reversal; however, they will not prevent this effect from occurring in noninverting applications. For these applications, the fix is a 3.92 kΩ resistor in series with the noninverting input of the device and is illustrated in Figure 31. 10µF + 0.1µF 2 VIN 7 VOUT 6 OP176 3 RL 2kΩ 4 0.1µF 10µF R FB* –15V 2 V IN OP176 +15V ΩR L 3 ΩR S Figure 33. Unity Gain Follower V OUT 6 10µF + 2kΩ 3.92kΩ 0.1µF *R FB IS OPTIONAL 10pF Figure 31. Output Voltage Phase Reversal Fix 4.99kΩ VIN Overdrive Recovery 4.99kΩ The overdrive recovery time of an operational amplifier is the time required for the output voltage to recover to a rated output level from a saturated condition. This recovery time is important in applications where the amplifier must recover quickly after a large abnormal transient event. The circuit shown in Figure 32 was used to evaluate the OP176’s overload recovery time. The OP176 takes approximately 1 µs to recover to VOUT = +10 V and approximately 900 ns to recover to VOUT = –10 V. R1 Ω1kΩ 2 3 7 OP176 2kΩ 4 2.49kΩ VOUT 6 0.1µF 10µF + –15V R2 Ω10kΩ Figure 34. Unity Gain Inverter 2 3 OP176 V IN 4Vp-p @ 100Hz RS 909Ω 6 V OUT In inverting and noninverting applications, the feedback resistance forms a pole with the source resistance and capacitance (RS and CS) and the OP176’s input capacitance (CIN), as shown in Figure 35. With RS and RF in the kΩ range, this pole can create excess phase shift and even oscillation. A small capacitor, CFB, in parallel with RFB eliminates this problem. By setting RS (CS + CIN) = RFB CFB, the effect of the feedback pole is completely removed. RL Ω2.43kΩ Figure 32. Overload Recovery Time Test Circuit High Speed Operation CFB As with most high speed amplifiers, care should be taken with supply decoupling, lead dress, and component placement. Recommended circuit configurations for inverting and noninverting applications are shown in Figure 33 and Figure 34. RFB RS VOUT CS CIN Figure 35. Compensating the Feedback Pole –10– REV. 0 OP176 Attention to Source Impedances Minimizes Distortion RG RS* RX RX = RO RG WHERE RO = OPEN-LOOP OUTPUT RESISTANCE RF CF = [ I + ( | AI CL| VOUT * RS = RG//RF IF RG//RF > 2kΩ FOR MINIMUM DISTORTION Figure 36. Balanced Input Impedance to Mininize Distortion in Noninverting Amplifier Circuits RF + RG ) CL RO RF APPLICATIONS USING THE OP176 A High Speed, Low Noise Differential Line Driver The circuit of Figure 38 is a unique line driver widely used in many applications. With ± 18 V supplies, this line driver can deliver a differential signal of 30 V p-p into a 2.5 kΩ load. The high slew rate and wide bandwidth of the OP176 combine to yield a full power bandwidth of 130 kHz while the low noise front end produces a referred-to-input noise voltage spectral density of 15 nV/√Hz. The circuit is capable of driving lower impedance loads as well. For example, with a reduced output level of 5 V rms (14 V p-p), the circuit exhibits a full-power bandwidth of 190 kHz while driving a differential load of 249 Ω! The design is a transformerless, balanced transmission system where output common-mode rejection of noise is of paramount importance. Like the transformer-based design, either output can be shorted to ground for unbalanced line driver applications without changing the circuit gain of 1. Other circuit gains can be set according to the equation in the diagram. This allows the design to be easily set for noninverting, inverting, or differential operation. input. The value of R S is determined by the parallel combination of R F and RG to maintain the low distortion performance of the OP176. For a more generalized treatment on circuit impedances and their effects on circuit distortion, please review the section on Active Filters at the end of the Applications section. R3 2kΩ 2 3 As with any high speed amplifier, care must be taken when driving capacitive loads. The graph in Figure 14 shows the OP176’s overshoot versus capacitive load. The test circuit is a standard noninverting voltage follower; it is this configuration that places the most demand on an amplifier’s stability. For capacitive loads greater than 400 pF, overshoot exceeds 40% and is roughly equivalent to a 45° phase margin. If the application requires the OP176 to drive loads larger than 400 pF, then external compensation should be used. Figure 37 shows a simple circuit which uses an in-the-loop compensation technique that allows the OP176 to drive any capacitive load. The equations in the figure allow optimization of the output resistor, RX, and the feedback capacitor, CF, for optimal circuit stability. One important note is that the circuit bandwidth is reduced by the feedback capacitor, CF, and is given by: VIN R9 50Ω VO1 R7 2kΩ R11 1kΩ R4 2kΩ 3 2 6 A2 R1 2kΩ Driving Capacitive Loads REV. 0 )] ( Figure 37. In-the-Loop Compensation Technique for Driving Capacitive Loads VIN BW = VOUT CL RF OP176 CF OP176 Figure 36 shows some guidelines for maximizing the distortion performance of the OP176 in noninverting applications. The best way to prevent unwanted distortion is to ensure that the parallel combination of the feedback and gain setting resistors (R F and RG) is less than 2 kΩ. Keeping the values of these resistors small has the added benefits of reducing the thermal noise of the circuit and dc offset errors. If the parallel combination of R F and RG is larger than 2 kΩ, then an additional resistor, R S, should be used in series with the noninverting RG RF VIN Since the OP176 is a very low distortion amplifier, careful attention should be given to source impedances seen by both inputs. As with many FET-type amplifiers, the p-channel JFETs in the OP176’s input stage exhibit a gate-to-source capacitance that varies with the applied input voltage. In an inverting configuration, the inverting input is held at a virtual ground and, as such, does not vary with input voltage. Thus, since the gate-to-source voltage is constant, there is no distortion due to input capacitance modulation. In noninverting applications, however, the gate-to-source voltage is not constant. The resulting capacitance modulation can cause distortion above 1 kHz if the input impedance is > 2 kΩ and unbalanced. A1 VO2 – VO1 = VIN 6 P1 10kΩ R2 2kΩ R5 2kΩ R6 2kΩ 2 3 A3 6 R10 50Ω R12 1kΩ VO2 R8 2kΩ A1, A2, A3 = OP176 GAIN = R3 R1 SET R2, R4, R5 = R1 AND R6, R7, R8 = R3 Figure 38. A High Speed, Low Noise Differential Line Driver 1 2 π R F CF –11– OP176 A Low Noise Microphone Preamplifier with a Phantom Power Option 1.0 Figure 39 is an example of a circuit that combines the strengths of the SSM2017 and the OP176 into a variable gain microphone preamplifier with an optional phantom power feature. The SSM2017’s strengths lie in its low noise and distortion, and gain flexibility/simplicity. However, rated only for 2 kΩ or higher loads, this makes driving 600 Ω loads somewhat limited with the SSM2017 alone. A pair of OP176s are used in the circuit as a high current output buffer (U2) and a DC servo stage (U3). The OP176’s high output current drive capability provides a high level drive into 600 Ω loads when operating from ± 18 V supplies. For a complete treatment of the circuit design details, the interested reader should consult application note AN-242, available from Analog Devices. ±VS = ±18V 80kHz LPF 0.1 G = 2000 0.010 G = 200 G=4 This amplifier’s performance is quite good over programmed gain ranges of 2 to 2000. For a typical audio load of 600 Ω, THD + N at various gains and an output level of 10 V rms is illustrated in Figure 40. For all but the very highest gain, the THD + N is consistent and well below 0.01%, while the gain of 2000 becomes more limited by noise. The noise performance of the circuit is exceptional with a referred-to-input noise voltage spectral density of 1 nV/√Hz at a circuit gain of 1000. G = 20 0.001 20 100 1k 10k Figure 40. Low Noise Microphone Preamplifier THD + N Performance at Various Gains (VOUT = 10 V rms and RL = 600 Ω) +48V +18V +VS + C8 47µF/ 63V ΩR10 100Ω R9 6.81kΩ C6 0.1µF PHANTOM POWER SUPPLY CONNECTIONS, INTERLOCKED WITH +/–VS (SEE NOTE 5). R8 6.81kΩ C7 0.1µF Z1 20k Z2 + C3 100µF/25V + C4 100µF/25V –18V –VS C5 33pF 1) TO MICROPHONE CIN1 ΩRP1 47µF/ 49.9Ω 63V RB1 10kΩ 2200µF/ 10V + CN 4.7nF/ FILM COMMON RB2 10kΩ +IN R2 20kΩ + –IN CIN2 ΩRP2 47µF/ 49.9Ω 63V CG1 3 RG 3) 8 1 CG2 2 + 2200µF/ 10V + Z3 +VS U1 CRF2 SSM2017P 100pF 7 6 4 CRF1 100pF –VS R1 10kΩ U2 OP176 ΩR3 49.9Ω 4 2 6 5 R7 1kΩ –VS Z4 R6 10kΩ 7 R4 221kΩ +VS C1 1µF FILM U3 OP176 +V S NOTES: 1) Z1–Z4 1N752 (SEE TEXT). 2) CINX, CGX LOW LEAKAGE ELECTROLYTIC TYPES (SEE TEXT). 3) GAIN = G = 2 x ((10k/RG ) +1) (SEE TEXT). 4) ALL RESISTORS 1% METAL FILM. 5) DOTTED PHANTOM POWER RELATED COMPONENTS OPTIONAL (SEE TEXT). OUTPUT 3 7 OUT COMMON D1 D2 1N458 1N458 2 6 3 R5 221kΩ 4 –VS C2 1µF FILM Figure 39. A Low Noise Microphone Preamplifier –12– REV. 0 OP176 A Low Noise, +5 V/+10 V Reference A Differential ADC Driver In many high resolution applications, voltage reference noise can be a major contributor to overall system error. Monolithic voltage references often exhibit too much wide band noise to be used alone in these systems. Only through careful filtering and buffering of these monolithic references can one realize wideband microvolt noise levels. The circuit illustrated in Figure 41 is an example of a low noise precision reference optimized for both ac and dc performance around the OP176. With a +10 V reference (the AD587), the circuit exhibits a 1 kHz spot output noise spectral density < 10 nV/√Hz. The reference output voltage is selectable between 5 V and 10 V, depending only on the selection of the monolithic reference. The output table illustrated in the figure provides a selection of monolithic references compatible with this circuit. High performance audio sigma-delta ADCs, such as the stereo 16-bit AD1878 and the 18-bit AD1879, present challenging design problems with regards to input interfacing. Because of an internal switched capacitor input circuit, the ADC input structure presents a difficult dynamic load to the drive amplifier with fast transient input currents due to their 3 MHz ADC sampling rate. Also, these ADCs inputs are differential with a rated full-scale range of ± 6.3 V, or about 4.4 V rms. Hence, the ADC interface circuit of Figure 42 is designed to accept a balanced input signal to drive the low dynamic impedances seen at the inputs of these ADCs. The circuit uses two OP176 U1 TOLERANCE (+/–mV) 10V 10V 10V 10V 5V 5V 5V 5V AD587 REF01 REF10 AD581 REF195 AD586 REF02 REF05 5 TO 10 30 TO 100 30 TO 50 5 TO 30 2 TO 10 2.5 TO 20 15 TO 50 15 TO 25 C1 100pF +15V 2 6 U1 4 C4 0.1µF R2 R1 ΩR5 5.76kΩ 51Ω R3 100Ω VOUT R6 3.3Ω 2 5 RTRIM 10kΩ (OPTIONAL) C1 100µF/25V C2 100µF/25V C3 0.0047µF R4 R3 ΩR6 5.62kΩ 5.49kΩ 51Ω U2 R2 10kΩ C4 0.01µF U1, U2 = OP176 C2 100pF 4 3 100µ/25V –12V ANALOG 0.1µF U1 (–) 6 –VS 5.62kΩ C3 100µF/25V 7 R1 1kΩ BALANCED INPUTS (+) R4 100Ω U2 OP176 8 0.1µF TO U1, U2 OUTPUT TABLE VOUT +12V ANALOG 100µ/25V COM +VS C5 0.01µF TO VIN – AD1878/ AD1879 SIGMADELTA ADC VIN + L & R INPUTS = AG, PIN 10 OR 18 (+) R5 1.1kΩ 5kΩ C5 10µF/25V REF COMMON 5kΩ USE FOR SINGLE-ENDED INPUTS NOTES C1–C5 = NPO CERAMIC, NON-INDUCTIVE, C3-C5 CLOSE TO ADC R1–R6 = 1% METAL FILM Figure 41. A Low Noise, +5 V/+10 V Reference Figure 42. A Balanced Driver Circuit for Sigma-Delta ADCs In operation, the basic reference voltage is set by U1, either a 5 V or 10 V 3-terminal reference chosen from the table. In this case, the reference used is a 10 V buried Zener reference, but all U1 IC types shown can plug into the pinout and can be optionally trimmed. The stable 10 V from the reference is then applied to the R1-C1-C2 noise filter, which uses electrolytic capacitors for a low corner frequency. When electrolytic capacitors are used for filtering, one must be cognizant of their dc leakage current errors. Here, however, a dc bootstrap of C1 is used, so this capacitor sees only the small R2 dc drop as bias, effectively lowering its leakage current to negligible levels. The resulting low noise, dc-accurate output of the filter is then buffered by a low noise, unity gain op amp using an OP176. With the OP176’s low VOS and control of the source resistances, the dc performance of this circuit is quite good and will not compromise voltage reference accuracy and/or drift. Also, the OP176 has a typical current limit of 50 mA, so it can provide higher output currents when compared to a typical IC reference alone. REV. 0 –13– amplifiers as inverting low-pass filters for their speed and high output current drive. The outputs of the OP176s then drive the differential ADC inputs through an RC network. This RC network buffers the amplifiers against step changes at the ADC sampling inputs using one differential (C3) and two commonmode connected capacitors (C4 and C5). The 51 Ω series resistors isolate the OP176s from the heavily capacitive loads, while the capacitors absorb the transient currents. Operating on ± 12 V supplies, this circuit exhibits a very low THD + N of 0.001% at 5 V rms outputs. For single-ended drive sources, a third op amp unity gain inverter can be added between R2’s (+) input terminal and R4. For best results, short-lead, noninductive capacitors are suggested for C3, C4, and C5 (which are placed close to the ADC), and 1% metal-film types for R1 through R6. For surface mount PCBs, these components can be NPO ceramic chip capacitors and thin-film chip resistors. OP176 parasitics. One percent metal-film resistors and two percent film capacitors of polystyrene or polypropylene are recommended. Using the suggested values, the frequency response relative to the ideal RIAA characteristic is within ± 0.2 dB over 20 Hz–20 kHz. Even tighter response can be achieved by using the alternate values, shown in brackets “[ ],” with the trade-off of a non off-the-shelf part. An RIAA Phono Preamp Figure 43 illustrates a simple phono preamplifier using RIAA equalization. The OP176 is used here to provide gain and is chosen for its low input voltage noise and high speed performance. The feedback equalization network (R1, R2, C1, and C2) forms a three time constant network, providing reasonably accurate equalization with standard component values. The input components terminate a moving magnet phono cartridge as recommended by the manufacturer, the element values shown being typical. When this ac coupled circuit is built with a low noise bipolar input device such as the OP176, amplifier bias current makes direct cartridge coupling difficult. This circuit uses input and output capacitor coupling to minimize biasing interactions. As previously mentioned, the OP176 was chosen for three reasons: (1) For optimal circuit noise performance, the amplifier used should exhibit voltage and current noise densities of 5 nV/√Hz and 1 pA/√Hz, respectively. (2) For high gain accuracy, especially at high stage gains, the amplifier should exhibit a gain bandwidth product in excess of 5 MHz. (3) Equally important because of the 100% feedback through the network at high frequencies, the amplifier must be unity gain stable. With the OP176, the circuit exhibits low distortion over the entire range, generally well below 0.01% at outputs levels of 5 V rms using ± 18 V supplies. To achieve maximum performance from this high gain, low level circuit, power supplies should be well regulated and noise free, and care should be taken with shielding and conductor layout. Input ac coupling to the amplifier is provided via C5, and the low frequency termination resistance, RT, is the parallel equivalent of R6 and R7. R3 of the feedback network is ac grounded via C4, a large value electrolytic. Additionally, this resistor is set to a low value to minimize circuit noise from nonamplifier sources. These design measures reduce the dc offset at the output of the OP176 to a few millivolts. The output coupling network of C3 and R4 is shown as suitable for wide band response, but it can be set to a 7950 µs time constant for use as a 20 Hz rumble filter. Active Filter Circuits Using the OP176 A general active filter topology that lends itself to both high-pass (HP) and low-pass (LP) filters is the well known Sallen-Key (SK) VCVS (Voltage-Controlled, Voltage Source) architecture. This filter type uses the op amp as a fixed gain voltage follower at either unity or a higher gain. Discussed here are simplified 2pole, unity gain forms of these filters, which are attractive for several reasons: One, at audio frequencies, using an amplifier with a 10 MHz bandwidth such as the OP176, these filters exhibit reasonably low sensitivities for unity gain and high damping (low Q). Second, as voltage followers, they are also inherently gain accurate within their pass band; hence, no gain resistor scaling errors are generated. Third, they can also be made “dc accurate,” with output dc errors of only a few millivolts. The specific filter response in terms of HP, LP and damping is determined by the RC network around the op amp, as shown in Figure 44a. The 1 kHz gain (“G”) of this circuit, controlled by R3, is calculated as: G (@ 1 kHz) = 0.101 × 1 + R1 R3 For an R3 of 200 Ω, the circuit gain is just under 50 × (≈ 34 dB), and higher gains are possible by decreasing R3. For any value of R3, the R5-C6 time constant should be equal to R3 and the series equivalent of C1 and C2. Using readily available standard values for network elements (R1, R2, C1, and C2) makes the design easily reproducible and inexpensive. These components are ideally high quality precision types, for low equalization errors and minimum +VS MOVING MAGNET PICKUP R6 Ω100kΩ 0.1µF 100µF 0.1µF 100µF –VS +VS C5 100µF/25V +18V –18V C3 100µF/25V 3 Ct 150pF ΩR7 100kΩ Rt = R6| |R7 –~ 50kΩ 7 U1 OP176 2 4 –VS 6 R1 100kΩ 1% [97.6kΩ ] Ω200Ω (34dB) Ω100Ω (40dB) C1 0.03µF 2% R2 8.25kΩ 1% [7.87kΩ] R3 ΩR5 499Ω VOUT C2 0.01µF 2% ΩR4 100kΩ C6 3nF C4 1000µF/16V Figure 43. An RIAA Phono Preamplifier Circuit –14– REV. 0 OP176 High Pass Sections Low Pass Sections Figure 44a illustrates the high-pass form of a 2-pole SK filter using an OP176. For simplicity and practicality, capacitors C1 and C2 are set equal (“C”), and resistors R2 and R1 are adjusted to a ratio, N, which provides the filter damping coefficient, α, as per the design expressions. This high pass design is begun with selection of standard capacitor values for C1 and C2 and a calculation of N. The values for R1 and R2 are then determined from the following expressions: In the LP SK arrangement of Figure 44b, the R and C elements are interchanged where the resistors are made equal. Here, the ratio of C2/C1 (“M”) is used to set the filter α, as noted. Otherwise, this filter is similar to the HP section, and the resulting 1 kHz LP response is shown in Figure 45. The design begins with a choice of a standard capacitor value for C1 and a calculation of M. This then forces a value of “M × C1” for C2. Then, the value for R1 and R2 (“R”) is calculated according to the following equation: R1 = 1 2π × FREQ × C × N R= 1 2π × FREQ × C1 × M and R2 = N × R1 IN IN OUT R1 11k (11.254k) C1 0.01µF C2 0.01µF OP176 3 R2 22k (22.508k) +VS 7 6 2 4 –VS R2 11k (11.254k) GIVEN: α, FREQ SET C1 = C2 = C α= 2 N= N 4 α2 R1 = OUT R1 11k (11.254k) 1 Q R2 = R1 = 1 2 π FREQ x C x C2 0.01µF C1 0.02µF GIVEN: α, FREQ OP176 3 4 –VS 1 = Q C2 M= = C1 α2 α= 2 M 4 CHOOSE C1 C2 = M x C1 R= ZCOMP 1 2 π FREQ x C1 x M 1 kHz BW SHOWN 1 kHz BW SHOWN ZCOMP (LOW PASS) OUTPUT IN (–) C2 OUTPUT IN (–) 6 N ZCOMP (HIGH PASS) R2 R2 C2 7 2 R2 = N x R1 ZCOMP +VS R1 C1 C1 R1 Figures 44b. Two-Pole Unity Gain HP/LP Active Filters Figures 44a. Two-Pole Unity Gain HP/LP Active Filters 10.000 LP 0.0 HP –10.00 –20.00 dBr In this examples, circuit α (or 1/Q) is set equal to √2, providing a Butterworth (maximally flat) characteristic. The filter corner frequency is normalized to 1 kHz, with resistor values shown in both rounded and (exact) form. Various other 2-pole response shapes are possible with appropriate selection of α, and frequency can be easily scaled, using inversely proportional R or C values for a given α. The 22 V/µs slew rate of the OP176 will support 20 V p-p outputs above 100 kHz with low distortion. The frequency response resulting with this filter is shown as the dotted HP portion of Figure 45. –30.00 –40.00 –50.00 –60.00 –70.00 20 100 1k FREQUENCY – Hz 10k 50k Figure 45. Relative Frequency Response of 2-Pole, 1 kHz Butterworth LP (Left) and HP (Right) Active Filters REV. 0 –15– OP176 Passive Component Selection for Active Filters 1 The passive components suitable for active filters deserve more than casual attention. Resistors should be 1%, low TC, metalfilm types of the RN55 or RN60 style. Capacitors should be 1% or 2% film types preferably, such as polypropylene or polystyrene, or NPO (COG) ceramic for smaller values. THD +N – % 0.1 Active Filter Circuit Subtleties In designing active filter circuits with the OP176, moderately low values (10 kΩ or less) for R1 and R2 can be used to minimize the effects of Johnson noise when critical. The practical tradeoff is, of course, capacitor size and expense. DC errors will result for larger values of resistance, unless compensation for amplifier input bias current is used. To add bias compensation in the HP filter section of Figure 42a, a feedback compensation resistor equal to R2 can be used. This will minimize bias current induced offset to the product of the OP176’s IOS and R2. For an R2 of 25 kΩ, this produces a typical compensated offset voltage of 50 µV. Similar compensation is applied to Figure 42b, using a resistance equal to R1+ R2. Using dc compensation, filter output dc errors using the OP176 will be dominated by its VOS, which is typically 1 mV or less. A caveat here is that the additional resistors can increase noise substantially. For example, a 10 kΩ resistor generates ~ 12 nV/ √Hz of noise and is about twice that of the OP176. These resistors can be ac bypassed to eliminate their noise using a simple shunt capacitor chosen such that its reactance (XC) is much less than R at the lowest frequency of interest. A more subtle form of ac degradation is also possible in these filters, namely nonlinear input capacitance modulation. This issue was previously covered for general cases in the section on minimizing distortion. In active filter circuits, a fully compensating network (for both dc and ac performance) can be used to minimize this distortion. To be most effective, this network (ZCOMP) should include R1 through C2 as noted for either filter type, of the same style and value as their counterparts in the forward path. The effects of a ZCOMP network on the THD + N performance of two 1 kHz HP filters is illustrated in Figure 46. One filter (A) is the example shown in Figure 44a (Curves A1 and A2), while the second (B) uses RC values scaled 10 times upward in impedance (Curves B1 and B2). Both filters operate with a 2 V rms input, ± 18 V supplies, 100 kΩ loading, and analyzer bandwidth of 80 kHz. B1 0.010 A1 B2 0.001 A2 0.0001 20 100 1k FREQUENCY – Hz 10 k 20k Figure 46. THD + N (%) vs. Frequency for Various 1 kHz HP Active Filters Illustrating the Effects of the ZCOMP Network Curves A1 and B1 show performance with ZCOMP shorted, while curves A2 and B2 illustrate operation with ZCOMP active. For the “A” example values, distortion in the pass band of 1 kHz–20 kHz is below 0.001% compensated, and slightly higher uncompensated. With the higher impedance “B” network, there is a much greater difference between compensated and uncompensated responses, underscoring the sensitivity to higher impedances. Although the positive effect of ZCOMP is seen for both “A” and “B” cases, there is a buffering effect which takes place with lower impedances. As case “A” shows, when using larger capacitance values in the source, the amplifier’s nonlinear C-V input characteristics have less effect on the signal. Thus, to minimize the necessity for the complete ZCOMP compensation, effective filter designs should use the lowest capacitive impedances practical, with an 0.01 µF lower value limit as a goal for lowest distortion (while lower values can certainly be used, they may suffer higher distortion without the use of full compensation). Since most designs are likely to use low relative impedances for reasons of low noise and offset, the effects of CM distortion may or may not actually be apparent to a given application. –16– REV. 0 OP176 97 EP I1 98 4 R6 R5 CM2 8 7 –IN Q1 2 CIN 9 35 VN1 D1 IOS 12 D2 EN 1 3 EOS VN2 +IN VN3 DN1 36 5 98 VN5 DN3 10 13 DN2 DN4 VN4 DN5 16 CN1 C1 DN6 VN6 14 11 CM1 15 Q2 17 6 C2 R3 R4 EM 97 V2 C7 19 D3 21 23 24 26 25 R12 R9 G1 R7 G2 C3 R8 R10 22 G3 C5 G4 R11 C6 E2 R13 C4 98 98 D4 EREF 20 V3 51 99 D7 R15 D8 G8 ISY D5 28 30 F1 27 G5 R14 D6 98 C9 R18 G9 D9 D10 G6 G7 50 Figure 47. OP176 Spice Model Schematic REV. 0 L2 F2 33 32 R16 29 V5 31 C8 R17 V4 –17– 34 OP176 OP176 SPICE Model * * Node Assignments * Noninverting Input * | Inverting Input * | | Positive Supply * | | | Negative Supply * | | | | Output * | | | | | * | | | | | .SUBCKT OP176 1 2 99 50 34 * * INPUT STAGE & POLE AT 100 MHz * R3 5 51 2.487 R4 6 51 2.487 CIN 1 2 3.7E-12 CM1 1 98 7.5E-12 CM2 2 98 7.5E-12 C2 5 6 320E-12 I1 97 4 100E-3 IOS 1 2 1E-9 EOS 9 3 POLY(1) (26,28) 0.2E-3 1 Q1 5 2 7 QX Q2 6 9 8 QX R5 7 4 1.970 R6 8 4 1.970 D1 2 36 DZ D2 1 36 DZ EN 3 1 (10,0) 1 GN1 0 2 (13,0) 1E-3 GN2 0 1 (16,0) 1E-3 * EREF 98 0 (28,0) 1 EP 97 0 (99,0) 1 EM 51 0 (50,0) 1 * * VOLTAGE NOISE SOURCE * DN1 35 10 DEN DN2 10 11 DEN VN1 35 0 DC 2 VN2 0 11 DC 2 * * CURRENT NOISE SOURCE * DN3 12 13 DIN DN4 13 14 DIN VN3 12 0 DC 2 VN4 0 14 DC 2 * * CURRENT NOISE SOURCE * DN5 15 16 DIN DN6 16 17 DIN VN5 15 0 DC 2 VN6 0 17 DC 2 * * GAIN STAGE & DOMINANT POLE AT 32 Hz * R7 18 98 1.243E6 C3 18 98 4E-9 G1 98 18 (5,6) 4.021E-1 V2 97 19 1.35 V3 20 51 1.35 D3 18 19 DX D4 20 18 DX * * POLE/ZERO PAIR AT 1.5 MHz/2.7 MHz * R8 21 98 1E3 R9 21 22 1.25E3 C4 22 98 47.2E-12 G2 98 21 (18,28) 1E-3 * * POLE AT 100 MHz * R10 23 98 1 C5 23 98 1.59E-9 G3 98 23 (21,28) 1 * * POLE AT 100 MHz * R11 24 98 1 C6 24 98 1.59E-9 G4 98 24 (23,28) 1 * * COMMON-MODE GAIN NETWORK WITH ZERO AT 1 kHz * R12 25 26 1E6 C7 25 26 60E-12 R13 26 98 1 E2 25 98 POLY(2) (1,98) (2,98) 0 2.50 2.50 * * POLE AT 100 MHz * R14 27 98 1 C8 27 98 1.59E-9 G5 98 27 (24,28) 1 * * OUTPUT STAGE * R15 28 99 58.333E3 R16 28 50 58.333E3 C9 28 50 1E-6 ISY 99 50 1.743E-3 R17 29 99 100 R18 29 50 100 L2 29 34 1E-9 G6 32 50 (27,29) 10E-3 G7 33 50 (29,27) 10E-3 G8 29 99 (99,27) 10E-3 G9 50 29 (27,50) 10E-3 V4 30 29 1.74 V5 29 31 1.74 F1 29 0 V4 1 F2 0 29 V5 1 D5 27 30 DX D6 31 27 DX D7 99 32 DX D8 99 33 DX D9 50 32 DY D10 50 33 DY * * MODELS USED * .MODEL QX PNP(BF=5E5) .MODEL DX D(IS=1E-12) .MODEL DY D(IS=1E-15 BV=50) .MODEL DZ D(IS=1E-15 BV=7.0) .MODEL DEN D(IS=1E-12 RS=4.35K KF=1.95E-15 AF=1) .MODEL DIN D(IS=1E-12 RS=268 KF=1.08E-15 AF=1) .ENDS OP176 –18– REV. 0 OP176 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 8-Lead Plastic DIP (N-8) 8 5 0.280 (7.11) 0.240 (6.10) PIN 1 1 4 0.325 (8.25) 0.300 (7.62) 0.430 (10.92) 0.348 (8.84) 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.130 (3.30) MIN 0.160 (4.06) 0.115 (2.93) 0.100 (2.54) BSC 0.022 (0.558) 0.014 (0.356) 0.070 (1.77) 0.045 (1.15) 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) SEATING PLANE 8-Lead Narrow-Body SO (SO-8) 8 5 0.1574 (4.00) 0.1497 (3.80) PIN 1 1 0.2440 (6.20) 0.2284 (5.80) 4 0.1968 (5.00) 0.1890 (4.80) 0.0098 (0.25) 0.0040 (0.10) 0.0196 (0.50) x 45° 0.0099 (0.25) 0.0688 (1.75) 0.0532 (1.35) 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC REV. 0 0.0098 (0.25) 0.0075 (0.19) –19– 8° 0° 0.0500 (1.27) 0.0160 (0.41) –20– PRINTED IN U.S.A. C1878–10–1/94 OP176 FOR CATALOG ORDERING GUIDE Model Temperature Range Package Description Package Option* OP176GP OP176GS OP176GSR OP176GBC –40°C to +85°C –40°C to +85°C –40°C to +85°C +25°C 8-Pin Plastic DIP 8-Pin SOIC SO-8 Reel, 2500 Pieces DICE N-8 SO-8 *For outline information see Package Information section. REV. 0 –21–