RT9594A/B MOSFET Integrated Smart Photoflash Capacitor Charger with IGBT Driver General Description Features The RT9594A/B are complete photoflash module solutions for digital and film cameras. They are targeted for applications that use 2 to 4 AA batteries or 1 to 2 lithiumion batteries. The RT9594A/B adopt flyback topology which use constant primary peak current and zero secondary valley current to charge photoflash capacitor quickly and efficiently. The built-in 50V MOSFET allows flexibility in transformer design and simplifies the PCB layout. The RT9594A/B also integrate an IGBT driver for igniting photoflash tube. Only a few external components are required, which greatly reduces the PCB space and cost. The RT9594A/B are available in the WQFN-16L 3x3 package. z 50V MOSFET Integrated z 1.6V to 9V Battery Input Voltage Range Two Charge Current Levels Setting Charges Any Size Photoflash Capacitor Adjustable Input Current Adjustable Output Voltage Charge Complete Indicator Built-in IGBT Driver for IGBT Application Constant Peak Current Control 16-Lead WQFN Package RoHS Compliant and Halogen Free z z z z z z z z z Applications z z z Pin Configurations Lead Plating System G : Green (Halogen Free and Pb Free) VDD : 5V (typ.) VDD : 3.3V (typ.) RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. VBAT CS VDOUT FBVD VDD FB 10 STAT 9 AGND 1 12 2 11 PGND 3 17 4 5 6 7 8 DRVOUT ` SW 16 15 14 13 Note : Richtek products are : PGND SW PGND (TOP VIEW) VDRV Package Type QW : WQFN-16L 3x3 (W-Type) DRVIN RT9594A/B Digital Still Camera Film Camera Flash Unit Camera Phone Flash CHARGE Ordering Information WQFN-16L 3x3 Marking Information For marking information, contact our sales representative directly or through a Richtek distributor located in your area. DS9594A/B-02 April 2011 www.richtek.com 1 RT9594A/B Typical Application Circuit V OUT GSD2004S 1:N V BAT C2 47uF CD 330pF FB SW VDD 10 STAT 5 DRVIN 6 RT9594A/B VDRV 7 8 DRVOUT CHARGE 2 CS AGND R4 100k R3 1k 13, 14 11 FBVD C1 1uF PGND VBAT 12 3.3V/5V 15, 16 R5 27k C OUT 100uF/ 330V R2 150k * optional 1 + R1 150k VDOUT 3 Strobe 3.3V/5V IGBT Gate C3 0.1uF 9 4 Figure 1. Typical Application Circuit Note * : If the spike voltage on SW pin is higher than 50V (internal N-MOSFET DC rating ) while internal N-MOSFET switches off, place the capacitor (CD) between SW pin and PGND to reduce the spike voltage. V OUT GSD2004S 1:N V BAT C2 47uF + R1 150k C OUT 100uF/ 330V R2 150k R4 100k FB DRVIN 2 CS 6 RT9594A/B VDRV 7 8 CHARGE R5 27k SW VDD 10 STAT 5 R3 1k 13, 14 11 DRVOUT 4 AGND C1 1uF FBVD 12 3.3V/5V 15, 16 PGND VBAT 1 VDOUT 3 Strobe 3.3V/5V IGBT Gate C3 0.1uF 9 Figure 2. Application Circuit for the Gate Drive Voltage of IGBT Same as VDD Voltage www.richtek.com 2 DS9594A/B-02 April 2011 RT9594A/B Function Block Diagram DRVIN VDRV DRVOUT SW Sense Maximum Off AGND VBAT SW S CHARGE FB 1V + - Enable 0.8V Q R PGND + Ipeak VDD STAT VDOUT 1V OTP OCP CS + - FBVD Functional Pin Description Pin No. Pin Name Pin Function 1 VBAT Battery Voltage Pin. 2 CS Input Current Setting Pin. 3 VDOUT Voltage Detector Output Pin. Open drain output. 4 FBVD Voltage Detector Feedback Pin. Charge Enable Pin. The charge function is executed when CHARGE pin is set 5 CHARGE from Low to High. The chip is in Shutdown mode when CHARGE pin is set to Low. 6 DRVIN IGBT Driver Input Pin. 7 VDRV IGBT Driver Power Pin. 8 DRVOUT IGBT Driver Output Pin. 9 AGND Analog Ground. 10 STAT Charge Status Output. Open Drain output. When target output voltage is reached, N-MOSFET turns on. This pin needs a pull up resistor. 11 FB Feedback Voltage Pin. 12 VDD Power Input Pin. 13, 14 SW 15, 16, 17 (Exposed Pad) PGND DS9594A/B-02 April 2011 N-MOSFET Switching Node. Power Ground. The exposed pad must be soldered to a large PCB and connected to PGND for maximum power dissipation. www.richtek.com 3 RT9594A/B Absolute Maximum Ratings z z z z z z z z z (Note 1) Supply Voltage, VDD -----------------------------------------------------------------------------------------------------Battery Input Voltage, VBAT ---------------------------------------------------------------------------------------------Built-in N-Channel Enhancement MOSFET Drain-Source Voltage ----------------------------------------------------------------------------------------------------SW Pulse Current (Pulse Width ≤ 1us) -----------------------------------------------------------------------------SW Continuous Current ------------------------------------------------------------------------------------------------CS, VDOUT, FBVD, CHARGE, DRVIN, VDRV, DRVOUT, STAT, FB -----------------------------------------Power Dissipation, PD @ TA = 25°C WQFN-16L 3x3 -----------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-16L 3x3, θJA ------------------------------------------------------------------------------------------------------WQFN-16L 3x3, θJC -----------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------ Recommended Operating Conditions z z z 6V 12V 50V 4A 2A 6V 1.67W 60°C/W 7°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Built-in N-Channel Enhancement MOSFET Drain-Source Voltage ----------------------------------------------------------------------------------------------------- 40V Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VDD = 3.3V/5V, TA = 25°C, unless otherwise specification) Parameter V DD Operating Voltage Symbol RT9594A RT9594B Test Conditions VDD Min Typ Max Units 3.15 3.3 3.4 4.5 5 5.5 1.6 -- 9 V V Battery Voltage VBAT Switch-Off Current (IVDD) IVDD _SW _OFF V FB = 1.1V -- 1 10 uA Shutdown Current (IVDD) IOFF -- 0.01 1 uA FB Voltage VFB 0.985 1 1.015 V -- -- 8 mV -- 11 19 Ω Line Regulation RT9594A RT9594B ｜ΔV FB｜ STAT Open Drain RDS(ON) CHARGE pin = 0V 3.15V ≤ V DD ≤ 3.4V 4.5V ≤ VDD ≤ 5.5V Charge Enable High VCEH 1.3 -- -- V Charge Enable Low VCEL -- -- 0.4 V To be continued www.richtek.com 4 DS9594A/B-02 April 2011 RT9594A/B Parameter Symbol Test Conditions Min Typ Max Units -- 300 400 -- 250 350 Max Off Time During Pre-Charge -- 9 -- us Min Off Time -- 400 -- ns 2 -- 5.5 V 0.8 1.5 2.4 V Built-in N-Channel Enhancement MOSFET Drain-Source On-Resistance RT9594A RDS(ON) ID = 10mA RT9594B mΩ IGBT Driver IGBT Driver Supply Voltage VVDRV DRVIN Trip Point DRVOUT On Resistance to VVDRV VVDRV = 3.3V -- 6 -- Ω DRVOUT On Resistance to GND VVDRV = 3.3V -- 6 -- Ω Propagation Delay (Rising) -- 20 -- ns Propagation Delay (Falling) -- 200 -- ns 0.95 0.99 1.03 V -- 65 -- mV -- 12 -- Ω Voltage Detector Voltage Detector Trip (Falling) VFBVD Voltage Detector Hysteresis VFBVD_HYS FBVD Falling VDOUT on Resistance to GND Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board (single layer, 1S) of JEDEC 51-3 thermal measurement standard. The case point of θJC is on the expose pad for the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS9594A/B-02 April 2011 www.richtek.com 5 RT9594A/B Typical Operating Characteristics Charge Time vs. VBAT Charge Time vs. VBAT 12 12 VDD = 3.3V, COUT = 140μF VOUT = 0 to 300V 10 10 9 9 8 7 IPK-PRI = 1.4A 6 5 VDD = 5V, COUT = 140μF VOUT = 0 to 300V 11 Charge Time (s) Charge Time (s) 11 IPK-PRI = 1.6A 8 7 5 4 4 3 3 2 IPK-PRI = 1.4A 6 IPK-PRI = 1.6A 2 1 2 3 4 5 6 7 1 VBAT (V) 2 3 4 5 6 7 VBAT (V) Output Voltage vs. VBAT Switching 308 VOUT = 100V Output Voltage (V) 306 VSW (20V/Div) 304 TA = 25°C 302 I PRI (1A/Div) 300 TA = 85°C TA = -40°C I SEC (200mA/Div) 298 296 1.5 2.5 3.5 4.5 5.5 6.5 Time (1μs/Div) VBAT (V) Charging Switching VOUT = 300V CHARGE (5V/Div) VSW (20V/Div) STAT (5V/Div) I PRI (1A/Div) I IN (200mA/Div) VOUT (50V/Div) I SEC (200mA/Div) Time (1μs/Div) www.richtek.com 6 VBAT = 3.7V, VDD = 3.3V COUT = 140μF Time (1s/Div) DS9594A/B-02 April 2011 RT9594A/B Application Information The RT9594A/B integrate a constant peak current controller for charging photoflash capacitor and an IGBT driver for igniting flash tube. The photoflash capacitor charger uses constant primary peak current and SW falling control to efficiently charge the photoflash capacitor. Pulling the CHARGE pin high will initiate the charging cycle. During MOS on period, the primary current ramps up linearly according to VBAT and primary inductance. A resistor connecting from CS pin to GND determines the primary peak current. During the MOS off period, the energy stored in the flyback transformer is boosted to the output capacitor. The secondary current decreases linearly at a rate determined by the secondary inductance and the output voltage (neglecting the voltage drop of the diode). The SW pin monitors the secondary current. When the secondary current drops to 0A, SW voltage falls then MOS on period starts again. The charging cycle repeats itself and charges the output capacitor. The output voltage is sensed by a voltage divider connecting to the anode of the rectifying diode. When the output voltage reaches the desired voltage set by the resistor divider, the charging block will be disabled and stop charging. Then STAT pin will be pulled low to indicate the complete charging. The voltage-sensing path will be cut off when charging completed to minimize the output voltage decay. Both the CHARGE and STAT pins can be easily interfaced to a microprocessor in a digital system. Transformer The flyback transformer should be appropriately designed to ensure effective and efficient operation. 1. Turns Ratio The turns ratio of transformer (N) should be high enough so that the absolute maximum voltage rating for the internal N-MOSFET drain to source voltage is not exceeded. Choose the minimum turns ratio according to the following formula : VOUT NMIN ≥ 45 − VBAT Where : VOUT : Target Output Voltage VBAT : Battery Voltage DS9594A/B-02 April 2011 2. Primary Inductance For each switching cycle, energy transferred to the output capacitor is proportional to the primary inductance for a constant primary current. The higher the primary inductance is, the higher the charging efficiency will be. Besides, to ensure enough off time for output voltage sensing, the primary inductance should be high enough according to the following formula : 400 × 10 −9 × VOUT L PRI ≥ N × IPK −PRI VOUT : Target Output Voltage N : Transformer turns ratio IPK-PRI : Primary peak current 3. Leakage Inductance The leakage inductance of the transformer results in the first spike voltage when N-MOSFET turns off. The spike voltage is proportional to the leakage inductance and inductor peak current. The spike voltage must not exceed the dynamic rating of the N-MOSFET drain to source voltage (50V). 4. Transformer Secondary Capacitance Any capacitance on the secondary can severely affect the efficiency. A small secondary capacitance is multiplied by N2 when reflected to the primary will become large. This capacitance forms a resonant circuit with the primary leakage inductance of the transformer. Therefore, both the primary leakage inductance and secondary side capacitance should be minimized. Rectifying Diode The rectifying diode should be with short reverse recovery time (small parasitic capacitance). Large parasitic capacitance increases switching loss and lowers charging efficiency. In addition, the peak reverse voltage and peak current of the diode should be sufficient. The peak reverse voltage of the diode is approximately : VPK −R ≈ VOUT + (N × VBAT ) The peak current of the diode equal primary peak current divide transformer turn ratio as the following equation : I IPK −SEC = PK −PRI N Where : N is transformer turns ratio. www.richtek.com 7 RT9594A/B Adjustable Input Current Lower Charging Current at Low Battery Voltage The RT9594A/B simply adjust peak primary current by a resistor RCS connecting to CS pin as shown in Function block diagram. RCS determines the peak current of primary N-MOSFET according to the following Equation : The RT9594A/B also offers two stage charging function. If the resistor divider is connected from VBAT to FBVD to GND as shown in Figure 5, it will detect the battery voltage. Because of the reference voltage of the internal detector is 1V, thus the battery trip point is 2.5V. When battery voltage is >2.5V, the VDOUT open drain MOS inside the RT9594A/B will be turned on (VDOUT state become GND), the peak current value will be determined by R4. When battery voltage is <2.5V, the VDOUT open drain MOS inside the RT9594A/B will be turned off (VDOUT state become OPEN), then the peak current is determined by R4 series with R5. Thus charging current is decreasing as shown in Figure 7. Adjustable Output Voltage The RT9594A/B sense output voltage by a voltage divider connecting to the anode of the rectifying diode during OFF time as shown in Figure 3. This eliminates power loss at voltage-sensing circuit when charging completed. R1 to R2 ratio determines the output voltage as shown in the typical application circuit. The feedback reference voltage is 1V. If VOUT = 300V, according the following equation : ( VOUT = VFB × 1 + ) R1 + R2 R1 + R2 , so = 299. R3 R3 As shown in the Figure 6 circuit, the FBVD voltage also could be set by the GPIO signal. When GPIO voltage is >1V, the first stage peak current value will be determined by R4. When the GPIO voltage is <1V, the second stage peak current is determined by R4 series with R5. 1:N V BAT It is recommend to set R3 = 1kΩ and R1 = R2 = 150kΩ for reducing parasitic capacitance coupling effect of the FB pin. R1 and R2 MUST be greater than 0805 size resistor for enduring secondary HV. Another sensing method is to sense the output voltage directly as shown in Figure 4. 47uF R6 1.5M V OUT C OUT 100uF /330V R2 150k R7 1M FBVD VDOUT R5 3k R4 V OUT CS 3.3V R3 1k Strobe DRVIN VDRV RT9594A/B 24k VDD 3.3V/5V 0.1uF To IGBT Gate DRVOUT 1uF 100K R1 150k GSD2004S R1 150k FB select appropriate RCS according to the battery capability and required charging time. SW Where the IPK-PRI is the primary peak current. Users could VBAT (Ω) PGND RCS = 40000 IPK −PRI CHARGE AGND STAT C OUT R2 150k Figure 5. Two Stage Charging Application Circuit FB R3 1k 1:N V BAT R2 10M C OUT R3 66.5k Figure 4. Sensing Output Voltage VDOUT R4 CS 24k VDD 1uF 100K STAT FB SW VBAT FBVD 3.3V C1 10nF www.richtek.com 8 R5 3k PGND GPIO FB C OUT 100uF /330V R2 150k V OUT R1 10M V OUT R1 150k 47uF Figure 3. Sensing Anode of Diode GSD2004S DRVIN VDRV RT9594A/B DRVOUT R3 1k Strobe 3.3V/5V 0.1uF To IGBT Gate CHARGE AGND Figure 6. Two Stage Charging by GPIO Signal DS9594A/B-02 April 2011 RT9594A/B VBAT < 2.5V VBAT (1V/Div) Change to lower current I IN (200mA/Div) VOUT (50V/Div) Time (1s/Div) Figure 7. Lower Charging Current Layout Guide For best performance, careful PCB layout is necessary. The following guidelines should be strictly followed when designing a PCB layout for the RT9594A/B. 1. Both of primary and secondary power paths should be as short as possible. 2. Place the RCS as close to chip as possible. The GND side of RCS should be directly connected to ground plane to avoid noise coupling. 3. Keep FB node area small and far away from nodes with voltage switching to reduce parasitic capacitance coupling effect. 4. The PGND should be connected to VBAT ground plane to reduce switching noise. V BAT V OUT PGND SW PGND SW PGND PGND 16 15 14 13 Bottom VDD 11 FB 10 STAT 9 AGND 12 1 2 PGND 3 17 5 6 7 8 DRVIN VDRV DRVOUT 4 CHARGE AGND VBAT CS VDOUT FBVD Figure 8. Suggestion Layout DS9594A/B-02 April 2011 www.richtek.com 9 RT9594A/B Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b A3 Symbol 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A1 1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 16L QFN 3x3 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. www.richtek.com 10 DS9594A/B-02 April 2011