® RT9595 MOSFET Integrated Smart Photoflash Capacitor Charger with IGBT Driver General Description Features The RT9595 is a complete photoflash module solution for digital and film cameras. It is targeted for applications that use 2 to 3 AA batteries or 1 Lithium-Ion battery. The RT9595 adopts fly back topology which use constant primary peak current and zero secondary valley current to charge photoflash capacitor quickly and efficiently. The built-in 45V MOSFET allows flexibility in transformer design and simplifies the PCB layout. The RT9595 also integrate an IGBT driver for igniting photoflash tube. Only a few external components are required, which greatly reduce the PCB space and cost. The RT9595 is available in the WDFN-10L 3x3 package. z z z z z z z z z z Applications z RT9595 z Package Type QW : WDFN-10L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : ` z RoHS compliant and compatible with the current require- Digital Still Camera Film Camera Flash Unit Camera Phone Flash Pin Configurations (TOP VIEW) GND DRVOUT VDD DRVIN CHARGE 1 2 3 4 5 GND Ordering Information 45V MOSFET Integrated Charges any Size Photoflash Capacitor Adjustable Input Current Adjustable Output Voltage Charge Complete Indicator Built-In IGBT Driver for IGBT Application Constant Peak Current Control Over Voltage Protection 10-Lead WDFN Package RoHS Compliant and Halogen Free 11 10 9 8 7 6 SW NC CS FB STAT ments of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. WDFN-10L 3x3 Marking Information FC= : Product Code FC=YM DNN YMDNN : Date Code Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9595-04 March 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT9595 Typical Application Circuit VOUT GSD2004S 1:N VBAT R1 150k R2 150k 3 3.3V/5V C1 1µF R4 100k VDD COUT 100µF/ 330V R3 1k 7 FB SW 10 + C2 47µF DRVIN 4 Strobe RT9595 6 STAT 5 DRVOUT CHARGE 8 CS GND 2 IGBT Gate 1, Exposed Pad (11) RCS 54k R5 54k GPIO (Floating/GND) Function Block Diagram DRVIN VDD DRVOUT SW Sense DCM Maximum Off S CHARGE FB 1V + - Enable Q GND 0.8V STAT SW FB R SW + - IPEAK SW OVP CS Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS9595-04 March 2012 RT9595 Functional Pin Description Pin No. 1, 11 (Exposed Pad) Pin Name Pin Function GND Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. 2 DRVOUT IGBT Driver Output Pin. 3 VDD Power Input Pin. 4 DRVIN IGBT Driver Input Pin. 5 CHARGE 6 STAT 7 FB Feedback Voltage Pin. 8 CS Input Current Setting Pin. 9 NC No Internal Connection. 10 SW N-MOSFET Switching Node. Charge Enable Pin. The charge function is executed when CHARGE pin is set from Low to High. The chip is in Shutdown mode when CHARGE pin is set to Low. Charge Status Output. Open Drain output. When target output voltage is reached, N-MOSFET turns on. This pin needs a pull up resistor. Absolute Maximum Ratings z z z z z z z z (Note 1) Supply Voltage, VDD -----------------------------------------------------------------------------------------------------Built-in N-Channel Enhancement MOSFET Drain-Source Voltage ----------------------------------------------------------------------------------------------------CS, CHARGE, DRVIN, DRVOUT, STAT, FB ------------------------------------------------------------------------SW Pulse Current (Pulse Width ≤ 1μs) ----------------------------------------------------------------------------SW Continuous Current ------------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WDFN-10L 3x3 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WDFN-10L 3x3, θJA ------------------------------------------------------------------------------------------------------WDFN-10L 3x3, θJC ------------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) ---------------------------------------------------------------------------------------------MM (Machine Mode) ------------------------------------------------------------------------------------------------------ Recommended Operating Conditions z z z 6V 45V 6V 4A 2A 1.667W 60°C/W 7.5°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Drain Source Voltage ----------------------------------------------------------------------------------------------------- 40V Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9595-04 March 2012 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT9595 Electrical Characteristics (VDD = 3.3V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 2.9 -- 5.5 V VDD Operating Voltage VDD Switch Off Current IVDD_SW_OFF VFB = 1.1V -- 1 10 μA Shutdown Current IOFF CHARGE pin = 0V -- 0.01 1 μA FB Voltage VFB 0.985 1 1.015 V Line Regulation | ΔVFB | -- -- 10 mV -- 11 19 Ω 2.9V < VDD < 5.5V STAT Open Drain RDS(ON) Charge Enable High VCEH 1.3 -- -- V Charge Enable Low VCEL -- -- 0.4 V -- 0.3 0.4 Ω Maximum Off Time During Pre-Charge -- 9 -- μs Minimum Off Time -- 400 -- ns 0.8 1.5 2.4 V Built-In N-Channel Enhancement MOSFET Drain-Source On-Resistance RDS(ON) VDD = 3.3V, I D = 10mA IGBT Driver DRVIN Trip Point DRVOUT On Resistance to VDD VDD = 3.3V -- 6 -- Ω DRVOUT On Resistance to GND VDD = 3.3V -- 11 -- Ω Propagation Delay (Rising) -- 20 -- ns Propagation Delay (Falling) -- 200 -- ns Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS9595-04 March 2012 RT9595 Typical Operating Characteristics Switching Switching VSW (20V/Div) VSW (20V/Div) I PRI (1A/Div) I PRI (1A/Div) I SEC (200mA/Div) I SEC (200mA/Div) VDD = 3.3V, VOUT = 100V, VBAT = 3.7V VDD = 3.3V, VOUT = 300V, VBAT = 3.7V Time (2.5μs/Div) Time (2.5μs/Div) Charge Time vs. VBAT Charging Time 14 CHARGE (5V/Div) VDD = 3.3V, VOUT = 0 to 300V, COUT = 140μF Charge Time (s) 12 STAT (5V/Div) I IN (500mA/Div) VOUT (200V/Div) 10 8 6 IPK-PRI = 1.4A 4 IPK-PRI = 1.6A VDD = 3.3V, VBAT = 3.7V, COUT = 140μF 2 1.5 Time (1s/Div) 2 2.5 3 3.5 4 4.5 5 5.5 VBAT (V) Charge Time vs. VBAT 14 Output Voltage vs. VBAT 310 VDD = 5V, VOUT = 0 to 300V, COUT = 140μF VDD = 3.3V 308 306 Output Voltage (V) Charge Time (s) 12 10 8 6 IPK-PRI = 1.4A 304 302 300 298 296 85°C 25°C −40°C 294 4 292 IPK-PRI = 1.6A 290 2 1.5 2 2.5 3 3.5 4 4.5 5 VBAT (V) Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9595-04 March 2012 5.5 1.5 2 2.5 3 3.5 4 4.5 5 5.5 VBAT (V) is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT9595 Application Information The RT9595 integrates a constant peak current controller for charging photoflash capacitor and an IGBT driver for igniting flash tube. The photoflash capacitor charger uses constant primary peak current and SW falling control to efficiently charge the photoflash capacitor. Pulling the CHARGE pin high will initiate the charging cycle. However, the CHARGE signal must come from low to high after VDD > 2V for at lease 1μs delay time. VDD 2V Charge Current Setting The RT9595 simply adjusts peak primary current by a resistor RCS connecting to the CS pin as shown in the Function Block Diagram. RCS determines the peak current of the primary N-MOSFET according to the following equation : 40000 IPK_PRI = (A) RCS Where the IPK-PRI is the primary peak current. Users could select appropriate RCS according to the battery capability and required charging time. Transformer CHARGE The flyback transformer should be appropriately designed to ensure effective and efficient operation. >1µs Figure 1. Recommend Charge Timing Chart During MOSFET on period, the primary current ramps up linearly according to VBAT and primary inductance. A resistor connecting from CS pin to GND determines the primary peak current. During the MOSFET off period, the energy stored in the flyback transformer is boosted to the output capacitor. The secondary current decreases linearly at a rate determined by the secondary inductance and the output voltage (neglecting the voltage drop of the diode). The SW pin monitors the secondary current. When the secondary current drops to 0A, SW voltage falls, and then the MOSFET on period starts again. The charging cycle repeats itself and charges the output capacitor. The output voltage is sensed by a voltage divider connecting to the anode of the rectifying diode. When the output voltage reaches the desired voltage set by the resistor divider, the charging block will be disabled and charging will be stopped. Then STAT pin will be pulled low to indicate the complete charging. The voltage-sensing path will be cut off when charging is completed to minimize the output voltage decay. Both the CHARGE and STAT pins can be easily interfaced to a microprocessor in a digital system. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 1. Turns Ratio The turns ratio of transformer (N) should be high enough so that the absolute maximum voltage rating for the internal N-MOSFET drain to source voltage is not exceeded. Choose the minimum turns ratio according to the following formula : VOUT NMIN ≥ 40 − VBAT Where : VOUT : Target Output Voltage VBAT : Battery Voltage 2. Primary Inductance Each switching cycle, energy transferred to the output capacitor is proportional to the primary inductance for a constant primary current. The higher the primary inductance, the higher the charging efficiency. Besides, to ensure enough off time for the output voltage sensing, the primary inductance should be high enough according to the following formula : 400 × 10-9 × VOUT LPRI ≥ N × IPK-PRI VOUT : Target Output Voltage N : Transformer turns ratio IPK-PRI : Primary peak current is a registered trademark of Richtek Technology Corporation. DS9595-04 March 2012 RT9595 3. Leakage Inductance If VOUT = 300V, according the following equation : The leakage inductance of the transformer results in the first spike voltage when N-MOSFET turns off. The spike voltage is proportional to the leakage inductance and inductor peak current. The spike voltage must not exceed the dynamic rating of the N-MOSFET drain to source voltage (45V). VOUT = VFB × (1 + 4. Transformer Secondary Capacitance Any capacitance on the secondary can severely affect the efficiency. A small secondary capacitance is multiplied by N2 when reflected to the primary will become large. R1+R2 R1+R2 ) and = 299 R3 R3 It is recommended to set R3 = 1kΩ and R1 = R2 = 150kΩ for reducing parasitic capacitance coupling effect of the FB pin. R1 and R2 MUST be greater than 0805 size resistor for enduring secondary HV. Another sensing method is to sense the output voltage directly as shown in Figure 3. V OUT R1 150k This capacitance forms a resonant circuit with the primary leakage inductance of the transformer. Therefore, both the primary leakage inductance and secondary side capacitance should be minimized. C OUT R2 150k FB R3 1k Rectifying Diode The rectifying diode should be with short reverse recovery time (small parasitic capacitance). Large parasitic capacitance increases switching loss and lowers charging efficiency. Figure 2. Sensing Anode of Diode V OUT R1 10M In addition, the peak reverse voltage and peak current of the diode should be sufficient. R2 10M C OUT FB The peak reverse voltage of the diode can be calculated as following Equation : C1 10nF R3 66.5k VPK-R ≈ VOUT + (N × VBAT ) The peak current of the diode equals the primary peak current divided by the transformer turn ratio as the following equation : I IPK-SEC = PK-PRI N Where : N is the transformer turns ratio. Output Voltage Setting The RT9595 senses the output voltage by a voltage divider connecting to the anode of the rectifying diode during OFF time as shown in Figure 2. This eliminates power loss at voltage-sensing circuit when charging is completed. R1 to R2 ratio determines the output voltage as shown in the typical application circuit. The feedback reference voltage is 1V. Copyright © 2012 Richtek Technology Corporation. All rights reserved. DS9595-04 March 2012 Figure 3. Sensing Output Voltage Over Voltage Protection (OVP) The RT9595 provides over voltage protection (OVP) function. In the typical application circuit, if the FB resistor R1, R2 or R3 is open, the FB voltage will be pulled low or floating. In this condition, when the CHARGE pin goes High, the RT9595 begins switching, once the SW voltage rises to higher than 10V, the OVP function will be triggered. The avoiding OVP battery voltage upper limit is shown as the following equation : VBAT < 10V − 0.16 × (R1+R2+R3) N × R3 N : Transformer turns ratio. is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT9595 1.8 Maximum Power Dissipation (W) False Triggering Prevention The RT9595 includes a mechanism to prevent false triggering of DRVOUT while the device is still in charging mode. With this mechanism, the DRVIN pin is only allowed to trigger DRVOUT when the CHARGE pin is low. BUF DRVIN DRVOUT CHARGE Four Layers PCB 1.6 1.4 1.2 WDFN-10L 3x3 1.0 0.8 0.6 0.4 0.2 0.0 0 Figure 4. Trigger Logic 25 50 75 100 125 Ambient Temperature (°C) For continuous operation, do not exceed absolute maximum operation junction temperature. The maximum power dissipation depends on the thermal resistance of IC package, PCB layout, the rate of surroundings airflow and temperature difference between junction to ambient. The maximum power dissipation can be calculated by following formula : Figure 5. Derating Curve of Maximum Power Dissipation Layout Consideration For best performance, the following guidelines should be strictly followed. ` Both of primary and secondary power paths should be as short as possible. ` Place the RCS as close to chip as possible. The GND side of RCS should be directly connected to ground plane to avoid noise coupling. ` Keep FB node area small and far away from nodes with voltage switching to reduce parasitic capacitance coupling effect. ` The PGND should be connected to VBAT ground plane to reduce switching noise. PD(MAX) = (TJ(MAX) − TA) / θJA Where T J(MAX) is the maximum operation junction temperature , TA is the ambient temperature and the θJA is the junction to ambient thermal resistance. For recommended operating conditions specification, the maximum junction temperature is 125°C. The junction to ambient thermal resistance θJA is layout dependent. For WDFN-10L 3x3 packages, the thermal resistance θJA is 60°C/W on the standard JEDEC 51-7 four layers thermal test board. The maximum power dissipation at TA = 25°C can be calculated by following formula : PD(MAX) = (125°C − 25°C) / (60°C/W) = 1.667W for WDFN-10L 3x3 packages The maximum power dissipation depends on operating ambient temperature for fixed T J(MAX) and thermal resistance θJA. For WDFN-10L 3x3 package, the Figure 5 of derating curves allows the designer to see the effect of rising ambient temperature on the maximum power allowed. Copyright © 2012 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 VOUT PGND Bottom GND 1 10 SW DRVOUT 2 9 NC 8 CS VDD 3 DRVIN 4 CHARGE 5 GND Thermal Considerations 7 11 6 PGND VBAT RCS FB STAT GND GND Figure 6. Recommended Layout Guideline is a registered trademark of Richtek Technology Corporation. DS9595-04 March 2012 RT9595 Outline Dimension D2 D L E E2 1 e SEE DETAIL A b 2 1 2 1 A A1 A3 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 2.300 2.650 0.091 0.104 E 2.950 3.050 0.116 0.120 E2 1.500 1.750 0.059 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 10L DFN 3x3 Package Richtek Technology Corporation 5F, No. 20, Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. DS9595-04 March 2012 www.richtek.com 9