24AA52/24LCS52
2K 2.2V I2C™ Serial EEPROM with Software Write-Protect
Description:
Device Selection Table
Part
Number
VCC
Range
Max Clock
Frequency
Temp
Ranges
24AA52
1.8-5.5
400 kHz(1)
I
24LCS52
2.2-5.5
400 kHz
I
Note 1:
100 kHz for VCC <2.2V
Features:
• Single Supply with Operation Down to 1.8V
• Low-Power CMOS Technology:
- 1 mA active current, typical
- 1 A standby current, typical (I-temp)
• Organized as 1 Block of 256 Bytes (256 x 8)
• Software Write Protection for Lower 128 Bytes
• Hardware Write Protection for Entire Array
• 2-Wire Serial Interface Bus, I2C™ Compatible
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz (24AA52) and 400 kHz (24LCS52)
Compatibility
• Self-Timed Write Cycle (including auto-erase)
• Page Write Buffer for up to 16 Bytes
• ESD Protection > 4,000V
• 1,000,000 Erase/Write Cycles
• Data Retention > 200 Years
• 8-Lead PDIP, SOIC, TSSOP, MSOP, DFN and
TDFN Packages
• Pb-Free Finishes Available
• Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +85°C
The Microchip Technology Inc. 24AA52/24LCS52
(24XXX52*) is a 2 Kbit Electrically Erasable PROM
capable of operation across a broad voltage range
(1.8V to 5.5V). This device has a software write-protect
feature for the lower half of the array, as well as an
external pin that can be used to write-protect the entire
array. The software write-protect feature is enabled by
sending the device a special command. Once this
feature has been enabled, it cannot be reversed. In
addition to the software protect feature, there is a WP
pin that can be used to write-protect the entire array,
regardless of whether the software write-protect
register has been written or not. This allows the system
designer to protect none, half, or all of the array,
depending on the application. The device is organized
as one block of 256 x 8-bit memory with a 2-wire serial
interface. Low-voltage design permits operation down
to 1.8V, with standby and active currents of only 1 A
and 1 mA, respectively. The 24XXX52 also has a page
write capability for up to 16 bytes of data. The 24XXX52
is available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, MSOP, DFN and TDFN packages.
Block Diagram
A0 A1 A2
I/O
Control
Logic
SDA SCL
VCC
VSS
Package Types
PDIP/SOIC/TSSOP/MSOP/DFN/TDFN
A0
1
8
VCC
A1
2
7
WP
A2
3
6
SCL
VSS
4
5
SDA
A0 1
A1 2
A2 3
VSS 4
WP
Memory
Control
Logic
HV Generator
XDEC
Software write
protected area
(00h-7Fh)
Standard
Array
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
8 VCC
7 WP
6 SCL
5 SDA
*24XXX52 is used in this document as a generic part number
for the 24AA52/24LCS52 devices.
1996-2011 Microchip Technology Inc.
DS21166K-page 1
24AA52/24LCS52
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ......................................................................................................... -0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied ................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
VCC = +1.8V to +5.5V
Industrial (I): TA = -40°C to +85°C
Min
Typ
Max
Units
Conditions
D1
VIH
A0, A1, A2, SCL, SDA
and WP pins
—
—
—
—
—
D2
—
High-level input voltage
0.7 VCC
—
—
V
—
D3
VIL
Low-level input voltage
D4
VHYS
Hysteresis of Schmitt
Trigger inputs
D5
VOL
D6
ILI
D7
D8
D9
ICC write Operating current
—
—
0.3 VCC
V
0.2 VCC for VCC < 2.5V
0.05 VCC
—
—
V
(Note)
Low-level output voltage
—
—
0.40
V
IOL = 3.0 mA, VCC = 2.5V
Input leakage current
—
—
±1
A
VIN = VSS or VCC
ILO
Output leakage current
—
—
±1
A
VOUT = VSS or VCC
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
—
10
pF
VCC = 5.0V (Note)
TA = 25°C, FCLK = 1 MHz
—
1.0
3.0
mA
VCC = 5.5V, SCL = 400 kHz
D10
ICC read
D11
ICCS
Note:
Standby current
—
0.20
1.0
mA
—
—
—
0.36
—
1.0
—
A
Industrial
SDA = SCL = VCC
A0, A1, A2, WP = VSS
This parameter is periodically sampled and not 100% tested.
DS21166K-page 2
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
TABLE 1-2:
AC SPECIFICATIONS
AC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
VCC = +1.8V to +5.5V
Industrial (I): TA = -40°C to +85°C
Min
Typ
Max
Units
Conditions
1
FCLK
Clock frequency
—
—
—
—
400
100
kHz
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
2
THIGH
Clock high time
600
4000
—
—
—
—
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
3
TLOW
Clock low time
1300
4700
—
—
—
—
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
4
TR
SDA and SCL rise time
(Note 1)
—
—
—
—
300
1000
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
5
TF
SDA and SCL fall time
—
—
—
300
ns
(Note 1)
6
THD:STA
Start condition hold time
600
4000
—
—
—
—
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
7
TSU:STA
Start condition setup
time
600
4700
—
—
—
—
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
8
THD:DAT
Data input hold time
0
—
—
—
ns
(Note 2)
9
TSU:DAT
Data input setup time
100
250
—
—
—
—
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
10
TSU:STO
Stop condition setup
time
600
4000
—
—
—
—
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
11
TAA
Output valid from clock
(Note 2)
—
—
—
—
900
3500
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
12
TBUF
Bus free time: Time the
bus must be free before
a new transmission can
start
1300
4700
—
—
—
—
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
13
TOF
Output fall time from VIH 20 + 0.1 CB
minimum to VIL
—
maximum
—
—
250
250
ns
2.2V VCC 5.5V
1.8V VCC 2.5V (24AA52)
14
TSP
Input filter spike
suppression
(SDA and SCL pins)
—
—
50
ns
(Note 1 and Note 3)
15
TWC
Write cycle time
(byte or page)
—
—
5
ms
—
16
—
Endurance
1M
—
—
cycles 25°C, VCC = 5.0V (Note 4)
Note 1: Not 100% tested. CB = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site
at www.microchip.com.
1996-2011 Microchip Technology Inc.
DS21166K-page 3
24AA52/24LCS52
FIGURE 1-1:
BUS TIMING DATA
5
4
2
3
SCL
7
SDA
IN
8
10
9
6
14
12
11
SDA
OUT
FIGURE 1-2:
BUS TIMING START/STOP
D4
SCL
6
7
10
SDA
Start
DS21166K-page 4
Stop
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Symbol
PDIP
SOIC
TSSOP
MSOP
DFN(1)
TDFN(1)
A0
1
1
1
1
1
1
Chip Address Input
A1
2
2
2
2
2
2
Chip Address Input
A2
3
3
3
3
3
3
Chip Address Input
VSS
4
4
4
4
4
4
Ground
SDA
5
5
5
5
5
5
Serial Address/Data I/O
SCL
6
6
6
6
6
6
Serial Clock
WP
7
7
7
7
7
7
Write-Protect Input
VCC
8
8
8
8
8
8
+1.8V to 5.5V Power Supply
Note 1:
2.1
The exposed pad on the DFN/TDFN packages can be connected to VSS or left floating.
A0, A1, A2
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 24XXX52 devices may be connected to the
same bus by using different Chip Select bit
combinations. These inputs must be connected to
either VSS or VCC.
2.2
Description
Serial Address/Data Input/Output
(SDA)
2.3
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
2.4
Write-Protect (WP)
This is the hardware write-protect pin. It can be tied to
VCC or VSS. If tied to VCC, the hardware write protection
is enabled. If the WP pin is tied to VSS, the hardware
write protection is disabled.
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pullup resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
1996-2011 Microchip Technology Inc.
DS21166K-page 5
24AA52/24LCS52
3.0
FUNCTIONAL DESCRIPTION
The 24XXX52 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data, as a receiver. The bus has to be
controlled by a master device, which generates the
Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24XXX52
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
4.1
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
4.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
FIGURE 4-1:
SCL
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited; although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out (FIFO) fashion.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
Note:
Bus Not Busy (A)
Both data and clock lines remain high.
4.2
4.4
The 24XXX52 does not generate any
Acknowledge
bits
if
an
internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-ofdata to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (24XXX52) will leave the data
line high to enable the master to generate the Stop
condition.
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
Start
Condition
Address or
Acknowledge
Valid
(D)
(C)
(A)
SDA
DS21166K-page 6
Data
Allowed
to Change
Stop
Condition
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
4.6
Device Addressing
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code which is
set to ‘1010’ for normal read and write operations and
‘0110’ for writing to the write-protect register. The
control byte is followed by three Chip Select bits (A2,
A1, A0). The Chip Select bits allow the use of up to
eight 24XXX52 devices on the same bus and are used
to determine which device is accessed. The Chip
Select bits in the control byte must correspond to the
logic levels on the corresponding A2, A1 and A0 pins
for the device to respond. The device will not acknowledge if you attempt a Read command with the control
code set to ‘0110’.
The eighth bit of slave address determines if the master
device wants to read or write to the 24XXX52
(Figure 4-2). When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected.
Control
Code
Chip
Select
R/W
Read
1010
A2 A1 A0
1
Write
1010
A2 A1 A0
0
Set Write-Protect
Register
0110
A2 A1 A0
0
Operation
FIGURE 4-2:
CONTROL BYTE
ALLOCATION
Start
Read/Write
Slave Address
1
0
1
0
R/W A
A2
A1
A0
A2
A1
A0
OR
0
1
1
0
5.0
WRITE OPERATIONS
5.1
Byte Write
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit, which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow,
once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the Address Pointer of the 24XXX52.
1996-2011 Microchip Technology Inc.
After receiving another Acknowledge signal from the
24XXX52, the master device will transmit the data word
to be written into the addressed memory location. The
24XXX52 acknowledges again and the master generates a Stop condition. This initiates the internal write
cycle, which means that during this time, the 24XXX52
will not generate Acknowledge signals (Figure 5-1). If
an attempt is made to write to the array when the software or hardware write protection has been enabled,
the device will acknowledge the command, but no data
will be written. The write cycle time must be observed
even if the write protection is enabled.
5.2
Page Write
The write control byte, word address and the first data
byte are transmitted to the 24XXX52 in the same way
as in a byte write. Instead of generating a Stop condition, the master transmits up to 15 additional data bytes
to the 24XXX52, which are temporarily stored in the onchip page buffer and will be written into the memory
after the master has transmitted a Stop condition. Upon
receipt of each word, the four lower order Address
Pointer bits are internally incremented by one. The
higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 5-2). If an attempt
is made to write to the array when the hardware write
protection has been enabled, the device will acknowledge the command, but no data will be written. The
write cycle time must be observed even if the write
protection is enabled.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multiples of the page buffer size (or ‘page size’)
and end at addresses that are integer multiples of [page size – 1]. If a Page Write
command attempts to write across a physical page boundary, the result is that the
data wraps around to the beginning of the
current page (overwriting data previously
stored there), instead of being written to
the next page, as might be expected. It is
therefore necessary for the application
software to prevent page write operations
that would attempt to cross a page
boundary.
DS21166K-page 7
24AA52/24LCS52
FIGURE 5-1:
BYTE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
Word
Address
P
A
C
K
Bus Activity
FIGURE 5-2:
S
T
A
R
T
SDA Line
S
DS21166K-page 8
A
C
K
A
C
K
PAGE WRITE
Bus Activity
Master
Bus Activity
S
T
O
P
Data
Control
Byte
Word
Address (n)
Data (n + 1)
Data (n)
S
T
O
P
Data (n + 15)
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
6.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 6-1 for flow
diagram.
FIGURE 6-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
1996-2011 Microchip Technology Inc.
DS21166K-page 9
24AA52/24LCS52
7.0
WRITE PROTECTION
The 24XXX52 has a software write-protect feature that
allows the lower half of the array (addresses 00h-7Fh)
to be permanently write-protected, as well as a WP pin
that can be used to protect the entire array.
7.1
Software Write-Protect
The software write-protect feature is invoked by writing
to the write-protect register. This is done by sending a
command similar to a normal Write command. As shown
in Figure 7-1, the write-protect register is written by
sending a Write command with the slave address set to
‘0110’ instead of ‘1010’ and the address bits and data
bits are “don’t cares.” Once the software write-protect
register has been written, the device will not
acknowledge the ‘0110’ control byte.
FIGURE 7-1:
SETTING WRITE-PROTECT REGISTER
Bus Activity
Master
S
T
A
R
T
SDA Line
S 0
Control
Byte
1
1
S
T
O
P
Data
P
0
Bus Activity
7.2
Word
Address
A
C
K
A
C
K
A
C
K
Resetting the Software
Write-Protect Fuse
It is possible to reset the software write-protect feature
on the 24XXX52. This is done by sending a command
similar to setting the software write-protect command,
except the command is sent before the regular control
byte and is ‘1001’. The full command will be shown in
Figure 7-2. In order for the command to work, a voltage
of Vcc + 5.5V must be applied to the WP pin and must
be sustained for 1S before the command is given. The
customer should also allow for a 5 ms delay after the
Stop bit for TWC.
DS21166K-page 10
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
FIGURE 7-2:
RESETTING WRITE-PROTECT FUSE (RWPF)
WP = VHH = VCC + 5.5V
1s
RWPF
Command
Bus Activity
Master
SDA Line
S
T
A
R
T
Control
Byte
1 0 0 1 0 0 0 S 1 0 1 0 0 0 0 0
Bus Activity
Note:
7.3
Word
Address (0x09)
0 0 0 0 1 0 0 1
A
C
K
S
T
O
P
Data (0xFF)
P
1 1 1 1 1 1 1 1
A
C
K
TWC
A
C
K
Clock = 100 kHz, VDD = 1.8V to 5.5V
Hardware Write-Protect
The WP pin can be tied to VCC or VSS. If tied to VCC, the
entire array will be write-protected, regardless of
whether the software write-protect register has been
written or not. If the WP pin is set to VCC, it will prevent
the software write-protect register from being written. If
the WP is tied to VSS, write protection is determined by
the status of the software write-protect register for
addresses 00h-7Fh. Addresses 80h-FFh are solely
protected by the WP pin level.
1996-2011 Microchip Technology Inc.
DS21166K-page 11
24AA52/24LCS52
8.0
READ OPERATION
8.3
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
8.1
Current Address Read
The 24XXX52 contains an address counter that
maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n+1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 24XXX52
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24XXX52
discontinues transmission (Figure 8-1).
8.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
24XXX52 as part of a write operation. Once the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. The master then issues the control byte again, but
with the R/W bit set to a ‘1’. The 24XXX52 then issues
an acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 24XXX52
discontinues transmission (Figure 8-2).
FIGURE 8-1:
Sequential Read
Sequential reads are initiated in the same way as a
random read, with the exception that after the 24XXX52
transmits the first data byte, the master issues an
acknowledge, as opposed to a Stop condition in a
random read. This directs the 24XXX52 to transmit the
next sequentially addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24XXX52 contains an
internal Address Pointer, which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4
Contiguous Addressing Across
Multiple Devices
The Chip Select bits (A2, A1, A0) can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24XXX52 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A8; A1 as address bit A9, and A2
as address bit A10. It is not possible to sequentially
read across device boundaries.
8.5
Noise Protection and Brown-Out
The 24XXX52 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Bus Activity
DS21166K-page 12
Control
Byte
S
T
O
P
Data (n)
P
A
C
K
N
O
A
C
K
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
FIGURE 8-2:
RANDOM READ
Bus Activity
Master
S
T
A
R
T
Control
Byte
S
SDA Line
Bus Activity
Master
Control
Byte
S
T
O
P
Data (n)
P
S
A
C
K
Bus Activity
FIGURE 8-3:
S
T
A
R
T
Word
Address (n)
A
C
K
A
C
K
N
O
A
C
K
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + X)
SDA Line
Bus Activity
P
A
C
K
1996-2011 Microchip Technology Inc.
A
C
K
A
C
K
A
C
K
N
O
A
C
K
DS21166K-page 13
24AA52/24LCS52
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
XXXXXXXX
TXXXXNNN
YYWW
8-Lead SOIC (150 mil)
XXXXXXXT
XXXXYYWW
NNN
8-Lead TSSOP
24AA52
I/P e3 3EC
0510
Example:
24LCS52I
SN e3 0510
3EC
Example:
XXXX
S52
TYWW
I510
NNN
3EC
8-Lead MSOP
Example:
XXXXXT
4S52I
YWWNNN
5103EC
8-Lead 2x3 DFN
XXX
YWW
NN
8-Lead 2x3 TDFN
XXX
YWW
NN
DS21166K-page 14
Example:
Example:
2M4
510
3E
Example:
AM4
510
3E
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
Part Number
TSSOP
MSOP
DFN
TDFN
24AA52
A52
4A52I
2M1
AM1
24LCS52
S52
4S52I
2M4
AM4
Legend: XX...X
T
Y
YY
WW
NNN
e3
Note:
Note:
Note:
1st Line Marking Codes
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
1996-2011 Microchip Technology Inc.
DS21166K-page 15
24AA52/24LCS52
3
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E1
1
3
2
D
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A2
A
L
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c
e
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b1
b
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=
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<
: 9&
-<
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9
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=
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9
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: *+
1,
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+%&,&!&
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!#.#
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DS21166K-page 16
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1996-2011 Microchip Technology Inc.
DS21166K-page 17
24AA52/24LCS52
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS21166K-page 18
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
!
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3
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1996-2011 Microchip Technology Inc.
DS21166K-page 19
24AA52/24LCS52
() )"* !
(+%+(
!
3
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N
E
E1
NOTE 1
1
2
b
e
c
A
φ
A2
A1
L
L1
6&!
'!
9'&!
7"')
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99..
7
7
7:
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: 8&
=
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##4>#&
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9
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.3
3
&
R
=
<R
9#4!!
=
9#>#&
)
=
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'!
!#.#
&"#'
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&"!
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#%!
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!!
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- '!
#&
.0
1,2 1!'!
&$& "!
**&
"&&
!
.32 %'!
("!"*&
"&&
(%
%
'&
"
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* ,<?1
DS21166K-page 20
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1996-2011 Microchip Technology Inc.
DS21166K-page 21
24AA52/24LCS52
," !
*-, , !
3
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N
E
E1
NOTE 1
1
2
e
b
A2
A
c
φ
L
L1
A1
6&!
'!
9'&!
7"')
%!
99..
7
7
7:
;
<
&
: 8&
=
?1,
=
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<
&#
%%
=
: >#&
.
##4>#&
.
-1,
: 9&
-1,
3
&9&
9
3
&&
9
1,
?
<
.3
3
&
R
=
<R
9#4!!
<
=
-
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)
=
!"#$%&"' ()"&'"!&)
&#*&&&#
'!
!#.#
&"#'
#%!
&"!
!
#%!
&"!
!!
&$#''!#
- '!
#&
.0
1,2 1!'!
&$& "!
**&
"&&
!
.32 %'!
("!"*&
"&&
(%
%
'&
"
!!
* ,1
DS21166K-page 22
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1996-2011 Microchip Technology Inc.
DS21166K-page 23
24AA52/24LCS52
.
$*-,'/00%&.
3
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e
D
b
N
N
L
K
E2
E
EXPOSED PAD
NOTE 1
NOTE 1
2
1
2
1
D2
BOTTOM VIEW
TOP VIEW
A
A3
A1
NOTE 2
6&!
'!
9'&!
7"')
%!
99..
7
7
7:
;
<
&
: 8&
<
&#
%%
,
&&4!!
-
.3
: 9&
1,
: >#&
.
.$
!##9&
-
=
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=
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&&9&
9
-
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&&&
.$
!##
U
=
=
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&&>#&
1,
-1,
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&#*&&&#
4' '
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- 4!!*!"&#
'!
#&
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1,2 1!'!
&$& "!
**&
"&&
!
.32 %'!
("!"*&
"&&
(%
%
'&
"
!!
* ,-,
DS21166K-page 24
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1996-2011 Microchip Technology Inc.
DS21166K-page 25
24AA52/24LCS52
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS21166K-page 26
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
1996-2011 Microchip Technology Inc.
DS21166K-page 27
24AA52/24LCS52
.
$*-,/00%12(.
3
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4%&
&#&
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DS21166K-page 28
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
APPENDIX A:
REVISION HISTORY
Revision G
Added 2.2V to document; Revised Features section to
include Standard and Pb-free finishes.
Corrections to Section 1.0, Electrical Characteristics;
Product ID System, added lead finish info.
Revision H
Added Reset Software Write-Protect feature.
Added 2x3 DFN package option.
Revision J
Revised Sections 6.3 and 8.4. Revised DFN Package
Drawing.
Revision K (11/2011)
Added TDFN package.
1996-2011 Microchip Technology Inc.
DS21166K-page 29
24AA52/24LCS52
NOTES:
DS21166K-page 30
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
1996-2011 Microchip Technology Inc.
DS21166K-page 31
24AA52/24LCS52
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: 24AA52/24LCS52
Literature Number: DS21166K
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS21166K-page 32
1996-2011 Microchip Technology Inc.
24AA52/24LCS52
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
X
/XX
Temperature Package
Range
X
Lead Finish
Examples:
a)
b)
Device:
= 1.8V, 2 Kbit I2C Serial EEPROM
= 1.8V, 2 Kbit I2C Serial EEPROM
(Tape and Reel)
24LCS52: = 2.2V, 2 Kbit I2C Serial EEPROM
24LCS52T: = 2.2V, 2 Kbit I2C Serial EEPROM
(Tape and Reel)
24AA52:
24AA52T:
Temperature I
Range:
Package:
=
P
=
SN
=
ST
=
MS =
MC =
MNY(1)=
-40°C to +85°C
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (150 mil body), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
Plastic Micro Small Outline (MSOP), 8-lead
Micro Lead Frame (2x3 mm body), 8-lead
TDFN (2x3x0.75 mm body), 8-lead (Tape
and Reel only)
c)
d)
e)
f)
g)
24AA52-I/P: Industrial Temperature,
1.8V, PDIP package
24AA52-I/SN: Industrial Temperature,
1.8V, SOIC package
24AA52T-I/MS: Tape and Reel, Industrial
Temperature, 1.8V, MSOP package
24LCS52-I/P: Industrial
2.2V, PDIP package
24LCS52-I/MC: Industrial
2.2V, DFN package
24LCS52T-I/MS: Tape
Industrial Temperature,
package
Temperature,
Temperature,
and Reel,
2.2V, MSOP
24LCS52T-I/MNY: Tape and Reel, Industrial Temperature, 2.2V, TDFN package
Note 1: "Y" indicates a Nickel Palladium Gold (NiPdAu) finish.
1996-2011 Microchip Technology Inc.
DS21166K-page33
24AA52/24LCS52
NOTES:
DS21166K-page 34
1996-2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, chipKIT,
chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net,
dsPICworks, dsSPEAK, ECAN, ECONOMONITOR,
FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP,
Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB,
MPLINK, mTouch, Omniscient Code Generation, PICC,
PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE,
rfLAB, Select Mode, Total Endurance, TSHARC,
UniWinDriver, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 1996-2011, Microchip Technology Incorporated, Printed in
the U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-61341-786-7
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
1996-2011 Microchip Technology Inc.
DS21166K-page 35
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4123
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
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Tel: 91-20-2566-1512
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Tel: 33-1-69-53-63-20
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Tel: 81-45-471- 6166
Fax: 81-45-471-6122
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Tel: 49-89-627-144-0
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Tel: 678-957-9614
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Mississauga, Ontario,
Canada
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Fax: 905-673-6509
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Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8569-7000
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
China - Chongqing
Tel: 86-23-8980-9588
Fax: 86-23-8980-9500
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
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China - Hangzhou
Tel: 86-571-2819-3187
Fax: 86-571-2819-3189
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Taiwan - Hsin Chu
Tel: 886-3-5778-366
Fax: 886-3-5770-955
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-330-9305
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Zhuhai
Tel: 86-756-3210040
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DS21166K-page 36
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