34AA02/34LC02
2K I2C™ Serial EEPROM Software Write-Protect
Package Types
Features:
• Permanent and Resettable Software Write-Protect
for Lower Half of the Array (00h-7Fh)
• Single Supply with Operation Down to 1.7V
• Low-Power CMOS Technology:
- Read current 1 mA, typical
- Standby current, 100 nA, typical
• 2-Wire Serial Interface Bus, I2C™ Compatible
• Cascadable up to Eight Devices
• Schmitt Trigger Inputs for Noise Suppression
• Output Slope Control to Eliminate Ground Bounce
• 100 kHz and 400 kHz Compatibility
• 1 MHz Clock for LC Versions
• Page Write Time 3 ms, typical
• Self-Timed Erase/Write Cycle
• 16-Byte Page Write Buffer
• ESD Protection > 4,000V
• Software Write Protection for Lower 128 Bytes
• Hardware Write Protection for Entire Array
• More than 1 Million Erase/Write Cycles
• Data Retention > 200 Years
• 8-Lead PDIP, SOIC, TSSOP, MSOP and TDFN
Packages
• 6-Lead SOT-23 Package
• Pb-free and RoHS Compliant
• Available for Extended Temperature Ranges:
- Industrial (I): -40°C to +85°C
- Automotive (E): -40°C to +125°C
Device Selection Table
Part
Number
34AA02
34LC02
Note 1:
VCC
Range
Max. Clock
Frequency
Temp
Ranges
1.7-5.5
400 kHz(1)
I,E
2.2-5.5
1 MHz
I,E
PDIP/SOIC/TSSOP/MSOP/TDFN
A0
1
8
VCC
A1
2
7
WP
A1 2
A2
3
6
SCL
VSS
4
5
SDA
A2 3
VSS 4
A0 1
8 VCC
7 WP
6 SCL
5 SDA
SOT-23
SCL
1
6 VCC
VSS
2
5
SDA
3
4 A1
A0
Description:
The Microchip Technology Inc. 34AA02/34LC02
(34XX02*) is a 2 Kbit Electrically Erasable PROM
capable of operation across a broad voltage range
(1.7V to 5.5V). This device has two software writeprotect features for the lower half of the array, as well
as an external pin that can be used to write-protect the
entire array. This allows the system designer to protect
none, half, or all of the array, depending on the
application. The device is organized as one block of
256 x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with
standby and active currents of only 100 nA and 1 mA,
respectively. The 34XX02 also has a page write
capability for up to 16 bytes of data. The 34XX02 is
available in the standard 8-pin PDIP, surface mount
SOIC, TSSOP, MSOP and TDFN packages. The
34XX02 is also available in the 6-lead, SOT-23
package.
100 kHz for VCC <1.8V.
*34XX02 is used in this document as a generic part number
for the 34AA02/34LC02 devices.
2011 Microchip Technology Inc.
DS22029F-page 1
34AA02/34LC02
Block Diagram
A0 A1 A2
I/O
Control
Logic
WP
HV Generator
Memory
Control
Logic
XDEC
Software writeprotected area
(00h-7Fh)
Standard
Array
SDA SCL
VCC
VSS
Write-Protect
Circuitry
YDEC
Sense Amp.
R/W Control
DS22029F-page 2
2011 Microchip Technology Inc.
34AA02/34LC02
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC.............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature with power applied................................................................................................-40°C to +125°C
ESD protection on all pins 4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. These are stress ratings only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
TABLE 1-1:
DC SPECIFICATIONS
DC CHARACTERISTICS
Param.
Symbol
No.
Characteristic
VCC = +1.7V to +5.5V
Industrial (I): TA = -40°C to +85°C
Automotive (E):TA = -40°C to +125°C
Min.
Typ.
Max.
Units
Conditions
—
A0, A1, A2, SCL, SDA
and WP pins
—
—
—
—
—
D1
VIH
High-level input voltage
0.7 VCC
—
—
V
—
D2
VIL
Low-level input voltage
D3
VHYS
Hysteresis of Schmitt
Trigger inputs
D4
VOL
Low-level output voltage
D5
VHV
High-Voltage Detect
—
—
0.3 VCC
V
0.2 VCC for VCC < 2.5V
0.05 VCC
—
—
V
(Note)
—
—
0.40
V
IOL = 3.0 mA, VCC = 2.5V
7
—
10
V
A0 Pin only, VCC < 2.2V
VCC + 4.8
—
10
V
A0 Pin only, VCC 2.2V
10
—
VCC + 4.8
V
A0 Pin only, VCC 5.2V
D6
ILI
Input leakage current
—
—
±1
A
VIN = VSS or VCC
D7
ILO
Output leakage current
—
—
±1
A
VOUT = VSS or VCC
D8
CIN,
COUT
Pin capacitance
(all inputs/outputs)
—
—
10
pF
VCC = 5.5V (Note)
TA = 25°C, FCLK = 1 MHz
D9
ICC write Operating current
—
0.1
3
mA
VCC = 5.5V, SCL = 1 MHz
D10
ICC read
—
0.05
1
mA
—
D11
ICCS
—
—
0.01
—
1
5
A
A
Industrial
Automotive
SDA = SCL = VCC
A0, A1, A2, WP = VSS
Note:
Standby current
This parameter is periodically sampled and not 100% tested.
2011 Microchip Technology Inc.
DS22029F-page 3
34AA02/34LC02
TABLE 1-2:
AC SPECIFICATIONS
VCC = +1.7V to +5.5V
Industrial (I): TA = -40°C to +85°C
Automotive (E):TA = -40°C to +125°C
AC CHARACTERISTICS
Param.
No.
Symbol
Characteristic
Min.
Max.
Units
Conditions
1
FCLK
Clock frequency
—
—
—
100
400
1000
kHz
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
2
THIGH
Clock high time
4000
600
500
—
—
—
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
3
TLOW
Clock low time
4700
1300
500
—
—
—
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
4
TR
SDA and SCL rise time (Note 1)
—
—
—
1000
300
300
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
5
TF
SDA and SCL fall time (Note 1)
—
—
—
1000
300
300
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
6
THD:STA
Start condition hold time
4000
600
250
—
—
—
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
7
TSU:STA
Start condition setup time
4700
600
250
—
—
—
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
8
THD:DAT
Data input hold time
0
—
ns
(Note 2)
9
TSU:DAT
Data input setup time
250
100
100
—
—
—
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
10
TSU:STO
Stop condition setup time
4000
600
250
—
—
—
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
11
TSU:WP
WP setup time
4000
600
600
—
—
—
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
12
THD:WP
WP hold time
4700
600
600
—
—
—
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
13
TAA
Output valid from clock (Note 2)
—
—
—
3500
900
400
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
14
TBUF
Bus free time: Time the bus must be
free before a new transmission can
start
1300
4700
—
—
—
ns
1.7V VCC < 1.8V
1.8V VCC 5.5V
2.5V VCC 5.5V (34LC02)
16
TSP
Input filter spike suppression
(SDA and SCL pins)
—
50
ns
All except 34LC02
(Note 1 and Note 3)
17
TWC
Write cycle time (byte or page)
—
5
ms
18
—
Endurance
1M
—
cycles
Note
1:
2:
3:
4:
—
25°C, VCC = 5.5V, Block mode
(Note 4)
Not 100% tested. CB = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the
falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs, which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult
the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com.
DS22029F-page 4
2011 Microchip Technology Inc.
34AA02/34LC02
FIGURE 1-1:
BUS TIMING DATA
5
SCL
7
SDA
In
3
4
D4
2
8
10
9
6
16
14
13
SDA
Out
WP
2011 Microchip Technology Inc.
(protected)
(unprotected)
11
12
DS22029F-page 5
34AA02/34LC02
2.0
FUNCTIONAL DESCRIPTION
The 34XX02 has two Software Write-Protect features
that allow you to protect half of the array from being
written (Addresses 00h-7Fh). One command, Software
Write-Protect (SWP) will prevent writes to half of the
array and is resettable by using the Clear Software
Write-Protect (CSWP) command. The other command
is Permanent Software Write-Protect (PSWP), which is
not resettable and will permanently lock half the array
from being written to. The device still has an external
pin (WP) that allows you to protect the entire array if so
desired.
The 34XX02 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data, as a receiver. The bus has to be
controlled by a master device, which generates the
Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 34XX02
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
• Data transfer may be initiated only when the bus
is not busy.
• During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited; although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out (FIFO) fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. Exceptions to this rule relating to software write
protection are described in Section 7.0 “Write Protection”. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
Note:
The 34XX02 does not generate any
Acknowledge bits
if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
course, setup and hold times must be taken into
account. During reads, a master must signal an end-ofdata to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (34XX02) will leave the data line
high to enable the master to generate the Stop
condition.
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus Not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
DS22029F-page 6
2011 Microchip Technology Inc.
34AA02/34LC02
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
Start
Condition
Address or
Acknowledge
Valid
(C)
(A)
SCL
SDA
3.6
Device Addressing
FIGURE 3-2:
A control byte is the first byte received following the
Start condition from the master device. The first part of
the control byte consists of a 4-bit control code which is
set to ‘1010’ for normal read and write operations and
‘0110’ for writing to the write-protect register. The
control byte is followed by three Chip Select bits (A2,
A1, A0). The Chip Select bits allow the use of up to
eight 34XX02 devices on the same bus and are used to
determine which device is accessed. The Chip Select
bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the
device to respond.
For the SOT-23 package, the A2 pin is not connected.
During device addressing, the A2 Chip Select bit
(Figure 3-2) should be set to ‘0’. Only four 34XX02
SOT-23 packages can be connected to the same bus.
The eighth bit of slave address determines if the master
device wants to read or write to the 34XX02
(Figure 3-2). When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected.
Control
Code
Chip
Select
R/W
Read
1010
A2 A1 A0
1
Write
1010
A2 A1 A0
0
Write-Protect Register
0110
A2 A1 A0
0
Operation
2011 Microchip Technology Inc.
Stop
Condition
Data
Allowed
to Change
CONTROL BYTE
ALLOCATION
Start
Read/Write
Slave Address
1
0
1
0
R/W A
A2
A1
A0
A2
A1
A0
OR
0
1
1
0
4.0
WRITE OPERATIONS
4.1
Byte Write
Following the Start signal from the master, the device
code(4 bits), the Chip Select bits (3 bits) and the R/W
bit, which is a logic low, are placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow,
once it has generated an Acknowledge bit during the
ninth clock cycle. Therefore, the next byte transmitted
by the master is the word address and will be written
into the Address Pointer of the 34XX02.
After receiving another Acknowledge signal from the
34XX02, the master device will transmit the data word
to be written into the addressed memory location. The
34XX02 acknowledges again and the master generates
a Stop condition. This initiates the internal write cycle,
which means that during this time, the 34XX02 will not
generate Acknowledge signals (Figure 4-1). If an
attempt is made to write to the array when the software
or hardware write protection has been enabled, the
device will acknowledge the command, but no data will
be written. The write cycle time must be observed even
if the write protection is enabled.
DS22029F-page 7
34AA02/34LC02
4.2
Page Write
Note:
The write control byte, word address and the first data
byte are transmitted to the 34XX02 in the same way as
in a byte write. Instead of generating a Stop condition,
the master transmits up to 15 additional data bytes to
the 34XX02, which are temporarily stored in the onchip page buffer and will be written into the memory
after the master has transmitted a Stop condition. Upon
receipt of each word, the four lower order Address
Pointer bits are internally incremented by one. The
higher order four bits of the word address remain
constant. If the master should transmit more than 16
bytes prior to generating the Stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the Stop condition is received, an
internal write cycle will begin (Figure 4-2). If an attempt
is made to write to the array when the hardware write
protection has been enabled, the device will acknowledge the command, but no data will be written. The
write cycle time must be observed even if the write
protection is enabled.
FIGURE 4-1:
BYTE WRITE
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Control
Byte
Word
Address
A
C
K
A
C
K
PAGE WRITE
S
T
A
R
T
SDA Line
S
DS22029F-page 8
Data
A
C
K
Bus Activity
Master
Bus Activity
S
T
O
P
P
Bus Activity
FIGURE 4-2:
Page write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes actually
being written. Physical page boundaries
start at addresses that are integer multiples of the page buffer size (or ‘page size’)
and end at addresses that are integer multiples of [page size – 1]. If a Page Write
command attempts to write across a physical page boundary, the result is that the
data wraps around to the beginning of the
current page (overwriting data previously
stored there), instead of being written to
the next page, as might be expected. It is
therefore necessary for the application
software to prevent page write operations
that would attempt to cross a page
boundary.
Control
Byte
Word
Address (n)
Data (n + 1)
Data (n)
S
T
O
P
Data (n + 15)
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
2011 Microchip Technology Inc.
34AA02/34LC02
5.0
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write
cycle, this can be used to determine when the cycle is
complete (this feature can be used to maximize bus
throughput). Once the Stop condition for a Write
command has been issued from the master, the device
initiates the internally timed write cycle. ACK polling
can be initiated immediately. This involves the master
sending a Start condition followed by the control byte
for a Write command (R/W = 0). If the device is still
busy with the write cycle, then no ACK will be returned.
If the cycle is complete, then the device will return the
ACK and the master can then proceed with the next
Read or Write command. See Figure 5-1 for flow
diagram.
FIGURE 5-1:
ACKNOWLEDGE
POLLING FLOW
Send
Write Command
Send Stop
Condition to
Initiate Write Cycle
Send Start
Send Control Byte
with R/W = 0
Did Device
Acknowledge
(ACK = 0)?
No
Yes
Next
Operation
2011 Microchip Technology Inc.
DS22029F-page 9
34AA02/34LC02
6.0
READ OPERATION
6.3
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘1’. There are three basic types
of read operations: current address read, random read
and sequential read.
6.1
Current Address Read
The 34XX02 contains an address counter that
maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous
access (either a read or write operation) was to
address n, the next current address read operation
would access data from address n+1. Upon receipt of
the slave address with R/W bit set to ‘1’, the 34XX02
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 34XX02
discontinues transmission (Figure 6-1).
6.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is done by sending the word address to the
34XX02 as part of a write operation. Once the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. The master then issues the control byte again, but
with the R/W bit set to a ‘1’. The 34XX02 then issues
an acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 34XX02
discontinues transmission (Figure 6-2).
FIGURE 6-1:
Sequential Read
Sequential reads are initiated in the same way as a
random read, with the exception that after the 34XX02
transmits the first data byte, the master issues acknowledge, as opposed to a Stop condition in a random read.
This directs the 34XX02 to transmit the next sequentially addressed 8-bit word (Figure 6-3).
To provide sequential reads, the 34XX02 contains an
internal Address Pointer, which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
6.4
Contiguous Addressing Across
Multiple Devices
The Chip Select bits (A2, A1, A0) can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 34XX02 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A8; A1 as address bit A9, and A2
as address bit A10. It is not possible to sequentially
read across device boundaries.
6.5
Noise Protection and Brown-Out
The 34XX02 employs a VCC threshold detector circuit
which disables the internal erase/write logic if the VCC
is below 1.35V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
SDA Line
S
Bus Activity
Control
Byte
S
T
O
P
Data (n)
P
A
C
K
N
O
A
C
K
DS22029F-page 10
2011 Microchip Technology Inc.
34AA02/34LC02
FIGURE 6-2:
RANDOM READ
Bus Activity
Master
S
T
A
R
T
Control
Byte
S
SDA Line
Bus Activity
Master
Control
Byte
S
T
O
P
Data (n)
P
S
A
C
K
Bus Activity
FIGURE 6-3:
S
T
A
R
T
Word
Address (n)
A
C
K
A
C
K
N
O
A
C
K
SEQUENTIAL READ
Control
Byte
Data (n)
Data (n + 1)
Data (n + 2)
S
T
O
P
Data (n + X)
SDA Line
Bus Activity
P
A
C
K
A
C
K
A
C
K
A
C
K
N
O
A
C
K
2011 Microchip Technology Inc.
DS22029F-page 11
34AA02/34LC02
7.0
WRITE PROTECTION
7.2
The 34XX02 has two software write-protect features
(SWP and PSWP) that allows the lower half of the array
(addresses 00h-7Fh) to be write-protected, as well as
a WP pin that can be used to protect the entire array.
The permanent software write-protect feature is
enabled by sending the device a special command.
Once this feature has been enabled, it cannot be
reversed. The resettable software write-protect feature
is also enabled by sending the device a special
command but can be reset by issuing another special
command. In addition to the software protect features,
there is a WP pin that can be used to write-protect the
entire array, regardless of whether the software writeprotect register has been written or not.
In addition to hardware write-protect the 34XX02 has
an additional software write-protect feature that, when
set, protects the first 128 bytes (00-7Fh) of the array
from being written.
Setting the software write protection is done by sending
the SWP instruction. SWP can also then be cleared by
issuing a CSWP instruction (see Figure 7-1).
These two instructions follow the same format as the
BYTE WRITE instruction with the exception of the
Device Type Identifier, (typically ‘1010’, instead
changes to ‘0110’). Once this identifier is recognized
by the device, the rest of the Byte Write command,
address and data, are “don’t cares”. In addition to the
identifier, high voltage must be applied to the A0 pin of
the device and specific levels must be present on A1
and A2. See Table 7-1 for the available commands.
Table 7-2 and Table 7-3 describe how the 34XX02 will
acknowledge specific commands under various
circumstances.
7.1
Software Write Protection (SWP)
and Clear Software Write
Protection (CSWP)
Hardware Write Protection
7.3
The WP pin allows the user to write-protect the entire
array (00-FF) when the pin is tied to VCC. If the pin is
tied to VSS the write protection is disabled.
Permanent Software Write-Protect
(PSWP)
The Permanent software write protection, or PSWP is
another instruction that may be used to permanently
protect the first 128 byte of the array. Once this
command is issued, the user will no longer have the
ability to clear this feature regardless of instruction,
power cycling, or state of the WP pin. Also, once this
instruction has been executed, the device will no
longer acknowledge the device identifier ‘0110’.
FIGURE 7-1:
SOFTWARE WRITE PROTECTION FOR SWP, CSWP, PSWP, OR CPSWP
Bus Activity
Master
SDA Line
Bus Activity
DS22029F-page 12
S
T
A
R
T
Control
Byte
Address
Byte
Data
AA
S0 1 10A
2 10 0
S
T
O
P
P
A
C
K
“Don’t Care”
A
C
K
A
“Don’t Care” C
K
2011 Microchip Technology Inc.
34AA02/34LC02
TABLE 7-1:
SOFTWARE WRITE PROTECTION INSTRUCTION SET WP = 0
Address Pins
A2
A1
A0
Device Type Identifier
B7
B6
B5
B4
Chip Select Bits
B3
B2
VSS
VHV
0
1
1
0
0
0
SWP
VSS
CSWP
VSS
VCC
VHV
0
1
1
0
0
1
PSWP
A2
A1
A0
0
1
1
0
A2
A1
Read SWP
VSS
VSS
VHV
0
1
1
0
0
0
Read CSWP
VSS
VCC
VHV
0
1
1
0
0
1
Read PSWP
A2
A1
A0
0
1
1
0
A2
A1
1. A0 is used to detect VHV for the SWP and CSWP commands.
2. B3, B2 and B1 are compared to the A2, A1 and A0 external pins, respectively on the 34XX02.
TABLE 7-2:
B1
B0
1
1
A0
1
1
A0
0
0
0
1
1
1
ACKNOWLEDGE TABLE FOR WRITE OR WRITE PROTECTION WITH R/W = 0
WriteProtect
Status
Permanently Protected
x
Instruction
ACK
Address
ACK
Data Byte
PSWP, SWP, CSWP
No
Ack
Don’t Care
No
Ack
Don’t Care No Ack
PAGE or BYTE
WRITE in lower 128
bytes
Ack
Address
Ack
SWP
0
Protected with SWP
CSWP
PSWP
PAGE or BYTE
WRITE in lower 128
bytes
SWP
1
0
Not Protected
1
TABLE 7-3:
R/W
CSWP
PSWP
PAGE or BYTE
WRITE
PSWP, SWP, or CSWP
PAGE or BYTE
WRITE
PSWP, SWP, or CSWP
PAGE or BYTE
WRITE
No
Ack
Ack
Ack
Ack
Don’t Care
Don’t Care
No
Ack
Ack
Ack
Address
Ack
Don’t Care
Data
ACK
Write
Cycle
No
No Ack
No
Don’t Care No Ack
No
Don’t Care
Don’t Care
Ack
Ack
Yes
Yes
Data
No Ack
No
Don’t Care No Ack
No
Don’t Care No Ack
Don’t Care No Ack
No
No
No
Ack
Ack
Ack
Don’t Care
Don’t Care
No
Ack
Ack
Ack
Ack
Address
Ack
Data
No Ack
No
Ack
Don’t Care
Ack
Don’t Care
Ack
Yes
Ack
Address
Ack
Data
Ack
Yes
Ack
Don’t Care
Ack
Ack
Address
Ack
Don’t Care
Don’t Care No Ack
Address
No Ack
No
No
ACKNOWLEDGE TABLE FOR WRITE OR WRITE PROTECTION WITH R/W = 1
Status
Permanently Protected
Protected with SWP
Not protected
2011 Microchip Technology Inc.
Instruction
ACK
PSWP, SWP, CSWP
SWP
CSWP
PSWP
PSWP, SWP, CSWP
No Ack
No Ack
Ack
Ack
Ack
DS22029F-page 13
34AA02/34LC02
8.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 8-1.
TABLE 8-1:
PIN FUNCTION TABLE
Symbol
PDIP
SOIC
TSSOP
MSOP
TDFN
SOT-23
A0
1
1
1
1
1
5
Chip Address Input
A1
2
2
2
2
2
4
Chip Address Input
8.1
A2
3
3
3
3
3
NC
VSS
4
4
4
4
4
2
Chip Address Input
Ground
SDA
5
5
5
5
5
3
Serial Address/Data I/O
SCL
6
6
6
6
6
1
Serial Clock
WP
7
7
7
7
7
NC
VCC
8
8
8
8
8
6
A0, A1, A2
The levels on these inputs are compared with the
corresponding bits in the slave address. The chip is
selected if the compare is true.
Up to eight 34XX02 devices (four for the SOT-23
package) may be connected to the same bus by using
different Chip Select bit combinations. These inputs
must be connected to either VSS or VCC.
The A0 pin is also used to detect VHV.
8.2
Description
8.3
Write-Protect Input
+1.7V to 5.5V Power Supply
Serial Clock (SCL)
This input is used to synchronize the data transfer to
and from the device.
8.4
Write-Protect (WP)
This is the hardware write-protect pin. It can be tied to
VCC or VSS. If tied to VCC, the hardware write protection
is enabled. If the WP pin is tied to VSS, the hardware
write protection is disabled.
Serial Address/Data Input/Output
(SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open
drain terminal. Therefore, the SDA bus requires a pullup resistor to VCC (typical 10 k for 100 kHz, 2 k for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
DS22029F-page 14
2011 Microchip Technology Inc.
34AA02/34LC02
9.0
PACKAGING INFORMATION
9.1
Package Marking Information
8-Lead PDIP (300 mil)
Example:
XXXXXXXX
TXXXXNNN
YYWW
34AA02
I/P e3 3EC
0810
8-Lead SOIC (3.90 mm)
Example:
XXXXXXXT
XXXXYYWW
NNN
34LC02I
SN e3 0810
3EC
Example:
8-Lead TSSOP
XXXX
34A2
TYWW
I810
NNN
3EC
Example:
8-Lead MSOP
XXXXXT
34AA2I
YWWNNN
8103EC
8-Lead 2x3 TDFN
Example:
AJ2
810
3E
XXX
YWW
NN
1st Line Marking Codes
Part Number
TSSOP
MSOP
I-Temp
E-Temp
34AA02
34A2
34AA2T
AJ2
AJ3
34LC02
34L2
34LC2T
AJ5
AJ6
2011 Microchip Technology Inc.
TDFN
DS22029F-page 15
34AA02/34LC02
6-Lead SOT-23
XXNN
Example:
SKEC
SOT-23 Marking Codes
Device
I-Temp
E-Temp
34AA02
SKNN
SLNN
34LC02
STNN
SUNN
Pb-free topside mark is same; Pb-free
noted only on carton label.
Legend: XX...X
T
Y
YY
WW
NNN
e3
Note:
Note:
Part number or part number code
Temperature (I, E)
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code (2 characters for small packages)
Pb-free JEDEC designator for Matte Tin (Sn)
For very small packages with no room for the Pb-free JEDEC designator
e3 , the marking will only appear on the outer carton or reel label.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
Note:
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
DS22029F-page 16
2011 Microchip Technology Inc.
34AA02/34LC02
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2011 Microchip Technology Inc.
DS22029F-page 17
34AA02/34LC02
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22029F-page 18
2011 Microchip Technology Inc.
34AA02/34LC02
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS22029F-page 19
34AA02/34LC02
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DS22029F-page 20
2011 Microchip Technology Inc.
34AA02/34LC02
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2011 Microchip Technology Inc.
DS22029F-page 21
34AA02/34LC02
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22029F-page 22
2011 Microchip Technology Inc.
34AA02/34LC02
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2011 Microchip Technology Inc.
DS22029F-page 23
34AA02/34LC02
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22029F-page 24
2011 Microchip Technology Inc.
34AA02/34LC02
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS22029F-page 25
34AA02/34LC02
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS22029F-page 26
2011 Microchip Technology Inc.
34AA02/34LC02
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DS22029F-page 27
34AA02/34LC02
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PIN 1 ID BY
LASER MARK
1
2
3
e
e1
D
A
A2
c
φ
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A1
L1
6&!
'!
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DS22029F-page 28
2011 Microchip Technology Inc.
34AA02/34LC02
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2011 Microchip Technology Inc.
DS22029F-page 29
34AA02/34LC02
APPENDIX A:
REVISION HISTORY
Revision A (1/2007)
Original release of this document.
Revision B (2/2007)
Replaced Package Drawings.
Revision C (2/2008)
Added TDFN and SOT-23 Package info; Removed
“VL” Part.
Revision D (4/2008)
Updated Product Identification System table,
example (e).
Revision E (01/2010)
Revised SOT-23 and TDFN marking codes.
Revision F (03/2011)
Revised Section 3.6; Updated spec to new template.
DS22029F-page 30
2011 Microchip Technology Inc.
34AA02/34LC02
THE MICROCHIP WEB SITE
CUSTOMER SUPPORT
Microchip provides online support via our WWW site at
www.microchip.com. This web site is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the web site contains the following
information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata,
application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives
•
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Development Systems Information Line
Customers
should
contact
their
distributor,
representative or field application engineer (FAE) for
support. Local sales offices are also available to help
customers. A listing of sales offices and locations is
included in the back of this document.
Technical support is available through the web site
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.
2011 Microchip Technology Inc.
DS22029F-page 31
34AA02/34LC02
READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip
product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our
documentation can better serve you, please FAX your comments to the Technical Publications Manager at
(480) 792-4150.
Please list the following information, and use this outline to provide us with your comments about this document.
TO:
Technical Publications Manager
RE:
Reader Response
Total Pages Sent ________
From: Name
Company
Address
City / State / ZIP / Country
Telephone: (_______) _________ - _________
FAX: (______) _________ - _________
Application (optional):
Would you like a reply?
Y
N
Device: 34AA02/34LC02
Literature Number: DS22029F
Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
DS22029F-page 32
2011 Microchip Technology Inc.
34AA02/34LC02
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
Device
Device:
X
/XX
Temperature Package
Range
34AA02:
34AA02T:
34LC02:
34LC02T:
Temperature I
Range:
E
=
=
Package:
=
=
=
=
=
=
OT
P
SN
ST
MS
MNY(1)
= 1.7V, 2 Kbit I2C Serial EEPROM
= 1.7V, 2 Kbit I2C Serial EEPROM
(Tape and Reel)
= 2.2V, 2 Kbit I2C Serial EEPROM
= 2.2V, 2 Kbit I2C Serial EEPROM
(Tape and Reel)
-40°C to +85°C
-40°C to +125°C
Plastic Small Outline (SOT-23), 6-lead
Plastic DIP (300 mil body), 8-lead
Plastic SOIC (3.90 mm body), 8-lead
Plastic TSSOP (4.4 mm), 8-lead
Plastic Micro Small Outline (MSOP), 8-lead
Plastic Dual Flat, no lead package
(2x3 mm body), 8-lead
Examples:
a)
34AA02-I/P: Industrial
1.7V, PDIP package
Temperature,
b)
34AA02-I/SN: Industrial Temperature,
1.7V, SOIC package
c)
34AA02T-E/MS:
Tape
and
Reel,
Automotive Temperature, 1.7V, MSOP
package
d)
34LC02-I/P: Industrial
2.2V, PDIP package
e)
34LC02-I/MNY: Industrial Temperature,
2.2V, DFN package
f)
34LC02T-E/MS:
Tape
and
Reel,
Automotive Temperature, 2.2V, MSOP
package
Temperature,
Note 1: “Y” indicates a Nickel Palladium Gold (NiPdAu) finish.
2011 Microchip Technology Inc.
DS22029F-page 33
34AA02/34LC02
NOTES:
DS22029F-page 34
2011 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2011, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-947-1
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
2011 Microchip Technology Inc.
DS22029F-page 35
Worldwide Sales and Service
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://www.microchip.com/
support
Web Address:
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02/18/11
DS22029F-page 36
2011 Microchip Technology Inc.