RM0377 Reference manual Ultra-low-power STM32L0x1 advanced ARM®-based 32-bit MCUs Introduction This reference manual targets application developers. It provides complete information on how to use the STM32L0x1 microcontroller memory and peripherals. The STM32L0x1 is a line of microcontrollers with different memory sizes, packages and peripherals. For ordering information, mechanical and electrical device characteristics please refer to the corresponding datasheets. For information on the ARM® Cortex®-M0+ core, please refer to the Cortex®-M0+ Technical Reference Manual. Related documents Cortex®-M0+ Technical Reference Manual, available from www.arm.com. STM32L0 Series Cortex®-M0+ programming manual (PM0223). STM32L0x1 datasheets. February 2016 DocID025942 Rev 5 1/874 www.st.com RM0377 Contents Contents 1 2 Documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.1 List of abbreviations for registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.2 Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 1.3 Peripheral availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 1.4 Product category definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 System and memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.1 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 2.1.1 S0: Cortex®-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.1.2 S1: DMA-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 2.1.3 BusMatrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 AHB/APB bridges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 2.2 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 2.2.2 Memory map and register boundary addresses . . . . . . . . . . . . . . . . . . 50 2.3 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 2.4 Boot configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 BOOT0/GPIO pin sharing (category 1 devices only) . . . . . . . . . . . . . . . . . . . . . .54 Empty check (category 1 devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Bank swapping (category 5 devices only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Physical remap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 Embedded bootloader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 3 Flash program memory and data EEPROM (FLASH) . . . . . . . . . . . . . . 56 3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.2 NVM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 3.3 NVM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3.1 NVM organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 3.3.2 Dual-bank boot capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 3.3.3 Reading the NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Protocol to read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Relation between CPU frequency/Operation mode/NVM read time. . . . . . . . . . .64 Data buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 3.3.4 Writing/erasing the NVM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 DocID025942 Rev 5 2/874 33 Contents RM0377 Write/erase protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 Unlocking/locking operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 Detailed description of NVM write/erase operations. . . . . . . . . . . . . . . . . . . . . . .76 Parallel write half-page Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . .82 Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 3.4 Memory protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 3.4.1 RDP (Read Out Protection) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 3.4.2 PcROP (Proprietary Code Read-Out Protection) . . . . . . . . . . . . . . . . . 89 3.4.3 Protections against unwanted write/erase operations . . . . . . . . . . . . . . 91 3.4.4 Write/erase protection management . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 3.4.5 Protection errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Write protection error flag (WRPERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 Read error (RDERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 3.5 NVM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 3.5.1 3.6 Hard fault . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Memory interface management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 3.6.1 Operation priority and evolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Write/erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Option byte loading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 3.6.2 Sequence of operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Read as data while write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Fetch while write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 Write while another write operation is ongoing . . . . . . . . . . . . . . . . . . . . . . . . . . .96 3.7 3.6.3 Change the number of wait states while reading . . . . . . . . . . . . . . . . . . 96 3.6.4 Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Flash register description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Read registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 Write to registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 3/874 3.7.1 Access control register (FLASH_ACR) . . . . . . . . . . . . . . . . . . . . . . . . . 99 3.7.2 Program and erase control register (FLASH_PECR) . . . . . . . . . . . . . 100 3.7.3 Power-down key register (FLASH_PDKEYR) . . . . . . . . . . . . . . . . . . . 104 3.7.4 PECR unlock key register (FLASH_PEKEYR) . . . . . . . . . . . . . . . . . . 104 3.7.5 Program and erase key register (FLASH_PRGKEYR) . . . . . . . . . . . . 104 3.7.6 Option bytes unlock key register (FLASH_OPTKEYR) . . . . . . . . . . . . 105 3.7.7 Status register (FLASH_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 3.7.8 Option bytes register (FLASH_OPTR) . . . . . . . . . . . . . . . . . . . . . . . . . 108 3.7.9 Write protection register 1 (FLASH_WRPROT1) . . . . . . . . . . . . . . . . . 110 DocID025942 Rev 5 RM0377 Contents 3.8 4 3.7.10 Write protection register 2 (FLASH_WRPROT2) . . . . . . . . . . . . . . . . . 111 3.7.11 Flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Option bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 3.8.1 Option bytes description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 3.8.2 Mismatch when loading protection flags . . . . . . . . . . . . . . . . . . . . . . . 114 3.8.3 Reloading Option bytes by software . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Cyclic redundancy check calculation unit (CRC) . . . . . . . . . . . . . . . . 115 4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.2 CRC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 4.3 CRC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Polynomial programmability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 4.4 5 CRC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 4.4.1 Data register (CRC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 4.4.2 Independent data register (CRC_IDR) . . . . . . . . . . . . . . . . . . . . . . . . 118 4.4.3 Control register (CRC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 4.4.4 Initial CRC value (CRC_INIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.4.5 CRC polynomial (CRC_POL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 4.4.6 CRC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Firewall (FW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.2 Firewall main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 5.3 Firewall functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.3.1 Firewall AMBA bus snoop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 5.3.2 Functional requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Debug consideration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 Write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Interruptions management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 5.3.3 Firewall segments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Code segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Non-volatile data segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Volatile data segment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 5.3.4 Segment accesses and properties . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Segment access depending on the Firewall state . . . . . . . . . . . . . . . . . . . . . . .124 Segments properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 5.3.5 Firewall initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 DocID025942 Rev 5 4/874 33 Contents RM0377 5.3.6 Firewall states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Opening the Firewall. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 Closing the Firewall . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127 5.4 6 Firewall registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.4.1 Code segment start address (FW_CSSA) . . . . . . . . . . . . . . . . . . . . . . 128 5.4.2 Code segment length (FW_CSL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 5.4.3 Non-volatile data segment start address (FW_NVDSSA) . . . . . . . . . . 129 5.4.4 Non-volatile data segment length (FW_NVDSL) . . . . . . . . . . . . . . . . . 129 5.4.5 Volatile data segment start address (FW_VDSSA) . . . . . . . . . . . . . . . 130 5.4.6 Volatile data segment length (FW_VDSL) . . . . . . . . . . . . . . . . . . . . . . 130 5.4.7 Configuration register (FW_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 5.4.8 Firewall register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Power control (PWR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.1 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 6.1.1 Independent A/D converter supply and reference voltage . . . . . . . . . . 134 On packages with more than 64 pins and UFBGA64 . . . . . . . . . . . . . . . . . . . . .134 On packages with 64 pins or less (except BGA package) . . . . . . . . . . . . . . . . .134 6.1.2 RTC and RTC backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 RTC registers access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 6.1.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 6.1.4 Dynamic voltage scaling management . . . . . . . . . . . . . . . . . . . . . . . . 135 Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 Range 2 and 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136 6.2 6.3 6.1.5 Dynamic voltage scaling configuration . . . . . . . . . . . . . . . . . . . . . . . . 137 6.1.6 Voltage regulator and clock management when VDD drops below 1.71 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 6.1.7 Voltage regulator and clock management when modifying the VCORE range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.1.8 Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V 138 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 6.2.1 Power-on reset (POR)/power-down reset (PDR) . . . . . . . . . . . . . . . . . 141 6.2.2 Brown out reset (BOR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 6.2.3 Programmable voltage detector (PVD) . . . . . . . . . . . . . . . . . . . . . . . . 142 6.2.4 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . 143 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 6.3.1 Behavior of clocks in low-power modes . . . . . . . . . . . . . . . . . . . . . . . . 145 Sleep and Low-power sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 5/874 DocID025942 Rev 5 RM0377 Contents Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145 6.3.2 Slowing down system clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.3.3 Peripheral clock gating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 6.3.4 Low-power run mode (LP run) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Entering Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 Exiting Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147 6.3.5 Entering low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.6 Exiting low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 6.3.7 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 I/O states in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 Entering Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 Exiting Sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 6.3.8 Low-power sleep mode (LP sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 I/O states in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 Entering Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 Exiting Low-power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 6.3.9 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 I/O states in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Entering Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .151 Exiting Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 6.3.10 Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154 I/O states in Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Entering Standby mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Exiting Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .154 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 6.3.11 Waking up the device from Stop and Standby modes using the RTC and comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 RTC auto-wakeup (AWU) from the Stop mode . . . . . . . . . . . . . . . . . . . . . . . . .156 RTC auto-wakeup (AWU) from the Standby mode. . . . . . . . . . . . . . . . . . . . . . .156 Comparator auto-wakeup (AWU) from the Stop mode. . . . . . . . . . . . . . . . . . . .157 6.4 7 Power control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 6.4.1 PWR power control register (PWR_CR) . . . . . . . . . . . . . . . . . . . . . . . 158 6.4.2 PWR power control/status register (PWR_CSR) . . . . . . . . . . . . . . . . . 161 6.4.3 PWR register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Reset and clock control (RCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 7.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 7.1.1 System reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 Low-power management reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 DocID025942 Rev 5 6/874 33 Contents RM0377 Option byte loader reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164 7.2 7.1.2 Power reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 7.1.3 RTC and backup registers reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 7.2.1 HSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 External source (HSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .170 External crystal/ceramic resonator (HSE crystal) . . . . . . . . . . . . . . . . . . . . . . . .170 7.2.2 HSI16 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 7.2.3 MSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 7.2.4 PLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 7.2.5 LSE clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 External source (LSE bypass) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 7.2.6 LSI clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 LSI measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 7.3 7/874 7.2.7 System clock (SYSCLK) selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.2.8 System clock source frequency versus voltage range . . . . . . . . . . . . . 174 7.2.9 HSE clock security system (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 7.2.10 LSE Clock Security System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.2.11 RTC clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 7.2.12 Watchdog clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.2.13 Clock-out capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 7.2.14 Internal/external clock measurement using TIM21 . . . . . . . . . . . . . . . 176 7.2.15 Clock-independent system clock sources for TIM2/TIM21/TIM22 . . . . 177 RCC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.3.1 Clock control register (RCC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 7.3.2 Internal clock sources calibration register (RCC_ICSCR) . . . . . . . . . . 181 7.3.3 Clock configuration register (RCC_CFGR) . . . . . . . . . . . . . . . . . . . . . 182 7.3.4 Clock interrupt enable register (RCC_CIER) . . . . . . . . . . . . . . . . . . . . 184 7.3.5 Clock interrupt flag register (RCC_CIFR) . . . . . . . . . . . . . . . . . . . . . . 186 7.3.6 Clock interrupt clear register (RCC_CICR) . . . . . . . . . . . . . . . . . . . . . 187 7.3.7 GPIO reset register (RCC_IOPRSTR) . . . . . . . . . . . . . . . . . . . . . . . . . 188 7.3.8 AHB peripheral reset register (RCC_AHBRSTR) . . . . . . . . . . . . . . . . 189 7.3.9 APB2 peripheral reset register (RCC_APB2RSTR) . . . . . . . . . . . . . . 190 7.3.10 APB1 peripheral reset register (RCC_APB1RSTR) . . . . . . . . . . . . . . 191 7.3.11 GPIO clock enable register (RCC_IOPENR) . . . . . . . . . . . . . . . . . . . . 193 7.3.12 AHB peripheral clock enable register (RCC_AHBENR) . . . . . . . . . . . 195 DocID025942 Rev 5 RM0377 8 Contents 7.3.13 APB2 peripheral clock enable register (RCC_APB2ENR) . . . . . . . . . . 196 7.3.14 APB1 peripheral clock enable register (RCC_APB1ENR) . . . . . . . . . . 198 7.3.15 GPIO clock enable in Sleep mode register (RCC_IOPSMENR) . . . . . 200 7.3.16 AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 7.3.17 APB2 peripheral clock enable in Sleep mode register (RCC_APB2SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 7.3.18 APB1 peripheral clock enable in Sleep mode register (RCC_APB1SMENR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 7.3.19 Clock configuration register (RCC_CCIPR) . . . . . . . . . . . . . . . . . . . . . 205 7.3.20 Control/status register (RCC_CSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 7.3.21 RCC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 General-purpose I/Os (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.2 GPIO main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.3 GPIO functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 8.4 8.3.1 General-purpose I/O (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 8.3.2 I/O pin alternate function multiplexer and mapping . . . . . . . . . . . . . . . 216 8.3.3 I/O port control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 8.3.4 I/O port data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 8.3.5 I/O data bitwise handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 8.3.6 GPIO locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 8.3.7 I/O alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 8.3.8 External interrupt/wakeup lines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 8.3.9 Input configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 8.3.10 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 8.3.11 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 8.3.12 Analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 8.3.13 Using the HSE or LSE oscillator pins as GPIOs . . . . . . . . . . . . . . . . . 221 8.3.14 Using the GPIO pins in the RTC supply domain . . . . . . . . . . . . . . . . . 221 8.3.15 BOOT0/GPIO pin sharing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 GPIO registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A..E and H) . . . . . . . 223 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..E and H) . . 223 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 DocID025942 Rev 5 8/874 33 Contents 9 10 RM0377 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 8.4.5 GPIO port input data register (GPIOx_IDR) (x = A..E and H) . . . . . . . 225 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..E and H) . . . . . 225 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..E and H) . . . . 225 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 226 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..E and H) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 8.4.11 GPIO port bit reset register (GPIOx_BRR) (x =A..E and H) . . . . . . . . 228 8.4.12 GPIO register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 System configuration controller (SYSCFG) . . . . . . . . . . . . . . . . . . . . 231 9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 9.2 SYSCFG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 9.2.1 SYSCFG memory remap register (SYSCFG_CFGR1) . . . . . . . . . . . . 232 9.2.2 SYSCFG peripheral mode configuration register (SYSCFG_CFGR2) 233 9.2.3 Reference control and status register (SYSCFG_CFGR3) . . . . . . . . . 234 9.2.4 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 9.2.5 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 9.2.6 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 9.2.7 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 9.2.8 SYSCFG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . 239 10.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 10.2 DMA main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 10.3 DMA functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 10.3.1 DMA transactions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 10.3.2 Arbiter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 10.3.3 DMA channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 Programmable data sizes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 Pointer incrementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 9/874 DocID025942 Rev 5 RM0377 Contents Channel configuration procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 Circular mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 Memory-to-memory mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .242 10.3.4 Programmable data width, data alignment and endians . . . . . . . . . . . 243 Addressing an AHB peripheral that does not support byte or halfword write operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244 10.3.5 Error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 10.3.6 DMA interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 10.3.7 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 DMA controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 10.4 11 12 DMA registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 10.4.1 DMA interrupt status register (DMA_ISR) . . . . . . . . . . . . . . . . . . . . . . 247 10.4.2 DMA interrupt flag clear register (DMA_IFCR) . . . . . . . . . . . . . . . . . . 248 10.4.3 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . 249 10.4.4 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 10.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 10.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 10.4.7 DMA channel selection register (DMA_CSELR) . . . . . . . . . . . . . . . . . 253 10.4.8 DMA register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . 257 11.1 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 11.2 SysTick calibration value register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 11.3 Interrupt and exception vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 Extended interrupt and event controller (EXTI) . . . . . . . . . . . . . . . . . 260 12.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 12.2 EXTI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 12.3 EXTI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 12.3.1 EXTI block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 12.3.2 Wakeup event management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 12.3.3 Peripherals asynchronous interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . 262 12.3.4 Hardware interrupt selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 12.3.5 Hardware event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 DocID025942 Rev 5 10/874 33 Contents RM0377 12.3.6 13 Software interrupt/event selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 12.4 EXTI interrupt/event line mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 12.5 EXTI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 12.5.1 EXTI interrupt mask register (EXTI_IMR) . . . . . . . . . . . . . . . . . . . . . . 265 12.5.2 EXTI event mask register (EXTI_EMR) . . . . . . . . . . . . . . . . . . . . . . . . 265 12.5.3 EXTI rising edge trigger selection register (EXTI_RTSR) . . . . . . . . . . 266 12.5.4 Falling edge trigger selection register (EXTI_FTSR) . . . . . . . . . . . . . . 266 12.5.5 EXTI software interrupt event register (EXTI_SWIER) . . . . . . . . . . . . 267 12.5.6 EXTI pending register (EXTI_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 12.5.7 EXTI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 13.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 13.2 ADC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 13.3 ADC pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 13.4 ADC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 13.4.1 ADC voltage regulator (ADVREGEN) . . . . . . . . . . . . . . . . . . . . . . . . . 273 Analog reference for the ADC internal voltage regulator . . . . . . . . . . . . . . . . . .274 ADVREG enable sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 ADVREG disable sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .274 13.4.2 Calibration (ADCAL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 Calibration factor forcing Software Procedure . . . . . . . . . . . . . . . . . . . . . . . . . .276 13.4.3 ADC on-off control (ADEN, ADDIS, ADRDY) . . . . . . . . . . . . . . . . . . . 276 13.4.4 ADC clock (CKMODE, PRESC[3:0], LFMEN) . . . . . . . . . . . . . . . . . . . 277 Low frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 13.4.5 Configuring the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 13.4.6 Channel selection (CHSEL, SCANDIR) . . . . . . . . . . . . . . . . . . . . . . . . 279 Temperature sensor, VREFINT internal channels . . . . . . . . . . . . . . . . . . . . . . . .279 13.4.7 Programmable sampling time (SMP) . . . . . . . . . . . . . . . . . . . . . . . . . . 279 13.4.8 Single conversion mode (CONT=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 13.4.9 Continuous conversion mode (CONT=1) . . . . . . . . . . . . . . . . . . . . . . . 280 13.4.10 Starting conversions (ADSTART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 13.4.11 Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 13.4.12 Stopping an ongoing conversion (ADSTP) . . . . . . . . . . . . . . . . . . . . . 283 13.5 11/874 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) . 283 13.5.1 Discontinuous mode (DISCEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 13.5.2 Programmable resolution (RES) - fast conversion mode . . . . . . . . . . 285 DocID025942 Rev 5 RM0377 Contents 13.6 13.5.3 End of conversion, end of sampling phase (EOC, EOSMP flags) . . . . 285 13.5.4 End of conversion sequence (EOSEQ flag) . . . . . . . . . . . . . . . . . . . . 286 13.5.5 Example timing diagrams (single/continuous modes . . . . . . . . . . . . . . . . . hardware/software triggers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Data management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 13.6.1 Data register and data alignment (ADC_DR, ALIGN) . . . . . . . . . . . . . 288 13.6.2 ADC overrun (OVR, OVRMOD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 13.6.3 Managing a sequence of data converted without using the DMA . . . . 289 13.6.4 Managing converted data without using the DMA without overrun . . . 289 13.6.5 Managing converted data using the DMA . . . . . . . . . . . . . . . . . . . . . . 289 DMA one shot mode (DMACFG=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 DMA circular mode (DMACFG=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 13.7 Low-power features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 13.7.1 Wait mode conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 13.7.2 Auto-off mode (AUTOFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 13.8 Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR, AWD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 13.9 Oversampler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 13.9.1 ADC operating modes support when oversampling . . . . . . . . . . . . . . 296 13.9.2 Analog watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 13.9.3 Triggered mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296 13.10 Temperature sensor and internal reference voltage . . . . . . . . . . . . . . . . 297 Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 Reading the temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .298 Calculating the actual VDDA voltage using the internal reference voltage . . . . .299 Converting a supply-relative ADC measurement to an absolute voltage value .299 13.11 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 13.12 ADC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 13.12.1 ADC interrupt and status register (ADC_ISR) . . . . . . . . . . . . . . . . . . . 301 13.12.2 ADC interrupt enable register (ADC_IER) . . . . . . . . . . . . . . . . . . . . . . 302 13.12.3 ADC control register (ADC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 13.12.4 ADC configuration register 1 (ADC_CFGR1) . . . . . . . . . . . . . . . . . . . 306 13.12.5 ADC configuration register 2 (ADC_CFGR2) . . . . . . . . . . . . . . . . . . . 310 13.12.6 ADC sampling time register (ADC_SMPR) . . . . . . . . . . . . . . . . . . . . . 311 13.12.7 ADC watchdog threshold register (ADC_TR) . . . . . . . . . . . . . . . . . . . 312 13.12.8 ADC channel selection register (ADC_CHSELR) . . . . . . . . . . . . . . . . 313 13.12.9 ADC data register (ADC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 DocID025942 Rev 5 12/874 33 Contents RM0377 13.12.10 ADC Calibration factor (ADC_CALFACT) . . . . . . . . . . . . . . . . . . . . . . 314 13.12.11 ADC common configuration register (ADC_CCR) . . . . . . . . . . . . . . . . 315 13.12.12 ADC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 14 15 Comparator (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 14.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 14.2 COMP main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 319 14.3 COMP functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 14.3.1 COMP block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 14.3.2 COMP pins and internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 14.3.3 COMP reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 14.3.4 Comparator LOCK mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 14.3.5 Power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 14.4 COMP interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321 14.5 COMP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 14.5.1 Comparator 1 control and status register (COMP1_CSR) . . . . . . . . . . 322 14.5.2 Comparator 2 control and status register (COMP2_CSR) . . . . . . . . . . 323 14.5.3 COMP register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Advanced encryption standard hardware accelerator (AES) . . . . . . 326 15.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.2 AES main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 15.3 AES functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 15.4 Encryption and derivation keys . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 15.5 AES chaining algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 15.5.1 Electronic CodeBook (ECB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 15.5.2 Cipher block chaining (CBC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 Suspended mode for a given message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 15.5.3 Counter Mode (CTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 Suspend mode in CTR mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 13/874 15.6 Data type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 15.7 Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 15.7.1 Mode 1: encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 15.7.2 Mode 2: key derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 15.7.3 Mode 3: decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 15.7.4 Mode 4: key derivation and decryption . . . . . . . . . . . . . . . . . . . . . . . . 340 DocID025942 Rev 5 RM0377 Contents 15.8 AES DMA interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 15.9 Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 15.10 Processing time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 15.11 AES interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 15.12 AES registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.12.1 AES control register (AES_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 15.12.2 AES status register (AES_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 15.12.3 AES data input register (AES_DINR) . . . . . . . . . . . . . . . . . . . . . . . . . 347 15.12.4 AES data output register (AES_DOUTR) . . . . . . . . . . . . . . . . . . . . . . 347 15.12.5 AES key register 0(AES_KEYR0) (LSB: key [31:0]) . . . . . . . . . . . . . . 348 15.12.6 AES key register 1 (AES_KEYR1) (Key[63:32]) . . . . . . . . . . . . . . . . . 348 15.12.7 AES key register 2 (AES_KEYR2) (Key [95:64]) . . . . . . . . . . . . . . . . . 349 15.12.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96]) . . . . . . . . . . . . 349 15.12.9 AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0]) . . . . 349 15.12.10 AES initialization vector register 1 (AES_IVR1) (IVR[63:32]) . . . . . . . 350 15.12.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) . . . . . . . 351 15.12.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96]) . 351 15.12.13 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 16 General-purpose timers (TIM2/TIM3) . . . . . . . . . . . . . . . . . . . . . . . . . . 353 16.1 TIM2/TIM3 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 16.2 TIM2/TIM3 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 16.3 TIM2/TIM3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 16.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .355 16.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Upcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .357 Downcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .360 Center-aligned mode (up/down counting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 16.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 Internal clock source (CK_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .367 External clock source mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .368 External clock source mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .370 16.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 16.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 16.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 16.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 DocID025942 Rev 5 14/874 33 Contents RM0377 16.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 16.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 PWM edge-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .378 Downcounting configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 PWM center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .379 16.3.10 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Particular case: OCx fast enable: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .382 16.3.11 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 382 16.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 16.3.13 Timer input XOR function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 16.3.14 Timers and external trigger synchronization . . . . . . . . . . . . . . . . . . . . 386 Slave mode: Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .386 Slave mode: Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .387 Slave mode: Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .388 Slave mode: External Clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . .389 16.3.15 Timer synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Using one timer as prescaler for another timer . . . . . . . . . . . . . . . . . . . . . . . . .390 Using one timer to enable another timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .391 Using one timer to start another timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .393 Starting 2 timers synchronously in response to an external trigger . . . . . . . . . .395 16.3.16 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 16.4 TIM2/TIM3 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 16.4.1 TIMx control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 397 16.4.2 TIMx control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 399 16.4.3 TIMx slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . . . . . 400 16.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 402 16.4.5 TIMx status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 16.4.6 TIMx event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . . . 405 16.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . . . . . 406 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .406 Input capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .408 16.4.8 TIMx capture/compare mode register 2 (TIMx_CCMR2) . . . . . . . . . . . 409 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .409 Input capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .410 16.4.9 TIMx capture/compare enable register (TIMx_CCER) . . . . . . . . . . . . . 410 16.4.10 TIMx counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 16.4.11 TIMx prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 16.4.12 TIMx auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . . . 412 16.4.13 TIMx capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . . . . 413 15/874 DocID025942 Rev 5 RM0377 Contents 16.4.14 TIMx capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . . . . 413 16.4.15 TIMx capture/compare register 3 (TIMx_CCR3) . . . . . . . . . . . . . . . . . 414 16.4.16 TIMx capture/compare register 4 (TIMx_CCR4) . . . . . . . . . . . . . . . . . 414 16.4.17 TIMx DMA control register (TIMx_DCR) . . . . . . . . . . . . . . . . . . . . . . . 415 16.4.18 TIMx DMA address for full transfer (TIMx_DMAR) . . . . . . . . . . . . . . . 415 Example of how to use the DMA burst feature . . . . . . . . . . . . . . . . . . . . . . . . . .416 16.4.19 TIM2 option register (TIM2_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 16.4.20 TIM3 option register (TIM3_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 16.5 17 TIMx register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 General-purpose timers (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 17.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 17.2 TIM21/22 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 17.2.1 17.3 TIM21/22 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 TIM21/22 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 17.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 Prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .423 17.3.2 Counter modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425 Upcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .425 Downcounting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .429 Center-aligned mode (up/down counting) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .432 17.3.3 Clock selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 Internal clock source (CK_INT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .436 External clock source mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .438 17.3.4 Capture/compare channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 17.3.5 Input capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 17.3.6 PWM input mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 17.3.7 Forced output mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 17.3.8 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 17.3.9 PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 PWM center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .447 Hints on using center-aligned mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .448 17.3.10 Clearing the OCxREF signal on an external event . . . . . . . . . . . . . . . 448 17.3.11 One-pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Particular case: OCx fast enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .451 17.3.12 Encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 451 17.3.13 TIM21/22 external trigger synchronization . . . . . . . . . . . . . . . . . . . . . . 453 Slave mode: Reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .453 DocID025942 Rev 5 16/874 33 Contents RM0377 Slave mode: Gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .454 Slave mode: Trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .455 17.3.14 Timer synchronization (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 17.3.15 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 17.4 TIM21/22 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 17.4.1 TIM21/22 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . 457 17.4.2 TIM21/22 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . 459 17.4.3 TIM21/22 slave mode control register (TIMx_SMCR) . . . . . . . . . . . . . 460 17.4.4 TIM21/22 Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . . . 463 17.4.5 TIM21/22 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . 463 17.4.6 TIM21/22 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . 465 17.4.7 TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) . . . . . . . 466 Output compare mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .466 Input capture mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .468 17.4.8 TIM21/22 capture/compare enable register (TIMx_CCER) . . . . . . . . . 469 17.4.9 TIM21/22 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 17.4.10 TIM21/22 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 17.4.11 TIM21/22 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . 470 17.4.12 TIM21/22 capture/compare register 1 (TIMx_CCR1) . . . . . . . . . . . . . . 471 17.4.13 TIM21/22 capture/compare register 2 (TIMx_CCR2) . . . . . . . . . . . . . . 471 17.4.14 TIM21 option register (TIM21_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 17.4.15 TIM22 option register (TIM22_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 17.4.16 TIM21/22 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 18 Basic timers (TIM6/7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.2 TIM6/7 main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 18.3 TIM6/7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 18.3.1 Time-base unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 Prescaler description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .477 18.4 17/874 18.3.2 Counting mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 18.3.3 Clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 18.3.4 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483 TIM6/7 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 18.4.1 TIM6/7 control register 1 (TIMx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . 484 18.4.2 TIM6/7 control register 2 (TIMx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . 485 18.4.3 TIM6/7 DMA/Interrupt enable register (TIMx_DIER) . . . . . . . . . . . . . . 485 DocID025942 Rev 5 RM0377 19 Contents 18.4.4 TIM6/7 status register (TIMx_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 18.4.5 TIM6/7 event generation register (TIMx_EGR) . . . . . . . . . . . . . . . . . . 486 18.4.6 TIM6/7 counter (TIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 18.4.7 TIM6/7 prescaler (TIMx_PSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 18.4.8 TIM6/7 auto-reload register (TIMx_ARR) . . . . . . . . . . . . . . . . . . . . . . 487 18.4.9 TIM6/7 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 19.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 19.2 LPTIM main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 19.3 LPTIM implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 19.4 LPTIM functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 19.4.1 LPTIM block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 19.4.2 LPTIM reset and clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 19.4.3 Glitch filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 19.4.4 Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 19.4.5 Trigger multiplexer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 19.4.6 Operating mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 19.4.7 Timeout function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494 19.4.8 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495 19.4.9 Register update . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 19.4.10 Counter mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 19.4.11 Timer enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 19.4.12 Encoder mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 20 19.5 LPTIM interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 19.6 LPTIM registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 19.6.1 LPTIM interrupt and status register (LPTIMx_ISR) . . . . . . . . . . . . . . . 500 19.6.2 LPTIM interrupt clear register (LPTIMx_ICR) . . . . . . . . . . . . . . . . . . . 501 19.6.3 LPTIM interrupt enable register (LPTIMx_IER) . . . . . . . . . . . . . . . . . . 502 19.6.4 LPTIM configuration register (LPTIMx_CFGR) . . . . . . . . . . . . . . . . . . 503 19.6.5 LPTIM control register (LPTIMx_CR) . . . . . . . . . . . . . . . . . . . . . . . . . 506 19.6.6 LPTIM compare register (LPTIMx_CMP) . . . . . . . . . . . . . . . . . . . . . . . 507 19.6.7 LPTIM autoreload register (LPTIMx_ARR) . . . . . . . . . . . . . . . . . . . . . 507 19.6.8 LPTIM counter register (LPTIMx_CNT) . . . . . . . . . . . . . . . . . . . . . . . . 508 19.6.9 LPTIM register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 DocID025942 Rev 5 18/874 33 Contents RM0377 20.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 20.2 IWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 20.3 IWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 20.3.1 IWDG block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 20.3.2 Window option . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 Configuring the IWDG when the window option is enabled . . . . . . . . . . . . . . . .511 Configuring the IWDG when the window option is disabled . . . . . . . . . . . . . . . .511 20.4 21 20.3.4 Behavior in Stop and Standby modes . . . . . . . . . . . . . . . . . . . . . . . . . 512 20.3.5 Register access protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 20.3.6 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 IWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 20.4.1 Key register (IWDG_KR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513 20.4.2 Prescaler register (IWDG_PR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 20.4.3 Reload register (IWDG_RLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 20.4.4 Status register (IWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 20.4.5 Window register (IWDG_WINR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 20.4.6 IWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 21.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 21.2 WWDG main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 21.3 WWDG functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 21.3.1 Enabling the watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 21.3.2 Controlling the downcounter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 21.3.3 Advanced watchdog interrupt feature . . . . . . . . . . . . . . . . . . . . . . . . . 520 21.3.4 How to program the watchdog timeout . . . . . . . . . . . . . . . . . . . . . . . . 521 21.3.5 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 WWDG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 21.4.1 Control register (WWDG_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 21.4.2 Configuration register (WWDG_CFR) . . . . . . . . . . . . . . . . . . . . . . . . . 524 21.4.3 Status register (WWDG_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 21.4.4 WWDG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 Real-time clock (RTC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 22.1 19/874 Hardware watchdog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 System window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . 519 21.4 22 20.3.3 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 DocID025942 Rev 5 RM0377 Contents 22.2 RTC main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 22.3 RTC functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 22.3.1 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 22.3.2 GPIOs controlled by the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 22.3.3 Clock and prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 22.3.4 Real-time clock and calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 22.3.5 Programmable alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 22.3.6 Periodic auto-wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 22.3.7 RTC initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 RTC register access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533 RTC register write protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533 Calendar initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .533 Daylight saving time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534 Programming the alarm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534 Programming the wakeup timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .534 22.3.8 Reading the calendar . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 When BYPSHAD control bit is cleared in the RTC_CR register. . . . . . . . . . . . .534 When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .535 22.3.9 Resetting the RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535 22.3.10 RTC synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 22.3.11 RTC reference clock detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536 22.3.12 RTC smooth digital calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 Calibration when PREDIV_A<3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538 Verifying the RTC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .538 Re-calibration on-the-fly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .539 22.3.13 Time-stamp function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 539 22.3.14 Tamper detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 RTC backup registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .540 Tamper detection initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .540 Trigger output generation on tamper event . . . . . . . . . . . . . . . . . . . . . . . . . . . .541 Timestamp on tamper event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .541 Edge detection on tamper inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .541 Level detection with filtering on RTC_TAMPx inputs . . . . . . . . . . . . . . . . . . . . .541 22.3.15 Calibration clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 22.3.16 Alarm output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 Alarm alternate function output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .542 22.4 RTC low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 22.5 RTC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 DocID025942 Rev 5 20/874 33 Contents RM0377 22.6 RTC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 22.6.1 RTC time register (RTC_TR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 22.6.2 RTC date register (RTC_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 22.6.3 RTC control register (RTC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 22.6.4 RTC initialization and status register (RTC_ISR) . . . . . . . . . . . . . . . . . 549 22.6.5 RTC prescaler register (RTC_PRER) . . . . . . . . . . . . . . . . . . . . . . . . . 552 22.6.6 RTC wakeup timer register (RTC_WUTR) . . . . . . . . . . . . . . . . . . . . . . 553 22.6.7 RTC alarm A register (RTC_ALRMAR) . . . . . . . . . . . . . . . . . . . . . . . . 554 22.6.8 RTC alarm B register (RTC_ALRMBR) . . . . . . . . . . . . . . . . . . . . . . . . 555 22.6.9 RTC write protection register (RTC_WPR) . . . . . . . . . . . . . . . . . . . . . 556 22.6.10 RTC sub second register (RTC_SSR) . . . . . . . . . . . . . . . . . . . . . . . . . 556 22.6.11 RTC shift control register (RTC_SHIFTR) . . . . . . . . . . . . . . . . . . . . . . 557 22.6.12 RTC timestamp time register (RTC_TSTR) . . . . . . . . . . . . . . . . . . . . . 558 22.6.13 RTC timestamp date register (RTC_TSDR) . . . . . . . . . . . . . . . . . . . . 559 22.6.14 RTC time-stamp sub second register (RTC_TSSSR) . . . . . . . . . . . . . 560 22.6.15 RTC calibration register (RTC_CALR) . . . . . . . . . . . . . . . . . . . . . . . . . 561 22.6.16 RTC tamper configuration register (RTC_TAMPCR) . . . . . . . . . . . . . . 562 22.6.17 RTC alarm A sub second register (RTC_ALRMASSR) . . . . . . . . . . . . 565 22.6.18 RTC alarm B sub second register (RTC_ALRMBSSR) . . . . . . . . . . . . 566 22.6.19 RTC option register (RTC_OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567 22.6.20 RTC backup registers (RTC_BKPxR) . . . . . . . . . . . . . . . . . . . . . . . . . 568 22.6.21 RTC register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 23 Inter-integrated circuit (I2C) interface . . . . . . . . . . . . . . . . . . . . . . . . . 571 23.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 23.2 I2C main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571 23.3 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 23.4 I2C functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 23.4.1 I2C1/3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 23.4.2 I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 23.4.3 I2C clock requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 23.4.4 Mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Communication flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .575 23.4.5 I2C initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 Enabling and disabling the peripheral . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .576 Noise filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .576 I2C timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .577 21/874 DocID025942 Rev 5 RM0377 Contents 23.4.6 Software reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 23.4.7 Data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .581 Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582 Hardware transfer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .582 23.4.8 I2C slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 I2C slave initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .583 Slave clock stretching (NOSTRETCH = 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .584 Slave without clock stretching (NOSTRETCH = 1). . . . . . . . . . . . . . . . . . . . . . .584 Slave Byte Control mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .585 Slave transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .586 Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .590 23.4.9 I2C master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592 I2C master initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .592 Master communication initialization (address phase) . . . . . . . . . . . . . . . . . . . . .594 Initialization of a master receiver addressing a 10-bit address slave . . . . . . . . .595 Master transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .596 Master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .600 23.4.10 I2C_TIMINGR register configuration examples . . . . . . . . . . . . . . . . . . 604 23.4.11 SMBus specific features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 605 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605 SMBUS is based on I2C specification rev 2.1. . . . . . . . . . . . . . . . . . . . . . . . . . .605 Bus protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605 Address resolution protocol (ARP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .605 Received Command and Data acknowledge control . . . . . . . . . . . . . . . . . . . . .606 Host Notify protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606 SMBus alert . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .606 Timeouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .607 Bus idle detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608 23.4.12 SMBus initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608 Received Command and Data Acknowledge control (Slave mode) . . . . . . . . . .608 Specific address (Slave mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608 Packet error checking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .608 Timeout detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609 Bus Idle detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .609 23.4.13 SMBus: I2C_TIMEOUTR register configuration examples . . . . . . . . . 610 23.4.14 SMBus slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611 SMBus Slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .611 SMBus Slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .612 SMBus Master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .614 DocID025942 Rev 5 22/874 33 Contents RM0377 SMBus Master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .616 23.4.15 Wakeup from Stop mode on address match . . . . . . . . . . . . . . . . . . . . 618 23.4.16 Error conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618 Bus error (BERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .618 Arbitration lost (ARLO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .619 Overrun/underrun error (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .619 Packet Error Checking Error (PECERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .619 Timeout Error (TIMEOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .619 Alert (ALERT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .620 23.4.17 DMA requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .620 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .621 23.4.18 Debug mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 23.5 I2C low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 23.6 I2C interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 23.7 I2C registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 23.7.1 Control register 1 (I2C_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623 23.7.2 Control register 2 (I2C_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626 23.7.3 Own address 1 register (I2C_OAR1) . . . . . . . . . . . . . . . . . . . . . . . . . . 629 23.7.4 Own address 2 register (I2C_OAR2) . . . . . . . . . . . . . . . . . . . . . . . . . . 630 23.7.5 Timing register (I2C_TIMINGR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631 23.7.6 Timeout register (I2C_TIMEOUTR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 632 23.7.7 Interrupt and status register (I2C_ISR) . . . . . . . . . . . . . . . . . . . . . . . . 633 23.7.8 Interrupt clear register (I2C_ICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635 23.7.9 PEC register (I2C_PECR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636 23.7.10 Receive data register (I2C_RXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 23.7.11 Transmit data register (I2C_TXDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 637 23.7.12 I2C register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 24 Universal synchronous asynchronous receiver transmitter (USART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 24.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 24.2 USART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640 24.3 USART extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641 24.4 USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 24.5 USART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 24.5.1 23/874 USART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645 DocID025942 Rev 5 RM0377 Contents 24.5.2 USART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647 Character transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .647 Single byte communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .648 Break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .649 Idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .649 24.5.3 USART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .650 Character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .651 Break character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .651 Idle character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .651 Overrun error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .652 Selecting the proper oversampling method . . . . . . . . . . . . . . . . . . . . . . . . . . . .652 Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .654 Configurable stop bits during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .655 24.5.4 USART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655 How to derive USARTDIV from USARTx_BRR register values . . . . . . . . . . . . .656 24.5.5 Tolerance of the USART receiver to clock deviation . . . . . . . . . . . . . . 657 24.5.6 USART auto baud rate detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659 24.5.7 Multiprocessor communication using USART . . . . . . . . . . . . . . . . . . . 660 Idle line detection (WAKE=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .661 4-bit/7-bit address mark detection (WAKE=1) . . . . . . . . . . . . . . . . . . . . . . . . . .661 24.5.8 Modbus communication using USART . . . . . . . . . . . . . . . . . . . . . . . . 662 Modbus/RTU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .662 Modbus/ASCII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .662 24.5.9 USART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 Even parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663 Odd parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663 Parity checking in reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663 Parity generation in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .663 24.5.10 USART LIN (local interconnection network) mode . . . . . . . . . . . . . . . 664 LIN transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .664 LIN reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .664 24.5.11 USART synchronous mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666 24.5.12 USART Single-wire Half-duplex communication . . . . . . . . . . . . . . . . . 669 24.5.13 USART Smartcard mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669 Block mode (T=1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .672 Direct and inverse convention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .673 24.5.14 USART IrDA SIR ENDEC block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674 IrDA low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .675 24.5.15 USART continuous communication in DMA mode . . . . . . . . . . . . . . . 676 DocID025942 Rev 5 24/874 33 Contents RM0377 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .676 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .677 Error flagging and interrupt generation in multibuffer communication . . . . . . . .678 24.5.16 RS232 hardware flow control and RS485 driver enable using USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .679 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .679 RS485 Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .680 24.5.17 Wakeup from Stop mode using USART . . . . . . . . . . . . . . . . . . . . . . . . 680 Using Mute mode with Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .681 Determining the maximum USART baudrate allowing to wakeup correctly from Stop mode when the USART clock source is the HSI clock . . . . . . . . . . . . . . . . . . . .681 24.6 USART low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 24.7 USART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 24.8 USART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 24.8.1 Control register 1 (USARTx_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684 24.8.2 Control register 2 (USARTx_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687 24.8.3 Control register 3 (USARTx_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691 24.8.4 Baud rate register (USARTx_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 695 24.8.5 Guard time and prescaler register (USARTx_GTPR) . . . . . . . . . . . . . 695 24.8.6 Receiver timeout register (USARTx_RTOR) . . . . . . . . . . . . . . . . . . . . 696 24.8.7 Request register (USARTx_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 697 24.8.8 Interrupt and status register (USARTx_ISR) . . . . . . . . . . . . . . . . . . . . 698 24.8.9 Interrupt flag clear register (USARTx_ICR) . . . . . . . . . . . . . . . . . . . . . 703 24.8.10 Receive data register (USARTx_RDR) . . . . . . . . . . . . . . . . . . . . . . . . 704 24.8.11 Transmit data register (USARTx_TDR) . . . . . . . . . . . . . . . . . . . . . . . . 705 24.8.12 USART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 25 Low-power universal asynchronous receiver transmitter (LPUART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 25.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708 25.2 LPUART main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 25.3 LPUART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709 25.4 LPUART functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710 25.4.1 LPUART character description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712 25.4.2 LPUART transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 Character transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .714 Single byte communication. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .715 25/874 DocID025942 Rev 5 RM0377 Contents Break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .716 Idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .716 25.4.3 LPUART receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 Start bit detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .716 Character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .717 Break character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .717 Idle character . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .717 Overrun error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .718 Selecting the clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .718 Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .719 Configurable stop bits during reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .719 25.4.4 LPUART baud rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719 25.4.5 Tolerance of the LPUART receiver to clock deviation . . . . . . . . . . . . . 720 25.4.6 Multiprocessor communication using LPUART . . . . . . . . . . . . . . . . . . 721 Idle line detection (WAKE=0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .722 4-bit/7-bit address mark detection (WAKE=1) . . . . . . . . . . . . . . . . . . . . . . . . . .722 25.4.7 LPUART parity control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 Even parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .723 Odd parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .723 Parity checking in reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .724 Parity generation in transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .724 25.4.8 Single-wire Half-duplex communication using LPUART . . . . . . . . . . . 724 25.4.9 Continuous communication in DMA mode using LPUART . . . . . . . . . 724 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .725 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .726 Error flagging and interrupt generation in multibuffer communication . . . . . . . .727 25.4.10 RS232 Hardware flow control and RS485 Driver Enable using LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .728 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .728 RS485 Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .729 25.4.11 Wakeup from Stop mode using LPUART . . . . . . . . . . . . . . . . . . . . . . . 730 Using Mute mode with Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .730 Determining the maximum LPUART baudrate allowing to wakeup correctly from Stop mode when the LPUART clock source is the HSI clock. . . . . . . . . . . . . . .730 25.5 LPUART low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 25.6 LPUART interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 25.7 LPUART registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 25.7.1 Control register 1 (LPUART_CR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733 25.7.2 Control register 2 (LPUART_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736 DocID025942 Rev 5 26/874 33 Contents RM0377 25.7.3 Control register 3 (LPUART_CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738 25.7.4 Baud rate register (LPUART_BRR) . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 25.7.5 Request register (LPUART_RQR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740 25.7.6 Interrupt & status register (LPUART_ISR) . . . . . . . . . . . . . . . . . . . . . . 741 25.7.7 Interrupt flag clear register (LPUART_ICR) . . . . . . . . . . . . . . . . . . . . . 744 25.7.8 Receive data register (LPUART_RDR) . . . . . . . . . . . . . . . . . . . . . . . . 745 25.7.9 Transmit data register (LPUART_TDR) . . . . . . . . . . . . . . . . . . . . . . . . 745 25.7.10 LPUART register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 26 Serial peripheral interface/ inter-IC sound (SPI/I2S) . . . . . . . . . . . . . 748 26.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 26.1.1 SPI main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 26.1.2 SPI extended features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 26.1.3 I2S features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 26.2 SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 26.3 SPI functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 26.3.1 26.3.2 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Communications between one master and one slave . . . . . . . . . . . . . 751 Full-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .751 Half-duplex communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .751 Simplex communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .752 26.3.3 Standard multi-slave communication . . . . . . . . . . . . . . . . . . . . . . . . . . 754 26.3.4 Multi-master communication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 26.3.5 Slave select (NSS) pin management . . . . . . . . . . . . . . . . . . . . . . . . . . 755 26.3.6 Communication formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757 Clock phase and polarity controls. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .757 Data frame format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .758 26.3.7 SPI configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 26.3.8 Procedure for enabling SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 26.3.9 Data transmission and reception procedures . . . . . . . . . . . . . . . . . . . 760 Rx and Tx buffers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .760 Tx buffer handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .760 Rx buffer handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .760 Sequence handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .760 26.3.10 Procedure for disabling the SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 26.3.11 Communication using DMA (direct memory addressing) . . . . . . . . . . 763 26.3.12 SPI status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 Tx buffer empty flag (TXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .765 27/874 DocID025942 Rev 5 RM0377 Contents Rx buffer not empty (RXNE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .765 Busy flag (BSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .765 26.3.13 SPI error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 766 Overrun flag (OVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .766 Mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .766 CRC error (CRCERR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .767 TI mode frame format error (FRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .767 26.4 SPI special features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 26.4.1 TI mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767 TI protocol in master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .767 26.4.2 CRC calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 CRC principle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .768 CRC transfer managed by CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .768 CRC transfer managed by DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .769 Resetting the SPIx_TXCRC and SPIx_RXCRC values . . . . . . . . . . . . . . . . . . .769 26.5 SPI interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 26.6 I2S functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 26.6.1 I2S general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 26.6.2 Supported audio protocols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772 I2S Philips standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .773 MSB justified standard . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .775 LSB justified standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .776 PCM standard. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .778 26.6.3 Clock generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 26.6.4 I2S master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781 Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .781 Transmission sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .781 Reception sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .782 26.6.5 I2S slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783 Transmission sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .783 Reception sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .784 26.6.6 I2S status flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784 Busy flag (BSY) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .784 Tx buffer empty flag (TXE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785 RX buffer not empty (RXNE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785 Channel Side flag (CHSIDE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785 26.6.7 I2S error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785 Underrun flag (UDR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .785 Overrun flag (OVR). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .786 Frame error flag (FRE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .786 DocID025942 Rev 5 28/874 33 Contents RM0377 26.7 26.6.8 I2S interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 26.6.9 DMA features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 SPI and I2S registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787 26.7.1 SPI control register 1 (SPI_CR1) (not used in I2S mode) . . . . . . . . . . 787 26.7.2 SPI control register 2 (SPI_CR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789 26.7.3 SPI status register (SPI_SR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790 26.7.4 SPI data register (SPI_DR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 26.7.5 SPI CRC polynomial register (SPI_CRCPR) (not used in I2S mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792 26.7.6 SPI RX CRC register (SPI_RXCRCR) (not used in I2S mode) . . . . . . 793 26.7.7 SPI TX CRC register (SPI_TXCRCR) (not used in I2S mode) . . . . . . 793 26.7.8 SPI_I2S configuration register (SPI_I2SCFGR) . . . . . . . . . . . . . . . . . . 794 26.7.9 SPI_I2S prescaler register (SPI_I2SPR) . . . . . . . . . . . . . . . . . . . . . . . 795 26.7.10 SPI register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 27 Debug support (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 27.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797 27.2 Reference ARM® documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 27.3 Pinout and debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 27.4 27.3.1 SWD port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 27.3.2 SW-DP pin assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 27.3.3 Internal pull-up & pull-down on SWD pins . . . . . . . . . . . . . . . . . . . . . . 799 ID codes and locking mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 27.4.1 MCU device ID code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799 DBG_IDCODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .799 27.5 SWD port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 27.5.1 SWD protocol introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 27.5.2 SWD protocol sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 27.5.3 SW-DP state machine (reset, idle states, ID code) . . . . . . . . . . . . . . . 801 27.5.4 DP and AP read/write accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 27.5.5 SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 27.5.6 SW-AP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803 27.6 Core debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 27.7 BPU (Break Point Unit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 27.7.1 27.8 29/874 BPU functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 DWT (Data Watchpoint) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 DocID025942 Rev 5 RM0377 Contents 27.9 27.8.1 DWT functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 27.8.2 DWT Program Counter Sample Register . . . . . . . . . . . . . . . . . . . . . . 805 MCU debug component (DBG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805 27.9.1 Debug support for low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . 805 27.9.2 Debug support for timers, watchdog and I2C . . . . . . . . . . . . . . . . . . . . 806 27.9.3 Debug MCU configuration register (DBG_CR) . . . . . . . . . . . . . . . . . . 806 27.9.4 Debug MCU APB1 freeze register (DBG_APB1_FZ) . . . . . . . . . . . . . 808 27.9.5 Debug MCU APB2 freeze register (DBG_APB2_FZ) . . . . . . . . . . . . . 810 27.10 DBG register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .811 28 Device electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 28.1 Memory size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 28.1.1 28.2 Flash size register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 Unique device ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812 Appendix A Code examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 A.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 A.2 NVM/RCC Operation code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814 A.3 A.4 A.2.1 Increasing the CPU frequency preparation sequence code . . . . . . . . . 814 A.2.2 Decreasing the CPU frequency preparation sequence code . . . . . . . . 814 A.2.3 Switch from PLL to HSI16 sequence code . . . . . . . . . . . . . . . . . . . . . . 815 A.2.4 Switch to PLL sequence code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815 NVM Operation code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 A.3.1 Unlocking the data EEPROM and FLASH_PECR register code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816 A.3.2 Locking data EEPROM and FLASH_PECR register code example . . . 816 A.3.3 Unlocking the NVM program memory code example . . . . . . . . . . . . . . 816 A.3.4 Unlocking the option bytes area code example . . . . . . . . . . . . . . . . . . 817 A.3.5 Write to data EEPROM code example . . . . . . . . . . . . . . . . . . . . . . . . . 817 A.3.6 Erase to data EEPROM code example . . . . . . . . . . . . . . . . . . . . . . . . 817 A.3.7 Program Option byte code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 A.3.8 Erase Option byte code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818 A.3.9 Program a single word to Flash program memory code example . . . . 819 A.3.10 Program half-page to Flash program memory code example. . . . . . . . 820 A.3.11 Erase a page in Flash program memory code example . . . . . . . . . . . . 821 A.3.12 Mass erase code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822 Clock Controller. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 DocID025942 Rev 5 30/874 33 Contents RM0377 A.5 A.6 A.4.1 HSE start sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 823 A.4.2 PLL configuration modification code example . . . . . . . . . . . . . . . . . . . 824 A.4.3 MCO selection code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 A.5.1 Locking mechanism code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . 825 A.5.2 Alternate function selection sequence code example. . . . . . . . . . . . . . 825 A.5.3 Analog GPIO configuration code example . . . . . . . . . . . . . . . . . . . . . . 825 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 A.6.1 A.7 A.8 A.9 31/874 DMA Channel Configuration sequence code example . . . . . . . . . . . . . 826 Interrupts and event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 A.7.1 NVIC initialization example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826 A.7.2 Extended interrupt selection code example . . . . . . . . . . . . . . . . . . . . . 826 ADC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 A.8.1 Calibration code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827 A.8.2 ADC enable sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . 827 A.8.3 ADC disable sequence code example . . . . . . . . . . . . . . . . . . . . . . . . . 828 A.8.4 ADC clock selection code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 828 A.8.5 Single conversion sequence code example - Software trigger . . . . . . . 828 A.8.6 Continuous conversion sequence code example - Software trigger. . . 829 A.8.7 Single conversion sequence code example - Hardware trigger . . . . . . 829 A.8.8 Continuous conversion sequence code example - Hardware trigger . . 830 A.8.9 DMA one shot mode sequence code example . . . . . . . . . . . . . . . . . . . 830 A.8.10 DMA circular mode sequence code example . . . . . . . . . . . . . . . . . . . . 831 A.8.11 Wait mode sequence code example. . . . . . . . . . . . . . . . . . . . . . . . . . . 831 A.8.12 Auto off and no wait mode sequence code example . . . . . . . . . . . . . . 831 A.8.13 Auto off and wait mode sequence code example . . . . . . . . . . . . . . . . . 832 A.8.14 Analog watchdog code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832 A.8.15 Oversampling code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833 A.8.16 Temperature configuration code example. . . . . . . . . . . . . . . . . . . . . . . 833 A.8.17 Temperature computation code example . . . . . . . . . . . . . . . . . . . . . . . 833 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834 A.9.1 Upcounter on TI2 rising edge code example . . . . . . . . . . . . . . . . . . . . 834 A.9.2 Up counter on each 2 ETR rising edges code example . . . . . . . . . . . . 834 A.9.3 Input capture configuration code example . . . . . . . . . . . . . . . . . . . . . . 835 A.9.4 Input capture data management code example . . . . . . . . . . . . . . . . . . 835 A.9.5 PWM input configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 836 DocID025942 Rev 5 RM0377 Contents A.10 A.9.6 PWM input with DMA configuration code example . . . . . . . . . . . . . . . . 836 A.9.7 Output compare configuration code example . . . . . . . . . . . . . . . . . . . . 837 A.9.8 Edge-aligned PWM configuration example. . . . . . . . . . . . . . . . . . . . . . 837 A.9.9 Center-aligned PWM configuration example . . . . . . . . . . . . . . . . . . . . 838 A.9.10 ETR configuration to clear OCxREF code example . . . . . . . . . . . . . . . 838 A.9.11 Encoder interface code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 A.9.12 Reset mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 839 A.9.13 Gated mode code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 A.9.14 Trigger mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840 A.9.15 External clock mode 2 + trigger mode code example. . . . . . . . . . . . . . 841 A.9.16 One-Pulse mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841 A.9.17 Timer prescaling another timer code example . . . . . . . . . . . . . . . . . . . 842 A.9.18 Timer enabling another timer code example. . . . . . . . . . . . . . . . . . . . . 842 A.9.19 Master and slave synchronization code example . . . . . . . . . . . . . . . . . 843 A.9.20 Two timers synchronized by an external trigger code example . . . . . . 845 A.9.21 DMA burst feature code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846 Low-power timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 A.10.1 A.11 A.12 IWDG code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 A.11.1 IWDG configuration code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847 A.11.2 IWDG configuration with window code example. . . . . . . . . . . . . . . . . . 847 WWDG code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 A.12.1 A.13 A.14 Pulse counter configuration code example . . . . . . . . . . . . . . . . . . . . . . 847 WWDG configuration code example. . . . . . . . . . . . . . . . . . . . . . . . . . . 848 RTC code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 848 A.13.1 RTC calendar configuration code example. . . . . . . . . . . . . . . . . . . . . . 848 A.13.2 RTC alarm configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 849 A.13.3 RTC WUT configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 849 A.13.4 RTC read calendar code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849 A.13.5 RTC calibration code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850 A.13.6 RTC tamper and time stamp configuration code example . . . . . . . . . . 850 A.13.7 RTC tamper and time stamp code example . . . . . . . . . . . . . . . . . . . . . 851 A.13.8 RTC clock output code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 I2C code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851 A.14.1 I2C configured in slave mode code example . . . . . . . . . . . . . . . . . . . . 851 A.14.2 I2C slave transmitter code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 A.14.3 I2C slave receiver code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852 DocID025942 Rev 5 32/874 33 Contents RM0377 A.15 A.14.4 I2C configured in master mode to receive code example. . . . . . . . . . . 852 A.14.5 I2C configured in master mode to transmit code example . . . . . . . . . . 853 A.14.6 I2C master transmitter code example . . . . . . . . . . . . . . . . . . . . . . . . . . 853 A.14.7 I2C master receiver code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853 A.14.8 I2C configured in master mode to transmit with DMA code example . . 853 A.14.9 I2C configured in slave mode to receive with DMA code example . . . . 854 USART code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854 A.15.1 USART transmitter configuration code example. . . . . . . . . . . . . . . . . . 854 A.15.2 USART transmit byte code example. . . . . . . . . . . . . . . . . . . . . . . . . . . 854 A.15.3 USART transfer complete code example . . . . . . . . . . . . . . . . . . . . . . . 854 A.15.4 USART receiver configuration code example . . . . . . . . . . . . . . . . . . . . 854 A.15.5 USART receive byte code example . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 A.15.6 USART LIN mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855 A.15.7 USART synchronous mode code example . . . . . . . . . . . . . . . . . . . . . . 855 A.15.8 USART single-wire half-duplex code example . . . . . . . . . . . . . . . . . . . 856 A.15.9 USART smartcard mode code example . . . . . . . . . . . . . . . . . . . . . . . . 856 A.15.10 USART IrDA mode code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856 A.15.11 USART DMA code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857 A.15.12 USART hardware flow control code example . . . . . . . . . . . . . . . . . . . . 857 A.16 A.17 A.18 29 33/874 LPUART code example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 A.16.1 LPUART receiver configuration code example . . . . . . . . . . . . . . . . . . . 858 A.16.2 LPUART receive byte code example . . . . . . . . . . . . . . . . . . . . . . . . . . 858 SPI code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858 A.17.1 SPI master configuration code example . . . . . . . . . . . . . . . . . . . . . . . . 858 A.17.2 SPI slave configuration code example . . . . . . . . . . . . . . . . . . . . . . . . . 858 A.17.3 SPI full duplex communication code example . . . . . . . . . . . . . . . . . . . 858 A.17.4 SPI master configuration with DMA code example. . . . . . . . . . . . . . . . 859 A.17.5 SPI slave configuration with DMA code example . . . . . . . . . . . . . . . . . 859 A.17.6 SPI interrupt code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 DBG code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 A.18.1 DBG read device Id code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 A.18.2 DBG debug in LPM code example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 DocID025942 Rev 5 RM0377 List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. STM32L0x1 memory density . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Features per category. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 STM32L0x1 peripheral register boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Boot modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 NVM organization (category 1 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 NVM organization (category 2 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 NVM organization (category 3 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 NVM organization for UFB = 0 (192 Kbyte category 5 devices) . . . . . . . . . . . . . . . . . . . . . 59 Flash memory and data EEPROM remapping (192 Kbyte category 5 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 NVM organization for UFB = 0 (128 Kbyte category 5 devices) . . . . . . . . . . . . . . . . . . . . . 60 Flash memory and data EEPROM remapping (128 Kbyte category 5 devices) . . . . . . . . . 61 NVM organization for UFB = 0 (64 Kbyte category 5 devices) . . . . . . . . . . . . . . . . . . . . . . 61 Boot pin and BFB2 bit configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Link between master clock power range and frequencies . . . . . . . . . . . . . . . . . . . . . . . . . 64 Delays to memory access and number of wait states. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Internal buffer management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Configurations for buffers and speculative reading . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Dhrystone performances in all memory interface configurations . . . . . . . . . . . . . . . . . . . . 71 NVM write/erase timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 NVM write/erase duration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Protection level and content of RDP Option bytes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Link between protection bits of FLASH_WRPROTx register and protected address in Flash program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Memory access vs mode, protection and Flash program memory sectors. . . . . . . . . . . . . 91 Flash interrupt request . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Flash interface - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 Option byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Option byte organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 CRC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 Segment accesses according to the Firewall state. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 Segment granularity and area ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Firewall register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 Performance versus VCORE ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 Summary of low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 Sleep-now . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Sleep-on-exit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Sleep-now (Low-power sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 Sleep-on-exit (Low-power sleep) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153 Standby mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 PWR - register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 System clock source frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 RCC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 Port bit configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 GPIO register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 SYSCFG register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 Programmable data width & endian behavior (when bits PINC = MINC = 1) . . . . . . . . . . 243 DocID025942 Rev 5 34/874 36 List of tables Table 47. Table 48. Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. Table 67. Table 68. Table 69. Table 70. Table 71. Table 72. Table 73. Table 74. Table 75. Table 76. Table 77. Table 78. Table 79. Table 80. Table 81. Table 82. Table 83. Table 84. Table 85. Table 86. Table 87. Table 88. Table 89. Table 90. Table 91. Table 92. Table 93. Table 94. Table 95. Table 96. Table 97. Table 98. 35/874 RM0377 DMA interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 Summary of the DMA requests for each channel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 DMA register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 List of vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 EXTI lines connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Extended interrupt/event controller register map and reset values. . . . . . . . . . . . . . . . . . 269 ADC internal signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 ADC pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 Latency between trigger and start of conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Configuring the trigger polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 External triggers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 tSAR timings depending on resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Analog watchdog comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Analog watchdog channel selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Maximum output results vs N and M. Grayed values indicates truncation . . . . . . . . . . . . 295 ADC interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 ADC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317 COMP register map and reset values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Processing time (in clock cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 AES interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 AES register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 TIM2/TIM3 internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 TIM2/3 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 Counting direction versus encoder signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 TIMx Internal trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 Output control bit for standard OCx channels. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 TIM21/22 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 TIM6/7 register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 488 STM32L0x1 LPTIM features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489 Prescaler division ratios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492 Encoder counting scenarios . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 LPTIM external trigger connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 LPTIM register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 IWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 WWDG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525 RTC pin PC13 configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 RTC_OUT mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 Effect of low-power modes on RTC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 Interrupt control bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 RTC register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568 STM32L0x1 I2C features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572 Comparison of analog vs. digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 I2C-SMBUS specification data setup and hold times . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 I2C configuration table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 I2C-SMBUS specification clock timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 Examples of timings settings for fI2CCLK = 8 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 Examples of timings settings for fI2CCLK = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . 604 SMBus timeout specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 SMBUS with PEC configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609 Examples of TIMEOUTA settings for various I2CCLK frequencies DocID025942 Rev 5 RM0377 List of tables (max tTIMEOUT = 25 ms) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 Table 99. Examples of TIMEOUTB settings for various I2CCLK frequencies . . . . . . . . . . . . . . . . . 610 Table 100. Examples of TIMEOUTA settings for various I2CCLK frequencies (max tIDLE = 50 µs) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610 Table 101. low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 Table 102. I2C Interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621 Table 103. I2C register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638 Table 104. STM32L0x1 USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642 Table 105. Noise detection from sampled data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 Table 106. Error calculation for programmed baud rates at fCK = 32 MHz in both cases of oversampling by 16 or by 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657 Table 107. Tolerance of the USART receiver when BRR [3:0] = 0000. . . . . . . . . . . . . . . . . . . . . . . . 658 Table 108. Tolerance of the USART receiver when BRR [3:0] is different from 0000 . . . . . . . . . . . . 658 Table 109. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663 Table 110. Effect of low-power modes on the USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 Table 111. USART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682 Table 112. USART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706 Table 113. Error calculation for programmed baudrates at fck = 32,768 KHz . . . . . . . . . . . . . . . . . . 720 Table 114. Tolerance of the LPUART receiver when BRR [3:0] is different from 0000 . . . . . . . . . . . 721 Table 115. Frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 Table 116. Effect of low-power modes on the LPUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 Table 117. LPUART interrupt requests. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731 Table 118. LPUART register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 Table 119. STM32L0x1 SPI implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749 Table 120. SPI interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770 Table 121. Audio-frequency precision using standard 8 MHz HSE . . . . . . . . . . . . . . . . . . . . . . . . . . 780 Table 122. I2S interrupt requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786 Table 123. SPI register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796 Table 124. SW debug port pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798 Table 125. REV-ID values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 Table 126. Packet request (8-bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800 Table 127. ACK response (3 bits). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 Table 128. DATA transfer (33 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801 Table 129. SW-DP registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802 Table 130. 32-bit debug port registers addressed through the shifted value A[3:2] . . . . . . . . . . . . . . 803 Table 131. Core debug registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804 Table 132. DBG register map and reset values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811 Table 133. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860 DocID025942 Rev 5 36/874 36 List of figures RM0377 List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Figure 41. Figure 42. Figure 43. Figure 44. Figure 45. Figure 46. Figure 47. 37/874 System architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Structure of one internal buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Timing to fetch and execute instructions with prefetch disabled. . . . . . . . . . . . . . . . . . . . . 68 Timing to fetch and execute instructions with prefetch enabled . . . . . . . . . . . . . . . . . . . . . 70 RDP levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 CRC calculation unit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 STM32L0x1 firewall connection schematics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Firewall functional states . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Power supply overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 Performance versus VDD and VCORE range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 Power-on reset/power-down reset waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 BOR thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 PVD thresholds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Simplified diagram of the reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 HSE/ LSE clock sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 Using TIM21 channel 1 input capture to measure frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 Basic structure of an I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Basic structure of a five-volt tolerant I/O port bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 Input floating/pull up/pull down configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219 Output configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 Alternate function configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 High impedance-analog configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 DMA block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 DMA request mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 Extended interrupts and events controller (EXTI) block diagram . . . . . . . . . . . . . . . . . . . 261 Extended interrupt/event GPIO mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 ADC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 ADC calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 Calibration factor forcing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 Enabling/disabling the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 ADC clock scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277 Analog to digital conversion time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 ADC conversion timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 Stopping an ongoing conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 Single conversions of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Continuous conversion of a sequence, software trigger . . . . . . . . . . . . . . . . . . . . . . . . . . 286 Single conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 Continuous conversions of a sequence, hardware trigger . . . . . . . . . . . . . . . . . . . . . . . . 287 Data alignment and resolution (oversampling disabled: OVSE = 0). . . . . . . . . . . . . . . . . 288 Example of overrun (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Wait mode conversion (continuous mode, software trigger). . . . . . . . . . . . . . . . . . . . . . . 291 Behavior with WAIT=0, AUTOFF=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Behavior with WAIT=1, AUTOFF=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292 Analog watchdog guarded area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 DocID025942 Rev 5 RM0377 Figure 48. Figure 49. Figure 50. Figure 51. Figure 52. Figure 53. Figure 54. Figure 55. Figure 56. Figure 57. Figure 58. Figure 59. Figure 60. Figure 61. Figure 62. Figure 63. Figure 64. Figure 65. Figure 66. Figure 67. Figure 68. Figure 69. Figure 70. Figure 71. Figure 72. Figure 73. Figure 74. Figure 75. Figure 76. Figure 77. Figure 78. Figure 79. Figure 80. Figure 81. Figure 82. Figure 83. Figure 84. Figure 85. Figure 86. Figure 87. Figure 88. Figure 89. Figure 90. Figure 91. Figure 92. Figure 93. Figure 94. Figure 95. Figure 96. Figure 97. Figure 98. List of figures 20-bit to 16-bit result truncation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Numerical example with 5-bits shift and rounding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 Triggered oversampling mode (TOVS bit = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297 Temperature sensor and VREFINT channel block diagram . . . . . . . . . . . . . . . . . . . . . . 298 Comparator 1 and 2 block diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 ECB encryption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 ECB decryption mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 CBC mode encryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 CBC mode decryption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Example of suspend mode management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 CTR mode encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 CTR mode decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 32-bit counter + nonce organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 128-bit block construction according to the data type. . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 128-bit block construction according to the data type (continued) . . . . . . . . . . . . . . . . . . 338 Mode 1: encryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 Mode 2: key derivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 Mode 3: decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 Mode 4: key derivation and decryption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 DMA requests and data transfers during Input phase (AES_IN) . . . . . . . . . . . . . . . . . . . 341 DMA requests during Output phase (AES_OUT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 General-purpose timer block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 356 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 356 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359 Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded). . . . . 359 Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . 360 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 Counter timing diagram, Update event when repetition counter is not used . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 364 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 365 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 366 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 367 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 368 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 372 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 Output stage of capture/compare channel (channel 1). . . . . . . . . . . . . . . . . . . . . . . . . . . 373 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 DocID025942 Rev 5 38/874 42 List of figures Figure 99. Figure 100. Figure 101. Figure 102. Figure 103. Figure 104. Figure 105. Figure 106. Figure 107. Figure 108. Figure 109. Figure 110. Figure 111. Figure 112. Figure 113. Figure 114. Figure 115. Figure 116. Figure 117. Figure 118. Figure 119. Figure 120. Figure 121. Figure 122. Figure 123. Figure 124. Figure 125. Figure 126. Figure 127. Figure 128. Figure 129. Figure 130. Figure 131. Figure 132. Figure 133. Figure 134. Figure 135. Figure 136. Figure 137. Figure 138. Figure 139. Figure 140. Figure 141. Figure 142. Figure 143. Figure 144. Figure 145. Figure 146. Figure 147. Figure 148. 39/874 RM0377 Output compare mode, toggle on OC1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 Example of one-pulse mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 385 Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 385 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 Control circuit in external clock mode 2 + trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Master/Slave timer example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 Gating timer y with OC1REF of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 Gating timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 393 Triggering timer y with update of timer x. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Triggering timer y with Enable of timer x . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 Triggering timer x and y with timer x TI1 input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 General-purpose timer block diagram (TIM21/22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 424 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 425 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431 Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 . . . . . . . . . . . . . . . 433 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 . . . . . . . . . . . . . . 434 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 434 Counter timing diagram, Update event with ARPE=1 (counter underflow). . . . . . . . . . . . 435 Counter timing diagram, Update event with ARPE=1 (counter overflow) . . . . . . . . . . . . . 435 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 436 TI2 external clock connection example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 Control circuit in external clock mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 External trigger input block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 438 Control circuit in external clock mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439 Capture/compare channel (example: channel 1 input stage) . . . . . . . . . . . . . . . . . . . . . . 440 Capture/compare channel 1 main circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 Output stage of capture/compare channel (channel 1 and 2). . . . . . . . . . . . . . . . . . . . . . 441 PWM input mode timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 Output compare mode, toggle on OC1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 445 Edge-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 Center-aligned PWM waveforms (ARR=8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 Clearing TIMx OCxREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 Example of one pulse mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 DocID025942 Rev 5 RM0377 Figure 149. Figure 150. Figure 151. Figure 152. Figure 153. Figure 154. Figure 155. Figure 156. Figure 157. Figure 158. Figure 159. Figure 160. Figure 161. Figure 162. Figure 163. Figure 164. Figure 165. Figure 166. Figure 167. Figure 168. Figure 169. Figure 170. Figure 171. Figure 172. Figure 173. Figure 174. Figure 175. Figure 176. Figure 177. Figure 178. Figure 179. Figure 180. Figure 181. Figure 182. Figure 183. Figure 184. Figure 185. Figure 186. Figure 187. Figure 188. Figure 189. Figure 190. Figure 191. Figure 192. Figure 193. Figure 194. Figure 195. Figure 196. Figure 197. List of figures Example of counter operation in encoder interface mode . . . . . . . . . . . . . . . . . . . . . . . . 452 Example of encoder interface mode with TI1FP1 polarity inverted . . . . . . . . . . . . . . . . . 453 Control circuit in reset mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 Control circuit in gated mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 Control circuit in trigger mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456 Basic timer block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 Counter timing diagram with prescaler division change from 1 to 2 . . . . . . . . . . . . . . . . . 478 Counter timing diagram with prescaler division change from 1 to 4 . . . . . . . . . . . . . . . . . 478 Counter timing diagram, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479 Counter timing diagram, internal clock divided by 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 Counter timing diagram, internal clock divided by 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 Counter timing diagram, internal clock divided by N. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481 Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482 Control circuit in normal mode, internal clock divided by 1 . . . . . . . . . . . . . . . . . . . . . . . . 483 Low-power timer block diagram- . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 Glitch filter timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491 LPTIM output waveform, Single counting mode configuration . . . . . . . . . . . . . . . . . . . . . 493 LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 493 LPTIM output waveform, Continuous counting mode configuration . . . . . . . . . . . . . . . . . 494 Waveform generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 Encoder mode counting sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 Independent watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 Watchdog block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 Window watchdog timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 RTC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 I2C1/3 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 I2C2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574 I2C bus protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 Setup and hold timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 I2C initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 Data reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 Data transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 Slave initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=0. . . . . . . . . . . . . 587 Transfer sequence flowchart for I2C slave transmitter, NOSTRETCH=1. . . . . . . . . . . . . 588 Transfer bus diagrams for I2C slave transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 Transfer sequence flowchart for slave receiver with NOSTRETCH=0 . . . . . . . . . . . . . . . 590 Transfer sequence flowchart for slave receiver with NOSTRETCH=1 . . . . . . . . . . . . . . . 591 Transfer bus diagrams for I2C slave receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 Master clock generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 Master initialization flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 10-bit address read access with HEAD10R=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 10-bit address read access with HEAD10R=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 Transfer sequence flowchart for I2C master transmitter for N≤255 bytes . . . . . . . . . . . . 597 Transfer sequence flowchart for I2C master transmitter for N>255 bytes . . . . . . . . . . . . 598 Transfer bus diagrams for I2C master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599 Transfer sequence flowchart for I2C master receiver for N≤255 bytes. . . . . . . . . . . . . . . 601 Transfer sequence flowchart for I2C master receiver for N >255 bytes . . . . . . . . . . . . . . 602 DocID025942 Rev 5 40/874 42 List of figures RM0377 Figure 198. Figure 199. Figure 200. Figure 201. Figure 202. Figure 203. Figure 204. Figure 205. Figure 206. Figure 207. Figure 208. Figure 209. Figure 210. Figure 211. Figure 212. Figure 213. Figure 214. Figure 215. Figure 216. Figure 217. Figure 218. Figure 219. Figure 220. Figure 221. Figure 222. Figure 223. Figure 224. Figure 225. Figure 226. Figure 227. Figure 228. Figure 229. Figure 230. Figure 231. Figure 232. Figure 233. Figure 234. Figure 235. Figure 236. Figure 237. Figure 238. Figure 239. Figure 240. Figure 241. Figure 242. Figure 243. Figure 244. Figure 245. Figure 246. Figure 247. Transfer bus diagrams for I2C master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603 Timeout intervals for tLOW:SEXT, tLOW:MEXT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 607 Transfer sequence flowchart for SMBus slave transmitter N bytes + PEC. . . . . . . . . . . . 611 Transfer bus diagrams for SMBus slave transmitter (SBC=1) . . . . . . . . . . . . . . . . . . . . . 612 Transfer sequence flowchart for SMBus slave receiver N Bytes + PEC . . . . . . . . . . . . . 613 Bus transfer diagrams for SMBus slave receiver (SBC=1) . . . . . . . . . . . . . . . . . . . . . . . 614 Bus transfer diagrams for SMBus master transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615 Bus transfer diagrams for SMBus master receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617 I2C interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622 USART block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646 Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648 TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649 Start bit detection when oversampling by 16 or 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650 Data sampling when oversampling by 16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653 Data sampling when oversampling by 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661 Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662 Break detection in LIN mode (11-bit break length - LBDL bit is set) . . . . . . . . . . . . . . . . . 665 Break detection in LIN mode vs. Framing error detection. . . . . . . . . . . . . . . . . . . . . . . . . 666 USART example of synchronous transmission. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 USART data clock timing diagram (M bits = 00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667 USART data clock timing diagram (M bits = 01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 RX data setup/hold time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 ISO 7816-3 asynchronous protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 Parity error detection using the 1.5 stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671 IrDA SIR ENDEC- block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675 IrDA data modulation (3/16) -Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 Hardware flow control between 2 USARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680 USART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683 LPUART Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711 Word length programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713 Configurable stop bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714 TC/TXE behavior when transmitting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716 Mute mode using Idle line detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722 Mute mode using address mark detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 Hardware flow control between 2 LPUARTs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727 RS232 RTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728 RS232 CTS flow control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729 LPUART interrupt mapping diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732 SPI block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 Full-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751 Half-duplex single master/ single slave application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752 Simplex single master/single slave application (master in transmit-only/ slave in receive-only mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753 Figure 248. Master and three independent slaves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754 41/874 DocID025942 Rev 5 RM0377 Figure 249. Figure 250. Figure 251. Figure 252. Figure 253. Figure 254. Figure 255. Figure 256. Figure 257. Figure 258. Figure 259. Figure 260. Figure 261. Figure 262. Figure 263. Figure 264. Figure 265. Figure 266. Figure 267. Figure 268. Figure 269. Figure 270. Figure 271. Figure 272. Figure 273. Figure 274. Figure 275. Figure 276. Figure 277. List of figures Multi-master application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755 Hardware/software slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 756 Data clock timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 TXE/RXNE/BSY behavior in master / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761 TXE/RXNE/BSY behavior in slave / full-duplex mode (BIDIMODE=0, RXONLY=0) in the case of continuous transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762 Transmission using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764 Reception using DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 765 TI mode transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768 I2S block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771 I2S Philips protocol waveforms (16/32-bit full accuracy, CPOL = 0). . . . . . . . . . . . . . . . . 773 I2S Philips standard waveforms (24-bit frame with CPOL = 0) . . . . . . . . . . . . . . . . . . . . . 773 Transmitting 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 Receiving 0x8EAA33 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774 I2S Philips standard (16-bit extended to 32-bit packet frame with CPOL = 0) . . . . . . . . . 774 Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 775 MSB Justified 16-bit or 32-bit full-accuracy length with CPOL = 0 . . . . . . . . . . . . . . . . . . 775 MSB justified 24-bit frame length with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775 MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 776 LSB justified 16-bit or 32-bit full-accuracy with CPOL = 0 . . . . . . . . . . . . . . . . . . . . . . . . 776 LSB justified 24-bit frame length with CPOL = 0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776 Operations required to transmit 0x3478AE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 Operations required to receive 0x3478AE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777 LSB justified 16-bit extended to 32-bit packet frame with CPOL = 0 . . . . . . . . . . . . . . . . 777 Example of 16-bit data frame extended to 32-bit channel frame . . . . . . . . . . . . . . . . . . . 778 PCM standard waveforms (16-bit) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778 PCM standard waveforms (16-bit extended to 32-bit packet frame). . . . . . . . . . . . . . . . . 778 Audio sampling frequency definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 I2S clock generator architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779 Block diagram of STM32L0x1 MCU and Cortex®-M0+-level debug support . . . . . . . . . . 797 DocID025942 Rev 5 42/874 42 Documentation conventions RM0377 1 Documentation conventions 1.1 List of abbreviations for registers The following abbreviations are used in register descriptions: read/write (rw) Software can read and write to these bits. read-only (r) Software can only read these bits. write-only (w) Software can only write to this bit. Reading the bit returns the reset value. read/clear (rc_w1) Software can read as well as clear this bit by writing 1. Writing ‘0’ has no effect on the bit value. read/clear (rc_w0) Software can read as well as clear this bit by writing 0. Writing ‘1’ has no effect on the bit value. read/clear by read (rc_r) Software can read this bit. Reading this bit automatically clears it to ‘0’. Writing ‘0’ has no effect on the bit value. read/set (rs) Software can read as well as set this bit. Writing ‘0’ has no effect on the bit value. Reserved (Res.) Reserved bit, must be kept at reset value. 1.2 Glossary This section gives a brief definition of acronyms and abbreviations used in this document: 43/874 Sector: 32 pages write protection granularity in the Code area Page: 32 words for Code and System Memory areas, 1 word for Data, Factory Option and User Option areas Word: data of 32-bit length. Half-word: data of 16-bit length. Byte: data of 8-bit length. IAP (in-application programming): IAP is the ability to re-program the Flash memory of a microcontroller while the user program is running. ICP (in-circuit programming): ICP is the ability to program the Flash memory of a microcontroller using the JTAG protocol, the SWD protocol or the bootloader while the device is mounted on the user application board. Option bytes: product configuration bits stored in the Flash memory. OBL: option byte loader. AHB: advanced high-performance bus. NVM: non-volatile memory. ECC: error code correction. DMA: direct memory access. MIF: NVM interface. PCROP: proprietary code read-out protection. DocID025942 Rev 5 RM0377 1.3 Documentation conventions Peripheral availability For peripheral availability and number across all sales types, please refer to the particular device datasheet. 1.4 Product category definition Table 1 gives an overview of memory density versus product line. The present reference manual describes the superset of features for each product line, Refer to Table 2 for the list of features per category. Table 1. STM32L0x1 memory density Memory density Category 1(1) Category 2(1) Category 3 Category 5(1) 8 Kbytes STM32L011x STM32L021x (AES) - - - 16 Kbytes STM32L011x STM32L021x (AES) STM32L031x STM32L041x (AES) - - 32 Kbytes - STM32L031x STM32L041x (AES) STM32L051x - 64 Kbytes - - STM32L051x STM32L071x 128 Kbytes - - - STM32L071x STM32L081x (AES) 192 Kbytes - - - STM32L071x STM32L081x (AES) 1. Products under development. Table 2. Features per category Feature Category 1 MPU - NVM full-featured, single bank fullfullfeatured, featured, full-featured single bank single bank Cyclic redundancy check calculation unit (CRC) full-featured full-featured full-featured full-featured Firewall (FW) - Power control (PWR) full-featured full-featured full-featured full-featured Reset and clock control (RCC) HSE supports bypass only, no CSS on HSE full-featured full-featured full-featured GPIOA full-featured full-featured full-featured full-featured DocID025942 Rev 5 Category 2 Category 3 Category 5 - - full-featured full-featured full-featured full-featured 44/874 46 Documentation conventions RM0377 Table 2. Features per category (continued) Feature Category 1 Category 2 Category 3 Category 5 GPIOB [0:9], BOOT0/PB9 sharing the same pin full-featured full-featured full-featured GPIOC [14:15] [0][13:15] GPIOD - - [2] full-featured GPIOE - - - full-featured GPIOH - [0:1] [0:1] [0:1][9:10] System configuration controller (SYSCFG) full-featured full-featured full-featured full-featured Direct memory access controller (DMA1) full-featured full-featured full-featured full-featured Nested vectored interrupt controller (NVIC) full-featured full-featured full-featured full-featured Extended interrupt and event controller (EXTI) full-featured full-featured full-featured full-featured Analog-to-digital converter (ADC1) full-featured full-featured full-featured full-featured Comparator (COMP1) full-featured full-featured full-featured full-featured Comparator (COMP2) full-featured full-featured full-featured full-featured Advanced encryption standard hardware accelerator (AES) full-featured full-featured General-purpose timers (TIM2) full-featured full-featured full-featured full-featured General-purpose timers (TIM3) - General-purpose timers (TIM21) full-featured full-featured full-featured full-featured General-purpose timers (TIM22) - full-featured full-featured full-featured Basic timers (TIM6) - - Basic timers (TIM7) - - Low power timer (LPTIM1) full-featured full-featured full-featured full-featured Independent watchdog (IWDG) full-featured full-featured full-featured full-featured System window watchdog (WWDG) full-featured full-featured full-featured full-featured Real-time clock (RTC) full-featured full-featured full-featured full-featured Inter-integrated circuit (I2C1) interface full-featured full-featured full-featured full-featured Inter-integrated circuit (I2C2) interface - - Inter-integrated circuit (I2C3) interface - - Universal synchronous asynchronous receiver transmitter (USART1) - - 45/874 DocID025942 Rev 5 - full-featured full-featured - - full-featured full-featured full-featured full-featured - full-featured full-featured full-featured - full-featured full-featured full-featured RM0377 Documentation conventions Table 2. Features per category (continued) Feature Category 1 Universal synchronous asynchronous receiver transmitter (USART2) Category 2 Category 3 Category 5 no synchronous mode, no LIN mode, no dual clock, full-featured full-featured full-featured no receiver timeout, no ModBus, no autobaudrate Universal synchronous asynchronous receiver transmitter (USART4) - - - full-featured Universal synchronous asynchronous receiver transmitter (USART5) - - - full-featured Low-power universal asynchronous receiver transmitter (LPUART1) full-featured full-featured full-featured full-featured Serial peripheral interface(SPI1) full-featured full-featured full-featured full-featured Serial peripheral interface/ inter-IC sound (SPI2/I2S2) - Debug support (DBG) full-featured full-featured full-featured full-featured Device electronic signature full-featured full-featured full-featured full-featured DocID025942 Rev 5 - full-featured full-featured 46/874 46 System and memory overview RM0377 2 System and memory overview 2.1 System architecture The main system consists of: Two masters: – Cortex®-M0+ core (AHB-lite bus) – GP-DMA (general-purpose DMA) Three slaves: – Internal SRAM – Internal Non-volatile memory – AHB to APB, which connects all the APB peripherals These are interconnected using a multilayer AHB bus architecture as shown in Figure 1: Figure 1. System architecture *3,2SRUWV $%&'(+ ,23257 &RUWH[ 0 0,) 0HPRU\LQWHUIDFH 6\VWHPEXV 190PHPRU\ 65$0 %XVPDWUL[ '0$ $+%EXV '0$ &RQWUROOHU &KDQQHOV WR $+%$3% %ULGJHV 5HVHWDQG FORFN FRQWUROOHU 5&& &5& $3%EXVHV 6<6&)* ),5(:$// 3:5 (;7, $'& &203 7,0 /37,0 ,:'* ::'* 57& '%*0&8 ,& 86$57/38$57 63, '0$UHTXHVW 069 1. Refer to Table 1: STM32L0x1 memory density, to Table 2: Features per category and to the device datasheets for the GPIO ports and peripherals available on your device. 47/874 DocID025942 Rev 5 RM0377 2.1.1 System and memory overview S0: Cortex®-bus This bus connects the DCode/ICode bus of the Cortex®-M0+ core to the BusMatrix. This bus is used by the core to fetch instructions, get data and access the AHB/APB resources. 2.1.2 S1: DMA-bus This bus connects the AHB master interface of the DMA to the BusMatrix which manages the access of the different masters to Flash memory and data EEPROM, the SRAM and the AHB/APB peripherals. 2.1.3 BusMatrix The BusMatrix manages the access arbitration between masters. The arbitration uses a Round Robin algorithm. The BusMatrix is composed of two masters (CPU, DMA) and three slaves (NVM interface, SRAM, AHB2APB1/2 bridges). AHB/APB bridges The AHB/APB bridge provide full synchronous connections between the AHB and the 2 APB buses. APB1 and APB2 operate at a maximum frequency of 32 MHz. Refer to Section 2.2.2: Memory map and register boundary addresses on page 50 for the address mapping of the peripherals connected to this bridge. After each device reset, all peripheral clocks are disabled (except for the SRAM and MIF). Before using a peripheral you have to enable its clock in the RCC_AHBENR, RCC_APB2ENR, RCC_APB1ENR or RCC_IOPENR register. Note: When a 16- or 8-bit access is performed on an APB register, the access is transformed into a 32-bit access: the bridge duplicates the 16- or 8-bit data to feed the 32-bit vector. DocID025942 Rev 5 48/874 48 RM0377 2.2 Memory organization 2.2.1 Introduction Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space. The bytes are coded in memory in Little Endian format. The lowest numbered byte in a word is considered the word’s least significant byte and the highest numbered byte the most significant. The addressable memory space is divided into 8 main blocks, of 512 Mbytes each. Figure 2. Memory map [)))))))) [( [( [))) &RUWH[0 SHULSKHUDOV )/0/24 [ RESERVED [& [)) !(" [ RESERVED [$ [ [))))))) 2SWLRQE\WHV !0" [ [ 6\VWHP PHPRU\ !0" [ [ RESERVED [ 3HULSKHUDOV [ RESERVED [ )ODVKV\VWHP PHPRU\ 65$0 [ RESERVED &2'( [ [ &LASHSYSTEM MEMORYOR 32!- DEMENDINGON "//4 CONFIGURATION 5HVHUYHG 069 49/874 DocID025942 Rev 5 RM0377 All the memory areas that are not allocated to on-chip memories and peripherals are considered “Reserved”. For the detailed mapping of available memory and register areas, please refer to Memory map and register boundary addresses and peripheral sections. 2.2.2 Memory map and register boundary addresses See the datasheet corresponding to your device for a comprehensive diagram of the memory map. The following table gives the boundary addresses of the peripherals available in the devices. Table 3. STM32L0x1 peripheral register boundary addresses(1) Bus IOPORT AHB Boundary address Size (bytes) Peripheral Peripheral register map 0X5000 1C00 - 0X5000 1FFF 1K GPIOH Section 8.4.12: GPIO register map 0X5000 1400 - 0X5000 1BFF 2K Reserved - 0X5000 1000 - 0X5000 13FF 1K GPIOE Section 8.4.12: GPIO register map 0X5000 0C00 - 0X5000 0FFF 1K GPIOD Section 8.4.12: GPIO register map 0X5000 0800 - 0X5000 0BFF 1K GPIO C Section 8.4.12: GPIO register map 0X5000 0400 - 0X5000 07FF 1K GPIOB Section 8.4.12: GPIO register map 0X5000 0000 - 0X5000 03FF 1K GPIOA Section 8.4.12: GPIO register map 0X4002 6400 - 0X4002 FFFF 49 K Reserved - 0X4002 6000 - 0X4002 63FF 1K AES (Cat. 1, 2 and 5 with AES only) Section 15.12.13: AES register map 0X4002 5400 - 0X4002 5FFF 3K Reserved - 0X4002 4400 - 0X4002 53FF 3K Reserved - 0X4002 3400 - 0X4002 3FFF 3K Reserved - 0X4002 3000 - 0X4002 33FF 1K CRC Section 4.4.6: CRC register map 0X4002 2400 - 0X4002 2FFF 3K Reserved - 0X4002 2000 - 0X4002 23FF 1K FLASH Section 3.7.11: Flash register map 0X4002 1400 - 0X4002 1FFF 3K Reserved - 0X4002 1000 - 0X4002 13FF 1K RCC Section 7.3.21: RCC register map 0X4002 0400 - 0X4002 0FFF 3K Reserved - 0X4002 0000 - 0X4002 03FF 1K DMA1 Section 10.4.8: DMA register map DocID025942 Rev 5 50/874 55 RM0377 Table 3. STM32L0x1 peripheral register boundary addresses(1) (continued) Bus APB2 APB1 51/874 Boundary address Size (bytes) Peripheral Peripheral register map 0X4001 5C00 - 0X4001 FFFF 42 K Reserved - 0X4001 5800 - 0X4001 5BFF 1K DBG Section 27.10: DBG register map 0X4001 3C00 - 0X4001 57FF 7K Reserved - 0X4001 3800 - 0X4001 3BFF 1K USART1 Section 24.8.12: USART register map 0X4001 3400 - 0X4001 37FF 1K Reserved - 0X4001 3000 - 0X4001 33FF 1K SPI1 Section 26.7.10: SPI register map 0X4001 2800 - 0X4001 2FFF 2K Reserved - 0X4001 2400 - 0X4001 27FF 1K ADC1 Section 13.12.12: ADC register map 0X4001 2000 - 0X4001 23FF 1K Reserved - 0X4001 1C00 - 0X4001 1FFF 1K Firewall Section 5.4.8: Firewall register map 0X4001 1800 - 0X4001 1BFF 1K Reserved - 0X4001 1400 - 0X4001 17FF 1K TIM22 Section 17.4.16: TIM21/22 register map 0X4001 0C000 - 0X4001 13FF 2K Reserved - 0X4001 0800 - 0X4001 0BFF 1K TIM21 Section 17.4.16: TIM21/22 register map 0X4001 0400 - 0X4001 07FF 1K EXTI Section 12.5.7: EXTI register map 0X4001 0000 - 0X4001 03FF 1K SYSCFG, COMP Section 9.2.8: SYSCFG register map, Section 14.5.3: COMP register map 0X4000 8000 - 0X4000 FFFF 32 K Reserved - 0X4000 7C00 - 0X4000 7FFF 1K LPTIM1 Section 19.6.9: LPTIM register map 0X4000 7800 - 0X4000 7BFF 1K I2C3 Section 23.7.12: I2C register map 0X4000 7000 - 0X4000 73FF 1K PWR Section 6.4.3: PWR register map 0X4000 5C00 - 0x4000 6FFF 1K Reserved - DocID025942 Rev 5 RM0377 Table 3. STM32L0x1 peripheral register boundary addresses(1) (continued) Bus Boundary address Size (bytes) Peripheral Peripheral register map 0X4000 5800 - 0X4000 5BFF 1K I2C2 Section 23.7.12: I2C register map 0X4000 5400 - 0X4000 57FF 1K I2C1 Section 23.7.12: I2C register map 0X4000 5000 - 0X4000 53FF 1K USART5 Section 24.8.12: USART register map 0X4000 4C00 - 0X4000 4FFF 1K USART4 Section 24.8.12: USART register map 0X4000 4800 - 0X4000 4BFF 1K LPUART1 Section 25.7.10: LPUART register map 0X4000 4400 - 0X4000 47FF 1K USART2 Section 24.8.12: USART register map 0X4000 3C000 - 0X4000 43FF 2K Reserved - 0X4000 3800 - 0X4000 3BFF 1K SPI2 Section 26.7.10: SPI register map 0X4000 3400 - 0X4000 37FF 1K Reserved - 0X4000 3000 - 0X4000 33FF 1K IWDG Section 20.4.6: IWDG register map 0X4000 2C00 - 0X4000 2FFF 1K WWDG Section 21.4.4: WWDG register map 0X4000 2800 - 0X4000 2BFF 1K RTC + BKP_REG Section 22.6.21: RTC register map 0X4000 1800 - 0X4000 27FF 3K Reserved - 0X4000 1400 - 0X4000 17FF 1K TIMER7 Section 18.4.9: TIM6/7 register map 0X4000 1000 - 0X4000 13FF 1K TIMER6 Section 18.4.9: TIM6/7 register map 0X4000 0800 - 0X4000 0FFF 1K Reserved - 0X4000 0400 - 0X4000 07FF 1K TIMER3 Section 16.5: TIMx register map 0X4000 0000 - 0X4000 03FF 1K TIMER2 Section 16.5: TIMx register map 0X2000 2000 - 0X3FFF FFFF ~524 M Reserved - 0X2000 0000 - 0X2000 4FFF up to 8K SRAM - APB1 SRAM DocID025942 Rev 5 52/874 55 RM0377 Table 3. STM32L0x1 peripheral register boundary addresses(1) (continued) Bus NVM Boundary address Size (bytes) Peripheral Peripheral register map 0X0800 0000 - 0X0802 FFFF up to 192 K Flash program memory - 0x0808 0000 - 0x0808 17FF up to 6 K Data EEPROM - 0x1FF0 0000 - 0x1FF0 1FFF 8K System memory - 0x1FF8 0020 - 0x1FF8 007F 96 Factory option bytes - 0x1FF8 0000 - 0x1FF8 001F 32 User option bytes - 1. Refer to Table 1: STM32L0x1 memory density, to Table 2: Features per category and to the device datasheets for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or peripherals are reserved. 2.3 Embedded SRAM STM32L0x1 devices feature up to 8 Kbytes of static SRAM.This RAM can be accessed as bytes, half-words (16 bits) or full words (32 bits). This memory can be addressed at maximum system clock frequency without wait state and thus by both CPU and DMA. The SRAM start address is 0x2000 0000. The CPU can access the SRAM from address 0x0000 0000 when physical remap is selected through boot pin or MEM_MODE (see Section 9.2.1: SYSCFG memory remap register (SYSCFG_CFGR1)). 2.4 Boot configuration In the STM32L0x1, three different boot modes can be selected through the BOOT0 pin and boot configuration bits in the User option byte, as shown in the following table. Table 4. Boot modes(1) Boot mode configuration 53/874 Aliasing nBOOT1 bit BOOT0 pin nBOOT_SEL bit nBOOT0 bit X 0 0 X Flash program memory is selected as boot area 1 1 0 X System memory is selected as boot area 0 1 0 X Embedded SRAM is selected as boot area X X 1 1 Flash program memory is selected as boot area DocID025942 Rev 5 RM0377 Table 4. Boot modes(1) (continued) Boot mode configuration Aliasing nBOOT1 bit BOOT0 pin nBOOT_SEL bit nBOOT0 bit 1 X 1 0 System memory is selected as boot area 0 X 1 0 Embedded SRAM is selected as boot area 1. Grayed options are available on category 1 devices only. The boot mode configuration is latched on the 2nd rising edge of SYSCLK after reset. For category 1 devices, the value present on BOOT0 pin is latched on NRST rising edge. It is up to the user to set nBOOT1 and BOOT0 to select the required boot mode. The boot mode configuration is also re-sampled when exiting from Standby mode, except for category 1 devices where BOOT0 pin is latched on NRST rising edge. Consequently the boot mode configuration must not be modified in Standby mode (except for category 1 devices). After this startup delay has elapsed, the CPU fetches the top-of-stack value from address 0x0000 0000, then starts code execution from the boot memory at 0x0000 0004. Depending on the selected boot mode, Flash program memory, system memory or SRAM is accessible as follows: Boot from Flash program memory: the Flash program memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x0800 0000). In other words, the Flash memory contents can be accessed starting from address 0x0000 0000 or 0x0800 0000. Boot from system memory: the system memory is aliased in the boot memory space (0x0000 0000), but still accessible from its original memory space (0x1FF0 0000). Boot from the embedded SRAM: the SRAM is aliased in the boot memory space (0x0000 0000), but it is still accessible from its original memory space (0x2000 0000). BOOT0/GPIO pin sharing (category 1 devices only) On category 1 devices, the BOOT0 pin is shared with a GPIO pin. The pin state is latched on NRST rising edge as BOOT0 state. The pin logic level can then be read as an input value on the shared GPIO pin. This pin feature specific input voltage characteristics (refer to the corresponding datasheets for details). Empty check (category 1 devices only) On category 1 devices, an internal empty check flag is implemented to allow easy programming of virgin devices by the bootloader. This flag is used when BOOT0 pin is configured to select Flash program memory as target boot area. When this flag is set, the device is considered as unprogrammed and the system memory (bootloader) is selected as boot area instead of the Flash program memory to allow the application to program the Flash memory. The empty check flag is updated only when the option bytes are loaded: it is set when the content of address 0x8000 0000 is read as 0x0000 0000 and cleared otherwise. As a result, only a power-on reset or setting OBL_LAUNCH bit in FLASH_CR register can clear this flag after programming a virgin device to execute user code after system reset. DocID025942 Rev 5 54/874 55 RM0377 Note: If the device is programmed for the first time but the option bytes are not reloaded, the system memory will still be selected as boot area after system reset. In this case, the bootloader code switches the boot memory mapping to Flash program memory and performs a jump to the user code it hosts. Bank swapping (category 5 devices only) For devices featuring two banks, the bank swapping mechanism allows the CPU to point either to bank1 or to bank 2 in the boot memory space (0x0000 0000). Either Flash program and data EEPROM address are changed (see Table 10: NVM organization for UFB = 0 (128 Kbyte category 5 devices), Table 12: NVM organization for UFB = 0 (64 Kbyte category 5 devices)). Physical remap Once the boot pin and bit are selected, the application software can modify the memory accessible in the code area. This modification is performed by programming the MEM_MODE bits in the SYSCFG memory remap register (SYSCFG_CFGR1). Embedded bootloader The embedded bootloader is located in the System memory, programmed by ST during production. It is used to reprogram the Flash memory using one of the following serial interfaces: For category 1 devices: USART2 or SPI1. For category 2 devices: USART2 or SPI1. For category 3 devices: USART1, USART2, SPI1 or SPI2 For category 5 devices: USART1, USART2, SPI1, SPI2, I2C1 or I2C2. For details concerning the bootloader serial interface corresponding I/O, refer to your device datasheet. For further details on STM32 bootloader, please refer to AN2606. 55/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) 3 Flash program memory and data EEPROM (FLASH) 3.1 Introduction The non-volatile memory (NVM) is composed of: 3.2 Up to 192 Kbytes of Flash program memory. This area is used to store the application code. Up to 6 Kbytes of data EEPROM An information block: – Up to 8 Kbytes of System memory – Up to 8x4 bytes of user Option bytes – Up to 96 bytes of factory Option bytes NVM main features The NVM interface features: Read interface organized by word, half-word or byte in every area Programming in the Flash memory performed by word or half-page Programming in the Option bytes area performed by word Programming in the data EEPROM performed by word, half-word or byte Erase operation performed by page (in Flash memory, data EEPROM and Option bytes) Option byte Loader ECC (Error Correction Code): 6 bits stored for every word to recognize and correct just one error Mass erase operation Read / Write protection PCROP protection Low-power mode Category 5 devices only: – Dual-bank memory with read-while-write – Dual-bank boot capability allowing to boot either from Bank 1 or Bank 2 at startup – Bank swapping capability. DocID025942 Rev 5 56/874 114 Flash program memory and data EEPROM (FLASH) 3.3 NVM functional description 3.3.1 NVM organization RM0377 The NVM is organized as 32-bit memory cells that can be used to store code, data, boot code or Option bytes. The memory array is divided into pages. A page is composed of 32 words (or 128 bytes) in Flash program memory and System memory, and 1 single word (or 4 bytes) in data EEPROM and Option bytes areas (user and factory). A Flash sector is made of 32 pages (or 4 Kbytes). The sector is the granularity of the write protection. Table 5. NVM organization (category 1 devices) NVM Flash program memory Data EEPROM Information block 57/874 NVM addresses Size (bytes) Name 0x0800 0000 - 0x0800 007F 128 bytes Page 0 0x0800 0080 - 0x0800 00FF 128 bytes Page 1 - - - 0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31 . . . . . . . . . 0x0800 3000 - 0x0800 307F 128 bytes Page 96 0x0800 3080 - 0x0800 30FF 128 bytes Page 97 - - - 0x0800 3F80 - 0x0800 3FFF 128 bytes Page 127 0x0808 0000 - 0x0808 01FF 512 bytes Data EEPROM 0x1FF0 0000 - 0x1FF0 0FFF 4 Kbytes System memory 0x1FF8 0020 - 0x1FF8 007F 96 bytes Factory Options 0x1FF8 0000 - 0x1FF8 001F 32 bytes User Option bytes DocID025942 Rev 5 Description sector 0 . . . sector 3 RM0377 Flash program memory and data EEPROM (FLASH) Table 6. NVM organization (category 2 devices) NVM Flash program memory Data EEPROM Information block NVM addresses Size (bytes) Name 0x0800 0000 - 0x0800 007F 128 bytes Page 0 0x0800 0080 - 0x0800 00FF 128 bytes Page 1 - - - 0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31 . . . . . . . . . 0x0800 7000 - 0x0800 707F 128 bytes Page 224 0x0800 7080 - 0x0800 70FF 128 bytes Page 225 - - - 0x0800 7F80 - 0x0800 7FFF 128 bytes Page 255 0x0808 0000 - 0x0808 03FF 1 Kbytes Data EEPROM 0x1FF0 0000 - 0x1FF0 0FFF 4 Kbytes System memory 0x1FF8 0020 - 0x1FF8 007F 96 bytes Factory Options 0x1FF8 0000 - 0x1FF8 001F 32 bytes User Option bytes Description sector 0 . . . sector 7 Table 7. NVM organization (category 3 devices) NVM Flash program memory(1) Data EEPROM NVM addresses Size (bytes) Name 0x0800 0000 - 0x0800 007F 128 bytes Page 0 0x0800 0080 - 0x0800 00FF 128 bytes Page 1 - - - 0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31 . . . . . . . . . 0x0800 7000 - 0x0800 707F 128 bytes Page 224 0x0800 7080 - 0x0800 70FF 128 bytes Page 225 - - - 0x0800 7F80 - 0x0800 7FFF 128 bytes Page 255 . . . . . . . . . 0x0800 F000 - 0x0800 F07F 128 bytes Page 480 0x0800 F080 - 0x0800 F0FF 128 bytes Page 481 - - - 0x0800 FF80 - 0x0800 FFFF 128 bytes Page 511 0x0808 0000 - 0x0808 07FF 2 Kbytes - DocID025942 Rev 5 Description sector 0 . . . sector 7 . . . sector 15 Data EEPROM 58/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Table 7. NVM organization (category 3 devices) (continued) NVM Information block NVM addresses Size (bytes) Name Description 0x1FF0 0000 - 0x1FF0 0FFF 4 Kbytes - System memory 0x1FF8 0020 - 0x1FF8 007F 96 bytes - Factory Options 0x1FF8 0000 - 0x1FF8 001F 32 bytes - User Option bytes 1. For 32 Kbyte category 3 devices, the Flash program memory is divided into 256 pages of 128 bytes each. Table 8. NVM organization for UFB = 0 (192 Kbyte category 5 devices) NVM Flash program memory Data EEPROM Information block 59/874 NVM addresses Size (bytes) Name 0x0800 0000 - 0x0800 007F 128 bytes Page 0 0x0800 0080 - 0x0800 00FF 128 bytes Page 1 - - - 0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31 . . . . . . . . . 0x0800 7000 - 0x0800 707F 128 bytes Page 224 0x0800 7080 - 0x0800 70FF 128 bytes Page 225 - - - 0x0800 7F80 - 0x0800 7FFF 128 bytes Page 255 . . . . . . . . . - - - 0x0801 7F80- 0x0801 7FFF 128 bytes Page 767 sector 23 0x0801 8000 - 0x0801 807F 128 bytes Page 768 sector 24 . . . . . . . . . . . . 0x0802 F000 - 0x0802 F07F 128 bytes Page 1504 0x0802 F080 - 0x0802 F0FF 128 bytes Page 1505 - - - 0x0802 FF80 - 0x0802 FFFF 128 bytes Page 1535 0x0808 0000 - 0x0808 0BFF 0x0808 0C00 - 0x0808 17FF 6 Kbytes Description sector 0 . . . Bank 1 sector 7 . . . Bank 2 sector 47 - Data EEPROM Bank 1 - Data EEPROM Bank 2 0x1FF0 0000 - 0x1FF0 1FFF 8 Kbytes - System memory 0x1FF8 0020 - 0x1FF8 007F 96 bytes - Factory Options 0x1FF8 0000 - 0x1FF8 001F 32 bytes - User Option bytes DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Table 9. Flash memory and data EEPROM remapping (192 Kbyte category 5 devices) NVM addresses MEM_MODE = 0, BOOT0= 0 and UFB = 0 MEM_MODE = 0, BOOT0= 0 and UFB = 1 MEM_MODE = 0, BOOT0= 0 and UFB = 0 MEM_MODE = 0, BOOT0= 0 and UFB = 1 Bank 1 0x0800 0000 0x0801 7FFF 0x0801 8000 0x0802 FFFF 0x0000 0000 0x0001 7FFF 0x0001 8000 0x0002 FFFF Bank 2 0x0801 8000 0x0802 FFFF 0x08000 0000 0x0801 7FFF 0x0001 8000 0x0002 FFFF 0x0000 0000 0x0001 7FFF Bank 1 0x0808 0000 0x0808 0BFF 0x0808 0C00 0x0808 17FF 0x0008 0000 0x0008 0BFF 0x0008 0C00 0x0008 17FF Bank 2 0x0808 0C00 0x0808 17FF 0x0808 0000 0x0008 0BFF 0x0008 0C00 0x0008 17FF 0x0008 0000 0x0008 0BFF NVM Description Flash program memory Data EEPROM Remapped addresses Table 10. NVM organization for UFB = 0 (128 Kbyte category 5 devices) NVM Flash program memory NVM addresses Size (bytes) Name 0x0800 0000 - 0x0800 007F 128 bytes Page 0 0x0800 0080 - 0x0800 00FF 128 bytes Page 1 - - - 0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31 . . . . . . . . . 0x0800 7000 - 0x0800 707F 128 bytes Page 224 0x0800 7080 - 0x0800 70FF 128 bytes Page 225 - - - 0x0800 7F80 - 0x0800 7FFF 128 bytes Page 255 . . . . . . . . . . . . 0x0800 FF80- 0x0800 FFFF 128 bytes Page 511 sector 15 0x0801 0000 - 0x0801 007F 128 bytes Page 512 sector 16 . . . . . . . . . . . . 0x0801 F000 - 0x0801 F07F Data EEPROM - - 0x0801 FF80 - 0x0801 FFFF 128 bytes Page 1023 0x0808 0C00 - 0x0808 17FF sector 0 . . . Bank 1 sector 7 Bank 2 Page 992 - 0x0808 0000 - 0x0808 0BFF Description 6 Kbytes DocID025942 Rev 5 sector 31 - Data EEPROM Bank 1 - Data EEPROM Bank 2 60/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Table 10. NVM organization for UFB = 0 (128 Kbyte category 5 devices) (continued) NVM Information block NVM addresses Size (bytes) Name Description 0x1FF0 0000 - 0x1FF0 1FFF 8 Kbytes - System memory 0x1FF8 0020 - 0x1FF8 007F 96 bytes - Factory Options 0x1FF8 0000 - 0x1FF8 001F 32 bytes User Option bytes Table 11. Flash memory and data EEPROM remapping (128 Kbyte category 5 devices) NVM addresses NVM MEM_MODE = 0, BOOT0= 0 and UFB = 0 MEM_MODE = 0, BOOT0= 0 and UFB = 1 MEM_MODE = 0, BOOT0= 0 and UFB = 0 MEM_MODE = 0, BOOT0= 0 and UFB = 1 Bank 1 0x0800 0000 0x0800 FFFF 0x0801 0000 0x0801 FFFF 0x0000 0000 0x0000 FFFF 0x0001 0000 0x0001 FFFF Bank 2 0x0801 0000 0x0801 FFFF 0x0800 0000 0x0800 FFFF 0x0001 0000 0x0001 FFFF 0x0000 0000 0x0000 FFFF Bank 1 0x0808 0000 0x0808 0BFF 0x0808 0C00 0x0808 17FF 0x0008 0000 0x0008 0BFF 0x0008 0C00 0x0008 17FF Bank 2 0x0808 0C00 0x0808 17FF 0x0808 0000 0x0808 0BFF 0x0008 0C00 0x0008 17FF 0x0008 0000 0x0008 0BFF Description Flash program memory Remapped addresses Data EEPROM Table 12. NVM organization for UFB = 0 (64 Kbyte category 5 devices)(1) NVM Flash program memory Data EEPROM Information block NVM addresses Size (bytes) Name 0x0800 0000 - 0x0800 007F 128 bytes Page 0 0x0800 0080 - 0x0800 00FF 128 bytes Page 1 - - - 0x0800 0F80 - 0x0800 0FFF 128 bytes Page 31 . . . . . . . . . 0x0800 F000 - 0x0800 F07F 128 bytes Page 480 - - - - - - 0x0800 FF80 - 0x0800 FFFF 128 bytes Page 511 0x0808 0C00 - 0x0808 17FF 3 Kbytes - Data EEPROM Bank 2 0x1FF0 0000 - 0x1FF0 1FFF 8 Kbytes - System memory 0x1FF8 0020 - 0x1FF8 007F 96 bytes - Factory Options 0x1FF8 0000 - 0x1FF8 001F 32 bytes 1. Flash memory and data EEPROM remapping is not possible on 64 Kbyte category 5 devices. 61/874 DocID025942 Rev 5 Description sector 0 . . . Bank 1 sector 15 User Option bytes RM0377 3.3.2 Flash program memory and data EEPROM (FLASH) Dual-bank boot capability Category 5 devices have two Flash memory banks: Bank 1 and Bank 2. They feature an additional boot mechanism which allows booting either from Bank 2 or from Bank 1 depending on BFB2 bit status (bit 23 in FLASH_OPTR register). When the BFB2 bit is set and the boot pins are configured to boot from Flash memory (BOOT0 = 0 and BOOT1 = x), the device maps the System memory at address 0. It boots from the System memory after reset and Standby and executes (during approximately 440 µs) the embedded bootloader code which implements the dualbank boot mechanism: Note: a) The System memory code first checks Bank 2. If it contains a valid code (see note below), it sets the UFB bit in SYSCFG_CFGR1 register to map Bank 2 at address 0x0800 0000, jumps to the application code located in Bank 2, and leaves the bootloader. b) If the code located in Bank 2 is not valid, the System memory code checks Bank 1 code. If it is valid (see note below), it jumps to the application located in Bank 1 (UFB is kept at ‘0’ so that Bank 1 remains mapped at address 0x0800 0000). c) If both Bank 2 and Bank 1 do not contain valid code (see note below), the normal bootloader operations are executed when the protection level2 is disabled. Otherwise, the System memory code jumps to Bank 1 regardless of its validity. Refer to Table 13 for more details. When BFB2 bit is reset (default state), the dual-bank boot mechanism is not performed. The code is considered as valid when the first data located at the bank start address (which should be the stack pointer) points to a valid address (stack top address). For category 5 devices, the Flash memory Bank 1 and Bank 2, System memory or SRAM can be selected as the boot area, as shown in Table 13 below. Table 13. Boot pin and BFB2 bit configuration Protection level BFB2 bit Boot mode selection pins Boot mode Aliasing BOOT1 BOOT0 0 X 0 User Flash memory User Flash memory Bank1 is selected as the boot area. 0 1 System memory Boot on System memory to execute bootloader. 1 1 Embedded SRAM Boot on Embedded SRAM X 0 System memory Boot on System memory to execute dual bank boot mechanism. If Bank 2 and Bank 1are not valid, bootloader is executed for Flash update. 0 1 System memory Boot on System memory to execute bootloader. 1 1 Embedded SRAM Boot on Embedded SRAM. 0 or 1 1 DocID025942 Rev 5 62/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Table 13. Boot pin and BFB2 bit configuration (continued) Protection level BFB2 bit Boot mode selection pins Boot mode Aliasing BOOT1 BOOT0 0 2 1 X 0 User Flash memory 0 1 User Flash memory 1 1 User Flash memory X 0 System memory 0 1 System memory 1 1 System memory User Flash memory Bank1 is selected as the boot area. Boot on System memory to execute dual bank boot mechanism. If Bank 2 isn’t valid, it jumps to Bank 1. When entering System memory, you can either execute the bootloader (for Flash update) or execute Dual Bank Jump (see Table 13). When protection level2 is enabled, the bootloader is never executed to perform a Flash update. When the conditions a, b, and c described below are fulfilled, it is equivalent to configuring boot pins for System memory boot (BOOT0 = 1 and BOOT1 = 0). In this case when protection level2 is disabled, normal bootloader operations are executed. a) BFB2 bit is set. b) Both banks do not contain valid code. c) Boot pins configured as follows: BOOT0 = 0 and BOOT1 = x. When the BFB2 bit is set, and Bank 2 and/or Bank 1 contain valid user application code, the Dual Bank Boot is always performed (bootloader always jumps to the user code). Consequently, if you have set the BFB2 bit (to boot from Bank 2) then, to be able to execute the bootloader code for Flash update when protection level2 is disabled, you have to: 3.3.3 a) Set the BFB2 bit to 0, BOOT0 = 1 and BOOT1 = 0 or, b) Program the content of address 0x0801 8000/0x0801 0000 (base address of Bank2) and 0x0800 0000 (base address of Bank1) to 0x0. Reading the NVM Protocol to read To read the NVM content, take any address from Table 7. The clock of the memory interface must be running. (see MIFEN bit in Section 7.3.12: AHB peripheral clock enable register (RCC_AHBENR)). Depending on the clock frequency, a 0 or a 1 wait state can be necessary to read the NVM. The user must set the correct number of wait states (LATENCY bit in the FLASH_ACR register). No control is done to verify if the frequency or the power used is correct, with respect to the number of wait states. A wrong number of wait states can generate wrong read values (high frequency and 0 wait states) or a long time to execute a code (low frequency with 1 wait state). You can read the NVM by word (4 bytes), half-word (2 bytes) or byte. 63/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) When the NVM features only one bank, it is not possible to read during a write/erase operation. If a write/erase operation is ongoing, the reading will be in a wait state until the write/erase operation completes, stalling the master that requested the read operation, except when the address is read-protected. In this case, the error is sent to the master by a hard fault or a memory interface flag; no stall is generated and no read is waiting. When two banks are available (category 5 devices), read operations from one bank can be performed while write or erase operations are performed on the other bank. Relation between CPU frequency/Operation mode/NVM read time The device (and the NVM) can work at different power ranges. For every range, some master clock frequencies can be set. Table 14 resumes the link between the power range and the frequencies to ensure a correct time access to the NVM. Table 14. Link between master clock power range and frequencies Name Power range Maximum frequency (with 1 wait state) Maximum frequency (without wait states) Range 1 1.65 V - 1.95 V 32 MHz 16 MHz Range 2 1.35 V - 1.65 V 16 MHz 8 MHz Range 3 1.05 V - 1.35 V 4.2 MHz 4.2 MHz Table 15 shows the delays to read a word in the NVM. Comparing the complete time to read a word (Ttotal) with the clock period, you can see that in Range 3 no wait state is necessary, also with the maximum frequency (4.2 MHz) allowed by the device. Ttotal is the time that the NVM needs to return a value, and not the complete time to read it (from memory to Core through the memory interface); all remaining time is lost. Table 15. Delays to memory access and number of wait states Name Ttotal Range 1 46.1 ns Range 2 86.8 ns Range 3 184.6 ns Frequency Period No wait state required 32 MHz 31.25 1 16 MHz 62.5 0 16 MHz 62.5 1 8 MHz 125 0 4 MHz 250 0 2 MHz 500 0 DocID025942 Rev 5 64/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Change the CPU Frequency After reset, the clock used is the MSI (2.1 MHz) and 0 wait state is configured in the FLASH_ACR register. The following software sequences have to be respected to tune the number of wait states needed to access the NVM with the CPU frequency. A CPU clock or a number of wait state configuration changes may take some time before being effective. Checking the AHB prescaler factor and the clock source status values is a way to ensure that the correct CPU clock frequency is the configured one. Similarly, the read of FLASH_ACR is a way to ensure that the number of programmed wait states is effective. Increasing the CPU frequency (in the same voltage range) 1. Program 1 wait state in LATENCY bit of FLASH_ACR register, if necessary. 2. Check that the new number of wait states is taken into account by reading the FLASH_ACR register. When the number of wait states changes, the memory interface modifies the way the read access is done to the NVM. The number of wait states cannot be modified when a read operation is ongoing, so the memory interface waits until no read is done on the NVM. If the master reads back the content of the FLASH_ACR register, this reading is stopped (and also the master which requested the reading) until the number of wait states is really changed. If the user does not read back the register, the following access to the NVM may be done with 0 wait states, even if the clock frequency has been increased, and consequently the values are wrong. 3. Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock Controller (RCC). 4. Check that the new CPU clock source and/or the new CPU clock prescaler value is taken into account by reading respectively the clock source status and/or the AHB prescaler value in the Reset & Clock Controller (RCC). This check is important as some clocks may take time to get available. For code example, refer to A.2.1: Increasing the CPU frequency preparation sequence code, A.2.3: Switch from PLL to HSI16 sequence code and A.2.4: Switch to PLL sequence code. Decreasing the CPU frequency (in the same voltage range) 65/874 1. Modify the CPU clock source and/or the AHB clock prescaler in the Reset & Clock Controller (RCC). 2. Check that the new CPU clock source and/or the new CPU clock prescaler value is taken into account by reading respectively the clock source status and/or the AHB prescaler value in the Reset and Clock Controller (RCC). 3. Program 0 wait state in LATENCY bit of the FLASH_ACR register, if needed. 4. Check that the new number of wait states is taken into account by reading FLASH_ACR. It is necessary to read back the register for the reasons explained in the previous paragraph. DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Data buffering In the NVM, six buffers can impact the performance (and in some conditions help to reduce the power consumption) during read operations, both for fetch and data. The structure of one buffer is shown on Figure 3. Figure 3. Structure of one internal buffer $GGUHVV 9DOXH +LVWRU\ 069 Each buffer stores 3 different types of information: address, data and history. In a read operation, if the address is found, the memory interface can return data without accessing the NVM. Data in the buffer is 32 bit wide (even if the master only reads 8 or 16 bits), so that a value can be returned whatever the size used in a previous reading. The history is used to know if the content of a buffer is valid and to delete (with a new value) the older one. The buffers are used to store the value received by the NVM during normal read operations, and for speculative readings. Disabling the speculative reading makes that only the data requested by masters is stored in buffers, if enabled (default). This can increase the performance as no wait state is necessary if the value is already available in buffers, and reduce the power consumption as the number of reads in memory is reduced and all combinatorial paths from memory are stable. The buffers are divided in groups to manage different tasks. The number of buffers in every group can change starting from the configuration selected by the user (see Table 16). The total number of buffers used is always 6 (if enabled). The history is always managed by group. The memory interface always searches if a particular address is available in all buffers without checking the group of buffers and if the read is fetch or data. At reset or after a write/erase operation that changes several addresses, all buffers are empty and the history is set to EMPTY. After a program by word, half-word or byte, only the buffer with the concerned address is cleaned. DocID025942 Rev 5 66/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Table 16. Internal buffer management Buffers for fetch DISAB_BUF PREFTEN PRE_READ 1 - 0 Buffers for data Buffers for jumps Buffers for prefetch Buffers for last value Buffers for pre-read Buffers for last value - 0 0 0 0 0 0 0 3 0 1 0 2 0 1 0 2 1 1 0 2 0 0 1 3 0 1 1 1 0 1 1 2 1 1 1 1 If a value in a buffer is not empty, the history shows the time elapsed between the moment it has been read or written. The history is organized as a list of values from the latest to the oldest one. At a given instant, only one buffer in a group can have a particular value of history (except the empty value). Moving a buffer to the latest position, all other buffers in the group move one step further, thus maintaining the order. The history is changed to the latest position when the buffer is read (the master requests for the buffer content) or written (with a new value from the NVM). The memory interface always writes the oldest buffer (or one empty buffer, if any) of the right group when a new address is required in memory. Three configuration bits of the FLASH_ACR register are used to manage the buffering: DISAB_BUF Setting this bit disables all buffers. When this bit is 1, the prefetch or the pre-read operations cannot be enabled and if, for example, the master requests the same address twice, two readings are generated in the NVM. PRFTEN Setting this bit to 1 (with DISAB_BUF to 0) enables the prefetch. When the memory interface does not have any operation in progress, the address following the last address fetched is read and stored in a buffer. PRE_READ Setting this bit to 1 (with DISAB_BUF to 0) enables the pre-read. When the memory interface does not have any operation in progress or prefetch to execute, the address following the last data address is read and stored in a buffer. Fetch and prefetch A memory interface fetch is a read from the NVM to execute the operation that has been read. The memory interface does not check the master who performs the read operation, or the location it reads from, but it only verifies if the read operation is done to execute what has been read. It means that a fetch can be performed: in all areas, with any size (16 or 32 bits). The memory interface stores in the buffers: 67/874 The address of jumps so that, in a loop, it is only necessary to access the NVM the first time, because then the jump address is already available. The last read address so that, when performing a fetching on 16 bits, the other 16 bits are already available. DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) To manage the fetch, the memory interface uses 4 buffers: at reset (DISAB_BUF = 0, PRFTEN = 0, PRE_READ = 0). 3 buffers are used to manage the jumps and 1 buffer to store the last value fetched. With this configuration, the 4 buffers for fetch are organized in 2 groups with separate histories: the group for loops and the group for the last value fetched. Setting the PRFTEN bit to 1 enables the prefetch. The prefetch is a speculative read in the NVM, which is executed when no read is requested by masters, and where the memory interface reads from the last address fetched increased by 4 (one word). This read is with a lower priority and it is aborted if a master requests a read (data or fetch) to a different address than the prefetch one. When the prefetch is enabled, one buffer for loops is moved to a new group (of only one buffer) to store the prefetched value: 2 buffers continue to store the jumps, 1 buffer is used for prefetch and 1 buffer is used for the last value. The memory interface can only prefetch one address, so the function is temporarily disabled when no fetch is done and the prefetch is already completed. After a prefetch, if the master requests the prefetched value, the content of the prefetch buffer is copied to the last value buffer and a new prefetch is enabled. If, instead, the master requests a different address, the content of the prefetch buffer is lost, a read in the NVM is started (if necessary) and, when it is complete, a new prefetch is enabled at the new address fetched increased by 4. The prefetch can only increase the performance when reading with 1 wait state and for mostly linear codes: the user must evaluate the pros and cons to enable or not the prefetch in every situation. The prefetch increases the consumption because many more readings are done in the NVM (and not all of them will be used by the master). To see the advantages of prefetch on Dhrystone code, refer to the Dhrystone performances section. Figure 4 shows the timing to fetch a linear code in the NVM when the prefetch is disabled, both for 0 wait state (a) and 1 wait state (b). You can compare these two sequences with the ones in Figure 5, when the prefetch is enabled, to have an idea of the advantages of a prefetch on a linear code with 0 and 1 wait states. Figure 4. Timing to fetch and execute instructions with prefetch disabled ĐLJĐůĞ ĐLJĐůĞ ĐLJĐůĞ ĐLJĐůĞ ĐLJĐůĞ ĐLJĐůĞ ĐLJĐůĞ ĐLJĐůĞ ĐLJĐůĞ ĐLJĐůĞ ĐLJĐůĞ ϭ Ϯ ϯ ϰ ϱ ϲ ϳ ϴ ϵ ϭϬ ϭϭ ĚĚƌ ϭΘϮ ĚĚƌ ϭΘϮ &ĞƚĐŚ ϭΘϮ &ĞƚĐŚ ϭΘϮ džĞĐ͘ ϭ džĞĐ͘ Ϯ ĚĚƌ ϯΘϰ &ĞƚĐŚ ϯΘϰ tĂŝƚ ;ĂͿ džĞĐ͘ ϯ džĞĐ͘ ϰ ĚĚƌ ϱΘϲ &ĞƚĐŚ ϱΘϲ džĞĐ͘ ϱ džĞĐ͘ ϲ tĂŝƚ džĞĐ͘ ϯ džĞĐ͘ ϰ ĚĚƌ ϱΘϲ &ĞƚĐŚ ϱΘϲ džĞĐ͘ ϭ džĞĐ͘ Ϯ ĚĚƌ ϯΘϰ &ĞƚĐŚ ϯΘϰ ;ďͿ tĂŝƚ džĞĐ͘ ϱ džĞĐ͘ ϲ D^ϯϮϯϵϲsϭ 1. (a) corresponds to 0 wait state. 2. (b) corresponds to 1 wait state. DocID025942 Rev 5 68/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Figure 5 shows the timing to fetch and execute instructions from the NVM with 0 wait states (a) and 1 wait state (b) when the prefetch is enabled. The read executed by the prefetch appears in green. Read as data and pre-read A data read from the memory interface, corresponds to any read operation that is not a fetch. The master reads operation constants and parameters as data. All reads done by DMA (to copy from one address to another) are read as data. No check is done on the location of the data read (can be in every area of the NVM). At reset, (DISAB_BUF = 0, PRFTEN = 0, PRE_READ = 0), the memory interface uses 2 buffers organized in one group to store the last two values read as data. In some particular cases (for example when the DMA is reading a lot of consecutive words in the NVM), it can be useful to enable the pre-read (PRE_READ = 1 with DISAB_BUF = 0). The pre-read works exactly like the prefetch: it is a speculative reading at the last data address increased by 4 (one word). With this configuration, one buffer of data is moved to a new group to store the pre-read value, while the second buffer continues to store the last value read. For a prefetch, the pre-read value is copied in the last read value if the master requests it, or is lost if the master requests a different address. The pre-read has a lower priority than a normal read or a prefetch operation: this means that it will be launched only when no other type of read is ongoing. Pay attention to the fact that a pre-read used in a wrong situation can be harmful: in a code where a data read is not done linearly, reducing the number of buffers (from 2 to 1) used for the last read value can increase the number of accesses to the NVM (and the time to read the value). Moreover, this can generate a delay on prefetch. An example of this situation is the code Dhrystone, whose results are shown in the corresponding section. As for a prefetch operation, the user must select the right moment to enable and disable the pre-read. 69/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Figure 5. Timing to fetch and execute instructions with prefetch enabled F\FOH F\FOH F\FOH F\FOH F\FOH F\FOH F\FOH F\FOH F\FOH $GGU )HWFK ([HF ([HF $GGU )HWFK ([HF ([HF $GGU )HWFK ([HF $GGU $GGU 5HDG )HWFK :DLW $GGU D $GGU 5HDG ([HF ([HF $GGU )HWFK ([HF ([HF 5HDG :DLW $GGU )HWFK $GGU 5HDG :DLW ([HF E ([HF ([HF 069 Table 17 is a summary of the possible configurations. Table 17. Configurations for buffers and speculative reading DISAB_BUF PRFTEN PRE_READ Description 1 X X Buffers disabled 0 0 0 Buffer enabled: no speculative reading is done 0 1 0 Prefetch enabled: speculative reading on fetch enabled 0 0 1 pre-read enabled: speculative reading on data enabled 0 1 1 Prefetch and pre-read enabled: speculative reading on fetch and data enabled DocID025942 Rev 5 70/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Dhrystone performances The Dhrystone test is used to evaluate the memory interface performances. The test has been executed in all memory interface configurations. Refer to Table 18 for a summary of the results. Common parameters are: the matrix size is 20 x 20 the loop is executed 1757 times the version of ARM® compiler is 4.1 [Build 561] Here is some explanation about the results: Table 18. Dhrystone performances in all memory interface configurations 71/874 Number of wait states DISAB_BUF PRFTEN PRE_READ Number of DMIPS (x1000) DMIPS x MHz 0 1 0 0 953 15.25 0 0 0 0 953 15.25 0 0 1 0 953 15.25 0 0 0 1 953 15.25 0 0 1 1 953 15.25 1 1 0 0 677 21.66 1 0 0 0 690 22.08 1 0 1 0 823 26.34 1 0 0 1 691 22.11 1 0 1 1 816 26.11 The pre-read is not useful for this test: when enabled with the prefetch, it reduces the memory interface performance because only one buffer is used to store the last data read and, in this code, the master rarely reads the data linearly. This justifies the very small increase of performance when enabled without a prefetch. The buffers (without speculative readings) with 1 wait state give a little advantage that can be considered without any costs. At a 0 wait state, the best performance (as certified by ARM®) may be due to a different code alignment during the compilation. DocID025942 Rev 5 RM0377 3.3.4 Flash program memory and data EEPROM (FLASH) Writing/erasing the NVM There are many ways to change the NVM content. The memory interface helps to reduce the possibility of unwanted changes and to implement by hardware all sequences necessary to erase or write in the different memory areas. Write/erase protocol To write/erase memory content when the protections have been removed, the user needs to: 1. configure the operation to execute, 2. send to the memory interface the right number of data, writing one or several addresses in the NVM, 3. wait for the operation to complete. During the waiting time, the user can prepare the next operation (except in very particular cases) writing the new configuration and starting to write data for the next write/erase operation. The waiting time depends on the type of operation. A write/erase can last from Tprog (3.2 ms) to 2 x Tglob (3.7 ms) + Tprog (3.2 ms). The memory interface can be configured to write a half-page (16 words in the Flash program memory) with only one waiting time. This can reduce the time to program a big amount of data. Two different protocols can be used: single programming and multiple programming operation. Single programming operation With this protocol, the software has to write a value in a not-protected address of the NVM. When the memory interface receives this writing request, it stalls the master for some pulses of clock (for more details, see Table 19) while it checks the protections and the previous value and it latches the new value inside the NVM. The software can then start to configure the next operation. The operation will complete when the EOP bit of FLASH_SR register rises (if it was 0 at the operation start). The operation time is resumed in Table 21 for all operations. Multiple programming operation (half page) You can write a half-page (16 words) in Flash program memory, To execute this protocol, follow the next conditions: PGAERR bit in the FLASH_SR register has to be zero (no previous alignment errors). The first address has to be half-page aligned (the 6 lower bits of the address have to be at zero). All 16 words must be in the same half-page (address bits 7 to 31 must be the same for all 16 words). This means that the first address sets the half-page and the next ones must be inside this half-page. The written data will be stored sequentially in the next addresses. It is not important that the addresses increase or change (for example, the same address can be used 16 times), as the memory interface will automatically increase the address internally. Only words (32 bits) can be written. DocID025942 Rev 5 72/874 114 Flash program memory and data EEPROM (FLASH) RM0377 When the memory interface receives the first address, it stalls the master for some pulses of clock while it checks the protections and the previous value and it latches the new value inside the NVM (for more details, see Table 19). Then, the memory interface waits for the second address. No read is accepted: only a fetch will be executed, but it aborts the ongoing write operation. After the second address, the memory interface stalls the core for a short time (less than the previous one) to perform a check and to latch it in the NVM before waiting for the next one. This sequence continues until all 16 words have been latched inside the NVM. A wrong alignment or size will abort the write operation. If the 16 addresses are correctly latched, the memory interface starts the write operation. The operation will complete when EOP bit of FLASH_SR register rises (if it was 0 at the operation start). The operation time is resumed in Table 21. This protocol can be used either through application code running from RAM or through DMA with application code running from RAM or core sleeping. Unlocking/locking operations Before performing a write/erase operation, it is necessary to enable it. The user can write into the Flash program memory, data EEPROM and Option bytes areas. To perform a write/erase operation, unlock PELOCK bit of the FLASH_PECR register. When this bit is unlocked (its value is 0), the other bits of the same register can be modified. When PELOCK is 0, the write/erase operations can be executed in the data EEPROM. To write/erase the Flash program memory, unlock PRGLOCK bit of the FLASH_PECR register. The bit can only be unlocked when PELOCK is 0. To write/erase the user Option bytes, unlock OPTLOCK bit of the FLASH_PECR register. The bit can only be unlocked when PELOCK is 0. No relation exists between PRGLOCK and OPTLOCK: the first one can be unlocked when the second one is locked and vice versa. Unlocking the data EEPROM and the FLASH_PECR register After a reset, the data EEPROM and the FLASH_PECR register are not accessible in write mode because PELOCK bit in the FLASH_PECR register is set. The same unlocking sequence unprotects both of them at the same time. The following sequence is used to unlock the data EEPROM and the FLASH_PECR register: Write PEKEY1 = 0x89ABCDEF to the FLASH_PEKEYR register Write PEKEY2 = 0x02030405 to the FLASH_PEKEYR register For code example, refer to A.3.1: Unlocking the data EEPROM and FLASH_PECR register code example. 73/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Any wrong key sequence will lock up FLASH_PECR until the next reset and generate a hard fault. Idem if the master tries to write another register between the two key sequences or if it uses the wrong key. A reading access does not generate an error and does not interrupt the sequence. A hard fault is returned in any of the four cases below: After the first write access if the PEKEY1 value entered is erroneous. During the second write access if PEKEY1 is correctly entered but the value of PEKEY2 does not match. If there is any attempt to write a third value to PEKEYR (attention: this is also true for the debugger). If there is any attempt to write a different register of the memory interface between PEKEY1 and PEKEY2. When properly executed, the unlocking sequence clears PELOCK bit in the FLASH_PECR register. To lock FLASH_PECR and the data EEPROM again, the software only needs to set PELOCK bit in FLASH_PECR. When locked again, PELOCK bit needs a new sequence to return to 0. For code example, refer to A.3.2: Locking data EEPROM and FLASH_PECR register code example. Unlocking the Flash program memory An additional protection is implemented to write/erase the Flash program memory. After a reset, the Flash program memory is no more accessible in write mode: PRGLOCK bit is set in the FLASH_PECR register. A write access to the Flash program memory is granted by clearing PRGLOCK bit. The following sequence is used to unlock the Flash program memory: Unlock the FLASH_PECR register (see the Unlocking the data EEPROM and the FLASH_PECR register section). Write PRGKEY1 = 0x8C9DAEBF to the FLASH_PRGKEYR register. Write PRGKEY2 = 0x13141516 to the FLASH_PRGKEYR register. For code example, refer to A.3.3: Unlocking the NVM program memory code example. If the keys are written with PELOCK set to 1, no error is generated and PRGLOCK remains at 1. It will be unlocked while re-executing the sequence with PELOCK = 0. Any wrong key sequence will lock up PRGLOCK in FLASH_PECR until the next reset, and return a hard fault. A hard fault is returned in any of the four cases below: After the first write access if the entered PRGKEY1 value is erroneous. During the second write access if PRGKEY1 is correctly entered but the PRGKEY2 value does not match. If there is any attempt to write a third value to PRGKEYR (this is also true for the debugger). If there is any attempt to write a different register of the memory interface between PRGKEY1 and PRGKEY2. When properly executed, the unlocking sequence clears the PRGLOCK bit and the Flash program memory is write-accessible. DocID025942 Rev 5 74/874 114 Flash program memory and data EEPROM (FLASH) RM0377 To lock the Flash program memory again, the software only needs to set PRGLOCK bit in FLASH_PECR. When locked again, PRGLOCK bit needs a new sequence to return to 0. If PELOCK returns to 1 (locked), PRGLOCK is automatically locked, too. Unlocking the Option bytes area An additional write protection is implemented on the Option bytes area. It is necessary to unlock OPTLOCK to reload or write/erase the Option bytes area. After a reset, the Option bytes area is not accessible in write mode: OPTLOCK bit in the FLASH_PECR register is set. A write access to the Option bytes area is granted by clearing OPTLOCK. The following sequence is used to unlock the Option bytes area: 1. Unlock the FLASH_PECR register (see the Unlocking the data EEPROM and the FLASH_PECR register section). 2. Write OPTKEY1 = 0xFBEAD9C8 to the FLASH_OPTKEYR register. 3. Write OPTKEY2 = 0x24252627 to the FLASH_OPTKEYR register. For code example, refer to A.3.4: Unlocking the option bytes area code example. If the keys are written with PELOCK = 1, no error is generated, OPTLOCK remains at 1 and it will be unlocked when re-executing the sequence with PELOCK to 0. Any wrong key sequence will lock up OPTLOCK in FLASH_PECR until the next reset, and return a hard fault. A hard fault is returned in any of the four cases below: After the first write access if the OPTKEY1 value entered is erroneous. During the second write access if OPTKEY1 is correctly entered but the OPTKEY2 value does not match. If there is any attempt to write a third value to OPTKEYR (this is also true for the debugger). If there is any attempt to write a different register of the memory interface between OPTKEY1 and OPTKEY2. When properly executed, the unlocking sequence clears the OPTLOCK bit and the Option bytes area is write-accessible. To lock the Option bytes area again, the software only needs to set OPTLOCK bit in FLASH_PECR. When relocked, OPTLOCK bit needs a new sequence to return to 0. If PELOCK returns to 1 (locked), OPTLOCK is automatically locked, too. Select between different types of operations When the necessary unlock sequence has been executed (PELOCK, PRGLOCK and OPTLOCK), the user can enable different types of write and erase operations, writing the right configuration in the FLASH_PECR register. The bits involved are: 75/874 PRG DATA FIX ERASE FPRG DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Detailed description of NVM write/erase operations This section details the different types of write and erase operations, showing the necessary bits for each one. Write to data EEPROM Purpose Write one word in the data EEPROM with a specific value. Size Write by byte, half-word or word. Address Select a valid address in the data EEPROM. Protocol Single programming operation. Requests PELOCK = 0, ERASE = 0. Errors WRPERR is set to 1 (and the write operation is not executed) if PELOCK = 1 or if the memory is read-out protected. Description This operation aims at writing a word or a part of a word in the data EEPROM. The user must write the right value at the right address and with the right size. The memory interface automatically executes an erase operation when necessary (if all bits are currently set to 0, there is no need to delete the old content before writing). Similarly, if the data to write is at 0, only the erase operation is executed. When only a write operation or an erase operation is executed, the duration is Tprog (3.2 ms); if both are executed, the duration is 2 x Tprog (6.4 ms). It is possible to force the memory interface to execute every time both erase and write operations set the FIX flag to 1. Duration Tprog (3.2 ms) or 2 x Tprog (6.4 ms). Options Set the FIX bit to force the memory interface to execute every time an erase (to delete the old content) and a write operation (to write new data) occur. This gives a fix time for the operation for any data value and for previous data. For code example, refer to A.3.5: Write to data EEPROM code example. DocID025942 Rev 5 76/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Erase data EEPROM Purpose Delete one row in data EEPROM. This operation performs the same function as Write a word which size is null to data EEPROM. It is available for compatibility purpose only. Size Erase only by word. Address Select one valid address in the data EEPROM. Protocol Single programming operation. Requests PELOCK = 0, ERASE = 1 (optional DATA = 1). Errors WRPERR is set to 1 if PELOCK = 1 or if the memory is read-out protected. SIZERR is set to 1 if the size is not a word. Description This operation aims at deleting the content of a row in the data EEPROM. A row contains only 1 word. The user must write a value at the right address with a word size. The data is not important: only an erase is executed (also with data different from zero). Duration Tprog (3.2 ms). For code example, refer to A.3.6: Erase to data EEPROM code example. Write Option bytes Purpose Write one word in the Option bytes area with a specific value. Size Write only by word. Address Select a valid address in the Option bytes area. Protocol Single programming operation. Requests PELOCK = 0, OPTLOCK = 0, ERASE = 0. Errors WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1. WRPERR is set to 1 if the actual read-out protection level is 2 (the Option bytes area cannot be written at Level 2). SIZERR is set to 1 if the size is not the word 77/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Description This operation aims at writing a word in the Option bytes area. The Option bytes area can only be written in Level 0 or Level 1. The user must consider that, in a word, the 16 higher bits (from 16 to 31) have to be the complement of the 16 lower bits (from 0 to 15): a mismatch between the higher and lower parts of data would generate an error during the Option bytes loading (see Section 3.8: Option bytes) and force the memory interface to load the default values. The memory interface does not check at the write time if the data is correctly complemented. The user must write the desired value at the right address with a word size. As for data EEPROM, the memory interface deletes the previous content before writing, if necessary. If the data to write is at 0, the memory interface does not execute the useless write operation. When only a write operation or only an erase operation is executed, the duration is Tprog (3.2 ms). If both are executed, the duration is 2 x Tprog (6.4 ms). The memory interface can be forced to execute every time both erase and write operations set the FIX flag to 1. Some configurations need a closer attention because they change the protections. The memory interface can change the Option bytes write in a Mass Erase or force some bits not to reduce the protections: for more details, see Section 3.4.4: Write/erase protection management. Duration Tprog (3.2 ms) or 2 x Tprog (6.4 ms). Options FIX bit can be set to force the memory interface to execute every time an erase (to delete the old content) and a write operation (to write the new data) occur. This gives a fix time to program for every data value and for previous data. For code example, refer to A.3.7: Program Option byte code example. DocID025942 Rev 5 78/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Erase Option bytes Purpose Delete one row in the Option bytes area. This operation performs the same function as Write Option Byte with a zero value. It is available for compatibility purpose only. Size Erase only by word. Address Select a valid address in the Option bytes area. Protocol Single programming operation. Requests PELOCK = 0, OPTLOCK = 0, ERASE = 1 (optional OPT = 1). Errors WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1. WRPERR is set to 1 if the actual protection level is 2 (the Option bytes area cannot be erased at Level 2). SIZERR is set to 1 if the size is not the word. Description This operation aims at deleting the content of a row in the Option bytes area. A row contains only 1 word. The use must write zero at the right address with a word size. Refer to Section : Write Option bytes for additional information. Since all bits are set to 0 after an erase operation, there will be a mismatch during the Option bytes loading and the default values will be loaded. Duration Tprog (3.2 ms). For code example, refer to A.3.8: Erase Option byte code example. 79/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Program a single word to Flash program memory Purpose Write one word in the Flash program memory with a specific value. Size Write only by word. Address Select an address in the Flash program memory. Protocol Single programming operation. Requests PELOCK = 0, PRGLOCK = 0. Errors WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1. WRPERR is set to 1 if the user tries to write in a write-protected sector (see the PcROP (Proprietary Code Read-Out Protection) section). NOTZEROERR is set to 1 if the user tries to write a value in a word which is not zero. This error does not stop the write operation on category 3 devices while the operation is stopped on other categories. SIZERR is set to 1 if the size is not a word. Description This operation allows writing a word in Flash program memory. The user must write the right value at the right address with a word size. The memory interface cannot execute an erase to delete the previous content before the write operation is performed. If the previous content is not null: – Category 3 devices NOTZEROERR is set to 1. The real value written in the memory is the OR of the previous value and the new value (the memory interface writes 1 when there was 0 before). This is done both for data and ECC. Reading back the data might not return the old value, the new one or the ORed values. The ECC is not compatible with the data any more. – Other categories NOTZEROERR is set to 1. Writing a word to an address containing a non-null value is not performed. Duration Tprog (3.2 ms). For code example, refer to A.3.9: Program a single word to Flash program memory code example. DocID025942 Rev 5 80/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Program half-page in Flash program memory Purpose Write one half page (16 words) in the Flash program memory. Size Write only by word. Address Select one address in the Flash program memory aligned to a half-page (for the first address) and inside the same half-page selected by the second address for the next 15 addresses. Protocol Multiple programming operation. Requests PELOCK = 0, PRGLOCK = 0, FPRG = 1, PRG = 1. Errors WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1. WRPERR is set to 1 if the user tries to write in a write-protected sector (see the PcROP (Proprietary Code Read-Out Protection) section). NOTZEROERR is set to 1 if the user tries to write a value in a word which is not zero. This error does not stop the write operation on category 3 devices while the operation is stopped on other categories. The check is done when all 16 addresses have been received, before the current write phase in Flash memory. The error flags are set only when all checks are performed. SIZERR is set to 1 if the size is not the word. PGAERR is set to 1 if the first address is not aligned to a half-page and if one of the following addresses (address from 2 to 16) is outside the half-page determined by the first address. No check is done to verify if the address has increased or if it has changed: this is done automatically by the memory interface. What is important is that the first address is aligned to the half-page, and that the next addresses are in the same half-page. FWWERR is set to 1 if the write is aborted because the master fetched in the NVM. The read as data does not stop the write operation. Description This operation allows writing a half-page in Flash program memory. The user must write the 16 desired values at the right address with a word size (as explained in the multiple programming operation). The memory interface cannot execute an erase to delete the previous content before writing (the user must delete the page before writing). As for the single programming operation, if the previous content is not null: – Category 3 devices NOTZEROERR is set to 1. The written value is the OR of previous and new data. This means that reading back the written address may return a value which is different from the written one. 81/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) – Other categories NOTZEROERR is set to 1. Writing a word to an address containing a non-null value is not performed. When a half-page operation starts, the memory interface waits for 16 addresses/data, aborting (with a hard fault) all read accesses that are not a fetch (refer to Fetch and prefetch). A fetch stops the half-page operation. The memory content remains unchanged, the FWWERR error is set in the FLASH_SR register. To complete the halfpage programming operation, all the desired values should be written again. Duration Tprog (3.2 ms). For code example, refer to A.3.10: Program half-page to Flash program memory code example. Parallel write half-page Flash program memory Purpose Write 2 half-pages (one per bank) in parallel in Flash program memory. Size Write only by word. Address For each half-page, one address, aligned to half-page start address, must be selected in Flash program memory. The following 15 addresses must point to the half-page selected by first address. Furthermore, the addresses of the second half-page must be on a different bank with respect to the start address of the first half-page (only the first address is checked). Protocol Multiple programming operation. Requests PELOCK = 0, PRGLOCK = 0, FPRG = 1, PRG = 1, PARALLELBANK=1. Errors This operation can generate the same kind of errors as program half-page in flash program memory. However, PGAERR is also generated when the second half-page selected is located in the same bank as the first half-page. All the errors detected during this operation abort the whole program operation (i.e. both banks). Description This operation programs in parallel one half-page on both Flash program memory banks. This speeds up the initial programming of the whole NVM. It is possible to start with Bank 1 or Bank 2. Duration Tprog (3.2 ms). DocID025942 Rev 5 82/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Erase a page in Flash program memory Purpose Delete one page (32 words) in the Flash program memory. Size Erase only by word (it deletes a page of the Flash program memory writing with a word size) Address Select a valid address in the Flash program memory. Protocol Single programming operation. Requests PELOCK = 0, PRGLOCK = 0, ERASE = 1, PRG = 1. Errors WRPERR is set to 1 if PELOCK = 1 or PRGLOCK = 1. WRPERR is set to 1 if the row is in a protected sector (see PcROP (Proprietary Code Read-Out Protection)). SIZERR is set to 1 if the size is not the word. Description This operation aims at deleting the content of a row in the Flash program memory. The user must write a value in the right address with a word size. The data is not important: only an erase is executed (also with data not at zero). The address does not need to be aligned to the page: the memory interface will delete the page which contents the address. Duration Tprog (3.2 ms). For code example, refer to A.3.11: Erase a page in Flash program memory code example. 83/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Mass erase Purpose Remove the read and write protection on the Flash program memory and data EEPROM. Size Erase only by word. Address To generate a mass erase, it is necessary to write 0x015500AA to the first Option bytes address (bits 31 to 25 and 15 to 9 are not complemented because they are not used, and not checked) with Level 1 as the actual level. Protocol Single programming operation. Requests PELOCK = 0, OPTLOCK = 0, Protection Level = 1, the lower nibble of data has to be 0xAA (Level 0), with 0x55 as the third nibble. Errors WRPERR is set to 1 if PELOCK = 1 or OPTLOCK = 1. WRPERR is set to 1 if the actual protection level is 2 (the Option bytes area cannot be written in Level 2). SIZERR is set to 1 if the size is not the word. Description This operation is similar to the write user Option byte operation: the memory interface changes it in a mass erase when the actual Protection Level is 1 and the requested Protection Level is 0. The user must write the desired value in the first address of the Option bytes area with a word size. A mass erase deletes the content of the Flash program memory and data EEPROM, changes the protection level to Level 0 and disables PcROP. (WPRMOD = 0). The bits write protection and BOR_LEVEL remain unchanged. Unlike all other operations, the software cannot request new writing operations while a mass erase is ongoing. To be sure that a mass erase has completed, the software can reset the EOP bit of FLASH_SR register before the write operation and check when EOP goes to 1 (End Of Program). If this limitation is not respected, a wrong value may be written in the Flash program memory and data EEPROM when the Protection Level is written, thus adding unwanted protections (also for mismatch) that could make the device useless. Duration 2 x Tprog (6.4 ms) + Tglob (3.7 ms) For code example, refer to A.3.12: Mass erase code example. DocID025942 Rev 5 84/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Timing tables Table 19. NVM write/erase timings Delay to latch the first address/data (in AHB clock pulses) Delay to latch the next address/data (in AHB clock pulses) Write to data EEPROM 18 - Erase data EEPROM 17 - Write Option bytes 18 - Erase Option bytes 17 - Program a single word in Flash program memory 78 - Program half-page in Flash program memory 63 6 Erase a page in Flash program memory 76 - Operation Table 20. NVM write/erase duration Operation Parameters/Conditions Duration Previous data = 0 FIX = 0 Tprog (3.2 ms) Previous data /= 0 New data = 0 Size = word FIX = 0 Tprog (3.2 ms) Other situations 2 x Tprog (6.4 ms) - Tprog (3.2 ms) Previous data = 0 FIX = 0 Tprog (3.2 ms) Previous data /= 0 New data = 0 FIX = 0 Tprog (3.2 ms) Other situations 2 x Tprog (6.4 ms) Erase Option bytes - Tprog (3.2 ms) Program a single word in Flash program memory - Tprog (3.2 ms) Program a half-page in Flash program memory - Tprog (3.2 ms) Erase a page in Flash program memory - Tprog (3.2 ms) Mass erase - 2 x Tprog (6.4 ms) + Tglob (3.7 ms) Write to data EEPROM Erase data EEPROM Write Option bytes 85/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Status register The FLASH_SR Status Register gives some information on the memory interface or the NVM status (operation(s) ongoing) and about errors that happened. BSY This flags is set and reset by hardware. It is set to 1 every time the memory interface executes a write/erase operation, and it informs that no other operation can be executed. If a new operation is requested, different behaviors can occur: Waiting for read, or waiting for write/erase, or waiting for option loading: If the software requests a write operation while a write/erase operation is executing (HVOFF = 0), the memory interface stalls the master and has the pending operation execute as soon as the write/erase operation is complete. Hard fault: If the software requests a data read in a half-page operation when the memory interface is waiting for the next address/data (BSY is already 1 but HVOFF = 0), the memory interface generates a hard fault (because it cannot execute the read) and continues to wait for missing addresses. RDERR error: If the software requests a read operation while a write/erase operation is executing (HVOFF = 0) but the address is protected, the memory interface rises the flag and continues to wait for the end of the write/erase operation. Write abort: If the software fetches in the NVM when the memory interface is waiting for an address/data in a half-page operation, the write/erase operation is aborted, the FWWERR flag is raised and the fetch is executed. EOP This flag is set by hardware and reset by software. The software can reset it writing 1 in the status register. This bit is set when the write/erase operation is completed and the memory interface can work on other operations (or start to work on pending operations). It is useful to clear it before starting a new write/erase operation, in order to know when the actual operation is complete. It is very important to wait for this flag to rise when a mass erase is ongoing, before requesting a new operation. HVOFF This flag is set and reset by hardware and it is a memory interface information copy coming from the NVM: it informs when the High-Voltage Regulators are on (= 0) or off (= 1). PGAERR This flag is set by hardware and reset by software. It informs when an alignment error happened. It is raised when: The first address in a half-page operation is not aligned to a half-page (lower 6 bits equal to zero). A half-page change happened in a half-page operation (the addresses from 2 to 16 in a half-page operation are not in the same half-page, selected by the first address). An alignment error aborts the write/erase operation and an interrupt can be generated (if ERRIE = 1 in the FLASH_PECR register). The content of the NVM is not changed. If this flag is set, the memory interface blocks all other half-page operations. DocID025942 Rev 5 86/874 114 Flash program memory and data EEPROM (FLASH) RM0377 To reset this flag, the software need to write it to 1. SIZERR This flag is set by hardware and reset by software. It informs when a size error happened. It is raised when: A write by byte and half-word occurs in the Flash program memory and Option bytes. An erase (with bit ERASE = 1 in FLASH_PECR register) by byte or half-word occurs in all areas. A size error aborts the write/erase operation and an interrupt can be generated (if ERRIE = 1 in the FLASH_PECR register). The content of the NVM is not changed. To reset this flag, the software needs to write it to 1. NOTZEROERR This flag is set by hardware and reset by software. It indicates that the application software is attempting to write to one or more NVM addresses that contain a non-zero value. Except for category 3 devices, the modify operation is always aborted when this condition is met. For category 3 devices, a not-zero error does not abort the write/erase operation but the value might be corrupted. In a write by half-page, all 16 words are checked between the first address/value and the second one, and the flag is only set when all words are checked. If the flag is set, it means that at least one word has an actual value not at zero. In a write by word, only the targeted word is checked and the flag is immediately set if the content is not zero. An interrupt is generated if ERRIE = 1 in FLASH_PECR register. To reset this flag, the application software needs to program it to 1. Note: Notification of a not-zero error condition (i.e. NOTZEROERR flag and the associated interrupt) can be disabled by the application software via the NZDISABLE bit in FLASH_PECR register. However, for all device except category 3 devices, the condition is still checked internally and modify operation is anyway blocked 3.4 Memory protection The user can protect part of the NVM (Flash program memory, data EEPROM and Option bytes areas) from unwanted write and against code hacking (unwanted read). Three types of protections are implemented. 87/874 DocID025942 Rev 5 RM0377 3.4.1 Flash program memory and data EEPROM (FLASH) RDP (Read Out Protection) This type of protection aims at protecting against unwanted read (hacking) of the NVM content. This protection is managed by RDPROT bitfield in the FLASH_OPTR register. The value is loaded from the Option bytes area during a boot and copied in the read-only register. Three protection levels are defined: Level 0: no protection Level 0 is set when RDPROT is set to 0xAA. When this level is enabled, and if no other protection is enabled, read and write can be done in the Flash program memory, data EEPROM and Option bytes areas without restrictions. It is also possible to read and write the backup registers freely. Level 1: memory read protection Level 1 is set when RDPROT is set to any value except 0xAA and 0xCC, respectively used for Level 0 and Level 2. This is the default protection level after an Option bytes erase or when there is a mismatch in the RDPROT field. The memory boot mode is saved internally if the device boot from RAM or from System Memory, or if the debugger (single-wire) is connected. This information is reset only by a power-down reset, by entering Standby mode (the system reset or the option loading is not sufficient) or when the device moves to Level 2. It protects the Flash program memory and data EEPROM. When protection Level 1 is set through boot from RAM, bootloader or debugger, a power-down or a standby is required to execute the user code. When this level is enabled: – No access to the Flash program memory and data EEPROM (read both for fetch and data and write) and no backup register reading is performed if the debug features (single-wire), or the device boot in the RAM, or the System memory is connected. If the user tries to read the Flash memory or data EEPROM, a hard fault is generated. No restriction is present on other areas: it is possible to read and write/erase the Option bytes area and to execute or read in the System Memory. – All operations are possible when the boot is done in the Flash program memory. – Writing the first Option byte with a value that changes the protection level to Level 0 (it is necessary that byte 0 is 0xAA and byte 2 is 0x55), a mass erase is generated. The mass erase deletes the Flash program memory and data EEPROM, deletes the first Option byte and then rewrites it to enable Level 0 and disable PCROP (WPRMOD = 0), and deletes the backup registers content. Level 2: disable debug and chip read protection Level 2 is set when RDPROT is set to 0xCC. When this level is enabled, it is only possible to boot from the Flash program memory, and the debug features (single-wire) are disabled. The Option bytes are protected against write/erase and the protection level can no longer be changed. The application can write/erase to the Flash program memory and data EEPROM (it is only possible to boot from the Flash program memory and execute the customer code) and access the backup registers. When an Option bytes loading is executed and Level 2 is enabled, old information on debug or boot in the RAM or System memory are deleted. Figure 6 resumes the way the protection level can be changed and Table 21 the link between the values read in the Option bytes and the protection level. DocID025942 Rev 5 88/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Figure 6. RDP levels :ULWH 5'3 [&& /HYHO 5'3 [$$ 5'3 [&& GHIDXOW :ULWH 5'3 [$$DQG 5'3 [&& :ULWH 5'3 [$$ 0DVVHUDVH :ULWH 5'3 [&&DQG 5'3 [$$ /HYHO /HYHO 5'3 [&& :ULWH 5'3 [&& 5'3 [$$ :ULWH 5'3 [$ 5'3GHFUHDVH 5'3LQFUHDVH 5'3XQFKDQJHG -36 Table 21. Protection level and content of RDP Option bytes RDP byte value RDP complementary value Read Protection status 0xAA 0x55 Level 0 0xCC 0x33 Level 2 Any other value Complement of RDP byte Level 1 Any value Not the complement value of RDP byte Level 1 3.4.2 PcROP (Proprietary Code Read-Out Protection) The Flash program memory can be protected from being read by a hacking code: the read data are blocked (not for a fetch). The protected code must not access data in the protected zone, including the literal pool. The Flash program memory can be protected against a hacking code read: this blocks the data read (not for a fetch), assuming that the native code is compiled according to the PcROP option. This mode is activated setting WPRMOD = 1 in the FLASH_OPTR register. The protection granularity is the sector (1 sector = 32 pages = 4 KB). To protect a sector, set to 0 the right bit in the WRPROT configuration: 0 means read and write protection, 1 means no protection. Table 22 shows the link between the bits of the WRPROT configuration and the address of the Flash memory sectors. 89/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Any read access performed as data (see Read as data and pre-read) in a protected sector will trigger the RDERR flag in the FLASH_SR register. Any read-protected sector is also write-protected and any write access to one of these sectors will trigger the WRPERR flag in the FLASH_SR register. Table 22. Link between protection bits of FLASH_WRPROTx register and protected address in Flash program memory(1) Bit Start address End address Bit Start address End address 0 0x0800 0000 0x0800 0FFF 24 0x0801 8000 0x0801 8FFF 1 0x0800 1000 0x0800 1FFF 25 0x0801 9000 0x0801 9FFF 2 0x0800 2000 0x0800 2FFF 26 0x0801 A000 0x0801 AFFF 3 0x0800 3000 0x0800 3FFF 27 0x0801 B000 0x0801 BFFF 4 0x0800 4000 0x0800 4FFF 28 0x0801 C000 0x0801 CFFF 5 0x0800 5000 0x0800 5FFF 29 0x0801 D000 0x0801 DFFF 6 0x0800 6000 0x0800 6FFF 30 0x0801 E000 0x0801 EFFF 7 0x0800 7000 0x0800 7FFF 31 0x0801 F000 0x0801 FFFF 8 0x0800 8000 0x0800 8FFF 32 0x0802 0000 0x0802 0FFF 9 0x0800 9000 0x0800 9FFF 33 0x0802 1000 0x0802 1FFF 10 0x0800 A000 0x0800 AFFF 34 0x0802 2000 0x0802 2FFF 11 0x0800 B000 0x0800 BFFF 35 0x0802 3000 0x0802 3FFF 12 0x0800 C000 0x0800 CFFF 36 0x0802 4000 0x0802 4FFF 13 0x0800 D000 0x0800 DFFF 37 0x0802 5000 0x0802 5FFF 14 0x0800 E000 0x0800 EFFF 38 0x0802 6000 0x0802 6FFF 15 0x0800 F000 0x0800 FFFF 39 0x0802 7000 0x0802 7FFF 16 0x0801 0000 0x0801 0FFF 40 0x0802 8000 0x0802 8FFF 17 0x0801 1000 0x0801 1FFF 41 0x0802 9000 0x0802 9FFF 18 0x0801 2000 0x0801 2FFF 42 0x0802 A000 0x0802 AFFF 19 0x0801 3000 0x0801 3FFF 43 0x0802 B000 0x0802 BFFF 20 0x0801 4000 0x0801 4FFF 44 0x0802 C000 0x0802 CFFF 21 0x0801 5000 0x0801 5FFF 45 0x0802 D000 0x0802 DFFF 22 0x0801 6000 0x0801 6FFF 46 0x0802 E000 0x0802 EFFF 23 0x0801 7000 0x0801 7FFF 47 0x0802 F000 0x0802 FFFF 1. Bits 0 to 3 apply to category 1 devices only, bits 0 to 7 apply to category 2, and bits 0 to 15 to category 3. When WPRMOD = 1 (PcROP enabled), it is not possible to reduce the protection on a sector: new zeros (to protect new sectors) can be set, but new ones (to remove the protection from sectors) cannot be added. This is valid regardless of the protection level (RDPROT configuration). When WPRMOD is active, if the user tries to reset WPRMOD or to remove the protection from a sector, the programming is launched but WPRMOD or protected sectors remain unchanged. DocID025942 Rev 5 90/874 114 Flash program memory and data EEPROM (FLASH) RM0377 The only way to remove a protection from a sector is to request a mass erase (which changes the protection level to 0 and disables PcROP): when PcROP is disabled, the protection on sectors can be changed freely. 3.4.3 Protections against unwanted write/erase operations The memory interface implements two ways to protect against unwanted write/erase operations which are valid for all matrix or only for specific sectors of the Flash program memory. As explained in the Unlocking/locking operations section, the user can: Write/erase to the data EEPROM only when PELOCK = 0 in the FLASH_PECR register. Write/erase to the Option bytes area only when PELOCK = 0 and OPTLOCK = 0 in the FLASH_PECR register. Write/erase to the Flash program memory only when PELOCK = 0 and PRGLOCK = 0 in the FLASH_PECR register. To see the sequences to set PELOCK, PRGLOCK and OPTLOCK, refer to the Unlocking the data EEPROM and the FLASH_PECR register, Unlocking the Flash program memory and Unlocking the Option bytes area sections. In the Flash program memory, it is possible to add another write protection with the sector granularity. When PcROP is disabled (WPRMODE = 0), the bits of WRPROT are used to enable the write protection on the sectors. The polarity is opposed relatively to PcROP: to protect a sector, it is necessary to set the bit to 1; to remove the protection, it is necessary to set the bit to 0. Table 22 is valid for a write protection as well. As explained, when PcROP is enabled, the sectors protected against read are also protected against write/erase. It is always possible to change the write protection on sectors both in Level 0 and Level 1 (provided that it is possible to write/erase to Option bytes and that PcROP is disabled). Table 23 resumes the protections. Table 23. Memory access vs mode, protection and Flash program memory sectors Mode Flash program memory sectors User (including In Application Programming) no Debug, or no Boot in RAM, or no Boot in System memory User in Debug, or with Boot in RAM, or with Boot in System memory RDP Level 1 Level 0 Level 2 Level 0 Level 1 Level 2 Flash program memory (FLASH_PRGLOCK = 1) R R R Protected (no access) NA(1) Flash memory (FLASH_PRLOCK = 0) R/W R/W R/W Protected (no access) NA(1) Flash program memory in WRP pages R R R Protected (no access) NA(1) 91/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Table 23. Memory access vs mode, protection and Flash program memory sectors (continued) Mode Flash program memory sectors User (including In Application Programming) no Debug, or no Boot in RAM, or no Boot in System memory User in Debug, or with Boot in RAM, or with Boot in System memory RDP Level 1 Level 0 Level 2 Level 0 Level 1 Level 2 Flash program memory in PCROP pages Fetch Fetch Fetch Protected (no access) NA(1) Data EEPROM (FLASH_PELOCK = 1) R R R Protected (no access) NA(1) Data EEPROM (FLASH_PELOCK = 0) R/W R/W R/W Protected (no access) NA(1) Option bytes (FLASH_OPTLOCK = 1) R R R R NA(1) Option bytes (FLASH_OPTLOCK = 0) R/W R R/W R/W NA(1) 1. NA stands for “not applicable”. 3.4.4 Write/erase protection management Here is a summary of the rules to change all previous protections: When the protection Level is 2, no protection change can be done. When in Level 0 or 1, it is always possible to move to Level 2, writing xx33xxCC (the x are the hexadecimal digits that can have any value) in the first Option byte word. When in Level 0, it is possible to move to Level 1, writing any value in the first Option byte word that is not xx33xxCC (Level 2) or xx55xxAA (Level 0). when in Level 1, the protection can be reduced to Level 0, writing xx55xxAA in the first Option byte word. This generates a mass erase and deletes the PcROP field too. It is always possible to enable PcROP (except in Level 2), writing x0xxx1xx in the first Option byte word. If there is a mismatch during an Option byte loading on this flag, PcROP is enabled. PcROP can be removed on requesting a mass erase (move from Level 1 to Level 0). When PcROP is disabled, a write protection can be added on sectors (writing 1) or removed (writing 0) in the third word of the Option bytes. A mismatch concerns all write-protected sectors (if PcROP is disabled). When PcROP is enabled, protected sectors can be added (writing 0) but cannot be removed. A mismatch concerns all read- and write-protected sectors (if PcROP is enabled). A mass erase does not delete the third word of the Option bytes: the user must write it correctly. DocID025942 Rev 5 92/874 114 Flash program memory and data EEPROM (FLASH) 3.4.5 RM0377 Protection errors Write protection error flag (WRPERR) If an erase/program operation to a write-protected page of the Flash program memory and data EEPROM is launched, the Write Protection Error flag (WRPERR) is set in the FLASH_SR register. Consequently, the WRPERR flag is set when the software tries to: Write to a WRP page. Write to a System memory page or to factory option bytes. Write to the Flash program memory, data EEPROM or Option bytes if they are not unlocked by PEKEY, PRGKEY or OPTKEY. Write to the Flash program memory, data EEPROM or Option bytes when the RDP Option byte is set and the device is in debug mode or is booting from the RAM or from the System memory. A write-protection error aborts the write/erase operation and an interrupt can be generated (if ERRIE = 1 in the FLASH_PECR register). To reset this flag, the software needs to write it to 1. Read error (RDERR) If the software tries to read a sector protected by PcROP, the RDERR flag of FLASH_SR is raised. The data received on the bus is at 0. If the error interrupt is enabled (ERRIE = 1 in the FLASH_PECR register), an interrupt is generated. To reset this flag, the software needs to write it to 1. 3.5 NVM interrupts Setting the End of programming interrupt enable bit (EOPIE) in the FLASH_PECR register enables an interrupt generation when an erase or a programming operation ends successfully. In this case, the End of programming (EOP) bit in the FLASH_SR register is set. To reset it, the software needs to write it to 1. Setting the Error interrupt enable bit (ERRIE) in the FLASH_PECR register enables an interrupt generation if an error occurs during a programming or an erase operation request. In this case, one or several error flags are set in the FLASH_SR register: RDERR (PCROP Read protection error flags) WRPERR (Write protection error flags) PGAERR (Programming alignment error flag) OPTVERR (Option validity error flag) SIZERR (Size error flag) FWWERR (Fetch while write error flag) NOTZEROERR (Write a not zero word error flag) To reset the error flag, the software needs to write the right flag to 1. 93/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Table 24. Flash interrupt request Interrupt event Event flag Enable control bit EOP EOPIE RDERR WRPERR PGAERR OPTVERR SIZERR FWWERR NOTZEROERR ERRIE End of operation Error 3.5.1 Hard fault A hard fault is generated on: 3.6 The memory bus if a read access is attempted when RDP is set. The memory bus if a read as data is received; then, the memory interface is waiting for a data/address during a half-page write (after the 1st address and before the 16th address). The register bus if an incorrect value is written in PEKEYR, PRGKEYR, or OPTKEYR. Memory interface management The purpose of this section is to clarify what happens when one operation is requested while another is ongoing: the way the different operations work together and are managed by the memory interface. 3.6.1 Operation priority and evolution There are three types of operations and each of them has different flows: Read If no operation is ongoing and the read address is not protected, the read is executed without delays and with the actual configurations. If the read address is protected, the operation is filtered (the read requested is never sent to the memory) and an error is raised. If the read address is not protected but the memory interface is busy and cannot perform the operation, the read is put on hold to be executed as soon as possible. DocID025942 Rev 5 94/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Write/erase If no operation is ongoing and the write address is not protected, the write/erase will start immediately; after some clock pulses (see Table 19) during which the bus and the master are blocked, the memory interface continues the operation freeing the bus and the master. If the address is protected, the write/erase is filtered (the write/erase requested is never sent to the memory) and an error is raised. If the address is not protected but one or several conditions are not met, the operation is aborted (the abort needs more time to be executed because the NVM and data EEPROM need to return to default configuration) and an error is raised. If the address to write/erase is not protected and all rules are respected, and if the memory interface is busy, the operation is put on hold to be executed as soon as possible. Option byte loading If a write/erase is ongoing, the Option byte loading waits for the end of operation then it is executed: no other write/erase is accepted, even if waiting. If no write/erase is ongoing, the Option byte is executed directly (the read operation is executed until the system reset goes to 0 as a result of the Option byte request). This means that the Option byte loading has a bigger priority than the read and write/erase operations. All other operations are executed in the order of request. 3.6.2 Sequence of operations The following description does not apply when one of the operation is made on one bank and the other in another bank using to the read-while-write feature of category 5 devices. Read as data while write If the master requests a read as data (see Read as data and pre-read) while a write operation is ongoing, there are three different cases: 95/874 1. If the read is in a protected area, the RDERR flag is raised and the write operation continues. 2. If the write operation uses a Single programming operation or a Multiple programming operation (half page) and all addresses/data have been sent to the memory interface, the read is put on hold and will be executed when the write operation is complete. It is important to emphasize that, during all the time spent when the read waits to be executed, the master is blocked and no other operation can be executed until the write and read operations are complete. 3. if the write operation uses a Multiple programming operation (half page) and not all addresses/data have been sent to the memory interface, the read is not accepted, a hard fault is generated and the memory interface continues to wait for the missing addresses/data to complete the write operation. DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Fetch while write If the master fetches an instruction while a write is ongoing, the situation is similar to a read as data (see 1. and 2.), but the last case is as follows: If the write operation uses a Multiple programming operation (half page) and not all addresses/data have been sent to the memory interface, the write is aborted and it is as it had never happened: the read is accepted and the value is sent to the master. Write while another write operation is ongoing If the master requests a write operation while another one is ongoing, there are different cases: 3.6.3 If the previous write uses a Single programming operation or a Multiple programming operation (half page) and all addresses/data have been sent to the memory interface, and if the new write is in a protected area, the WRPERR flag is raised, the previous write continues and the new write is deleted. If the previous write uses a Single programming operation or a Multiple programming operation (half page) and all addresses/data have been sent to the memory interface, and if the new Single programming operation or Multiple programming operation (half page) is not in a protected area, the new write is put on hold and will be executed when the first write operation is complete. It is important to emphasize that the master who requested the second write is blocked until the first write completes and the second has stored the address and data internally. It is forbidden to request a new write when a mass erase is ongoing: during all the steps of the mass erase, the data is not stored internally and the new data can change the value stored as a protection, adding unwanted protections. It is possible to change configurations to prepare a new write operation when the first operation uses a Single programming operation or a Multiple programming operation (half page) and all addresses/data have been sent to the memory interface. Change the number of wait states while reading To change the number of wait states, it is necessary to write to the FLASH_ACR register. The read/write of a register uses a different interface than the memory read/write. The number of wait states cannot be changed while the memory interface is reading and the memory interface cannot be stopped if a request is sent to the register interface. For this reason, while a master is reading the memory and another master changes the wait state number, the register interface will be locked until the change takes effect (until the readings stop). To stop the master which is changing the number of wait states, it is important to read back the content of the FLASH_ACR register: it is not possible to know the number of clock cycles that will be necessary to change the number of wait states as it depends on the customer code. DocID025942 Rev 5 96/874 114 Flash program memory and data EEPROM (FLASH) 3.6.4 RM0377 Power-down To put the NVM in power-down, it is necessary to execute an unlocking sequence. The following sequence is used to unlock RUN_PD bit of the FLASH_ACR register: Write PDKEY1 = 0x04152637 to the FLASH_PDKEYR register. Write PEKEY2 = 0xFAFBFCFD to the FLASH_PDKEYR register. It is necessary to write the two keys without constraints about other read or write. No error is generated if the wrong key is used: when both have been written, RUN_PD bit is unlocked and can be written to 1, putting the NVM in power-down mode. Resetting the RUN_PD flag to 0 (making the NVM available) automatically resets the sequence and the two keys are requested to re-enable RUN_PD. 97/874 DocID025942 Rev 5 RM0377 3.7 Flash program memory and data EEPROM (FLASH) Flash register description Read registers To read all internal registers of the memory interface, the user must read at the register addresses. The content is available immediately (no wait state is necessary to read registers). If the user tries to read the FLASH_ACR register after modifying the number of wait states, the content will be available when the change takes effect (when no read is done in the NVM memory, so the number of wait states is changed). When no register is selected or when a wrong address is sent to the memory interface, a zero value is sent as an answer. No error is generated. When the master sends a request to read 8 or 16 bits, the memory interface returns the corresponding part of the register on the data output bus. For example, if a register content is 0x12345678 and the master sends a request to read the second byte, the output will be 0x34343434 (because 0x34 is the content of the second register byte when starting to count bytes from zero). Similarly, if the master sends a request to read half-word zero of the previous register, the output will be 0x56785678. Write to registers In the configuration registers of the memory interface, there are two types of bits: the bits that can be written to directly the bits needing a particular sequence to unlock. To know which category a bit belongs to, see the next sections where every bit is explained in details. When it is possible to write directly to a register or a key-register, the user must write the expected value at the register address. If the address is not correct, no error is generated. If the user tries to modify a read-only register, no error is generated and the modify operation does not take any effect. It is possible to write registers by byte, half-word and word. When an unlock sequence is necessary, the correct values to use are given. DocID025942 Rev 5 98/874 114 Flash program memory and data EEPROM (FLASH) 3.7.1 RM0377 Access control register (FLASH_ACR) Address offset: 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. PRE_READ DISAB_BUF RUN_PD SLEEP_PD Res. PRFTEN LATENCY Reset value: 0x0000 0000 rw rw rw rw rw rw Bits 31:7 Reserved, must be kept at reset value Bit 6 PRE_READ This bit enables the pre-read. 0: The pre-read is disabled 1: The pre-read is enabled. The memory interface stores the last address read as data and tries to read the next one when no other read or write or prefetch operation is ongoing. Note: It is automatically reset every time the DISAB_BUF bit (in this register) is set to 1. Bit 5 DISAB_BUF This bit disables the buffers used as a cache during a read. This means that every read will access the NVM even for an address already read (for example, the previous address). When this bit is reset, the PRFTEN and PRE_READ bits are automatically reset, too. 0: The buffers are enabled 1: The buffers are disabled. Every time one NVM value is necessary, one new memory read sequence has do be done. Bit 4 RUN_PD This bit determines if the NVM is in power-down mode or in idle mode when the device is in run mode. It is possible to write this bit only when there is an unlocked writing of the FLASH_PDKEYR register. The correct sequence is explained in Section 3.6.4: Power-down. When writing this bit to 0, the keys are automatically lost and a new unlock sequence is necessary to re-write it to 1. 0: When the device is in Run mode, the NVM is in Idle mode. 1: When the device is in Run mode, the NVM is in power-down mode. Bit 3 SLEEP_PD This bit allows to have the Flash program memory and data EEPROM in power-down mode or in idle mode when the device is in Sleep mode. 0: When the device is in Sleep mode, the NVM is in Idle mode. 1: When the device is in Sleep mode, the NVM is in power-down mode. 99/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Bit 2 Reserved, must be kept at reset value Bit 1 PRFTEN This bit enables the prefetch. It is automatically reset every time the DISAB_BUF bit (in this register) is set to 1. To know how the prefetch works, see the Fetch and prefetch section. 0: The prefetch is disabled. 1: The prefetch is enabled. The memory interface stores the last address fetched and tries to read the next one when no other read or write operation is ongoing. Bit 0 LATENCY The value of this bit specifies if a 0 or 1 wait-state is necessary to read the NVM. The user must write the correct value relative to the core frequency and the operation mode (power). The correct value to use can be found in Table 15. No check is done to verify if the configuration is correct. To increase the clock frequency, the user has to change this bit to ‘1’, then to increase the frequency. To reduce the clock frequency, the user has to decrease the frequency, then to change this bit to ‘0’. 0: Zero wait state is used to read a word in the NVM. 1: One wait state is used to read a word in the NVM. 3.7.2 Program and erase control register (FLASH_PECR) Address offset: 0x04 Reset value: 0x0000 0007 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. FIX Res. Res. Res. DATA PROG OPT_LOCK PRG_LOCK PE_LOCK rw ERASE rw FPRG rw PARRALELBANK rw EOPIE 29 ERRIE 30 OBL_LAUNCH 31 NZDISABLE This register can only be written after a good write sequence done in FLASH_PEKEYR, resetting the PELOCK bit. rw rw rw rw rw rs rs rs rw DocID025942 Rev 5 100/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Bits 31:24 Reserved, must be kept at reset value Bit 23 NZDISABLE: Non-Zero check notification disable When this bit is set, the application software does not check if the previous NVM content is zero before programming a word or an half-page in the program or boot area. As a result, the NOTZEROERR flag will always remain at 0 and no interrupt will be generated if the above condition is met. By default, NZDISABLE is set to 0. It can be modified only when PELOCK is 0. 0: error interrupt disabled 1: error interrupt enabled On category 3 devices, this bit is not available and the behavior corresponds to NZDISABLE=0. Bits 22:19 Reserved, must be kept at reset value Bit 18 OBL_LAUNCH Setting this bit, the software requests the reloading of Option byte. The Option byte reloading does not stop an ongoing modify operation, but it blocks new ones. The Option byte reloading generates a system reset. 0: Option byte loading completed. 1: Option byte loading to be done. Note: This bit can only be modified when OPTLOCK is 0. Locking OPTLOCK (or other lock bits) does not reset this bit. Bit 17 ERRIE: Error interrupt enable 0: Error interrupt disable. 1: Error interrupt enable. Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this bit; the interrupt remains enabled. Bit 16 EOPIE: End of programming interrupt enable 0: End of program interrupt disable. 1: End of program interrupt enable. Note: This bit can only be modified when PELOCK is 0. Locking PELOCK does not reset this bit; the interrupt remains enabled. Bit 15 PARALLELBANK: Parallel bank programming mode. This bit can be set and cleared by software when no program or erase operation is ongoing. When it is set, 2 half-pages can be programmed, the first one in Bank 1 and the second one in Bank 2. 0: Parallel bank mode disabled 1: Parallel bank mode enabled This bit is available only for category 5 devices. Bits 14:11 Reserved, must be kept at reset value Bit 10 FPRG: Half Page programming mode 0: Half Page programming disabled. 1: Half Page programming enabled. Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set. Bit 9 ERASE 0: No erase operation requested. 1: Erase operation requested. Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set. 101/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) Bit 8 FIX 0: An erase phase is automatically performed, when necessary, before a program operation in the data EEPROM and the Option bytes areas. The programming time can be: Tprog (program operation) or 2 * Tprog (erase + program operations). 1: The program operation is always performed with a preliminary erase and the programming time is: 2 * Tprog. Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set. Bits 7:5 Reserved, must be kept at reset value Bit 4 DATA 0: Data EEPROM not selected. 1: Data memory selected. Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set.This bit is not very useful as the page and word have the same size in the data EEPROM, but it is used to identify an erase operation (by page) from a word operation. Bit 3 PROG This bit is used for half-page program operations and for page erase operations in the Flash program memory. 0: The Flash program memory is not selected. 1: The Flash program memory is selected. Note: This bit can be modified when PELOCK is 0. It is reset when PELOCK is set. DocID025942 Rev 5 102/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Bit 2 OPTLOCK: Option bytes lock This bit blocks the write/erase operations to the user Option bytes area and the OBL_LAUNCH bit (in this register). It can only be written to 1 to re-lock. To reset to 0, a correct sequence of unlock with OPTKEYR register is necessary (see Unlocking the Option bytes area), with PELOCK bit at 0. If the sequence is not correct, the bit will be locked until the next system reset and a hard fault is generated. If the sequence is executed when PELOCK = 1, the bit remains locked and no hard fault is generated. The keys to unlock are: – First key:0xFBEAD9C8 – Second key: 0x24252627 0: The write and erase operations in the Option bytes area are disabled. 1: The write and erase operations in the Option bytes area are enabled. Note: This bit is set when PELOCK is set. Bit 1 PRGLOCK: Program memory lock This bit blocks the write/erase operations to the Flash program memory. It can only be written to 1 to re-lock. To reset to 0, a correct sequence of unlock with PRGKEYR register is necessary (see Unlocking the Flash program memory), with PELOCK bit at 0. If the sequence is not correct, the bit will be locked until the next system reset and a hard fault is generated. If the sequence is executed when PELOCK = 1, the bit remains locked and no hard fault is generated. The keys to unlock are: – First key:0x8C9DAEBF – Second key: 0x13141516 0: The write and erase operations in the Flash program memory are disabled. 1: The write and erase operations in the Flash program memory are enabled. Note: This bit is set when PELOCK is set. Bit 0 PELOCK: FLASH_PECR lock This bit locks the FLASH_PECR register. It can only be written to 1 to re-lock. To reset to 0, a correct sequence of unlock with PEKEYR register (see Unlocking the data EEPROM and the FLASH_PECR register) is necessary. If the sequence is not correct, the bit will be locked until the next system reset and one hard fault is generated. The keys to unlock are: – First key: 0x89ABCDEF – Second key: 0x02030405 0: The FLASH_PECR register is unlocked; it can be modified and the other bits unlocked. Data write/erase operations are enabled. 1: The FLASH_PECR register is locked and no write/erase operation can start. 103/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) 3.7.3 Power-down key register (FLASH_PDKEYR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FLASH_PDKEYR[31:16] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w w w w w w w FLASH_PDKEYR15:0] Bits 31:0 3.7.4 w w This is a write-only register. With a sequence of two write operations (the first one with 0x04152637 and the second one with 0xFAFBFCFD), the write size being that of a word, it is possible to unlock the RUN_PD bit of the FLASH_ACR register. For more details, refer to Section 3.6.4: Power-down. PECR unlock key register (FLASH_PEKEYR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 w w w w w w w w 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 w w w w w w w w 7 6 5 4 3 2 1 0 w w w w w w w FLASH_PEKEYR[31:16] FLASH_PEKEYR15:0] w w w w w w w w w Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with 0x89ABCDEF and the second one with 0x02030405), the write size being that of a word, it is possible to unlock the FLASH_PECR register. For more details, refer to Unlocking the data EEPROM and the FLASH_PECR register. 3.7.5 Program and erase key register (FLASH_PRGKEYR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FLASH_PRGKEYR[31:16] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w FLASH_PRGKEYR15:0] w w w w w w w w w Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with 0x8C9DAEBF and the second one with 0x13141516), the write size being that of a word, it is possible to unlock the Flash program memory. The sequence can only be executed when PELOCK is already unlocked. For more details, refer to Unlocking the Flash program memory. DocID025942 Rev 5 104/874 114 Flash program memory and data EEPROM (FLASH) 3.7.6 RM0377 Option bytes unlock key register (FLASH_OPTKEYR) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 FLASH_OPTKEYR[31:16] w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w w w w w w w w FLASH_OPTKEYR[15:0] w w Bits 31:0 This is a write-only register. With a sequence of two write operations (the first one with 0xFBEAD9C8 and the second one with 0x24252627), the write size being that of a word, it is possible to unlock the Option bytes area and the OBL_LAUNCH bit. The sequence can only be executed when PELOCK is already unlocked. For more details, refer to Unlocking the Option bytes area. 105/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) 3.7.7 Status register (FLASH_SR) Address offset: 0x018 26 25 24 23 22 21 20 19 18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. OPTVERR SIZERR PGAERR WRPERR Res. Res. Res. Res. READY rc_w1 rc_w1 rc_w1 rc_w1 r rc_w1 17 16 NOTZERO ERR 27 rc_w1 rc_w1 1 0 BSY 28 FWWER 29 EOP 30 ENDHV 31 RDERR Reset value: 0x0000 000C r rc_w1 r Bits 31:18 Reserved, must be kept at reset value Bit 17 FWWERR This bit is set by hardware when a write/erase operation is aborted to perform a fetch. This is not a real error, but it is used to inform that the write/erase operation did not execute. To reset this flag, write 1. 0: No write/erase operation aborted to perform a fetch. 1: A write/erase operation aborted to perform a fetch. Bit 16 NOTZEROERR This bit is set by hardware when a program in the Flash program or System Memory tries to overwrite a not-zero area. In category 3 devices, this flag does not stop the program operation: it is possible that the value found when reading back is not what the user wrote. To reset this flag, write 1. 0: The write operation is done in an erased region or the memory interface can apply an erase before a write. 1: The write operation is attempting to write to a not-erased region and the memory interface cannot apply an erase before a write. Except for category 3 devices, the modify operation is aborted. For category 3 devices a not-zero error does not abort the write/erase operation. Bit 15:14 Reserved, must be kept at reset value Bit 13 RDERR This bit is set by hardware when the user tries to read an area protected by PcROP. It is cleared by writing 1. 0: No read protection error happened. 1: One read protection error happened. Bit 12 Reserved, must be kept at reset value Bit 11 OPTVERR: Option valid error This bit is set by hardware when, during an Option byte loading, there was a mismatch for one or more configurations. It means that the configurations loaded may be different from what the user wrote in the memory. It is cleared by writing 1. If an error happens while loading the protections (WPRMOD, RDPROT, WRPROT), the source code in the Flash program memory may not execute correctly. 0: No error happened during the Option bytes loading. 1: One or more errors happened during the Option bytes loading. DocID025942 Rev 5 106/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Bit 10 SIZERR: Size error This bit is set by hardware when the size of data to program is not correct. It is cleared by writing 1. 0: No size error happened. 1: One size error happened. Bit 9 PGAERR: Programming alignment error This bit is set by hardware when an alignment error has happened: the first word of a half-page operation is not aligned to a half-page, or one of the following words in a half-page operation does not belong to the same half-page as the first word. When this bit is set, it has to be cleared before writing 1, and no half-page operation is accepted. 0: No alignment error happened. 1: One alignment error happened. Bit 8 WRPERR: Write protection error This bit is set by hardware when an address to be programmed or erased is write-protected. It is cleared by writing 1. 0: No protection error happened. 1: One protection error happened. Bit 7:4 Reserved, must be kept at reset value Bit 3 READY When this bit is set, the NVM is ready for read and write/erase operations. 0: The NVM is not ready. No read or write/erase operation can be done. 1: The NVM is ready. Bit 2 ENDHV This bit is set and reset by hardware. 0: High voltage is executing a write/erase operation in the NVM. 1: High voltage is off, no write/erase operation is ongoing. Bit 1 EOP: End of program This bit is set by hardware at the end of a write or erase operation when the operation has not been aborted. It is reset by software (writing 1). 0: No EOP operation occurred 1: An EOP event occurred. An interrupt is generated if EOPIE bit is set. Bit 0 BSY: Memory interface busy Write/erase operations are in progress. 0: No write/erase operation is in progress. 1: A write/erase operation is in progress. 107/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) 3.7.8 Option bytes register (FLASH_OPTR) Address offset 0x1C Reset value: 0xX0XX 0XXX. It depends on the value programmed in the option bytes. During production, it is set to 0x8070 00AA. 22 21 20 Res. Res. Res. Res. Res. r r 15 14 13 12 11 10 9 8 Res. Res. Res. Res. Res. Res. Res. r 18 17 16 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r RDPROT r 19 BOR_LEV[3:0] 23 WDG_SW 24 nRTS_STOP 25 nRST_STDBY 26 BFB2 27 WPRMOD 28 nBOOT_SEL 29 nBOOT0 30 nBOOT1 31 Bit 31 nBOOT1 This bit is used in conjunction with BOOT0 signal to configure the device boot mode (see Section 2.4: Boot configuration). If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1. If the device is protected at Level 2, BOOT0 and nBOOT1 lose their meaning: the boot is always forced in the Flash program memory. Bit 30 nBOOT0 This bit is available on category 1 devices only. When nBOOT_SEL is cleared, nBOOT0 bit defines the value of BOOT0 signal that is used to select the device boot mode (see Section 2.4: Boot configuration). Bit 29 nBOOT_SEL 0: BOOT0 signal is defined by BOOT0 pin value (default mode) 1: BOOT0 signal is defined by nBOOT0 option bit This bit is available on category 1 devices only. It is held at ‘0’ on other devices. Bits 28:24 Reserved, must be kept at reset value Bit 23 BFB2: Boot from Bank 2 This bit contains the user option byte loaded by the device OPTL. This bit is used to boot from Bank 2. Actually this bit indicates whether a boot from System memory or from Flash program memory has been selected. If boot from System memory is selected, the jump to Bank 1 or Bank 2 is performed by software depending on the value of the first two words at the beginning of each bank. When BFB2 is set, user Flash memory is not aliased at address 0. Instead, the System Flash memory is aliased at address 0 through MEM_MODE bits in SYSCFG_CFGR1. When BFB2 is set, the PRIMASK is set at code startup. It prevents the activation of all exceptions that have a configurable priority. 0: BOOT from Bank 1 (category 5 devices) or USER Flash memory (other categories) 1: BOOT from System memory Note: This bit is available in category 5 devices only. Bit 22 nRST_STDBY If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1. 0: Reset generated when entering the Standby mode. 1: No reset generated. DocID025942 Rev 5 108/874 114 Flash program memory and data EEPROM (FLASH) RM0377 Bit 21 nRST_STOP If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1. 0: Reset generated when entering the Stop mode. 1: No reset generated. Bit 20 WDG_SW If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1. 0: Hardware watchdog. 1: Software watchdog. Bit 19:16 BOR_LEV: Brown out reset threshold level These bits reset the threshold level for a 1.45 V to 1.55 V voltage range (power-down only). In this particular case, VDD must have been above VBOR0 to start the device OBL sequence, in order to disable the BOR. The power-down is then monitored by the PDR. If the BOR is disabled, a “grey zone” exists between 1.65 V and the VPDR threshold (this means VDD can be below the minimum operating voltage (1.65 V) without any reset until the VPDR threshold). If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 0x8. 0xxx: BOR OFF. This is the reset threshold level for the 1.45 V - 1.55 V voltage range (power-down only). In this particular case, VDD must have been above BOR LEVEL 1 to start the device OBL sequence in order to disable the BOR. The power-down is then monitored by the PDR. Note: If the BOR is disabled, a "grey zone" exists between 1.65 V and the VPDR threshold (this means that VDD may be below the minimum operating voltage (1.65 V) without causing a reset until it crosses the VPDR threshold) 1000: BOR LEVEL 1 is the reset threshold level for VBOR0 (around 1.8 V) 1001: BOR LEVEL 2 is the reset threshold level for VBOR1 (around 2.0 V) 1010: BOR LEVEL 3 is the reset threshold level for VBOR2 (around 2.5 V) 1011: BOR LEVEL 4 is the reset threshold level for VBOR3 (around 2.7 V). 1100: BOR LEVEL 5 is the reset threshold level for VBOR4 (around 3.0 V) Note: Refer to the device datasheets for the exact definition of BOR levels. Bit 15:9 Reserved, must be kept at reset value Bit 8 WPRMOD This bit selects between write and read protection of Flash program memory sectors. If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 1. 0: PCROP disabled. The WRPROT bits are used as a write protection on a sector. 1: PCROP enabled. The WRPROT bits are used as a read protection on a sector. Bits 7:0 RDPROT: Read protection These bits contain the protection level loaded during the Option byte loading. If there is a mismatch on this configuration during the Option bytes loading, it is loaded with 0x00. 0xAA: Level 0 0xCC: Level 2 Others: Level 1 109/874 DocID025942 Rev 5 RM0377 Flash program memory and data EEPROM (FLASH) 3.7.9 Write protection register 1 (FLASH_WRPROT1) Address offset: 0x20 Reset value: 0xXXXX XXXX. It depends on the value programmed in the option bytes. During production, it is set to 0x0000 0000. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 WRPROT1[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r WRPROT1[15:0] r r Bits 31:0 WRPROT1: Write protection – If WPRMOD = 0 in the FLASH_OPTR register, these bits contain the write protection configuration for the Flash memory (every bit protects a 4-Kbyte sector: the first bit protects the first sector, the second bit protects the second page and so on). In this case, 1 = sector protected, 0 = no protection. – If WPRMOD = 1, these bits are used to protect from reading as data (see Read as data and pre-read), and then also from writing, with the same granularity and with the same combination of bits and sectors. The read protection does not protect against a fetch. In this case, 1 = no protection, 0 = sector protected. When WPRMOD = 0, it is possible to set or reset these bits without any limitation changing the relative Option bytes. When WPRMOD = 1, it is only possible to increase the protection, which means that the user can add zeros but cannot add ones. The mass erase deletes the WPRMOD bits but does not delete the content of this register. After a mass erase, the user must write the relative Option bytes with zeros to remove completely the write protections. If there is a mismatch on this configuration during the Option bytes loading, and the content of WPRMOD in the FLASH_OPTR register is: 1, this configuration is loaded with 0x0000. 0, this configuration is loaded with 0xFFFF. If there was a mismatch when WPRMOD was loaded in the FLASH_OPTR register (thus loaded with ones), the register is loaded with 0x0000. DocID025942 Rev 5 110/874 114 Flash program memory and data EEPROM (FLASH) 3.7.10 RM0377 Write protection register 2 (FLASH_WRPROT2) Address offset: 0x80 Reset value: 0x 0000 XXXX. It depends on the value programmed in the option bytes. During production, it is set to 0x0000 0000. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r r r r r r r r WRPROT2 [15:0] r r Bit 31:16 Reserved, must be kept at reset value Bits 15:0 WRPROT2: Write protection – If WPRMOD = 0 in the FLASH_OPTR register, these bits contain the write protection configuration for the Flash memory (every bit protects a 4-Kbyte sector: the first bit protects the first sector, the second bit protects the second page and so on). In this case, 1 = sector protected, 0 = no protection. – If WPRMOD = 1, these bits are used to protect from reading as data (see Read as data and pre-read), and then also from writing, with the same granularity and with the same combination of bits and sectors. The read protection does not protect against a fetch. In this case, 1 = no protection, 0 = sector protected. When WPRMOD = 0, it is possible to set or reset these bits without any limitation changing the relative Option bytes. When WPRMOD = 1, it is only possible to increase the protection, which means that the user can add zeros but cannot add ones. The mass erase deletes the WPRMOD bits but does not delete the content of this register. After a mass erase, the user must write the relative Option bytes with zeros to remove completely the write protections. If there is a mismatch on this configuration during the Option bytes loading, and the content of WPRMOD in the FLASH_OPTR register is: 1, this configuration is loaded with 0x0000. 0, this configuration is loaded with 0xFFFF. If there was a mismatch when WPRMOD was loaded in the FLASH_OPTR register (thus loaded with ones), the register is loaded with 0x0000. 111/874 DocID025942 Rev 5 RM0377 3.7.11 Flash program memory and data EEPROM (FLASH) Flash register map 0 0 0 0 0 0 0 0 0 LATENCY PELOCK Res. PRFTEN OPTLOCK 0 PRGLOCK RUN_PD SLEEP_PD 0 PRG DESAB_8BUF 0 Res. Res. 0 DATA FIX PRE_READ ERASE 0 Res. FPRG Res. Res. PARRALELBANK. Res. EOPIE Res. ERRIE Res. Res. Res. Res. 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PKEYR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PRGKEYR[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_ OPTKEYR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FLASH_SR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FWWERR NOTZEROERR Res. Res. RDERR Res. Res. Res. Res. Res. READY 0 0 1 WDG_SW X X X X X FLASH_ WRPROT1 X Res. nRST_STOP X Res. nRST_STBY BOR_LEV:0] Res. BFB2 Res. X Res. nBOOT_SEL X Res. nBOOT0 X Res. nBOOT1 0xXXXX0XXX Res. FLASH_OPTR 0 0 0 0 0 X BSY 0 EOP 0 ENDHV 0 WRPERR 0 WPRMOD 0 PGAERR 0 Res. 0 SIZERR 0 Res. 0 OPTVERR 0 Res. 0 Res. OPTKEYR[31:0] 0x00000000 0x01C 1 0 0 RDPROT[7:0] X X X X X X X X X X X X X X X X X X X X X X X X 0x0000XXXX X X X X X X X X X X X X X X X X FLASH_ WRPROT2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WRPROT1[31:0] Res. 0x080 0 0 PDKEYR[31:0] 0x0000000C 0x020 0 0 Res. 0x018 0 FLASH_ PRGKEYR 0x00000000 0x014 0 FLASH_ PKEYR 0x00000000 0x010 0 FLASH_ PDKEYR 0x00000000 0x00C 0 Res. 0x008 0 OBL_LAUNCH 0x00000007 NZDISABLE Res. Res. Res. Res. Res. Res. FLASH_PECR Res. 0x004 Res. 0x00000000 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. FLASH_ACR Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 25. Flash interface - register map and reset values 0xXXX 0000 X X X X X X X WRPROT2[15:0] X X X X X X X X X X Refer to Section 2.2.2 on page 50 for the register boundary addresses. DocID025942 Rev 5 112/874 114 Flash program memory and data EEPROM (FLASH) 3.8 RM0377 Option bytes On the NVM, an area is reserved to store a set of Option bytes which are used to configure the product. Some option bytes are written in factory while others can be configured by the end user. The configuration managed by an end user is stored the Option bytes area (32 bytes). To be taken into account, a boot sequence must be executed. This boot sequence occurs after a power-on reset when exiting from Standby mode, or by reloading the option bytes by software (Section 3.8.3: Reloading Option bytes by software). The Option bytes are automatically loaded during the boot. They are used to set the content of the FLASH_OPTR and FLASH_WRPROTx registers. Every word, when read during the boot, is interpreted as explained in Table 26: the lower 16 bits contain the data to copy in the memory interface registers and the higher 16 bits contain the complemented value used to check that the data read are correct. If there is an error during loading operation (the higher part is not the complement of the lower one), the default value is stored in the registers. The check is done by configuration. Section 3.8.2 explains what happens when there is a mismatch on protection configurations. During a write, no control is done to check if the higher part of a word is the complement of the lower part: this check must be performed by the user application. Table 26. Option byte format 3.8.1 31-24 23-16 15-8 7-0 Complemented Option byte 1 Complemented Option byte 0 Option byte 1 Option byte 0 Option bytes description The Option bytes can be read from the memory locations listed in Table 27. Table 27. Option byte organization Address [31:16] [15:0] 0x1FF8 0000 nFLASH_OPTR[15:0] FLASH_OPTR[15:0] 0x1FF8 0004 nFLASH_OPTR[31:16] FLASH_OPTR[31:16] 0x1FF8 0008 nFLASH_WRPROT1[15:0] FLASH_WRPROT1[15:0] 0x1FF8 000C nFLASH_WRPROT1[31:16] FLASH_WRPROT1[31:16] 0x1FF8 0010 nFLASH_WRPROT2[15:0] FLASH_WRPROT2[15:0] Refer to Section 3.7.8: Option bytes register (FLASH_OPTR) and Section 3.7.9: Write protection register 1 (FLASH_WRPROT1) for the meaning of each bit. 113/874 DocID025942 Rev 5 RM0377 3.8.2 Flash program memory and data EEPROM (FLASH) Mismatch when loading protection flags When there is a mismatch during an Option byte loading, the memory interface sets the default value in registers. In the Option byte area, there are three kinds of protection information: RDPROT This configuration sets the Protection Level. As explained in the next section, changing this level changes the possibility to access the NVM and the product. The default value is Level 1. It is possible to return to Level 0 from Level 1 but all content of the data EEPROM and Flash program memory will be deleted (mass erase). It is always possible to move to Level 2, but not to change protection levels when Level 2 is loaded (if the user writes in Option bytes a Level 2 but never reloads the Option bytes, the memory interface continues to works in the previous level and it is possible to write again a different protection level in the Option bytes area). WPRMOD This flag is independent from RDPROT and set if the Flash program memory is protected from read or write. When this flag is 1 (read protection), the only way to reset it is to request a mass erase (also returning to Level 0). This means that there is no way to remove the read protection when the device is in Level 2. The default value is 1 (read protection) and a mismatch on this bit also generates the default value for the WRPROT configuration. WRPROT This configuration sets which sectors of the Flash program memory are read- or writeprotected. If the read protection is disabled (WPRMOD = 0), 1 must be set in the right bit to protect a sector. If the read protection is enabled (WPRMOD = 1), 0 must be in the right bit to protect a sector. If during boot there is a mismatch on WPRMOD, this configuration is loaded with zeros so that all sectors of the Flash program memory are protected from read. If WPRMOD has been read correctly but there is a mismatch reading WRPROT, the register will be loaded with zeros if WPRMOD = 1, and with ones if WPRMOD = 0. Thus, a mismatch on a protection can have a serious impact on the normal execution of code (if it is in the Flash program memory): when there is a read protection, only a fetch is possible. In the Flash program memory, some values are read as data (the constants, for example) during a code execution; protecting all sectors from read prevents the execution of the application code from the Flash program memory. 3.8.3 Reloading Option bytes by software It is possible to request an Option byte reloading by setting the OBL_LAUNCH flag to 1 in the FLASH_PECR register. This bit can be set only when OPTLOCK = 0 (and PELOCK = 0). Setting this bit, the ongoing write/erase is completed, but no new write/erase or read operation is executed. The reload of Option bytes generates a reset of the device but without a power-down. The options must be reloaded after every change of the Option bytes in the NVM, so that the changes can apply. It is possible to reload by setting OBL_LAUNCH, or with a power-on of the V18 domain (i.e. after a power-on reset or after a standby). DocID025942 Rev 5 114/874 114 Cyclic redundancy check calculation unit (CRC) 4 Cyclic redundancy check calculation unit (CRC) 4.1 Introduction RM0377 The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from 8-, 16or 32-bit data word and a generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the functional safety standards, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at link time and stored at a given memory location. 4.2 115/874 CRC main features Fully programmable polynomial with programmable size (7, 8, 16, 32 bits). Handles 8-,16-, 32-bit data size Programmable CRC initial value Single input/output 32-bit data register Input buffer to avoid bus stall during calculation CRC computation done in 4 AHB clock cycles (HCLK) for the 32-bit data size General-purpose 8-bit register (can be used for temporary storage) Reversibility option on I/O data DocID025942 Rev 5 RM0377 4.3 Cyclic redundancy check calculation unit (CRC) CRC functional description Figure 7. CRC calculation unit block diagram $+%EXV ELWUHDGDFFHVV 'DWDUHJLVWHURXWSXW &5&FRPSXWDWLRQ ELWZULWHDFFHVV 'DWDUHJLVWHULQSXW 069 The CRC calculation unit has a single 32-bit read/write data register (CRC_DR). It is used to input new data (write access), and holds the result of the previous CRC calculation (read access). Each write operation to the data register creates a combination of the previous CRC value (stored in CRC_DR) and the new one. CRC computation is done on the whole 32-bit data word or byte by byte depending on the format of the data being written. The CRC_DR register can be accessed by word, right-aligned half-word and right-aligned byte. For the other registers only 32-bit access is allowed. The duration of the computation depends on data width: 4 AHB clock cycles for 32-bit 2 AHB clock cycles for 16-bit 1 AHB clock cycles for 8-bit An input buffer allows to immediately write a second data without waiting for any wait states due to the previous CRC calculation. The data size can be dynamically adjusted to minimize the number of write accesses for a given number of bytes. For instance, a CRC for 5 bytes can be computed with a word write followed by a byte write. The input data can be reversed, to manage the various endianness schemes. The reversing operation can be performed on 8 bits, 16 bits and 32 bits depending on the REV_IN[1:0] bits in the CRC_CR register. For example: input data 0x1A2B3C4D is used for CRC calculation as: 0x58D43CB2 with bit-reversal done by byte 0xD458B23C with bit-reversal done by half-word 0xB23CD458 with bit-reversal done on the full word The output data can also be reversed by setting the REV_OUT bit in the CRC_CR register. The operation is done at bit level: for example, output data 0x11223344 is converted into 0x22CC4488. DocID025942 Rev 5 116/874 120 Cyclic redundancy check calculation unit (CRC) RM0377 The CRC calculator can be initialized to a programmable value using the RESET control bit in the CRC_CR register (the default value is 0xFFFFFFFF). The initial CRC value can be programmed with the CRC_INIT register. The CRC_DR register is automatically initialized upon CRC_INIT register write access. The CRC_IDR register can be used to hold a temporary value related to CRC calculation. It is not affected by the RESET bit in the CRC_CR register. Polynomial programmability The polynomial coefficients are fully programmable through the CRC_POL register, and the polynomial size can be configured to be 7, 8, 16 or 32 bits by programming the POLYSIZE[1:0] bits in the CRC_CR register. Even polynomials are not supported. If the CRC data is less than 32-bit, its value can be read from the least significant bits of the CRC_DR register. To obtain a reliable CRC calculation, the change on-fly of the polynomial value or size can not be performed during a CRC calculation. As a result, if a CRC calculation is ongoing, the application must either reset it or perform a CRC_DR read before changing the polynomial. The default polynomial value is the CRC-32 (Ethernet) polynomial: 0x4C11DB7. 4.4 CRC registers 4.4.1 Data register (CRC_DR) Address offset: 0x00 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 DR[31:16] rw 15 14 13 12 11 10 9 8 7 DR[15:0] rw Bits 31:0 DR[31:0]: Data register bits This register is used to write new data to the CRC calculator. It holds the previous CRC calculation result when it is read. If the data size is less than 32 bits, the least significant bits are used to write/read the correct value. 117/874 DocID025942 Rev 5 RM0377 Cyclic redundancy check calculation unit (CRC) 4.4.2 Independent data register (CRC_IDR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. IDR[7:0] rw Bits 31:8 Reserved, must be kept cleared. Bits 7:0 IDR[7:0]: General-purpose 8-bit data register bits These bits can be used as a temporary storage location for one byte. This register is not affected by CRC resets generated by the RESET bit in the CRC_CR register 4.4.3 Control register (CRC_CR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. REV_ OUT Res. Res. RESET Res. Res. Res. Res. Res. Res. Res. rw REV_IN[1:0] rw rw POLYSIZE[1:0] rw rw rs Bits 31:8 Reserved, must be kept cleared. Bit 7 REV_OUT: Reverse output data This bit controls the reversal of the bit order of the output data. 0: Bit order not affected 1: Bit-reversed output format Bits 6:5 REV_IN[1:0]: Reverse input data These bits control the reversal of the bit order of the input data 00: Bit order not affected 01: Bit reversal done by byte 10: Bit reversal done by half-word 11: Bit reversal done by word DocID025942 Rev 5 118/874 120 Cyclic redundancy check calculation unit (CRC) RM0377 Bits 4:3 POLYSIZE[1:0]: Polynomial size These bits control the size of the polynomial. 00: 32 bit polynomial 01: 16 bit polynomial 10: 8 bit polynomial 11: 7 bit polynomial Bits 2:1 Reserved, must be kept cleared. Bit 0 RESET: RESET bit This bit is set by software to reset the CRC calculation unit and set the data register to the value stored in the CRC_INIT register. This bit can only be set, it is automatically cleared by hardware 4.4.4 Initial CRC value (CRC_INIT) Address offset: 0x10 Reset value: 0xFFFF FFFF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 6 5 4 3 2 1 0 22 21 20 19 18 17 16 6 5 4 3 2 1 0 CRC_INIT[31:16] rw 15 14 13 12 11 10 9 8 7 CRC_INIT[15:0] rw Bits 31:0 CRC_INIT: Programmable initial CRC value This register is used to write the CRC initial value. 4.4.5 CRC polynomial (CRC_POL) Address offset: 0x14 Reset value: 0x04C11DB7 31 30 29 28 27 26 25 24 23 POL[31:16] rw 15 14 13 12 11 10 9 8 7 POL[15:0] rw Bits 31:0 POL[31:0]: Programmable polynomial This register is used to write the coefficients of the polynomial to be used for CRC calculation. If the polynomial size is less than 32-bits, the least significant bits have to be used to program the correct value. 119/874 DocID025942 Rev 5 RM0377 4.4.6 Cyclic redundancy check calculation unit (CRC) CRC register map Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 28. CRC register map and reset values CRC_DR DR[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_IDR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CRC_CR 0 Res. 0x08 Reset value 0x10 CRC_INIT Reset value 0x14 1 1 1 1 1 1 1 0 0 0 IDR[7:0] REV_OUT 0x04 1 Res. 1 RESET 1 0 0 0 0 Res. 1 POLYSIZE[1:0] 1 REV_IN[1:0] Reset value Res. 0x00 0 0 0 0 0 1 1 1 1 1 0 CRC_INIT[31:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CRC_POL Polynomial coefficients Reset value 0x04C11DB7 1 1 1 1 1 1 1 1 Refer to Section 2.2.2 on page 50 for the register boundary addresses. DocID025942 Rev 5 120/874 120 Firewall (FW) RM0377 5 Firewall (FW) 5.1 Introduction The Firewall is made to protect a specific part of code or data into the Non-Volatile Memory, and/or to protect the Volatile data into the SRAM from the rest of the code executed outside the protected area. 5.2 Firewall main features The code to protect by the Firewall (Code Segment) may be located in: – The Flash program memory map – The SRAM memory, if declared as an executable protected area during the Firewall configuration step. The data to protect can be located either – in the Flash program or the Data EEPROM memory (non-volatile data segment) – in the SRAM memory (volatile data segment) The software can access these protected areas once the Firewall is opened. The Firewall can be opened or closed using a mechanism based on “call gate” (Refer to Opening the Firewall). The start address of each segment and its respective length must be configured before enabling the Firewall (Refer to Section 5.3.5: Firewall initialization). Each illegal access into these protected segments (if the Firewall is enabled) generates a reset which immediately kills the detected intrusion. Any DMA access to protected segments is forbidden whatever the Firewall state (opened or closed). It is considered as an illegal access and generates a reset. 121/874 DocID025942 Rev 5 RM0377 Firewall (FW) 5.3 Firewall functional description 5.3.1 Firewall AMBA bus snoop The Firewall peripheral is snooping the AMBA buses on which the memories (volatile and non-volatile) are connected. A global architecture view is illustrated in Figure 8. Figure 8. STM32L0x1 firewall connection schematics $+%6ODYH $+%0DVWHU &257(;0 $+%0DVWHU '0$ % 8 6 0 $ 7 5 , ; , 1 7 ( 5 ) $ & ( )ODVKSURJUDP PHPRU\DQGGDWD ((3520 ),5(:$// $+%6ODYH 65$0 069 5.3.2 Functional requirements There are several requirements to guaranty the highest security level by the application code/data which needs to be protected by the Firewall and to avoid unwanted Firewall alarm (reset generation). Debug consideration In debug mode, if the Firewall is opened, the accesses by the debugger to the protected segments are not blocked. For this reason, the Read out level 2 protection must be active in conjunction with the Firewall implementation. If the debug is needed, it is possible to proceed in the following way: A dummy code having the same API as the protected code may be developed during the development phase of the final user code. This dummy code may send back coherent answers (in terms of function and potentially timing if needed), as the protected code should do in production phase. In the development phase, the protected code can be given to the customer-end under NDA agreement and its software can be developed in level 0 protection. The customerend code needs to embed an IAP located in a write protected segment in order to allow future code updates when the production parts will be Level 2 ROP. DocID025942 Rev 5 122/874 132 Firewall (FW) RM0377 Write protection In order to offer a maximum security level, the following points need to be respected: It is mandatory to keep a write protection on the part of the code enabling the Firewall. This activation code should be located outside the segments protected by the Firewall. The write protection is also mandatory on the code segment protected by the Firewall. The sector including the reset vector must be write-protected. Interruptions management The code protected by the Firewall must not be interruptible. It is up to the user code to disable any interrupt source before executing the code protected by the Firewall. If this constraint is not respected, if an interruption comes while the protected code is executed (Firewall opened), the Firewall will be closed as soon as the interrupt subroutine is executed. When the code returns back to the protected code area, a Firewall alarm will raise since the “call gate” sequence will not be applied and a reset will be generated. Concerning the interrupt vectors and the first user sector in the Flash program memory: If the first user sector (including the reset vector) is protected by the Firewall, the NVIC vector should be reprogrammed outside the protected segment. If the first user sector is not protected by the Firewall, the interrupt vectors may be kept at this location. There is no interruption generated by the Firewall. 5.3.3 Firewall segments The Firewall has been designed to protect three different segment areas: Code segment This segment is located into the Flash program memory. It should contain the code to execute which requires the Firewall protection. The segment must be reached using the “call gate” entry sequence to open the Firewall. A system reset is generated if the “call gate” entry sequence is not respected (refer to Opening the Firewall) and if the Firewall is enabled using the FWDIS bit in the system configuration register. The length of the segment and the segment base address must be configured before enabling the Firewall (refer to Section 5.3.5: Firewall initialization). Non-volatile data segment This segment contains non-volatile data used by the protected code which must be protected by the Firewall. The access to this segment is defined into Section 5.3.4: Segment accesses and properties. The Firewall must be opened before accessing the data in this area. The Non-Volatile data segment should be located into the Flash program or 2-Kbyte Data EEPROM memory. The segment length and the base address of the segment must be configured before enabling the Firewall (refer to Section 5.3.5: Firewall initialization). 123/874 DocID025942 Rev 5 RM0377 Firewall (FW) Volatile data segment Volatile data used by the protected code located into the code segment must be defined into the SRAM memory. The access to this segment is defined into the Section 5.3.4: Segment accesses and properties. Depending on the Volatile data segment configuration, the Firewall must be opened or not before accessing this segment area. The segment length and the base address of the segment as well as the segment options must be configured before enabling the Firewall (refer to Section 5.3.5: Firewall initialization). The Volatile data segment can also be defined as executable (for the code execution) or shared using two bit of the Firewall configuration register (bit VDS for the volatile data sharing option and bit VDE for the volatile data execution capability). For more details, refer to Table 29. 5.3.4 Segment accesses and properties All DMA accesses to the protected segments are forbidden, whatever the Firewall state, and generate a system reset. Segment access depending on the Firewall state Each of the three segments has specific properties which are presented in Table 29. Table 29. Segment accesses according to the Firewall state Segment Code segment Non-volatile data segment Volatile data segment Firewall opened access allowed Read and execute Read and write Read and Write Execute if VDE = 1 and VDS = 0 into the Firewall configuration register Firewall closed access allowed Firewall disabled access allowed No access allowed. Any access to the segment (except the “call gate” entry) generates a system reset All accesses are allowed (according to the EEPROM protection properties in which the code is located) No access allowed All accesses are allowed (according to the EEPROM protection properties in which the code is located) No access allowed if VDS = 0 and VDE = 0 into the Firewall configuration register Read/write/execute accesses allowed if VDS = 1 (whatever VDE bit value) Execute if VDE = 1 and VDS = 0 but with a “call gate” entry to open the Firewall at first. All accesses are allowed DocID025942 Rev 5 124/874 132 Firewall (FW) RM0377 The Volatile data segment is a bit different from the two others. The segment can be: Shared (VDS bit in the register) It means that the area and the data located into this segment can be shared between the protected code and the user code executed in a non-protected area. The access is allowed whether the Firewall is opened or closed or disabled. The VDS bit gets priority over the VDE bit, this last bit value being ignored in such a case. It means that the Volatile data segment can execute parts of code located there without any need to open the Firewall before executing the code. Execute The VDE bit is considered as soon as the VDS bit = 0 in the FW_CR register. If the VDS bit = 1, refer to the description above on the Volatile data segment sharing. If VDS = 0 and VDE = 1, the Volatile data segment is executable. To avoid a system reset generation from the Firewall, the “call gate” sequence should be applied on the Volatile data segment to open the Firewall as an entry point for the code execution. Segments properties Each segment has a specific length register to define the segment size to be protected by the Firewall: CSL register for the Code segment length register, NVDSL for the Non-volatile data segment length register, and VDSL register for the Volatile data segment length register. Granularity and area ranges for each of the segments are presented in Table 30. Table 30. Segment granularity and area ranges Segment 5.3.5 Granularity Area range Code segment 256 bytes up to 64 Kbytes - 256 bytes Non-volatile data segment 256 bytes up to 64 Kbytes - 256 bytes Volatile data segment 64 bytes 8 Kbytes - 64 bytes Firewall initialization The initialization phase should take place at the beginning of the user code execution (refer to the Write protection). The initialization phase consists of setting up the addresses and the lengths of each segment which needs to be protected by the Firewall. It must be done before enabling the Firewall, because the enabling bit can be written once. Thus, when the Firewall is enabled, it cannot be disabled anymore until the next system reset. Once the Firewall is enabled, the accesses to the address and length segments are no longer possible. All write attempts are discarded. A segment defined with a length equal to 0 is not considered as protected by the Firewall. As a consequence, there is no reset generation from the Firewall when an access to the base address of this segment is performed. After a reset, the Firewall is disabled by default (FWDIS bit in the SYSCFG register is set). It has to be cleared to enable the Firewall feature. 125/874 DocID025942 Rev 5 RM0377 Firewall (FW) Below is the initialization procedure to follow: 1. Configure the RCC to enable the clock to the Firewall module 2. Configure the RCC to enable the clock of the system configuration registers 3. Set the base address and length of each segment (CSSA, CSL, NVDSSA, NVDSL, VDSSA, VDSL registers) 4. Set the configuration register of the Firewall (FW_CR register) 5. Enable the Firewall clearing the FWDIS bit in the system configuration register. The Firewall configuration register (FW_CR register) is the only one which can be managed in a dynamic way even if the Firewall is enabled: 5.3.6 when the Non-Volatile data segment is undefined (meaning the NVDSL register is equal to 0), the accesses to this register are possible whatever the Firewall state (opened or closed). when the Non-Volatile data segment is defined (meaning the NVDSL register is different from 0), the accesses to this register are only possible when the Firewall is opened. Firewall states The Firewall has three different states as shown in Figure 9: Disabled: The FWDIS bit is set by default after the reset. The Firewall is not active. Closed: The Firewall protects the accesses to the three segments (Code, Non-volatile data, and Volatile data segments). Opened: The Firewall allows access to the protected segments as defined in Section 5.3.4: Segment accesses and properties. Figure 9. Firewall functional states )LUHZDOOGLVDEOH UHVHW ,OOHJDODFFHVVHVWR WKHSURWHFWHG VHJPHQWV (QDEOHWKHILUHZDOO ):',6 3URWHFWHGFRGHMXPSV WRDQXQSURWHFWHG VHJPHQWDQG)3$ µµFDOOJDWH¶¶HQWU\ )LUHZDOO FORVHG )LUHZDOO RSHQHG &RGHSURWHFWHGMXPSV WRXQSURWHFWHG VHJPHQWV 069 DocID025942 Rev 5 126/874 132 Firewall (FW) RM0377 Opening the Firewall As soon as the Firewall is enabled, it is closed. It means that most of the accesses to the protected segments are forbidden (refer to Section 5.3.4: Segment accesses and properties). In order to open the Firewall to interact with the protected segments, it is mandatory to apply the “call gate” sequence described hereafter. “call gate” sequence The “call gate” is composed of 3 words located on the first three 32-bit addresses of the base address of the code segment and of the Volatile data segment if it is declared as not shared (VDS = 0) and executable (VDE = 1). – 1st word: Dummy 32-bit words always closed in order to protect the “call gate” opening from an access due to a prefetch buffer. – 2nd and 3rd words: 2 specific 32-bit words called “call gate” and always opened. To open the Firewall, the code currently executed must jump to the 2nd word of the “call gate” and execute the code from this point. The 2nd word and 3rd word execution must not be interrupted by any intermediate instruction fetch; otherwise, the Firewall is not considered open and comes back to a close state. Then, executing the 3rd word after receiving the intermediate instruction fetch would generate a system reset as a consequence. As soon as the Firewall is opened, the protected segments can be accessed as described in Section 5.3.4: Segment accesses and properties. Closing the Firewall The Firewall is closed immediately after it is enabled (clearing the FWDIS bit in the system configuration register). To close the Firewall, the protected code must: Write the correct value in the Firewall Pre Arm Flag into the FW_CR register. Jump to any executable location outside the Firewall segments. If the Firewall Pre Arm Flag is not set when the protected code jumps to a non protected segment, a reset is generated. This control bit is an additional protection to avoid an undesired attempt to close the Firewall with the private information not yet cleaned (see the note below). For security reasons, following the application for which the Firewall is used, it is advised to clean all private information from CPU registers and hardware cells. 127/874 DocID025942 Rev 5 RM0377 Firewall (FW) 5.4 Firewall registers 5.4.1 Code segment start address (FW_CSSA) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 ADD[23:16] rw 15 14 13 12 11 10 9 8 ADD[15:8] 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res rw Bits 31:24 Reserved, must be kept at reset value. Bits 23:8 ADD[23:8]: code segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity. Note: These bits can be written only before enabling the Firewall. Refer to Section 5.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. 5.4.2 Code segment length (FW_CSL) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 19 18 17 16 LENG[21:16] rw 15 14 13 12 11 LENG15:8] 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:22 Reserved, must be kept at the reset value. Bits 21:8 LENG[21:8]: code segment length LENG[21:8] selects the size of the code segment expressed in bytes but is a multiple of 256 bytes. The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01 Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall. These bits can only be written before enabling the Firewall. Refer to Section 5.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. DocID025942 Rev 5 128/874 132 Firewall (FW) 5.4.3 RM0377 Non-volatile data segment start address (FW_NVDSSA) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 Res. Res. Res. Res. Res. Res. Res. Res. 23 22 21 20 19 18 17 16 ADD[23:16] rw 15 14 13 12 11 10 9 8 ADD[15:8] 7 6 5 4 3 2 1 0 Res Res Res Res Res Res Res Res rw Bits 31:24 Reserved, must be kept at the reset value. Bits 23:8 ADD[23:8]: Non-volatile data segment start address The LSB bits of the start address (bit 7:0) are reserved and forced to 0 in order to allow a 256-byte granularity. Note: These bits can only be written before enabling the Firewall. Refer to Section 5.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. 5.4.4 Non-volatile data segment length (FW_NVDSL) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 21 20 19 18 17 16 LENG[21:16] rw 15 14 13 12 11 LENG[15:8] 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:22 Reserved, must be kept at the reset value. Bits 21:8 LENG[21:8]: Non-volatile data segment length LENG[21:8] selects the size of the Non-volatile data segment expressed in bytes but is a multiple of 256 bytes. The segment area is defined from {ADD[23:8],0x00} to {ADD[23:8]+LENG[21:8], 0x00} - 0x01 Note: If LENG[21:8] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall. These bits can only be written before enabling the Firewall. Refer to Section 5.3.5: Firewall initialization. Bits 7:0 Reserved, must be kept at the reset value. 129/874 DocID025942 Rev 5 RM0377 Firewall (FW) 5.4.5 Volatile data segment start address (FW_VDSSA) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res Res Res Res Res Res ADD[15:6] rw Bits 31:16 Reserved, must be kept at the reset value. Bits 15:6 ADD[15:6]: Volatile data segment start address The LSB bit of the start address (bits 5:0) are reserved and forced to 0 in order to allow a 64-byte granularity. Note: These bits can only be written before enabling the Firewall. Refer to Section 5.3.5: Firewall initialization. Bits 5:0 Reserved, must be kept at the reset value. 5.4.6 Volatile data segment length (FW_VDSL) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. LENG[15:6] rw Bits 31:16 Reserved, must be kept at the reset value. Bits 15:6 LENG[15:6]: Non-volatile data segment length LENG[15:6] selects the size of the Non-volatile data segment expressed in bytes but is a multiple of 64 bytes. The segment area is defined from {ADD[15:6],0x00} to {ADD[15:6]+LENG[15:6], 0x00} - 0x01 Note: If LENG[15:6] = 0 after enabling the Firewall, this segment is not defined, thus not protected by the Firewall. These bits can only be written before enabling the Firewall. Refer to Section 5.3.5: Firewall initialization. Bits 5:0 Reserved, must be kept at the reset value. DocID025942 Rev 5 130/874 132 Firewall (FW) 5.4.7 RM0377 Configuration register (FW_CR) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VDE VDS FPA rw rw rw Bits 31:3 Reserved, must be kept at the reset value. Bit 2 VDE: Volatile data execution 0: Volatile data segment cannot be executed if VDS = 0 1: Volatile data segment is declared executable whatever VDS bit value When VDS = 1, this bit has no meaning. The Volatile data segment can be executed whatever the VDE bit value. If VDS = 1, the code can be executed whatever the Firewall state (opened or closed) If VDS = 0, the code can only be executed if the Firewall is opened or applying the “call gate” entry sequence if the Firewall is closed. Refer to Segment access depending on the Firewall state. Bit 1 VDS: Volatile data shared 0: Volatile data segment is not shared and cannot be hit by a non protected executable code when the Firewall is closed. If it is accessed in such a condition, a system reset will be generated by the Firewall. 1: Volatile data segment is shared with non protected application code. It can be accessed whatever the Firewall state (opened or closed). Refer to Segment access depending on the Firewall state. Bit 0 FPA: Firewall prearm 0: any code executed outside the protected segment when the Firewall is opened will generate a system reset. 1: any code executed outside the protected segment will close the Firewall. Refer to Closing the Firewall. This register is protected in the same way as the Non-volatile data segment (refer to Section 5.3.5: Firewall initialization). 131/874 DocID025942 Rev 5 0x20 0x18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. VDE VDS FPA Reset Value Res. FW_CR Res. Reset Value Res. 0x1C Res. Reset Value Res. 0 0 0 DocID025942 Rev 5 0 0 0 0 0 0 0 0 0 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 0 Res. ADD 0 Res. 0 0 Res. LENG 0 Res. ADD 0 Res. Res. Res. Res. Res. Res. LENG Res. Res. Res. Res. Res. Res. Res. Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FW_CSSA Res. Res. Res. Res. Res. Res. Res. Res. Register Res. Res. Res. Res. Res. Res. Res. Res. ADD Res. Reset Value 0 Res. Reset Value 0 Res. 0 LENG 0 LENG Res. Res. 0 Res. 0 Res. Res. Res. 0 Res. 0 0 Res. Res. Res. 0 Res. 0 0 0 Res. Res. Res. Res. 0 0 0 Res. Res. Res. 0 Res. Res. Res. 0 0 Res. Res. Res. Reset Value 0 0 0 Res. Res. Res. Res. Res. 0 0 0 Res. Res. Res. Res. Res. 0 0 0 Res. Res. Res. Res. Res. Res. 0 0 Res. Res. Res. Res. Res. Res. Res. Reset Value 0 Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Reset Value Res. Res. FW_VDSL Res. Res. Res. Reset Value Res. Res. Res. Res. Res. Res. Res. FW_VDSSA Res. FW_NVDSL Res. FW_NVDSSA Res. Res. 0x14 FW_VDSL Res. 0x14 Res. 0x10 Res. 0xC FW_CSL Res. 0x8 Res. 0x4 Res. 0x0 Res. Offset Res. 5.4.8 Res. RM0377 Firewall (FW) Firewall register map The table below provides the Firewall register map and reset values. Table 31. Firewall register map and reset values Refer to Section 2.2.2 on page 50 for the register boundary addresses. 132/874 132 Power control (PWR) RM0377 6 Power control (PWR) 6.1 Power supplies The device requires a 1.8-to-3.6 V VDD operating voltage supply (down to 1.65 V at powerdown) when the BOR is available. The device requires a 1.65-to-3.6 V VDD operating voltage supply when the BOR is not available. An embedded linear voltage regulator is used to supply the internal digital power, ranging from 1.2 to 1.8 V. VDD = 1.8 V (at power-on) or 1.65 V (at power-down) to 3.6 V when the BOR is available. VDD = 1.65 V to 3.6 V, when BOR is not available VDD is the external power supply for I/Os and internal regulator. It is provided externally through VDD pins VCORE = 1.2 to 1.8 V VCORE is the power supply for digital peripherals, SRAM and Flash memory. It is generated by a internal voltage regulator. Three VCORE ranges can be selected by software depending on VDD (refer Figure 11). VSSA, VDDA = 1.8 V (at power-on) or 1.65 V (at power-down) to 3.6 V, when BOR is available and VSSA, VDDA = 1.65 to 3.6 V, when BOR is not available. VDDA is the external analog power supply for ADC, reset blocks, RC oscillators and PLL. For category 1 devices in low-pin count packages, VDDA is bonded to VDD (refer to the corresponding datasheets for more details). VREF+ VREF+ is the input reference voltage. It is only available as an external pin on a few packages, otherwise it is bonded to VDDA. 133/874 DocID025942 Rev 5 RM0377 Power control (PWR) Figure 10. Power supply overview 9''$GRPDLQ IURP9XSWR9''$95() $'& 7HPS6HQVRU 5HVHWEORFN 3// 9''9''$ 966966$ 9''GRPDLQ 9&RUHGRPDLQ )ODVKPHPRU\ ,2VXSSO\ 966 9'' 6WDQGE\ FLUFXLWU\:DNHXS ORJLF,:'*57& /6(FU\VWDO. RVF5&& &RUHPHPRULHV 'LJLWDO SHULSKHUDOV 9ROWDJHUHJXODWRU '\QDPLFYROWDJH VFDOLQJ 06Y9 1. VDDA and VSSA must be connected to VDD and VSS, respectively. 2. Depending on the operating power supply range used, some peripherals may be used with limited features or performance. 3. VREF+ is only available on TFBGA64 package. 6.1.1 Independent A/D converter supply and reference voltage To improve conversion accuracy, the ADC has an independent power supply that can be filtered separately, and shielded from noise on the PCB. Note: The ADC voltage supply input is available on a separate VDDA pin An isolated supply ground connection is provided on the VSSA pin For category 1 devices in 14-pin package, VDDA is internally connected to VDD. On packages with more than 64 pins and UFBGA64 To ensure a better accuracy on low-voltage inputs and outputs, the user can connect to VREF+ a separate external reference voltage lower than VDD. VREF+ is the highest voltage, represented by the full scale value, for an analog input (ADC). For ADC: 1.65 V VREF+ < VDDA On packages with 64 pins or less (except BGA package) VREF+ pin is not available. It is internally connected to the ADC voltage supply (VDDA). DocID025942 Rev 5 134/874 163 Power control (PWR) 6.1.2 RM0377 RTC and RTC backup registers The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar, two programmable alarm interrupts, and a periodic programmable wakeup flag with interrupt capability. The RTC contains 5 backup data registers (20 bytes). These backup registers are reset when a tamper detection event occurs. For more details refer to Real-time clock (RTC) section. RTC registers access After reset, the RTC Registers (RTC registers and RTC backup registers) are protected against possible stray write accesses. To enable access to the RTC Registers, proceed as follows: 6.1.3 1. Enable the power interface clock by setting the PWREN bits in the RCC_APB1ENR register. 2. Set the DBP bit in the PWR_CR register (see Section 6.4.1). 3. Select the RTC clock source through RTCSEL[1:0] bits in RCC_CSR register. 4. Enable the RTC clock by programming the RTCEN bit in the RCC_CSR register. Voltage regulator An embedded linear voltage regulator supplies all the digital circuitries except for the Standby circuitry. The regulator output voltage (VCORE) can be programmed by software to three different ranges within 1.2 - 1.8 V (typical) (see Section 6.1.4). The voltage regulator is always enabled after Reset. It works in three different modes: main (MR), low-power (LPR) and power-down, depending on the application modes. 6.1.4 In Run mode, the regulator is main (MR) mode and supplies full power to the VCORE domain (core, memories and digital peripherals). In Low-power run mode, the regulator is in low-power (LPR) mode and supplies lowpower to the VCORE domain, preserving the contents of the registers and internal SRAM. In Sleep mode, the regulator is main (MR) mode and supplies full power to the VCORE domain, preserving the contents of the registers and internal SRAM. In Low-power sleep mode, the regulator is in low-power (LPR) mode and supplies lowpower to the VCORE domain, preserving the contents of the registers and internal SRAM. In Stop mode the regulator supplies low power to the VCORE domain, preserving the content of registers and internal SRAM. In Standby mode, the regulator is powered off. The content of the registers and SRAM are lost except for the Standby circuitry. Dynamic voltage scaling management The dynamic voltage scaling is a power management technique which consists in increasing or decreasing the voltage used for the digital peripherals (VCORE), according to the circumstances. Dynamic voltage scaling to increase VCORE is known as overvolting. It allows improving the device performance. Refer to Figure 11 for a description of the device operating conditions versus CPU performance and to the datasheet electrical characteristics for ADC clock frequency versus dynamic range. 135/874 DocID025942 Rev 5 RM0377 Power control (PWR) Dynamic voltage scaling to decrease VCORE is known as undervolting. It is performed to save power, particularly in laptops and other mobile devices where the energy comes from a battery and is thus limited. Range 1 Range 1 is the “high performance” range. The voltage regulator outputs a 1.8 V voltage (typical) as long as the VDD input voltage is above 1.71 V. Flash program and erase operations can be performed in this range. When VDD is below 2.0 V, the CPU frequency changes from initial to final state must respect the following conditions: fCPUfinal < 4xfCPUinitial. In addition, a 5 μs delay must be respected between two changes. For example to switch from 4.2 to 32 MHz, switch from 4.2 to 16 MHz, wait for 5 μs, then switch from 16 to 32 MHz. Range 2 and 3 The regulator can also be programmed to output a regulated 1.5 V (typical, range 2) or a 1.2 V (typical, range 3) without any limitations on VDD (1.65 to 3.6 V). At 1.5 V, the Flash memory is still functional but with medium read access time. This is the “medium performance” range. Program and erase operations on the Flash memory are still possible. At 1.2 V, the Flash memory is still functional but with slow read access time. This is the “low performance” range. Program and erase operations on the Flash memory are not possible under these conditions. Refer to Table 32 for details on the performance for each range. Table 32. Performance versus VCORE ranges CPU performance Power performance VCORE range Typical Value (V) Max frequency (MHz) 1 WS 0 WS High Low 1 1.8 32 16 Medium Medium 2 1.5 16 8 Low High 3 1.2 4.2 4.2 DocID025942 Rev 5 VDD range 1.71 - 3.6 1.65 - 3.6 136/874 163 Power control (PWR) RM0377 Figure 11. Performance versus VDD and VCORE range 0+] 0+] )&38 !0+] :6 0+] 0+] )&38 !0+] :6 0+] 0+] :6 9 &25( 9 9' ' :6 :6 9 9 9 9 9±9 5DQJ H 5D QJH 5DQJH 069 6.1.5 Dynamic voltage scaling configuration The following sequence is required to program the voltage regulator ranges: 1. Check VDD to identify which ranges are allowed (see Figure 11: Performance versus VDD and VCORE range). 2. Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0. 3. Configure the voltage scaling range by setting the VOS[1:0] bits in the PWR_CR register. 4. Poll VOSF bit of in PWR_CSR register. Wait until it is reset to 0. Note: During voltage scaling configuration, the system clock is stopped until the regulator is stabilized (VOSF=0). This must be taken into account during application development, in case a critical reaction time to interrupt is needed, and depending on peripheral used (timer, communication,...). 6.1.6 Voltage regulator and clock management when VDD drops below 1.71 V When VCORE range 1 is selected and VDD drops below 1.71 V, the application must reconfigure the system. A three-step sequence is required to reconfigure the system: 1. Detect that VDD drops below 1.71 V: Use the PVD to monitor the VDD voltage and to generate an interrupt when the voltage goes under the selected level. To detect the 1.71 V voltage limit, the application can 137/874 DocID025942 Rev 5 RM0377 Power control (PWR) select by software PVD threshold 2 (2.26 V typical). For more details on the PVD, refer to Section 6.2.3. 2. Adapt the clock frequency to the voltage range that will be selected at next step: Below 1.71 V, the system clock frequency is limited to 16 MHz for range 2 and 4.2 MHz for range 3. 3. Select the required voltage range: Note that when VDD is below 1.71 V, only range 2 or range 3 can be selected. Note: When VCORE range 2 or range 3 is selected and VDD drops below 1.71 V, no system reconfiguration is required. 6.1.7 Voltage regulator and clock management when modifying the VCORE range When VDD is above 1.71 V, any of the 3 voltage ranges can be selected: When the voltage range is above the targeted voltage range (e.g. from range 1 to 2): a) Adapt the clock frequency to the lower voltage range that will be selected at next step. b) Select the required voltage range. When the voltage range is below the targeted voltage range (e.g. from range 3 to 1): a) Select the required voltage range. b) Tune the clock frequency if needed. When VDD is below 1.71 V, only range 2 and 3 can be selected: 6.1.8 From range 2 to range 3 a) Adapt the clock frequency to voltage range 3. b) Select voltage range 3. From range 3 to range 2 a) Select the voltage range 2. b) Tune the clock frequency if needed. Voltage range and limitations when VDD ranges from 1.71 V to 2.0 V The STM32L0x1 voltage regulator is based on an architecture designed for Ultra-low-power a. It does not use any external capacitor. Such regulator is sensitive to fast changes of load. In this case, the output voltage is reduced for a short period of time. Considering that the core voltage must be higher than 1.65 V to ensure a 32 MHz operation, this phenomenon is critical for very low VDD voltages (e.g. 1.71 V VDD minimum value). To guarantee 32 MHz operation at VDD =1.8 V±5%, with 1 wait state, and VCORE range 1, the CPU frequency in run mode must be managed to prevent any changes exceeding a ratio of 4 in one shot. A delay of 5 μs must be respected between 2 changes. There is no limitation when waking up from low-power mode. 6.2 Power supply supervisor The device has an integrated zeropower power-on reset (POR)/power-down reset (PDR), coupled with a brown out reset (BOR) circuitry. For devices operating between 1.8 and 3.6 DocID025942 Rev 5 138/874 163 Power control (PWR) RM0377 V, the BOR is always active at power-on and ensures proper operation starting from 1.8 V. After the 1.8 V BOR threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable BOR permanently (in which case, the VDD min value at power-down is 1.65 V). For devices operating between 1.65 V and 3.6 V, the BOR is permanently disabled. Consequently, the start-up time at power-on can be decreased down to 1 ms typically. Five BOR thresholds can be configured by option bytes, starting from 1.65 to 3 V. To reduce the power consumption in Stop mode, the internal voltage reference, VREFINT, can be automatically switch off. The device remains in reset mode when VDD is below a specified threshold, VPOR, VPDR or VBOR, without the need for any external reset circuit. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. 7 different PVD levels can be selected by software between 1.85 and 3.05 V, with a 200 mV step. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine then generates a warning message and/or put the MCU into a safe state. The PVD is enabled by software. The different power supply supervisor (POR, PDR, BOR, PVD) are illustrated in Figure 12. 139/874 DocID025942 Rev 5 RM0377 Power control (PWR) Figure 12. Power supply supervisors 9'' 9'' $ 9 39' 9 %2 5 P9 K\VWHUHVLV P9 K\VWHUHVLV 9325 93'5 ,7HQDEOHG 39'RXWSXW %25UHVHW 1567 %253'5UHVHW 1567 3253'5UHVHW 1567 39' %25DOZD\VDFWLYH %25GLVDEOHGE\RSWLRQE\WH 3253'5%25QRWDYDLODEOH DLE 1. The PVD is available on all devices and it is enabled or disabled by software. 2. The BOR is available only on devices operating from 1.8 to 3.6 V, and unless disabled by option byte it will mask the POR/PDR threshold. 3. When the BOR is disabled by option byte, the reset is asserted when VDD goes below PDR level 4. For devices operating from 1.65 to 3.6 V, there is no BOR and the reset is released when VDD goes above POR level and asserted when VDD goes below PDR level DocID025942 Rev 5 140/874 163 Power control (PWR) 6.2.1 RM0377 Power-on reset (POR)/power-down reset (PDR) The device has an integrated POR/PDR circuitry that allows operation down to 1.5 V. During power-on, the device remains in Reset mode when VDD/VDDA is below a specified threshold, VPOR, without the need for an external reset circuit. The POR feature is always enabled and the POR threshold is 1.5 V. During power-down, the PDR keeps the device under reset when the supply voltage (VDD) drops below the VPDR threshold. The PDR feature is always enabled and the PDR threshold is 1.5 V. The POR and PDR are used only when the BOR is disabled (see Section 6.2.2: Brown out reset (BOR))). To insure the minimum operating voltage (1.65 V), the BOR should be configured to BOR Level 1. When the BOR is disabled, a “gray zone” exist between the minimum operating voltage (1.65 V) and the VPOR/VPDR threshold. This means that VDD can be lower than 1.65 V without device reset until the VPDR threshold is reached. For more details concerning the power-on/power-down reset threshold, refer to the electrical characteristics of the datasheet. Figure 13. Power-on reset/power-down reset waveform sͬs WKZ WZ dĞŵƉŽƌŝnjĂƚŝŽŶ ƚZ^ddDWK ZĞƐĞƚ 069 6.2.2 Brown out reset (BOR) During power-on, the Brown out reset (BOR) keeps the device under reset until the supply voltage reaches the specified VBOR threshold. For devices operating from 1.65 to 3.6 V, the BOR option is not available and the power supply is monitored by the POR/PDR. As the POR/PDR thresholds are at 1.5 V, a “gray zone” exists between the VPOR/VPDR thresholds and the minimum product operating voltage 1.65 V. For devices operating from 1.8 to 3.6 V, the BOR is always active at power-on and it's threshold is 1.8 V. Then when the system reset is released, the BOR level can be reconfigured or disabled by option byte loading. If the BOR level is kept at the lowest level, 1.8 V at power-on and 1.65 V at power-down, the system reset is fully managed by the BOR and the product operating voltages are within safe ranges. 141/874 DocID025942 Rev 5 RM0377 Power control (PWR) And when the BOR option is disabled by option byte, the power-down reset is controlled by the PDR and a “gray zone” exists between the 1.65 V and VPDR. VBOR is configured through device option bytes. By default, the Level 4 threshold is activated. 5 programmable VBOR thresholds can be selected. BOR Level 1 (VBOR0): reset threshold level for 1.69 to 1.80 V voltage range BOR Level 2 (VBOR1): reset threshold level for 1.94 to 2.1 V voltage range BOR Level 3 (VBOR2): reset threshold level for 2.3 to 2.49 V voltage range BOR Level 4 (VBOR3): reset threshold level for 2.54 to 2.74 V voltage range BOR Level 5 (VBOR4): reset threshold level for 2.77 to 3.0 V voltage range When the supply voltage (VDD) drops below the selected VBOR threshold, a device reset is generated. When the VDD is above the VBOR upper limit the device reset is released and the system can start. BOR can be disabled by programming the device option bytes. To disable the BOR function, VDD must have been higher than VBOR0 to start the device option byte programming sequence. The power-on and power-down is then monitored by the POR and PDR (see Section 6.2.1: Power-on reset (POR)/power-down reset (PDR)) The BOR threshold hysteresis is ~100 mV (between the rising and the falling edge of the supply voltage). Figure 14. BOR thresholds sͬs %25WKUHVKROG P9 K\VWHUHVLV 5HVHW 069 6.2.3 Programmable voltage detector (PVD) You can use the PVD to monitor the VDD power supply by comparing it to a threshold selected by the PLS[2:0] bits in the PWR_CR (see Section 6.4.1). The PVD can use an external input analog voltage (PVD_IN) which is compared internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode when PLS[2:0] = 111. The PVD is enabled by setting the PVDE bit. A PVDO flag is available, in the PWR_CSR (see Section 6.4.2), to indicate if VDD is higher or lower than the PVD threshold. This event is internally connected to the EXTI line16 and can generate an interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated when VDD drops below the PVD threshold and/or when VDD rises above the PVD threshold depending on EXTI line16 rising/falling edge configuration. As an example the service routine could perform emergency shutdown tasks. DocID025942 Rev 5 142/874 163 Power control (PWR) RM0377 Figure 15. PVD thresholds sͬs 39'WKUHVKROG 39'RXWSXW 6.2.4 P9 K\VWHUHVLV 069 Internal voltage reference (VREFINT) The internal reference (VREFINT) provides stable voltage for analog peripherals. The functions managed through the internal voltage reference (VREFINT) are BOR, PVD, ADC and comparators. The internal voltage reference (VREFINT) is always enabled when one of these features is used. The internal voltage reference consumption is not negligible, in particular in Stop and Standby mode. To reduce power consumption, the ULP bit (ultra-low-power) in the PWR_CR register can be set to disable the internal voltage reference. However, in this case, when exiting from the Stop/Standby mode, the functions managed through the internal voltage reference are not reliable during the internal voltage reference startup time (up to 3 ms). To reduce the wakeup time, the device can exit from Stop/Standby mode without waiting for the internal voltage reference startup time. This is performed by setting the FWU bit (Fast wakeup) in the PWR_CR register before entering Stop/Standby mode. If the ULP bit is set, the functions that were enabled before entering Stop/Standby mode will be disabled during these modes, and enabled again only after the end of the internal voltage reference startup time whatever FWU value. The VREFINTRDYF flag in the PWR_CSR register indicates that the internal voltage reference is ready. When the device exits from low-power mode on an NRST pulse, it does not wait for internal voltage reference startup (even if ULP=1 and FWU=0). The application should check the VREFINTRDYF flag if necessary. 143/874 DocID025942 Rev 5 RM0377 6.3 Power control (PWR) Low-power modes By default, the microcontroller is in Run mode after a system or a power-on reset. In Run mode the CPU is clocked by HCLK and the program code is executed. Several low-power modes are available to save power when the CPU does not need to be kept running, for example when waiting for an external event. It is up to the user to select the mode that gives the best compromise between low-power consumption, performance, short startup time and available wakeup sources. The devices feature five low-power modes: Low-power run mode: regulator in low-power mode, limited clock frequency, limited number of peripherals running (refer to Section 6.3.4) Sleep mode: Cortex®-M0+ core stopped, peripherals kept running (refer to Section 6.3.7) Low-power sleep mode: Cortex®-M0+core stopped, limited clock frequency, limited number of peripherals running, regulator in low-power mode, Flash stopped ((refer to Section 6.3.8)) Stop mode (all clocks are stopped, regulator running, regulator in low-power mode (refer to Section 6.3.9) Standby mode: VCORE domain powered off ((refer to Section 6.3.10)) In addition, the power consumption in Run mode can be reduced by one of the following means: Slowing down the system clocks Gating the clocks to the APBx and AHBx peripherals when they are unused. Table 33. Summary of low-power modes Mode name Low-power run Sleep (Sleep now or Sleep-on-exit) Low-power sleep (Sleep now or Sleepon-exit) Effect on VDD domain Voltage regulator clocks Entry Wakeup Effect on VCORE domain clocks LPSDSR and LPRUN bits + Clock setting The regulator is forced in Main regulator (1.8 V) None None In low-power mode WFI or Return from ISR Any interrupt None ON WFE Wakeup event CPU CLK OFF no effect on other clocks or analog clock sources LPSDSR bits + WFI or Return from ISR Any interrupt None LPSDSR bits + WFE In low-power mode Wakeup event CPU CLK OFF no effect on other clocks or analog clock sources, Flash CLK OFF DocID025942 Rev 5 144/874 163 Power control (PWR) RM0377 Table 33. Summary of low-power modes (continued) Mode name Entry Wakeup PDDS, LPSDSR Any EXTI line or LPDS bits + (configured in the EXTI SLEEPDEEP bit + registers, internal and WFI, Return from external lines) ISR or WFE Stop Standby WKUP pin rising edge, RTC alarm (Alarm A or PDDS bit + Alarm B), RTC Wakeup SLEEPDEEP bit + event, RTC tamper WFI, Return from event, RTC timestamp ISR or WFE event, external reset in NRST pin, IWDG reset Effect on VCORE domain clocks Effect on VDD domain Voltage regulator clocks ON, in low-power mode (depending on PWR_CR) All VCORE domain clocks OFF HSI16(1), HSE and MSI OFF oscillators OFF 1. HSI16 can run in Stop mode provided HSI16KERON is set in Clock control register (RCC_CR). 6.3.1 Behavior of clocks in low-power modes APB peripheral and DMA clocks can be disabled by software. Sleep and Low-power sleep modes The CPU clock is stopped in Sleep and Low-power sleep mode. The memory interface clocks (Flash memory and RAM interfaces) and all peripherals clocks can be stopped by software during Sleep. The memory interface clock is stopped and the RAM is in powerdown when in Low-power sleep mode. The AHB to APB bridge clocks are disabled by hardware during Sleep/Low-power sleep mode when all the clocks of the peripherals connected to them are disabled. Stop and Standby modes The system clock and all high speed clocks are stopped in Stop and Standby modes: PLL is disabled Internal RC 16 MHz (HSI16) oscillator is disabled, except if HSI16KERON is set in Stop mode (see Section 7.3.1: Clock control register (RCC_CR)) External 1-24 MHz (HSE) oscillator is disabled Internal 65 kHz - 4.2 MHz (MSI) oscillator is disabled When exiting this mode by an interrupt (Stop mode), the internal MSI or HSI16 can be selected as system clock. For both oscillators, their respective configuration (range and trimming) value is kept on Stop mode exit. When exiting this mode by a reset (Standby mode), the internal MSI oscillator is selected as system clock. The range and the trimming value are reset to the default 2.1 MHz. If a Flash program operation or an access to APB domain is ongoing, the Stop/Standby mode entry is delayed until the Flash memory or the APB access has completed. 145/874 DocID025942 Rev 5 RM0377 6.3.2 Power control (PWR) Slowing down system clocks In Run mode the speed of the system clocks (SYSCLK, HCLK, PCLK1, PCLK2) can be reduced by programming the prescaler registers. These prescalers can also be used to slow down peripherals before entering Sleep mode. For more details refer to Section 7.3.3: Clock configuration register (RCC_CFGR). 6.3.3 Peripheral clock gating In Run mode, the HCLK and PCLKx for individual peripherals and memories can be stopped at any time to reduce power consumption. To further reduce power consumption in Sleep mode the peripheral clocks can be disabled prior to executing the WFI or WFE instructions. Peripheral clock gating is controlled by the AHB peripheral clock enable register (RCC_AHBENR), APB2 peripheral clock enable register (RCC_APB2ENR), APB1 peripheral clock enable register (RCC_APB1ENR) (see Section 7.3.12: AHB peripheral clock enable register (RCC_AHBENR), Section 7.3.14: APB1 peripheral clock enable register (RCC_APB1ENR) and Section 7.3.13: APB2 peripheral clock enable register (RCC_APB2ENR)). Disabling the peripherals clocks in Sleep mode can be performed automatically by resetting the corresponding bit in RCC_AHBLPENR and RCC_APBxLPENR registers (x can 1 or 2). 6.3.4 Low-power run mode (LP run) To further reduce the consumption when the system is in Run mode, the regulator can be configured in low-power mode. In this mode, the system frequency should not exceed f_MSI range1. Please refer to the product datasheet for more details on voltage regulator and peripherals operating conditions. Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. Low-power run mode can only be entered when VCORE is in range 2. In addition, the dynamic voltage scaling must not be used when Low-power run mode is selected. Only Stop and Sleep modes with regulator configured in low-power mode is allowed when Low-power run mode is selected. Note: In Low-power run mode, all I/O pins keep the same state as in Run mode. Entering Low-power run mode To enter Low-power run mode proceed as follows: 1. Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and RCC_AHBENR registers. 2. The frequency of the system clock must be decreased to not exceed the frequency of f_MSI range1. 3. The regulator is forced in low-power mode by software (LPRUN and LPSDSR bits set) DocID025942 Rev 5 146/874 163 Power control (PWR) RM0377 Exiting Low-power run mode To exit Low-power run mode proceed as follows: 6.3.5 1. The regulator is forced in Main regulator mode by software. 2. The Flash memory is switched on, if needed. 3. The frequency of the clock system can be increased. Entering low-power mode Low-power modes (except for Low-power run mode) are entered by executing the WFI (Wait For Interrupt) or WFE (Wait for Event) instructions, or when the SLEEPONEXIT bit in Cortex®-M0+ System Control register is set on Return from ISR. Entering low-power mode through WFI or WFE will be executed only is no interrupt and no event is pending. 6.3.6 Exiting low-power mode The microcontroller exists from Sleep and Stop mode depending on the way the mode was entered: If the WFI instruction or Return from ISR was used to enter the low-power mode, any peripheral interrupt acknowledged by the NVIC can wake up the device. This includes EXTI lines and any GPIO toggle. If the WFE instruction was used to enter low-power mode, the microcontroller exits the low-power mode as soon as an event occurs. The wakeup event can be generated either by: – An NVIC IRQ interrupt: This is done by enabling an interrupt in the peripheral control register but not in the NVIC, and by enabling the SEVONPEND bit in the Cortex®-M0+ System Control register. When the microcontroller resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. – An event: This is done by configuring an external or internal EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. 147/874 DocID025942 Rev 5 RM0377 6.3.7 Power control (PWR) Sleep mode I/O states in Sleep mode In Sleep mode, all I/O pins keep the same state as in Run mode. Entering Sleep mode The Sleep mode is entered according to Section 6.3.5: Entering low-power mode. Refer to Table 34: Sleep-now and Table 35: Sleep-on-exit for details on how to enter Sleep mode. Exiting Sleep mode The Sleep mode is exited according to Section 6.3.6: Exiting low-power mode. Refer to Table 34: Sleep-now and Table 35: Sleep-on-exit for more details on how to exit Sleep mode. Table 34. Sleep-now Sleep-now mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 0 and – No interrupt (for WFI) or event (for WFE) is pending Refer to the Cortex®-M0+ System Control register (see PM0223 programming manual). Mode entry On return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 and – No interrupt is pending Refer to the Cortex®-M0+ System Control register (see PM0223 programming manual). Mode exit If WFI or return from ISR was used for entry: Interrupt: refer to Table 50: List of vectors If WFE was used for entry and SVONPEND = 0 Wakeup event: refer to Section 12.3.2: Wakeup event management If WFE was used for entry and SVONPEND = 1 Interrupt event when disabled in NVIC (refer to Table 50: List of vectors) or wakeup event (refer to Section 12.3.2: Wakeup event management) Wakeup latency None DocID025942 Rev 5 148/874 163 Power control (PWR) RM0377 Table 35. Sleep-on-exit Sleep-on-exit Description WFI (wait for interrupt) while: – SLEEPDEEP = 0 and – No interrupt (for WFI) or event (for WFE) is pending Refer to the Cortex®-M0+ System Control register (see PM0223 programming manual). 6.3.8 Mode entry On return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 and – No interrupt is pending Refer to the Cortex®-M0+ System Control register (see PM0223 programming manual). Mode exit Interrupt: refer to Table 50: List of vectors Wakeup latency None Low-power sleep mode (LP sleep) I/O states in Low-power sleep mode In Low-power sleep mode, all I/O pins keep the same state as in Run mode. Entering Low-power sleep mode To enter Low-power sleep mode, proceed as follows: 1. The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. This reduces power consumption but increases the wake-up time. 2. Each digital IP clock must be enabled or disabled by using the RCC_APBxENR and RCC_AHBENR registers. 3. The frequency of the system clock must be decreased. 4. The regulator is forced in low-power mode by software (LPSDSR bits set). 5. Follow the steps described in Section 6.3.5: Entering low-power mode. Refer to Table 36: Sleep-now (Low-power sleep) and Table 37: Sleep-on-exit (Low-power sleep) for details on how to enter Low-power sleep mode. In Low-power sleep mode, the Flash memory can be switched off and the RAM memory remains available. In this mode, the system frequency should not exceed f_MSI range1. Please refer to product datasheet for more details on voltage regulator and peripherals operating conditions. Low-power sleep mode can only be entered when VCORE is in range 2. 149/874 DocID025942 Rev 5 RM0377 Note: Power control (PWR) To be able to read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. Exiting Low-power sleep mode The Low-power sleep mode is exited according to Section 6.3.6: Exiting low-power mode. When exiting Low-power sleep mode by issuing an interrupt or a wakeup event, the regulator is configured in Main regulator mode, the Flash memory is switched on (if necessary), and the system clock can be increased. When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Low-power sleep mode. Refer to Table 36: Sleep-now (Low-power sleep) and Table 37: Sleep-on-exit (Low-power sleep) for more details on how to exit Sleep low-power mode. Table 36. Sleep-now (Low-power sleep) Sleep-now mode Mode entry Description Voltage regulator in low-power mode and the Flash memory switched off WFI (Wait for Interrupt) or WFE (wait for event) while: – SLEEPDEEP = 0 and – No interrupt (for WFI) or event (for WFE) is pending Refer to the Cortex®-M0+ System Control register (see PM0223 programming manual). On return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 and – No interrupt is pending Refer to the Cortex®-M0+ System Control register (see PM0223 programming manual). Mode exit Voltage regulator in Main regulator mode and the Flash memory switched on If WFI or Return from ISR was used for entry: Interrupt: Refer to Table 50: List of vectors If WFE was used for entry and SEVONPEND = 0 Wakeup event: Refer to Section 12.3.2: Wakeup event management If WFE was used for entry and SVONPEND = 1 Interrupt event when disabled in NVIC (refer to Table 50: List of vectors) or wakeup event (refer to Section 12.3.2: Wakeup event management) Wakeup latency Regulator wakeup time from low-power mode DocID025942 Rev 5 150/874 163 Power control (PWR) RM0377 Table 37. Sleep-on-exit (Low-power sleep) Sleep-on-exit Description WFI (wait for interrupt) while: – SLEEPDEEP = 0 and – No interrupt (for WFI) or event (for WFE) is pending Refer to the Cortex®-M0+ System Control register (see PM0223 programming manual). 6.3.9 Mode entry On return from ISR while: – SLEEPDEEP = 0 and – SLEEPONEXIT = 1 and – No interrupt is pending Refer to the Cortex®-M0+ System Control register (see PM0223 programming manual). Mode exit Interrupt: refer to Table 50: List of vectors. Wakeup latency regulator wakeup time from low-power mode Stop mode The Stop mode is based on the Cortex®-M0+ Deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI16 (except if HSI16KERON is set in Stop mode, see Section 7.3.1: Clock control register (RCC_CR)) and the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved. To get the lowest consumption in Stop mode, the internal Flash memory also enters lowpower mode. When the Flash memory is in power-down mode, an additional startup delay is incurred when waking up from Stop mode. To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature sensor can be switched off before entering Stop mode. They can be switched on again by software after exiting Stop mode using the ULP bit in the PWR_CR register. I/O states in Low-power sleep mode In Stop mode, all I/O pins keep the same state as in Run mode. Entering Stop mode Refer to Section 6.3.5: Entering low-power mode and to Table 38 for details on how to enter the Stop mode. If the application needs to disable the external clock before entering Stop mode, the HSEON bit must be first disabled and the system clock switched to HSI16. Otherwise, if the HSEON bit is kept enabled while external clock (external oscillator) can be removed before entering Stop mode, the clock security system (CSS) feature must be enabled to detect any external oscillator failure and avoid a malfunction behavior when entering Stop mode. 151/874 DocID025942 Rev 5 RM0377 Power control (PWR) To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPSDSR or LPDS bit in the PWR_CR register (see Section 6.4.1). If Flash memory programming or an access to the APB domain is ongoing, the Stop mode entry is delayed until the memory or APB access has completed. In Stop mode, the following features can be selected by programming individual control bits: Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. Refer to Section 20.3: IWDG functional description in Section 20: Independent watchdog (IWDG). Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register (see Section 7.3.20). Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR register. External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the RCC_CSR register. The ADCcan also consume power in Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register must both be written to 0. Exiting Stop mode Refer to Section 6.3.6: Exiting low-power mode and to Table 38 for details on how to exit Stop mode. When exiting Stop mode by issuing an interrupt or a wakeup event, the MSI or HSI16 RC oscillator is selected as system clock depending the bit STOPWUCK in the RCC_CFGR register. When the voltage regulator operates in low-power mode, an additional startup delay is incurred when waking up from Stop mode. By keeping the internal regulator ON during Stop mode, the consumption is higher although the startup time is reduced. DocID025942 Rev 5 152/874 163 Power control (PWR) RM0377 Table 38. Stop mode Stop mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – No interrupt (for WFI) or event (for WFE) is pending. – SLEEPDEEP bit is set in Cortex®-M0+ System Control register – PDDS bit = 0 in Power Control register (PWR_CR) – WUF bit = 0 in Power Control/Status register (PWR_CSR) – MSI or HSI16 RC oscillator are selected as system clock for Stop mode exit by configuring the STOPWUCK bit in the RCC_CFGR register. Note: To enter the Stop mode, all EXTI Line pending bits (in Section 12.5.6: EXTI pending register (EXTI_PR)), all peripherals interrupt pending bits, the RTC Alarm (Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time-stamp flags, must be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues. Mode entry 153/874 On return from ISR while: – No interrupt is pending. – SLEEPDEEP bit is set in Cortex®-M0+ System Control register – SLEEPONEXIT = 1 – PDDS bit = 0 in Power Control register (PWR_CR) – WUF bit = 0 in Power Control/Status register (PWR_CSR) – MSI or HSI16 RC oscillator are selected as system clock for Stop mode exit by configuring the STOPWUCK bit in the RCC_CFGR register. Note: To enter the Stop mode, all EXTI Line pending bits (in Section 12.5.6: EXTI pending register (EXTI_PR)), all peripherals interrupt pending bits, the RTC Alarm (Alarm A and Alarm B), RTC wakeup, RTC tamper, and RTC time-stamp flags, must be reset. Otherwise, the Stop mode entry procedure is ignored and program execution continues. Mode exit If WFI or return from ISR was used for entry: Any EXTI Line configured in Interrupt mode (the corresponding EXTI Interrupt vector must be enabled in the NVIC). Refer to Table 50: List of vectors. If WFE was used for entry and SEVONPEND = 0 Any EXTI Line configured in event mode. Refer to Section 12.3.2: Wakeup event management on page 261 If WFE was used for entry and SEVONPEND = 1 – Any EXTI Line configured in event mode (even if the corresponding EXTI interrupt is disabled in the NVIC). The interrupt source can be an external interrupt or a peripheral with wakeup capability (refer to Table 50: List of vectors). – A wakeup event (refer to Section 12.3.2: Wakeup event management on page 261) Wakeup latency MSI or HSI16 RC wakeup time + regulator wakeup time from Low-power mode + FLASH wakeup time DocID025942 Rev 5 RM0377 6.3.10 Power control (PWR) Standby mode The Standby mode allows to achieve the lowest power consumption. It is based on the Cortex®-M0+ Deepsleep mode, with the voltage regulator disabled. The VCORE domain is consequently powered off. The PLL, the MSI, the HSI16 oscillator and the HSE oscillator are also switched off. SRAM and register contents are lost except for the RTC registers, RTC backup registers and Standby circuitry (see Figure 10). I/O states in Standby mode In Standby mode, all I/O pins are high impedance except for: Reset pad Wakeup pins (WKUP1, WKUP2, WKUP3) RTC functions (tamper, time-stamp, RTC Alarm out, RTC clock calibration out) on the following I/Os: – Category 1: PA0, PA2 – Category 2: PC13, PA0, PA2 – Category 3: PC13, PA0 – Category 5: PC13, PA0, PE6 Entering Standby mode Refer to Section 6.3.5: Entering low-power mode and to Table 39 for details on how to enter Standby mode. In Standby mode, the following features can be selected by programming individual control bits: Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a reset. Refer to Section 20.3: IWDG functional description on page 510. Real-time clock (RTC): this is configured by the RTCEN bit in the RCC_CSR register (see Section 7.3.20). Internal RC oscillator (LSI RC): this is configured by the LSION bit in the RCC_CSR register. External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the RCC_CSR register. Exiting Standby mode The microcontroller exits Standby mode when an external Reset (NRST pin), an IWDG Reset, a rising edge on WKUP pins (WUKP1, WKUP2 or WKUP3), an RTC alarm, a tamper event, or a time-stamp event is detected. All registers are reset after wakeup from Standby except for PWR power control/status register (PWR_CSR). After waking up from Standby mode, program execution restarts in the same way as after a Reset (boot pins sampling, vector reset is fetched, etc.). The SBF status flag in the PWR_CSR register (see Section 6.4.2) indicates that the MCU was in Standby mode. Refer to Section 6.3.6: Exiting low-power mode and to Table 39 for more details on how to exit Standby mode. DocID025942 Rev 5 154/874 163 Power control (PWR) RM0377 Table 39. Standby mode Standby mode Description WFI (Wait for Interrupt) or WFE (Wait for Event) while: – SLEEPDEEP = 1 in Cortex®-M0+ System Control register – PDDS = 1 bit in Power Control register (PWR_CR) – No interrupt (for WFI) or event (for WFE) is pending. – WUF = 0 bit in Power Control/Status register (PWR_CSR) – the RTC flag corresponding to the chosen wakeup source (RTC Alarm A, RTC Alarm B, RTC wakeup, Tamper or Time-stamp flags) is cleared Mode entry On return from ISR while: – SLEEPDEEP = 1 in Cortex®-M0+ System Control register – SLEEPONEXIT = 1 – PDDS bit = 1 in Power Control register (PWR_CR) – No interrupt is pending. – WUF bit = 0 in Power Control/Status register (PWR_CSR) – the RTC flag corresponding to the chosen wakeup source (RTC Alarm A, RTC Alarm B, RTC wakeup, Tamper or Time-stamp flags) is cleared. Mode exit WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup, tamper event, time-stamp event, external reset in NRST pin, IWDG reset. Wakeup latency Reset phase Debug mode By default, the debug connection is lost if the application puts the MCU in Stop or Standby mode while the debug features are used. This is due to the fact that the Cortex®-M0+ core is no longer clocked. However, by setting some configuration bits in the DBG_CR register, the software can be debugged even when using the low-power modes extensively. For more details, refer to Section 27.9.1: Debug support for low-power modes. 6.3.11 Waking up the device from Stop and Standby modes using the RTC and comparators The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC Wakeup event, a tamper event, a time-stamp event, or a comparator event, without depending on an external interrupt (Auto-wakeup mode). These RTC alternate functions can wake up the system from Stop and Standby low-power modes while the comparator events can only wake up the system from Stop mode. The system can also wake up from low-power modes without depending on an external interrupt (Auto-wakeup mode) by using the RTC alarm or the RTC wakeup events. 155/874 DocID025942 Rev 5 RM0377 Power control (PWR) The RTC provides a programmable time base for waking up from Stop or Standby mode at regular intervals. For this purpose, two of the three alternative RTC clock sources can be selected by programming the RTCSEL[1:0] bits in the RCC_CSR register (see Section 7.3.20): Low-power 32.768 kHz external crystal oscillator (LSE OSC). This clock source provides a precise time base with very low-power consumption (less than 1 µA added consumption in typical conditions) Low-power internal RC oscillator (LSI RC) This clock source has the advantage of saving the cost of the 32.768 kHz crystal. This internal RC Oscillator is designed to use minimum power consumption. RTC auto-wakeup (AWU) from the Stop mode To wake up from the Stop mode with an RTC alarm event, it is necessary to: a) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC Alarm interrupt in the RTC_CR register c) Configure the RTC to generate the RTC alarm To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to: a) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper Interrupt in the RTC_TCR register c) Configure the RTC to detect the tamper or time stamp event To wake up from the Stop mode with an RTC Wakeup event, it is necessary to: a) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) b) Enable the RTC Wakeup Interrupt in the RTC_CR register c) Configure the RTC to generate the RTC Wakeup event RTC auto-wakeup (AWU) from the Standby mode To wake up from the Standby mode with an RTC alarm event, it is necessary to: a) Enable the RTC Alarm interrupt in the RTC_CR register b) Configure the RTC to generate the RTC alarm To wake up from the Stop mode with an RTC Tamper or time stamp event, it is necessary to: a) Enable the RTC TimeStamp Interrupt in the RTC_CR register or the RTC Tamper Interrupt in the RTC_TCR register b) Configure the RTC to detect the tamper or time stamp event To wake up from the Stop mode with an RTC Wakeup event, it is necessary to: a) Enable the RTC Wakeup Interrupt in the RTC_CR register b) Configure the RTC to generate the RTC Wakeup event DocID025942 Rev 5 156/874 163 Power control (PWR) RM0377 Comparator auto-wakeup (AWU) from the Stop mode 157/874 To wake up from the Stop mode with a comparator 1 or comparator 2 wakeup event, it is necessary to: a) Configure the EXTI Line 21 for comparator 1 or EXTI Line 22 for comparator 2 (Interrupt or Event mode) to be sensitive to the selected edges (falling, rising or falling and rising) b) Configure the comparator to generate the event. DocID025942 Rev 5 RM0377 Power control (PWR) 6.4 Power control registers The peripheral registers have to be accessed by half-words (16-bit) or words (32-bit). 6.4.1 PWR power control register (PWR_CR) Address offset: 0x00 Reset value: 0x0000 1000 (reset by wakeup from Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LPDS rw 15 Res. 14 13 DS_EE LPRUN _KOFF rw rw Bits 31:17 Bit 16 12 11 VOS[1:0] rw rw 10 9 8 FWU ULP DBP rw rw rw 7 6 5 PLS[2:0] rw rw rw 4 3 2 PVDE CSBF CWUF rw rc_w1 rc_w1 1 0 PDDS LPSDSR rw rw Reserved, always read as 0. LPDS: Regulator in Low-power deepsleep mode This bit allows switching the regulator to low-power mode when the CPU enters Stop mode. Its behavior depends on LPSDSR bit. – if LPSDSR = 1: bit has no effect. – if LPSDSR = 0: 0: Voltage regulator in main mode during Deepsleep mode (Stop mode) 1: Voltage regulator switches to low-power mode when the CPU enters Deepsleep mode (Stop mode). The regulator goes back to main mode when the CPU exits from Deepsleep mode. Bit 15 Reserved, always read as 0. Bit 14 LPRUN: Low-power run mode When LPRUN bit is set together with the LPSDSR bit, the regulator is switched from main mode to low-power mode. Otherwise, it remains in main mode. The regulator goes back to operate in main mode when LPRUN is reset. If this bit is set (with LPSDSR bit set) and the CPU enters sleep or Deepsleep mode (LP sleep or Stop mode), then, when the CPU wakes up from these modes, it enters Run mode but with LPRUN bit set. To enter again Low-power run mode, it is necessary to perform a reset and set LPRUN bit again. It is forbidden to reset LPSDSR when the MCU is in Low-power run mode. LPSDSR is used as a prepositioning for the entry into low-power mode, indicating to the system which configuration of the regulator will be selected when entering low-power mode. The LPSDSR bit must be set before the LPRUN bit is set. LPSDSR can be reset only when LPRUN bit=0. 0: Voltage regulator in main mode in Low-power run mode 1: Voltage regulator in low-power mode in Low-power run mode Bits 13 DS_EE_KOFF: Deepsleep mode with non-volatile memory kept off When entering low-power mode (Stop or Standby only), if DS_EE_KOFF and RUN_PD bits are both set in FLASH_ACR register (refer to Section 3.7.1: Access control register (FLASH_ACR), the non-volatile memory (Flash program memory and data EEPROM) will not be woken up when exiting from Deepsleep mode. 0: NVM woken up when exiting from Deepsleep mode even if the bit RUN_PD is set 1: NVM not woken up when exiting from low-power mode (if the bit RUN_PD is set) DocID025942 Rev 5 158/874 163 Power control (PWR) Bits 12:11 Bit 10 VOS[1:0]: Voltage scaling range selection These bits are used to select the internal regulator voltage range. Before resetting the power interface by resetting the PWRRST bit in the RCC_APB1RSTR register, these bits have to be set to ‘10’ and the frequency of the system has to be configured accordingly. 00: forbidden (bits are unchanged and keep the previous value, no voltage change occurs) 01: 1.8 V (range 1) 10: 1.5 V (range 2) 11: 1.2 V (range 3) FWU: Fast wakeup This bit works in conjunction with ULP bit. If ULP = 0, FWU is ignored If ULP = 1 and FWU = 1: VREFINT startup time is ignored when exiting from low-power mode. The VREFINTRDYF flag in the PWR_CSR register indicates when the VREFINT is ready again. If ULP=1 and FWU = 0: Exiting from low-power mode occurs only when the VREFINT is ready (after its startup time). This bit is not reset by resetting the PWRRST bit in the RCC_APB1RSTR register. 0: Low-power modes exit occurs only when VREFINT is ready 1: VREFINT start up time is ignored when exiting low-power modes Bit 9 ULP: Ultra-low-power mode When set, the VREFINT is switched off in low-power mode. This bit is not reset by resetting the PWRRST bit in the RCC_APB1RSTR register. 0: VREFINT is on in low-power mode 1: VREFINT is off in low-power mode Bit 8 DBP: Disable backup write protection In reset state, the RTC, RTC backup registers and RCC CSR register are protected against parasitic write access. This bit must be set to enable write access to these registers. 0: Access to RTC, RTC Backup and RCC CSR registers disabled 1: Access to RTC, RTC Backup and RCC CSR registers enabled Note: If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, this bit must remain set to 1. Bits 7:5 Bit 4 159/874 RM0377 PLS[2:0]: PVD level selection These bits are written by software to select the voltage threshold detected by the power voltage detector: 000: 1.9 V 001: 2.1 V 010: 2.3 V 011: 2.5 V 100: 2.7 V 101: 2.9 V 110: 3.1 V 111: External input analog voltage (Compare internally to VREFINT) PVD_IN input (PB7) has to be configured as analog input when PLS[2:0] = 111. Note: Refer to the electrical characteristics of the datasheet for more details. PVDE: Power voltage detector enable This bit is set and cleared by software. 0: PVD disabled 1: PVD enabled DocID025942 Rev 5 RM0377 Power control (PWR) Bit 3 CSBF: Clear standby flag This bit is always read as 0. 0: No effect 1: Clear the SBF Standby flag (write). Bit 2 CWUF: Clear wakeup flag This bit is always read as 0. 0: No effect 1: Clear the WUF Wakeup flag after 2 system clock cycles Bit 1 PDDS: Power-down deepsleep This bit is set and cleared by software. 0: Enter Stop mode when the CPU enters Deepsleep. The regulator is in low-power mode. 1: Enter Standby mode when the CPU enters Deepsleep. Bit 0 LPSDSR: Low-power deepsleep/Sleep/Low-power run – DeepSleep/Sleep modes When this bit is set, the regulator switches in low-power mode when the CPU enters sleep or Deepsleep mode. The regulator goes back to main mode when the CPU exits from these modes. – Low-power run mode When this bit is set, the regulator switches in low-power mode when the bit LPRUN is set. The regulator goes back to main mode when the bit LPRUN is reset. This bit is set and cleared by software. 0: Voltage regulator on during Deepsleep/Sleep/Low-power run mode 1: Voltage regulator in low-power mode during Deepsleep/Sleep/Low-power run mode Note: If the sequence below is executed: 1) Low-power run 2) Low-power sleep 3) Run 4) Low-power run after returning from Low-power deepsleep/Sleep mode (step 2), the regulator goes back to main mode (step 3). Then to switch to Low-power run mode (step 4), it is necessary to perform a reset and set LPSDSR bit again. DocID025942 Rev 5 160/874 163 Power control (PWR) 6.4.2 RM0377 PWR power control/status register (PWR_CSR) Address offset: 0x04 Reset value: 0x0000 0008 (not reset by wakeup from Standby mode) Additional APB cycles are needed to read this register versus a standard APB read. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. EWUP 3 EWUP 2 EWUP 1 Res. REG LPF VOSF VREFIN TRDYF PVDO SBF WUF rw rw rw r r r r r r Res. Res. Res. Res. Res. Bits 31:11 Reserved, must be kept at reset value. Bit 10 EWUP3: Enable WKUP pin 3 This bit is set and cleared by software. 0: WKUP pin 3 is used for general purpose I/Os. An event on the WKUP pin 3 does not wakeup the device from Standby mode. 1: WKUP pin 3 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 3wakes-up the system from Standby mode). Note: This bit is reset by a system reset. Bit 9 EWUP2: Enable WKUP pin 2 This bit is set and cleared by software. 0: WKUP pin 2 is used for general purpose I/Os. An event on the WKUP pin 2 does not wakeup the device from Standby mode. 1: WKUP pin 2 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 2 wakes-up the system from Standby mode). Note: This bit is reset by a system reset. Bit 8 EWUP1: Enable WKUP pin 1 This bit is set and cleared by software. 0: WKUP pin 1 is used for general purpose I/Os. An event on the WKUP pin 1 does not wakeup the device from Standby mode. 1: WKUP pin 1 is used for wakeup from Standby mode and forced in input pull down configuration (rising edge on WKUP pin 1 wakes-up the system from Standby mode). Note: This bit is reset by a system reset. Bits 7:6 Reserved, must be kept at reset value. Bit 5 REGLPF: Regulator LP flag This bit is set by hardware when the MCU is in Low-power run mode. When the MCU exits from Low-power run mode, this bit stays at 1 until the regulator is ready in main mode. A polling on this bit is recommended to wait for the regulator main mode. This bit is reset by hardware when the regulator is ready. 0: Regulator is ready in main mode 1: Regulator voltage is in low-power mode 161/874 DocID025942 Rev 5 RM0377 Power control (PWR) Bit 4 VOSF: Voltage Scaling select flag A delay is required for the internal regulator to be ready after the voltage range is changed. The VOSF bit indicates that the regulator has reached the voltage level defined with bits VOS of PWR_CR register. This bit is reset when VOS[1:0] in PWR_CR register change. It is set once the regulator is ready. 0: Regulator is ready in the selected voltage range 1: Regulator voltage output is changing to the required VOS level. Bit 3 VREFINTRDYF: Internal voltage reference (VREFINT) ready flag This bit indicates the state of the internal voltage reference, VREFINT. 0: VREFINT is OFF 1: VREFINT is ready Bit 2 PVDO: PVD output This bit is set and cleared by hardware. It is valid only if PVD is enabled by the PVDE bit. 0: VDD is higher than the PVD threshold selected with the PLS[2:0] bits. 1: VDD is lower than the PVD threshold selected with the PLS[2:0] bits. Note: The PVD is stopped by Standby mode. For this reason, this bit is equal to 0 after Standby or reset until the PVDE bit is set. Bit 1 SBF: Standby flag This bit is set by hardware and cleared only by a POR/PDR (power-on reset/power-down reset) or by setting the CSBF bit in the PWR power control register (PWR_CR) 0: Device has not been in Standby mode 1: Device has been in Standby mode Bit 0 WUF: Wakeup flag This bit is set by hardware and cleared by a system reset or by setting the CWUF bit in the PWR power control register (PWR_CR) 0: No wakeup event occurred 1: A wakeup event was received from the WKUP pin or from the RTC alarm (Alarm A or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup). Note: An additional wakeup event is detected if the WKUP pins are enabled (by setting the EWUPx (x=1, 2, 3) bits) when the WKUP pin levels are already high. DocID025942 Rev 5 162/874 163 Power control (PWR) 6.4.3 RM0377 PWR register map The following table summarizes the PWR registers. CSBF CWUF PDDS LPSDSR 0 0 0 0 0 0 PVDO SBF WUF 0 PVDE 0 0 VOSF 0 Reset value 1 VREFINTRDYF 0 0 REGLPF 0 0 Res. Res. ULP DBP 0 EWUP1 LPRUN DS_EE_KOFF. LPDS FWU PWR_CSR 0 EWUP2 0x004 VOS [1:0] EWUP3 Reset value Res. PWR_CR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x000 Register Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 40. PWR - register map and reset values 0 0 1 0 0 0 PLS[2:0] 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. 163/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) 7 Reset and clock control (RCC) 7.1 Reset There are three types of reset, defined as system reset, power reset and RTC domain reset. 7.1.1 System reset A system reset sets all registers to their reset values except for the RTC, RTC backup registers and control/status registers (RCC_CR and RCC_CSR). A system reset is generated when one of the following events occurs: A low level on the NRST pin (external reset) Window watchdog end-of-count condition (WWDG reset) Independent watchdog end-of-count condition (IWDG reset) A software reset (SW reset) (see Software reset) Low-power management reset (see Low-power management reset) Option byte loader reset (see Option byte loader reset) Exit from Standby mode Firewall protection (see Section 5: Firewall (FW)) The reset source can be identified by checking the reset flags in the control/status register, RCC_CSR (see Section 7.3.20). Software reset The SYSRESETREQ bit in Cortex®-M0+ AIRCR register (Application Interrupt and Reset Control Register) must be set to force a software reset on the device. Refer to ARM® Cortex®-M0+ Technical Reference Manual for more details. Low-power management reset There are two ways to generate a low-power management reset: Reset generated when entering Standby mode: This type of reset is enabled by resetting nRST_STDBY bit in user option bytes. In this case, whenever a Standby mode entry sequence is successfully executed, the device is reset instead of entering Standby mode. Reset when entering Stop mode: This type of reset is enabled by resetting nRST_STOP bit in user option bytes. In this case, whenever a Stop mode entry sequence is successfully executed, the device is reset instead of entering Stop mode. Option byte loader reset The Option byte loader reset is generated when the OBL_LAUNCH bit (bit 18) is set in the FLASH_PECR register. This bit is used to launch by software the option byte loading. For further information on the user option bytes, refer to Section 3: Flash program memory and data EEPROM (FLASH). DocID025942 Rev 5 164/874 212 Reset and clock control (RCC) 7.1.2 RM0377 Power reset A power reset is generated when one of the following events occurs: Power-on/power-down reset (POR/PDR reset) BOR reset A power reset sets all registers to their reset values including for the RTC domain (see Figure 16) These sources act on the NRST pin and it is always kept low during the delay phase. The RESET service routine vector is fixed at address 0x0000_0004 in the memory map. For more details, refer to Table 50: List of vectors. The system reset signal provided to the device is output on the NRST pin (except the Exit from Standby reset which is not output on the NRST pin but generates system reset). The pulse generator guarantees a minimum reset pulse duration of 20 µs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low. Figure 16. Simplified diagram of the reset circuit 9''9''$ 538 ([WHUQDO UHVHW )LOWHU 1567 3XOVH JHQHUDWRU PLQV 6\VWHPUHVHW ::'*UHVHW ,:'*UHVHW 3RZHUUHVHW 6RIWZDUHUHVHW /RZSRZHUPDQDJHPHQW 2SWLRQ%\WH/RDGHUUHVHW )LUHZDOOUHVHW -36 7.1.3 RTC and backup registers reset The RTC peripheral, RTC clock source selection (in RCC_CSR) and the backup registers are reset only when one of the following events occurs: 165/874 A software reset, triggered by setting the RTCRST bit in the RCC_CSR register (see Section 7.3.20) Power reset (BOR/POR/PDR). DocID025942 Rev 5 RM0377 7.2 Reset and clock control (RCC) Clocks Four different clock sources can be used to drive the system clock (SYSCLK): HSI16 (high-speed internal) oscillator clock HSE (high-speed external) oscillator clock The HSE external quartz connexion is available only on cat. 2 devices in LQFP48 package. PLL clock MSI (multispeed internal) oscillator clock The MSI at 2.1MHz is used as system clock source after startup from power reset, system or RTC domain reset, and after wake-up from Standby mode. The HSI16, HSI16 divided by 4, or the MSI at any of its possible frequency can be used to wake up from Stop mode. The devices have two secondary clock sources: 37 kHz low speed internal RC (LSI RC) which drives the independent watchdog and optionally the RTC used for Auto-wakeup from Stop/Standby mode and the LPTIMER. 32.768 kHz low speed external crystal (LSE crystal) which optionally drives the realtime clock (RTCCLK), the LPTIMER and USARTs. Each clock source can be switched on or off independently when it is not used to optimize power consumption. Several prescalers can be used to configure the AHB frequency and the two APBs (APB1 and APB2) domains. The maximum frequency of AHB, APB1 and the APB2 domains is 32 MHz. It depends on the device voltage range. For more details refer to Section 6.1.4: Dynamic voltage scaling management. All the peripheral clocks are derived from the system clock (SYSCLK) except: The ADC can be derived either from the APB clock or the HSI16 clock. The LPUART1 and USART1/2 clock which is derived (selected by software) from one of the four following sources: – system clock – HSI16 clock – LSE clock – APB clock (PCLK) The I2C1 clock which is derived (selected by software) from one of the three following sources: – system clock – HSI16 clock – APB clock (PCLK) The LPTIMER clock which is derived (selected by software) from one of the four following sources: – HSI16 clock – LSE clock – LSI clock – APB clock (PCLK) The RTC clock which is derived from the following clock sources: DocID025942 Rev 5 166/874 212 Reset and clock control (RCC) RM0377 – LSE clock, – LSI clock, – 1 MHz HSE_RTC (HSE divided by a programmable prescaler). IWDG clock which is always the LSI clock. The system clock (SYSCLK) frequency must be higher or equal to the RTC clock frequency. The RCC feeds the Cortex® System Timer (SysTick) external clock with the AHB clock (HCLK) divided by 8. The SysTick can work either with this clock or with the Cortex® clock (HCLK), configurable in the SysTick Control and Status Register. 167/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) Figure 17. Clock tree #9 (QDEOH:DWFKGRJ /6,5& :DWFKGRJ/6 /6,WHPSR /HJHQG +6( +LJKVSHHGH[WHUQDOFORFNVLJQDO +6, +LJKVSHHGLQWHUQDOFORFNVLJQDO /6, /RZVSHHGLQWHUQDOFORFNVLJQDO /6( /RZVSHHGH[WHUQDOFORFNVLJQDO 06, 0XOWLVSHHGLQWHUQDOFORFNVLJQDO 57&6(/ 57&HQDEOH /6(26& 57& /6(WHPSR /68 /6' /6' #9 0+] #9 06,5& /6, /6( 06, /HYHOVKLIWHUV #9 0&26(/ $'&HQDEOH $'&&/. 0&2 QRWGHHSVOHHS #9 +6,5& /HYHOVKLIWHUV #9 &.B3:5 QRWGHHSVOHHS FNBUFKV +6, 6\VWHP &ORFN 06, +6, +6( #9 +6(26& /HYHOVKLIWHUV #9 3//65& /68 #9 0+]&ORFN 'HWHFWRU #9 3//&/. QRWVOHHSRU GHHSVOHHS +&/. 7,0[&/. $+% 35(6& « ; 3&/.WR$3% SHULSKHUDOV $3% 35(6& 3HULSKHUDO FORFNHQDEOH WR7,0[ ,I$3%SUHVF [ HOVH[ /6' )&/. FNBSOOLQ 3// /HYHOVKLIWHUV #9''&25( +6(SUHVHQWRUQRW QRWVOHHSRU GHHSVOHHS &ORFN 6RXUFH &RQWURO $3% 35(6& 3HULSKHUDO FORFNHQDEOH 3&/.WR$3% 0+] SHULSKHUDOV PD[ 3HULSKHUDO FORFNHQDEOH ,I$3%SUHVF [ HOVH[ /6, /6( +6, 6<6&/. 3&/. WR7,0[ 3HULSKHUDOV HQDEOH 3HULSKHUDOV HQDEOH /37,0&/. 3HULSKHUDOV HQDEOH /38$57 8$57&/. ,&&/. 06Y9 1. For full details about the internal and external clock source characteristics, please refer to the “Electrical characteristics” section in your device datasheet. DocID025942 Rev 5 168/874 212 Reset and clock control (RCC) RM0377 The timer clock frequencies are automatically fixed by hardware. There are two cases: 1. If the APB prescaler is 1, the timer clock frequencies are set to the same frequency as that of the APB domain to which the timers are connected. 2. Otherwise, they are set to twice (×2) the frequency of the APB domain to which the timers are connected. fCLK acts as Cortex®-M0+ free running clock. For more details refer to the Section 27: Debug support (DBG). 7.2.1 HSE clock The high speed external clock signal (HSE) can be generated from two possible clock sources: HSE external crystal/ceramic resonator HSE user external clock The resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. The loading capacitance values must be adjusted according to the selected oscillator. Figure 18. HSE/ LSE clock sources Clock source External clock for category 2 (LQFP48 only), category 3 and 5 devices Hardware configuration 26&B,1 26&B287 *3,2 ([WHUQDO VRXUFH 06Y9 169/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) Figure 18. HSE/ LSE clock sources Clock source Hardware configuration External clock for category 1 and 2 devices (packages with less that 48 pins) &.B,1 *3,2 ([WHUQDO VRXUFH 06Y9 26&B,1 Crystal/Ceramic resonators (for category 2, 3 and 5 devices) &/ 26&B287 /RDG FDSDFLWRUV &/ 06Y9 External source (HSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 32 MHz. This mode is selected by setting the HSEBYP and HSEON bits in the RCC_CR register (see Section 7.3.1: Clock control register (RCC_CR)). The external clock signal with ~50% duty cycle has to drive the following pin (see Figure 18): Note: On devices where OSC_IN and OSC_OUT pins are available: the OSC_IN pin must be driven while the OSC_OUT pin should be left hi-Z. Otherwise, the CK_IN pin must be driven. For details on pin availability, refers to the pinout section in your device datasheet. The external clock signal can be square, sinus or triangle. To minimize the consumption, it is recommended to use the square signal. External crystal/ceramic resonator (HSE crystal) The 1 to 24 MHz external oscillator has the advantage of producing a very accurate rate on the main clock. The associated hardware configuration is shown in Figure 18. Refer to the electrical characteristics section of the datasheet for more details. The HSERDY flag of the RCC_CR register (see Section 7.3.1) indicates whether the HSE oscillator is stable or not. At startup, the HSE clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC_CR register. The HSE Crystal can be switched on and off using the HSEON bit in the RCC_CR register. DocID025942 Rev 5 170/874 212 Reset and clock control (RCC) RM0377 For code example, refer to A.4.1: HSE start sequence code example. 7.2.2 HSI16 clock The HSI16 clock signal is generated from an internal 16 MHz RC oscillator. It can be used directly as a system clock or as PLL input. The HSI16 clock can be used after wake-up from the Stop low-power mode, this ensure a smaller wake-up time than a wake-up using MSI clock. The HSI16 RC oscillator has the advantage of providing a clock source at low cost (no external components). It also has a faster startup time than the HSE crystal oscillator however, even with calibration the frequency is less accurate than an external crystal oscillator or ceramic resonator. The HSI16 clock can be kept running in Stop mode by setting HSI16KERON bit in RCC_CR register (see Section 7.3.1: Clock control register (RCC_CR)). In this case the HSI16 clock can be used for dedicated peripherals which can run in Stop mode. Calibration RC oscillator frequencies can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at an ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the HSI16CAL[7:0] bits in the Internal Clock Sources Calibration Register (RCC_ICSCR) (see Section 7.3.2). If the application is subject to voltage or temperature variations, this may affect the RC oscillator speed. You can trim the HSI16 frequency in the application by using the HSI16TRIM[4:0] bits in the RCC_ICSCR register. For more details on how to measure the HSI16 frequency variation please refer to Section 7.2.14: Internal/external clock measurement using TIM21. The HSI16RDY flag in the RCC_CR register indicates whether the HSI16 oscillator is stable or not. At startup, the HSI16 RC output clock is not released until this bit is set by hardware. The HSI16 RC oscillator can be switched on and off using the HSI16ON bit in the RCC_CR register. 7.2.3 MSI clock The MSI clock signal is generated from an internal RC oscillator. Its frequency range can be adjusted by software by using the MSIRANGE[2:0] bits in the RCC_ICSCR register (see Section 7.3.2: Internal clock sources calibration register (RCC_ICSCR)). Seven frequency ranges are available: 65.536 kHz, 131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz. The MSI clock is always used as system clock after restart from Reset and wake-up from Standby. After wake-up from Stop mode, the MSI clock can be selected as system clock instead of HSI16 (or HSI16/4). When the device restarts after a reset or a wake-up from Standby, the MSI frequency is set to its default value. The MSI frequency does not change after waking up from Stop. The MSI RC oscillator has the advantage of providing a low-cost (no external components) low-power clock source. It is used as wake-up clock in low-power modes to reduce power consumption. 171/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) The MSIRDY flag in the RCC_CR register indicates whether the MSI RC is stable or not. At startup, the MSI RC output clock is not released until this bit is set by hardware. The MSI RC can be switched on and off by using the MSION bit in the RCC_CR register (see Section 7.3.1). It can also be used as a backup clock source (auxiliary clock) if the HSE crystal oscillator fails. Refer to Section 7.2.9: HSE clock security system (CSS) on page 174. Calibration The MSI RC oscillator frequency can vary from one chip to another due to manufacturing process variations, this is why each device is factory calibrated by ST for 1% accuracy at an ambient temperature, TA, of 25 °C. After reset, the factory calibration value is loaded in the MSICAL[7:0] bits in the RCC_ICSCR register. If the application is subject to voltage or temperature variations, this may affect the RC oscillator speed. You can trim the MSI frequency in the application by using the MSITRIM[7:0] bits in the RCC_ICSCR register. For more details on how to measure the MSI frequency variation please refer to Section 7.2.14: Internal/external clock measurement using TIM21. 7.2.4 PLL The internal PLL can be clocked by the HSI16 RC or HSE clocks. The PLL input clock frequency must range between 2 and 24 MHz. The desired frequency is obtained by using the multiplication factor and output division embedded in the PLL: Note: The system clock is derived from the PLL VCO divided by the output division factor. The application software must set correctly the PLL multiplication factor to avoid exceeding 96 MHz as PLLVCO when the product is in range 1, 48 MHz as PLLVCO when the product is in range 2, 24 MHz when the product is in range 3. It must also set correctly the output division to avoid exceeding 32 MHz as SYSCLK. The minimum input clock frequency for PLL is 2 MHz (when using HSE as PLL source). The PLL configuration (selection of the source clock, multiplication factor and output division factor) must be performed before enabling the PLL. Once the PLL is enabled, these parameters cannot be changed. To modify the PLL configuration, proceed as follows: 1. Disable the PLL by setting PLLON to 0. 2. Wait until PLLRDY is cleared. The PLL is now fully stopped. 3. Change the desired parameter. 4. Enable the PLL again by setting PLLON to 1. An interrupt can be generated when the PLL is ready if enabled in the RCC_CIER register (see Section 7.3.4). For code example, refer to A.4.2: PLL configuration modification code example. DocID025942 Rev 5 172/874 212 Reset and clock control (RCC) 7.2.5 RM0377 LSE clock The LSE crystal is a 32.768 kHz low speed external crystal or ceramic resonator. It has the advantage of providing a low-power but highly accurate clock source to the real-time clock peripheral (RTC) for clock/calendar or other timing functions. The LSE crystal is switched on and off through the LSEON bit in the RCC_CSR register (see Section 7.3.20). The crystal oscillator driving strength can be changed at runtime through the LSEDRV[1:0] bits of the RCC_CSR register to obtain the best compromise between robustness and short start-up time on one hand and low power consumption on the other hand. The driving capability can be changed dynamically between the different drive level, except when the low drive mode is reached. In this case it can only be changed to another mode through a power-on reset or an RTC reset. The LSERDY flag in the RCC_CSR register indicates whether the LSE crystal is stable or not. At startup, the LSE crystal output clock signal is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC_CIER register (see Section 7.3.4). External source (LSE bypass) In this mode, an external clock source must be provided. It can have a frequency of up to 1 MHz. This mode is selected by setting the LSEBYP and LSEON bits in the RCC_CSR (see Section 7.3.1). The external clock signal (square, sinus or triangle) with ~50% duty cycle has to drive the OSC32_IN pin while the OSC32_OUT pin should be left Hi-Z (see Figure 18). 7.2.6 LSI clock The LSI RC acts as an low-power clock source that can be kept running in Stop and Standby mode for the independent watchdog (IWDG). The clock frequency is around 37 kHz. The LSI RC oscillator can be switched on and off using the LSION bit in the RCC_CSR register (see Section 7.3.20). The LSIRDY flag in RCC_CSR indicates whether the low-speed internal oscillator is stable or not. At startup, the clock is not released until this bit is set by hardware. An interrupt can be generated if enabled in the RCC_CIER (see Section 7.3.4). Since the IWDG is activated, the LSI oscillator cannot be stopped by LSION=0. The LSI oscillator is stopped by system reset (except if IWDG is enabled by hardware option through WDG_SW option bit in FLASH_OPTR register). If the IWDG was enabled by software, then the LSI oscillator must be enabled again after system reset to ensure correct IWDG and/or RTC operation. LSI measurement The frequency dispersion of the LSI oscillator can be measured to have accurate RTC time base and/or IWDG timeout (when LSI is used as clock source for these peripherals) with an acceptable accuracy. For more details, refer to the electrical characteristics section of the datasheets. For more details on how to measure the LSI frequency, please refer to Section 7.2.14: Internal/external clock measurement using TIM21. 173/874 DocID025942 Rev 5 RM0377 7.2.7 Reset and clock control (RCC) System clock (SYSCLK) selection Four different clock sources can be used to drive the system clock (SYSCLK): The HSI16 oscillator The HSE oscillator The PLL The MSI oscillator clock (default after reset) When a clock source is used directly or through the PLL as system clock, it is not possible to stop it. A switch from one clock source to another occurs only if the target clock source is ready (clock stable after startup delay or PLL locked). If a clock source which is not yet ready is selected, the switch will occur when the clock source will be ready. Status bits in the RCC_CR register indicate which clock(s) is (are) ready and which clock is currently used as system clock. 7.2.8 System clock source frequency versus voltage range The following table gives the different clock source maximum frequencies depending on the product voltage range. Table 41. System clock source frequency Product voltage range Clock frequency MSI HSI16 HSE PLL HSE 32 MHz (external clock) or 24 MHz (crystal) 32 MHz (PLLVCO max = 96 MHz) Range 1 (1.8 V) 4.2 MHz 16 MHz Range 2 (1.5 V) 4.2 MHz 16 MHz 16 MHz 16 MHz (PLLVCO max = 48 MHz) Range 3 (1.2 V) 4.2 MHz NA 8 MHz 4 MHz (PLLVCO max = 24 MHz) 7.2.9 HSE clock security system (CSS) The Clock security system can be activated on the HSE by software. In this case, the clock detector is enabled after the HSE oscillator startup delay, and disabled when this oscillator is stopped. If an HSE clock failure is detected, this oscillator is automatically disabled and an CSSHSEI interrupt (Clock Security System Interrupt) is generated to inform the software of the failure, thus allowing the MCU to perform rescue operations. The CSSHSEI is linked to the Cortex®-M0+ NMI (Non-Maskable Interrupt) exception vector. Note: Once the CSSHSE is enabled, if the HSE clock fails, the CSSHSE interrupt occurs and an NMI is automatically generated. The NMI is executed indefinitely unless the CSSHSE interrupt pending bit is cleared. As a consequence, the NMI interrupt service routine (ISR) must clear the CSSHSE interrupt by setting the CSSHSEC bit in the RCC_CICR register. DocID025942 Rev 5 174/874 212 Reset and clock control (RCC) RM0377 If the HSE oscillator is used directly or indirectly as the system clock (indirectly means: it is used as PLL input clock, and the PLL clock is used as system clock), a detected failure causes a switch of the system clock and the disabling of the HSE oscillator. If the HSE oscillator clock is the clock entry of the PLL used as system clock when the failure occurs, the PLL is disabled too. When an HSE failure occurs, the system clock can be switched to the MSI or to the internal 16-MHz HSI clock depending on the value of STOPWUCK bit in the RCC_CFGR register. Note: Category 1 devices do not feature HSE clock security system. The HSE clock is available only in bypass mode. 7.2.10 LSE Clock Security System Clock Security System can be activated on the LSE by software. This is done by writing the CSSLSEON bit in the RCC_CSR register. This bit can be disabled by a hardware reset, an RTC software reset, or after an LSE clock failure detection. CSSLSEON bit must be written after the LSE and LSI clocks are enabled (LSEON and LSION set) and ready (LSERDY and LSIRDY bits set by hardware), and after the RTC clock has been selected through the RTCSEL bit. The LSE CSS works in all modes: run, Sleep, Stop and Standby. If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied to the RTC but the content of the registers does not change. A wakeup is generated in Standby mode. In any other modes, an interrupt can be sent to wake-up the software (see Section 7.3.4). The software MUST then reset the CSSLSEON bit and stop the defective 32 kHz oscillator by resetting LSEON bit. It can change the RTC clock source (LSI, HSE or no clock) through the RTCSEL bit, or take any required action to secure the application. 7.2.11 RTC clock The RTC has the same clock source which can be either the LSE, the LSI, or the HSE 1 MHz clock (HSE divided by a programmable prescaler). It is selected by programming the RTCSEL[1:0] bits in the RCC_CSR register (see Section 7.3.20) and the RTCPRE[1:0] bits in the RCC_CR register (see Section 7.3.1). Once the RTC clock source have been selected, the only possible way of modifying the selection is to set the RTCRST bit in the RCC_CSR register, or by a POR. If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and Standby low-power modes, and can be used as wakeup source. However, when the HSE is the RTC clock source, the RTC cannot be used in the Stop and Standby low-power modes. When the RTC is clocked by the LSE, the RTC remains clocked and functional under system reset. Note: To be able to read the RTC calendar register when the APB1 clock frequency is less than seven times the RTC clock frequency (7*RTCLCK), the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. 175/874 DocID025942 Rev 5 RM0377 7.2.12 Reset and clock control (RCC) Watchdog clock If the Independent watchdog (IWDG) is started by either hardware option or software access, the LSI oscillator is forced ON and cannot be disabled. After the LSI oscillator temporization, the clock is provided to the IWDG. If the IWDG was enabled by software, the LSI clock is disabled after system reset. The LSI oscillator must then be enabled again to ensure correct IWDG operation. 7.2.13 Clock-out capability The microcontroller clock output (MCO) capability allows the clock to be output onto the external MCO pin using a configurable prescaler (1, 2, 4, 8, or 16). The configuration registers of the corresponding GPIO port must be programmed in alternate function mode. One of 7 clock signals can be selected as the MCO clock: SYSCLK HSI16 MSI HSE PLL LSI LSE The selection is controlled by the MCOSEL[3:0] bits of the RCC_CFGR register (see Section 7.3.19). For code example, refer to A.4.3: MCO selection code example. 7.2.14 Internal/external clock measurement using TIM21 It is possible to indirectly measure the frequency of all on-board clock source generators by means of the TIM21 channel 1 input capture, as represented on Figure 19. Figure 19. Using TIM21 channel 1 input capture to measure frequencies 7,B503>@ *3,2 06, /6, +6(B57& /6( 7,0 7, (75 /6( 7, *3,2 069 TIM21 has an input multiplexer that selects which of the I/O or the internal clock is to trigger the input capture. This selection is performed through the TI1_RMP [2:0] bits in the TIM21_OR register. DocID025942 Rev 5 176/874 212 Reset and clock control (RCC) RM0377 The primary purpose of connecting the LSE to the channel 1 input capture is to be able to accurately measure the HSI16 and MSI system clocks (for this, either the HSI16 or MSI should be used as the system clock source). The number of HSI16 (MSI, respectively) clock counts between consecutive edges of the LSE signal provides a measure of the internal clock period. Taking advantage of the high precision of LSE crystals (typically a few tens of ppm’s), it is possible to determine the internal clock frequency with the same resolution, and trim the source to compensate for manufacturing-process- and/or temperature- and voltagerelated frequency deviations. The MSI and HSI16 oscillators both have dedicated user-accessible calibration bits for this purpose. The basic concept consists in providing a relative measurement (e.g. the HSI16/LSE ratio): the precision is therefore closely related to the ratio between the two clock sources. The higher the ratio, the better the measurement. It is however not possible to have a good enough resolution when the MSI clock is low (typically below 1 MHz). In this case, it is advised to: accumulate the results of several captures in a row use the timer’s input capture prescaler (up to 1 capture every 8 periods) use the RTC_OUT signal at 512 Hz (when the RTC is clocked by the LSE) as the input for the channel1 input capture. This improves the measurement precision TIM21 can also be used to measure the LSI, MSI, or HSE_RTC: this is useful for applications with no crystal. The ultra-low-power LSI oscillator has a wide manufacturing process deviation: by measuring it as a function of the HSI16 clock source, its frequency can be determined with the precision of the HSI16.The HSE_RTC frequency (HSE divided by a programmable prescaler) being relatively high (1 MHz), the relative frequency measurement is not very accurate. Its main purpose is consequently to obtain a rough indication of the external crystal frequency. This can be useful to meet the requirements of the IEC 60730/IEC 61335 standards, which require to be able to determine harmonic or subharmonic frequencies (–50/+100% deviations). 7.2.15 Clock-independent system clock sources for TIM2/TIM21/TIM22 In a number of applications using the 32.768 kHz clock as RTC timebase, timebases completely independently from the system clock are useful. This allows to schedule tasks without having to take into account the processor state (the processor may be stopped or executing at low, medium or full speed). For this purpose, the LSE clock is internally redirected to the 3 timers’ ETR inputs, which are used as additional clock sources. This gives up to three independent time bases (using the auto-reload feature) with 1 or 2 compare additional channels for fractional events. For instance, the TIM21 auto-reload interrupt can be programmed for a 1 second tick interrupt with an additional interrupt occurring 250 ms after the main tick. Note: 177/874 In this configuration, make sure that you have at least a ratio of 2 between the external clock (LSE) and the APB clock. If the application uses an APB clock frequency lower than twice the LSE clock frequency (typically LSE = 32.768 kHz, so twice LSE = 65.536 kHz), it is mandatory to use the external trigger prescaler feature of the timer: it can divide the ETR clock by up to 8. DocID025942 Rev 5 RM0377 Reset and clock control (RCC) 7.3 RCC registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. 7.3.1 Clock control register (RCC_CR) Address offset: 0x00 System Reset value: 0b0000 0000 00XX 0X00 0000 0011 0000 0000 where X is undefined Power-on reset value: 0x0000 0300 Access: no wait state, word, half-word and byte access 31 Res. 15 Res. 30 Res. 14 Res. 29 Res. 13 Res. 28 Res. 12 Res. 27 Res. 11 Res. 26 25 Res. PLL RDY 24 PLLON r rw 10 9 8 Res. MSI RDY MSION r rw 23 Res. 22 Res. 21 RTCPRE[1:0] rw 7 Res. 20 rw 19 18 17 16 CSSHS EON. HSE BYP HSE RDY HSE ON rw rw r rw 6 5 4 3 2 1 0 Res. HSI16 OUTEN HSI16 DIVF HSI16 DIVEN HSI16 RDYF. HSI16K ERON HSI16 ON rw r rw r rw rw Bits 31:26 Reserved, must be kept at reset value. Bit 25 PLLRDY: PLL clock ready flag This bit is set by hardware to indicate that the PLL is locked. 0: PLL unlocked 1: PLL locked Bit 24 PLLON: PLL enable bit This bit is set and cleared by software to enable PLL. Cleared by hardware when entering Stop or Standby mode. This bit can not be reset if the PLL clock is used as system clock or is selected to become the system clock. 0: PLL OFF 1: PLL ON Bits 23:22 Reserved, must be kept at reset value. Bits 21:20 RTCPRE[1:0] RTC prescaler These bits are set and reset by software to obtain a 1 MHz clock from HSE. This prescaler cannot be modified if HSE is enabled (HSEON = 1).These bits are reset by a power -on reset,. Their value is not modified by a system reset. 00: HSE is divided by 2 for RTC clock 01: HSE is divided by 4 for RTC clock 10: HSE is divided by 8 for RTC clock 11: HSE is divided by 16 for RTC clock Bit 19 CSSHSEON: Clock security system on HSE enable bit This bit is set by software to enable the clock security system (CSS) on HSE. This bit is "set only" (disabled by system reset). When CSSHSEON is set, the clock detector is enabled by hardware when the HSE oscillator is ready, and disabled by hardware if an oscillator failure is detected. 0: Clock security system OFF (clock detector OFF) 1: Clock security system ON (clock detector ON if HSE oscillator is stable, OFF otherwise) DocID025942 Rev 5 178/874 212 Reset and clock control (RCC) RM0377 Bit 18 HSEBYP: HSE clock bypass bit This bit is set and cleared by software to bypass the oscillator with an external clock. The external clock must be enabled with the HSEON bit, to be used by the device. The HSEBYP bit can be written only if the HSE oscillator is disabled. This bit is reset by power-on reset. Its value is not modified by system reset 0: HSE oscillator not bypassed 1: HSE oscillator bypassed with an external clock Bit 17 HSERDY: HSE clock ready flag This bit is set by hardware to indicate that the HSE oscillator is stable. After the HSEON bit is cleared, HSERDY goes low after 6 HSE oscillator clock cycles. 0: HSE oscillator not ready 1: HSE oscillator ready Bit 16 HSEON: HSE clock enable bit This bit is set and cleared by software. Cleared by hardware to stop the HSE oscillator when entering Stop or Standby mode. This bit cannot be reset if the HSE oscillator is used directly or indirectly as the system clock. 0: HSE oscillator OFF 1: HSE oscillator ON Bits 15:10 Reserved, must be kept at reset value. Bit 9 MSIRDY: MSI clock ready flag This bit is set by hardware to indicate that the MSI oscillator is stable. 0: MSI oscillator not ready 1: MSI oscillator ready Note: Once the MSION bit is cleared, MSIRDY goes low after 6 MSI clock cycles. Bit 8 MSION: MSI clock enable bit This bit is set and cleared by software. Set by hardware to force the MSI oscillator ON when exiting from Stop or Standby mode, or in case of a failure of the HSE oscillator used directly or indirectly as system clock. This bit cannot be cleared if the MSI is used as system clock. 0: MSI oscillator OFF 1: MSI oscillator ON Bits 7:6 Reserved, must be kept at reset value. Bit 5 HSI16OUTEN: 16 MHz high-speed internal clock output enable This bit is set and cleared by software. When this bit is set, TIM2 ETR input is connected to the 16 MHz HSI output clock (HSI16) provided ETR_RMP is set to 011 in TIM2 option register (TIM2_OR). This bit can be written anytime by the application. 0: HSI16 output clock disabled 1: HSI16 output clock enabled Bit 4 HSI16DIVF HSI16 divider flag This bit is set and reset by hardware. As a write in HSI16DIVEN has not an immediate effect on the frequency, this flag indicates the current status of the HSI16 divider. 0: 16 MHz HSI clock not divided 1: 16 MHz HSI clock divided by 4 Bit 3 HSI16DIVEN HSI16 divider enable bit This bit is set and reset by software to enable/disable the 16 MHz HSI divider by 4. It can be written anytime. 0: no 16 MHz HSI division requested 1: 16 MHz HSI division by 4 requested 179/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) Bit 2 HSI16RDYF: Internal high-speed clock ready flag This bit is set by hardware to indicate that the HSI 16 MHz oscillator is stable. This bit is set to ‘1’ only if the HSI 16 MHz oscillator is enabled by HSI16KERON or by IP request. After the HSI16ON bit is cleared, HSI16RDY goes low after 6 HSI16 clock cycles. 0: HSI 16 MHz oscillator not ready 1: HSI 16 MHz oscillator ready Bit 1 HSI16KERON: High-speed internal clock enable bit for some IP kernels This bit is set and reset by software to force the HSI 16 MHz oscillator ON, even in Stop mode, so that it can be quickly available as kernel clock for USARTs or I2C1. This bit has no effect on the value of HSI16ON. 0: HSI 16 MHz oscillator not forced ON 1: HSI 16 MHz oscillator forced ON even in Stop mode Bit 0 HSI16ON: 16 MHz high-speed internal clock enable This bit is set and cleared by software. It cannot be cleared if the 16 MHz HSI is used directly or indirectly as system clock. 0: HSI16 oscillator OFF 1: HSI16 oscillator ON DocID025942 Rev 5 180/874 212 Reset and clock control (RCC) 7.3.2 RM0377 Internal clock sources calibration register (RCC_ICSCR) Address offset: 0x04 Reset value: 0x00XX B0XX where X is undefined. Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 MSITRIM[7:0] 20 19 18 17 16 MSICAL[7:0] rw rw rw rw rw rw rw rw r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw r r r r r r MSIRANGE[2:0] rw rw HSI16TRIM[4:0] rw HSI16CAL[7:0] r r Bits 31:24 MSITRIM[7:0]: MSI clock trimming These bits are set by software to adjust MSI calibration. These bits provide an additional user-programmable trimming value that is added to the MSICAL[7:0] bits. They can be programmed to compensate for the variations in voltage and temperature that influence the frequency of the internal MSI RC. Bits 23:16 MSICAL[7:0]: MSI clock calibration These bits are automatically initialized at startup. Bits 15:13 MSIRANGE[2:0]: MSI clock ranges These bits are set by software to choose the frequency range of MSI.7 frequency ranges are available: 000: range 0 around 65.536 kHz 001: range 1 around 131.072 kHz 010: range 2 around 262.144 kHz 011: range 3 around 524.288 kHz 100: range 4 around 1.048 MHz 101: range 5 around 2.097 MHz (reset value) 110: range 6 around 4.194 MHz 111: not allowed Bits 12:8 HSI16TRIM[4:0]: High speed internal clock trimming These bits provide an additional user-programmable trimming value that is added to the HSI16CAL[7:0] bits. They can be programmed to compensated for the variations in voltage and temperature that influence the frequency of the internal HSI16 RC. Bits 7:0 HSI16CAL[7:0] Internal high speed clock calibration These bits are initialized automatically at startup. 181/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) 7.3.3 Clock configuration register (RCC_CFGR) Address offset: 0x0C Reset value: 0x0000 0000 Access: 0 wait state 2, word, half-word and byte access 1 or 2 wait states inserted only if the access occurs during clock source switch. 31 30 Res. 29 28 27 MCOPRE[2:0] 26 25 24 MCOSEL[3:0] 23 22 21 PLLDIV[1:0] 20 19 18 PLLMUL[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 STOP WUCK. Res. rw PPRE2[2:0] rw rw PPRE1[2:0] rw rw rw HPRE[3:0] rw rw rw rw 17 16 Res. PLL SRC rw 1 SWS[1:0] rw r r 0 SW[1:0] rw rw Bits 31 Reserved, must be kept at reset value. Bits 30:28 MCOPRE[2:0]: Microcontroller clock output prescaler These bits are set and cleared by software. It is highly recommended to change this prescaler before MCO output is enabled. 000: MCO is divided by 1 001: MCO is divided by 2 010: MCO is divided by 4 011: MCO is divided by 8 100: MCO is divided by 16 Others: not allowed Bits 27:24 MCOSEL[3:0]: Microcontroller clock output selection These bits are set and cleared by software. 0000: MCO output disabled, no clock on MCO 0001: SYSCLK clock selected 0010: HSI16 oscillator clock selected 0011: MSI oscillator clock selected 0100: HSE oscillator clock selected 0101: PLL clock selected 0110: LSI oscillator clock selected 0111: LSE oscillator clock selected 1000: Reserved Others: reserved Note: This clock output may have some truncated cycles at startup or during MCO clock source switching. Bits 23:22 PLLDIV[1:0]: PLL output division These bits are set and cleared by software to control PLL output clock division from PLL VCO clock. These bits can be written only when the PLL is disabled. 00: not allowed 01: PLL clock output = PLLVCO / 2 10: PLL clock output = PLLVCO / 3 11: PLL clock output = PLLVCO / 4 DocID025942 Rev 5 182/874 212 Reset and clock control (RCC) RM0377 Bits 21:18 PLLMUL[3:0]: PLL multiplication factor These bits are written by software to define the PLL multiplication factor to generate the PLL VCO clock. These bits can be written only when the PLL is disabled. 0000: PLLVCO = PLL clock entry x 3 0001: PLLVCO = PLL clock entry x 4 0010: PLLVCO = PLL clock entry x 6 0011: PLLVCO = PLL clock entry x 8 0100: PLLVCO = PLL clock entry x 12 0101: PLLVCO = PLL clock entry x 16 0110: PLLVCO = PLL clock entry x 24 0111: PLLVCO = PLL clock entry x 32 1000: PLLVCO = PLL clock entry x 48 others: not allowed Caution: The PLL VCO clock frequency must not exceed 96 MHz when the product is in Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is in Range 3. Bit 17 Reserved, must be kept at reset value. Bit 16 PLLSRC: PLL entry clock source This bit is set and cleared by software to select PLL clock source. This bit can be written only when PLL is disabled. 0: HSI16 oscillator clock selected as PLL input clock 1: HSE oscillator clock selected as PLL input clock Note: The PLL minimum input clock frequency is 2 MHz. Bit 15 STOPWUCK: Wake-up from Stop clock selection This bit is set and cleared by software to select the wake-up from Stop clock. 0: internal 64 KHz to 4 MHz (MSI) oscillator selected as wake-up from Stop clock 1: internal 16 MHz (HSI16) oscillator selected as wake-up from Stop clock (or HSI16/4 if HSI16DIVEN=1) Bit 14 Reserved, must be kept at reset value. Bits 13:11 PPRE2[2:0]: APB high-speed prescaler (APB2) These bits are set and cleared by software to control the division factor of the APB highspeed clock (PCLK2). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 Bits 10:8 PPRE1[2:0]: APB low-speed prescaler (APB1) These bits are set and cleared by software to control the division factor of the APB low-speed clock (PCLK1). 0xx: HCLK not divided 100: HCLK divided by 2 101: HCLK divided by 4 110: HCLK divided by 8 111: HCLK divided by 16 183/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) Bits 7:4 HPRE[3:0]: AHB prescaler These bits are set and cleared by software to control the division factor of the AHB clock. Caution: Depending on the device voltage range, the software has to set correctly these bits to ensure that the system frequency does not exceed the maximum allowed frequency (for more details please refer to the Dynamic voltage scaling management section in the PWR chapter.) After a write operation to these bits and before decreasing the voltage range, this register must be read to be sure that the new value has been taken into account. 0xxx: SYSCLK not divided 1000: SYSCLK divided by 2 1001: SYSCLK divided by 4 1010: SYSCLK divided by 8 1011: SYSCLK divided by 16 1100: SYSCLK divided by 64 1101: SYSCLK divided by 128 1110: SYSCLK divided by 256 1111: SYSCLK divided by 512 Bits 3:2 SWS[1:0]: System clock switch status These bits are set and cleared by hardware to indicate which clock source is used as system clock. 00: MSI oscillator used as system clock 01: HSI16 oscillator used as system clock 10: HSE oscillator used as system clock 11: PLL used as system clock Bits 1:0 SW[1:0]: System clock switch These bits are set and cleared by software to select SYSCLK source. Set by hardware to force MSI selection when leaving Standby mode or in case of failure of the HSE oscillator used directly or indirectly as system clock (if the Clock Security System is enabled). 00: MSI oscillator used as system clock 01: HSI16 oscillator used as system clock 10: HSE oscillator used as system clock 11: PLL used as system clock 7.3.4 Clock interrupt enable register (RCC_CIER) Address: 0x10 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CSS LSE Res. MSI RDYIE PLL RDYIE LSE RDYIE LSI RDYIE r r r r r r DocID025942 Rev 5 HSE HSI16 RDYIE RDYIE r r 184/874 212 Reset and clock control (RCC) RM0377 Bits 31:8 Reserved, must be kept at reset value. Bit 7 CSSLSE: LSE CSS interrupt flag This bit is set and reset by software to enable/disable the interrupt caused by the Clock Security System on external 32 kHz oscillator. 0: LSE CSS interrupt disabled 1: LSE CSS interrupt enabled Bit 6 Reserved, must be kept at reset value. Bit 5 MSIRDYIE: MSI ready interrupt flag This bit is set and reset by software to enable/disable the interrupt caused by the MSI oscillator stabilization. 0: MSI ready interrupt disabled 1: MSI ready interrupt enabled Bit 4 PLLRDYIE: PLL ready interrupt flag This bit is set and reset by software to enable/disable the interrupt caused by the PLL lock. 0: PLL lock interrupt disabled 1: PLL lock interrupt enabled Bit 3 HSERDYIE: HSE ready interrupt flag This bit is set and reset by software to enable/disable the interrupt caused by the HSE oscillator stabilization. 0: HSE ready interrupt disabled 1: HSE ready interrupt enabled Bit 2 HSI16RDYIE: HSI16 ready interrupt flag This bit is set and reset by software to enable/disable the interrupt caused by the HSI16 oscillator stabilization. 0: HSI16 ready interrupt disabled 1: HSI16 ready interrupt enabled Bit 1 LSERDYIE: LSE ready interrupt flag This bit is set and reset by software to enable/disable the interrupt caused by the LSE oscillator stabilization. 0: LSE ready interrupt disabled 1: LSE ready interrupt enabled Bit 0 LSIRDYIE: LSI ready interrupt flag This bit is set and reset by software to enable/disable the interrupt caused by the LSI oscillator stabilization. 0: LSI ready interrupt disabled 1: LSI ready interrupt enabled 185/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) 7.3.5 Clock interrupt flag register (RCC_CIFR) Address: 0x14 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. CSS HSEF CSS LSEF Res. MSI RDYF PLL RDYF HSE RDYF HSI16 RDYF LSE RDYF LSI RDYF r r r r r r r r r Bits 31:9 Reserved, must be kept at reset value. Bit 8 CSSHSEF: Clock Security System Interrupt flag This bit is reset by software by writing the CSSHSEC bit. It is set by hardware in case of HSE clock failure. 0: No clock security interrupt caused by HSE clock failure 1: Clock security interrupt caused by HSE clock failure Bit 7 CSSLSEF: LSE Clock Security System Interrupt flag This bit is reset by software by writing the CSSLSEC bit. It is set by hardware in case of LSE clock failure and the CSSLSE is set. 0: No failure detected on LSE clock failure 1: Failure detected on LSE clock failure Bit:6 Reserved, must be kept at reset value. Bit 5 MSIRDYF: MSI ready interrupt flag This bit is reset by software by writing the MSIRDYC bit. It is set by hardware when the MSI clock becomes stable and the MSIRDYIE is set. 0: No clock ready interrupt caused by MSI clock failure 1: Clock ready interrupt caused by MSI clock failure Bit 4 PLLRDYF: PLL ready interrupt flag This bit is reset by software by writing the PLLRDYC bit. It is set by hardware when the PLL clock becomes stable and the PLLRDYIE is set. 0: No clock ready interrupt caused by PLL clock failure 1: Clock ready interrupt caused by PLL clock failure Bit 3 HSERDYF: HSE ready interrupt flag This bit is reset by software by writing the HSERDYC bit. It is set by hardware when the HSE clock becomes stable and the HSERDYIE is set. 0: No clock ready interrupt caused by HSE clock failure 1: Clock ready interrupt caused by HSE clock failure DocID025942 Rev 5 186/874 212 Reset and clock control (RCC) RM0377 Bit 2 HSI16RDYF: HSI16 ready interrupt flag This bit is reset by software by writing the HSI16RDYC bit. It is set by hardware when the HSE clock becomes stable and the HSI16RDYIE is set. 0: No clock ready interrupt caused by HSI16 clock failure 1: Clock ready interrupt caused by HSI16 clock failure Bit 1 LSERDYF: LSE ready interrupt flag This bit is reset by software by writing the LSERDYC bit. It is set by hardware when the LSE clock becomes stable and the LSERDYIE is set. 0: No clock ready interrupt caused by LSE clock failure 1: Clock ready interrupt caused by LSE clock failure Bit 0 LSIRDYF: LSI ready interrupt flag This bit is reset by software by writing the LSIRDYC bit. It is set by hardware when the LSI clock becomes stable and the LSIRDYIE is set. 0: No clock ready interrupt caused by LSI clock failure 1: Clock ready interrupt caused by LSI clock failure 7.3.6 Clock interrupt clear register (RCC_CICR) Address: 0x18 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. CSS HSEC CSS LSEC Res. MSI RDYC PLL RDYC HSE RDYC HSI16 RDYC LSE RDYIC LSI RDYC w w w w w w w w Res. Res. Res. Res. Res. Res. Bits 31:9 Reserved, must be kept at reset value. Bit 8 CSSHSEC: Clock Security System Interrupt clear This bit is set by software to clear the CSSHSEF flag. It is reset by hardware. 0: No effect 1: CSSHSEF flag cleared Bit 7 CSSLSEC: LSE Clock Security System Interrupt clear This bit is set by software to clear the CSSLSEF flag. It is reset by hardware. 0: No effect 1: CSSLSEF flag cleared Bit:6 Reserved, must be kept at reset value. Bit 5 MSIRDYC: MSI ready Interrupt clear This bit is set by software to clear the MSIRDYF flag. It is reset by hardware. 0: No effect 1: MSIRDYF flag cleared 187/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) Bit 4 PLLRDYC: PLL ready Interrupt clear This bit is set by software to clear the PLLRDYF flag. It is reset by hardware. 0: No effect 1: PLLRDYF flag cleared Bit 3 HSERDYC: HSE ready Interrupt clear This bit is set by software to clear the HSERDYF flag. It is reset by hardware. 0: No effect 1: HSERDYF flag cleared Bit 2 HSI16RDYC: HSI16 ready Interrupt clear This bit is set by software to clear the HSI16RDYF flag. It is reset by hardware. 0: No effect 1: HSI16RDYF flag cleared Bit 1 LSERDYC: LSE ready Interrupt clear This bit is set by software to clear the LSERDYF flag. It is reset by hardware. 0: No effect 1: LSERDYF flag cleared Bit 0 LSIRDYC: LSI ready Interrupt clear This bit is set by software to clear the LSIRDYF flag. It is reset by hardware. 0: No effect 1: LSIRDYF flag cleared 7.3.7 GPIO reset register (RCC_IOPRSTR) Address: 0x1C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. IOPH RST Res. Res. IOPER ST IOPD RST IOPC RST IOPB RST IOPA RST rw rw rw rw rw rw Bits 31:8 Reserved, must be kept at reset value. Bit 7 IOPHRST: I/O port H reset This bit is set and cleared by software. 0: no effect 1: resets I/O port H Bits 6:5 Reserved, must be kept at reset value. Bit 4 IOPERST: I/O port E reset This bit is set and cleared by software. 0: no effect 1: resets I/O port E DocID025942 Rev 5 188/874 212 Reset and clock control (RCC) RM0377 Bit 3 IOPDRST: I/O port D reset This bit is set and cleared by software. 0: no effect 1: resets I/O port D Bit 2 IOPCRST: I/O port C reset This bit is set and cleared by software. 0: no effect 1: resets I/O port C Bit 1 IOPBRST: I/O port B reset This bit is set and cleared by software. 0: no effect 1: resets I/O port B Bit 0 IOPARST: I/O port A reset This bit is set and cleared by software. 0: no effect 1: resets I/O port A 7.3.8 AHB peripheral reset register (RCC_AHBRSTR) Address offset: 0x20 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRYP RST Res. Res. Res. Res. Res. Res. Res. Res. 7 6 5 3 2 1 0 Res. DMA RST Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 Res. CRC RST Res. MIF RST rw Res. Res. rw Res. Res. rw Res. Res. rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 CRYPTRST: Crypto module reset This bit is set and reset by software. 0: no effect 1: resets CRYPTO module Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 Reserved, must be kept at reset value. Bits 15: 13 Reserved, must be kept at reset value. Bit 12 CRCRST: Test integration module reset This bit is set and reset by software. 0: no effect 1: resets test integration module Bits 11:9 Reserved, must be kept at reset value. 189/874 DocID025942 Rev 5 Res. 4 Res. rw Res. Res. rw RM0377 Reset and clock control (RCC) Bit 8 MIFRST: Memory interface reset This bit is set and reset by software. This reset can be activated only when the E2 is in IDDQ mode. 0: no effect 1: resets memory interface Bits 7:1 Reserved, must be kept at reset value. Bit 0 DMARST: DMA reset This bit is set and reset by software. 0: no effect 1: resets DMA 7.3.9 APB2 peripheral reset register (RCC_APB2RSTR) Address offset: 0x24 Reset value: 0x00000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. DBG RST Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. USART1 RST Res. SPI1 RST Res. Res. ADC RST Res. Res. Res. TIM22 RST Res. Res. TIM21 RST Res. SYSCF GRST rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bit 22 DBGRST: DBG reset This bit is set and cleared by software. 0: No effect 1: Resets DBG Bits 21:15 Reserved, must be kept at reset value. Bit 14 USART1RST: USART1 reset This bit is set and cleared by software. 0: No effect 1: Reset USART1 Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1RST: SPI 1 reset This bit is set and cleared by software. 0: No effect 1: Reset SPI 1 Bits 11:10 Reserved, must be kept at reset value. Bit 9 ADCRST: ADC interface reset This bit is set and cleared by software. 0: No effect 1: Reset ADC interface DocID025942 Rev 5 190/874 212 Reset and clock control (RCC) RM0377 Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM22RST: TIM22 timer reset This bit is set and cleared by software. 0: No effect 1: Reset TIM22 timer Bits 4:3 Reserved, must be kept at reset value. Bit 2 TIM21RST: TIM21 timer reset This bit is set and cleared by software. 0: No effect 1: Reset TIM21 timer Bit 1 Reserved, must be kept at reset value. Bit 0 SYSCFGRST: System configuration controller reset This bit is set and cleared by software. 0: No effect 1: Reset System configuration controller 7.3.10 APB1 peripheral reset register (RCC_APB1RSTR) Address offset: 0x28 Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 LPTIM1 RST I2C3 RST Res. PWR RST CRS RST rw rw rw rw rw 15 14 13 12 11 Res. SPI2 RST Res. WWDG RST rw Res. rw 26 Res. 10 Res. 25 Res. 9 Res. 24 Res. 8 Res. 23 22 21 Res. I2C2 RST I2C1 RST rw rw rw 7 6 Res. rw rw Res. rw Bit 31 LPTIM1RST: Low-power timer reset This bit is set and cleared by software. 0: No effect 1: Resets low-power timer Bit 30 I2C3RST: I2C3 reset This bit is set and cleared by software. 0: No effect 1: Resets I2C3 Bit 28 PWRRST: Power interface reset This bit is set and cleared by software. 0: No effect 1: Reset power interface Bit 27 Reserved, must be kept at reset value. Bits 26:23 Reserved, must be kept at reset value. 191/874 DocID025942 Rev 5 20 19 18 17 16 USART5 USART4 LPUART1 USART2 Res. RST RST RST RST rw rw rw 5 4 3 2 1 0 TIM7 RST TIM6 RST Res. TIM3 RST TIM2 RST rw rw Res. rw RM0377 Reset and clock control (RCC) Bit 22 I2C2RST: I2C2 reset This bit is set and cleared by software. 0: No effect 1: Resets I2C2 Bit 21 I2C1RST: I2C1 reset This bit is set and cleared by software. 0: No effect 1: Resets I2C1 Bit 20 USART5RST: USART5 reset This bit is set and cleared by software. 0: No effect 1: Resets USART5 Bit 19 USART4RST: USART4 reset This bit is set and cleared by software. 0: No effect 1: Resets USART4 Bit 18 LPUART1RST: LPUART1 reset This bit is set and cleared by software. 0: No effect 1: Resets LPUART1 Bit 17 USART2RST: USART2 reset This bit is set and cleared by software. 0: No effect 1: Resets USART2 Bits 16:15 Reserved, must be kept at reset value. Bit 14 SPI2RST: SPI2 reset This bit is set and cleared by software. 0: No effect 1: Resets SPI2 Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGRST: Window watchdog reset This bit is set and cleared by software. 0: No effect 1: Resets window watchdog Bits 10:9 Reserved, must be kept at reset value. Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM7RST: Timer 7 reset Set and cleared by software. 0: No effect 1: Resets timer7 Bit 4 TIM6RST: Timer 6 reset Set and cleared by software. 0: No effect 1: Resets timer6 DocID025942 Rev 5 192/874 212 Reset and clock control (RCC) RM0377 Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM3RST: Timer3 reset Set and cleared by software. 0: No effect 1: Resets timer3 Bit 0 TIM2RST: Timer2 reset Set and cleared by software. 0: No effect 1: Resets timer2 7.3.11 GPIO clock enable register (RCC_IOPENR) Address: 0x2C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. IOPH EN Res. IOPE EN IOPD EN IOPC EN IOPB EN IOPA EN rw rw rw rw rw Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:8 Reserved, must be kept at reset value. Bit 7 IOPHEN: I/O port H clock enable bit This bit is set and cleared by software. 0: port H clock disabled 1: port H clock enabled Bits 6:45 Reserved, must be kept at reset value. Bit 4 IOPEEN: I/O port E clock enable bit This bit is set and cleared by software. 0: port E clock disabled 1: port E clock enabled Bit 3 IOPDEN: I/O port D clock enable bit This bit is set and cleared by software. 0: port D clock disabled 1: port D clock enabled 193/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) Bit 2 IOPCEN: IO port C clock enable bit This bit is set and cleared by software. 0: port C clock disabled 1: port C clock enabled Bit 1 IOPBEN: IO port B clock enable bit This bit is set and cleared by software. 0: port B clock disabled 1: port B clock enabled Bit 0 IOPAEN: IO port A clock enable bit This bit is set and cleared by software. 0: port A clock disabled 1: port A clock enabled DocID025942 Rev 5 194/874 212 Reset and clock control (RCC) 7.3.12 RM0377 AHB peripheral clock enable register (RCC_AHBENR) Address offset: 0x30 Reset value: 0x0000 0100 Access: no wait state, word, half-word and byte access When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRYP EN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. CRC EN Res. Res. Res. MIF EN Res. Res. Res. Res. Res. Res. Res. DMA EN rw rw rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 CRYPEN: Crypto clock enable bit This bit is set and reset by software. 0: Crypto clock disabled 1: Crypto clock enabled Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 Reserved, must be kept at reset value. Bits 15: 13 Reserved, must be kept at reset value. Bit 12 CRCEN: CRC clock enable bit This bit is set and reset by software. 0: Test integration module clock disabled 1: Test integration module clock enabled Bits 11:9 Reserved, must be kept at reset value. Bit 8 MIFEN: NVM interface clock enable bit This bit is set and reset by software. This reset can be activated only when the NVM is in power-down mode. 0: NVM interface clock disabled 1: NVM interface clock enabled Bits 7:1 Reserved, must be kept at reset value. Bit 0 DMAEN: DMA clock enable bit This bit is set and reset by software. 0: DMA clock disabled 1: DMA clock enabled 195/874 DocID025942 Rev 5 rw RM0377 Reset and clock control (RCC) 7.3.13 APB2 peripheral clock enable register (RCC_APB2ENR) Address: 0x34 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait states, except if the access occurs while an access to a peripheral in the APB2 domain is on going. In this case, wait states are inserted until the access to APB2 peripheral is finished. Note: 31 When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DBG EN Res. Res. Res. Res. Res. Res. 6 5 4 3 2 1 0 Res. TIM22 EN Res. TIM21 EN Res. SYSCF EN Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 Res. USART1 EN Res. SPI1 EN Res. ADC EN rw rw rw Res. Res. FWEN rw rs rw Res. rw rw Bits 31:23 Reserved, must be kept at reset value. Bit 22 DBGEN: DBG clock enable bit This bit is set and cleared by software. 0: DBG clock disabled 1: DBG clock enabled Bits 21:15 Reserved, must be kept at reset value. Bit 14 USART1EN: USART1 clock enable bit This bit is set and cleared by software. 0: USART1 clock disabled 1: USART1 clock enabled Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1EN: SPI1 clock enable bit This bit is set and cleared by software. 0: SPI1 clock disabled 1: SPI1 clock enabled Bits 11:10 Reserved, must be kept at reset value. Bit 9 ADCEN: ADC clock enable bit This bit is set and cleared by software. 0: ADC clock disabled 1: ADC clock enabled Bit 8 Reserved, must be kept at reset value. Bit 7 FWEN: Firewall clock enable bit This bit is set by software and reset by hardware. Software can only program this bit to 1. Writing 0 has not effect. 0: Firewall disabled 1: Firewall clock enabled DocID025942 Rev 5 196/874 212 Reset and clock control (RCC) RM0377 Bit 6 Reserved, must be kept at reset value. Bit 5 TIM22EN: TIM22 timer clock enable bit This bit is set and cleared by software. 0:TIM22 clock disabled 1: TIM22 clock enabled Bits 4:3 Reserved, must be kept at reset value. Bit 2 TIM21EN: TIM21 timer clock enable bit This bit is set and cleared by software. 0: TIM21 clock disabled 1: TIM21 clock enabled Bit 1 Reserved, must be kept at reset value. Bit 0 SYSCFGEN: System configuration controller clock enable bit This bit is set and cleared by software. 0: System configuration controller clock disabled 1: System configuration controller clock enabled 197/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) 7.3.14 APB1 peripheral clock enable register (RCC_APB1ENR) Address: 0x38 Reset value: 0x0000 0000 Access: word, half-word and byte access No wait state, except if the access occurs while an access to a peripheral on APB1 domain is on going. In this case, wait states are inserted until this access to APB1 peripheral is finished. Note: When the peripheral clock is not active, the peripheral register values may not be readable by software and the returned value is always 0x0. 31 30 LPTIM1 EN I2C3 EN 29 28 Res. PWR EN 27 Res rw rw rw rw rw 15 14 13 12 11 Res. SPI2 EN Res. WWDG EN rw Res. rw 26 25 24 Res. Res. Res. 10 9 8 Res. Res. Res. 23 22 21 Res. I2C2 EN I2C1 EN rw rw rw rw rw rw 7 6 5 4 3 2 1 0 Res. TIM7 EN TIM6 EN Res. TIM3 EN TIM2 EN rw rw rw rw Res. rw 20 19 18 17 16 USART5 USART4 LPUART1 USART2 EN EN EN EN Res. Res. rw Bit 31 LPTIM1EN: Low-power timer clock enable bit This bit is set and cleared by software. 0: Low-power timer clock disabled 1: Low-power timer clock enabled Bit 30 I2C3EN: I2C3 clock enable bit This bit is set and cleared by software. 0: I2C3 clock disabled 1: I2C3 clock enabled Bit 28 PWREN: Power interface clock enable bit This bit is set and cleared by software. 0: Power interface clock disabled 1: Power interface clock enabled Bit 27 Reserved, must be kept at reset value. Bits 26:23 Reserved, must be kept at reset value. Bit 22 I2C2EN: I2C2 clock enable bit This bit is set and cleared by software. 0: I2C2 clock disabled 1: I2C2 clock enabled Bit 21 I2C1EN: I2C1 clock enable bit This bit is set and cleared by software. 0: I2C1 clock disabled 1: I2C1 clock enabled Bit 20 USART5EN: USART5 clock enable bit This bit is set and cleared by software. 0: USART5 clock disabled 1: USART5 clock enabled DocID025942 Rev 5 198/874 212 Reset and clock control (RCC) RM0377 Bit 19 USART4EN: USART4 clock enable bit This bit is set and cleared by software. 0: USART4 clock disabled 1: USART4 clock enabled Bit 18 LPUART1EN: LPUART1 clock enable bit This bit is set and cleared by software. 0: LPUART1 clock disabled 1: LPUART1 clock enabled Bit 17 USART2EN: USART2 clock enable bit This bit is set and cleared by software. 0: USART2 clock disabled 1: USART2 clock enabled Bits 16:15 Reserved, must be kept at reset value. Bit 14 SPI2EN: SPI2 clock enable bit This bit is set and cleared by software. 0: SPI2 clock disabled 1: SPI2 clock enabled Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGEN: Window watchdog clock enable bit This bit is set and cleared by software. 0: Window watchdog clock disabled 1: Window watchdog clock enabled Bits 10:9 Reserved, must be kept at reset value. Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM7EN: Timer 7 clock enable bit Set and cleared by software. 0: Timer 7 clock disabled 1: Timer 7 clock enabled Bit 4 TIM6EN: Timer 6 clock enable bit Set and cleared by software. 0: Timer 6 clock disabled 1: Timer 6 clock enabled Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM3EN: Timer3 clock enable bit Set and cleared by software. 0: Timer3 clock disabled 1: Timer3 clock enabled Bit 0 TIM2EN: Timer2 clock enable bit Set and cleared by software. 0: Timer2 clock disabled 1: Timer2 clock enabled 199/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) 7.3.15 GPIO clock enable in Sleep mode register (RCC_IOPSMENR) Address: 0x3C Reset value: the bits corresponding to the available GPIO ports are set Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. IOPHS MEN Res. IOPES MEN IOPDS MEN IOPCS MEN IOPBS MEN IOPAS MEN rw rw rw rw rw Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31: 8 Reserved, must be kept at reset value. Bit 7 IOPHSMEN: Port H clock enable during Sleep mode bit This bit is set and cleared by software. 0: Port H clock is disabled in Sleep mode 1: Port H clock is enabled in Sleep mode (if enabled by IOPHEN) Bits 6:5 Reserved, must be kept at reset value. Bit 4 IOPESMEN: Port E clock enable during Sleep mode bit This bit is set and cleared by software. 0: Port E clock is disabled in Sleep mode 1: Port E clock is enabled in Sleep mode (if enabled by IOPDEN) Bit 3 IOPDSMEN: Port D clock enable during Sleep mode bit This bit is set and cleared by software. 0: Port D clock is disabled in Sleep mode 1: Port D clock is enabled in Sleep mode (if enabled by IOPDEN) Bit 2 IOPCSMEN: Port C clock enable during Sleep mode bit This bit is set and cleared by software. 0: Port C clock is disabled in Sleep mode 1: Port C clock is enabled in Sleep mode (if enabled by IOPCEN) Bit 1 IOPBSMEN: Port B clock enable during Sleep mode bit This bit is set and cleared by software. 0: Port B clock is disabled in Sleep mode 1: Port B clock is enabled in Sleep mode (if enabled by IOPBEN) Bit 0 IOPASMEN: Port A clock enable during Sleep mode bit This bit is set and cleared by software. 0: Port A clock is disabled in Sleep mode 1: Port A clock is enabled in Sleep mode (if enabled by IOPAEN) DocID025942 Rev 5 200/874 212 Reset and clock control (RCC) 7.3.16 RM0377 AHB peripheral clock enable in Sleep mode register (RCC_AHBSMENR) Address: 0x40 Reset value: the bits corresponding to the available peripherals are set Access: no wait state, word, half-word and byte access 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CRYP SMEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. CRC SMEN Res. Res. SRAM SMEN MIF SMEN Res. Res. Res. Res. Res. Res. Res. DMA SMEN rw rw rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 CRYPTSMEN: Crypto clock enable during Sleep mode bit This bit is set and reset by software. 0: Crypto clock disabled in Sleep mode 1: Crypto clock enabled in Sleep mode Bits 23:20 Reserved, must be kept at reset value. Bits 19:16 Reserved, must be kept at reset value. Bits 15: 13 Reserved, must be kept at reset value. Bit 12 CRCSMEN: CRC clock enable during Sleep mode bit This bit is set and reset by software. 0: Test integration module clock disabled in Sleep mode 1: Test integration module clock enabled in Sleep mode (if enabled by CRCEN) Bits 11:10 Reserved, must be kept at reset value. Bit 9 SRAMSMEN: SRAM interface clock enable during Sleep mode bit This bit is set and reset by software. 0: NVM interface clock disabled in Sleep mode 1: NVM interface clock enabled in Sleep mode Bit 8 MIFSMEN: NVM interface clock enable during Sleep mode bit This bit is set and reset by software. 0: NVM interface clock disabled in Sleep mode 1: NVM interface clock enabled in Sleep mode Bits 7:1 Reserved, must be kept at reset value. Bit 0 DMASMEN: DMA clock enable during Sleep mode bit This bit is set and reset by software. 0: DMA clock disabled in Sleep mode 1: DMA clock enabled in Sleep mode 201/874 DocID025942 Rev 5 rw RM0377 Reset and clock control (RCC) 7.3.17 APB2 peripheral clock enable in Sleep mode register (RCC_APB2SMENR) Address: 0x44 Reset value: the bits corresponding to the available peripherals are set. Access: no wait state, word, half-word and byte access 31 Res. 30 29 Res. Res. 28 Res. 27 Res. 26 Res. 25 24 Res. Res. 23 22 21 20 19 18 17 16 Res. DBG SMEN Res. Res. Res. Res. Res. Res. 6 5 4 3 2 1 0 Res. TIM22 SMEN Res. TIM21 SMEN Res. SYSCF SMEN rw 15 14 Res. USART1 SMEN rw 13 12 Res. SPI1 SMEN rw 11 Res. 10 9 Res. ADC SMEN 8 Res. 7 Res. rw Res. rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bit 22 DBGSMEN: DBG clock enable during Sleep mode bit This bit is set and cleared by software. 0: DBG clock disabled in Sleep mode 1: DBG clock enabled in Sleep mode (if enabled by DBGEN) Bits 21:15 Reserved, must be kept at reset value. Bit 14 USART1SMEN: USART1 clock enable during Sleep mode bit This bit is set and cleared by software. 0: USART1 clock disabled in Sleep mode 1: USART1 clock enabled in Sleep mode (if enabled by USART1EN) Bit 13 Reserved, must be kept at reset value. Bit 12 SPI1SMEN: SPI1 clock enable during Sleep mode bit This bit is set and cleared by software. 0: SPI1 clock disabled in Sleep mode 1: SPI1 clock enabled in Sleep mode (if enabled by SPI1EN) Bits 11:10 Reserved, must be kept at reset value. Bit 9 ADCSMEN: ADC clock enable during Sleep mode bit This bit is set and cleared by software. 0: ADC clock disabled in Sleep mode 1: ADC clock enabled in Sleep mode (if enabled by ADCEN) Bit 8:6 Reserved, must be kept at reset value. Bit 5 TIM22SMEN: TIM22 timer clock enable during Sleep mode bit This bit is set and cleared by software. 0:TIM22 clock disabled in Sleep mode 1: TIM22 clock enabled in Sleep mode (if enabled by TIM22EN) Bits 4:3 Reserved, must be kept at reset value. DocID025942 Rev 5 202/874 212 Reset and clock control (RCC) RM0377 Bit 2 TIM21SMEN: TIM21 timer clock enable during Sleep mode bit This bit is set and cleared by software. 0: TIM21 clock disabled in Sleep mode 1: TIM21 clock enabled in Sleep mode (if enabled by TIM21EN) Bit 1 Reserved, must be kept at reset value. Bit 0 SYSCFGSMEN: System configuration controller clock enable during Sleep mode bit This bit is set and cleared by software. 0: System configuration controller clock disabled in Sleep mode 1: System configuration controller clock enabled in Sleep mode 7.3.18 APB1 peripheral clock enable in Sleep mode register (RCC_APB1SMENR) Address: 0x48 Reset value: the bits corresponding to the available peripherals are set Note: Access: no wait state, word, half-word and byte access 31 30 LPTIM1 I2C3 SMEN SMEN rw rw 15 14 Res. SPI2 SMEN rw 29 28 Res. PWR SMEN 13 12 27 26 25 24 23 22 I2C2 SMEN Res. Res. Res. Res. Res. 11 10 9 8 7 rw Res. Res. WWDG Res. SMEN Res. Res. 21 20 19 18 16 Res. rw rw rw rw rw 6 5 4 3 2 1 0 TIM7 SMEN TIM6 SMEN Res. TIM3 SMEN TIM2 SMEN rw rw rw rw Res. rw Res. Bit 31 LPTIM1SMEN: Low-power timer clock enable during Sleep mode bit This bit is set and cleared by software. 0: Low-power timer clock disabled in Sleep mode 1: Low-power timer clock enabled in Sleep mode (if enabled by LPTIM1EN) Bit 30 I2C3SMEN: I2C3 clock enable during Sleep mode bit This bit is set and cleared by software. 0: I2C3 clock disabled in Sleep mode 1: I2C3 clock enabled in Sleep mode (if enabled by I2C3EN) Bit 28 PWRSMEN: Power interface clock enable during Sleep mode bit This bit is set and cleared by software. 0: Power interface clock disabled in Sleep mode 1: Power interface clock enabled in Sleep mode (if enabled by PWREN) Bit 27 Reserved, must be kept at reset value. Bits 26:23 Reserved, must be kept at reset value. Bit 22 I2C2SMEN: I2C2 clock enable during Sleep mode bit This bit is set and cleared by software. 0: I2C2 clock disabled in Sleep mode 1: I2C2 clock enabled in Sleep mode (if enabled by I2C2EN) 203/874 17 I2C1 USART5 USART4 LPUART1 USART2 SMEN SMEN SMEN SMEN SMEN DocID025942 Rev 5 rw RM0377 Reset and clock control (RCC) Bit 21 I2C1SMEN: I2C1 clock enable during Sleep mode bit This bit is set and cleared by software. 0: I2C1 clock disabled in Sleep mode 1: I2C1 clock enabled in Sleep mode (if enabled by I2C1EN) Bit 20 USART5SMEN: USART5 clock enable during Sleep mode bit This bit is set and cleared by software. 0: USART5 clock disabled in Sleep mode 1: USART5 clock enabled in Sleep mode (if enabled by USART5EN) Bit 19 USART4SMEN: USART4 clock enable during Sleep mode bit This bit is set and cleared by software. 0: USART4 clock disabled in Sleep mode 1: USART4 clock enabled in Sleep mode (if enabled by USART4EN) Bit 18 LPUART1SMEN: LPUART1 clock enable during Sleep mode bit This bit is set and cleared by software. 0: LPUART1 clock disabled in Sleep mode 1: LPUART1 clock enabled in Sleep mode (if enabled by LPUART1EN) Bit 17 USART2SMEN: USART2 clock enable during Sleep mode bit This bit is set and cleared by software. 0: USART2 clock disabled in Sleep mode 1: USART2 clock enabled in Sleep mode (if enabled by USART2EN) Bits 16:15 Reserved, must be kept at reset value. Bit 14 SPI2SMEN: SPI2 clock enable during Sleep mode bit This bit is set and cleared by software. 0: SPI2 clock disabled in Sleep mode 1: SPI2 clock enabled in Sleep mode (if enabled by SPI2SEN) Bits 13:12 Reserved, must be kept at reset value. Bit 11 WWDGSMEN: Window watchdog clock enable during Sleep mode bit This bit is set and cleared by software. 0: Window watchdog clock disabled in Sleep mode 1: Window watchdog clock enabled in Sleep mode (if enabled by WWDGEN) Bits 10:9 Reserved, must be kept at reset value. Bits 8:6 Reserved, must be kept at reset value. Bit 5 TIM7SMEN: Timer 7 clock enable during Sleep mode bit Set and cleared by software. 0: Timer 7 clock disabled in Sleep mode 1: Timer 7 clock enabled in Sleep mode (if enabled by TIM7EN) Bit 4 TIM6SMEN: Timer 6 clock enable during Sleep mode bit Set and cleared by software. 0: Timer 6 clock disabled in Sleep mode 1: Timer 6 clock enabled in Sleep mode (if enabled by TIM6EN) DocID025942 Rev 5 204/874 212 Reset and clock control (RCC) RM0377 Bits 3:2 Reserved, must be kept at reset value. Bit 1 TIM3SMEN: Timer3 clock enable during Sleep mode bit Set and cleared by software. 0: Timer3 clock disabled in Sleep mode 1: Timer3 clock enabled in Sleep mode (if enabled by TIM3EN) Bit 0 TIM2SMEN: Timer2 clock enable during Sleep mode bit Set and cleared by software. 0: Timer2 clock disabled in Sleep mode 1: Timer2 clock enabled in Sleep mode (if enabled by TIM2EN) 7.3.19 Clock configuration register (RCC_CCIPR) Address: 0x4C Reset value: 0x0000 0000 Access: no wait state, word, half-word and byte access 31 Res. 30 Res. 29 Res. 28 Res. 27 Res. 26 Res. 25 Res. 24 Res. 23 Res. 22 Res. 21 Res. 20 19 18 17 16 Res. LPTIM1 SEL1 LPTIM1 SEL0 I2C3 SEL1 I2C3 SEL0 rw rw rw rw 3 2 1 0 rw 15 Res. 14 13 12 Res. I2C1 SEL1 I2C1 SEL0 rw rw 11 10 LPUART1 LPUART1 SEL1 SEL0 rw 9 Res. 8 Res. 7 Res. 6 Res. 5 Res. 4 Res. rw rw Bits 31:26 Reserved, must be kept at reset value. Bits 25:20 Reserved, must be kept at reset value. Bits 19:18 LPTIM1SEL: Low-power Timer clock source selection bits This bit is set and cleared by software. 00: APB clock selected as LP Timer clock 01: LSI clock selected as LP Timer clock 10: HSI16 clock selected as LP Timer clock 11: LSE clock selected as LP Timer clock Bits 17:16 I2C3SEL: I2C3 clock source selection bits This bit is set and cleared by software. 00: APB clock selected as I2C3 clock 01: System clock selected as I2C3 clock 10: HSI16 clock selected as I2C3 clock 11: not used Bits 15:14 Reserved, must be kept at reset value. Bits 13:12 I2C1SEL: I2C1 clock source selection bits This bit is set and cleared by software. 00: APB clock selected as I2C1 clock 01: System clock selected as I2C1 clock 10: HSI16 clock selected as I2C1 clock 11: not used 205/874 USART2 USART2 USART1 USART1 SEL1 SEL0 SEL1 SEL0 DocID025942 Rev 5 rw rw rw RM0377 Reset and clock control (RCC) Bits 11:10 LPUART1SEL: LPUART1 clock source selection bits This bit is set and cleared by software. 00: APB clock selected as LPUART1 clock 01: System clock selected as LPUART1 clock 10: HSI16 clock selected as LPUART1 clock 11: LSE clock selected as LPUART1 clock Bits 9:4 Reserved, must be kept at reset value. Bits 3:2 USART2SEL: USART2 clock source selection bits This bit is set and cleared by software. 00: APB clock selected as USART2 clock 01: System clock selected as USART2 clock 10: HSI16 clock selected as USART2 clock 11: LSE clock selected as USART2 clock Bits 1:0 USART1SEL: USART1 clock source selection bits This bit is set and cleared by software. 00: APB clock selected as USART1 clock 01: System clock selected as USART1 clock 10: HSI16 clock selected as USART1 clock 11: LSE clock selected as USART1 clock 7.3.20 Control/status register (RCC_CSR) Address: 0x50 Power-on reset value: 0x0C00 0004 Access: 0 wait state 3, word, half-word and byte access Wait states are inserted in case of successive accesses to this register. Note: The LSEON, LSEBYP, RTCSEL,LSEDRV and RTCEN bits in the RCC control and status register (RCC_CSR) are in the RTC domain. As these bits are write protected after reset, the DBP bit in the Power control register (PWR_CR) has to be set to be able to modify them. Refer to Section 6.1.2: RTC and RTC backup registers for further information. These bits are only reset after a RTC domain reset (see Section 6.1.2). Any internal or external reset does not have any effect on them. 31 30 29 28 27 26 25 24 LPWR RSTF WWDG RSTF IWDG RSTF SFT RSTF POR RSTF PIN RSTF OBL RS TF FW RSTF 23 RMVF r r r r r r r r rt_w 15 14 13 12 11 10 9 8 7 Res. CSSLS CSSLS ED EON r rw LSEDRV[1:0] LSE BYP rw rw LSERDY LSEON r Res. 22 21 20 19 18 RTC RST. RTC EN rw rw rw rw 3 2 1 0 Res. LSI RDY LSION r rw Res. Res. Res. 6 5 4 Res. rw DocID025942 Rev 5 Res. Res. Res. 17 16 RTCSEL[1:0] 206/874 212 Reset and clock control (RCC) RM0377 Bit 31 LPWRRSTF: Low-power reset flag This bit is set by hardware when a Low-power management reset occurs. It is cleared by writing to the RMVF bit, or by a POR. 0: No Low-power management reset occurred 1: Low-power management reset occurred For further information on Low-power management reset, refer to Section : Low-power management reset. Bit 30 WWDGRSTF: Window watchdog reset flag This bit is set by hardware when a window watchdog reset occurs. It is cleared by writing to the RMVF bit, or by a POR. 0: No window watchdog reset occurred 1: Window watchdog reset occurred Bit 29 IWDGRSTF: Independent watchdog reset flag This bit is set by hardware when an independent watchdog reset from VDD domain occurs. It is cleared by writing to the RMVF bit, or by a POR. 0: No watchdog reset occurred 1: Watchdog reset occurred Bit 28 SFTRSTF: Software reset flag This bit is set by hardware when a software reset occurs. It is cleared by writing to the RMVF bit, or by a POR. 0: No software reset occurred 1: Software reset occurred Bit 27 PORRSTF: POR/PDR reset flag This bit is set by hardware when a POR/PDR reset occurs. It is cleared by writing to the RMVF bit. 0: No POR/PDR reset occurred 1: POR/PDR reset occurred Bit 26 PINRSTF: PIN reset flag This bit is set by hardware when a reset from the NRST pin occurs. It is cleared by writing to the RMVF bit, or by a POR. 0: No reset from NRST pin occurred 1: Reset from NRST pin occurred Bit 25 OBLRSTF Options bytes loading reset flag This bit is set by hardware when an OBL reset occurs. It is cleared by writing to the RMVF bit, or by a POR. 0: No OBL reset occurred 1: OBL reset occurred Bit 24 FWRSTF: Firewall reset flag This bit is set by hardware when the firewall has generated a reset. It is cleared by writing to the RMVF bit, or by a power-on reset. 0: No firewall reset occurred 1: firewall reset occurred Bit 23 RMVF: Remove reset flag This bit is set by software to clear the reset flags. 0: No effect 1: Clear the reset flags Bits 22:20 Reserved, must be kept at reset value. 207/874 DocID025942 Rev 5 RM0377 Reset and clock control (RCC) Bit 19 RTCRST: RTC software reset bit This bit is set and cleared by software. 0: Reset not activated 1: Resets the RTC peripheral, its clock source selection and the backup registers. Bit 18 RTCEN: RTC clock enable bit This bit is set and cleared by software. It is reset by setting the RTCRST bit or by a POR. 0: RTC clock disabled 1: RTC clock enabled Bits 17:16 RTCSEL[1:0]: RTC clock source selection bits These bits are set by software to select the clock source for the RTC. Once the RTC clock source has been selected it cannot be switched until RTCRST is set or a Power On Reset occurred. The only exception is if the LSE oscillator clock was selected, if the LSE clock stops and it is detected by the CSSHSE, in that case the clock can be switched. 00: No clock 01: LSE oscillator clock used as RTC clock 10: LSI oscillator clock used as RTC clock 11: HSE oscillator clock divided by a programmable prescaler (selection through the RTCPRE[1:0] bits in the RCC clock control register (RCC_CR)) used as the RTC clock If the LSE or LSI is used as RTC clock source, the RTC continues to work in Stop and Standby low-power modes, and can be used as wake-up source. However, when the HSE clock is used as RTC clock source, the RTC cannot be used in Stop and Standby low-power modes. Bit 15: Reserved, must be kept at reset value. Bit 14 CSSLSED: CSS on LSE failure detection flag This bit is set by hardware to indicate when a failure has been detected by the clock security system on the external 32 kHz oscillator (LSE). It is cleared by a power-on reset or by an RTC software reset (RTCRST bit). 0: No failure detected on LSE (32 kHz oscillator) 1: Failure detected on LSE (32 kHz oscillator) Bit 13 CSSLSEON CSS on LSE enable bit This bit is set by software to enable the Clock Security System on LSE (32 kHz oscillator). CSSLSEON must be enabled after the LSE and LSI oscillators are enabled (LSEON and LSION bits enabled) and ready (LSERDY and LSIRDY flags set by hardware), and after the RTCSEL bit is selected. Once enabled this bit cannot be disabled, except after an LSE failure detection (CSSLSED =1). In that case the software MUST disable the CSSLSEON bit. Reset by power on reset and RTC software reset (RTCRST bit). 0: CSS on LSE (32 kHz oscillator) OFF 1: CSS on LSE (32 kHz oscillator) ON Bits 12-11 LSEDRV; LSE oscillator Driving capability bits These bits are set by software to select the driving capability of the LSE oscillator. They are cleared by a power-on reset or an RTC reset. Once “00” has been written, the content of LSEDRV cannot be changed by software. 00: Lowest drive 01: Medium low drive 10: Medium high drive 11: Highest drive DocID025942 Rev 5 208/874 212 Reset and clock control (RCC) RM0377 Bit 10 LSEBYP: External low-speed oscillator bypass bit This bit is set and cleared by software to bypass oscillator in debug mode. This bit can be written only when the LSE oscillator is disabled. It is reset by setting the RTCRST bit or by a POR. 0: LSE oscillator not bypassed 1: LSE oscillator bypassed Bit 9 LSERDY: External low-speed oscillator ready bit This bit is set and cleared by hardware to indicate when the LSE oscillator is stable. After the LSEON bit is cleared, LSERDY goes low after 6 LSE oscillator clock cycles. It is reset by setting the RTCRST bit or by a POR. 0: External 32 kHz oscillator not ready 1: External 32 kHz oscillator ready Bit 8 LSEON: External low-speed oscillator enable bit This bit is set and cleared by software. It is reset by setting the RTCRST bit or by a POR. 0: LSE oscillator OFF 1:LSE oscillator ON Bits 7:3 Reserved, must be kept at reset value. Bit 1 LSIRDY: Internal low-speed oscillator ready bit This bit is set and cleared by hardware to indicate when the LSI oscillator is stable. After the LSION bit is cleared, LSIRDY goes low after 3 LSI oscillator clock cycles. This bit is reset by system reset. 0: LSI oscillator not ready 1: LSI oscillator ready Bit 0 LSION: Internal low-speed oscillator enable bit This bit is set and cleared by software. It is reset by system reset. 0: LSI oscillator OFF 1: LSI oscillator ON 209/874 DocID025942 Rev 5 0x20 RCC_AHBRSTR Reset value 0 0 DocID025942 Rev 5 0 0 Reset value 0 LSIRDYC 0 0 IOPARST LSERDYC 0 0 0 0 0 0 DMARST HSI16RDYC 0 IOPBRST 0 IOPCRST 0 Res. 0 Res. PLLRDYC HSERDYC 0 IOPERST MSIRDYF PLLRDYF HSERDYF HSI16RDYF LSERDYF LSIRDYF 0 0 0 0 0 0 LSIRDYIE 0 LSERDYIE 0 HSI16RDYIE 0 PLLRDYIE 0 HSERDYIE 0 MSIRDYIE 0 Res. 0 Res. x IOPDRST Res. 0 CSSLSE x Res. MSIRDYC 0 Res. CSSLSEF. Reset value x MSION HSI16RDYF HSI16KERON 0 0 0 0 HSI16CAL[7:0] x x x HSI16ON HSI16DIVF HSI16DIVEN HSI16OUTEN Res. Res. MSIRDY Res. Res. 0 Res. Res. 0 Res. CSSHSEF. SW [1:0] Res. 0 Res. CSSLSEC. SWS [1:0] Res. Res. Res. Res. Res. 1 Res. CSSHSEC. Reset value Res. Reset value IOPHRST Res. HPRE[3:0] Res. HSEON HSEBYP 1 Res. Res. Res. Res. PPRE1 [2:0] Res. 1 0 MIFRST Res. Res. Res. Res. PPRE2 [2:0] Res. 1 0 Res. Res. Res. Res. Res. Res. x 0 Res. Res. Res. Res. Res. Res. HSI16TRIM[4:0 ] 1 CRCRST Res. Res. Res. MSIRAN GE[2:0] 0 Res. Res. 0 Res. PLLSRC STOPWUCK 0 Res. Res. Res. MSICAL[7:0] Res. Res. HSERDY CSSLSEON 0 Res. Res. Res. Res. X X 0 X 0 Res. Res. x Res. 0 Res. 0 Res. 0 Res. 0 Res. Res. 0 Res. Res. 0 Res. x Res. Res. Res. Res. x Res. Res. Res. x Res. x Res. 0 Res. Res. PLL ON RTC PRE [1:0] Res. Res. 0 Res. 0x08 Res. Res. Res. x Res. Res. 0 Res. MSITRIM[7:0] Res. Res. PLLMUL[3: 0] Res. x Res. Res. Res. 0 Res. Res. Res. PLL RDY 0 Res. Res. PLL DIV [1:0] Res. Res. Res. Res. Res. Res. 0 Res. Res. 0 CRYPRST Res. MCOSE L [3:0] Res. 0 Res. Res. Res. Reset value Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. 0 Res. Res. Res. Res. MCOPR E [2:0] Res. Res. 0 Res. 0 Res. RCC_IOPRSTR Res. RCC_CICR 0 Res. 0x1C RCC_CIFR 0 Res. 0x18 RCC_ICSCR Res. 0x14 RCC_CIER Res. Reset value Res. 0x10 RCC_CFGR Res. 0x0C 0 Res. Reset value Res. 0x04 RCC_CR Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 7.3.21 Res. RM0377 Reset and clock control (RCC) RCC register map The following table gives the RCC register map and the reset values. Table 42. RCC register map and reset values 0 Reserved x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 210/874 212 0x44 211/874 RCC_APB2SM ENR Reset value 1 DocID025942 Rev 5 1 Res. 1 1 1 1 1 IOPBSMEN IOPASMEN 1 1 1 Res. DMASMEN 1 1 Res. TIM3EN TIM2EN 1 0 SYSCFGEN Res. TIM21EN IOPCEN IOPBEN IOPAEN 0 0 0 Res. DMAEN Res. TIM3RST TIM2RST Res. Res. 0 SYSCFGSMEN Res. 0 IOPCSMEN 1 Res. 0 Res. TIM6RST IOPEEN IOPDEN 0 Res. 0 TIM21SMEN Res. Res. TIM7RST Res. Res. Res. Res. Res. 0 Res. TIM6EN IOPESMEN 1 IOPDSMEN 0 Res. 0 Res. Res. Res. Res. IOPHEN Res. Res. WWDRST Res. Res. 0 Res. TIM22EN Res. Res. MIFEN 0 Res. 0 TIM7EN 0 Res. Res. Res. FWEN Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. SPI2RST Res. 0 TIM22SMEN Res. Reset value Res. Res. 0 IOPHSMEN 0 Res. ADCEN Res. Res. Reset value Res. MIFSMEN 1 Res. 0 Res 0 Res. Res. WWDGEN Res. CRCEN Res. Res. 0 SRAMSMEN Res. Res. Res. SPI1EN Res. 0 ADCSMEN Res. Res. 0 Res. 1 Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. USART1EN 0 CRCSMEN SPI2EN Res. USART2RST Res. Res. LPUART1RST Res. Res. USART4RST Res. 0 SPI1SMEN Res. 0 Res. Res. Res. Res. I2C1RST USART5RST Res. 0 USART1SMEN Res. 0 Res. Res. Res. I2C2RST 0 Res. 0 Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. 0 Res. USART2EN 0 Res. Res. Res. Res. Res. 0 Res. LPUART1EN 0 Res. Res. Res. Res. 0 Res. USART4EN 0 Res. Res. Res. 0 Res. Res. Res. Res. I2C1EN USART5EN 0 Res. DBGEN Res. CRYPEN Res. Res. 0 Res. Res. Res. Res. Res. Res. I2C2EN 0 Res. Res. Res. Res. 0 Res. Res. Res 0 Res. Res. Reset value Res. Res. Res. Res. Res. Reset value DBGSMEN Reset value Res. RCC_IOPSMEN CRYPSMEN 0 Res. Reset value Res. 0 Res. 0 Res. RCC_IOPENR Res. Res. 0 Res. Res. Res. PWRRST 0 Res. Res. Res. Res. 0 Res. 0 Res. Res. Res. I2C3RST 0 Res. Res. 0 Res. LPTIM1RST 0 Res. Res. PWREN Reset value Res. Res. Res. Reset value Res. Res. Res. Res. Res. RCC_APB1RSTR Res. Res. RCC_AHBSM ENR Res. RCC_APB2ENR Res. 0x40 RCC_AHBENR Res. 0x3C RCC_APB1ENR I2C3EN 0x38 LPTIM1EN 0x34 Res. 0x30 Res. 0x2C Res. 0x28 SYSCFGRST Res. TIM21RST Res. Res. TM12RST Res. Res. Res. ADCRST Res. Res. SPI1RST Res. USART1RST Res. Res. Res. Res. Res. Res. Res. DBGRST Res. Res. Res. Res. Res. Res. Res. Res. Res. RCC_APB2RSTR Res. 0x24 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. Reset and clock control (RCC) RM0377 Table 42. RCC register map and reset values (continued) 0 0 0 0 0 0 0 1 1 0x50 PINRSTF OBLRSTF FWRSTF RMVF 0 0 0 0 1 1 0 0 0 RTCEN 0 0 RTC SEL [1:0] 0 DocID025942 Rev 5 0 LPUART1SEL0 0 0 0 LSE DRV [1:0] 0 0 0 0 0 USART2SEL0 USART1SEL1 USART1SEL0 0 0 0 0 Res. LSIRDY LSION TIM6SMEN TIM3SMEN TIM2SMEN Res. Res. TIM7SMEN Res. Res. Res. Res Res. WWDGSMEN Res. Res. 1 USART2SEL1 Res. Res. Res. Res. Res. Res. SPI2SMEN 1 Res. Res. LPUART1SEL1 1 Res. I2C1SEL0 0 Res. I2C1SEL1 Res. 0 Res. I2C3SEL0 0 Res. I2C3SEL1 0 LSEON LPTIM1SEL0 0 LSEBYP LPTIM1SEL1 0 1 LSERDY Res. 0 CSSLSEON 1 CSSLSED USART2SMEN 1 Res. USART4SMEN LPUART1SMEN 1 Res. I2C1SMEN USART5SMEN 1 Res. Res Res. Res. Res. Res. PWRSMEN I2C2SMEN Res. Res. Res. Res Res. Res. 1 Res. RCC_CCIPR 1 Res. 0 RTCRST Res. Reset value Res. 1 Res. I2C3SMEN 1 Res. LPTIM1SMEN Reset value 1 Res. PORRSTF Reset value SFTRSTF RCC_CSR IWDGRSTF 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RCC_APB1 SMENR Res. 0x4C Register Res. 0x48 LPWRSTF Offset WWDGRSTF RM0377 Reset and clock control (RCC) Table 42. RCC register map and reset values (continued) 1 1 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. 212/874 212 General-purpose I/Os (GPIO) RM0377 8 General-purpose I/Os (GPIO) 8.1 Introduction Each general-purpose I/O port has four 32-bit configuration registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR and GPIOx_PUPDR), two 32-bit data registers (GPIOx_IDR and GPIOx_ODR) and a 32-bit set/reset register (GPIOx_BSRR). In addition all GPIOs have a 32-bit locking register (GPIOx_LCKR) and two 32-bit alternate function selection registers (GPIOx_AFRH and GPIOx_AFRL). 8.2 8.3 GPIO main features Output states: push-pull or open drain + pull-up/down Output data from output data register (GPIOx_ODR) or peripheral (alternate function output) Speed selection for each I/O Input states: floating, pull-up/down, analog Input data to input data register (GPIOx_IDR) or peripheral (alternate function input) Bit set and reset register (GPIOx_ BSRR) for bitwise write access to GPIOx_ODR Locking mechanism (GPIOx_LCKR) provided to freeze the I/O port configurations Analog function Alternate function selection registers Fast toggle capable of changing every two clock cycles Highly flexible pin multiplexing allows the use of I/O pins as GPIOs or as one of several peripheral functions GPIO functional description Subject to the specific hardware characteristics of each I/O port listed in the datasheet, each port bit of the general-purpose I/O (GPIO) ports can be individually configured by software in several modes: Input floating Input pull-up Input-pull-down Analog Output open-drain with pull-up or pull-down capability Output push-pull with pull-up or pull-down capability Alternate function push-pull with pull-up or pull-down capability Alternate function open-drain with pull-up or pull-down capability Each I/O port bit is freely programmable, however the I/O port registers have to be accessed as 32-bit words, half-words or bytes. The purpose of the GPIOx_BSRR and GPIOx_BRR registers is to allow atomic read/modify accesses to any of the GPIOx_ODR registers. In this way, there is no risk of an IRQ occurring between the read and the modify access. 213/874 DocID025942 Rev 5 RM0377 General-purpose I/Os (GPIO) Figure 20 and Figure 21 show the basic structures of a standard and a 5 V tolerant I/O port bit, respectively. Table 43 gives the possible port bit configurations. Figure 20. Basic structure of an I/O port bit $QDORJ 7RRQFKLS SHULSKHUDO $OWHUQDWHIXQFWLRQLQSXW ,QSXWGDWDUHJLVWHU RQRII 9'',2[9'',2[ WULJJHU RQRII ,2SLQ 2XWSXWGULYHU 9'',2[ RQRII 3026 3URWHFWLRQ GLRGH 3XOO GRZQ 966 2XWSXW FRQWURO 966 1026 5HDGZULWH )URPRQFKLS SHULSKHUDO 3URWHFWLRQ GLRGH 3XOO XS ,QSXWGULYHU 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG 966 $OWHUQDWHIXQFWLRQRXWSXW 3XVKSXOO RSHQGUDLQRU GLVDEOHG $QDORJ 069 Figure 21. Basic structure of a five-volt tolerant I/O port bit 7RRQFKLS SHULSKHUDO ,QSXWGDWDUHJLVWHU $OWHUQDWHIXQFWLRQLQSXW 5HDGZULWH )URPRQFKLS SHULSKHUDO 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG $OWHUQDWHIXQFWLRQRXWSXW RQRII 9'',2[ 9''B)7 77/6FKPLWW WULJJHU RQRII 3XOO XS 3URWHFWLRQ GLRGH ,QSXWGULYHU ,2SLQ 2XWSXWGULYHU 9'',2[ RQRII 3026 2XWSXW FRQWURO 3XOO GRZQ 966 3URWHFWLRQ GLRGH 966 1026 966 3XVKSXOO RSHQGUDLQRU GLVDEOHG DLG 1. VDD_FT is a potential specific to five-volt tolerant I/Os and different from VDD. DocID025942 Rev 5 214/874 230 General-purpose I/Os (GPIO) RM0377 Table 43. Port bit configuration table(1) MODE(i) [1:0] 01 10 00 11 OTYPER(i) OSPEED(i) [1:0] PUPD(i) [1:0] I/O configuration 0 0 0 GP output PP 0 0 1 GP output PP + PU 0 1 0 GP output PP + PD 1 1 Reserved 0 0 GP output OD 1 0 1 GP output OD + PU 1 1 0 GP output OD + PD 1 1 1 Reserved (GP output OD) 0 0 0 AF PP 0 0 1 AF PP + PU 0 1 0 AF PP + PD 1 1 Reserved 0 0 AF OD 1 0 1 AF OD + PU 1 1 0 AF OD + PD 1 1 1 Reserved 0 SPEED [1:0] 1 0 SPEED [1:0] 1 x x x 0 0 Input Floating x x x 0 1 Input PU x x x 1 0 Input PD x x x 1 1 Reserved (input floating) x x x 0 0 Input/output x x x 0 1 x x x 1 0 x x x 1 1 Analog Reserved 1. GP = general-purpose, PP = push-pull, PU = pull-up, PD = pull-down, OD = open-drain, AF = alternate function. 215/874 DocID025942 Rev 5 RM0377 8.3.1 General-purpose I/Os (GPIO) General-purpose I/O (GPIO) During and just after reset, the alternate functions are not active and most of the I/O ports are configured in analog mode. The debug pins are in AF pull-up/pull-down after reset: PA14: SWCLK in pull-down PA13: SWDIO in pull-up When the pin is configured as output, the value written to the output data register (GPIOx_ODR) is output on the I/O pin. It is possible to use the output driver in push-pull mode or open-drain mode (only the low level is driven, high level is HI-Z). The input data register (GPIOx_IDR) captures the data present on the I/O pin at every AHB clock cycle. All GPIO pins have weak internal pull-up and pull-down resistors, which can be activated or not depending on the value in the GPIOx_PUPDR register. 8.3.2 I/O pin alternate function multiplexer and mapping The device I/O pins are connected to on-board peripherals/modules through a multiplexer that allows only one peripheral alternate function (AF) connected to an I/O pin at a time. In this way, there can be no conflict between peripherals available on the same I/O pin. Each I/O pin has a multiplexer with up to sixteen alternate function inputs (AF0 to AF15) that can be configured through the GPIOx_AFRL (for pin 0 to 7) and GPIOx_AFRH (for pin 8 to 15) registers: After reset the multiplexer selection is alternate function 0 (AF0). The I/Os are configured in alternate function mode through GPIOx_MODER register. The specific alternate function assignments for each pin are detailed in the device datasheet. In addition to this flexible I/O multiplexing architecture, each peripheral has alternate functions mapped onto different I/O pins to optimize the number of peripherals available in smaller packages. To use an I/O in a given configuration, the user has to proceed as follows: Debug function: after each device reset these pins are assigned as alternate function pins immediately usable by the debugger host GPIO: configure the desired I/O as output, input or analog in the GPIOx_MODER register. Peripheral alternate function: – Connect the I/O to the desired AFx in one of the GPIOx_AFRL or GPIOx_AFRH register. – Select the type, pull-up/pull-down and output speed via the GPIOx_OTYPER, GPIOx_PUPDR and GPIOx_OSPEEDER registers, respectively. – Configure the desired I/O as an alternate function in the GPIOx_MODER register. Additional functions: – For the ADC and COMP, configure the desired I/O in analog mode in the GPIOx_MODER register and configure the required function in the ADC and COMP registers. DocID025942 Rev 5 216/874 230 General-purpose I/Os (GPIO) – RM0377 For the additional functions like RTC, WKUPx and oscillators, configure the required function in the related RTC, PWR and RCC registers. These functions have priority over the configuration in the standard GPIO registers. Please refer to the “Alternate function mapping” table in the device datasheet for the detailed mapping of the alternate function I/O pins. 8.3.3 I/O port control registers Each of the GPIO ports has four 32-bit memory-mapped control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR) to configure up to 16 I/Os. The GPIOx_MODER register is used to select the I/O mode (input, output, AF, analog). The GPIOx_OTYPER and GPIOx_OSPEEDR registers are used to select the output type (pushpull or open-drain) and speed. The GPIOx_PUPDR register is used to select the pullup/pull-down whatever the I/O direction. 8.3.4 I/O port data registers Each GPIO has two 16-bit memory-mapped data registers: input and output data registers (GPIOx_IDR and GPIOx_ODR). GPIOx_ODR stores the data to be output, it is read/write accessible. The data input through the I/O are stored into the input data register (GPIOx_IDR), a read-only register. See Section 8.4.5: GPIO port input data register (GPIOx_IDR) (x = A..E and H) and Section 8.4.6: GPIO port output data register (GPIOx_ODR) (x = A..E and H) for the register descriptions. 8.3.5 I/O data bitwise handling The bit set reset register (GPIOx_BSRR) is a 32-bit register which allows the application to set and reset each individual bit in the output data register (GPIOx_ODR). The bit set reset register has twice the size of GPIOx_ODR. To each bit in GPIOx_ODR, correspond two control bits in GPIOx_BSRR: BS(i) and BR(i). When written to 1, bit BS(i) sets the corresponding ODR(i) bit. When written to 1, bit BR(i) resets the ODR(i) corresponding bit. Writing any bit to 0 in GPIOx_BSRR does not have any effect on the corresponding bit in GPIOx_ODR. If there is an attempt to both set and reset a bit in GPIOx_BSRR, the set action takes priority. Using the GPIOx_BSRR register to change the values of individual bits in GPIOx_ODR is a “one-shot” effect that does not lock the GPIOx_ODR bits. The GPIOx_ODR bits can always be accessed directly. The GPIOx_BSRR register provides a way of performing atomic bitwise handling. There is no need for the software to disable interrupts when programming the GPIOx_ODR at bit level: it is possible to modify one or more bits in a single atomic AHB write access. 217/874 DocID025942 Rev 5 RM0377 8.3.6 General-purpose I/Os (GPIO) GPIO locking mechanism It is possible to freeze the GPIO control registers by applying a specific write sequence to the GPIOx_LCKR register. The frozen registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. To write the GPIOx_LCKR register, a specific write / read sequence has to be applied. When the right LOCK sequence is applied to bit 16 in this register, the value of LCKR[15:0] is used to lock the configuration of the I/Os (during the write sequence the LCKR[15:0] value must be the same). When the LOCK sequence has been applied to a port bit, the value of the port bit can no longer be modified until the next MCU reset or peripheral reset. Each GPIOx_LCKR bit freezes the corresponding bit in the control registers (GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR, GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. The LOCK sequence (refer to Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..E and H)) can only be performed using a word (32-bit long) access to the GPIOx_LCKR register due to the fact that GPIOx_LCKR bit 16 has to be set at the same time as the [15:0] bits. For code example, refer to A.5.1: Locking mechanism code example. For more details please refer to LCKR register description in Section 8.4.8: GPIO port configuration lock register (GPIOx_LCKR) (x = A..E and H). 8.3.7 I/O alternate function input/output Two registers are provided to select one of the alternate function inputs/outputs available for each I/O. With these registers, the user can connect an alternate function to some other pin as required by the application. This means that a number of possible peripheral functions are multiplexed on each GPIO using the GPIOx_AFRL and GPIOx_AFRH alternate function registers. The application can thus select any one of the possible functions for each I/O. The AF selection signal being common to the alternate function input and alternate function output, a single channel is selected for the alternate function input/output of a given I/O. To know which functions are multiplexed on each GPIO pin, refer to the device datasheet. For code example, refer to A.5.2: Alternate function selection sequence code example. 8.3.8 External interrupt/wakeup lines All ports have external interrupt capability. To use external interrupt lines, the port must be configured in input mode.Section 12: Extended interrupt and event controller (EXTI) and to Section 12.3.2: Wakeup event management. DocID025942 Rev 5 218/874 230 General-purpose I/Os (GPIO) 8.3.9 RM0377 Input configuration When the I/O port is programmed as input: The output buffer is disabled The Schmitt trigger input is activated The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register The data present on the I/O pin are sampled into the input data register every AHB clock cycle A read access to the input data register provides the I/O state Figure 22 shows the input configuration of the I/O port bit. ,QSXWGDWDUHJLVWHU Figure 22. Input floating/pull up/pull down configurations 5HDGZULWH 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG RQ 77/6FKPLWW WULJJHU LQSXWGULYHU 9'',2[ 9'',2[ RQRII SURWHFWLRQ GLRGH SXOO XS ,2SLQ RQRII RXWSXWGULYHU SXOO GRZQ 966 SURWHFWLRQ GLRGH 966 069 8.3.10 Output configuration When the I/O port is programmed as output: The output buffer is enabled: – Open drain mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register leaves the port in Hi-Z (the P-MOS is never activated) – Push-pull mode: A “0” in the Output register activates the N-MOS whereas a “1” in the Output register activates the P-MOS The Schmitt trigger input is activated The pull-up and pull-down resistors are activated depending on the value in the GPIOx_PUPDR register The data present on the I/O pin are sampled into the input data register every AHB clock cycle A read access to the input data register gets the I/O state A read access to the output data register gets the last written value Figure 23 shows the output configuration of the I/O port bit. 219/874 DocID025942 Rev 5 RM0377 General-purpose I/Os (GPIO) ,QSXWGDWDUHJLVWHU Figure 23. Output configuration RQ 5HDGZULWH 9'',2[ 9'',2[ 77/6FKPLWW WULJJHU RQRII ,QSXWGULYHU 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG SURWHFWLRQ GLRGH SXOO XS 2XWSXWGULYHU 9'',2[ ,2SLQ RQRII 3026 SURWHFWLRQ GLRGH SXOO GRZQ 2XWSXW FRQWURO 966 1026 3XVKSXOORU 966 2SHQGUDLQ 966 069 Alternate function configuration When the I/O port is programmed as alternate function: The output buffer can be configured in open-drain or push-pull mode The output buffer is driven by the signals coming from the peripheral (transmitter enable and data) The Schmitt trigger input is activated The weak pull-up and pull-down resistors are activated or not depending on the value in the GPIOx_PUPDR register The data present on the I/O pin are sampled into the input data register every AHB clock cycle A read access to the input data register gets the I/O state Figure 24 shows the Alternate function configuration of the I/O port bit. Figure 24. Alternate function configuration ,QSXW GDWD UHJLVWHU $OWHUQDWH IXQFWLRQ LQSXW 7R RQFKLS SHULSKHUDO 5HDG 5HDGZULWH )URP RQFKLS SHULSKHUDO RQ 9'',2[9'',2[ 77/ 6FKPLWW WULJJHU RQRII SURWHFWLRQ GLRGH 3XOO XS ,QSXW GULYHU 2XWSXW GDWD UHJLVWHU :ULWH %LW VHWUHVHW UHJLVWHUV 8.3.11 ,2 SLQ 2XWSXW GULYHU RQRII 9'' 3026 2XWSXW FRQWURO SURWHFWLRQ GLRGH 3XOO GRZQ 966 966 1026 966 SXVKSXOO RU RSHQGUDLQ $OWHUQDWH IXQFWLRQ RXWSXW 06Y9 DocID025942 Rev 5 220/874 230 General-purpose I/Os (GPIO) 8.3.12 RM0377 Analog configuration When the I/O port is programmed as analog configuration: The output buffer is disabled The Schmitt trigger input is deactivated, providing zero consumption for every analog value of the I/O pin. The output of the Schmitt trigger is forced to a constant value (0). The weak pull-up and pull-down resistors are disabled by hardware Read access to the input data register gets the value “0” For code example, refer to A.5.3: Analog GPIO configuration code example. Figure 25 shows the high-impedance, analog-input configuration of the I/O port bit. Figure 25. High impedance-analog configuration ,QSXWGDWDUHJLVWHU $QDORJ 7RRQFKLS SHULSKHUDO 5HDGZULWH )URPRQFKLS SHULSKHUDO 8.3.13 2XWSXWGDWDUHJLVWHU :ULWH %LWVHWUHVHWUHJLVWHUV 5HDG RII 9'',2[ 77/6FKPLWW WULJJHU SURWHFWLRQ GLRGH ,QSXWGULYHU ,2SLQ SURWHFWLRQ GLRGH 966 $QDORJ 069 Using the HSE or LSE oscillator pins as GPIOs When the HSE or LSE oscillator is switched OFF (default state after reset), the related oscillator pins can be used as normal GPIOs. When the HSE or LSE oscillator is switched ON (by setting the HSEON or LSEON bit in the RCC_CSR register) the oscillator takes control of its associated pins and the GPIO configuration of these pins has no effect. When the oscillator is configured in a user external clock mode, only the OSC_IN, CK_IN or OSC32_IN pin is reserved for clock input and the OSC_OUT or OSC32_OUT pin can still be used as normal GPIO. 8.3.14 Using the GPIO pins in the RTC supply domain The PC13/PC14/PC15/PA0/PA2 GPIO functionality is lost when the core supply domain is powered off (when the device enters Standby mode). In this case, if their GPIO configuration is not bypassed by the RTC configuration, these pins are set in an analog input mode. For details about I/O control by the RTC, refer to Section 22.3: RTC functional description on page 528. 221/874 DocID025942 Rev 5 RM0377 8.3.15 General-purpose I/Os (GPIO) BOOT0/GPIO pin sharing On category 1 devices, the BOOT0 pin is shared with a GPIO pin. The BOOT0 pin input level can be read as an input value on the shared GPIO pin. This pin features specific input voltage characteristics (refer to the corresponding datasheet for more details). DocID025942 Rev 5 222/874 230 General-purpose I/Os (GPIO) 8.4 RM0377 GPIO registers This section gives a detailed description of the GPIO registers. For a summary of register bits, register address offsets and reset values, refer to Table 44. The peripheral registers can be written in word, half word or byte mode. 8.4.1 GPIO port mode register (GPIOx_MODER) (x =A..E and H) Address offset:0x00 Reset values: 31 30 0xEBFF FCFF for port A 0xFFFF FFFF for the other ports 29 MODE15[1:0] 28 MODE14[1:0] 27 26 MODE13[1:0] 25 24 MODE12[1:0] 23 22 MODE11[1:0] 21 20 MODE10[1:0] 19 18 17 16 MODE9[1:0] MODE8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MODE7[1:0] MODE6[1:0] MODE5[1:0] MODE4[1:0] MODE3[1:0] MODE2[1:0] MODE1[1:0] MODE0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y+1:2y MODEy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O mode. 00: Input mode 01: General purpose output mode 10: Alternate function mode 11: Analog mode (reset state) 8.4.2 GPIO port output type register (GPIOx_OTYPER) (x = A..E and H) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OT15 OT14 OT13 OT12 OT11 OT10 OT9 OT8 OT7 OT6 OT5 OT4 OT3 OT2 OT1 OT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 OTy: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output type. 0: Output push-pull (reset state) 1: Output open-drain 223/874 DocID025942 Rev 5 RM0377 General-purpose I/Os (GPIO) 8.4.3 GPIO port output speed register (GPIOx_OSPEEDR) (x = A..E and H) Address offset: 0x08 Reset value: 31 0x0C00 0000 for port A 0x0000 0000 for the other ports 30 29 OSPEED15 [1:0] 28 27 26 25 24 23 22 21 20 19 18 17 16 OSPEED14 [1:0] OSPEED13 [1:0] OSPEED12 [1:0] OSPEED11 [1:0] OSPEED10 [1:0] OSPEED9 [1:0] OSPEED8 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSPEED7 [1:0] OSPEED6 [1:0] OSPEED5 [1:0] OSPEED4 [1:0] OSPEED3 [1:0] OSPEED2 [1:0] OSPEED1 [1:0] OSPEED0 [1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y+1:2y OSPEEDy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O output speed. 00: Low speed 01: Medium speed 10: High speed 11: Very high speed Note: Refer to the device datasheet for the frequency specifications and the power supply and load conditions for each speed. 8.4.4 GPIO port pull-up/pull-down register (GPIOx_PUPDR) (x = A..E and H) Address offset: 0x0C Reset values: 31 30 PUPD15[1:0] 0x2400 0000 for port A 0x0000 0000 for the other ports 29 28 PUPD14[1:0] 27 26 PUPD13[1:0] 25 24 23 22 21 20 19 18 17 16 PUPD12[1:0] PUPD11[1:0] PUPD10[1:0] PUPD9[1:0] PUPD8[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PUPD7[1:0] PUPD6[1:0] PUPD5[1:0] PUPD4[1:0] PUPD3[1:0] PUPD2[1:0] PUPD1[1:0] PUPD0[1:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 2y+1:2y PUPDy[1:0]: Port x configuration bits (y = 0..15) These bits are written by software to configure the I/O pull-up or pull-down 00: No pull-up, pull-down 01: Pull-up 10: Pull-down 11: Reserved DocID025942 Rev 5 224/874 230 General-purpose I/Os (GPIO) 8.4.5 RM0377 GPIO port input data register (GPIOx_IDR) (x = A..E and H) Address offset: 0x10 Reset value: 0x0000 XXXX (where X means undefined) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ID15 ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 ID2 ID1 ID0 r r r r r r r r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 IDy: Port input data bit (y = 0..15) These bits are read-only. They contain the input value of the corresponding I/O port. 8.4.6 GPIO port output data register (GPIOx_ODR) (x = A..E and H) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ODy: Port output data bit (y = 0..15) These bits can be read and written by software. Note: For atomic bit set/reset, the OD bits can be individually set and/or reset by writing to the GPIOx_BSRR or GPIOx_BRR registers (x = A..E and H). 8.4.7 GPIO port bit set/reset register (GPIOx_BSRR) (x = A..E and H) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BS15 BS14 BS13 BS12 BS11 BS10 BS9 BS8 BS7 BS6 BS5 BS4 BS3 BS2 BS1 BS0 w w w w w w w w w w w w w w w w 225/874 DocID025942 Rev 5 RM0377 General-purpose I/Os (GPIO) Bits 31:16 BRy: Port x reset bit y (y = 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Resets the corresponding ODx bit Note: If both BSx and BRx are set, BSx has priority. Bits 15:0 BSy: Port x set bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000. 0: No action on the corresponding ODx bit 1: Sets the corresponding ODx bit 8.4.8 GPIO port configuration lock register (GPIOx_LCKR) (x = A..E and H) This register is used to lock the configuration of the port bits when a correct write sequence is applied to bit 16 (LCKK). The value of bits [15:0] is used to lock the configuration of the GPIO. During the write sequence, the value of LCKR[15:0] must not change. When the LOCK sequence has been applied on a port bit, the value of this port bit can no longer be modified until the next MCU reset or peripheral reset. Note: A specific write sequence is used to write to the GPIOx_LCKR register. Only word access (32-bit long) is allowed during this locking sequence. Each lock bit freezes a specific configuration register (control and alternate function registers). Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. LCKK rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LCK15 LCK14 LCK13 LCK12 LCK11 LCK10 LCK9 LCK8 LCK7 LCK6 LCK5 LCK4 LCK3 LCK2 LCK1 LCK0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw DocID025942 Rev 5 226/874 230 General-purpose I/Os (GPIO) RM0377 Bits 31:17 Reserved, must be kept at reset value. Bit 16 LCKK: Lock key This bit can be read any time. It can only be modified using the lock key write sequence. 0: Port configuration lock key not active 1: Port configuration lock key active. The GPIOx_LCKR register is locked until the next MCU reset or peripheral reset. LOCK key write sequence: WR LCKR[16] = ‘1’ + LCKR[15:0] WR LCKR[16] = ‘0’ + LCKR[15:0] WR LCKR[16] = ‘1’ + LCKR[15:0] RD LCKR RD LCKR[16] = ‘1’ (this read operation is optional but it confirms that the lock is active) Note: During the LOCK key write sequence, the value of LCK[15:0] must not change. Any error in the lock sequence aborts the lock. After the first lock sequence on any bit of the port, any read access on the LCKK bit will return ‘1’ until the next MCU reset or peripheral reset. Bits 15:0 LCKy: Port x lock bit y (y= 0..15) These bits are read/write but can only be written when the LCKK bit is ‘0. 0: Port configuration not locked 1: Port configuration locked 8.4.9 GPIO alternate function low register (GPIOx_AFRL) (x = A..E and H) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 AFSEL7[3:0] rw 15 rw rw rw rw 14 13 12 11 AFSEL3[3:0] rw rw rw 26 25 24 23 AFSEL6[3:0] rw rw rw rw 10 9 8 7 AFSEL2[3:0] rw rw rw rw 22 21 20 19 AFSEL5[3:0] rw rw rw rw 6 5 4 3 AFSEL1[3:0] rw rw rw rw 227/874 1000: Reserved 1001: Reserved 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved 1111: Reserved DocID025942 Rev 5 17 16 rw rw rw 2 1 0 AFSEL0[3:0] rw rw Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 0..7) These bits are written by software to configure alternate function I/Os AFSELy selection: 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 18 AFSEL4[3:0] rw rw rw RM0377 General-purpose I/Os (GPIO) 8.4.10 GPIO alternate function high register (GPIOx_AFRH) (x = A..E and H) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 AFSEL15[3:0] 26 25 24 23 AFSEL14[3:0] 22 21 20 19 AFSEL13[3:0] 18 17 16 AFSEL12[3:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AFSEL11[3:0] rw rw rw AFSEL10[3:0] rw rw rw rw AFSEL9[3:0] rw rw rw rw AFSEL8[3:0] rw rw rw rw rw Bits 31:0 AFSELy[3:0]: Alternate function selection for port x pin y (y = 8..15) These bits are written by software to configure alternate function I/Os AFSELy selection: 0000: AF0 0001: AF1 0010: AF2 0011: AF3 0100: AF4 0101: AF5 0110: AF6 0111: AF7 8.4.11 1000: Reserved 1001: Reserved 1010: Reserved 1011: Reserved 1100: Reserved 1101: Reserved 1110: Reserved 1111: Reserved GPIO port bit reset register (GPIOx_BRR) (x =A..E and H) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BR15 BR14 BR13 BR12 BR11 BR10 BR9 BR8 BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 w w w w w w w w w w w w w w w w Bits 31:16 Reserved Bits 15:0 BRy: Port x Reset bit y (y= 0..15) These bits are write-only. A read to these bits returns the value 0x0000 0: No action on the corresponding ODx bit 1: Reset the corresponding ODx bit DocID025942 Rev 5 228/874 230 229/874 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. 0 0 0 0 DocID025942 Rev 5 OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ID0 Res. 0 ID1 Res. BS0 Res. BS1 Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LCK0 Res. 0x24 GPIOx_AFRH AFSEL15[3:0] AFSEL14[3:0] AFSEL13[3:0] AFSEL12[3:0] AFSEL11[3:0] AFSEL10[3:0] AFSEL9[3:0] AFSEL8[3:0] (where x = A..E,H) 0 LCK1 Res. 0x20 GPIOx_AFRL (where x = A..E,H) ID2 GPIOx_LCKR (where x = A..E,H) ID3 0x1C BS2 0 BS3 0 LCK2 0 LCK3 0 ID4 Res. 0 ID5 Res. 0 BS4 Res. BR3 0 BS5 Res. BR4 0 LCK4 Res. BR5 0 LCK5 Res. BR6 0 ID6 Res. BR7 0 Res. OSPEED7[1:0] 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIOx_OTYPER (where x = A..E,H) 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 OT1 OT0 0 0 MODE0[1:0] MODE1[1:0] 1 0 0 0 0 0 0 0 0 OSPEED0[1:0] OT2 1 OSPEED0[1:0] OT3 MODE2[1:0] 1 OSPEED1[1:0] OT4 1 OSPEED1[1:0] OT5 MODE3[1:0] 1 OSPEED2[1:0] OT6 MODE4[1:0] 0 OSPEED2[1:0] OT7 OSPEED3[1:0] OT8 MODE5[1:0] MODE6[1:0] MODE7[1:0] MODE8[1:0] MODE9[1:0] MODE10[1:0] MODE11[1:0] MODE12[1:0] MODE13[1:0] MODE14[1:0] 0 OSPEED3[1:0] OT9 OSPEED4[1:0] 0 OSPEED4[1:0] OT11 OT10 OSPEED5[1:0] OT12 0 OSPEED5[1:0] OT13 OSPEED6[1:0] 0 OSPEED6[1:0] OT14 1 OT15 OSPEED7[1:0] OSPEED8[1:0] 1 0 1 PUPD0[1:0] OSPEED8[1:0] OSPEED9[1:0] 1 0 1 PUPD1[1:0] OSPEED9[1:0] OSPEED10[1:0] OSPEED11[1:0] OSPEED12[1:0] 1 0 1 PUPD2[1:0] OSPEED10[1:0] 0 1 PUPD3[1:0] OSPEED11[1:0] 0 1 PUPD4[1:0] OSPEED12[1:0] OSPEED13[1:0] 1 Res. MODE15[1:0] 1 PUPD5[1:0] OSPEED13[1:0] OSPEED14[1:0] 1 Res. 1 PUPD6[1:0] PUPD7[1:0] PUPD8[1:0] PUPD9[1:0] PUPD10[1:0] PUPD11[1:0] PUPD12[1:0] PUPD13[1:0] 0 ID7 Res. BR8 0 BS6 Res. BR9 0 BS7 Res. BR11 Reset value LCK6 Res. 0x18 GPIOx_BSRR (where x = A..E,H) LCK7 Res. 0x14 GPIOx_ODR (where x = A..E,H) BR10 0 ID8 0x10 0 0 ID9 0 BS8 0 BS9 0 LCK8 0 LCK9 0 0 0 ID11 0 Res. OSPEED14[1:0] Reset value ID10 0 BS11 0 BS10 0 LCK11 0 0 0 LCK10 0 0 0 1 ID12 0 0 0 0 1 ID13 0 0 0 0 BS12 0 0 0 0 1 BS13 0 0 0 0 1 LCK12 0 0 0 0 1 LCK13 0 0 0 0 1 ID14 0 Res. PUPD14[1:0] 0 0 1 ID15 0 0 0 1 1 BS14 0 0 1 1 BS15 0 Res. 0 0 0 LCK14 0 Res. 0 1 LCK15 0 0 0 Res. GPIOA_PUPDR 0 Res. Reset value 0 0 BR0 0 BR12 0x0C GPIOx_OSPEEDR (where x = B..E,H) 0 1 BR1 0 BR13 Reset value 1 Res. 0 Res. 0x08 GPIOA_OSPEEDR 1 LCKK 1 Res. 0x08 Reset value Res. 0x04 GPIOx_MODER (where x = B..E, H) OSPEED15[1:0] Reset value OSPEED15[1:0] 0x00 MODE0[1:0] MODE1[1:0] MODE2[1:0] MODE3[1:0] MODE4[1:0] MODE5[1:0] MODE6[1:0] MODE7[1:0] MODE8[1:0] MODE9[1:0] MODE10[1:0] MODE11[1:0] MODE12[1:0] MODE13[1:0] MODE14[1:0] MODE15[1:0] GPIOA_MODER PUPD15[1:0] 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register BR2 0 Res. Offset Res. 8.4.12 Res. 0 Res. Reset value 1 BR14 Reset value 0 BR15 Reset value 0 Res. Reset value Reset value GPIOx_IDR (where x = A..E,H) Res. General-purpose I/Os (GPIO) RM0377 GPIO register map The following table gives the GPIO register map and reset values. Table 44. GPIO register map and reset values 1 1 0 0 0 0 1 0 0 x x x x x x x x x x x x x x x x 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AFSEL7[3:0] AFSEL6[3:0] AFSEL5[3:0] AFSEL4[3:0] AFSEL3[3:0] AFSEL2[3:0] AFSEL1[3:0] AFSEL0[3:0] 0 0 RM0377 General-purpose I/Os (GPIO) BR7 BR6 BR5 BR4 BR3 BR2 BR1 BR0 0 BR8 0 BR9 BR12 0 BR11 BR13 0 BR10 BR14 Res. Reset value BR15 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. GPIOx_BRR (where x = A..E,H) Res. 0x28 Res. Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 44. GPIO register map and reset values (continued) 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. DocID025942 Rev 5 230/874 230 System configuration controller (SYSCFG) 9 System configuration controller (SYSCFG) 9.1 Introduction RM0377 The devices feature a set of configuration registers. The main purposes of the system configuration controller are the following: Remapping memories Remapping some trigger sources to timer input capture channels Managing external interrupts line multiplexing to the internal edge detector Enabling dedicated functions such as input capture multiplexing or oscillator pin remapping I2C Fm+ mode management Firewall management Temperature sensor and Internal voltage reference management (including for Comparator and ADC purposes). The Cortex®-M0+ can wake up from WFE (Wait For Event) when a transition occurs on the eventin input signal. To support semaphore management in multiprocessor environment, the core can also output events on the signal output EVENTOUT, during SEV instruction execution. In STM32L0x1 devices, an event input can be generated by an external interrupt line or by an RTC alarm interrupt. It is also possible to select which output pin is connected to the EVENTOUT signal of the Cortex®-M0+. The EVENTOUT multiplexing is managed by the GPIO alternate function capability (see Section 8.4.9: GPIO alternate function low register (GPIOx_AFRL) (x = A..E and H) and Section 8.4.10: GPIO alternate function high register (GPIOx_AFRH) (x = A..E and H)). Note: 231/874 EVENTOUT is not mapped on all GPIOs (for example PC13, PC14, PC15). DocID025942 Rev 5 RM0377 System configuration controller (SYSCFG) 9.2 SYSCFG registers The peripheral registers have to be accessed by words (32-bit). 9.2.1 SYSCFG memory remap register (SYSCFG_CFGR1) This register is used for specific configurations related to memory remap: Note: This register is not reset through the SYSCFGRST bit in the RCC_APB2RSTR register. Address offset: 0x00 Reset value: 0x000x 000x (X is the memory mode selected by the boot configuration). ) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 9 8 1 0 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. BOOT_MODE r 7 6 5 4 3 2 Res. Res. Res. Res. UFB Res. r rw MEM_MODE rw rw Bits 31:10 Reserved, must be kept at reset value Bits 9:8 BOOT_MODE: Boot mode selected by the boot pins status bits These bits are read-only. They indicate the boot mode selected by the boot configuration (see Section 2.4: Boot configuration on page 53). 00: Main Flash memory boot mode 01: System Flash memory boot mode 10: Reserved 11: Embedded SRAM boot mode Bits 7:4 Reserved, must be kept at reset value Bit 3 UFB: User bank swapping This bit is available only on category 5 devices and reserved on other categories. It is set and cleared by software. It controls the Bank 1/2 mapping (see Table 10: NVM organization for UFB = 0 (128 Kbyte category 5 devices) and Table 12: NVM organization for UFB = 0 (64 Kbyte category 5 devices)). 0: Flash Program memory Bank 1 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if MEM_MODE=00) and Data EEPROM Bank 1 at 0x0808 0000 (aliased at 0x0008 0000 if MEM_MODE=00) 1: Flash Program memory Bank 2 is mapped at 0x0800 0000 (and aliased at 0x0000 0000 if MEM_MODE=00) and Data EEPROM Bank 2 at 0x0808 0000 (and aliased at 0x0008 0000 if MEM_MODE=00) Bit 2 Reserved, must be kept at reset value Bits 1:0 MEM_MODE: Memory mapping selection bits These bits are set and cleared by software. This bit controls the memory’s internal mapping at address 0x0000 0000. After reset these bits take on the memory mapping selected by the boot configuration (see Section 2.4: Boot configuration on page 53). 00: Main Flash memory mapped at 0x0000 0000 01: System Flash memory mapped at 0x0000 0000 10: reserved 11: SRAM mapped at 0x0000 0000. DocID025942 Rev 5 232/874 238 System configuration controller (SYSCFG) 9.2.2 RM0377 SYSCFG peripheral mode configuration register (SYSCFG_CFGR2) Address offset: 0x04 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. I2C3_ I2C_PB9 I2C_PB8 I2C_PB7 I2C_PB6 I2C2_FMP I2C1_FMP FMP _FMP _FMP _FMP _FMP rw rw rw Res. 18 17 Res. Res. 2 1 16 Res. 0 FWDIS rw Bits 31:15 Reserved, must be kept at reset value Bit 14 I2C3 FMP: I2C3 Fm+ drive capability enable bit This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C3 pins PC0, PC1, PA8 and PB4 selected through the IOPORT control registers AF selection bits. Bit 13 I2C2 FMP: I2C2 Fm+ drive capability enable bit This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C2 pins PB13 and PB14 selected through the IOPORT control registers AF selection bits. Bit 12 I2C1 FMP: I2C1 Fm+ drive capability enable bit This bit is set and cleared by software. When it is set, Fm+ mode is enabled on I2C1 pins selected through the IOPORT control registers AF selection bits. This bit is bit is OR-ed with I2C_PBx_FMP bits. Bit 11 I2C PB9 FMP: Fm+ drive capability on PB9 enable bit This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB9. Bit 10 I2C PB8 FMP: Fm+ drive capability on PB8 enable bit This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB8. Bit 9 I2C PB7 FMP: Fm+ drive capability on PB7 enable bit This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB7. Bit 8 I2C PB6 FMP: Fm+ drive capability on PB6 enable bit This bit is set and cleared by software. When it is set, it forces Fm+ drive capability on PB6. Bits 7:1 Reserved, must be kept at reset value Bit 0 FWDIS: Firewall disable bit This bit is set by default (after reset). It is cleared by software to protect the access to the memory segments according to the Firewall configuration.Once cleared it cannot be set by software. Only a system reset set the bit. 0: Firewall access enabled 1: Firewall access disabled Note: This bit cannot be set by an APB reset. A system reset is required to set it. 233/874 DocID025942 Rev 5 RM0377 System configuration controller (SYSCFG) 9.2.3 Reference control and status register (SYSCFG_CFGR3) The SYSCFG_CFGR3 register is the reference control/status register. It contains all the bits/flags related to VREFINT and temperature sensor. Address offset: 0x20 System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 REF_ LOCK VREFINT _RDYF Res. Res. Res. Res. Res. Res. rs r 15 14 13 12 11 10 9 8 Res. ENBUF_VR EFINT_ COMP Res. Res. Res. Res. 23 22 21 20 19 18 17 Res. Res. Res. Res. Res. Res. Res. 7 6 5 4 3 2 rw rw rw Res. 1 ENBUF_ ENBUF_ SEL_VREF SENSOR VREFINT Res. Res. Res. Res. Res. _OUT _ADC _ ADC rw 16 0 Res. rw Bit 31 REF_LOCK: SYSCFG_CFGR3 lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the reference control/Status register, SYSCFG_CFGR3[31:0]. 0: SYSCFG_CFGR3[31:0] bits are read/write 1: SYSCFG_CFGR3[31:0] bits are read-only Bit 30 VREFINT_RDYF: VREFINT ready flag This bit is read-only. It shows the state of the internal voltage reference, VREFINT. When set, it indicates that VREFINT is available for BOR, PVD. 0: VREFINT OFF 1: VREFINT ready Bits 29:13 Reserved, must be kept at reset value Bit 12 ENBUF_VREFINT_COMP: VREFINT reference for comparator 2 enable bit This bit is set and cleared by software (only if REF_LOCK not set). 0: Buffer used to generate VREFINT reference for comparator 2 switched OFF. 1: Buffer used to generate VREFINT reference for comparator 2 switched ON. Bits 11:10 Reserved, must be kept at reset value Bit 9 ENBUF_SENSOR_ADC: Temperature sensor reference for ADC enable bit This bit is set and cleared by software (only if REF_LOCK not set). When this bit is set, the VREFINT is automatically enabled. 0: Buffer used to generate the temperature sensor reference for the ADC switched OFF. 1: Buffer used to generate the temperature sensor reference for the ADC switched ON. Bit 8 ENBUF_VREFINT_ADC: VREFINT reference for ADC enable bit This bit is set and cleared by software (only if REF_LOCK not set). 0: Buffer used to generate VREFINT reference for the ADC switched OFF. 1: Buffer used to generate VREFINT reference for the ADC switched ON. DocID025942 Rev 5 234/874 238 System configuration controller (SYSCFG) RM0377 Bits 7:6 Reserved, must be kept at reset value Bits 5:4 SEL_VREF_OUT: VREFINT_ADC connection bit These bits are set and cleared by software (only if REF_LOCK not set). These bits select which pad is connected to VREFINT_ADC when ENBUF_VREFINT_ADC is set. 00: no pad connected 01: PB0 connected 10: PB1 connected 11: PB0 and PB1 connected Bits 3:0 Reserved, must be kept at reset value 9.2.4 SYSCFG external interrupt configuration register 1 (SYSCFG_EXTICR1) Address offset: 0x08 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 5 4 3 2 1 0 rw rw rw Reserved 15 14 rw rw 13 12 11 10 rw rw rw EXTI3[3:0] rw 9 8 7 6 rw rw rw EXTI2[3:0] EXTI1[3:0] rw rw EXTI0[3:0] rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 0 to 3) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PH[x] (only PH[1:0] and PH[10:9]) Other configurations are reserved 235/874 DocID025942 Rev 5 RM0377 System configuration controller (SYSCFG) 9.2.5 SYSCFG external interrupt configuration register 2 (SYSCFG_EXTICR2) Address offset: 0x0C Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 6 5 4 3 18 17 16 2 1 0 Reserved 15 14 13 12 11 EXTI7[3:0] rw rw rw 10 9 8 7 EXTI6[3:0] rw rw rw EXTI5[3:0] rw rw rw rw rw EXTI4[3:0] rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 4 to 7) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin Other configurations are reserved 9.2.6 SYSCFG external interrupt configuration register 3 (SYSCFG_EXTICR3) Address offset: 0x10 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 6 5 4 3 18 17 16 2 1 0 Reserved 15 14 13 12 11 EXTI11[3:0] rw rw rw 10 9 8 7 EXTI10[3:0] rw rw rw rw EXTI9[3:0] rw rw rw rw EXTI8[3:0] rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 8 to 11) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin 0101: PH[x] (only PH[1:0] and PH[10:9]) Other configurations are reserved. DocID025942 Rev 5 236/874 238 System configuration controller (SYSCFG) 9.2.7 RM0377 SYSCFG external interrupt configuration register 4 (SYSCFG_EXTICR4) Address offset: 0x14 Reset value: 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 6 5 4 3 18 17 16 2 1 0 Reserved 15 14 13 12 11 10 EXTI15[3:0] rw rw rw 9 8 7 EXTI14[3:0] rw rw rw EXTI13[3:0] rw rw rw rw EXTI12[3:0] rw rw rw rw rw rw Bits 31:16 Reserved Bits 15:0 EXTIx[3:0]: EXTI x configuration (x = 12 to 15) These bits are written by software to select the source input for the EXTIx external interrupt. 0000: PA[x] pin 0001: PB[x] pin 0010: PC[x] pin 0011: PD[x] pin 0100: PE[x] pin Other configurations are reserved. 9.2.8 SYSCFG register map The following table gives the SYSCFG register map and the reset values. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFG_ EXTICR1 Res. 0x08 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value 237/874 0 0 0 0 0 0 0 EXTI2[3:0] 0 0 0 0 EXTI6[3:0] 0 0 0 0 Res. Res. UFB. Res. MEM_MODE x FWDISEN I2C_PB6_FMP 0 x Res. I2C_PB7_FMP 0 Res. Res. I2C_PB8_FMP 0 Res. I2C_PB9_FMP 0 x Res. I2C1_FMP 0 EXTI7[3:0] 0 DocID025942 Rev 5 0 EXTI3[3:0] 0 Res. 0x0C SYSCFG_ EXTICR2 Res. Reset value x I2C2_FMP Reset value x I2C3_FMP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFG_CFGR2 Res. 0x04 Res. Reset value BOOT_MODE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFG_CFGR1 Res. 0x00 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 45. SYSCFG register map and reset values 1 EXTI1[3:0] 0 0 0 0 EXTI5[3:0] 0 0 0 0 EXTI0[3:0] 0 0 0 0 EXTI4[3:0] 0 0 0 0 RM0377 System configuration controller (SYSCFG) 0 0 0 0 0 0 0 0 0 0 0 EXTI14[3:0] EXTI13[3:0] EXTI12[3:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. EXTI15[3:0] Res. 0 Res. 0 Res. 0 Res. 0 EXTI8[3:0] 0 0 0 0 SEL_VREF_OUT 0 Res. 0 Res. Res. ENBUF_VREFINT_COMP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Reset value Res. SYSCFG_CFGR3 REF_LOCK Refer to Section 14: Comparator (COMP) VREFINT_RDYF 0x20 0 EXTI9[3:0] Res. Reset value EXTI10[3:0] ENBUF_VREFINT_ADC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. COMP2_CTRL Res. 0x1C Res. COMP1_CTRL Res. 0x18 Res. 0x14 SYSCFG_ EXTICR4 Res. Reset value EXTI11[3:0] ENBUF_SENSOR_ADC Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SYSCFG_ EXTICR3 Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x10 Res. Register Res. Offset Res. Table 45. SYSCFG register map and reset values (continued) 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. DocID025942 Rev 5 238/874 238 Direct memory access controller (DMA) RM0377 10 Direct memory access controller (DMA) 10.1 Introduction Direct memory access (DMA) is used in order to provide high-speed data transfer between peripherals and memory as well as memory to memory. Data can be quickly moved by DMA without any CPU actions. This keeps CPU resources free for other operations. The DMA controller has up to 7 channels (except for category 1 devices which feature up to 5 channels), each dedicated to managing memory access requests from one or more peripherals. It has an arbiter for handling the priority between DMA requests. 10.2 239/874 DMA main features Up to 7 or 5 (category 1 devices) independently configurable channels (requests) Each channel is connected to dedicated hardware DMA requests, software trigger is also supported on each channel. This configuration is done by software. Priorities between requests from the DMA channels are software programmable (4 levels consisting of very high, high, medium, low) or hardware in case of equality (request 1 has priority over request 2, etc.) Independent source and destination transfer size (byte, half word, word), emulating packing and unpacking. Source/destination addresses must be aligned on the data size. Support for circular buffer management 3 event flags (DMA Half Transfer, DMA Transfer complete and DMA Transfer Error) logically ORed together in a single interrupt request for each channel Memory-to-memory transfer Peripheral-to-memory and memory-to-peripheral, and peripheral-to-peripheral transfers Access to Flash, SRAM, APB and AHB peripherals as source and destination Programmable number of data to be transferred: up to 65535 DocID025942 Rev 5 RM0377 Direct memory access controller (DMA) The block diagram is shown in the following figure. Figure 26. DMA block diagram )/,7) 6\VWHP )ODVK '0$ &K &K '0$ %XVPDWUL[ &RUWH[ 0 65$0 5HVHW &ORFNFRQWURO &5& 5&& XSWR &K %ULGJH $3% $UELWHU $+%6ODYH '0$UHTXHVW $'& 63,63, 86$57 /38$57 ,& 7,0 06Y9 10.3 DMA functional description The DMA controller performs direct memory transfer by sharing the system bus with the Cortex®-M0+ core. The DMA request may stop the CPU access to the system bus for some bus cycles, when the CPU and DMA are targeting the same destination (memory or peripheral). The bus matrix implements round-robin scheduling, thus ensuring at least half of the system bus bandwidth (both to memory and peripheral) for the CPU. 10.3.1 DMA transactions After an event, the peripheral sends a request signal to the DMA Controller. The DMA controller serves the request depending on the channel priorities. As soon as the DMA Controller accesses the peripheral, an Acknowledge is sent to the peripheral by the DMA Controller. The peripheral releases its request as soon as it gets the Acknowledge from the DMA Controller. Once the request is de-asserted by the peripheral, the DMA Controller release the Acknowledge. If there are more requests, the peripheral can initiate the next transaction. In summary, each DMA transfer consists of three operations: The loading of data from the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used DocID025942 Rev 5 240/874 256 Direct memory access controller (DMA) RM0377 for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register 10.3.2 The storage of the data loaded to the peripheral data register or a location in memory addressed through an internal current peripheral/memory address register. The start address used for the first transfer is the base peripheral/memory address programmed in the DMA_CPARx or DMA_CMARx register The post-decrementing of the DMA_CNDTRx register, which contains the number of transactions that have still to be performed. Arbiter The arbiter manages the channel requests based on their priority and launches the peripheral/memory access sequences. The priorities are managed in two stages: 10.3.3 Software: each channel priority can be configured in the DMA_CCRx register. There are four levels: – Very high priority – High priority – Medium priority – Low priority Hardware: if 2 requests have the same software priority level, the channel with the lowest number will get priority versus the channel with the highest number. For example, channel 2 gets priority over channel 4. DMA channels Each channel can handle DMA transfer between a peripheral register located at a fixed address and a memory address. The amount of data to be transferred (up to 65535) is programmable. The register which contains the amount of data items to be transferred is decremented after each transaction. Programmable data sizes Transfer data sizes of the peripheral and memory are fully programmable through the PSIZE and MSIZE bits in the DMA_CCRx register. Pointer incrementation Peripheral and memory pointers can optionally be automatically post-incremented after each transaction depending on the PINC and MINC bits in the DMA_CCRx register. If incremented mode is enabled, the address of the next transfer will be the address of the previous one incremented by 1, 2 or 4 depending on the chosen data size. The first transfer address is the one programmed in the DMA_CPARx/DMA_CMARx registers. During transfer operations, these registers keep the initially programmed value. The current transfer addresses (in the current internal peripheral/memory address register) are not accessible by software. If the channel is configured in non-circular mode, no DMA request is served after the last transfer (that is once the number of data items to be transferred has reached zero). In order to reload a new number of data items to be transferred into the DMA_CNDTRx register, the DMA channel must be disabled. 241/874 DocID025942 Rev 5 RM0377 Note: Direct memory access controller (DMA) If a DMA channel is disabled, the DMA registers are not reset. The DMA channel registers (DMA_CCRx, DMA_CPARx and DMA_CMARx) retain the initial values programmed during the channel configuration phase. In circular mode, after the last transfer, the DMA_CNDTRx register is automatically reloaded with the initially programmed value. The current internal address registers are reloaded with the base address values from the DMA_CPARx/DMA_CMARx registers. Channel configuration procedure The following sequence should be followed to configure a DMA channel x (where x is the channel number). 1. Set the peripheral register address in the DMA_CPARx register. The data will be moved from/ to this address to/ from the memory after the peripheral event. 2. Set the memory address in the DMA_CMARx register. The data will be written to or read from this memory after the peripheral event. 3. Configure the total number of data to be transferred in the DMA_CNDTRx register. After each peripheral event, this value will be decremented. 4. Configure the channel priority using the PL[1:0] bits in the DMA_CCRx register 5. Configure data transfer direction, circular mode, peripheral & memory incremented mode, peripheral & memory data size, and interrupt after half and/or full transfer in the DMA_CCRx register 6. Activate the channel by setting the ENABLE bit in the DMA_CCRx register. For code example, refer to A.6.1: DMA Channel Configuration sequence code example. As soon as the channel is enabled, it can serve any DMA request from the peripheral connected on the channel. Once half of the bytes are transferred, the half-transfer flag (HTIF) is set and an interrupt is generated if the Half-Transfer Interrupt Enable bit (HTIE) is set. At the end of the transfer, the Transfer Complete Flag (TCIF) is set and an interrupt is generated if the Transfer Complete Interrupt Enable bit (TCIE) is set. Circular mode Circular mode is available to handle circular buffers and continuous data flows (e.g. ADC scan mode). This feature can be enabled using the CIRC bit in the DMA_CCRx register. When circular mode is activated, the number of data to be transferred is automatically reloaded with the initial value programmed during the channel configuration phase, and the DMA requests continue to be served. Memory-to-memory mode The DMA channels can also work without being triggered by a request from a peripheral. This mode is called Memory to Memory mode. If the MEM2MEM bit in the DMA_CCRx register is set, then the channel initiates transfers as soon as it is enabled by software by setting the Enable bit (EN) in the DMA_CCRx register. The transfer stops once the DMA_CNDTRx register reaches zero. Memory to Memory mode may not be used at the same time as Circular mode. DocID025942 Rev 5 242/874 256 Direct memory access controller (DMA) 10.3.4 RM0377 Programmable data width, data alignment and endians When PSIZE and MSIZE are not equal, the DMA performs some data alignments as described in Table 46: Programmable data width & endian behavior (when bits PINC = MINC = 1). Table 46. Programmable data width & endian behavior (when bits PINC = MINC = 1) Number Source of data Destination port items to port width width transfer (NDT) Source content: address / data Transfer operations Destination content: address / data 8 8 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B1[7:0] @0x1 then WRITE B1[7:0] @0x1 3: READ B2[7:0] @0x2 then WRITE B2[7:0] @0x2 4: READ B3[7:0] @0x3 then WRITE B3[7:0] @0x3 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 8 16 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 00B0[15:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 00B1[15:0] @0x2 3: READ B3[7:0] @0x2 then WRITE 00B2[15:0] @0x4 4: READ B4[7:0] @0x3 then WRITE 00B3[15:0] @0x6 @0x0 / 00B0 @0x2 / 00B1 @0x4 / 00B2 @0x6 / 00B3 8 32 4 @0x0 / B0 @0x1 / B1 @0x2 / B2 @0x3 / B3 1: READ B0[7:0] @0x0 then WRITE 000000B0[31:0] @0x0 2: READ B1[7:0] @0x1 then WRITE 000000B1[31:0] @0x4 3: READ B3[7:0] @0x2 then WRITE 000000B2[31:0] @0x8 4: READ B4[7:0] @0x3 then WRITE 000000B3[31:0] @0xC @0x0 / 000000B0 @0x4 / 000000B1 @0x8 / 000000B2 @0xC / 000000B3 16 8 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B2[7:0] @0x1 3: READ B5B4[15:0] @0x4 then WRITE B4[7:0] @0x2 4: READ B7B6[15:0] @0x6 then WRITE B6[7:0] @0x3 @0x0 / B0 @0x1 / B2 @0x2 / B4 @0x3 / B6 16 16 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE B3B2[15:0] @0x2 3: READ B5B4[15:0] @0x4 then WRITE B5B4[15:0] @0x4 4: READ B7B6[15:0] @0x6 then WRITE B7B6[15:0] @0x6 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 16 32 4 @0x0 / B1B0 @0x2 / B3B2 @0x4 / B5B4 @0x6 / B7B6 1: READ B1B0[15:0] @0x0 then WRITE 0000B1B0[31:0] @0x0 2: READ B3B2[15:0] @0x2 then WRITE 0000B3B2[31:0] @0x4 3: READ B5B4[15:0] @0x4 then WRITE 0000B5B4[31:0] @0x8 4: READ B7B6[15:0] @0x6 then WRITE 0000B7B6[31:0] @0xC @0x0 / 0000B1B0 @0x4 / 0000B3B2 @0x8 / 0000B5B4 @0xC / 0000B7B6 32 8 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B0[7:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B4[7:0] @0x1 3: READ BBBAB9B8[31:0] @0x8 then WRITE B8[7:0] @0x2 4: READ BFBEBDBC[31:0] @0xC then WRITE BC[7:0] @0x3 @0x0 / B0 @0x1 / B4 @0x2 / B8 @0x3 / BC 32 16 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC 1: READ B3B2B1B0[31:0] @0x0 then WRITE B1B0[15:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B5B4[15:0] @0x2 3: READ BBBAB9B8[31:0] @0x8 then WRITE B9B8[15:0] @0x4 4: READ BFBEBDBC[31:0] @0xC then WRITE BDBC[15:0] @0x6 @0x0 / B1B0 @0x2 / B5B4 @0x4 / B9B8 @0x6 / BDBC 32 32 4 @0x0 / B3B2B1B0 @0x4 / B7B6B5B4 @0x8 / BBBAB9B8 @0xC / BFBEBDBC @0x0 / B3B2B1B0 1: READ B3B2B1B0[31:0] @0x0 then WRITE B3B2B1B0[31:0] @0x0 2: READ B7B6B5B4[31:0] @0x4 then WRITE B7B6B5B4[31:0] @0x4 @0x4 / B7B6B5B4 3: READ BBBAB9B8[31:0] @0x8 then WRITE BBBAB9B8[31:0] @0x8 @0x8 / BBBAB9B8 4: READ BFBEBDBC[31:0] @0xC then WRITE BFBEBDBC[31:0] @0xC @0xC / BFBEBDBC 243/874 DocID025942 Rev 5 RM0377 Direct memory access controller (DMA) Addressing an AHB peripheral that does not support byte or halfword write operations When the DMA initiates an AHB byte or halfword write operation, the data are duplicated on the unused lanes of the HWDATA[31:0] bus. So when the used AHB slave peripheral does not support byte or halfword write operations (when HSIZE is not used by the peripheral) and does not generate any error, the DMA writes the 32 HWDATA bits as shown in the two examples below: To write the halfword “0xABCD”, the DMA sets the HWDATA bus to “0xABCDABCD” with HSIZE = HalfWord To write the byte “0xAB”, the DMA sets the HWDATA bus to “0xABABABAB” with HSIZE = Byte Assuming that the AHB/APB bridge is an AHB 32-bit slave peripheral that does not take the HSIZE data into account, it will transform any AHB byte or halfword operation into a 32-bit APB operation in the following manner: an AHB byte write operation of the data “0xB0” to 0x0 (or to 0x1, 0x2 or 0x3) will be converted to an APB word write operation of the data “0xB0B0B0B0” to 0x0 an AHB halfword write operation of the data “0xB1B0” to 0x0 (or to 0x2) will be converted to an APB word write operation of the data “0xB1B0B1B0” to 0x0 For instance, if the user wants to write the APB backup registers (16-bit registers aligned to a 32-bit address boundary), he must configure the memory source size (MSIZE) to “16-bit” and the peripheral destination size (PSIZE) to “32-bit”. 10.3.5 Error management A DMA transfer error can be generated by reading from or writing to a reserved address space. When a DMA transfer error occurs during a DMA read or a write access, the faulty channel is automatically disabled through a hardware clear of its EN bit in the corresponding Channel configuration register (DMA_CCRx). The channel's transfer error interrupt flag (TEIF) in the DMA_IFR register is set and an interrupt is generated if the transfer error interrupt enable bit (TEIE) in the DMA_CCRx register is set. 10.3.6 DMA interrupts An interrupt can be produced on a Half-transfer, Transfer complete or Transfer error for each DMA channel. Separate interrupt enable bits are available for flexibility. Table 47. DMA interrupt requests Interrupt event Event flag Enable control bit Half-transfer HTIF HTIE Transfer complete TCIF TCIE Transfer error TEIF TEIE DocID025942 Rev 5 244/874 256 Direct memory access controller (DMA) 10.3.7 RM0377 DMA request mapping DMA controller The hardware requests from the peripherals (TIM2/6, ADC, SPI1/2, I2C1/2, AES (available only on Cat. 1, 2 and 5 with AES), USART1/2 and LPUART1) are mapped to the DMA channels (1 to 7) through the DMA channel selection register (s). On one channel, only one request must be enabled at a time. Refer to Figure 27: DMA request mapping. The peripheral DMA requests can be independently activated/de-activated by programming the DMA control bit in the registers of the corresponding peripheral. Figure 27. DMA request mapping '0$ 3HULSKHUDOUHTXHVWVLJQDOV )L[HGKDUGZDUHSULRULW\ &KDQQHO'0$B5(4 $'&7,0B&+$(6B,1 +LJKSULRULW\ 6:WULJJHU 0(00(0ELW $'&63,B5;86$57B7; /38$57B7;,&B7;,&B7; 7,0B837,0B83 $(6B2877,0B&+ 86$57B5;86$57B5; 86$57B7; 6:WULJJHU 0(00(0ELW &6 &KDQQHO'0$B5(4 &6 63,B7;86$57B5;,&B5; /38$57B5;,&B5; 7,0B&+7,0B&+7,0B83 86$57B7;86$57B7; 86$57B5;$(6B287 6:WULJJHU 0(00(0ELW &KDQQHO'0$B5(4 &6 63,B5;86$57B7; 86$57B7;,&B7;,&B7; $'& 63,B5;/38$57B7; ,&B7;7,0B&+7,0B83 6:WULJJHU 0(00(0ELW &KDQQHO'0$B5(4 &6 63,B7;86$57B5; 86$57B5;,&B5; 7,0B&+7,0B&+,&B5; 63,B7;/38$57B5; ,&B5;$(6B,1 6:WULJJHU 0(00(0ELW 63,B5;86$57B5; /38$57B5;,&B7; 7,0B75,*86$57B5; 86$57B5; 6:WULJJHU 0(00(0ELW '0$B&6(/5 &KDQQHO'0$B5(4 &6 &KDQQHO'0$B5(4 &6 63,B7;86$57B7; 86$57B7;86$57B7; /38$57B7;,&B5; 7,0B&+7,0B&+ 6:WULJJHU 0(00(0ELW ,QWHUQDO'0$ UHTXHVW &KDQQHO'0$B5(4 /RZSULRULW\ &6 06Y9 1. Available only on category 1 devices. Table 48 lists the DMA requests for each channel. 245/874 DocID025942 Rev 5 RM0377 Direct memory access controller (DMA) Table 48. Summary of the DMA requests for each channel Request Channel Peripherals number 1 0 ADC ADC Channel 2 Channel 3 Channel 4 ADC - ADC(2) (2) Channel 7(1) - - - - SPI2_TX SPI2_RX SPI2_TX USART1_ RX - - USART2_ RX USART2_ RX USART2_ TX (2) SPI1_TX 1 SPI1 - SPI1_RX SPI1_TX 2 SPI2 - - - 3 USART1 - 4 USART2 - USART2_ TX(2) USART2_ RX(2) USART2_T X 5 LPUART1 - LPUART1_ TX LPUART1_ RX LPUART1_ LPUART1_ LPUART1_ LPUART1_ RX(2) RX TX TX(2) 6 I2C1 - I2C1_TX I2C1_RX 7 I2C2 - - - I2C2_TX I2C2_RX 8 TIM2 TIM2_ CH3 TIM2_UP TIM2_CH2 TIM2_CH4 TIM2_CH1 - TIM6 - - - - - - TIM3_CH1 TIM3_ TRIG - 9 TIM6_UP SPI1_RX Channel 6(1) Channel 5 SPI2_RX USART1_T USART1_T USART1_RX X X I2C1_TX(2) I2C1_RX(2) I2C1_TX I2C1_RX - TIM2_CH2 TIM2_CH4 10 TIM3 - TIM3_CH3 TIM3_CH4 TIM3_UP 11 AES(3) AES_IN AES_OUT AES_OUT 12 USART4 - USART4_ RX USART4_TX - - USART4_ RX USART4_ TX 13 USART5 - USART5_ RX USART5_TX - - USART5_ RX USART5_ TX 14 I2C3 - I2C3_TX I2C3_RX I2C3_TX I2C3_RX - - 15 TIM7_UO - - - TIM7 - - - AES_IN 1. Not available on category 1 devices. 2. Available only on category 1 devices. 3. Available only on category 1,2 and 5 with AES. DocID025942 Rev 5 246/874 256 Direct memory access controller (DMA) 10.4 RM0377 DMA registers Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by bytes (8-bit), half-words (16-bit) or words (32bit). 10.4.1 DMA interrupt status register (DMA_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. TEIF7 HTIF7 TCIF7 GIF7 TEIF6 HTIF6 TCIF6 GIF6 TEIF5 HTIF5 TCIF5 GIF5 r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TEIF4 HTIF4 TCIF4 GIF4 TEIF3 HTIF3 TCIF3 GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 r r r r r r r r r r r r r r r r Bits 31:28 Reserved, must be kept at reset value. Bits 27, 23, 19, 15, TEIFx: Channel x transfer error flag (x = 1..7) 11, 7, 3 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer error (TE) on channel x 1: A transfer error (TE) occurred on channel x Bits 26, 22, 18, 14, HTIFx: Channel x half transfer flag (x = 1..7) 10, 6, 2 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No half transfer (HT) event on channel x 1: A half transfer (HT) event occurred on channel x Bits 25, 21, 17, 13, TCIFx: Channel x transfer complete flag (x = 1..7) 9, 5, 1 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No transfer complete (TC) event on channel x 1: A transfer complete (TC) event occurred on channel x Bits 24, 20, 16, 12, GIFx: Channel x global interrupt flag (x = 1..7) 8, 4, 0 This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the DMA_IFCR register. 0: No TE, HT or TC event on channel x 1: A TE, HT or TC event occurred on channel x 247/874 DocID025942 Rev 5 RM0377 Direct memory access controller (DMA) 10.4.2 DMA interrupt flag clear register (DMA_IFCR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 CHTIF CTCIF7 7 23 22 21 20 19 18 17 16 Res. Res. Res. Res. CTEIF 7 w w w w w w w w w w w w 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTEIF 4 CHTIF 4 CTCIF 4 CGIF4 CTEIF 3 w w w w w CHTIF CTCIF3 3 w w CGIF7 CGIF3 w CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF2 CHTIF2 CTCIF2 CGIF2 w w w w CTEIF5 CHTIF5 CTCIF5 CTEIF1 CHTIF1 CTCIF1 w w w CGIF5 CGIF1 w Bits 31:28 Reserved, must be kept at reset value. Bits 27, 23, 19, 15, CTEIFx: Channel x transfer error clear (x = 1..7) 11, 7, 3 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TEIF flag in the DMA_ISR register Bits 26, 22, 18, 14, CHTIFx: Channel x half transfer clear (x = 1..7) 10, 6, 2 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding HTIF flag in the DMA_ISR register Bits 25, 21, 17, 13, CTCIFx: Channel x transfer complete clear (x = 1..7) 9, 5, 1 This bit is set and cleared by software. 0: No effect 1: Clears the corresponding TCIF flag in the DMA_ISR register Bits 24, 20, 16, 12, CGIFx: Channel x global interrupt clear (x = 1..7) 8, 4, 0 This bit is set and cleared by software. 0: No effect 1: Clears the GIF, TEIF, HTIF and TCIF flags in the DMA_ISR register DocID025942 Rev 5 248/874 256 Direct memory access controller (DMA) 10.4.3 RM0377 DMA channel x configuration register (DMA_CCRx) (x = 1..7 , where x = channel number) Address offset: 0x08 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. MEM2 MEM MINC PINC CIRC DIR TEIE HTIE TCIE EN rw rw rw rw rw rw rw rw rw PL[1:0] rw rw MSIZE[1:0] PSIZE[1:0] rw rw rw rw Bits 31:15 Reserved, must be kept at reset value. Bit 14 MEM2MEM: Memory to memory mode This bit is set and cleared by software. 0: Memory to memory mode disabled 1: Memory to memory mode enabled Bits 13:12 PL[1:0]: Channel priority level These bits are set and cleared by software. 00: Low 01: Medium 10: High 11: Very high Bits 11:10 MSIZE[1:0]: Memory size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bits 9:8 PSIZE[1:0]: Peripheral size These bits are set and cleared by software. 00: 8-bits 01: 16-bits 10: 32-bits 11: Reserved Bit 7 MINC: Memory increment mode This bit is set and cleared by software. 0: Memory increment mode disabled 1: Memory increment mode enabled Bit 6 PINC: Peripheral increment mode This bit is set and cleared by software. 0: Peripheral increment mode disabled 1: Peripheral increment mode enabled 249/874 DocID025942 Rev 5 RM0377 Direct memory access controller (DMA) Bit 5 CIRC: Circular mode This bit is set and cleared by software. 0: Circular mode disabled 1: Circular mode enabled Bit 4 DIR: Data transfer direction This bit is set and cleared by software. 0: Read from peripheral 1: Read from memory Bit 3 TEIE: Transfer error interrupt enable This bit is set and cleared by software. 0: TE interrupt disabled 1: TE interrupt enabled Bit 2 HTIE: Half transfer interrupt enable This bit is set and cleared by software. 0: HT interrupt disabled 1: HT interrupt enabled Bit 1 TCIE: Transfer complete interrupt enable This bit is set and cleared by software. 0: TC interrupt disabled 1: TC interrupt enabled Bit 0 EN: Channel enable This bit is set and cleared by software. 0: Channel disabled 1: Channel enabled DocID025942 Rev 5 250/874 256 Direct memory access controller (DMA) 10.4.4 RM0377 DMA channel x number of data register (DMA_CNDTRx) (x = 1..7, where x = channel number) Address offset: 0x0C + 0d20 × (channel number – 1) Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw NDT[15:0] rw rw rw rw rw rw rw rw rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 NDT[15:0]: Number of data to transfer Number of data to be transferred (0 up to 65535). This register can only be written when the channel is disabled. Once the channel is enabled, this register is read-only, indicating the remaining bytes to be transmitted. This register decrements after each DMA transfer. Once the transfer is completed, this register can either stay at zero or be reloaded automatically by the value previously programmed if the channel is configured in auto-reload mode. If this register is zero, no transaction can be served whether the channel is enabled or not. 10.4.5 DMA channel x peripheral address register (DMA_CPARx) (x = 1..7, where x = channel number) Address offset: 0x10 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 PA [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw PA [15:0] rw Bits 31:0 PA[31:0]: Peripheral address Base address of the peripheral data register from/to which the data will be read/written. When PSIZE is 01 (16-bit), the PA[0] bit is ignored. Access is automatically aligned to a halfword address. When PSIZE is 10 (32-bit), PA[1:0] are ignored. Access is automatically aligned to a word address. 251/874 DocID025942 Rev 5 RM0377 Direct memory access controller (DMA) 10.4.6 DMA channel x memory address register (DMA_CMARx) (x = 1..7, where x = channel number) Address offset: 0x14 + 0d20 × (channel number – 1) Reset value: 0x0000 0000 This register must not be written when the channel is enabled. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 MA [31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw MA [15:0] rw Bits 31:0 MA[31:0]: Memory address Base address of the memory area from/to which the data will be read/written. When MSIZE is 01 (16-bit), the MA[0] bit is ignored. Access is automatically aligned to a halfword address. When MSIZE is 10 (32-bit), MA[1:0] are ignored. Access is automatically aligned to a word address. DocID025942 Rev 5 252/874 256 Direct memory access controller (DMA) 10.4.7 RM0377 DMA channel selection register (DMA_CSELR) Address offset: 0xA8 Reset value: 0x0000 0000 This register is used to manage the remapping of DMA channels (see Figure 27). 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 27 rw rw 25 24 23 22 C7S [3:0] 19 18 17 16 C5S [3:0] rw rw rw rw rw rw rw rw rw rw rw 10 9 8 7 6 5 4 3 2 1 0 rw rw C2S [3:0] rw rw rw rw rw Bits 31:28 Reserved, must be kept at reset value. Bits 27:24 C7S[3:0]: DMA channel 7 selection 0010: DMA channel 7 remapped to SPI2_TX 0100: DMA channel 7 remapped to USART2_TX 0101: DMA channel 7 remapped to LPUART1_TX 0110: DMA channel 7 remapped to I2C1_RX 1000: DMA channel 7 remapped to TIM2_CH2/TIM2_CH4 1100: DMA channel 7 remapped to USART4_TX 1101: DMA channel 7 remapped to USART5_TX Other configurations: DMA channel 7 not remapped Bits 23:20 C6S[3:0]: DMA channel 6 selection 0010: DMA channel 6 remapped to SPI2_RX 0100: DMA channel 6 remapped to USART2_RX 0101: DMA channel 6 remapped to LPUART1_RX 0110: DMA channel 6 remapped to I2C1_TX 1010: DMA channel 6 remapped to TIM3_TRIG 1100: DMA channel 6 remapped to USART4_RX 1101: DMA channel 6remapped to USART5_RX Other configurations: DMA channel 6 not remapped Bits 19:16 C5S[3:0]: DMA channel 5 selection 0010: DMA channel 5 remapped to SPI2_TX 0011: DMA channel 5 remapped to USART1_RX 0100: DMA channel 5 remapped to USART2_RX 0111: DMA channel 5 remapped to I2C2_RX 1000: DMA channel 5 remapped to TIM2_CH1 1010: DMA channel 5 remapped to TIM3_CH1 1011: DMA channel 5 remapped to AES_IN 1110: DMA channel 5 remapped to I2C3_RX Other configurations: DMA channel 5 not remapped 253/874 20 11 C3S [3:0] rw 21 C6S [3:0] rw C4S [3:0] rw 26 DocID025942 Rev 5 C1S [3:0] rw rw rw rw rw RM0377 Direct memory access controller (DMA) Bits 15:12 C4S[3:0]: DMA channel 4 selection 0010: DMA channel 4 remapped to SPI2_RX 0011: DMA channel 4 remapped to USART1_TX 0100: DMA channel 4 remapped to USART2_TX 0111: DMA channel 4 remapped to I2C2_TX 1000: DMA channel 4 remapped to TIM2_CH4 1110: DMA channel 4 remapped to I2C3_TX 1111: DMA channel 4 remapped to TIM7_UP Other configurations: DMA channel 4 not remapped Bits 11:8 C3S[3:0]: DMA channel 3 selection 0001: DMA channel 3 remapped to SPI1_TX 0011: DMA channel 3 remapped to USART1_RX 0101: DMA channel 3 remapped to LPUART1_RX 0110: DMA channel 3 remapped to I2C1_RX 1000: DMA channel 3 remapped to TIM2_CH2 1010: DMA channel 3 remapped to TIM4_CH4/TIM4_UP 1011: DMA channel 3 remapped to AES_OUT 1100: DMA channel 3 remapped to USART4_TX 1101: DMA channel 3 remapped to USART4_TX 1110: DMA channel 3 remapped to I2C3_RX Other configurations: DMA channel 3 not remapped Bits 7:4 C2S[3:0]: DMA channel 2 selection 0000: DMA channel 2 remapped to ADC 0001: DMA channel 2 remapped to SPI1_RX 0011: DMA channel 2 remapped to USART1_TX 0101: DMA channel 2 remapped to LPUART1_TX 0110: DMA channel 2 remapped to I2C1_TX 1000: DMA channel 2 remapped to TIM2_UP 1001: DMA channel 2 remapped to TIM6_UP 1010: DMA channel 2 remapped to TIM3_CH3 1011: DMA channel 2 remapped to AES_OUT 1100: DMA channel 2 remapped to USART4_RX 1101: DMA channel 2 remapped to USART5_RX 1110: DMA channel 2 remapped to I2C3_TX Other configurations: DMA channel 2 not remapped Bits 3:0 C1S[3:0]: DMA channel 1 selection 0000: DMA channel 1 remapped to ADC 1000: DMA channel 1 remapped to TIM2_CH3 1011: DMA channel 1 remapped to AES_IN Other configurations: DMA channel 1 not remapped DocID025942 Rev 5 254/874 256 0x48 255/874 DMA_CNDTR4 0 0 0 DMA_CPAR3 DMA_CMAR3 0 0 Reset value 0 Reset value 0 0 Reset value DocID025942 Rev 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 PL [1:0] 0 0 PA[31:0] MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PL [1:0] 0 NDT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 EN TCIE 0 TCIE 0 HTIE 0 TEIE HTIE 0 TEIE NDT[15:0] DIR 0 0 EN MA[31:0] 0 TCIE PA[31:0] 0 HTIE 0 0 PL [1:0] DIR GIF3 TEIF2 HTIF2 TCIF2 GIF2 TEIF1 HTIF1 TCIF1 GIF1 0 0 0 0 0 0 0 0 0 0 CHTIF7 CTCIF7 CGIF7 CTEIF6 CHTIF6 CTCIF6 CGIF6 CTEIF5 CHTIF5 CTCIF5 0 0 0 0 0 0 0 0 0 0 0 CHTIF3 CTCIF3 CGIF3 CTEIF2 CHTIF2 CTCIF2 CGIF2 CTEIF1 CHTIF1 CTCIF1 CGIF1 0 0 0 0 0 0 0 0 MINC PSIZE [1:0] MSIZE [1:0] CTEIF3 0 0 PINC CIRC DIR TEIE HTIE TCIE EN 0 PINC TCIF3 0 0 CIRC HTIF3 0 0 0 TEIE 0 0 DIR 0 0 0 PINC 0 CIRC GIF4 TEIF3 0 0 PINC MA[31:0] 0 MINC TCIF4 0 0 MINC HTIF4 0 0 CIRC Reset value MINC Reset value PL [1:0] PSIZE [1:0] GIF5 TEIF4 0 0 PSIZE [1:0] TCIF5 0 0 MSIZE [1:0] HTIF5 0 CGIF4 GIF6 TEIF5 0 CTCIF4 TCIF6 0 CHTIF4 HTIF6 0 MEM2MEM GIF7 TEIF6 0 CTEIF4 TCIF7 0 Res. HTIF7 0 0 MSIZE [1:0] 0 MEM2MEM Reset value MEM2MEM PA[31:0] Res. 0 Res. TEIF7 Res. Res. Res. Res. 0 CTEIF7 Res. Res. Res. Res. 0 CGIF5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 PSIZE [1:0] 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 0 MSIZE [1:0] 0 0 MEM2MEM DMA_CMAR2 Res. Reset value Res. DMA_CPAR2 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CMAR1 Res. 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CPAR1 Res. 0 0 0 Res. 0 0 Res. 0 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 0 Res. 0 0 0 0 Res. 0 0 0 Res. 0 0 0 0 Res. 0 0 0 0 Res. 0 0 0 Res. 0 0 0 Res. 0 0 0 0 0 Res. DMA_CCR4 0 0 0 0 0 Res. 0x44 Reset value 0 0 0 0 Res. 0x3C Reset value Res. Reset value Res. 0x38 DMA_CNDTR3 Res. Reset value Res. 0x34 DMA_CCR3 0 0 0 Res. 0x30 Reset value 0 Res. 0x28 Reset value 0 0 Res. 0x24 DMA_CNDTR2 0 0 Res. 0x20 DMA_CCR2 0 Res. 0x1C Reset value Res. 0x14 Reset value Res. 0x10 DMA_CNDTR1 Res. 0x0C DMA_CCR1 Res. 0x08 DMA_IFCR Res. 0x04 DMA_ISR Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. 10.4.8 Res. Direct memory access controller (DMA) RM0377 DMA register map The following table gives the DMA register map and the reset values. Table 49. DMA register map and reset values 0 0 0 0 0 0 0 NDT[15:0] 0 0 0 0 0 0 0 NDT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0377 Direct memory access controller (DMA) 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR4 Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0x08C PINC CIRC DIR TEIE HTIE TCIE EN 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] 0 PINC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 MEM2MEM MINC 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR6 Reset value 0 Res. Reset value 0 NDT[15:0] 0 DMA_CPAR6 PL [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR6 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value CIRC DIR TEIE HTIE TCIE EN PSIZE [1:0] 0 PINC 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DMA_CMAR7 Reset value 0 NDT[15:0] 0 DMA_CPAR7 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR7 0 PL [1:0] MSIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR7 Res. Reserved 0 0 MA[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value Res. Res. DMA_CSELR Res. Reserved Res. 0x090 0x0A8 PSIZE [1:0] 0 0 Reset value 0x088 0 0 Reset value 0x084 0 0 MSIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR6 0x07C 0x080 0 Reserved Res. 0x078 0 MA[31:0] Reset value 0x074 0 0 Reset value 0x070 0 MINC 0 0x068 0x06C 0 MEM2MEM 0 DMA_CMAR5 Reset value 0 NDT[15:0] 0 Res. 0x64 Reset value 0 PA[31:0] Res. 0x60 0 Res. Reset value DMA_CPAR5 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CNDTR5 Res. 0x5C 0 Res. Reset value PL [1:0] MSIZE [1:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DMA_CCR5 Res. Reserved Res. 0x54 0x58 0 MINC 0 Res. PA[31:0] 0 MEM2MEM Reset value Res. 0x50 DMA_CPAR4 Res. 0x4C Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 49. DMA register map and reset values (continued) C7S[3:0] 0 0 0 C6S[3:0] 0 0 0 0 C5S[3:0] 0 0 0 0 C4S[3:0] 0 0 C3S[3:0] 0 0 C2S[3:0] 0 0 C1S[3:0] 0 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. DocID025942 Rev 5 256/874 256 Nested vectored interrupt controller (NVIC) RM0377 11 Nested vectored interrupt controller (NVIC) 11.1 Main features Up to 39 maskable interrupt channels (see Table 50), These do not include the 16 interrupt lines of Cortex®-M0+. 4 programmable priority levels (2 bits of interrupt priority are used) Low-latency exception and interrupt handling Power management control Implementation of system control registers The NVIC and the processor core interface are closely coupled, which enables low-latency interrupt processing and efficient processing of late arriving interrupts. All interrupts including the core exceptions are managed by the NVIC. For more information on exceptions and NVIC programming, refer to the STM32L0 Series Cortex®-M0+ programming manual (PM0223). For code example, refer to A.7.1: NVIC initialization example. 11.2 SysTick calibration value register The SysTick calibration value is fixed to 4000, which gives a reference time base of 1 ms with the SysTick clock set to 4 MHz (max HCLK/8). 11.3 Interrupt and exception vectors Table 50 is the vector table for STM32L0x1 devices. Table 50. List of vectors(1)(2) Position 257/874 Priority Type of priority - - -3 Acronym Description Address - Reserved 0x0000_0000 fixed Reset Reset 0x0000_0004 -2 fixed NMI_Handler Non maskable interrupt. The RCC Clock Security System (CSS) is linked to the NMI vector. 0x0000_0008 -1 fixed HardFault_Handler All class of fault 0x0000_000C - - - Reserved 0x0000_0010 0x0000_002B 3 settable SVC_Handler System service call via SWI instruction 0x0000_002C - - - Reserved 0x0000_0030 0x0000_0037 5 settable PendSV_Handler Pendable request for system service 0x0000_0038 6 settable SysTick_Handler System tick timer 0x0000_003C DocID025942 Rev 5 RM0377 Nested vectored interrupt controller (NVIC) Table 50. List of vectors(1)(2) (continued) Position Priority Type of priority 0 7 settable WWDG Window Watchdog interrupt 0x0000_0040 1 8 settable PVD PVD through EXTI Line detection interrupt 0x0000_0044 2 9 settable RTC RTC global interrupt through EXTI17/19/20 line and LSE CSS interrupt through EXTI 19 line 0x0000_0048 3 10 settable FLASH Flash memory and data EEPROM global interrupt 0x0000_004C 4 11 settable RCC_CRS RCC global interrupt 0x0000_0050 5 12 settable EXTI[1:0] EXTI Line0 and 1 interrupts 0x0000_0054 6 13 settable EXTI[3:2] EXTI Line2 and 3 interrupts 0x0000_0058 7 14 settable EXTI[15:4] EXTI Line4 to 15 interrupts 0x0000_005C 8 15 settable - Reserved 0x0000_0060 9 16 settable DMA1_Channel1 DMA1 Channel1 global interrupt 0x0000_0064 10 17 settable DMA1_Channel[3:2] DMA1 Channel2 and 3 interrupts 0x0000_0068 11 18 settable DMA1_Channel[7:4] DMA1 Channel4 to 7 interrupts 0x0000_006C 12 19 settable ADC_COMP ADC and comparator interrupts through EXTI21 and 22 0x0000_0070 13 20 settable LPTIM1 LPTIMER1 interrupt through EXTI29 0x0000_0074 14 21 settable USART4/USART5 USART4/USART5 global interrupt 0x0000_0078 15 22 settable TIM2 TIMER2 global interrupt 0x0000_007C 16 23 settable TIM3 TIMER3 global interrupt 0x0000_0080 17 24 settable TIM6 TIMER6 global interrupt 0x0000_0084 18 25 settable TIM7 TIMER7 global interrupt 0x0000_0088 19 26 settable - reserved 0x0000_008C 20 27 settable TIM21 TIMER21 global interrupt 0x0000_0090 21 28 settable I2C3 I2C3 global interrupt 0x0000_0094 22 29 settable TIM22 TIMER22 global interrupt 0x0000_0098 23 30 settable I2C1 I2C1 global interrupt through EXTI23 0x0000_009C 24 31 settable I2C2 I2C2 global interrupt 0x0000_00A0 25 32 settable SPI1 SPI1 global interrupt 0x0000_00A4 26 33 settable SPI2 SPI2 global interrupt 0x0000_00A8 27 34 settable USART1 USART1 global interrupt through EXTI25 0x0000_00AC Acronym Description DocID025942 Rev 5 Address 258/874 269 Nested vectored interrupt controller (NVIC) RM0377 Table 50. List of vectors(1)(2) (continued) Position Priority Type of priority 28 35 settable USART2 USART2 global interrupt through EXTI26 0x0000_00B0 29 36 settable LPUART1 + AES LPUART1 global interrupt through EXTI28 + AES global interrupt 0x0000_00B4 Acronym Description Address 1. The grayed cells correspond to the Cortex®-M0+ interrupts. 2. Refer to Table 1: STM32L0x1 memory density, to Table 2: Features per category and to the device datasheets for the GPIO ports and peripherals available on your device. The memory area corresponding to unavailable GPIO ports or peripherals are reserved. 259/874 DocID025942 Rev 5 RM0377 Extended interrupt and event controller (EXTI) 12 Extended interrupt and event controller (EXTI) 12.1 Introduction The extended interrupts and events controller (EXTI) manages the external and internal asynchronous events/interrupts and generates the event request to the CPU/interrupt controller plus a wake-up request to the power controller. The EXTI allows the management of up to 30 event lines which can wake up the device from Stop mode. Some of the lines are configurable: in this case the active edge can be chosen independently, and a status flag indicates the source of the interrupt. The configurable lines are used by the I/Os external interrupts, and by few peripherals. Some of the lines are direct: they are used by some peripherals to generate a wakeup from Stop event or interrupt. In this case the status flag is provided by the peripheral. Each line can be masked independently for interrupt or event generation. Te EXTI controller also allows to emulate, by programming to a dedicated register, events or interrupts by software multiplexed with the corresponding hardware event line. 12.2 EXTI main features The EXTI main features are the following: 12.3 Generation of up to 30 event/interrupt requests (configurable and direct lines). Independent mask on each event/interrupt line Configurable rising or falling edge (configurable lines only) Dedicated status bit (configurable lines only) Emulation of event/interrupt requests (configurable lines only) EXTI functional description For the configurable interrupt lines, the interrupt line should be configured and enabled in order to generate an interrupt. This is done by programming the two trigger registers with the desired edge detection and by enabling the interrupt request by writing a ‘1’ to the corresponding bit in the interrupt mask register. When the selected edge occurs on the interrupt line, an interrupt request is generated. The pending bit corresponding to the interrupt line is also set. This request is cleared by writing a ‘1’ in the pending register. For the direct interrupt lines: the interrupt is enabled by default in the interrupt mask register and there is no corresponding pending bit in the pending register. To generate an event, the event line should be configured and enabled. This is done by programming the two trigger registers with the desired edge detection and by enabling the event request by writing a ‘1’ to the corresponding bit in the event mask register. When the selected edge occurs on the event line, an event pulse is generated. The pending bit corresponding to the event line is not set. For the configurable lines, an interrupt/event request can also be generated by software by writing a ‘1’ in the software interrupt/event register. DocID025942 Rev 5 260/874 269 Extended interrupt and event controller (EXTI) RM0377 Note: The interrupts or events associated to the direct lines are triggered only when the system is in Stop mode. If the system is still running, no interrupt/event is generated by the EXTI. 12.3.1 EXTI block diagram The block diagram is shown in Figure 28. Figure 28. Extended interrupts and events controller (EXTI) block diagram $3%EXV 3&/. 3HULSKHUDOLQWHUIDFH )DOOLQJ WULJJHU VHOHFWLRQ UHJLVWHU 5LVLQJ WULJJHU VHOHFWLRQ UHJLVWHU 6RIWZDUH LQWHUUXSW HYHQW UHJLVWHU (YHQW PDVN UHJLVWHU ,QWHUUXSW PDVN UHJLVWHU 3HQGLQJ UHTXHVW UHJLVWHU ,QWHUUXSWV &RQILJXUDEOH HYHQWV 'LUHFW HYHQWV (GJHGHWHFW FLUFXLW (YHQWV 5LVLQJ HGJH GHWHFW 6WRSPRGH :DNHXS 06Y9 12.3.2 Wakeup event management The STM32L0x1 microcontrollers are able to handle external or internal events in order to wake up the core (WFE). The wakeup event can be generated by either: 261/874 enabling an interrupt in the peripheral control register but not in the NVIC, and enabling the SEVONPEND bit in the Cortex®-M0+ system control register (see STM32L0 Series Cortex®-M0+ programming manual (PM0223)). When the MCU resumes from WFE, the peripheral interrupt pending bit and the peripheral NVIC IRQ channel pending bit (in the NVIC interrupt clear pending register) have to be cleared. or configuring an EXTI line in event mode. When the CPU resumes from WFE, it is not necessary to clear the peripheral interrupt pending bit or the NVIC IRQ channel pending bit as the pending bit corresponding to the event line is not set. DocID025942 Rev 5 RM0377 12.3.3 Extended interrupt and event controller (EXTI) Peripherals asynchronous interrupts Some peripherals can generate events when the system is in Run mode or in Stop mode, thus allowing to wake up the system from Stop mode. To accomplish this, the peripheral generates both a synchronized (to the system clock, e.g. APB clock) and an asynchronous version of the event. This asynchronous event is connected to an EXTI direct line. Note: Few peripherals with wakeup from Stop capability are connected to an EXTI configurable line. In this case the EXTI configuration is required to allow the wakeup from Stop mode. 12.3.4 Hardware interrupt selection To configure a line as an interrupt source, use the following procedure: 1. Configure the mask bits of the Interrupt lines (EXTI_IMR) 2. Configure the Trigger Selection bits of the Interrupt lines (EXTI_RTSR and EXTI_FTSR) 3. Configure the enable and mask bits that control the NVIC IRQ channel mapped to the extended interrupt controller (EXTI) so that an interrupt coming from any one of the lines can be correctly acknowledged. The direct lines do not require any EXTI configuration. For code example, refer to A.7.2: Extended interrupt selection code example. 12.3.5 Hardware event selection To configure a line as an event source, use the following procedure: 12.3.6 1. Configure the mask bits of the Event lines (EXTI_EMR) 2. Configure the Trigger Selection bits of the Event lines (EXTI_RTSR and EXTI_FTSR). Software interrupt/event selection Any of the configurable lines can be configured as software interrupt/event lines. The procedure below must be followed to generate a software interrupt. 1. Configure the mask bits of the Interrupt/Event lines (EXTI_IMR, EXTI_EMR) 2. Set the required bit in the software interrupt register (EXTI_SWIER). DocID025942 Rev 5 262/874 269 Extended interrupt and event controller (EXTI) 12.4 RM0377 EXTI interrupt/event line mapping In the STM32L0x1, 30 interrupt/event lines are available.The GPIOs are connected to 16 configurable interrupt/event lines as shown in Figure 29. Figure 29. Extended interrupt/event GPIO mapping (;7,>@ELWVLQ6<6&)*B(;7,&5UHJLVWHU 3$ 3% 3& (;7, (;7,>@ELWVLQ6<6&)*B(;7,&5UHJLVWHU 3$ 3% 3& (;7, (;7,>@ELWVLQ6<6&)*B(;7,&5UHJLVWHU 3$ 3% 3& (;7, 3' (;7,>@ELWVLQ6<6&)*B(;7,&5UHJLVWHU 3$ 3% 3& (;7, 06Y9 Note: 263/874 Refer to the datasheet for the list of available I/O ports. DocID025942 Rev 5 RM0377 Extended interrupt and event controller (EXTI) The 30 lines are connected as shown in Table 51: EXTI lines connections: Table 51. EXTI lines connections EXTI line Line source Line type 0-15 GPIO configurable 16 PVD configurable 17 RTC alarm configurable 18 Reserved 19 RTC tamper or timestamp or CSS_LSE configurable 20 RTC wakeup timer configurable 21 COMP1 output configurable 22 COMP2 output configurable 23 I2C1 wakeup direct 24 I2C3 wakeup direct 25 USART 1 wakeup direct 26 USART2 wakeup direct 27 Reserved 28 LPUART1 wakeup direct 29 LPTIM1 wakeup direct DocID025942 Rev 5 264/874 269 Extended interrupt and event controller (EXTI) 12.5 RM0377 EXTI registers Refer to Section 1.1 for a list of abbreviations used in register descriptions. The peripheral registers have to be accessed by words (32-bit). 12.5.1 EXTI interrupt mask register (EXTI_IMR) Address offset: 0x00 Reset value: 0x3F84 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. IM29 IM28 Res. IM26 IM25 IM24 IM23 IM22 IM21 IM20 IM19 IM18 IM17 IM16 rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IM15 IM14 IM13 IM12 IM11 IM10 IM9 IM8 IM7 IM6 IM5 IM4 IM3 IM2 IM1 IM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 IMx: Interrupt mask on line x (x = 29 to 28) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked Bit 27 Reserved, must be kept at reset value. Bits 26:0 IMx: Interrupt mask on line x (x = 26 to 0) 0: Interrupt request from Line x is masked 1: Interrupt request from Line x is not masked 12.5.2 EXTI event mask register (EXTI_EMR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. EM29 EM28 Res. EM26 EM25 EM24 EM23 EM22 EM21 EM20 EM19 EM18 EM17 EM16 rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EM15 EM14 EM13 EM12 EM11 EM10 EM9 EM8 EM7 EM6 EM5 EM4 EM3 EM2 EM1 EM0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:30 Reserved, must be kept at reset value. Bits 29:28 EMx: Event mask on line x (x = 29 to 28) 0: Event request from Line x is masked 1: Event request from Line x is not masked Bit 27 Reserved, must be kept at reset value. Bits 26:0 EMx: Event mask on line x (x = 26 to 0) 0: Event request from Line x is masked 1: Event request from Line x is not masked 265/874 DocID025942 Rev 5 RM0377 Extended interrupt and event controller (EXTI) 12.5.3 EXTI rising edge trigger selection register (EXTI_RTSR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. RT22 RT21 RT20 RT19 Res. RT17 RT16 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 RT16 2 1 0 RT15 RT14 RT13 RT12 RT11 RT10 RT9 RT8 RT7 RT6 RT5 RT4 RT3 RT2 RT1 RT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:19 RTx: Rising trigger event configuration bit of line x (x = 22 to 19) 0: Rising trigger disabled (for Event and Interrupt) for input line x 1: Rising trigger enabled (for Event and Interrupt) for input line x Bit 18 Reserved, must be kept at reset value. Bits 17:0 RTx: Rising trigger event configuration bit of line x (x = 17 to 0) 0: Rising trigger disabled (for Event and Interrupt) for input line x 1: Rising trigger enabled (for Event and Interrupt) for input line x Note: The configurable wakeup lines are edge triggered, no glitch must be generated on these lines. If a rising edge on the configurable interrupt line occurs while writing to the EXTI_RTSR register, the pending bit will not be set. Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition. 12.5.4 Falling edge trigger selection register (EXTI_FTSR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. FT22 FT21 FT20 FT19 Res. FT17 FT16 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FT15 FT14 FT13 FT12 FT11 FT10 FT9 FT8 FT7 FT6 FT5 FT4 FT3 FT2 FT1 FT0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw DocID025942 Rev 5 266/874 269 Extended interrupt and event controller (EXTI) Bits 31:23 RM0377 Reserved, must be kept at reset value. Bits 22:19 FTx: Falling trigger event configuration bit of line x (x = 22 to 19) 0: Falling trigger disabled (for Event and Interrupt) for input line x 1: Falling trigger enabled (for Event and Interrupt) for input line x Bit 18 Reserved, must be kept at reset value. Bits 17:0 FTx: Falling trigger event configuration bit of line x (x = 17 to 0) 0: Falling trigger disabled (for Event and Interrupt) for input line x 1: Falling trigger enabled (for Event and Interrupt) for input line x Note: The configurable wakeup lines are edge triggered, no glitch must be generated on these lines. If a falling edge on the configurable interrupt line occurs while writing to the EXTI_FTSR register, the pending bit will not be set. Rising and falling edge triggers can be set for the same interrupt line. In this configuration, both generate a trigger condition. 12.5.5 EXTI software interrupt event register (EXTI_SWIER) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. SWI22 SWI21 SWI20 SWI19 Res. SWI17 SWI16 rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SWI15 SWI14 SWI13 SWI12 SWI11 SWI10 SWI9 SWI8 SWI7 SWI6 SWI5 SWI4 SWI3 SWI2 SWI1 SWI0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:23 Reserved, must be kept at reset value. Bits 22:19 SWIx: Software interrupt on line x (x = 22 to 19) Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the interrupt is enabled on this line in EXTI_IMR and EXTI_EMR, an interrupt request is generated. This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to this bit). Bit 18 Reserved, must be kept at reset value. Bits 17:0 SWIx: Software interrupt on line x (x = 17 to 0) Writing a 1 to this bit when it is at 0 sets the corresponding pending bit in EXTI_PR. If the interrupt is enabled on this line in EXTI_IMR and EXTI_EMR, an interrupt request is generated. This bit is cleared by clearing the corresponding bit in EXTI_PR (by writing a 1 to this bit). 267/874 DocID025942 Rev 5 RM0377 Extended interrupt and event controller (EXTI) 12.5.6 EXTI pending register (EXTI_PR) Address offset: 0x14 Reset value: undefined 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. PIF22 PIF21 PIF20 PIF19 Res. PIF17 PIF16 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PIF15 PIF14 PIF13 PIF12 PIF11 PIF10 PIF9 PIF8 PIF7 PIF6 PIF5 PIF4 PIF3 PIF2 PIF1 PIF0 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits 31:23 Reserved, must be kept at reset value. Bits 22:19 PIFx: Pending interrupt flag on line x (x = 22 to 19) 0: No trigger request occurred 1: The selected trigger request occurred This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing it to 1 or by changing the sensitivity of the edge detector. Bit 18 Reserved, must be kept at reset value. Bits 17:0 PIFx: Pending interrupt flag on line x (x = 17 to 0) 0: No trigger request occurred 1: The selected trigger request occurred This bit is set when the selected edge event arrives on the interrupt line. This bit is cleared by writing it to 1 or by changing the sensitivity of the edge detector. DocID025942 Rev 5 268/874 269 Extended interrupt and event controller (EXTI) 12.5.7 RM0377 EXTI register map The following table gives the EXTI register map and the reset values. 0x14 Res. IM[26:24] EM[26:24] FT[22:19] Reset value 0 0 0 0 EXTI_SWIER SWI [22:19] Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x10 EXTI_FTSR Reset value 0 0 0 0 EXTI_PR PIF [22:19] Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x0C Res. 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value RT[22:19] 0 0 0 0 RT[17:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. EXTI_RTSR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FT[17:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. 0x08 EM[23:0] SWI[17:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Reset value 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. EXTI_EMR IM[23:0] Res. Res. Res. Res. Res. Res. Res. Res. Res. 0x04 1 1 Res. Res. Reset value IM[29:28] EXTI_IMR EM[29:28] 0x00 Register Res. Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 52. Extended interrupt/event controller register map and reset values PIF[17:0] 0 0 0 0 0 Refer to Section 2.2.2 for the register boundary addresses. 269/874 DocID025942 Rev 5 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0377 Analog-to-digital converter (ADC) 13 Analog-to-digital converter (ADC) 13.1 Introduction The 12-bit ADC is a successive approximation analog-to-digital converter. It has up to 19 multiplexed channels allowing it to measure signals from 16 external and 3 internal sources. A/D conversion of the various channels can be performed in single, continuous, scan or discontinuous mode. The result of the ADC is stored in a left-aligned or right-aligned 16-bit data register. The analog watchdog feature allows the application to detect if the input voltage goes outside the user-defined higher or lower thresholds. An efficient low-power mode is implemented to allow very low consumption at low frequency. A built-in hardware oversampler allows to improve analog performances while off-loading the related computational burden from the CPU. DocID025942 Rev 5 270/874 318 Analog-to-digital converter (ADC) 13.2 RM0377 ADC main features High performance – 12-bit, 10-bit, 8-bit or 6-bit configurable resolution – ADC conversion time: 0.87 µs for 12-bit resolution (1.14 MHz), 0.81 µs conversion time for 10-bit resolution, faster conversion times can be obtained by lowering resolution. – Self-calibration – Programmable sampling time – Data alignment with built-in data coherency – DMA support Low-power – Application can reduce PCLK frequency for low-power operation while still keeping optimum ADC performance. For example, 1.0 µs conversion time is kept, whatever the frequency of PCLK) – Wait mode: prevents ADC overrun in applications with low frequency PCLK – Auto off mode: ADC is automatically powered off except during the active conversion phase. This dramatically reduces the power consumption of the ADC. Analog input channels – up to 16 external analog inputs – 1 channel for internal temperature sensor (VSENSE) – 1 channel for internal reference voltage (VREFINT) Start-of-conversion can be initiated: – By software – By hardware triggers with configurable polarity (internal timer events from TIM2, TIM3, TIM6, TIM21, TIM22 or GPIO input events) Conversion modes – Can convert a single channel or can scan a sequence of channels. – Single mode converts selected inputs once per trigger – Continuous mode converts selected inputs continuously – Discontinuous mode Interrupt generation at the end of sampling, end of conversion, end of sequence conversion, and in case of analog watchdog or overrun events Analog watchdog Oversampler – 16-bit data register – Oversampling ratio adjustable from 2 to 256x – Programmable data shift up to 8-bits ADC supply requirements: 1.65 to 3.6 V ADC input range: VSSA VIN VDDA Figure 30 shows the block diagram of the ADC. 271/874 DocID025942 Rev 5 RM0377 13.3 Analog-to-digital converter (ADC) ADC pins and internal signals Table 53. ADC internal signals Internal signal name Signal type TRGx Input ADC conversion triggers VSENSE Input Internal temperature sensor output voltage VREFINT Input Internal voltage reference output voltage Description Table 54. ADC pins Name Signal type Remarks VDDA Input, analog power supply Analog power supply and positive reference voltage for the ADC, VDDA VDD VSSA Input, analog supply ground Ground for analog power supply. Must be at VSS potential ADC_IN[15:0] Analog input signals Up to 16 analog input channels DocID025942 Rev 5 272/874 318 Analog-to-digital converter (ADC) 13.4 RM0377 ADC functional description Figure 30 shows the ADC block diagram and Table 54 gives the ADC pin description. Figure 30. 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Refer to Table 57: External triggers for TRGi mapping. 13.4.1 ADC voltage regulator (ADVREGEN) The ADC has a specific internal voltage regulator which must be enabled and stable before using the ADC. The ADC voltage regulator stabilization time is entirely managed by the hardware and software does not need to care about it. After ADC operations are complete, the ADC can be disabled (ADEN=0). It is then possible to save more power by disabling the ADC voltage regulator (refer to the ADC voltage regulator disable sequence). Note: 273/874 When the internal voltage regulator is disabled, the internal analog calibration is kept. DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Analog reference for the ADC internal voltage regulator The internal ADC voltage regulator uses a buffered copy of the internal voltage reference. This buffer is always enabled when the main voltage regulator is in normal Run mode (MR mode, with the device operating either in Run or Sleep mode). When the main voltage regulator is in Low-power run mode (LPR mode, with the device operating in Low-power run, Low-power sleep or Stop mode), the voltage reference is disabled and the ADC cannot be used anymore. The software must follow the procedure described below to manage the ADC in Low powerrun mode: 1. Make sure that the ADC is disabled (ADEN = 0). 2. Write ADVREFEN = 0. 3. Enter Low-power run mode 4. Resume from Low-power run mode. 5. Check that REGLPF = 0. 6. Enable the ADC voltage regulator by using the sequence described in Section : ADVREG enable sequence (ADVREGEN= 1 in ADC_CR). 7. Write ADC_CR ADEN = 1 and wait until ADC_CR ADRDY = 1. 8. Write ADRDY = 1 to clear it. ADVREG enable sequence There are three ways to enable the voltage regulator: by writing ADVREGEN=1. by launching the calibration by writing by ADCAL=1 (the ADVREGEN bit will be automatically set to 1) by enabling the ADC by writing ADEN=1 ADVREG disable sequence To disable the ADC voltage regulator, perform the sequence below: 13.4.2 1. Ensure that the ADC is disabled (ADEN=0) 2. Write ADVREGEN=0 Calibration (ADCAL) The ADC has a calibration feature. During the procedure, the ADC calculates a calibration factor which is internally applied to the ADC until the next ADC power-off. The application must not use the ADC during calibration and must wait until it is complete. Calibration should be performed before starting A/D conversion. It removes the offset error which may vary from chip to chip due to process variation. The calibration is initiated by software by setting bit ADCAL=1. Calibration can only be initiated when the ADC is disabled (when ADEN=0). ADCAL bit stays at 1 during all the calibration sequence. It is then cleared by hardware as soon the calibration completes. After this, the calibration factor can be read from the ADC_DR register (from bits 6 to 0). DocID025942 Rev 5 274/874 318 Analog-to-digital converter (ADC) RM0377 The internal analog calibration is kept if the ADC is disabled (ADEN=0) or if the ADC voltage reference is disabled (ADVREGEN = 0). When the ADC operating conditions change (VDDA changes are the main contributor to ADC offset variations and temperature change to a lesser extend), it is recommended to re-run a calibration cycle. The calibration factor is lost in the following cases: The product is in STANDBY mode (power supply removed from the ADC) The ADC peripheral is reset. The calibration factor is maintained in the following low-power modes: Low-power run, Lowpower sleep and STOP. It is still possible to save and restore the calibration factor by software to save time when restarting the ADC (as long as temperature and voltage are stable during the ADC power down). The calibration factor can be written if the ADC is enabled but not converting (ADEN=1 and ADSTART=0). Then, at the next start of conversion, the calibration factor is automatically injected into the analog ADC. This loading is transparent and does not add any cycle latency to the start of the conversion. Calibration software procedure 1. Ensure that ADEN=0 2. Set ADCAL=1 3. Wait until ADCAL=0 (or until EOCAL=1). This can be handled by interrupt if the interrupt is enabled by setting the EOCALIE bit in the ADC_IER register 4. The calibration factor can be read from bits 6:0 of ADC_DR or ADC_CALFACT registers. For code example, refer to A.8.1: Calibration code example. Figure 31. ADC calibration W &$% $'&$/ $'&6WDWH 2)) 6WDUWXS &$/,%5$7( [ $'&B'5>@ 2)) &$/,%5$7,21 )$&725 $'&B&$/)$&7@ E\6: E\+: 069 If the ADC voltage regulator was not previously set, it will be automatically enabled when setting ADCAL=1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC calibration time is longer to take into account the stabilization time of the ADC voltage regulator. At the end of the calibration, the ADC voltage regulator remains enabled. 275/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Calibration factor forcing Software Procedure 1. Ensure that ADEN= 1 and ADSTART =0 (ADC started with no conversion ongoing) 2. Write ADC_CALFACT with the saved calibration factor 3. The calibration factor will be used as soon as a new conversion will be launched. Figure 32. Calibration factor forcing $'&VWDWH ,QWHUQDO FDOLEUDWLRQIDFWRU>@ 6WDUWFRQYHUVLRQ KDUGZDUHRUVRIWZDUH 5HDG\QRWFRQYHUWLQJ &RQYHUWLQJFKDQQHO 8SGDWLQJ 6LQJOHHQGHG FDOLEUDWLRQ ) 5HDG\ &RQYHUWLQJFKDQQHO 6LQJOHHQGHG ) :5,7($'&B&$/)$&7 &$/)$&7>@ E\6: ) E\+: 069 13.4.3 ADC on-off control (ADEN, ADDIS, ADRDY) At MCU power-up, the ADC is disabled and put in power-down mode (ADEN=0). As shown in Figure 33, the ADC needs a stabilization time of tSTAB before it starts converting accurately. Two control bits are used to enable or disable the ADC: Set ADEN=1 to enable the ADC. The ADRDY flag is set as soon as the ADC is ready for operation. Set ADDIS=1 to disable the ADC and put the ADC in power down mode. The ADEN and ADDIS bits are then automatically cleared by hardware as soon as the ADC is fully disabled. If the ADC voltage regulator was not previously set, it will be automatically enabled when setting ADEN=1 (bit ADVREGEN is automatically set by hardware). In this case, the ADC stabilization time tSTAB is longer to take into account the stabilization time of the ADC voltage regulator. Conversion can then start either by setting ADSTART=1 (refer to Section 13.5: Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) on page 283) or when an external trigger event occurs if triggers are enabled. Follow this procedure to enable the ADC: 1. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1. 2. Set ADEN=1 in the ADC_CR register. 3. Wait until ADRDY=1 in the ADC_ISR register (ADRDY is set after the ADC startup time). This can be handled by interrupt if the interrupt is enabled by setting the ADRDYIE bit in the ADC_IER register. For code example, refer to A.8.2: ADC enable sequence code example. DocID025942 Rev 5 276/874 318 Analog-to-digital converter (ADC) RM0377 Follow this procedure to disable the ADC: 1. Check that ADSTART=0 in the ADC_CR register to ensure that no conversion is ongoing. If required, stop any ongoing conversion by writing 1 to the ADSTP bit in the ADC_CR register and waiting until this bit is read at 0. 2. Set ADDIS=1 in the ADC_CR register. 3. If required by the application, wait until ADEN=0 in the ADC_CR register, indicating that the ADC is fully disabled (ADDIS is automatically reset once ADEN=0). 4. Clear the ADRDY bit in ADC_ISR register by programming this bit to 1 (optional). For code example, refer to A.8.3: ADC disable sequence code example. Figure 33. Enabling/disabling the ADC W 67$% $'(1 $'5'< $'',6 $'& VWDW E\6: 2)) 6WDUWXS 5'< &219(57,1*&+ 5'< 5(42) 2)) E\+: 069 Note: In auto-off mode (AUTOFF=1) the power-on/off phases are performed automatically, by hardware and the ADRDY flag is not set. 13.4.4 ADC clock (CKMODE, PRESC[3:0], LFMEN) The ADC has a dual clock-domain architecture, so that the ADC can be fed with a clock (ADC asynchronous clock) independent from the APB clock (PCLK). Figure 34. ADC clock scheme $',7) 5&& 5HVHW&ORFN&RQWUROOHU 3&/. $3%LQWHUIDFH %LWV&.02'(>@ RI$'&B&)*5 RURU $'& DV\QFKURQRXV FORFN %LWV35(6&>@ RI$'&B&&5 2WKHUV $QDORJ$'&B&. $QDORJ $'& %LWV&.02'(>@ RI$'&B&)*5 069 1. Refer to Section 7: Reset and clock control (RCC) on page 87 to see how PCLK and ADC asynchronous clock are enabled. 277/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) The input clock of the analog ADC can be selected between two different clock sources (see Figure 34: ADC clock scheme to see how PCLK and the ADC asynchronous clock are enabled): a) The ADC clock can be a specific clock source, named “ADC asynchronous clock “which is independent and asynchronous with the APB clock. Refer to RCC Section for more information on generating this clock source. To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be reset. b) The ADC clock can be derived from the APB clock of the ADC bus interface, divided by a programmable factor (2 or 4) according to bits CKMODE[1:0]. To select this scheme, bits CKMODE[1:0] of the ADC_CFGR2 register must be different from “00”. For code example, refer to A.8.4: ADC clock selection code example. In option a), the generated ADC clock can eventually be divided by a prescaler (1, 2, 4, 6, 8, 12, 16, 32, 64, 128, 256) when programming the bits PRESC[3:0] in the ADC_CCR register). Option a) has the advantage of reaching the maximum ADC clock frequency whatever the APB clock scheme selected. Option b) has the advantage of bypassing the clock domain resynchronizations. This can be useful when the ADC is triggered by a timer and if the application requires that the ADC is precisely triggered without any uncertainty (otherwise, an uncertainty of the trigger instant is added by the resynchronizations between the two clock domains). Table 55. Latency between trigger and start of conversion ADC clock source Caution: CKMODE[1:0] Latency between the trigger event and the start of conversion HSI16 MHz clock 00 Latency is not deterministic (jitter) PCLK divided by 2 01 Latency is deterministic (no jitter) and equal to 4.25 ADC clock cycles PCLK divided by 4 10 Latency is deterministic (no jitter) and equal to 4.125 ADC clock cycles PCLK divided by 1 11 Latency is deterministic (no jitter) and equal to 4.5 ADC clock cycles When selecting CKMODE[1:0]=11 (PCLK divided by 1), the user must ensure that PCLK has a 50% duty cycle. For this, inside the RCC, the user must select a system clock which has a 50% duty cycle and must configure the APB prescaler inside the RCC in bypass modes (refer to RCC section). In case of an internal source clock, this implies only that the AHB and APB prescalers do not divide the clock. Low frequency When selecting an analog ADC clock frequency lower than 3.5 MHz, it is mandatory to first enable the Low Frequency Mode by setting bit LFMEN=1 into the ADC_CCR register DocID025942 Rev 5 278/874 318 Analog-to-digital converter (ADC) 13.4.5 RM0377 Configuring the ADC Software must write to the ADCAL and ADEN bits in the ADC_CR register if the ADC is disabled (ADEN must be 0). Software must only write to the ADSTART and ADDIS bits in the ADC_CR register only if the ADC is enabled and there is no pending request to disable the ADC (ADEN = 1 and ADDIS = 0). For all the other control bits in the ADC_IER, ADC_CFGRi, ADC_SMPR, ADC_TR, ADC_CHSELR and ADC_CCR registers, software must only write to the configuration control bits if the ADC is enabled (ADEN = 1) and if there is no conversion ongoing (ADSTART = 0). Software must only write to the ADSTP bit in the ADC_CR register if the ADC is enabled (and possibly converting) and there is no pending request to disable the ADC (ADSTART = 1 and ADDIS = 0) Note: There is no hardware protection preventing software from making write operations forbidden by the above rules. If such a forbidden write access occurs, the ADC may enter an undefined state. To recover correct operation in this case, the ADC must be disabled (clear ADEN=0 and all the bits in the ADC_CR register). 13.4.6 Channel selection (CHSEL, SCANDIR) There are up to 19 multiplexed channels: 16 analog inputs from GPIO pins (ADC_IN0...ADC_IN15) 3 internal analog inputs (Temperature Sensor, Internal Reference Voltage ) It is possible to convert a single channel or to automatically scan a sequence of channels. The sequence of the channels to be converted must be programmed in the ADC_CHSELR channel selection register: each analog input channel has a dedicated selection bit (CHSEL0...CHSEL18). The order in which the channels will be scanned can be configured by programming the bit SCANDIR bit in the ADC_CFGR1 register: SCANDIR=0: forward scan Channel 0 to Channel 18 SCANDIR=1: backward scan Channel 18 to Channel 0 Temperature sensor, VREFINT internal channels The temperature sensor is connected to channel ADC_IN18. The internal voltage reference VREFINT is connected to channel ADC_IN17. 13.4.7 Programmable sampling time (SMP) Before starting a conversion, the ADC needs to establish a direct connection between the voltage source to be measured and the embedded sampling capacitor of the ADC. This sampling time must be enough for the input voltage source to charge the sample and hold capacitor to the input voltage level. Having a programmable sampling time allows to trim the conversion speed according to the input resistance of the input voltage source. The ADC samples the input voltage for a number of ADC clock cycles that can be modified using the SMP[2:0] bits in the ADC_SMPR register. 279/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) This programmable sampling time is common to all channels. If required by the application, the software can change and adapt this sampling time between each conversions. The total conversion time is calculated as follows: tCONV = Sampling time + 12.5 x ADC clock cycles Example: With ADC_CLK = 16 MHz and a sampling time of 1.5 ADC clock cycles: tCONV = 1.5 + 12.5 = 14 ADC clock cycles = 0.875 µs The ADC indicates the end of the sampling phase by setting the EOSMP flag. 13.4.8 Single conversion mode (CONT=0) In Single conversion mode, the ADC performs a single sequence of conversions, converting all the channels once. This mode is selected when CONT=0 in the ADC_CFGR1 register. Conversion is started by either: Setting the ADSTART bit in the ADC_CR register Hardware trigger event Inside the sequence, after each conversion is complete: The converted data are stored in the 16-bit ADC_DR register The EOC (end of conversion) flag is set An interrupt is generated if the EOCIE bit is set After the sequence of conversions is complete: The EOSEQ (end of sequence) flag is set An interrupt is generated if the EOSEQIE bit is set Then the ADC stops until a new external trigger event occurs or the ADSTART bit is set again. Note: To convert a single channel, program a sequence with a length of 1. 13.4.9 Continuous conversion mode (CONT=1) In continuous conversion mode, when a software or hardware trigger event occurs, the ADC performs a sequence of conversions, converting all the channels once and then automatically re-starts and continuously performs the same sequence of conversions. This mode is selected when CONT=1 in the ADC_CFGR1 register. Conversion is started by either: Setting the ADSTART bit in the ADC_CR register Hardware trigger event Inside the sequence, after each conversion is complete: The converted data are stored in the 16-bit ADC_DR register The EOC (end of conversion) flag is set An interrupt is generated if the EOCIE bit is set After the sequence of conversions is complete: The EOSEQ (end of sequence) flag is set An interrupt is generated if the EOSEQIE bit is set DocID025942 Rev 5 280/874 318 Analog-to-digital converter (ADC) RM0377 Then, a new sequence restarts immediately and the ADC continuously repeats the conversion sequence. Note: To convert a single channel, program a sequence with a length of 1. It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. 13.4.10 Starting conversions (ADSTART) Software starts ADC conversions by setting ADSTART=1. When ADSTART is set, the conversion: Starts immediately if EXTEN = 00 (software trigger) At the next active edge of the selected hardware trigger if EXTEN 00 The ADSTART bit is also used to indicate whether an ADC operation is currently ongoing. It is possible to re-configure the ADC while ADSTART=0, indicating that the ADC is idle. The ADSTART bit is cleared by hardware: In single mode with software trigger (CONT=0, EXTEN=00) – In discontinuous mode with software trigger (CONT=0, DISCEN=1, EXTEN=00) – At end of conversion (EOC=1) In all cases (CONT=x, EXTEN=XX) – Note: At any end of conversion sequence (EOSEQ=1) After execution of the ADSTP procedure invoked by software (see Section 13.4.12: Stopping an ongoing conversion (ADSTP) on page 283) In continuous mode (CONT=1), the ADSTART bit is not cleared by hardware when the EOSEQ flag is set because the sequence is automatically relaunched. When hardware trigger is selected in single mode (CONT=0 and EXTEN 00), ADSTART is not cleared by hardware when the EOSEQ flag is set. This avoids the need for software having to set the ADSTART bit again and ensures the next trigger event is not missed. 281/874 DocID025942 Rev 5 RM0377 13.4.11 Analog-to-digital converter (ADC) Timings The elapsed time between the start of a conversion and the end of conversion is the sum of the configured sampling time plus the successive approximation time depending on data resolution: tADC = tSMPL + tSAR = [ 1.5 |min + 12.5 |12bit ] x tADC_CLK tADC = tSMPL + tSAR = 93.8 ns |min + 781.3 ns |12bit = 0.875 µs |min (for fADC_CLK = 16 MHz) Figure 35. Analog to digital conversion time $'&VWDWH $QDORJ FKDQQHO ,QWHUQDO6+ $'67$57 5'< 6$03/,1*&+1 &+1 &+1 6DPSOH$,11 W 603/ VHW E\6: 6DPSOH$,11 +ROG$,11 W 6$5 FOHDUHGE\6: VHWE\+: (2603 VHW E\+: (2& $'&B'5 W 603/ W 6$5 6$03/,1*&+1 &219(57,1*&+1 FOHDUHG E\6: '$7$1 '$7$1 GHSHQGVRQ603>@ GHSHQGVRQ5(6>@ 069 Figure 36. ADC conversion timings $'67$57 $'&VWDWH W/$7(1&< 5HDG\ 6 &RQYHUVLRQ 6 &RQYHUVLRQ :/$7(1&< 6 &RQYHUVLRQ :/$7(1&< 6 &RQYHUVLRQ :/$7(1&< $'&B'5 'DWD 'DWD 'DWD 06Y9 1. EXTEN =00 or EXTEN 00 2. Trigger latency (refer to datasheet for more details) 3. ADC_DR register write latency (refer to datasheet for more details) DocID025942 Rev 5 282/874 318 Analog-to-digital converter (ADC) 13.4.12 RM0377 Stopping an ongoing conversion (ADSTP) The software can decide to stop any ongoing conversions by setting ADSTP=1 in the ADC_CR register. This will reset the ADC operation and the ADC will be idle, ready for a new operation. When the ADSTP bit is set by software, any ongoing conversion is aborted and the result is discarded (ADC_DR register is not updated with the current conversion). The scan sequence is also aborted and reset (meaning that restarting the ADC would restart a new sequence). Once this procedure is complete, the ADSTP and ADSTART bits are both cleared by hardware and the software must wait until ADSTART=0 before starting new conversions. Figure 37. Stopping an ongoing conversion $'&VWDWH $'67$57 5'< 6$03/,1*&+1 5'< &219(57,1*&+1 FOHDUHGE\+: VHWE\6: VHWE\6: $'6723 $'&B'5 FOHDUHGE\+: '$7$1 069 13.5 Conversion on external trigger and trigger polarity (EXTSEL, EXTEN) A conversion or a sequence of conversion can be triggered either by software or by an external event (for example timer capture). If the EXTEN[1:0] control bits are not equal to “0b00”, then external events are able to trigger a conversion with the selected polarity. The trigger selection is effective once software has set bit ADSTART=1. Any hardware triggers which occur while a conversion is ongoing are ignored. If bit ADSTART=0, any hardware triggers which occur are ignored. Table 56 provides the correspondence between the EXTEN[1:0] values and the trigger polarity. Table 56. Configuring the trigger polarity Source Note: EXTEN[1:0] Trigger detection disabled 00 Detection on rising edge 01 Detection on falling edge 10 Detection on both rising and falling edges 11 The polarity of the external trigger can be changed only when the ADC is not converting (ADSTART= 0). The EXTSEL[2:0] control bits are used to select which of 8 possible events can trigger conversions. 283/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Table 57 gives the possible external trigger for regular conversion. Software source trigger events can be generated by setting the ADSTART bit in the ADC_CR register. Table 57. External triggers Name Source EXTSEL[2:0] TRG0 TIM6_TRGO 000 TRG1 TIM21_CH2 001 TRG2 TIM2_TRGO 010 TRG3 TIM2_CH4 TRG4 011 TIM22_TRGO, TIM21_TRGO (2) (1) 100 TIM2_CH3 101 TRG6 TIM3_TRGO 110 TRG7 EXTI line 11 111 TRG5 1. TIM21_TRGO is not available on category 1 devices. 2. Available on all categories except category 3. Note: The trigger selection can be changed only when the ADC is not converting (ADSTART= 0). 13.5.1 Discontinuous mode (DISCEN) This mode is enabled by setting the DISCEN bit in the ADC_CFGR1 register. In this mode (DISCEN=1), a hardware or software trigger event is required to start each conversion defined in the sequence. On the contrary, if DISCEN=0, a single hardware or software trigger event successively starts all the conversions defined in the sequence. Example: Note: DISCEN=1, channels to be converted = 0, 3, 7, 10 – 1st trigger: channel 0 is converted and an EOC event is generated – 2nd trigger: channel 3 is converted and an EOC event is generated – 3rd trigger: channel 7 is converted and an EOC event is generated – 4th trigger: channel 10 is converted and both EOC and EOSEQ events are generated. – 5th trigger: channel 0 is converted an EOC event is generated – 6th trigger: channel 3 is converted and an EOC event is generated – ... DISCEN=0, channels to be converted = 0, 3, 7, 10 – 1st trigger: the complete sequence is converted: channel 0, then 3, 7 and 10. Each conversion generates an EOC event and the last one also generates an EOSEQ event. – Any subsequent trigger events will restart the complete sequence. It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. DocID025942 Rev 5 284/874 318 Analog-to-digital converter (ADC) 13.5.2 RM0377 Programmable resolution (RES) - fast conversion mode It is possible to obtain faster conversion times (tSAR) by reducing the ADC resolution. The resolution can be configured to be either 12, 10, 8, or 6 bits by programming the RES[1:0] bits in the ADC_CFGR1 register. Lower resolution allows faster conversion times for applications where high data precision is not required. Note: The RES[1:0] bit must only be changed when the ADEN bit is reset. The result of the conversion is always 12 bits wide and any unused LSB bits are read as zeros. Lower resolution reduces the conversion time needed for the successive approximation steps as shown in Table 58. Table 58. tSAR timings depending on resolution RES[1:0] bits 13.5.3 tSAR (ADC clock cycles) tSAR (ns) at fADC = 16 MHz tSMPL (min) tCONV (ADC clock cycles) (ADC clock cycles) (with min. tSMPL) tCONV (µs) at fADC = 16 MHz 12 12.5 781 ns 1.5 14 875 ns 10 11.5 719 ns 1.5 13 812 ns 8 9.5 594 ns 1.5 11 688 ns 6 7.5 469 ns 1.5 9 562 ns End of conversion, end of sampling phase (EOC, EOSMP flags) The ADC indicates each end of conversion (EOC) event. The ADC sets the EOC flag in the ADC_ISR register as soon as a new conversion data result is available in the ADC_DR register. An interrupt can be generated if the EOCIE bit is set in the ADC_IER register. The EOC flag is cleared by software either by writing 1 to it, or by reading the ADC_DR register. The ADC also indicates the end of sampling phase by setting the EOSMP flag in the ADC_ISR register. The EOSMP flag is cleared by software by writing1 to it. An interrupt can be generated if the EOSMPIE bit is set in the ADC_IER register. The aim of this interrupt is to allow the processing to be synchronized with the conversions. Typically, an analog multiplexer can be accessed in hidden time during the conversion phase, so that the multiplexer is positioned when the next sampling starts. Note: 285/874 As there is only a very short time left between the end of the sampling and the end of the conversion, it is recommenced to use polling or a WFE instruction rather than an interrupt and a WFI instruction. DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) 13.5.4 End of conversion sequence (EOSEQ flag) The ADC notifies the application of each end of sequence (EOSEQ) event. The ADC sets the EOSEQ flag in the ADC_ISR register as soon as the last data result of a conversion sequence is available in the ADC_DR register. An interrupt can be generated if the EOSEQIE bit is set in the ADC_IER register. The EOSEQ flag is cleared by software by writing 1 to it. 13.5.5 Example timing diagrams (single/continuous modes hardware/software triggers) Figure 38. Single conversions of a sequence, software trigger $'67$57 (2& (26(4 6&$1',5 $'&VWDWH 5 '< &+ $'&B'5 E\6: &+ &+ &+ ' ' ' &+ 5'< ' &+ &+ &+ ' ' ' E\+: 5'< ' 069 1. EXTEN=00, CONT=0 2. CHSEL=0x20601, WAIT=0, AUTOFF=0 For code example, refer to A.8.5: Single conversion sequence code example - Software trigger. Figure 39. Continuous conversion of a sequence, software trigger $'67$57 (2& (26(4 $'673 6&$1',5 $'&VWDWH 5'< $'&B'5 E\6: &+ &+ &+ &+ &+ &+ ' ' ' ' ' &+ 673 5'< ' &+ &+ ' E\+: 069 1. EXTEN=00, CONT=1, 2. CHSEL=0x20601, WAIT=0, AUTOFF=0 For code example, refer to A.8.6: Continuous conversion sequence code example Software trigger. DocID025942 Rev 5 286/874 318 Analog-to-digital converter (ADC) RM0377 Figure 40. Single conversions of a sequence, hardware trigger $'67$57 (2& (26(4 75*[ $'&VWDWH 5'< &+ &+ &+ ' ' $'&B'5 E\6: E\+: WULJJHUHG LJQRUHG &+ &+ 5'< ' ' &+ &+ &+ 5'< ' ' ' ' 069 1. EXTSEL=TRGx (over-frequency), EXTEN=01 (rising edge), CONT=0 2. CHSEL=0xF, SCANDIR=0, WAIT=0, AUTOFF=0 For code example, refer to A.8.7: Single conversion sequence code example - Hardware trigger. Figure 41. Continuous conversions of a sequence, hardware trigger $'67$57 (2& (26(4 $'673 75*[ $'&VWDWH 5'< $'&B'5 E\6: E\+: WULJJHUHG LJQRUHG &+ &+ &+ ' ' &+ ' &+ ' &+ ' &+ &+ &+ ' ' ' 6723 5'< 069 1. EXTSEL=TRGx, EXTEN=10 (falling edge), CONT=1 2. CHSEL=0xF, SCANDIR=0, WAIT=0, AUTOFF=0 For code example, refer to A.8.8: Continuous conversion sequence code example Hardware trigger. 287/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) 13.6 Data management 13.6.1 Data register and data alignment (ADC_DR, ALIGN) At the end of each conversion (when an EOC event occurs), the result of the converted data is stored in the ADC_DR data register which is 16-bit wide. The format of the ADC_DR depends on the configured data alignment and resolution. The ALIGN bit in the ADC_CFGR1 register selects the alignment of the data stored after conversion. Data can be right-aligned (ALIGN=0) or left-aligned (ALIGN=1) as shown in Figure 42. Figure 42. Data alignment and resolution (oversampling disabled: OVSE = 0) $/,*1 5(6 [ [ '5>@ '5>@ [ [ [ '5>@ [ [ '5>@ [ '5>@ [ [ [ '5>@ [ [ '5>@ [ [ [ '5>@ [ 069 13.6.2 ADC overrun (OVR, OVRMOD) The overrun flag (OVR) indicates a data overrun event, when the converted data was not read in time by the CPU or the DMA, before the data from a new conversion is available. The OVR flag is set in the ADC_ISR register if the EOC flag is still at ‘1’ at the time when a new conversion completes. An interrupt can be generated if the OVRIE bit is set in the ADC_IER register. When an overrun condition occurs, the ADC keeps operating and can continue to convert unless the software decides to stop and reset the sequence by setting the ADSTP bit in the ADC_CR register. The OVR flag is cleared by software by writing 1 to it. It is possible to configure if the data is preserved or overwritten when an overrun event occurs by programming the OVRMOD bit in the ADC_CFGR1 register: OVRMOD=0 – An overrun event preserves the data register from being overwritten: the old data is maintained and the new conversion is discarded. If OVR remains at 1, further conversions can be performed but the resulting data is discarded. OVRMOD=1 – The data register is overwritten with the last conversion result and the previous unread data is lost. If OVR remains at 1, further conversions can be performed and the ADC_DR register always contains the data from the latest conversion. DocID025942 Rev 5 288/874 318 Analog-to-digital converter (ADC) RM0377 Figure 43. Example of overrun (OVR) $'67$57 (2& (26(4 295 $'673 75*[ $'&VWDWH $'&B'55HDG $FFHVV 5'< &+ &+ &+ &+ &+ &+ 6723 5'< 29(5581 $'&B'5 29502' ' ' ' ' $'&B'5 29502' ' ' ' ' E\6: &+ ' ' E\+: WULJJHUHG 069 13.6.3 Managing a sequence of data converted without using the DMA If the conversions are slow enough, the conversion sequence can be handled by software. In this case the software must use the EOC flag and its associated interrupt to handle each data result. Each time a conversion is complete, the EOC bit is set in the ADC_ISR register and the ADC_DR register can be read. The OVRMOD bit in the ADC_CFGR1 register should be configured to 0 to manage overrun events as an error. 13.6.4 Managing converted data without using the DMA without overrun It may be useful to let the ADC convert one or more channels without reading the data after each conversion. In this case, the OVRMOD bit must be configured at 1 and the OVR flag should be ignored by the software. When OVRMOD=1, an overrun event does not prevent the ADC from continuing to convert and the ADC_DR register always contains the latest conversion data. 13.6.5 Managing converted data using the DMA Since all converted channel values are stored in a single data register, it is efficient to use DMA when converting more than one channel. This avoids losing the conversion data results stored in the ADC_DR register. When DMA mode is enabled (DMAEN bit set to 1 in the ADC_CFGR1 register), a DMA request is generated after the conversion of each channel. This allows the transfer of the converted data from the ADC_DR register to the destination location selected by the software. Note: 289/874 The DMAEN bit in the ADC_CFGR1 register must be set after the ADC calibration phase. DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Despite this, if an overrun occurs (OVR=1) because the DMA could not serve the DMA transfer request in time, the ADC stops generating DMA requests and the data corresponding to the new conversion is not transferred by the DMA. Which means that all the data transferred to the RAM can be considered as valid. Depending on the configuration of OVRMOD bit, the data is either preserved or overwritten (refer to Section 13.6.2: ADC overrun (OVR, OVRMOD) on page 288). The DMA transfer requests are blocked until the software clears the OVR bit. Two different DMA modes are proposed depending on the application use and are configured with bit DMACFG in the ADC_CFGR1 register: DMA one shot mode (DMACFG=0). This mode should be selected when the DMA is programmed to transfer a fixed number of data words. DMA circular mode (DMACFG=1) This mode should be selected when programming the DMA in circular mode or double buffer mode. DMA one shot mode (DMACFG=0) In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available and stops generating DMA requests once the DMA has reached the last DMA transfer (when a DMA_EOT interrupt occurs, see Section 10: Direct memory access controller (DMA) on page 239) even if a conversion has been started again. For code example, refer to A.8.9: DMA one shot mode sequence code example. When the DMA transfer is complete (all the transfers configured in the DMA controller have been done): The content of the ADC data register is frozen. Any ongoing conversion is aborted and its partial result discarded No new DMA request is issued to the DMA controller. This avoids generating an overrun error if there are still conversions which are started. The scan sequence is stopped and reset The DMA is stopped DMA circular mode (DMACFG=1) In this mode, the ADC generates a DMA transfer request each time a new conversion data word is available in the data register, even if the DMA has reached the last DMA transfer. This allows the DMA to be configured in circular mode to handle a continuous analog input data stream. For code example, refer to A.8.10: DMA circular mode sequence code example. DocID025942 Rev 5 290/874 318 Analog-to-digital converter (ADC) RM0377 13.7 Low-power features 13.7.1 Wait mode conversion Wait mode conversion can be used to simplify the software as well as optimizing the performance of applications clocked at low frequency where there might be a risk of ADC overrun occurring. When the WAIT bit is set to 1 in the ADC_CFGR1 register, a new conversion can start only if the previous data has been treated, once the ADC_DR register has been read or if the EOC bit has been cleared. This is a way to automatically adapt the speed of the ADC to the speed of the system that reads the data. Note: Any hardware triggers which occur while a conversion is ongoing or during the wait time preceding the read access are ignored. Figure 44. Wait mode conversion (continuous mode, software trigger) $'67$57 (2& (26(4 $'673 $'&B'55HDGDFFHVV $'&VWDWH 5'< $'&B'5 E\6: &+ &+ '/< ' '/< &+ ' '/< &+ '/< ' 6723 5'< ' E\+: 069 1. EXTEN=00, CONT=1 2. CHSEL=0x3, SCANDIR=0, WAIT=1, AUTOFF=0 For code example, refer to A.8.11: Wait mode sequence code example. 13.7.2 Auto-off mode (AUTOFF) The ADC has an automatic power management feature which is called auto-off mode, and is enabled by setting AUTOFF=1 in the ADC_CFGR1 register. When AUTOFF=1, the ADC is always powered off when not converting and automatically wakes-up when a conversion is started (by software or hardware trigger). A startup-time is automatically inserted between the trigger event which starts the conversion and the sampling time of the ADC. The ADC is then automatically disabled once the sequence of conversions is complete. Auto-off mode can cause a dramatic reduction in the power consumption of applications which need relatively few conversions or when conversion requests are timed far enough apart (for example with a low frequency hardware trigger) to justify the extra power and extra time used for switching the ADC on and off. 291/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Auto-off mode can be combined with the wait mode conversion (WAIT=1) for applications clocked at low frequency. This combination can provide significant power savings if the ADC is automatically powered-off during the wait phase and restarted as soon as the ADC_DR register is read by the application (see Figure 46: Behavior with WAIT=1, AUTOFF=1). Figure 45. Behavior with WAIT=0, AUTOFF=1 75*[ (2& (26(4 $'&B'55HDGDFFHVV 5'< 6WDUWXS $'&VWDWH &+ $'&B'5 E\6: &+ &+ &+ ' ' ' 2)) 6WDUWXS ' E\+: WULJJHUHG 069 1. EXTSEL=TRGx, EXTEN=01 (rising edge), CONT=x, ADSTART=1, CHSEL=0xF, SCANDIR=0, WAIT=1, AUTOFF=1 For code example, refer to A.8.12: Auto off and no wait mode sequence code example. Figure 46. Behavior with WAIT=1, AUTOFF=1 75*[ (2& (26(4 5'< 6WDUWXS &+ '/< 2)) 6WDUWXS &+ ' $'&B'5 E\6: '/< '/< 6WDUWXS ' &+ 2)) 6WDUWXS ' &+ 2)) $'&VWDWH '/< 2)) $'&B'55HDGDFFHVV &+ ' E\+: WULJJHUHG 069 1. EXTSEL=TRGx, EXTEN=01 (rising edge), CONT=x, ADSTART=1, CHSEL=0xF, SCANDIR=0, WAIT=1, AUTOFF=1 For code example, refer to A.8.13: Auto off and wait mode sequence code example. DocID025942 Rev 5 292/874 318 Analog-to-digital converter (ADC) 13.8 RM0377 Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR, AWD) The AWD analog watchdog feature is enabled by setting the AWDEN bit in the ADC_CFGR1 register. It is used to monitor that either one selected channel or all enabled channels (see Table 60: Analog watchdog channel selection) remain within a configured voltage range (window) as shown in Figure 47. The AWD analog watchdog status bit is set if the analog voltage converted by the ADC is below a lower threshold or above a higher threshold. These thresholds are programmed in the 12 least significant bits of the ADC_HTR and ADC_LTR 16-bit registers. An interrupt can be enabled by setting the AWDIE bit in the ADC_IER register. The AWD flag is cleared by software by writing 1 to it. When converting a data with a resolution of less than 12-bit (according to bits DRES[1:0]), the LSB of the programmed thresholds must be kept cleared because the internal comparison is always performed on the full 12-bit raw converted data (left aligned). For code example, refer to A.8.14: Analog watchdog code example. Table 59 describes how the comparison is performed for all the possible resolutions. Table 59. Analog watchdog comparison Resolution bits RES[1:0] Analog Watchdog comparison between: Comments Raw converted data, left aligned(1) Thresholds 00: 12-bit DATA[11:0] LT[11:0] and HT[11:0] - 01: 10-bit DATA[11:2],00 LT[11:0] and HT[11:0] The user must configure LT1[1:0] and HT1[1:0] to “00” 10: 8-bit DATA[11:4],0000 LT[11:0] and HT[11:0] The user must configure LT1[3:0] and HT1[3:0] to “0000” 11: 6-bit DATA[11:6],000000 LT[11:0] and HT[11:0] The user must configure LT1[5:0] and HT1[5:0] to “000000” 1. The watchdog comparison is performed on the raw converted data before any alignment calculation. Table 60 shows how to configure the AWDSGL and AWDEN bits in the ADC_CFGR1 register to enable the analog watchdog on one or more channels. Figure 47. Analog watchdog guarded area $QDORJYROWDJH +LJKHUWKUHVKROG +75 *XDUGHGDUHD /RZHUWKUHVKROG /75 DL 293/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Table 60. Analog watchdog channel selection Channels guarded by the analog watchdog None All channels (1) Single channel AWDSGL bit AWDEN bit x 0 0 1 1 1 1. Selected by the AWDCH[4:0] bits 13.9 Oversampler The oversampling unit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit. It provides a result with the following form, where N and M can be adjusted: 1 Result = ----- M n = N–1 Conversion t n n=0 It allows to perform by hardware the following functions: averaging, data rate reduction, SNR improvement, basic filtering. The oversampling ratio N is defined using the OVFS[2:0] bits in the ADC_CFGR2 register. It can range from 2x to 256x. The division coefficient M consists of a right bit shift up to 8 bits. It is configured through the OVSS[3:0] bits in the ADC_CFGR2 register. For code example, refer to A.8.15: Oversampling code example. The summation unit can yield a result up to 20 bits (256 x 12-bit), which is first shifted right. The upper bits of the result are then truncated, keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the ADC_DR data register. Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated. Figure 48. 20-bit to 16-bit result truncation 5DZELWGDWD 6KLIWLQJ 7UXQFDWLRQ DQGURXQGLQJ 069 DocID025942 Rev 5 294/874 318 Analog-to-digital converter (ADC) RM0377 The Figure 49 gives a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 49. Numerical example with 5-bits shift and rounding 5DZELWGDWD % )LQDOUHVXOWDIWHUELWVVKLIW DQGURXQGLQJWRQHDUHVW ' ' % ) 069 The Table 61 below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF. Table 61. Maximum output results vs N and M. Grayed values indicates truncation No-shift Oversa Max mpling OVSS = Raw data ratio 0000 1-bit shift 2-bit shift 3-bit shift 4-bit shift 5-bit shift 6-bit shift 7-bit shift 8-bit shift OVSS = 0001 OVSS = 0010 OVSS = 0011 OVSS = 0100 OVSS = 0101 OVSS = 0110 OVSS = OVSS = 0111 1000 2x 0x1FFE 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 4x 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 8x 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 0x0080 16x 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 0x0100 32x 0x1FFE0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 0x0200 64x 0x3FFC0 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 0x0400 128x 0x7FF80 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x0800 256x 0xFFF00 0xFF00 0xFF80 0xFFC0 0xFFE0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF The conversion timings in oversampled mode do not change compared to standard conversion mode: the sample time is maintained equal during the whole oversampling sequence. New data are provided every N conversion, with an equivalent delay equal to N x tADC = N x (tSMPL + tSAR). The flags features are raised as following: 295/874 the end of the sampling phase (EOSMP) is set after each sampling phase the end of conversion (EOC) occurs once every N conversions, when the oversampled result is available the end of sequence (EOCSEQ) occurs once the sequence of oversampled data is completed (i.e. after N x sequence length conversions total) DocID025942 Rev 5 RM0377 13.9.1 Analog-to-digital converter (ADC) ADC operating modes support when oversampling In oversampling mode, most of the ADC operating modes are available: Single or continuous mode conversions, forward or backward scanned sequences ADC conversions start either by software or with triggers ADC stop during a conversion (abort) Data read via CPU or DMA with overrun detection Low-power modes (WAIT, AUTOFF) Programmable resolution: in this case, the reduced conversion values (as per RES[1:0] bits in ADC_CFGR1 register) are accumulated, truncated, rounded and shifted in the same way as 12-bit conversions are Note: The alignment mode is not available when working with oversampled data. The ALIGN bit in ADC_CFGR1 is ignored and the data are always provided right-aligned. 13.9.2 Analog watchdog The analog watchdog functionality is available (AWDSGL and AWDEN bits), with the following difference: the RES[1:0] bits are ignored, comparison is always done on using the full 12-bits values HT[11:0] and LT[11:0] the comparison is performed on the most significant 12 bits of the 16 bits oversampled results ADC_DR[15:4] Note: Care must be taken when using high shifting values. This reduces the comparison range. For instance, if the oversampled result is shifted by 4 bits thus yielding a 12-bit data rightaligned, the affective analog watchdog comparison can only be performed on 8 bits. The comparison is done between ADC_DR[11:4] and HT[0:7] / LT[[0:7], and HT[11:8] / LT[11:8] must be kept reset. 13.9.3 Triggered mode The averager can also be used for basic filtering purposes. Although not a very efficient filter (slow roll-off and limited stop band attenuation), it can be used as a notch filter to reject constant parasitic frequencies (typically coming from the mains or from a switched mode power supply). For this purpose, a specific discontinuous mode can be enabled with TOVS bit in ADC_CFGR2, to be able to have an oversampling frequency defined by a user and independent from the conversion time itself. Figure 50 below shows how conversions are started in response to triggers in discontinuous mode. If the TOVS bit is set, the content of the DISCEN bit is ignored and considered as 1. DocID025942 Rev 5 296/874 318 Analog-to-digital converter (ADC) RM0377 Figure 50. Triggered oversampling mode (TOVS bit = 1) 7ULJJHU &217 ',6&(1 7296 7ULJJHU &K1 &K1 &K1 &K1 &K1 &K1 &K1 &K1 (2&IODJVHW 7ULJJHU 7ULJJHU 7ULJJHU &217 ',6&(1 7296 &K1 &K1 &K1 7ULJJHU 7ULJJHU 7ULJJHU 7ULJJHU &K1 &K1 &K1 &K1 (2&IODJVHW ',6&(1 ',6&(1ELWLVIRUFHGWRE\VRIWZDUHZKHQ7296ELWLVVHW 069 13.10 Temperature sensor and internal reference voltage The temperature sensor can be used to measure the junction temperature (TJ) of the device. The temperature sensor is internally connected to the ADC_IN18 input channel which is used to convert the sensor’s output voltage to a digital value. The sampling time for the temperature sensor analog pin must be greater than the minimum TS_temp value specified in the datasheet. When not in use, the sensor can be put in power down mode. The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode. Figure 51 shows the block diagram of connections between the temperature sensor, the internal voltage reference and the ADC. The TSEN bit must be set to enable the conversion of ADC_IN18 (temperature sensor) and the VREFEN bit must be set to enable the conversion of ADC_IN17 (VREFINT). The temperature sensor output voltage changes linearly with temperature. The offset of this line varies from chip to chip due to process variation (up to 45 °C from one chip to another). The uncalibrated internal temperature sensor is more suited for applications that detect temperature variations instead of absolute temperatures. To improve the accuracy of the temperature sensor measurement, calibration values are stored in system memory for each device by ST during production. During the manufacturing process, the calibration data of the temperature sensor and the internal voltage reference are stored in the system memory area. The user application can then read them and use them to improve the accuracy of the temperature sensor or the internal reference. Refer to the datasheet for additional information. 297/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Main features Supported temperature range: –40 to 125 °C Linearity: ±2 °C max., precision depending on calibration Figure 51. Temperature sensor and VREFINT channel block diagram 96(16( 7HPSHUDWXUH VHQVRU $'&B,1 FRQYHUWHG GDWD $'& 95(),17 ,QWHUQDO SRZHUEORFN $'&B,1 $GGUHVVGDWDEXV 76(1FRQWUROELW 95()(1FRQWUROELW 069 Reading the temperature 1. Select the ADC_IN18 input channel 2. Select an appropriate sampling time specified in the device datasheet (TS_temp). 3. Set the TSEN bit in the ADC_CCR register to wake up the temperature sensor from power down mode and wait for its stabilization time (tSTART) For code example, refer to A.8.16: Temperature configuration code example. 4. Start the ADC conversion by setting the ADSTART bit in the ADC_CR register (or by external trigger) 5. Read the resulting VSENSE data in the ADC_DR register 6. Calculate the temperature using the following formula: 130 °C – 30 °C Temperature in °C = ---------------------------------------------------------- TS_DATA – TS_CAL1 + 30 °C TS_CAL2 – TS_CAL1 V 30 – V SENSE Temperature in °C = ------------------------------------ + 30 °C Avg_Slope Where: TS_CAL2 is the temperature sensor calibration value acquired at 130°C TS_CAL1 is the temperature sensor calibration value acquired at 30°C TS_DATA is the actual temperature sensor output value converted by ADC Refer to the specific device datasheet for more information about TS_CAL1 and TS_CAL2 calibration points. For code example, refer to A.8.17: Temperature computation code example. Note: The sensor has a startup time after waking from power down mode before it can output VSENSE at the correct level. The ADC also has a startup time after power-on, so to minimize the delay, the ADEN and TSEN bits should be set at the same time. DocID025942 Rev 5 298/874 318 Analog-to-digital converter (ADC) RM0377 Calculating the actual VDDA voltage using the internal reference voltage The VDDA power supply voltage applied to the microcontroller may be subject to variation or not precisely known. The embedded internal voltage reference (VREFINT) and its calibration data acquired by the ADC during the manufacturing process at VDDA = 3 V can be used to evaluate the actual VDDA voltage level. The following formula gives the actual VDDA voltage supplying the device: VDDA = 3 V x VREFINT_CAL / VREFINT_DATA Where: VREFINT_CAL is the VREFINT calibration value VREFINT_DATA is the actual VREFINT output value converted by ADC Converting a supply-relative ADC measurement to an absolute voltage value The ADC is designed to deliver a digital value corresponding to the ratio between the analog power supply and the voltage applied on the converted channel. For most application use cases, it is necessary to convert this ratio into a voltage independent of VDDA. For applications where VDDA is known and ADC converted values are right-aligned you can use the following formula to get this absolute value: V DDA V CHANNELx = ------------------------------------- ADC_DATA x FULL_SCALE For applications where VDDA value is not known, you must use the internal voltage reference and VDDA can be replaced by the expression provided in the section Calculating the actual VDDA voltage using the internal reference voltage, resulting in the following formula: 3 V VREFINT_CAL ADC_DATA x V CHANNELx = -----------------------------------------------------------------------------------------------VREFINT_DATA FULL_SCALE Where: Note: 299/874 VREFINT_CAL is the VREFINT calibration value ADC_DATAx is the value measured by the ADC on channel x (right-aligned) VREFINT_DATA is the actual VREFINT output value converted by the ADC full_SCALE is the maximum digital value of the ADC output. For example with 12-bit resolution, it will be 212 - 1 = 4095 or with 8-bit resolution, 28 - 1 = 255. If ADC measurements are done using an output format other than 12 bit right-aligned, all the parameters must first be converted to a compatible format before the calculation is done. DocID025942 Rev 5 RM0377 13.11 Analog-to-digital converter (ADC) ADC interrupts An interrupt can be generated by any of the following events: End Of Calibration (EOCAL flag) ADC power-up, when the ADC is ready (ADRDY flag) End of any conversion (EOC flag) End of a sequence of conversions (EOSEQ flag) When an analog watchdog detection occurs (AWD flag) When the end of sampling phase occurs (EOSMP flag) when a data overrun occurs (OVR flag) Separate interrupt enable bits are available for flexibility. Table 62. ADC interrupts Interrupt event Event flag Enable control bit End Of Calibration EOCAL EOCALIE ADC ready ADRDY ADRDYIE EOC EOCIE End of sequence of conversions EOSEQ EOSEQIE Analog watchdog status bit is set AWD AWDIE EOSMP EOSMPIE OVR OVRIE End of conversion End of sampling phase Overrun DocID025942 Rev 5 300/874 318 Analog-to-digital converter (ADC) 13.12 RM0377 ADC registers Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions. 13.12.1 ADC interrupt and status register (ADC_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. EOCAL Res. Res. Res. AWD Res. Res. OVR EOSEQ EOC r_w1 r_w1 rc_w1 r_w1 r_w1 EOSMP ADRDY r_w1 r_w1 Bits 31:12 Reserved, must be kept at reset value. Bit 11 EOCAL: End Of Calibration flag This bit is set by hardware when calibration is complete. It is cleared by software writing 1 to it. 0: Calibration is not complete 1: Calibration is complete Bit 10:8 Reserved, must be kept at reset value. Bit 7 AWD: Analog watchdog flag This bit is set by hardware when the converted voltage crosses the values programmed in the ADC_LTR and ADC_HTR registers. It is cleared by software writing 1 to it. 0: No analog watchdog event occurred (or the flag event was already acknowledged and cleared by software) 1: Analog watchdog event occurred Bit 6:5 Reserved, must be kept at reset value. Bit 4 OVR: ADC overrun This bit is set by hardware when an overrun occurs, meaning that a new conversion has complete while the EOC flag was already set. It is cleared by software writing 1 to it. 0: No overrun occurred (or the flag event was already acknowledged and cleared by software) 1: Overrun has occurred Bit 3 EOSEQ: End of sequence flag This bit is set by hardware at the end of the conversion of a sequence of channels selected by the CHSEL bits. It is cleared by software writing 1 to it. 0: Conversion sequence not complete (or the flag event was already acknowledged and cleared by software) 1: Conversion sequence complete 301/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Bit 2 EOC: End of conversion flag This bit is set by hardware at the end of each conversion of a channel when a new data result is available in the ADC_DR register. It is cleared by software writing 1 to it or by reading the ADC_DR register. 0: Channel conversion not complete (or the flag event was already acknowledged and cleared by software) 1: Channel conversion complete Bit 1 EOSMP: End of sampling flag This bit is set by hardware during the conversion, at the end of the sampling phase.It is cleared by software by programming it to ‘1’. 0: Not at the end of the sampling phase (or the flag event was already acknowledged and cleared by software) 1: End of sampling phase reached Bit 0 ADRDY: ADC ready This bit is set by hardware after the ADC has been enabled (bit ADEN=1) and when the ADC reaches a state where it is ready to accept conversion requests. It is cleared by software writing 1 to it. 0: ADC not yet ready to start conversion (or the flag event was already acknowledged and cleared by software) 1: ADC is ready to start conversion 13.12.2 ADC interrupt enable register (ADC_IER) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. EOCAL IE Res. Res. Res. Res. Res. Res. rw AWDIE Res. rw Res. EOSEQ EOSMP ADRDY OVRIE EOCIE IE IE IE rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bit 11 EOCALIE: End of calibration interrupt enable This bit is set and cleared by software to enable/disable the end of calibration interrupt. 0: End of calibration interrupt disabled 1: End of calibration interrupt enabled Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 10:8 Reserved, must be kept at reset value. DocID025942 Rev 5 302/874 318 Analog-to-digital converter (ADC) RM0377 Bit 7 AWDIE: Analog watchdog interrupt enable This bit is set and cleared by software to enable/disable the analog watchdog interrupt. 0: Analog watchdog interrupt disabled 1: Analog watchdog interrupt enabled Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 6:5 Reserved, must be kept at reset value. Bit 4 OVRIE: Overrun interrupt enable This bit is set and cleared by software to enable/disable the overrun interrupt. 0: Overrun interrupt disabled 1: Overrun interrupt enabled. An interrupt is generated when the OVR bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 3 EOSEQIE: End of conversion sequence interrupt enable This bit is set and cleared by software to enable/disable the end of sequence of conversions interrupt. 0: EOSEQ interrupt disabled 1: EOSEQ interrupt enabled. An interrupt is generated when the EOSEQ bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 2 EOCIE: End of conversion interrupt enable This bit is set and cleared by software to enable/disable the end of conversion interrupt. 0: EOC interrupt disabled 1: EOC interrupt enabled. An interrupt is generated when the EOC bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 1 EOSMPIE: End of sampling flag interrupt enable This bit is set and cleared by software to enable/disable the end of the sampling phase interrupt. 0: EOSMP interrupt disabled. 1: EOSMP interrupt enabled. An interrupt is generated when the EOSMP bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 0 ADRDYIE: ADC ready interrupt enable This bit is set and cleared by software to enable/disable the ADC Ready interrupt. 0: ADRDY interrupt disabled. 1: ADRDY interrupt enabled. An interrupt is generated when the ADRDY bit is set. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 303/874 DocID025942 Rev 5 RM0377 13.12.3 Analog-to-digital converter (ADC) ADC control register (ADC_CR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. ADVR EGEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. ADSTP Res. ADSTA RT ADDIS ADEN rs rs rs ADCAL rs rw rs Bit 31 ADCAL: ADC calibration This bit is set by software to start the calibration of the ADC. It is cleared by hardware after calibration is complete. 0: Calibration complete 1: Write 1 to calibrate the ADC. Read at 1 means that a calibration is in progress. Note: Software is allowed to set ADCAL only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Note: Software is allowed to update the calibration factor by writing ADC_CALFACT only when ADEN=1 and ADSTART=0 (ADC enabled and no conversion is ongoing). Bits 30:29 Reserved, must be kept at reset value. Bits 28 ADVREGEN: ADC Voltage Regulator Enable This bit is set: - by software to enable the ADC internal voltage regulator. - by hardware when launching the calibration (setting ADCAL=1) or when enabling the ADC (setting ADEN=1) It is cleared by software to disable the voltage regulator (it can be cleared only if ADEN=0). 0: ADC voltage regulator disabled 1: ADC voltage regulator enabled Note: The software can program this bit field only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bits 27:5 Reserved, must be kept at reset value. Bit 4 ADSTP: ADC stop conversion command This bit is set by software to stop and discard an ongoing conversion (ADSTP Command). It is cleared by hardware when the conversion is effectively discarded and the ADC is ready to accept a new start conversion command. 0: No ADC stop conversion command ongoing 1: Write 1 to stop the ADC. Read 1 means that an ADSTP command is in progress. Note: Software is allowed to set ADSTP only when ADSTART=1 and ADDIS=0 (ADC is enabled and may be converting and there is no pending request to disable the ADC) Bit 3 Reserved, must be kept at reset value. DocID025942 Rev 5 304/874 318 Analog-to-digital converter (ADC) RM0377 Bit 2 ADSTART: ADC start conversion command This bit is set by software to start ADC conversion. Depending on the EXTEN [1:0] configuration bits, a conversion either starts immediately (software trigger configuration) or once a hardware trigger event occurs (hardware trigger configuration). It is cleared by hardware: – In single conversion mode (CONT=0, DISCEN=0), when software trigger is selected (EXTEN=00): at the assertion of the end of Conversion Sequence (EOSEQ) flag. – In discontinuous conversion mode(CONT=0, DISCEN=1), when the software trigger is selected (EXTEN=00): at the assertion of the end of Conversion (EOC) flag. – In all other cases: after the execution of the ADSTP command, at the same time as the ADSTP bit is cleared by hardware. 0: No ADC conversion is ongoing. 1: Write 1 to start the ADC. Read 1 means that the ADC is operating and may be converting. Note: Software is allowed to set ADSTART only when ADEN=1 and ADDIS=0 (ADC is enabled and there is no pending request to disable the ADC) Bit 1 ADDIS: ADC disable command This bit is set by software to disable the ADC (ADDIS command) and put it into power-down state (OFF state). It is cleared by hardware once the ADC is effectively disabled (ADEN is also cleared by hardware at this time). 0: No ADDIS command ongoing 1: Write 1 to disable the ADC. Read 1 means that an ADDIS command is in progress. Note: Software is allowed to set ADDIS only when ADEN=1 and ADSTART=0 (which ensures that no conversion is ongoing) Bit 0 ADEN: ADC enable command This bit is set by software to enable the ADC. The ADC will be effectively ready to operate once the ADRDY flag has been set. It is cleared by hardware when the ADC is disabled, after the execution of the ADDIS command. 0: ADC is disabled (OFF state) 1: Write 1 to enable the ADC. Note: Software is allowed to set ADEN only when all bits of ADC_CR registers are 0 (ADCAL=0, ADSTP=0, ADSTART=0, ADDIS=0 and ADEN=0) 305/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) 13.12.4 ADC configuration register 1 (ADC_CFGR1) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 Res. 15 28 26 AWDCH[4:0] rw rw rw rw rw 14 13 12 11 10 AUTOFF WAIT CONT OVRMOD rw 27 rw rw rw EXTEN[1:0] 25 24 Res. Res. 9 8 Res. 23 22 AWDEN AWDSGL rw rw 7 6 21 20 19 18 17 16 Res. Res. Res. Res. Res. DISCEN 5 4 3 2 1 rw EXTSEL[2:0] ALIGN RES[1:0] rw rw rw rw SCAND DMAC IR FG rw rw 0 DMAEN rw Bit 31 Reserved, must be kept at reset value. Bits 30:26 AWDCH[4:0]: Analog watchdog channel selection These bits are set and cleared by software. They select the input channel to be guarded by the analog watchdog. 00000: ADC analog input Channel 0 monitored by AWD 00001: ADC analog input Channel 1 monitored by AWD ..... 10010: ADC analog input Channel 18 monitored by AWD other values: Reserved, must not be used Note: The channel selected by the AWDCH[4:0] bits must be also set into the CHSELR register Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 25:24 Reserved, must be kept at reset value. Bit 23 AWDEN: Analog watchdog enable This bit is set and cleared by software. 0: Analog watchdog disabled 1: Analog watchdog enabled Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 22 AWDSGL: Enable the watchdog on a single channel or on all channels This bit is set and cleared by software to enable the analog watchdog on the channel identified by the AWDCH[4:0] bits or on all the channels 0: Analog watchdog enabled on all channels 1: Analog watchdog enabled on a single channel Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 21:17 Reserved, must be kept at reset value. DocID025942 Rev 5 306/874 318 Analog-to-digital converter (ADC) RM0377 Bit 16 DISCEN: Discontinuous mode This bit is set and cleared by software to enable/disable discontinuous mode. 0: Discontinuous mode disabled 1: Discontinuous mode enabled Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 15 AUTOFF: Auto-off mode This bit is set and cleared by software to enable/disable auto-off mode.. 0: Auto-off mode disabled 1: Auto-off mode enabled Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 14 WAIT: Wait conversion mode This bit is set and cleared by software to enable/disable wait conversion mode.. 0: Wait conversion mode off 1: Wait conversion mode on Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 13 CONT: Single / continuous conversion mode This bit is set and cleared by software. If it is set, conversion takes place continuously until it is cleared. 0: Single conversion mode 1: Continuous conversion mode Note: It is not possible to have both discontinuous mode and continuous mode enabled: it is forbidden to set both bits DISCEN=1 and CONT=1. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 12 OVRMOD: Overrun management mode This bit is set and cleared by software and configure the way data overruns are managed. 0: ADC_DR register is preserved with the old data when an overrun is detected. 1: ADC_DR register is overwritten with the last conversion result when an overrun is detected. Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 11:10 EXTEN[1:0]: External trigger enable and polarity selection These bits are set and cleared by software to select the external trigger polarity and enable the trigger. 00: Hardware trigger detection disabled (conversions can be started by software) 01: Hardware trigger detection on the rising edge 10: Hardware trigger detection on the falling edge 11: Hardware trigger detection on both the rising and falling edges Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 9 Reserved, must be kept at reset value. 307/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Bits 8:6 EXTSEL[2:0]: External trigger selection These bits select the external event used to trigger the start of conversion (refer to Table 57: External triggers for details): 000: TRG0 001: TRG1 010: TRG2 011: TRG3 100: TRG4 101: TRG5 110: TRG6 111: TRG7 Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 5 ALIGN: Data alignment This bit is set and cleared by software to select right or left alignment. Refer to Figure 42: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 288 0: Right alignment 1: Left alignment Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 4:3 RES[1:0]: Data resolution These bits are written by software to select the resolution of the conversion. 00: 12 bits 01: 10 bits 10: 8 bits 11: 6 bits Note: Software is allowed to write these bits only when ADEN=0. DocID025942 Rev 5 308/874 318 Analog-to-digital converter (ADC) RM0377 Bit 2 SCANDIR: Scan sequence direction This bit is set and cleared by software to select the direction in which the channels will be scanned in the sequence. 0: Upward scan (from CHSEL0 to CHSEL18) 1: Backward scan (from CHSEL18 to CHSEL0) Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 1 DMACFG: Direct memory access configuration This bit is set and cleared by software to select between two DMA modes of operation and is effective only when DMAEN=1. 0: DMA one shot mode selected 1: DMA circular mode selected For more details, refer to Section 13.6.5: Managing converted data using the DMA on page 289 Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 0 DMAEN: Direct memory access enable This bit is set and cleared by software to enable the generation of DMA requests. This allows to use the DMA controller to manage automatically the converted data. For more details, refer to Section 13.6.5: Managing converted data using the DMA on page 289. 0: DMA disabled 1: DMA enabled Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 309/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) 13.12.5 ADC configuration register 2 (ADC_CFGR2) Address offset: 0x10 Reset value: 0x0000 0000 31 30 CKMODE[1:0] 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 Res. OVSE rw rw 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. TOVS rw OVSS[3:0] rw rw rw OVSR[2:0] rw rw rw rw rw Bits 31:30 CKMODE[1:0]: ADC clock mode These bits are set and cleared by software to define how the analog ADC is clocked: 00: ADCCLK (Asynchronous clock mode), generated at product level (refer to RCC section) 01: PCLK/2 (Synchronous clock mode) 10: PCLK/4 (Synchronous clock mode) 11: PCLK (Synchronous clock mode). This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) In all synchronous clock modes, there is no jitter in the delay from a timer trigger to the start of a conversion. Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bits 29:10 Reserved, must be kept at reset value. Bits 9 TOVS: Triggered Oversampling This bit is set and cleared by software. 0: All oversampled conversions for a channel are done consecutively after a trigger 1: Each oversampled conversion for a channel needs a trigger Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 8:5 OVSS[3:0]: Oversampling shift This bit is set and cleared by software. 0000: No shift 0001: Shift 1-bit 0010: Shift 2-bits 0011: Shift 3-bits 0100: Shift 4-bits 0101: Shift 5-bits 0110: Shift 6-bits 0111: Shift 7-bits 1000: Shift 8-bits Other codes reserved Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). DocID025942 Rev 5 310/874 318 Analog-to-digital converter (ADC) RM0377 Bits 4:2 OVSR[2:0]: Oversampling ratio This bit filed defines the number of oversampling ratio. 000: 2x 001: 4x 010: 8x 011: 16x 100: 32x 101: 64x 110: 128x 111: 256x Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 1 Reserved, must be kept at reset value. Bit 0 OVSE: Oversampler Enable This bit is set and cleared by software. 0: Oversampler disabled 1: Oversampler enabled Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 13.12.6 ADC sampling time register (ADC_SMPR) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. SMP[2:0] rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 SMP[2:0]: Sampling time selection These bits are written by software to select the sampling time that applies to all channels. 000: 1.5 ADC clock cycles 001: 3.5 ADC clock cycles 010: 7.5 ADC clock cycles 011: 12.5 ADC clock cycles 100: 19.5 ADC clock cycles 101: 39.5 ADC clock cycles 110: 79.5 ADC clock cycles 111: 160.5 ADC clock cycles Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). 311/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) 13.12.7 ADC watchdog threshold register (ADC_TR) Address offset: 0x20 Reset value: 0x0FFF 0000 31 30 29 28 Res. Res. Res. Res. 15 14 13 12 Res. Res. Res. Res. 27 25 24 23 22 21 20 19 18 17 16 HT[11:0] rw rw rw rw rw rw rw rw rw rw rw rw 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw LT[11:0] rw Bits 31:28 26 rw rw rw rw rw Reserved, must be kept at reset value. Bit 27:16 HT[11:0]: Analog watchdog higher threshold These bits are written by software to define the higher threshold for the analog watchdog. Refer to Section 13.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR, AWD) on page 293 Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 15:12 Reserved, must be kept at reset value. Bit 11:0 LT[11:0]: Analog watchdog lower threshold These bits are written by software to define the lower threshold for the analog watchdog. Refer to Section 13.8: Analog window watchdog (AWDEN, AWDSGL, AWDCH, AWD_HTR/LTR, AWD) on page 293 Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). DocID025942 Rev 5 312/874 318 Analog-to-digital converter (ADC) 13.12.8 RM0377 ADC channel selection register (ADC_CHSELR) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 18 17 16 CHSEL CHSEL CHSEL 18 17 16 rw rw rw 2 1 0 CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL CHSEL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw Bits 31:19 Reserved, must be kept at reset value. Bits 18:0 CHSELx: Channel-x selection These bits are written by software and define which channels are part of the sequence of channels to be converted. 0: Input Channel-x is not selected for conversion 1: Input Channel-x is selected for conversion Note: Software is allowed to write these bits only when ADSTART=0 (which ensures that no conversion is ongoing). 13.12.9 ADC data register (ADC_DR) Address offset: 0x40 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r DATA[15:0] r r r r r r r r r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 DATA[15:0]: Converted data These bits are read-only. They contain the conversion result from the last converted channel. The data are left- or right-aligned as shown in Figure 42: Data alignment and resolution (oversampling disabled: OVSE = 0) on page 288. Just after a calibration is complete, DATA[6:0] contains the calibration factor. 313/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) 13.12.10 ADC Calibration factor (ADC_CALFACT) Address offset: 0xB4 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw CALFACT[6:0] rw rw rw rw Bits 31:7 Reserved, must be kept at reset value. Bits 6:0 CALFACT[6:0]: Calibration factor These bits are written by hardware or by software. – Once a single-ended inputs calibration is complete, they are updated by hardware with the calibration factors. – Software can write these bits with a new calibration factor. If the new calibration factor is different from the current one stored into the analog ADC, it will then be applied once a new single-ended calibration is launched. – Just after a calibration is complete, DATA[6:0] contains the calibration factor. Note: Software is allowed to write these bits only when ADEN=1 and ADSTART=0 (ADC is enabled and no calibration is ongoing and no conversion is ongoing). DocID025942 Rev 5 314/874 318 Analog-to-digital converter (ADC) RM0377 13.12.11 ADC common configuration register (ADC_CCR) Address offset: 0x308 Reset value: 0x0000 0000 31 30 29 28 27 26 25 LFMEN 24 23 22 Res. TS EN VREF EN 21 20 19 18 PRESC[3:0] 17 16 Res. Res. Res. Res. Res. Res. Res. Res. rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. rw Bits 31:26 Reserved, must be kept at reset value. Bit 25 LFMEN: Low Frequency Mode enable This bit is set and cleared by software to enable/disable the Low Frequency Mode. It is mandatory to enable this mode the user selects an ADC clock frequency lower than 3.5 MHz 0: Low Frequency Mode disabled 1: Low Frequency Mode enabled Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bit 24 Reserved, must be kept at reset value. Bit 23 TSEN: Temperature sensor enable This bit is set and cleared by software to enable/disable the temperature sensor. 0: Temperature sensor disabled 1: Temperature sensor enabled Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). 315/874 DocID025942 Rev 5 RM0377 Analog-to-digital converter (ADC) Bit 22 VREFEN: VREFINT enable This bit is set and cleared by software to enable/disable the VREFINT. 0: VREFINT disabled 1: VREFINT enabled Note: Software is allowed to write this bit only when ADSTART=0 (which ensures that no conversion is ongoing). Bits 21:18 PRESC[3:0]: ADC prescaler Set and cleared by software to select the frequency of the clock to the ADC. The clock is common for all the ADCs. 0000: input ADC clock not divided 0001: input ADC clock divided by 2 0010: input ADC clock divided by 4 0011: input ADC clock divided by 6 0100: input ADC clock divided by 8 0101: input ADC clock divided by 10 0110: input ADC clock divided by 12 0111: input ADC clock divided by 16 1000: input ADC clock divided by 32 1001: input ADC clock divided by 64 1010: input ADC clock divided by 128 1011: input ADC clock divided by 256 other: reserved Note: Software is allowed to write these bits only when the ADC is disabled (ADCAL=0, ADSTART=0, ADSTP=0, ADDIS=0 and ADEN=0). Bits 17:0 Reserved, must be kept at reset value. DocID025942 Rev 5 316/874 318 0xB4 0xB8 ... 0x304 317/874 ADC_CALFACT Reserved Reset value Reserved DocID025942 Rev 5 CHSEL14 CHSEL13 Reset value Reserved 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CHSEL10 CHSEL9 CHSEL8 CHSEL7 0 0 0 0 0 Res. 0 Res. 0 Res. 0 Res. 0 Res. TOVS Res. EXTEN[1:0] OVRMOD 0 Res. 0 Res. Res. CONT 0 Res. WAIT 0 Res. Res. AUTOFF 0 Res. Res. Res. Res. Res. Res. DISCEN 0 0 0 0 0 0 0 Reserved DATA[15:0] CHSEL0 0 CHSEL11 1 Reserved CHSEL12 Res. Res. Res. Reserved Reserved Res. Res. Res. Res. Res. 0 CHSEL1 0 Res. CHSEL15 Res. Res. Res. 0 CHSEL2 0 Res. CHSEL16 Res. Res. Res. EXTSEL [2:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ALIGN 0 0 0 OVSS [3:0] 0 OVSR [2:0] 0 DMAEN 0 0 0 0 OVSE RES [1:0] DMACFG EOSMPIE ADRDYIE 0 0 ADEN EOCIE 0 ADDIS 0 Res. EOSEQIE 0 ADSTART 0 Res. Res. Res. AWDIE Res. Res. Res. EOCALIE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EOSEQ EOC EOSMP ADRDY Res. Res. AWD Res. Res. Res. Res. EOCAL. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. OVR 0 SCANDIR 0 OVRIE ADSTP Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 CHSEL3 0 Res. 1 CHSEL17 Res. Res. Res. Res. AWDSGL Reset value CHSEL4 0 Res. 1 CHSEL18 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 CHSEL5 0 Res. 1 Res. Res. Res. Res. AWDEN Res. ADVREGEN Res. Res. Reset value CHSEL6 0 Res. Reserved 0 Res. 0 Res. 1 Res. HT[11:0] Res. Reserved Res. Res. Res. Res. Res. 1 Res. Reset value Reserved Reserved Res. Res. Res. Res. Res. 1 Res. Res. Res. 0 Res. Res. Res. Res. Res. 0 Res. Res. 1 Res. Res. Res. 0 Res. 1 Res. Res. Res. Res. Res. Res. Res. AWDCH[4:0] Res. 1 Res. Res. Res. Res. Res. ADC_CFGR1 Res. 1 Res. Reset value 1 Res. Res. Res. 0 Res. ADCAL 0 Res. Res. Res. Res. CKMODE[1:0] Reset value Res. ADC_DR Res. Res. ADC_CR Res. 0x44 ... 0xB0 Reset value Reserved 0 Res. 0x40 ADC_CHSELR 0 Res. 0x2C 0x30 0x34 0x38 0x3C 0 0 Res. 0x28 0 Res. 0x24 ADC_TR 0 Res. 0x20 Reset value ADC_SMPR Res. Reset value Res. 0x18 0x1C Res. 0x14 ADC_CFGR2 Res. 0x10 Res. 0x0C Res. 0x08 ADC_IER Res. 0x04 ADC_ISR Res. 0x00 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. Offset Res. Analog-to-digital converter (ADC) RM0377 13.12.12 ADC register map The following table summarizes the ADC registers. Table 63. ADC register map and reset values 0 0 0 0 0 0 0 0 0 0 SMP [2:0] 0 0 0 LT[11:0] CALFACT[6:0] 0 0 0 RM0377 Analog-to-digital converter (ADC) 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 Res. 0 PRESC[3:0] VREFEN Res. Res. Res. LFMEN 0 TSEN Reset value Res. ADC_CCR Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x308 Register Res. Offset Res. Table 63. ADC register map and reset values (continued) 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. DocID025942 Rev 5 318/874 318 Comparator (COMP) RM0377 14 Comparator (COMP) 14.1 Introduction STM32L0x1 devices embed two ultra-low power comparators COMP1, and COMP2 that can be used either as standalone devices (all terminal are available on I/Os) or combined with the timers. The comparators can be used for a variety of functions including: 14.2 Wake-up from low-power mode triggered by an analog signal, Analog signal conditioning, Cycle-by-cycle current control loop when combined with a PWM output from a timer. COMP main features COMP1 comparator with ultra low consumption COMP2 comparator with rail-to-rail inputs, fast or slow mode Each comparator has positive and configurable negative inputs used for flexible voltage selection: – I/O pins – Internal reference voltage and three submultiple values (1/4, 1/2, 3/4) provided by scaler (buffered voltage divider) Programmable speed / consumption (COMP2 only) The outputs can be redirected to an I/O or to timer inputs for triggering: – 319/874 Capture events COMP1, and COMP2 can be combined in a window comparator. Each comparator has interrupt generation capability with wake-up from Sleep and Stop modes (through the EXTI controller) DocID025942 Rev 5 RM0377 Comparator (COMP) 14.3 COMP functional description 14.3.1 COMP block diagram The block diagram of the comparators is shown in Figure 52: Comparator 1 and 2 block diagrams. Figure 52. Comparator 1 and 2 block diagrams &203,116(/ &203 95(),17 3$ 3$ 3$ 3$ &20332/$5,7< &203:0 &203,136(/ &203 &203,116(/ 95(),17 3$ 3$ 3$ ó95(),17 ò95(),17 ô95(),17 3% 3$ 3$ 3% 3% 3% 3% &20332/$5,7< :DNHXS (;7,OLQH *3,2[ &2039$/8( 7,0B(75 7,0B&+ 7,0B(75 7,0B&+ 7,0B(75 7,0B&+ /37,0B(75 /37,0B&+ :DNHXS (;7,OLQH *3,2[ &2039$/8( 7,0B(75 7,0B&+ 7,0B(75 7,0B&+ 7,0B(75 7,0B&+ /37,0B(75 /37,0B&+ 06Y9 1. Available on category 1 devices only. 14.3.2 COMP pins and internal signals The I/Os used as comparators inputs must be configured in analog mode in the GPIOs registers. The comparator output can be connected to the I/Os using the alternate function channel given in “Alternate function mapping” table in the datasheet. The output can also be internally redirected to a variety of timer input for the following purposes: Input capture for timing measures It is possible to have the comparator output simultaneously redirected internally and externally. DocID025942 Rev 5 320/874 325 Comparator (COMP) 14.3.3 RM0377 COMP reset and clocks The COMP clock provided by the clock controller is synchronous with the PCLK (APB clock). There is no clock enable control bit provided in the RCC controller. Reset and clock enable bits are common for COMP and SYSCFG. Note: Important: The polarity selection logic and the output redirection to the port works independently from the PCLK clock. This allows the comparator to work even in Stop mode. 14.3.4 Comparator LOCK mechanism The comparators can be used for safety purposes, such as over-current or thermal protection. For applications having specific functional safety requirements, it is necessary to insure that the comparator programming cannot be altered in case of spurious register access or program counter corruption. For this purpose, the comparator control and status registers can be write-protected (readonly). Once the programming is completed, the COMPxLOCK bit can be set to 1. This causes the whole COMPx_CSR register to become read-only, including the COMPxLOCK bit. The write protection can only be reset by a MCU reset. 14.3.5 Power mode COMP2 power consumption versus propagation delay can be adjusted to have the optimum trade-off for a given application. COMP2_SPEED bit in the COMP2_CSR register can be programmed to provide either higher speed/consumption or lower speed/consumption. 14.4 COMP interrupts The comparator outputs are internally connected to the Extended interrupts and events controller. Each comparator has its own EXTI line and can generate either interrupts or events. The same mechanism is used to exit from low-power modes. Refer to Interrupt and events section for more details. 321/874 DocID025942 Rev 5 RM0377 Comparator (COMP) 14.5 COMP registers 14.5.1 Comparator 1 control and status register (COMP1_CSR) The COMP1_CSR is the Comparator1 control/status register. It contains all the bits /flags related to comparator1. Address offset: 0x18 System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 COMP1 LOCK COMP1 VALUE Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 13 12 11 10 9 8 7 6 5 4 Res. COMP1 LPTIMIN1 Res. COMP1 WM rs r 15 14 COMP1 POLARITY rw Res. Res. Res. rw rw Res. Res. COMP1INN SEL rw 19 18 17 16 Res. Res. Res. 3 2 1 Res. 0 COMP1 Res. Res. Res. EN rw rw Bit 31 COMP1LOCK: COMP1_CSR register lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the comparator 1 control register, COMP1_CSR[31:0] 0: COMP1_CSR[31:0] for comparator 1 are read/write 1: COMP1_CSR[31:0] for comparator 1 are read-only Bit 30 COMP1VALUE: Comparator 1 output status bit This bit is read-only. It reflects the current comparator 1 output taking into account COMP1POLARITY bit effect. Bits 29:16 Reserved, must be kept at reset value Bit 15 COMP1POLARITY: Comparator 1 polarity selection bit This bit is set and cleared by software (only if COMP1LOCK not set). It inverts Comparator 1 polarity. 0: Comparator 1 output value not inverted 1: Comparator 1output value inverted Bits 14:13 Reserved, must be kept at reset value Bit 12 COMP1LPTIMIN1: Comparator 1 LPTIM input propagation bit This bit is set and cleared by software (assuming COMP1LOCK not set). It sends COMP1VALUE to LPTIM input 1. 0: Comparator 1 output gated 1: Comparator 1 output sent to LPTIM input 1 Bits 11:9 Reserved, must be kept at reset value Bit 8 COMP1WM: Comparator 1 window mode selection bit This bit is set and cleared by software (only if COMP1LOCK not set). It selects comparator 1 window mode where the Plus inputs of both comparators are connected together. 0: Plus input of comparator 1 connected to PA1. 1: Plus input of comparator 1 shorted with Plus input of comparator 2 (see COMP1_CSR). Bits 7:6 Reserved, must be kept at reset value DocID025942 Rev 5 322/874 325 Comparator (COMP) RM0377 Bits 5:4 COMP1INNSEL: Comparator 1 Input Minus connection configuration bit These bits are set and cleared by software (only if COMP1LOCK not set). They select which input is connected with the Input Minus of comparator 1 00: VREFINT 01: PA0 10: PA4 11: PA5 Bits 3:1 Reserved, must be kept at reset value Bit 0 COMP1EN: Comparator 1 enable bit This bit is set and cleared by software (only if COMP1LOCK not set). It switches oncomparator1 0: Comparator 1 switched OFF. 1: Comparator 1 switched ON. 14.5.2 Comparator 2 control and status register (COMP2_CSR) The COMP2_CSR is the Comparator2 control/status register. It contains all the bits /flags related to comparator2. Address offset: 0x1C System reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 COMP2 LOCK COMP2 VALUE Res. Res. Res. Res. Res. Res. Res. rs r 15 14 13 12 11 10 9 8 7 COMP2 POLARITY rw Res. COMP2 COMP2 LPTIMIN1 LPTIMIN2 rw rw Res. COMP2INPSEL rw rw Res. rw 22 21 Res. Res. 6 5 20 19 Res. Res. 4 COMP2INNSEL rw rw rw 3 COMP2 SPEED 18 17 Res. Res. 2 1 16 Res. 0 COMP2 Res. Res. EN rw rw Bit 31 COMP2LOCK: COMP2_CSR register lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the comparator 2 control register, COMP2_CSR[31:0] 0: COMP2_CSR[31:0] for comparator 1 are read/write 1: COMP2_CSR[31:0] for comparator 1 are read-only Bit 30 COMP2VALUE: Comparator 2 output status bit This bit is read-only. It reflects the current comparator 2 output taking into account COMP2POLARITY bit effect. Bits 29:16 Reserved, must be kept at reset value Bit 15 COMP2POLARITY: Comparator 2 polarity selection bit This bit is set and cleared by software (only if COMP2LOCK not set). It inverts Comparator 1 polarity. 0: Comparator 2 output value not inverted 1: Comparator 2 output value inverted Bit 14 Reserved, must be kept at reset value 323/874 DocID025942 Rev 5 RM0377 Comparator (COMP) Bit 13 COMP2LPTIMIN1: Comparator 2 LPTIM input 1 propagation bit This bit is set and cleared by software (assuming COMP2LOCK not set). It sends COMP2VALUE to LPTIM input 1. 0: Comparator 2 output gated 1: Comparator 2 output sent to LPTIM input 1 Note: COMP2LPTIMIN1 and COMP2LPTIMIN2 cannot both be set to ‘1’. Bit 12 COMP2LPTIMIN2: Comparator 2 LPTIM input 2 propagation bit This bit is set and cleared by software (assuming COMP2LOCK not set). It sends COMP2VALUE to LPTIM input 2. 0: Comparator 2 output gated 1: Comparator 2 output sent to LPTIM input 2 Note: COMP2LPTIMIN1 and COMP2LPTIMIN2 cannot both be set to ‘1’. Bit 11 Reserved, must be kept at reset value Bits 10:8 COMP2INPSEL: Comparator 2 Input Plus connection configuration bit These bits are set and cleared by software (only if COMP2LOCK not set). They select which input is connected with the Input Plus of comparator 2 000: PA3 001: PB4 010: PB5 011: PB6 100: PB7 101: PA7 (for category 1 devices only) Others: Reserved. Bit 7 Reserved, must be kept at reset value Bits 6:4 COMP2INNSEL: Comparator 2 Input Minus connection configuration bit These bits are set and cleared by software (only if COMP2LOCK not set). They select which input is connected with the Input Minus of comparator 2. 000: VREFINT 001: PA2 010: PA4 011: PA5 100: 1/4 VREFINT 101: 1/2 VREFINT 110: 3/4 VREFINT 111: PB3 Bit 3 COMP2SPEED: Comparator 2 power mode selection bit This bit is set and cleared by software (only if COMP2LOCK not set). It selects comparator 2 power mode. 0: slow speed 1: fast speed Bit 2 Reserved, must be kept at reset value Bit 0 COMP2EN: Comparator 2 enable bit This bit is set and cleared by software (only if COMP2LOCK not set). It switches oncomparator2. 0: Comparator 2 switched off. 1: Comparator 2 switched ON. DocID025942 Rev 5 324/874 325 0x1C 325/874 0 0 COMP2_CSR Reset value 0 0 DocID025942 Rev 5 COMP2LPTIMIN2 0 0 0 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. 0 0 0 0 0 COMP2EN Res. 0 Res. 0 COMP2SPEED COMP2INNSEL 0 Res. COMP2INPSEL 0 Res. COMP2LPTIMIN1 0 Res. COMP2POLARITY Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. COMP1EN Res. Res. Res. COMP1INNSEL Res. Res. COMP1WM Res. Res. Res. COMP1LPTIMIN1 Res. Res. COMP1POLARITY Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Res. COMP1_CSR COMP1LOCK 0x18 COMP1VALUE Offset COMP2LOCK 14.5.3 COMP2VALUE Comparator (COMP) RM0377 COMP register map The following table summarizes the comparator registers. Table 64. COMP register map and reset values 0 0 RM0377 15 Advanced encryption standard hardware accelerator (AES) Advanced encryption standard hardware accelerator (AES) The AES is only available in devices with AES peripheral (see Table 2: Features per category). 15.1 Introduction The AES hardware accelerator can be used to both encipher and decipher data using AES algorithm. It is a fully compliant implementation of the following standard: The advanced encryption standard (AES) as defined by Federal Information Processing Standards Publication (FIPS PUB 197, 2001 November 26) The accelerator encrypts and decrypts 128-bit blocks using 128-bit key length. It can also perform key derivation. The encryption or decryption key is stored in an internal register in order to minimize write operations by the CPU or DMA when processing several data blocks using the same key. By default, Electronic CodebBook mode (ECB) is selected. Cipher block chaining (CBC) or Counter (CTR) mode) chaining algorithms are also supported by the hardware. The AES supports DMA transfer for incoming and for outcoming data (2 DMA channels required). 15.2 AES main features Encryption/Decryption using AES Rijndael Block Cipher algorithm NIST FIPS 197 compliant implementation of AES encryption/decryption algorithm Internal 128-bit register for storing the encryption or derivation key (4x 32-bit registers) Electronic codebook (ECB), Cipher block chaining (CBC), and Counter mode (CTR) supported Key scheduler Key derivation for decryption 128-bit data block processing 128-bit key length 213 clock cycles to encrypt or decrypt one 128-bit block (including the input and output phases) 1x32-bit INPUT buffer and 1x32-bit OUTPUT buffer. Register access supporting 32-bit data width only. One 128-bit Register for the initialization vector when AES is configured in CBC mode or for the 32-bit counter initialization when CTR mode is selected. Automatic data flow control with support of direct memory access (DMA) using 2 channels, one for incoming data, and one for outcoming data. DocID025942 Rev 5 326/874 352 Advanced encryption standard hardware accelerator (AES) 15.3 RM0377 AES functional description Figure 53 shows the block diagram of the AES accelerator. Figure 53. Block diagram !(""53 !%3?32 !%3?#2 %3?)62 !%3?$).2 !%3?$/542 !%3?+%92X !%3(!2$7!2%!##%,%2!4/2 -36 The AES accelerator processes data blocks of 128-bits (4 words) using a key with a length of 128 bits, and an initialization vector when CBC or CTR chaining mode is selected. It provides 4 operating modes: Mode 1: Encryption using the encryption key stored in the AES_KEYRx registers. Mode 2: Key Derivation stored internally in the AES_KEYRx registers at the end of the key derivation processed from the encryption key stored in this register before enabling the AES. This mode is independent from the AES chaining mode selection. Mode 3: Decryption using a given (precomputed) decryption key stored in the AES_KEYRx registers. Mode 4: Key Derivation + Decryption using an encryption key stored in the AES_KEYRx registers (not used when the AES is configured in Counter mode for perform a chaining algorithm). The operating mode is selected by programming bits MODE[1:0] into the AES_CR register. The mode must be changed only when the AES is disabled (bit EN=0 in the AES_CR register). The KEY registers (AES_KEYRx) must be stored before enabling the AES. To select which one of the ECB, CBC or CTR mode is going to be used for the cryptographic solution, it is mandatory to write the bit CHMOD[1:0] of the AES_CR register and the AES_IVR register (only used for the CBC and CTR chaining modes) when the AES is disabled (bit EN =0 in the AES_CR register). Once enabled (bit EN=1), the AES is in the input phase, waiting for the software to write the input data words into the AES_DINR (4 words) for the modes 1, 3 or 4. The data corresponds either to the plaintext message or the cipher message. A wait cycle is automatically inserted between two consecutive writes to the AES_DINR register in order to send, interleaved with the data, the key to the AES processor. For mode 2, the key derivation processing is started immediately after the EN bit in the AES_CR register is set. It requires that the AES_KEYRx registers are loaded with the encrypted KEY before enabling the AES. At the end of the Key derivation processing (CCF flag is set), the derivative key is available in the AES_KEYRx registers and the AES is disabled by hardware. In this mode, the AES_KEYRx registers must not be read when AES is enabled and until the CCF flag is set to 1 by hardware. 327/874 DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) The status flag CCF (Computation Complete Flag) in the AES_SR register is set once the computation phase is complete. An interrupt can be generated if bit CCFIE=1 in the AES_CR register. The software can then read back the data from the AES_DOUTR register (for modes 1, 3, 4) or from the AES_KEYRx registers (if mode 2 is selected). The flag CCF has no meaning when DMAOUTEN = 1 in the AES_CR register, because the reading the AES_DOUTR register is managed by DMA automatically without any software action at the end of the computation phase. The operation ends with the output phase, during which the software reads successively the 4 output data words from the AES_DOUTR register in mode 1, 3 or 4. In mode 2 (key derivation mode), the data is automatically stored in the AES_KEYRx registers and the AES is disabled by hardware. Then, software can select mode 3 (decryption mode) before it enables the AES to start the decryption using this derivative key. During the input and output phases, the software must read or write the data bytes successively (except in mode 2) but the AES is tolerant of any delays occurring between each read or write operation (example: if servicing another interrupt at this time). The RDERR and WRERR flags in the AES_SR register are set when an unexpected read or write operation is detected. An interrupt can be generated if the ERRIE bit is set in the AES_CR register. AES is not disabled after an error detection and continues processing as normal. It is also possible to use the general purpose DMA to write the input words and to read the output words (refer to Figure 68 and Figure 69). The AES can be re-initialized at any moment by resetting the EN bit in the AES_CR register. Then the AES can be re-started from the beginning by setting EN=1, waiting for the first input data byte to be written (except in mode 2 where Key derivation processing starts as soon as the EN bit is set, starting from the value stored in the AES_KEYRx registers). 15.4 Encryption and derivation keys The AES_KEYRx registers are used to store the encryption or decryption keys. These four registers are organized in little-endian configuration: Register AES_KEYR0 has to be loaded with the 32-bit LSB of the key. Consequently, AES_KEYR3 has to be loaded with the 32-bit MSB of the 128-bit key. The key for encryption or decryption must be stored in these registers when the AES is disabled (EN = 0 into the AES_CR register). Their endianess are fixed. In mode 2 (key derivation), the AES_KEYRx needs to be loaded with the encryption key. Then, the AES has to be enabled. At the end of the computation phase, the derivation key is stored automatically in the AES_KEYRx registers, overwriting the previous encryption key. The AES is disabled by hardware when the derivation key is available. If the software needs to switch the AES to mode 3 (decryption mode), there is no need to write the AES_KEYRx registers if their content corresponds to the derivation key (previously computed by mode 2). In mode 4 (key derivation + decryption), the AES_KEYRx registers contain only the encryption key. The derivation key is calculated internally without any write to these registers. DocID025942 Rev 5 328/874 352 Advanced encryption standard hardware accelerator (AES) 15.5 RM0377 AES chaining algorithms Three algorithms are supported by the AES hardware and can be selected through the CHMOD[1:0] bits in the AES_CR register when the AES is disabled (bit EN = 0): 15.5.1 Electronic CodeBook (ECB) Cipher Block Chaining (CBC) Counter Mode (CTR) Electronic CodeBook (ECB) This is the default mode. This mode doesn’t use the AES_IVR register. There are no chaining operations. The message is divided into blocks and each block is encrypted separately. Figure 54 and Figure 55 describe the principle of the Electronic Codebook algorithm for encryption and decryption respectively. Figure 54. ECB encryption mode $(6B',153ODLQWH[W 'DWDW\SH>@ $(6B.(<5[ 'DWDW\SH>@ 6:$3 PDQDJHPHQW %ORFNFLSKHU (QFU\SWLRQ 6:$3 PDQDJHPHQW $(6B'2875&LSKHUWH[W 069 329/874 DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) Figure 55. ECB decryption mode $(6B ',15&LSKHUWH[W 'DWDW\SH >@ $(6B.(<5[ .H\ 'DWDW\SH >@ 6:$3 PDQDJHPHQW %ORFNFLSKHU 'HFU\SWLRQ 6:$3 PDQDJHPHQW $(6B '2875 3ODLQWH[W 069 DocID025942 Rev 5 330/874 352 Advanced encryption standard hardware accelerator (AES) 15.5.2 RM0377 Cipher block chaining (CBC) In cipher-block chaining (CBC) mode, each block of plain text is XORed with the previous cipher text block before being encrypted. To make each message unique, an initialization vector (AES_IVRx) is used during the first block processing. The initialization vector is XORed after the swapping management block in during encryption mode and before it in decryption mode (refer to Figure 56 and Figure 57). Figure 56. CBC mode encryption $(6B ',15 3ODLQWH[W 'DWDW\SH >@ $(6B ',15 3ODLQWH[W 6:$3 PDQDJHPHQW 'DWDW\SH >@ 6:$3 PDQDJHPHQW $(6B ,95[ $(6B.(<5[ .H\ 'DWDW\SH >@ %ORFNFLSKHU (QFU\SWLRQ $(6B.(<5[ .H\ 6:$3 PDQDJHPHQW $(6B'2875&LSKHUWH[W 'DWDW\SH >@ %ORFNFLSKHU (QFU\SWLRQ 6:$3 PDQDJHPHQW $(6B'2875&LSKHUWH[W 069 331/874 DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) Figure 57. CBC mode decryption $(6B',15&LSKHUWH[W 'DWDW\SH>@ $(6B.(<5[.H\ $(6B',15&LSKHUWH[W 6:$3 PDQDJHPHQW %ORFNFLSKHU 'HFU\SWLRQ 'DWDW\SH>@ $(6B.(<5[.H\ 6:$3 PDQDJHPHQW %ORFNFLSKHU 'HFU\SWLRQ $(6B,95[ 'DWDW\SH>@ 6:$3 PDQDJHPHQW $(6B'28753ODLQWH[W 'DWDW\SH>@ 6:$3 PDQDJHPHQW $(6B'28753ODLQWH[W 069 Note: When the AES is enabled, reading the AES_IVR returns the value 0x00000000. Suspended mode for a given message It is possible to suspend a message if another message with a higher priority needs to be processed. At the end of sending of this highest priority message, the suspended message may be resumed in both encryption or decryption mode. This feature is available only when the data transfer is done by CPU accesses to the AES_DOUTR and AES_DINR registers. It is advised to not use it when the DMA controller is managing the data transfer. For correct operation, the message must be suspended at the end of processing a block (after the fourth read of the AES_DOUTR register and before the next AES_DINR write access corresponding to the input of the next block to be processed). The AES should be disabled writing bit EN = 0 in the AES_CR register. The software has to read the AES_IVRx which contains the latest value to be used for the chaining XOR operation before message interruption. This value has to be stored for reuse by writing the AES_IVRx registers as soon as the interrupted message has to be resumed (when AES is disabled). It should be noted that this does not break the chaining operation and the message processing can be resumed as soon as the AES is enabled again to send the next 128-bit data block. This behavior is valid whatever the AES configuration (encryption or decryption mode). Figure 58 gives an example of a message 1 which is suspended in order to send a higher priority message 2, shorter than message 1. At the end of the 128-bit block processing, AES is disabled. The AES_IVR register is read back to store the value to be retrieved later on when the message is resumed, in order not to break the chaining operation. Then, the AES is configured to send message 2 and it is enabled to start processing. At the end of DocID025942 Rev 5 332/874 352 Advanced encryption standard hardware accelerator (AES) RM0377 message 2 processing, AES has to be disabled again and the AES_IVRx registers have to be loaded with the value previously stored when the message 1 was interrupted. Then software has to restart from the input value corresponding to block 4 as soon as AES is enabled to resume message 1. Figure 58.J Example of suspend mode management 0HVVDJH ELWEORFN ELWEORFN 1HZKLJKHUSULRULW\ PHVVDJHWR EHSURFHVVHG $(6GLVDEOHG UHDG$(6B,95DQGVWRUHWKHYDOXH &RQILJXULQJ$(6IRUQH[WPHVVDJH $(6HQDEOHG ELWEORFN ELWEORFN ELWEORFN ELWEORFN ELWEORFN ELWEORFN ELWEORFN $(6GLVDEOHG ZULWHWKH$(6B,95ZLWKWKHYDOXHVWRUHG $(6HQDEOHG ELWEORFN 069 333/874 DocID025942 Rev 5 RM0377 15.5.3 Advanced encryption standard hardware accelerator (AES) Counter Mode (CTR) In counter mode, a 32-bit counter is used in addition to a nonce value for the XOR operation with the cipher text or plain text (refer to Figure 59 and Figure 60). Figure 59. CTR mode encryption $(6B,95[ 1RQFH $(6B.(<5[.H\ $(6B,95[ FRXQWHU 1RQFH $(6B.(<5[.H\ %ORFNFLSKHU HQFU\SWLRQ $(6B',153ODLQWH[W $(6B',153ODLQWH[W 6ZDS PDQDJHPHQW 6ZDS PDQDJHPHQW 'DWDW\SH>@ 'DWDW\SH>@ 6ZDS PDQDJHPHQW FRXQWHU %ORFNFLSKHU HQFU\SWLRQ 'DWDW\SH>@ 'DWDW\SH>@ 6ZDS PDQDJHPHQW $(6B'2875&LSKHUWH[W $(6B'2875&LSKHUWH[W 06 Figure 60. CTR mode decryption $(6B,95[ 1RQFH $(6B.(<5[.H\ FRXQWHU %ORFNFLSKHU HQFU\SWLRQ $(6B',15&LSKHUWH[W 6ZDS PDQDJHPHQW 'DWDW\SH>@ 'DWDW\SH >@ 6ZDS PDQDJHPHQW $(6B'28753ODLQWH[W D^ϭϴϵϰϮsϭ DocID025942 Rev 5 334/874 352 Advanced encryption standard hardware accelerator (AES) RM0377 The nonce value and 32-bit counter are accessible through the AES_IVRx register and organized like below in Figure 61: Figure 61. 32-bit counter + nonce organization $(6B,95 $(6B,95 $(6B,95 1RQFH $(6B,95 ELWFRXQWHU 069 In Counter Mode, the counter is incremented from the initialized value for each block to be processed in order to guarantee a unique sequence which is not repeated for a long time. It is a 32-bit counter, meaning that the nonce message is kept to the initialized value stored when the AES was disabled. Only the 32-bit LSB of the 128-bit initialization vector register represents the counter. In contrast to CBC mode (which uses the AES_IVRx registers only once when processing the first data block), in Counter mode, the AES_IVRx registers are used for processing each data block. In counter mode, key derivation+decryption mode is not applicable. Note: The AES_IVRx register has be written only when the AES is disabled (bit EN = 0) to guarantee good AES behavior. Reading it while AES is enabled returns the value 0x00000000. Reading it while the AES is disabled returns the latest counter value (useful for managing suspend mode). In CTR mode, key derivation + decryption serves no purpose. Consequently it is forbidden to set MODE[1:0] = 11 in the AES_CR register and any attempt to set this configuration is forced to MODE[1:0] = 10 (which corresponds to CTR mode decryption). This uses the encryption block of the AES processor to decipher the message as shown in Figure 60). Suspend mode in CTR mode Like for the CBC mode, it is possible to interrupt a message, sending a higher priority message and resume the message which was interrupted. Refer to the Figure 58 and Chapter 15.5.2 for more details about the suspend mode capability. 335/874 DocID025942 Rev 5 RM0377 15.6 Advanced encryption standard hardware accelerator (AES) Data type Data are entered in the AES processor 32 bits at a time (words), by writing them in the AES_DINR register. AES handles 128-bit data blocks. The AES_DINR or AES_DOUTR registers must be read or written four times to handle one 128-bit data block with the MSB first. The system memory organization is little-endian: whatever the data type (bit, byte, 16-bit half-word, 32-bit word) used, the less-significant data occupies the lowest address location. Thus, there must be a bit, byte, or half-word swapping operation to be performed on data to be written in the AES_DINR from system memory before entering the AES processor, and the same swapping must be performed for AES data to be read from the AES_DOUTR register to the system memory, depending on to the kind of data to be encrypted or decrypted. The DATATYPE bits in the AES_CR register offer different swap modes to be applied to the AES_DINR register before sending it to the AES processor and to be applied on the AES_DOUTR register on the data coming out from the processor (refer to Figure 62). Note: The swapping operation concerns only the AES_DOUTR and AES_DINR registers. The AES_KEYRx and AES_IVRx registers are not sensitive to the swap mode selected. They have a fixed little-endian configuration (refer to Section 15.4 and Section 15.12). DocID025942 Rev 5 336/874 352 Advanced encryption standard hardware accelerator (AES) RM0377 Figure 62. 128-bit block construction according to the data type $!4!490%B.OSWAPPING !%3?$).2OR!%3?$/542 ,3" -3" 7ORD 7ORD 7ORD 7ORD ,3" -3" !%3PROCESSORINPUTOR!%3PROCESSOROUTPUT $!4!490% BBITORHALFWORDSWAPPING !%3?$).2OR!%3?$/542 -3" 7ORD 7ORD BIT BIT BIT BIT BIT BIT BIT BIT ,3" 7ORD 7ORD BIT BIT BIT BIT BIT BIT -3" BIT BIT ,3" !%3PROCESSORINPUTOR!%3PROCESSOROUTPUT $!4!490% BBITOR"YTESWAPPING !%3?$).2OR!%3?$/542 -3" 7ORD 7ORD BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT ,3" 7ORD 7ORD BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT -3" BIT BIT ,3" !%3PROCESSORINPUTOR!%3PROCESSOROUTPUT -36 337/874 DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) Figure 63. 128-bit block construction according to the data type (continued) $!4!490% B"ITSWAPPING !%3?$).2OR!%3?$/542 -3" 7/2$ 7/2$ BIT BIT BIT BIT BIT BIT BIT BIT BIT ,3" 7/2$ 7/2$ BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT BIT ,3" -3" !%3PROCESSORINPUTOR!%3PROCESSOROUTPUT -36 15.7 Operating modes 15.7.1 Mode 1: encryption 1. Disable the AES by resetting bit the EN bit in the AES_CR register. 2. Configure the Mode 1 by programming MODE[1:0]=00 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[1:0] bits. 3. Write the AES_KEYRx registers (128-bit encryption key) and the AES_IVRx registers if CTR or CBC mode is selected. For EBC mode, the AES_IVRx register is not used. 4. Enable the AES by setting the EN bit in the AES_CR register. 5. Write the AES_DINR register 4 times to input the plain text (MSB first) as shown in Figure 64: Mode 1: encryption on page 338. 6. Wait until the CCF flag is set in the AES_SR register. 7. Reads the AES_DOUTR register 4 times to get the cipher text (MSB first) as shown in Figure 64: Mode 1: encryption on page 338. 8. Repeat steps 5,6,7 to process all the blocks with the same encryption key. Figure 64. Mode 1: encryption 04 -3" 04 04 04 FLAG##& ,3" ).0540(!3% 72)4%/0%2!4)/.3 ).4/!%3?$).;= #4 -3" #/-054!4)/.0(!3% 040,!).4%847ORDS0404 #4#90(%24%847ORDS#4#4 DocID025942 Rev 5 #4 #4 #4 ,3" /540540(!3% 2%!$/0%2!4)/.3 /&!%3?$/54;= 069 338/874 352 Advanced encryption standard hardware accelerator (AES) 15.7.2 RM0377 Mode 2: key derivation 1. Disable the AES by resetting the EN bit in the AES_CR register. 2. Configure Mode 2 by programming MODE[1:0]=01 in the AES_CR register. Note that the CHMOD[1:0] bits are not significant in this case because this key derivation mode is independent from the chaining algorithm selected. 3. Write the AES_KEYRx registers with the encryption key to obtain the derivative key. A write to the AES_IVRx has no effect. 4. Enable the AES by setting the EN bit in the AES_CR register. 5. Wait until the CCF flag is set in the AES_SR register. 6. The derivation key is put automatically into the AES_KEYRx registers. Read the AES_KEYRx register to obtain the decryption key if needed. The AES is disabled by hardware. To restart a derivation key calculation, repeat steps 3, 4, 5 and 6. Figure 65. Mode 2: key derivation 72 %+ -3" 72 %+ 72 %+ 72 %+ 7!)45.4), FLAG##& 2$ $+ -3" ,3" #/-054!4)/.0(!3% ).0540(!3% 72)4%/0%2!4)/.3 ).4/!%3?+%92X;= %.INTO!%3?#2 339/874 2$ $+ 2$ $+ ,3" /540540(!3%/04)/.!, 2%!$/0%2!4)/.3 /&!%3?+%92X4;= BIT$ERIVATION+EY STOREDINTO!%3?+%92X %+%.#2904)/.+%97ORDS%+%+ $+$%#2904)/.+%97ORDS$+$+ 15.7.3 2$ $+ -36 Mode 3: decryption 1. Disable the AES by resetting the EN bit in the AES_CR register. 2. Configure Mode 3 by programming MODE[1:0] =10 in the AES_CR register and select which type of chaining mode needs to be performed by programming the CHMOD[1:0] bits. 3. Write the AES_KEYRx registers with the decryption key (this step can be bypassed if the derivation key is already stored in the AES_KEYRx registers using mode 2: key derivation). Write the AES_IVRx registers if CTR or CBC mode is selected. For EBC mode, the AES_IVRx registers are not used. 4. Enable the AES by setting the EN bit in the AES_CR register. 5. Write the AES_DINR register 4 times to input the cipher text (MSB first) as shown in Figure 66: Mode 3: decryption on page 340. 6. Wait until the CCF flag is set in the AES_SR register. 7. Read the AES_DOUTR register 4 times to get the plain text (MSB first) as shown in Figure 66: Mode 3: decryption on page 340. 8. Repeat steps 5, 6, 7 to process all the blocks using the same derivation key stored in the AES_KEYRx registers. DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) Figure 66. Mode 3: decryption 72 #4 72 #4 72 #4 -3" 72 #4 7!)45.4), FLAG##& ,3" ).0540(!3% 72)4%/0%2!4)/.3 ).4/!%3?$).;= 2$ 04 2$ 04 -3" #/-054!4)/.0(!3% Note: 2$ 04 ,3" /540540(!3% 2%!$/0%2!4)/.3 /&!%3?$/54;= 040,!).4%847ORDS0404 #4#90(%24%847ORDS#4#4 15.7.4 2$ 04 -36 Mode 4: key derivation and decryption 1. Disable the AES by resetting the EN bit in the AES_CR register. 2. Configure Mode 4 by programming MODE[1:0]=11 in the AES_CR register. This mode is forbidden when AES is configured in CTR mode. It will be forced to CTR decryption mode if the software writes MODE[1:0] = 11 and CHMOD[1:0] = 10. 3. Write the AES_KEYRx register with the encryption key. Write the AES_IVRx register if the CBC mode is selected. 4. Enable the AES by setting the EN bit in the AES_CR register. 5. Write the AES_DINR register 4 times to input the cipher text (MSB first) as shown in Figure 67: Mode 4: key derivation and decryption on page 340. 6. Wait until the CCF flag is set in the AES_SR register. 7. Read the AES_DOUTR register 4 times to get the plain text (MSB first) as shown in Figure 67: Mode 4: key derivation and decryption on page 340. 8. Repeat steps 5, 6, 7 to process all the blocks with the same encryption key The AES_KEYRx registers contain the encryption key during all phases of the processing, No derivation key is stored in these registers. The derivation key starting from the encryption key is stored internally in the AES without storing a copy in the AES_KEYRx registers. Figure 67. Mode 4: key derivation and decryption 72 #4 -3" 72 #4 72 #4 72 #4 7!)45.4), FLAG##& ,3" ).0540(!3% 72)4%/0%2!4)/.3 ).4/!%3?$).;= 2$ 04 -3" #/-054!4)/.0(!3% 040,!).4%847ORDS0404 #4#90(%24%847ORDS#4#4 DocID025942 Rev 5 2$ 04 2$ 04 2$ 04 ,3" /540540(!3% 2%!$/0%2!4)/.3 /&!%3?$/54;= -36 340/874 352 Advanced encryption standard hardware accelerator (AES) 15.8 RM0377 AES DMA interface The AES accelerator provides an interface to connect to the DMA controller. The DMA must be configured to transfer words. The AES can be associated with two distinct DMA request channels: A DMA request channel for the inputs: When the DMAINEN bit is set in the AES_CR register, the AES initiates a DMA request (AES_IN) during the INPUT phase each time it requires a word to be written to the AES_DINR register. The DMA channel must be configured in memory-to-peripheral mode with 32-bit data size. A DMA request channel for the outputs: When the DMAOUTEN bit is enabled, the AES initiates a DMA request (AES_OUT) during the OUTPUT phase each time it requires a word to be read from the AES_DOUTR register. The DMA channel must be configured in peripheral-to-memory mode with a data size equal to 32-bit. Four DMA requests are asserted for each phase, these are described in Figure 68 and Figure 69. DMA requests are generated until the AES is disabled. So, after the data output phase at the end of processing a 128-bit data block, the AES switches automatically to a new data input phase for the next data block if any. Note: For mode 2 (key derivation), access to the AES_KEYRx registers can be done by software using the CPU. No DMA channel is provided for this purpose. Consequently, the DMAINEN bit and DMAOUTEN bits in the AES_CR register have no effect during this mode. The CCF flag is not relevant when DMAOUTEN = 1 and software does not need to read it in this case. This bit may stay high and has to be cleared by software if the application needs to disable the AES to cancel the DMA management and use CPU access for the data input or data output phase. Figure 68. DMA requests and data transfers during Input phase (AES_IN) -/$%%NCRYPTION-ODEOR$ECRYPTION $-!2%15%343 -3" !%3?$).2 724 $-!2%1 . !%3?$).2 724 $-!2%1 .§ !%3?$).2 724 $-!2%1 .§ !%3?$).2 724 $-!2%1 .§ -36 341/874 DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) Figure 69. DMA requests during Output phase (AES_OUT) -/$%%NCRYPTION-ODEOR$ECRYPTION $-!2%15%343 -3" !%3?$/542 2$$ $-!2%1 .§ !%3?$/542 2$$ !%3?$/542 2$$ $-!2%1 .§ !%3?$/542 2$$ $-!2%1 .§ $-!2%1 .§ $0,!).OR#)0(%24%84DEPENDINGONMODEOFOPERATION 7/2$3$$ -36 15.9 Error flags The RDERR flag in the AES_SR register is set when an unexpected read operation is detected during the computation phase or during the input phase. The WRERR flag in the AES_SR register is set when an unexpected write operation is detected during the output phase or during the computation phase. The flags may be cleared setting the respective bit in the AES_CR register (CCFC bit to clear the CCF flag, ERRC bit to clear the WERR and RDERR flags). An interrupt can be generated when one of the error flags is set if the ERRIE bit in the AES_CR register has been previously set. If an error is detected, AES is not disabled by hardware and continues processing as normal. 15.10 Processing time The table summarizes the time required to process a 128-bit block for each mode of operation. Table 65. Processing time (in clock cycle) Input phase Computation phase Mode 1: Encryption 8 202 4 214 Mode 2: Key derivation - 80 - 80 Mode 3: Decryption 8 202 4 214 Mode 4: Key derivation + decryption 8 276 4 288 Mode of operation DocID025942 Rev 5 Output phase Total 342/874 352 Advanced encryption standard hardware accelerator (AES) 15.11 RM0377 AES interrupts Table 66. AES interrupt requests Event flag Enable control bit Exit from Wait CCF CCFIE yes AES read error flag RDERR ERRIE yes AES write error flag WRERR ERRIE yes Interrupt event AES computation completed flag 343/874 DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) 15.12 AES registers 15.12.1 AES control register (AES_CR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ERRIE CCFIE ERRC CCFC rw rw rw rw DMAO DMAI UTEN NEN Reserved r r r rw rw CHMOD[1:0] MODE[1:0] rw rw rw rw DATATYPE[1:0] rw rw EN rw Bit 31:13 Reserved, read as 0 Bit 12 DMAOUTEN: Enable DMA management of data output phase 0: DMA (during data output phase) disabled 1: DMA (during data output phase) enabled If the DMAOUTEN bit is set, DMA requests are generated for the output data phase in mode 1, 3 or 4. This bit has no effect in mode 2 (Key derivation). Bit 11 DMAINEN: Enable DMA management of data input phase 0: DMA (during data input phase) disabled 1: DMA (during data input phase) enabled If the DMAINEN bit is set, DMA requests are generated for the data input phase in mode 1, 3 or 4. This bit has no action in mode 2 (Key Derivation). Bit 10 ERRIE: Error interrupt enable An interrupt is generated if at least one of the both flags RDERR or WRERR is set. 0: Error interrupt disabled 1: Error interrupt enabled Bit 9 CCFIE: CCF flag interrupt enable An interrupt is generated if the CCF flag is set. 0: CCF interrupt disabled 1: CCF interrupt enabled Bit 8 ERRC: Error clear Writing 1 to this bit clears the RDERR and WRERR flags. This bit is always read low. Bit 7 CCFC: Computation Complete Flag Clear Writing 1 to this bit clears the CCF flag. This bit is always read low. DocID025942 Rev 5 344/874 352 Advanced encryption standard hardware accelerator (AES) RM0377 Bits 6:5 CHMOD[1:0]: AES chaining mode 00: Electronic codebook (EBC) 01: Cipher-Block Chaining (CBC) 10: Counter Mode (CTR) 11: Reserved. The AES chaining mode must only be changed while the AES is disabled. Writing these bits while the AES is enabled is forbidden to avoid unpredictable AES behavior. Bits 4:3 MODE[1:0]: AES operating mode 00: Mode 1: Encryption 01: Mode 2: Key derivation 10: Mode 3: Decryption 11: Mode 4: Key derivation + decryption The operation mode must only be changed if the AES is disabled. Writing these bits while the AES is enabled is forbidden to avoid unpredictable AES behavior. Mode 4 is forbidden if CTR mode is selected. It will be forced to Mode 3 if the software, nevertheless, attempts to set mode 4 for this CTR mode configuration. Bits 2:1 DATATYPE[1:0]: Data type selection (for data in and data out to/from the cryptographic block) 00: 32-bit data. No swapping. 01: 16-bit data or half-word. In the word, each half-word is swapped. For example, if one of the four 32-bit data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic block is 0x56AB7643 10: 8-bit data or bytes. In the word, all the bytes are swapped. For example, if one of the four 32-bit data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic block is 0xAB564376. 11: Bit data. In the word all the bits are swapped. For example, if one of the four 32-bit data written in the AES_DINR register is 0x764356AB, the value given to the cryptographic block is 0xD56AC26E The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is enabled is forbidden to avoid unpredictable AES behavior. Bits 0 EN: AES enable 0: AES disable 1: AES enable The AES can be re-initialized at any moment by resetting this bit: the AES is then ready to start processing a new block when EN is set. This bit is cleared by hardware when the AES computation is finished in mode 2 (Key derivation) 345/874 DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) 15.12.2 AES status register (AES_SR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Reserved r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Reserved r r r r r r r WRERR RDERR r r r r r r r r CCF r Bits 31:3 Reserved, read as 0 Bit 2 WRERR: Write error flag This bit is set by hardware when an unexpected write operation to the AES_DINR register is detected (during computation or data output phase). An interrupt is generated if the ERRIE bit has been previously set in the AES_CR register. This flag has no impact on the AES which continues running if even if WERR is set. It is cleared by software by setting the ERRC bit in the AES_CR register. 0: No write error detected 1: Write error detected Bit 1 RDERR: Read error flag This bit is set by hardware when an unexpected read operation from the AES_DOUTR register is detected (during computation or data input phase). An interrupt is generated if the ERRIE bit has been previously set in the AES_CR register.This flag has no impact on the AES which continues running if even if RDERR is set. It is cleared by software by setting the ERRC bit i in the AES_CR register. 0: No read error detected 1: Read error detected Bit 0 CCF: Computation complete flag This bit is set by hardware when the computation is complete. An interrupt is generated if the CCFIE bit has been previously set in the AES_CR register. It is cleared by software by setting the CCFC bit in the AES_CR register. 0: Computation complete 1: Computation is not complete Note: This bit is significant only when DMAOUTEN = 0. It may stay high when DMA_EN = 1. DocID025942 Rev 5 346/874 352 Advanced encryption standard hardware accelerator (AES) 15.12.3 RM0377 AES data input register (AES_DINR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DINR[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DINR[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 DINR[31:0]: Data Input Register. This register must be written 4 times during the input phase: – In Mode 1 (Encryption), 4 words must be written which represent the plain text from MSB to LSB. – In Mode 2 (Key Derivation), This register is not used because this mode concerns only derivative key calculation starting from the AES_KEYRx register. – In Mode 3 (Decryption) and 4 (Key Derivation+Decryption), 4 words must be written which represent the cipher text MSB to LSB. Note: This register must be accessed with 32-bit data width. 15.12.4 AES data output register (AES_DOUTR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DOUTR[31:16] r r r r r r r r r r r r r r r r 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 r r r r r r r DOUTR[15:0] r r r r r r r r r Bits 31:0 DOUTR[31:0]: Data output register This register is read only. Once the CCF flag (Computation Complete Flag) is set, reading this data register 4 times gives access to the 128-bit output results: - In Mode 1 (Encryption), the 4 words read represent the cipher text from MSB to LSB. - In Mode 2 (Key Derivation), there is no need to read this register because the derivative key is located in the AES_KEYRx registers. - In Mode 3 (Decryption) and Mode 4 (Key Derivation+Decryption), the 4 words read represent the plain text from MSB to LSB. Note: This register must be accessed with 32-bit data width. 347/874 DocID025942 Rev 5 RM0377 15.12.5 Advanced encryption standard hardware accelerator (AES) AES key register 0(AES_KEYR0) (LSB: key [31:0]) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR0[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR0[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR0[31:0]: Data Output Register (LSB key [31:0]) This register must be written before the EN bit in the AES_CR register is set: In Mode 1 (Encryption), mode 2 (Key Derivation) and mode 4 (Key Derivation + Decryption), the value to be written represents the encryption key from LSB, meaning Key [31:0]. In Mode 3 (Decryption), the value to be written represents the decryption key from LSB, meaning Key [31:0]. When the register is written with the encryption key in this decryption mode, reading it before the AES is enabled will return the encryption value. Reading it after CCF flag is set will return the derivation key. Reading this register while AES is enabled return an unpredictable value. Note: This register does not contain the derivation key in mode 4 (derivation key + decryption). It always contains the encryption key value. 15.12.6 AES key register 1 (AES_KEYR1) (Key[63:32]) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR1[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR1[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR1[31:0]: AES key register (key [63:32]) Refer to the description of AES_KEYR0. DocID025942 Rev 5 348/874 352 Advanced encryption standard hardware accelerator (AES) 15.12.7 RM0377 AES key register 2 (AES_KEYR2) (Key [95:64]) Address offset: 0x18 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR2[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR2[31:0]: AES key register (key [95:64]) Refer to the description of AES_KEYR0. 15.12.8 AES key register 3 (AES_KEYR3) (MSB: key[127:96]) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 KEYR3[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw KEYR3[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 KEYR3[31:0]: AES key register (MSB key [127:96]) Refer to the description of AES_KEYR0. 15.12.9 AES initialization vector register 0 (AES_IVR0) (LSB: IVR[31:0]) Address offset: 0x20 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVR0[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw IVR0[15:0] rw 349/874 rw rw rw rw rw rw rw rw DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) Bits 31:0 IVR0[31:0]: initialization vector register (LSB IVR [31:0]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: - The EBC mode (Electronic codebook) is selected. - The CTR or CBC mode is selected in addition with the Key derivation. In CTR mode (Counter mode), this register contains the 32-bit counter value. Reading this register while AES is enabled will return the value 0x00000000. 15.12.10 AES initialization vector register 1 (AES_IVR1) (IVR[63:32]) Address offset: 0x24 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVR1[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw IVR1[15:0] rw rw Bits 31:0 rw rw rw rw rw rw rw IVR1[31:0]: Initialization Vector Register (IVR [63:32]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: - The EBC mode (Electronic codebook) is selected. - The CTR or CBC mode is selected in addition with the Key derivation or key derivation+decryption mode. In CTR mode (Counter mode), this register contains the nonce value. Reading this register while AES is enabled will return the value 0x00000000. DocID025942 Rev 5 350/874 352 Advanced encryption standard hardware accelerator (AES) RM0377 15.12.11 AES initialization vector register 2 (AES_IVR2) (IVR[95:64]) Address offset: 0x28 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVR2[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw IVR2[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 IVR2[31:0]: Initialization Vector Register (IVR [95:64]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: - The EBC mode (Electronic codebook) is selected. - The CTR or CBC mode is selected in addition with the Key derivation or key derivation+decryption mode. In CTR mode (Counter mode), this register contains the nonce value. Reading this register while AES is enabled will return the value 0x00000000. 15.12.12 AES initialization vector register 3 (AES_IVR3) (MSB: IVR[127:96]) Address offset: 0x2C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IVR3[31:16] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw IVR3[15:0] rw rw rw rw rw rw rw rw rw Bits 31:0 IVR3[31:0]: Initialization Vector Register (MSB IVR [127:96]) This register must be written before the EN bit in the AES_CR register is set: The register value has no meaning if: - The EBC mode (Electronic codebook) is selected. - The CTR or CBC mode is selected in addition with the Key derivation or key derivation+decryption mode. In CTR mode (Counter mode), this register contains the nonce value. Reading this register while AES is enabled will return the value 0x00000000. 351/874 DocID025942 Rev 5 RM0377 Advanced encryption standard hardware accelerator (AES) 15.12.13 AES register map ERRC CCFC 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. 0x0008 0x000C 0x0010 0x0014 0x0018 AES_DINR Reset value Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RDERR CCF 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_KEYR0[31:0] 0 0 0 0 0 AES_KEYR1[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_KEYR2[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_KEYR3[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_IVR0[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_IVR1[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_IVR2 0 0 0 0 AES_IVR2[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 AES_IVR3 Reset value 0 AES_DOUTR[31:0] AES_IVR1 Reset value 0x002C 0 AES_IVR0 Reset value 0x0028 0 AES_KEYR3 Reset value 0x0024 0 AES_KEYR2 Reset value 0x0020 0 AES_KEYR1 Reset value 0x001C 0 AES_KEYR0 Reset value 0 AES_DINR[31:0] 0 AES_DOUTR Reset value WRERR MODE[1:0] Reset value EN CCFIE 0 Res. DATATYPE[1:0] ERRIE 0 CHMOD[1:0] DMAINEN 0 Res. Res. DMAOUTEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AES_SR Res. 0x0004 Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. AES_CR Res. 0x0000 Register Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 67. AES register map 0 0 0 0 AES_IVR3[31:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. DocID025942 Rev 5 352/874 352 General-purpose timers (TIM2/TIM3) RM0377 16 General-purpose timers (TIM2/TIM3) 16.1 TIM2/TIM3 introduction The general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare and PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 16.3.15. 16.2 TIM2/TIM3 main features General-purpose TIMx timer features include: 353/874 16-bit (TIM2/3) up, down, up/down auto-reload counter. 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65535. Up to 4 independent channels for: – Input capture – Output compare – PWM generation (Edge- and Center-aligned modes) – One-pulse mode output Synchronization circuit to control the timer with external signals and to interconnect several timers. Interrupt/DMA generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal/external trigger) – Trigger event (counter start, stop, initialization or count by internal/external trigger) – Input capture – Output compare Supports incremental (quadrature) encoder and hall-sensor circuitry for positioning purposes Trigger input for external clock or cycle-by-cycle current management DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 70. General-purpose timer block diagram ,QWHUQDOFORFN&.B,17 7,0[&/.IURP5&& (75) (75 7,0[B(75 7ULJJHU FRQWUROOHU 75*2 3RODULW\VHOHFWLRQHGJH (753 ,QSXWILOWHU GHWHFWRUSUHVFDOHU ,75 ,75 ,75 ,75 WRRWKHUWLPHUV WR'$&$'& 7*, ,75 75& 75*, 6ODYH FRQWUROOHU 5HVHWHQDEOHXSFRXQW PRGH 7,)B(' (QFRGHU LQWHUIDFH 7,)3 7,)3 8 $XWRUHORDGUHJLVWHU 6WRSFOHDURUXSGRZQ &.B36& ;25 7, 7,0[B&+ 7,0[B&+ ,QSXWILOWHU HGJHGHWHFWRU 7, ,QSXWILOWHU HGJHGHWHFWRU 7, ,QSXWILOWHU HGJHGHWHFWRU 7,)3 7,)3 ,& 36& &.B&17 SUHVFDOHU &&, 8 3UHVFDOHU 75& 7,)3 7,)3 75& ,&36 &&, ,& 3UHVFDOHU 7,0[B&+ 7, 7,0[B&+ ,QSXWILOWHU HGJHGHWHFWRU ,& 3UHVFDOHU 75& 7,)3 7,)3 &&, &DSWXUH&RPSDUHUHJLVWHU 2&5() ,&36 &DSWXUH&RPSDUHUHJLVWHU 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+ 2&5() 2XWSXW 2& FRQWURO 7,0[B&+ 2XWSXW 2& FRQWURO 7,0[B&+ &&, 8 3UHVFDOHU 2XWSXW 2& FRQWURO &&, 8 ,&36 ,&36 2&5() &&, 8 &&, ,& 8 &17FRXQWHU &DSWXUH&RPSDUHUHJLVWHU &&, 7,)3 7,)3 8, &DSWXUH&RPSDUHUHJLVWHU 2&5() 75& (75) 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW'0$RXWSXW 069 DocID025942 Rev 5 354/874 420 General-purpose timers (TIM2/TIM3) RM0377 16.3 TIM2/TIM3 functional description 16.3.1 Time-base unit The main block of the programmable timer is a 16-bit with its related auto-reload register. The counter can count up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: Counter Register (TIMx_CNT) Prescaler Register (TIMx_PSC): Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow (or underflow when downcounting) and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit/32-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 71 and Figure 16.3.2 give some examples of the counter behavior when the prescaler ratio is changed on the fly: 355/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 71. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 72. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 DocID025942 Rev 5 356/874 420 General-purpose timers (TIM2/TIM3) 16.3.2 RM0377 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An Update event can be generated at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register) The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 73. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 357/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 74. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 75. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID025942 Rev 5 358/874 420 General-purpose timers (TIM2/TIM3) RM0377 Figure 76. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 77. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 359/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 78. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 069 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. DocID025942 Rev 5 360/874 420 General-purpose timers (TIM2/TIM3) RM0377 The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 79. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ FQWBXGI 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 80. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 361/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 81. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 82. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID025942 Rev 5 362/874 420 General-purpose timers (TIM2/TIM3) RM0377 Figure 83. Counter timing diagram, Update event when repetition counter is not used &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11"). In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or 363/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. Figure 84. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1. Here, center-aligned mode 1 is used (for more details refer to Section 16.4.1: TIMx control register 1 (TIMx_CR1) on page 397). DocID025942 Rev 5 364/874 420 General-purpose timers (TIM2/TIM3) RM0377 Figure 85. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 86. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 1RWH+HUHFHQWHUBDOLJQHGPRGHRULVXSGDWHGZLWKDQ8,)RQRYHUIORZ 069 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. 365/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 87. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 88. Counter timing diagram, Update event with ARPE=1 (counter underflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH UHJLVWHU )' 069 DocID025942 Rev 5 366/874 420 General-purpose timers (TIM2/TIM3) RM0377 Figure 89. Counter timing diagram, Update event with ARPE=1 (counter overflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH )' UHJLVWHU 069 16.3.3 Clock selection The counter clock can be provided by the following clock sources: Internal clock (CK_INT) External clock mode1: external input pin (TIx) External clock mode2: external trigger input (ETR) Internal trigger inputs (ITRx): using one timer as prescaler for another timer. Refer to : Using one timer as prescaler for another timer on page 390 for more details. Internal clock source (CK_INT) If the slave mode controller is disabled (SMS=000 in the TIMx_SMCR register), then the CEN, DIR (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except UG which remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 90 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. 367/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 90. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 External clock source mode 1 This mode is selected when SMS=111 in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 91. TI2 external clock connection example 7,0[B60&5 76>@ RU 7,) 7,) ,75[ 7,B(' 7, )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ 7,)3 7,)3 (75) RU RU [[ 75*, (75) &.B,17 ,&)>@ &&3 7,0[B&&05 7,0[B&&(5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 DocID025942 Rev 5 368/874 420 General-purpose timers (TIM2/TIM3) RM0377 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: Note: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S= ‘01 in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. 3. Select rising edge polarity by writing CC2P=0 and CC2NP=0 in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=111 in the TIMx_SMCR register. 5. Select TI2 as the input source by writing TS=110 in the TIMx_SMCR register. 6. Enable the counter by writing CEN=1 in the TIMx_CR1 register. For code example, refer to A.9.1: Upcounter on TI2 rising edge code example. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. Figure 92. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 369/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. Figure 93 gives an overview of the external trigger input block. Figure 93. External trigger input block RU 7,) 7,) (75 RU RU 75*, (75SLQ 'LYLGHU (753 I'76 )LOWHU GRZQFRXQWHU (75) &.B,17 (73 (736>@ (7)>@ 7,0[B60&5 7,0[B60&5 7,0[B60&5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. For code example, refer to A.9.2: Up counter on each 2 ETR rising edges code example. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. DocID025942 Rev 5 370/874 420 General-purpose timers (TIM2/TIM3) RM0377 Figure 94. Control circuit in external clock mode 2 I &.B,17 &17B(1 (75 (753 (75) &RXQWHUFORFN &.B,17 &.B36& &RXQWHUUHJLVWHU 069 16.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). The following figure gives an overview of one Capture/Compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). 371/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 95. Capture/compare channel (example: channel 1 input stage) 7,)B(' 7RWKHVODYHPRGHFRQWUROOHU 7,)B5LVLQJ 7, )LOWHU 7,) GRZQFRXQWHU I'76 (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 &&3&&13 ,&)>@ 75& 7,0[B&&(5 7,0[B&&05 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO IURPVODYHPRGH FRQWUROOHU ,&36 'LYLGHU ,& &&6>@ ,&36>@ &&( 7,0[B&&05 7,0[B&&(5 069 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 96. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5+ 6 5HDG&&5/ KLJK UHDGBLQBSURJUHVV &&6>@ ,&36 ZULWHBLQBSURJUHVV ,QSXW PRGH 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ LIELW 0&8SHULSKHUDOLQWHUIDFH 2XWSXW PRGH &17!&&5 &RXQWHU &&* &&6>@ 8(9 &RPSDUDWRU &&( &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU &DSWXUH ZULWH&&5/ IURPWLPH EDVHXQLW 2&3( 7,0[B&&05 &17 &&5 7,0[B(*5 069 DocID025942 Rev 5 372/874 420 General-purpose timers (TIM2/TIM3) RM0377 Figure 97. Output stage of capture/compare channel (channel 1) 7,0[B60&5 2&&6 2&5()B&/5 (75) 7RWKHPDVWHU PRGHFRQWUROOHU RFUHIBFOUBLQW &17!&&5 2XWSXW PRGH &17 &&5 FRQWUROOHU 2&5() 2XWSXW HQDEOH FLUFXLW 2& &&3 7,0[B&&(5 2&0>@ &&( 7,0B&&(5 7,0[B&&05 069 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 16.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to 0 or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to 0. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 373/874 1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to 01 in the TIMx_CCMR1 register. As soon as CC1S becomes different from 00, the channel is configured in input and the TIMx_CCR1 register becomes read-only. 2. Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) detected (sampled at fDTS frequency). Then write IC1F bits to 0011 in the TIMx_CCMR1 register. 3. Select the edge of the active transition on the TI1 channel by writing the CC1P and CC1NP bits to 00 in the TIMx_CCER register (rising edge in this case). 4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to 00 in the TIMx_CCMR1 register). 5. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register, and/or the DMA request by setting the CC1DE bit in the TIMx_DIER register. For code example, refer to A.9.3: Input capture configuration code example. When an input capture occurs: The TIMx_CCR1 register gets the value of the counter on the active transition. CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. An interrupt is generated depending on the CC1IE bit. A DMA request is generated depending on the CC1DE bit. For code example, refer to A.9.4: Input capture data management code example. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: IC interrupt and/or DMA requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. DocID025942 Rev 5 374/874 420 General-purpose timers (TIM2/TIM3) 16.3.6 RM0377 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: Two ICx signals are mapped on the same TIx input. These 2 ICx signals are active on edges with opposite polarity. One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): 1. Select the active input for TIMx_CCR1: write the CC1S bits to 01 in the TIMx_CCMR1 register (TI1 selected). 2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): write the CC1P to ‘0’ and the CC1NP bit to ‘0’ (active on rising edge). 3. Select the active input for TIMx_CCR2: write the CC2S bits to 10 in the TIMx_CCMR1 register (TI1 selected). 4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): write the CC2P bit to ‘1’ and the CC2NP bit to ’0’(active on falling edge). 5. Select the valid trigger input: write the TS bits to 101 in the TIMx_SMCR register (TI1FP1 selected). 6. Configure the slave mode controller in reset mode: write the SMS bits to 100 in the TIMx_SMCR register. 7. Enable the captures: write the CC1E and CC2E bits to ‘1 in the TIMx_CCER register. For code example, refer to A.9.5: PWM input configuration code example. Figure 98. PWM input mode timing 7, 7,0[B&17 7,0[B&&5 7,0[B&&5 ,&FDSWXUH ,&FDSWXUH UHVHWFRXQWHU ,&FDSWXUH SXOVHZLGWK PHDVXUHPHQW ,&FDSWXUH SHULRG PHDVXUHPHQW DL 375/874 DocID025942 Rev 5 RM0377 16.3.7 General-purpose timers (TIM2/TIM3) Forced output mode In output mode (CCxS bits = 00 in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCxREF/OCx) to its active level, you just need to write 101 in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCxREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. e.g.: CCxP=0 (OCx active high) => OCx is forced to high level. OCxREF signal can be forced low by writing the OCxM bits to 100 in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt and DMA requests can be sent accordingly. This is described in the Output Compare Mode section. 16.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=000), be set active (OCxM=001), be set inactive (OCxM=010) or can toggle (OCxM=011) on match. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). Sends a DMA request if the corresponding enable bit is set (CCxDE bit in the TIMx_DIER register, CCDS bit in the TIMx_CR2 register for the DMA request selection). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE and/or CCxDE bits if an interrupt and/or a DMA request is to be generated. 4. Select the output mode. For example, you must write OCxM=011, OCxPE=0, CCxP=0 and CCxE=1 to toggle OCx output pin when CNT matches CCRx, CCRx preload is not used, OCx is enabled and active high. 5. Enable the counter by setting the CEN bit in the TIMx_CR1 register. For code example, refer to A.9.7: Output compare configuration code example. DocID025942 Rev 5 376/874 420 General-purpose timers (TIM2/TIM3) RM0377 The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=0, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 99. Figure 99. Output compare mode, toggle on OC1. :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ 2&5() 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 069 16.3.9 PWM mode Pulse width modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing 110 (PWM mode 1) or ‘111 (PWM mode 2) in the OCxM bits in the TIMx_CCMRx register. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the auto-reload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. 377/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CCRx TIMx_CNT or TIMx_CNT TIMx_CCRx (depending on the direction of the counter). However, to comply with the OCREF_CLR functionality (OCREF can be cleared by an external event through the ETR signal until the next PWM period), the OCREF signal is asserted only: When the result of the comparison changes, or When the output compare mode (OCxM bits in TIMx_CCMRx register) switches from the “frozen” configuration (no comparison, OCxM=‘000) to one of the PWM modes (OCxM=‘110 or ‘111). This forces the PWM by software while the timer is running. The timer is able to generate PWM in edge-aligned mode or center-aligned mode depending on the CMS bits in the TIMx_CR1 register. PWM edge-aligned mode Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to Section : Upcounting mode on page 357. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT <TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1. If the compare value is 0 then OCxREF is held at ‘0. Figure 100 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. For code example, refer to A.9.8: Edge-aligned PWM configuration example. Figure 100. Edge-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU &&5[ 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 069 DocID025942 Rev 5 378/874 420 General-purpose timers (TIM2/TIM3) RM0377 Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to Section : Downcounting mode on page 360. In PWM mode 1, the reference signal OCxREF is low as long as TIMx_CNT>TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1. 0% PWM is not possible in this mode. PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00 (all the remaining configurations having the same effect on the OCxREF/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to Section : Center-aligned mode (up/down counting) on page 363. Figure 101 shows some center-aligned PWM waveforms in an example where: TIMx_ARR=8, PWM mode is the PWM mode 1, The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. For code example, refer to A.9.9: Center-aligned PWM configuration example. 379/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 101. Center-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU 2&[5() &&5[ &06 &06 &06 &&[,) 2&[5() &&5[ &06 RU &&[,) 2&[5() µ¶ &&5[ &&[,) 2&[5() &&5[! µ¶ &06 &06 &06 &&[,) 2&[5() &&5[ &&[,) &06 &06 &06 µ¶ &06 &06 &06 $,E Hints on using center-aligned mode: When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. DocID025942 Rev 5 380/874 420 General-purpose timers (TIM2/TIM3) 16.3.10 RM0377 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be: In upcounting: CNT<CCRx ARR (in particular, 0<CCRx), In downcounting: CNT>CCRx. Figure 102. Example of one-pulse mode. 7, 2&5() 2& &RXQWHU 7,0B$55 7,0B&&5 W'(/$< W38/6( W 069 For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Let’s use TI2FP2 as trigger 1: 1. Map TI2FP2 on TI2 by writing CC2S=01 in the TIMx_CCMR1 register. 2. TI2FP2 must detect a rising edge, write CC2P=0 and CC2NP=’0’ in the TIMx_CCER register. 3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=110 in the TIMx_SMCR register. 4. TI2FP2 is used to start the counter by writing SMS to ‘110 in the TIMx_SMCR register (trigger mode). For code example, refer to A.9.16: One-Pulse mode code example. 381/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). The tDELAY is defined by the value written in the TIMx_CCR1 register. The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1+1). Let’s say you want to build a waveform with a transition from ‘0 to ‘1 when a compare match occurs and a transition from ‘1 to ‘0 when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=111 in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=1 in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0 in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable: In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) is forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. For code example, refer to A.9.16: One-Pulse mode code example. 16.3.11 Clearing the OCxREF signal on an external event 1. The external trigger prescaler should be kept off: bits ETPS[1:0] in the TIMx_SMCR register are cleared to 00. 2. The external clock mode 2 must be disabled: bit ECE in the TIMx_SMCR register is cleared to 0. 3. The external trigger polarity (ETP) and the external trigger filter (ETF) can be configured according to the application’s needs. For code example, refer to A.9.10: ETR configuration to clear OCxREF code example. Figure 103 shows the behavior of the OCxREF signal when the ETRF input becomes high, for both values of the OCxCE enable bit. In this example, the timer TIMx is programmed in PWM mode. DocID025942 Rev 5 382/874 420 General-purpose timers (TIM2/TIM3) RM0377 Figure 103. Clearing TIMx OCxREF &&5[ &RXQWHU&17 (75) 2&[5() 2&[&( µ¶ 2&[5() 2&[&( µ¶ 2&[5()B&/5 EHFRPHVKLJK 2&[5()B&/5 VWLOOKLJK 069 1. In case of a PWM with a 100% duty cycle (if CCRx>ARR), OCxREF is enabled again at the next counter overflow. 16.3.12 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. CC1NP and CC2NP must be kept cleared. When needed, you can program the input filter as well. The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 68. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal. In this mode, the counter is modified automatically following the speed and the direction of the incremental encoder and its content, therefore, always represents the encoder’s 383/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. Table 68. Counting direction versus encoder signals Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) Rising Falling Rising Falling Counting on TI1 only High Down Up No Count No Count Low Up Down No Count No Count Counting on TI2 only High No Count No Count Up Down Low No Count No Count Down Up Counting on TI1 and TI2 High Down Up Up Down Low Up Down Down Up Active edge TI1FP1 signal TI2FP2 signal An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. Figure 104 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1) CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2) CC1P=0, CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1) CC2P=0, CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2) SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling edges) CEN= 1 (TIMx_CR1 register, Counter is enabled) For code example, refer to A.9.11: Encoder interface code example. DocID025942 Rev 5 384/874 420 General-purpose timers (TIM2/TIM3) RM0377 Figure 104. Example of counter operation in encoder interface mode IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU XS GRZQ XS 069 Figure 105 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 105. Example of encoder interface mode with TI1FP1 polarity inverted IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU GRZQ XS GRZQ 069 The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a Real-Time clock. 16.3.13 Timer input XOR function The TI1S bit in the TIMx_CR2 register, allows the input filter of channel 1 to be connected to the output of a XOR gate, combining the three input pins TIMx_CH1 to TIMx_CH3. The XOR output can be used with all the timer input functions such as trigger or input capture. 385/874 DocID025942 Rev 5 RM0377 16.3.14 General-purpose timers (TIM2/TIM3) Timers and external trigger synchronization The TIMx Timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = 01 in the TIMx_CCMR1 register. Write CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edges only). Configure the timer in reset mode by writing SMS=100 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. Start the counter by writing CEN=1 in the TIMx_CR1 register. For code example, refer to A.9.12: Reset mode code example. The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request, or a DMA request can be sent if enabled (depending on the TIE and TDE bits in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 106. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 DocID025942 Rev 5 386/874 420 General-purpose timers (TIM2/TIM3) RM0377 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: 1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=01 in TIMx_CCMR1 register. Write CC1P=1 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in gated mode by writing SMS=101 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. 3. Enable the counter by writing CEN=1 in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=0, whatever is the trigger input level). For code example, refer to A.9.13: Gated mode code example. The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. Figure 107. Control circuit in gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 1. The configuration “CCxP=CCxNP=1” (detection of both rising and falling edges) does not have any effect in gated mode because gated mode acts on a level and not on an edge. 387/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: 1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=0000). The capture prescaler is not used for triggering, so you don’t need to configure it. CC2S bits are selecting the input capture source only, CC2S=01 in TIMx_CCMR1 register. Write CC2P=1 and CC2NP=0 in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI2 as the input source by writing TS=110 in TIMx_SMCR register. For code example, refer to A.9.14: Trigger mode code example. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. Figure 108. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 DocID025942 Rev 5 388/874 420 General-purpose timers (TIM2/TIM3) RM0377 Slave mode: External Clock mode 2 + trigger mode The external clock mode 2 can be used in addition to another slave mode (except external clock mode 1 and encoder mode). In this case, the ETR signal is used as external clock input, and another input can be selected as trigger input when operating in reset mode, gated mode or trigger mode. It is recommended not to select ETR as TRGI through the TS bits of TIMx_SMCR register. In the following example, the upcounter is incremented at each rising edge of the ETR signal as soon as a rising edge of TI1 occurs: 1. 2. 3. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS=00: prescaler disabled – ETP=0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. Configure the channel 1 as follows, to detect rising edges on TI: – IC1F=0000: no filter. – The capture prescaler is not used for triggering and does not need to be configured. – CC1S=01in TIMx_CCMR1 register to select only the input capture source – CC1P=0 and CC1NP=0 in TIMx_CCER register to validate the polarity (and detect rising edge only). Configure the timer in trigger mode by writing SMS=110 in TIMx_SMCR register. Select TI1 as the input source by writing TS=101 in TIMx_SMCR register. For code example, refer to A.9.15: External clock mode 2 + trigger mode code example. A rising edge on TI1 enables the counter and sets the TIF flag. The counter then counts on ETR rising edges. The delay between the rising edge of the ETR signal and the actual reset of the counter is due to the resynchronization circuit on ETRP input. 389/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 109. Control circuit in external clock mode 2 + trigger mode 7, &(1&17B(1 (75 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) 069 16.3.15 Timer synchronization The TIMx timers are linked together internally for timer synchronization or chaining. When one Timer is configured in Master Mode, it can reset, start, stop or clock the counter of another Timer configured in Slave Mode. Figure 110: Master/Slave timer example presents an overview of the trigger selection and the master mode selection blocks. Note: The clock of the slave timer must be enabled prior to receive events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Using one timer as prescaler for another timer Figure 110. Master/Slave timer example 7,0[ 7,0\ &ORFN 76 006 606 8(9 3UHVFDOHU &RXQWHU 0DVWHU 75*2 PRGH FRQWURO ,75 6ODYH &.B36& PRGH FRQWURO 3UHVFDOHU &RXQWHU ,QSXW WULJJHU VHOHFWLRQ 069 DocID025942 Rev 5 390/874 420 General-purpose timers (TIM2/TIM3) RM0377 For example, you can configure Timer x to act as a prescaler for Timer y. Refer to Figure 110. To do this, follow the sequence below: 1. Configure Timer x in master mode so that it outputs a periodic trigger signal on each update event UEV. If you write MMS=010 in the TIMx_CR2 register, a rising edge is output on TRGO1 each time an update event is generated. 2. To connect the TRGO1 output of Timer x to Timer y, Timer y must be configured in slave mode using ITR1 as internal trigger. You select this through the TS bits in the TIMy_SMCR register (writing TS=000). 3. Then you put the slave mode controller in external clock mode 1 (write SMS=111 in the TIMy_SMCR register). This causes Timer y to be clocked by the rising edge of the periodic Timer x trigger signal (which correspond to the timer x counter overflow). 4. Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register). For code example, refer to A.9.17: Timer prescaling another timer code example. Note: If OCx is selected on Timer x as trigger output (MMS=1xx), its rising edge is used to clock the counter of timer y. Using one timer to enable another timer In this example, we control the enable of Timer y with the output compare 1 of Timer x. Refer to Figure 110 for connections. Timer y counts on the divided internal clock only when OC1REF of Timer x is high. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3). 1. Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIMx_CR2 register). 2. Configure the Timer x OC1REF waveform (TIMx_CCMR1 register). 3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR register). 4. Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register). 5. Enable Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register). 6. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register). For code example, refer to A.9.18: Timer enabling another timer code example. Note: 391/874 The counter 2 clock is not synchronized with counter 1, this mode only affects the Timer y counter enable signal. DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 111. Gating timer y with OC1REF of timer x &.B,17 7,0(5[2&5() 7,0(5[&17 )& 7,0(5\&17 )' )( )) 7,0(5\7,) :ULWH7,) 069 In the example in Figure 111, the Timer y counter and prescaler are not initialized before being started. So they start counting from their current value. It is possible to start from a given value by resetting both timers before starting Timer x. You can then write any value you want in the timer counters. The timers can easily be reset by software using the UG bit in the TIMx_EGR registers. In the next example, we synchronize Timer x and Timer y. Timer x is the master and starts from 0. Timer y is the slave and starts from 0xE7. The prescaler ratio is the same for both timers. Timer y stops when Timer x is disabled by writing ‘0 to the CEN bit in the TIMy_CR1 register: 1. Configure Timer x master mode to send its Output Compare 1 Reference (OC1REF) signal as trigger output (MMS=100 in the TIMx_CR2 register). 2. Configure the Timer x OC1REF waveform (TIMx_CCMR1 register). 3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIMy_SMCR register). 4. Configure Timer y in gated mode (SMS=101 in TIMy_SMCR register). 5. Reset Timer x by writing ‘1 in UG bit (TIMx_EGR register). 6. Reset Timer y by writing ‘1 in UG bit (TIMy_EGR register). 7. Initialize Timer y to 0xE7 by writing ‘0xE7’ in the timer y counter (TIMy_CNTL). 8. Enable Timer y by writing ‘1 in the CEN bit (TIMy_CR1 register). 9. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register). 10. Stop Timer x by writing ‘0 in the CEN bit (TIMx_CR1 register). For code example, refer to A.9.19: Master and slave synchronization code example. DocID025942 Rev 5 392/874 420 General-purpose timers (TIM2/TIM3) RM0377 Figure 112. Gating timer y with Enable of timer x &.B,17 7,0(5[&(1 &17B(1 7,0(5[&17B,1,7 7,0(5[&17 7,0(5\&17 $% ( ( ( 7,0(5\&17B,1,7 7,0(5\ZULWH&17 7,0(5\7,) :ULWH7,) 069 Using one timer to start another timer In this example, we set the enable of Timer y with the update event of Timer x. Refer to Figure 110 for connections. Timer y starts counting from its current value (which can be nonzero) on the divided internal clock as soon as the update event is generated by Timer x. When Timer y receives the trigger signal its CEN bit is automatically set and the counter counts until we write ‘0 to the CEN bit in the TIM2_CR1 register. Both counter clock frequencies are divided by 3 by the prescaler compared to CK_INT (fCK_CNT = fCK_INT/3). 1. 393/874 Configure Timer x master mode to send its Update Event (UEV) as trigger output (MMS=010 in the TIMx_CR2 register). 2. Configure the Timer x period (TIMx_ARR registers). 3. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIM2_SMCR register). 4. Configure Timer y in trigger mode (SMS=110 in TIM2_SMCR register). 5. Start Timer x by writing ‘1 in the CEN bit (TIMx_CR1 register). DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Figure 113. Triggering timer y with update of timer x &.B,17 7,0(5[8(9 7,0(5[&17 )' )( )) 7,0(5\&17 7,0(5\&(1 &17B(1 7,0(5\7,) :ULWH7,) 069 As in the previous example, you can initialize both counters before starting counting. Figure 114 shows the behavior with the same configuration as in Figure 113 but in trigger mode instead of gated mode (SMS=110 in the TIMy_SMCR register). Figure 114. Triggering timer y with Enable of timer x &.B,17 7,0(5[&(1 &17B(1 7,0(5[&17B,1,7 7,0(5[&17 7,0(5\&17 &' ( ( ( ($ 7,0(5\&17B,1,7 7,0(5\ ZULWH&17 7,0(5\7,) :ULWH7,) 069 DocID025942 Rev 5 394/874 420 General-purpose timers (TIM2/TIM3) RM0377 Starting 2 timers synchronously in response to an external trigger In this example, we set the enable of timer x when its TI1 input rises, and the enable of Timer y with the enable of Timer x. Refer to Figure 110 for connections. To ensure the counters are aligned, Timer x must be configured in Master/Slave mode (slave with respect to TI1, master with respect to Timer y): 1. Configure Timer x master mode to send its Enable as trigger output (MMS=001 in the TIMx_CR2 register). 2. Configure Timer x slave mode to get the input trigger from TI1 (TS=100 in the TIMx_SMCR register). 3. Configure Timer x in trigger mode (SMS=110 in the TIMx_SMCR register). 4. Configure the Timer x in Master/Slave mode by writing MSM=1 (TIMx_SMCR register). 5. Configure Timer y to get the input trigger from Timer x (TS=000 in the TIM2_SMCR register). 6. Configure Timer y in trigger mode (SMS=110 in the TIM2_SMCR register). For code example, refer to A.9.20: Two timers synchronized by an external trigger code example. When a rising edge occurs on TI1 (Timer x), both counters starts counting synchronously on the internal clock and both TIF flags are set. Note: In this example both timers are initialized before starting (by setting their respective UG bits). Both counters starts from 0, but you can easily insert an offset between them by writing any of the counter registers (TIMx_CNT). You can see that the master/slave mode insert a delay between CNT_EN and CK_PSC on timer x. Figure 115. Triggering timer x and y with timer x TI1 input &.B,17 7,0(5[7, 7,0(5[&(1 &17B(1 7,0(5[&.B36& 7,0(5[&17 7,0(5[7,) 7,0(5\&(1 &17B(1 7,0(5\&.B36& 7,0(5\&17 7,0(5\7,) 069 395/874 DocID025942 Rev 5 RM0377 16.3.16 General-purpose timers (TIM2/TIM3) Debug mode When the microcontroller enters debug mode (Cortex®-M0+ core - halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. DocID025942 Rev 5 396/874 420 General-purpose timers (TIM2/TIM3) 16.4 RM0377 TIM2/TIM3 registers Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions. The 32-bit peripheral registers have to be written by words (32 bits). All other peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 16.4.1 TIMx control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. 9 8 CKD[1:0] rw 7 6 ARPE rw rw 5 CMS rw rw 4 3 2 1 0 DIR OPM URS UDIS CEN rw rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (ETR, TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered 1: TIMx_ARR register is buffered Bits 6:5 CMS: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1) Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Note: This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the bit CEN) 397/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generate an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC, CCRx). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: External clock, gated mode and encoder mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. DocID025942 Rev 5 398/874 420 General-purpose timers (TIM2/TIM3) 16.4.2 RM0377 TIMx control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. TI1S rw 6 5 4 MMS[2:0] rw rw rw 3 2 1 0 CCDS Res. Res. Res. rw Bits 15:8 Reserved, must be kept at reset value. Bit 7 TI1S: TI1 selection 0: The TIMx_CH1 pin is connected to TI1 input 1: The TIMx_CH1, CH2 and CH3 pins are connected to the TI1 input (XOR combination) Bits 6:4 MMS: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Compare - OC3REF signal is used as trigger output (TRGO) 111: Compare - OC4REF signal is used as trigger output (TRGO) Note: The clock of the slave timer or ADC must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer. Bit 3 CCDS: Capture/compare DMA selection 0: CCx DMA request sent when CCx event occurs 1: CCx DMA requests sent when update event occurs Bits 2:0 Reserved, must be kept at reset value. 399/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) 16.4.3 TIMx slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 15 14 ETP ECE rw rw 13 12 11 ETPS[1:0] rw rw 10 9 8 ETF[3:0] rw rw 7 6 MSM rw rw rw 5 4 TS[2:0] rw rw 3 2 Res. rw 1 0 SMS[2:0] rw rw rw Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is noninverted, active at high level or rising edge 1: ETR is inverted, active at low level or falling edge Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. 1: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). 2: It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). 3: If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. Bits 13:12 ETPS: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of CK_INT frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 DocID025942 Rev 5 400/874 420 General-purpose timers (TIM2/TIM3) RM0377 Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful if we want to synchronize several timers on a single external event. Bits 6:4 TS: Trigger selection This bit-field selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0). 001: Internal Trigger 1 (ITR1). 010: Internal Trigger 2 (ITR2). 011: Reserved. 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: External Trigger input (ETRF) See Table 69: TIM2/TIM3 internal trigger connection on page 402 for more details on ITRx meaning for each Timer. Note: These bits must be changed only when they are not used (e.g. when SMS=000) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at ‘1’. Bits 2:0 SMS: Slave mode selection When external signals are selected the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input Control register and Control Register description. 000: Slave mode disabled - if CEN = ‘1 then the prescaler is clocked directly by the internal clock. 001: Encoder mode 1 - Counter counts up/down on TI2FP1 edge depending on TI1FP2 level. 010: Encoder mode 2 - Counter counts up/down on TI1FP2 edge depending on TI2FP1 level. 011: Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input. 100: Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers. 101: Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Both start and stop of the counter are controlled. 110: Trigger Mode - The counter starts at a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled. 111: External Clock Mode 1 - Rising edges of the selected trigger (TRGI) clock the counter. Note: The gated mode must not be used if TI1F_ED is selected as the trigger input (TS=100). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the gated mode checks the level of the trigger signal. The clock of the slave timer must be enabled prior to receiving events from the master timer, and must not be changed on-the-fly while triggers are received from the master timer." 401/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Table 69. TIM2/TIM3 internal trigger connection Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) ITR2 (TS = 010) TIM2 TIM21 TIM22 TIM3 TIM3 TIM2 TIM22 TIM21 16.4.4 TIMx DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 Res. TDE Res. rw 12 rw Bit 15 11 10 9 CC4DE CC3DE CC2DE CC1DE rw rw rw 8 7 6 5 4 3 2 1 0 UDE Res. TIE Res. CC4IE CC3IE CC2IE CC1IE UIE rw rw rw rw rw rw rw Reserved, must be kept at reset value. Bit 14 TDE: Trigger DMA request enable 0: Trigger DMA request disabled. 1: Trigger DMA request enabled. Bit 13 Reserved, always read as 0 Bit 12 CC4DE: Capture/Compare 4 DMA request enable 0: CC4 DMA request disabled. 1: CC4 DMA request enabled. Bit 11 CC3DE: Capture/Compare 3 DMA request enable 0: CC3 DMA request disabled. 1: CC3 DMA request enabled. Bit 10 CC2DE: Capture/Compare 2 DMA request enable 0: CC2 DMA request disabled. 1: CC2 DMA request enabled. Bit 9 CC1DE: Capture/Compare 1 DMA request enable 0: CC1 DMA request disabled. 1: CC1 DMA request enabled. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bit 7 Reserved, must be kept at reset value. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bit 5 Reserved, must be kept at reset value. Bit 4 CC4IE: Capture/Compare 4 interrupt enable 0: CC4 interrupt disabled. 1: CC4 interrupt enabled. Bit 3 CC3IE: Capture/Compare 3 interrupt enable 0: CC3 interrupt disabled 1: CC3 interrupt enabled DocID025942 Rev 5 402/874 420 General-purpose timers (TIM2/TIM3) RM0377 Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled 1: CC2 interrupt enabled Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled 1: CC1 interrupt enabled Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled 16.4.5 TIMx status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 Res. Res. Res. 12 10 9 CC4OF CC3OF CC2OF CC1OF rc_w0 Bit 15:13 11 rc_w0 rc_w0 8 7 Res. Res. rc_w0 6 5 4 3 2 1 TIF Res. CC4IF CC3IF CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 0 Reserved, must be kept at reset value. Bit 12 CC4OF: Capture/Compare 4 overcapture flag refer to CC1OF description Bit 11 CC3OF: Capture/Compare 3 overcapture flag refer to CC1OF description Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0. 0: No overcapture has been detected 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8:7 Reserved, must be kept at reset value. Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred 1: Trigger interrupt pending Bit 5 Reserved, must be kept at reset value. Bit 4 CC4IF: Capture/Compare 4 interrupt flag refer to CC1IF description Bit 3 CC3IF: Capture/Compare 3 interrupt flag refer to CC1IF description 403/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value, with some exception in center-aligned mode (refer to the CMS bits in the TIMx_CR1 register description). It is cleared by software. 0: No match 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow (in upcounting and up/down-counting modes) or underflow (in downcounting mode) If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred 1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1 which matches the selected polarity) Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: At overflow or underflow and if UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=0 and UDIS=0 in the TIMx_CR1 register. When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=0 and UDIS=0 in the TIMx_CR1 register. DocID025942 Rev 5 404/874 420 General-purpose timers (TIM2/TIM3) 16.4.6 RM0377 TIMx event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. TG Res. CC4G CC3G CC2G CC1G UG w w w w w w Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in TIMx_SR register. Related interrupt or DMA transfer can occur if enabled. Bit 5 Reserved, must be kept at reset value. Bit 4 CC4G: Capture/compare 4 generation refer to CC1G description Bit 3 CC3G: Capture/compare 3 generation refer to CC1G description Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: CC1IF flag is set, Corresponding interrupt or DMA request is sent if enabled. If channel CC1 is configured as input: The current value of the counter is captured in TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initialize the counter and generates an update of the registers. Note that the prescaler counter is cleared too (anyway the prescaler ratio is not affected). The counter is cleared if the center-aligned mode is selected or if DIR=0 (upcounting), else it takes the auto-reload value (TIMx_ARR) if DIR=1 (downcounting). 405/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) 16.4.7 TIMx capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits of this register have a different function in input and in output mode. For a given bit, OCxx describes its function when the channel is configured in output, ICxx describes its function when the channel is configured in input. So you must take care that the same bit can have a different meaning for the input stage and for the output stage. 15 14 OC2CE 13 12 OC2M[2:0] IC2F[3:0] rw rw rw 11 10 OC2PE OC2FE IC2PSC[1:0] rw rw rw 9 8 CC2S[1:0] rw 7 6 OC1CE rw 5 4 OC1M[2:0] IC1F[3:0] rw rw rw 3 2 OC1PE OC1FE IC1PSC[1:0] rw rw rw 1 0 CC1S[1:0] rw rw Output compare mode Bit 15 OC2CE: Output compare 2 clear enable Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bit 7 OC1CE: Output compare 1 clear enable OC1CE: Output Compare 1 Clear Enable 0: OC1Ref is not affected by the ETRF input 1: OC1Ref is cleared as soon as a High level is detected on ETRF input DocID025942 Rev 5 406/874 420 General-purpose timers (TIM2/TIM3) RM0377 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas OC1 and OC1N active level depends on CC1P and CC1NP bits. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 001: Set channel 1 to active level on match. OC1REF signal is forced high when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. OC1REF signal is forced low when the counter TIMx_CNT matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1. 100: Force inactive level - OC1REF is forced low. 101: Force active level - OC1REF is forced high. 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as TIMx_CNT>TIMx_CCR1 else active (OC1REF=1). 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else inactive. Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken in account immediately. 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded in the active register at each update event. Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on counter and CCR1 values even when the trigger is ON. The minimum delay to activate CC1 output when an edge occurs on the trigger input is 5 clock cycles. 1: An active edge on the trigger input acts like a compare match on CC1 output. Then, OC is set to the compare level independently from the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OCFE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output. 01: CC1 channel is configured as input, IC1 is mapped on TI1. 10: CC1 channel is configured as input, IC1 is mapped on TI2. 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 407/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output. 01: CC2 channel is configured as input, IC2 is mapped on TI2. 10: CC2 channel is configured as input, IC2 is mapped on TI1. 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bits 7:4 IC1F: Input capture 1 filter This bit-field defines the frequency used to sample TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 1000: fSAMPLING=fDTS/8, N=6 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 0010: fSAMPLING=fCK_INT, N=4 1011: fSAMPLING=fDTS/16, N=6 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 0101: fSAMPLING=fDTS/2, N=8 1110: fSAMPLING=fDTS/32, N=6 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1111: fSAMPLING=fDTS/32, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bit-field defines the ratio of the prescaler acting on CC1 input (IC1). The prescaler is reset as soon as CC1E=0 (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). DocID025942 Rev 5 408/874 420 General-purpose timers (TIM2/TIM3) 16.4.8 RM0377 TIMx capture/compare mode register 2 (TIMx_CCMR2) Address offset: 0x1C Reset value: 0x0000 Refer to the above CCMR1 register description. 15 14 OC4CE 13 12 OC4M[2:0] IC4F[3:0] rw rw rw 11 10 OC4PE OC4FE IC4PSC[1:0] rw rw rw 9 8 CC4S[1:0] rw 7 6 OC3CE rw 5 4 OC3M[2:0] IC3F[3:0] rw rw rw 3 2 OC3PE OC3FE IC3PSC[1:0] rw rw rw 1 0 CC3S[1:0] rw rw Output compare mode Bit 15 OC4CE: Output compare 4 clear enable Bits 14:12 OC4M: Output compare 4 mode Bit 11 OC4PE: Output compare 4 preload enable Bit 10 OC4FE: Output compare 4 fast enable Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). Bit 7 OC3CE: Output compare 3 clear enable Bits 6:4 OC3M: Output compare 3 mode Bit 3 OC3PE: Output compare 3 preload enable Bit 2 OC3FE: Output compare 3 fast enable Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 409/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Input capture mode Bits 15:12 IC4F: Input capture 4 filter Bits 11:10 IC4PSC: Input capture 4 prescaler Bits 9:8 CC4S: Capture/Compare 4 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC4 channel is configured as output 01: CC4 channel is configured as input, IC4 is mapped on TI4 10: CC4 channel is configured as input, IC4 is mapped on TI3 11: CC4 channel is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC4S bits are writable only when the channel is OFF (CC4E = 0 in TIMx_CCER). Bits 7:4 IC3F: Input capture 3 filter Bits 3:2 IC3PSC: Input capture 3 prescaler Bits 1:0 CC3S: Capture/Compare 3 selection This bit-field defines the direction of the channel (input/output) as well as the used input. 00: CC3 channel is configured as output 01: CC3 channel is configured as input, IC3 is mapped on TI3 10: CC3 channel is configured as input, IC3 is mapped on TI4 11: CC3 channel is configured as input, IC3 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: CC3S bits are writable only when the channel is OFF (CC3E = 0 in TIMx_CCER). 16.4.9 TIMx capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CC4NP Res. CC4P CC4E CC3NP Res. CC3P CC3E CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E rw rw rw rw rw rw rw rw rw rw rw rw Bit 15 CC4NP: Capture/Compare 4 output Polarity. Refer to CC1NP description Bit 14 Reserved, must be kept at reset value. Bit 13 CC4P: Capture/Compare 4 output Polarity. refer to CC1P description Bit 12 CC4E: Capture/Compare 4 output enable. refer to CC1E description Bit 11 CC3NP: Capture/Compare 3 output Polarity. refer to CC1NP description Bit 10 Reserved, must be kept at reset value. Bit 9 CC3P: Capture/Compare 3 output Polarity. refer to CC1P description Bit 8 CC3E: Capture/Compare 3 output enable. refer to CC1E description DocID025942 Rev 5 410/874 420 General-purpose timers (TIM2/TIM3) RM0377 Bit 7 CC2NP: Capture/Compare 2 output Polarity. refer to CC1NP description Bit 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity. refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable. refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 output Polarity. CC1 channel configured as output: CC1NP must be kept cleared in this case. CC1 channel configured as input: This bit is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity. refer to CC1P description. Bit 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high 1: OC1 active low CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. 11: noninverted/both edges Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. Bit 0 CC1E: Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active 1: On - OC1 signal is output on the corresponding output pin CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled 1: Capture enabled Table 70. Output control bit for standard OCx channels CCxE bit 411/874 OCx output state 0 Output Disabled (OCx=0, OCx_EN=0) 1 OCx=OCxREF + Polarity, OCx_EN=1 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Note: The state of the external I/O pins connected to the standard OCx channels depends on the OCx channel state and the GPIO registers. 16.4.10 TIMx counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Low counter value 16.4.11 TIMx prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded in the active prescaler register at each update event. 16.4.12 TIMx auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw Bits 15:0 rw rw rw rw rw rw ARR[15:0]: Low Auto-reload value ARR is the value to be loaded in the actual auto-reload register. Refer to the Section 16.3.1: Time-base unit on page 355 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID025942 Rev 5 412/874 420 General-purpose timers (TIM2/TIM3) 16.4.13 RM0377 TIMx capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR1[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Low Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded in the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (bit OC1PE). Else the preload value is copied in the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signaled on OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 16.4.14 TIMx capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR2[15:0] rw rw Bits 15:0 CCR2[15:0]: Low Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded in the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (bit OC2PE). Else the preload value is copied in the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 413/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) 16.4.15 TIMx capture/compare register 3 (TIMx_CCR3) Address offset: 0x3C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR3[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR3[15:0]: Low Capture/Compare value If channel CC3 is configured as output: CCR3 is the value to be loaded in the actual capture/compare 3 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR3 register (bit OC3PE). Else the preload value is copied in the active capture/compare 3 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC3 output. If channel CC3is configured as input: CCR3 is the counter value transferred by the last input capture 3 event (IC3). 16.4.16 TIMx capture/compare register 4 (TIMx_CCR4) Address offset: 0x40 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR4[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR4[15:0]: Low Capture/Compare value 1. if CC4 channel is configured as output (CC4S bits): CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit OC4PE). Else the preload value is copied in the active capture/compare 4 register when an update event occurs. The active capture/compare register contains the value to be compared to the counter TIMx_CNT and signalled on OC4 output. 2. if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register): CCR4 is the counter value transferred by the last input capture 4 event (IC4). DocID025942 Rev 5 414/874 420 General-purpose timers (TIM2/TIM3) 16.4.17 RM0377 TIMx DMA control register (TIMx_DCR) Address offset: 0x48 Reset value: 0x0000 15 14 13 Res. Res. Res. 12 11 10 9 8 DBL[4:0] rw rw rw rw 7 6 5 Res. Res. Res. rw 4 3 2 1 0 rw rw DBA[4:0] rw rw rw Bits 15:13 Reserved, must be kept at reset value. Bits 12:8 DBL[4:0]: DMA burst length This 5-bit vector defines the number of DMA transfers (the timer recognizes a burst transfer when a read or a write access is done to the TIMx_DMAR address). 00000: 1 transfer, 00001: 2 transfers, 00010: 3 transfers, ... 10001: 18 transfers. Bits 7:5 Reserved, must be kept at reset value. Bits 4:0 DBA[4:0]: DMA base address This 5-bit vector defines the base-address for DMA transfers (when read/write access are done through the TIMx_DMAR address). DBA is defined as an offset starting from the address of the TIMx_CR1 register. Example: 00000: TIMx_CR1, 00001: TIMx_CR2, 00010: TIMx_SMCR, ... Example: Let us consider the following transfer: DBL = 7 transfers & DBA = TIMx_CR1. In this case the transfer is done to/from 7 registers starting from the TIMx_CR1 address. 16.4.18 TIMx DMA address for full transfer (TIMx_DMAR) Address offset: 0x4C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw DMAB[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 DMAB[15:0]: DMA register for burst accesses A read or write operation to the DMAR register accesses the register located at the address (TIMx_CR1 address) + (DBA + DMA index) x 4 where TIMx_CR1 address is the address of the control register 1, DBA is the DMA base address configured in TIMx_DCR register, DMA index is automatically controlled by the DMA transfer, and ranges from 0 to DBL (DBL configured in TIMx_DCR). 415/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) Example of how to use the DMA burst feature In this example the timer DMA burst feature is used to update the contents of the CCRx registers (x = 2, 3, 4) with the DMA transferring half words into the CCRx registers. This is done in the following steps: 1. Configure the corresponding DMA channel as follows: – DMA channel peripheral address is the DMAR register address – DMA channel memory address is the address of the buffer in the RAM containing the data to be transferred by DMA into CCRx registers. – Number of data to transfer = 3 (See note below). – Circular mode disabled. 2. Configure the DCR register by configuring the DBA and DBL bit fields as follows: DBL = 3 transfers, DBA = 0xE. 3. Enable the TIMx update DMA request (set the UDE bit in the DIER register). 4. Enable TIMx 5. Enable the DMA channel For code example, refer to A.9.21: DMA burst feature code example. Note: This example is for the case where every CCRx register to be updated once. If every CCRx register is to be updated twice for example, the number of data to transfer should be 6. Let's take the example of a buffer in the RAM containing data1, data2, data3, data4, data5 and data6. The data is transferred to the CCRx registers as follows: on the first update DMA request, data1 is transferred to CCR2, data2 is transferred to CCR3, data3 is transferred to CCR4 and on the second update DMA request, data4 is transferred to CCR2, data5 is transferred to CCR3 and data6 is transferred to CCR4. DocID025942 Rev 5 416/874 420 General-purpose timers (TIM2/TIM3) 16.4.19 RM0377 TIM2 option register (TIM2_OR) Address offset: 0x50 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4 3 2 TI4_RMP rw rw 1 0 ETR_RMP rw rw rw Bits 15:5 Reserved, must be kept at reset value. Bits 4:3 TI4_RMP: Internal trigger (TI4 connected to TIM2_CH4) remap This bit is set and cleared by software. 01: TIM2 TI4 input connected to COMP2_OUT 10: TIM2 TI4 input connected to COMP1_OUT others: TIM2 TI4 input connected to ORed GPIOs. Refer to the Alternate function mapping table in the device datasheets. Bits 2:0 ETR_RMP: Timer2 ETR remap This bit is set and cleared by software. 111: TIM2 ETR input is connected to COMP1_OUT 110: TIM2 ETR input is connected to COMP2_OUT 101: TIM2 ETR input is connected to LSE 011: TIM2 ETR input is connected to HSI16 when HSI16OUTEN bit is set in Clock control register (RCC_CR) (except for category 3 devices) others: TIM2 ETR input is connected to ORed GPIOs. Refer to the Alternate function mapping table in the device datasheets 417/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM2/TIM3) 16.4.20 TIM3 option register (TIM3_OR) Address offset: 0x50 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 4 3 2 TI_RMP rw rw 1 0 ETR_RMP rw rw rw Bits 15:5 Reserved, must be kept at reset value. Bit 4 TI_RMP: Timer3 remapping on PC9 This bit is set and cleared by software. 1: TIM3_CH4 selected 0: Reserved Bit 3 TI_RMP: Timer3 remap on PB5 This bit is set and cleared by software. 1: TIM3_CH2 selected 0: TIM22_CH2 selected Bit 2 TI_RMP: Timer3 TI remap This bit is set and cleared by software. 1: TIM3_TI1 input is connected to PE3, PA6, PC6 or PB4 0: Reserved Bits 1:0 ETR_RMP: Timer3 ETR remap These bits are set and cleared by software. others configurations: TIM3_ETR input is connected to PE2 or PD2 DocID025942 Rev 5 418/874 420 General-purpose timers (TIM2/TIM3) 16.5 RM0377 TIMx register map TIMx registers are mapped as described in the table below: Res. Res. ARPE 0 0 0 0 0 0 0 0 0 0 TIMx_DIER Res. Res. TIE Res. 0 0 0 Reset value 0 TIMx_CCMR2 Input Capture mode 0 0 0 OC4M [2:0] 0 0 0 0 0 OC4FE 0 0 0 IC4 PSC [1:0] 0 0 0 CC4S [1:0] 0 0 UIE UG 0 CC1G 0 CC2G 0 0 0 0 0 0 OC1FE 0 CC3G 0 OC1PE UIF CC1IE 0 CC1IF CC2IE 0 CC2IF CC3IE 0 CC3IF CC4IE 0 CC4IF Res. Res. 0 0 0 0 0 0 OC3M [2:0] 0 0 0 0 0 IC3 PSC [1:0] 0 0 0 CC3S [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIMx_CCER CC3P CC3E CC2NP Res. Res. Reset value 0 0 0 0 0 0 0 TIMx_CNT 0 0 0 0 0 0 0 0 0 0 0 CC1E 0 CC1P 0 CC1NP 0 CC2E Reset value Res. CC3S [1:0] CC3NP IC3F[3:0] 0 CC1S [1:0] 0 0 CC1S [1:0] CC4E CC4S [1:0] 0 0 IC1 PSC [1:0] IC1F[3:0] 0 0 0 OC1M [2:0] 0 0 CC4G OC1CE 0 0 CC4P IC4F[3:0] 0 CC2S [1:0] OC4PE Reset value OC4CE IC2F[3:0] TIMx_CCMR2 Output Compare mode 0 IC2 PSC [1:0] SMS[2:0] OC3FE 0 CC2S [1:0] OC3CE OC2M [2:0] OC2FE 0 OC2PE OC2CE Reset value TIMx_CCMR1 Input Capture mode 0 0 0 0 0 0 0 0 CNT[15:0] 0 0 0 0 0 0 0 TIMx_PSC Reset value 419/874 TG Res. 0 0 TIMx_CCMR1 Output Compare mode Reset value 0x28 TIF UDE Res. 0 Res. 0 TS[2:0] 0 Res. CC1DE CC1OF 0 Res. CC2DE CC2OF 0 Res. CC3DE 0 CC3OF 0 Res. CC4DE 0 CC4OF Res. Res. Res. TIMx_EGR 0 Res. Res. Res. Res. TIMx_SR 0 Res. 0 TDE MSM ECE 0 0 CC2P 0x24 0 0 0 0 Res. 0x20 0 0 0 MMS[2:0] 0 0 0 CC4NP 0x1C 0 0 ETF[3:0] Reset value 0x18 0 Reset value Reset value 0x14 CMS[1:0] TIMx_SMCR Reset value 0x10 0 ETP 0x0C 1 Res. 0x08 0 ETPS [1:0] Reset value 2 OC3PE Res. Res. 0 3 CEN Res. Res. Res. TIMx_CR2 Res. 0x04 Res. Reset value 4 Res. Res. CKD [1:0] 5 UDIS TIMx_CR1 6 Res. 7 URS 8 Res. 9 OPM 10 CCDS 11 DIR 12 TI1S 13 Res. 14 Res. 15 Res. 0x00 Register Res. Table 71. TIM2/3 register map and reset values Offset 0 0 PSC[15:0] 0 0 0 0 0 0 0 DocID025942 Rev 5 0 0 RM0377 General-purpose timers (TIM2/TIM3) 15 14 13 12 11 10 0 0 0 0 0 0 0 0 0 0 0 0 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CCR2[15:0] 0 0 0 0 0 0 0 0 0 CCR3[15:0] 0 0 0 0 0 0 0 TIMx_CCR4 0 0 CCR4[15:0] 0 0 0 0 0 0 0 0 Res. Reset value DBL[4:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TIM2_OR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value Res. Res. Res. Res. Res. Res. Res. Res. Res. TIM3_OR Res. 0x50 0 Res. Reset value ETR_RMP Reset value Res. DMAB[15:0] Res. TIMx_DMAR 0 DBA[4:0] TI4_RMP TIMx_DCR Res. Res. Res. 0x44 0x50 0 0 TIMx_CCR3 Reset value 0x4C 5 CCR1[15:0] TIMx_CCR2 Reset value 0x48 0 TIMx_CCR1 Reset value 0x40 6 Res. Reset value 0x3C 7 ARR[15:0] 0x30 0x38 8 TIMx_ARR Reset value 0x34 9 Res. 0x2C Register Res. Offset Res. Table 71. TIM2/3 register map and reset values (continued) TI_RMP 0 0 0 ETR_RMP 0 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. DocID025942 Rev 5 420/874 420 General-purpose timers (TIM21/22) RM0377 17 General-purpose timers (TIM21/22) 17.1 Introduction The TIM21/22 general-purpose timers consist of a 16-bit auto-reload counter driven by a programmable prescaler. They may be used for a variety of purposes, including measuring the pulse lengths of input signals (input capture) or generating output waveforms (output compare, PWM). Pulse lengths and waveform periods can be modulated from a few microseconds to several milliseconds using the timer prescaler and the RCC clock controller prescalers. The TIM21/22 timers are completely independent, and do not share any resources. They can be synchronized together as described in Section 17.3.14. 17.2 TIM21/22 main features 17.2.1 TIM21/22 main features The features of the TIM21/22 general-purpose timer include: 421/874 16-bit up, down, up/down, auto-reload counter 16-bit programmable prescaler used to divide the counter clock frequency by any factor between 1 and 65535 (can be changed “on the fly”) Up to 2 independent channels for: – Input capture – Output compare – PWM generation (edge- and center-aligned mode) – One-pulse mode output Synchronization circuit to control the timer with external signals and to interconnect several timers together Interrupt generation on the following events: – Update: counter overflow/underflow, counter initialization (by software or internal trigger) – Trigger event (counter start, stop, initialization or count by internal trigger) – Input capture – Output compare DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Figure 116. General-purpose timer block diagram (TIM21/22) ,QWHUQDOFORFN&.B,17 (75) (75 7,0[B(75 3RODULW\VHOHFWLRQHGJH ,75 ,75 (753 ,QSXWILOWHU 7*, ,75 75& 75*, 7ULJJHU FRQWUROOHU 75*2 6ODYH 5HVHWHQDEOHXSFRXQW FRQWUROOHU PRGH 7,)B(' (QFRGHU LQWHUIDFH 7,)3 7,)3 8 $XWRUHORDGUHJLVWHU 6WRS&OHDU &.B36& 7,0[B&+ 7,0[B&+ 7, 7, ,QSXWILOWHU HGJHGHWHFWRU ,QSXWILOWHU HGJHGHWHFWRU 7,)3 7,)3 ,& 36& &.B&17 SUHVFDOHU &&, 8 3UHVFDOHU 75& 7,)3 7,)3 75& ,&36 &17FRXQWHU &DSWXUH&RPSDUHUHJLVWHU &&, 8 ,& 3UHVFDOHU ,&36 8, 8 &&, 2&5() 2XWSXW FRQWURO 2& 7,0[B&+ &&, &DSWXUH&RPSDUHUHJLVWHU 2&5() 2XWSXW 2& FRQWURO 7,0[B&+ 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (75) (YHQW ,QWHUUXSW 06Y9 DocID025942 Rev 5 422/874 475 General-purpose timers (TIM21/22) RM0377 17.3 TIM21/22 functional description 17.3.1 Time-base unit The main block of the timer is a 16-bit counter with its related auto-reload register. The counters counts up, down or both up and down but also down or both up and down. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: Counter register (TIMx_CNT) Prescaler register (TIMx_PSC) Auto-reload register (TIMx_ARR) The auto-reload register is preloaded. Writing to or reading from the auto-reload register accesses the preload register. The content of the preload register are transferred into the shadow register permanently or at each update event (UEV), depending on the auto-reload preload enable bit (ARPE) in TIMx_CR1 register. The update event is sent when the counter reaches the overflow and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detailed for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in TIMx_CR1 register is set (refer also to the slave mode controller description to get more details on counter enabling). Note that the counter starts counting 1 clock cycle after setting the CEN bit in the TIMx_CR1 register. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as this control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 118 and Figure 119 give some examples of the counter behavior when the prescaler ratio is changed on the fly. 423/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Figure 117. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 DocID025942 Rev 5 424/874 475 General-purpose timers (TIM21/22) RM0377 Figure 118. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 17.3.2 Counter modes Upcounting mode In upcounting mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. Setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller on TIM21/22) also generates an update event. The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter restarts from 0, as well as the counter of the prescaler (but the prescale rate does not change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. 425/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): The auto-reload shadow register is updated with the preload value (TIMx_ARR), The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 119. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID025942 Rev 5 426/874 475 General-purpose timers (TIM21/22) RM0377 Figure 120. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 121. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 427/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Figure 122. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 123. Counter timing diagram, update event when ARPE=0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 DocID025942 Rev 5 428/874 475 General-purpose timers (TIM21/22) RM0377 Figure 124. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 069 Downcounting mode In downcounting mode, the counter counts from the auto-reload value (content of the TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a counter underflow event. An Update event can be generate at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until UDIS bit has been written to 0. However, the counter restarts from the current auto-reload value, whereas the counter of the prescaler restarts from 0 (but the prescale rate doesn’t change). In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupts when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): 429/874 The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that the auto-reload is updated before the counter is reloaded, so that the next period is the expected one. DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR=0x36. Figure 125. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ FQWBXGI 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 126. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID025942 Rev 5 430/874 475 General-purpose timers (TIM21/22) RM0377 Figure 127. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 128. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 431/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Center-aligned mode (up/down counting) In center-aligned mode, the counter counts from 0 to the auto-reload value (content of the TIMx_ARR register) – 1, generates a counter overflow event, then counts from the autoreload value down to 1 and generates a counter underflow event. Then it restarts counting from 0. Center-aligned mode is active when the CMS bits in TIMx_CR1 register are not equal to '00'. The Output compare interrupt flag of channels configured in output is set when: the counter counts down (Center aligned mode 1, CMS = "01"), the counter counts up (Center aligned mode 2, CMS = "10") the counter counts up and down (Center aligned mode 3, CMS = "11"). In this mode, the direction bit (DIR from TIMx_CR1 register) cannot be written. It is updated by hardware and gives the current direction of the counter. The update event can be generated at each counter overflow and at each counter underflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller) also generates an update event. In this case, the counter restarts counting from 0, as well as the counter of the prescaler. The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1 register. This is to avoid updating the shadow registers while writing new values in the preload registers. Then no update event occurs until the UDIS bit has been written to 0. However, the counter continues counting up and down, based on the current auto-reload value. In addition, if the URS bit (update request selection) in TIMx_CR1 register is set, setting the UG bit generates an update event UEV but without setting the UIF flag (thus no interrupt or DMA request is sent). This is to avoid generating both update and capture interrupt when clearing the counter on the capture event. When an update event occurs, all the registers are updated and the update flag (UIF bit in TIMx_SR register) is set (depending on the URS bit): The buffer of the prescaler is reloaded with the preload value (content of the TIMx_PSC register). The auto-reload active register is updated with the preload value (content of the TIMx_ARR register). Note that if the update source is a counter overflow, the autoreload is updated before the counter is reloaded, so that the next period is the expected one (the counter is loaded with the new value). The following figures show some examples of the counter behavior for different clock frequencies. DocID025942 Rev 5 432/874 475 General-purpose timers (TIM21/22) RM0377 Figure 129. Counter timing diagram, internal clock divided by 1, TIMx_ARR=0x6 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 1. Here, center-aligned mode 1 is used (for more details refer to Section 17.4.1: TIM21/22 control register 1 (TIMx_CR1) on page 457). Figure 130. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 433/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Figure 131. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 1RWH+HUHFHQWHUBDOLJQHGPRGHRULVXSGDWHGZLWKDQ8,)RQRYHUIORZ 069 1. Center-aligned mode 2 or 3 is used with an UIF on overflow. Figure 132. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID025942 Rev 5 434/874 475 General-purpose timers (TIM21/22) RM0377 Figure 133. Counter timing diagram, Update event with ARPE=1 (counter underflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHUXQGHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH UHJLVWHU )' 069 Figure 134. Counter timing diagram, Update event with ARPE=1 (counter overflow) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )' :ULWHDQHZYDOXHLQ7,0[B$55 $XWRUHORDGDFWLYH )' UHJLVWHU 069 435/874 DocID025942 Rev 5 RM0377 17.3.3 General-purpose timers (TIM21/22) Clock selection The counter clock can be provided by the following clock sources: Internal clock (CK_INT) External clock mode1: external input pin (TIx) External clock mode2: external trigger input (ETR connected internally to LSE) Internal trigger inputs (ITRx): connecting the trigger output from another timer. Refer to Section : Using one timer as prescaler for another timer for more details. Internal clock source (CK_INT) The internal clock source is selected when the slave mode controller is disabled (SMS=’000’). The CEN bit in the TIMx_CR1 register and the UG bit in the TIMx_EGR register are then used as control bits and can be changed only by software (except for UG which remains cleared). As soon as the CEN bit is programmed to 1, the prescaler is clocked by the internal clock CK_INT. Figure 135 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. Figure 135. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 DocID025942 Rev 5 436/874 475 General-purpose timers (TIM21/22) RM0377 External clock source mode 1 This mode is selected when SMS=’111’ in the TIMx_SMCR register. The counter can count at each rising or falling edge on a selected input. Figure 136. TI2 external clock connection example 7,0[B60&5 76>@ RU 7,) 7,) ,75[ 7,B(' 7, )LOWHU (GJH GHWHFWRU 7,)B5LVLQJ 7,)B)DOOLQJ 7,)3 7,)3 (75) RU RU [[ 75*, (75) &.B,17 ,&)>@ &&3 7,0[B&&05 7,0[B&&(5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 For example, to configure the upcounter to count in response to a rising edge on the TI2 input, use the following procedure: 1. Configure channel 2 to detect rising edges on the TI2 input by writing CC2S = ‘01’ in the TIMx_CCMR1 register. 2. Configure the input filter duration by writing the IC2F[3:0] bits in the TIMx_CCMR1 register (if no filter is needed, keep IC2F=’0000’). 3. Select the rising edge polarity by writing CC2P=’0’ and CC2NP=’0’ in the TIMx_CCER register. 4. Configure the timer in external clock mode 1 by writing SMS=’111’ in the TIMx_SMCR register. 5. Select TI2 as the trigger input source by writing TS=’110’ in the TIMx_SMCR register. 6. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register. For code example, refer to A.9.1: Upcounter on TI2 rising edge code example. Note: 437/874 The capture prescaler is not used for triggering, so you don’t need to configure it. When a rising edge occurs on TI2, the counter counts once and the TIF flag is set. The delay between the rising edge on TI2 and the actual clock of the counter is due to the resynchronization circuit on TI2 input. DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Figure 137. Control circuit in external clock mode 1 7, &17B(1 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 External clock source mode 2 This mode is selected by writing ECE=1 in the TIMx_SMCR register. The counter can count at each rising or falling edge on the external trigger input ETR. The Figure 138 gives an overview of the external trigger input block. Figure 138. External trigger input block RU 7,) 7,) (75 RU RU 75*, (75SLQ 'LYLGHU (753 I'76 )LOWHU GRZQFRXQWHU (75) &.B,17 (73 (736>@ (7)>@ 7,0[B60&5 7,0[B60&5 7,0[B60&5 LQWHUQDOFORFN (QFRGHU PRGH ([WHUQDOFORFN PRGH ([WHUQDOFORFN PRGH &.B36& ,QWHUQDOFORFN PRGH (&( 606>@ 7,0[B60&5 069 DocID025942 Rev 5 438/874 475 General-purpose timers (TIM21/22) RM0377 For example, to configure the upcounter to count each 2 rising edges on ETR, use the following procedure: 1. As no filter is needed in this example, write ETF[3:0]=0000 in the TIMx_SMCR register. 2. Set the prescaler by writing ETPS[1:0]=01 in the TIMx_SMCR register 3. Select rising edge detection on the ETR pin by writing ETP=0 in the TIMx_SMCR register 4. Enable external clock mode 2 by writing ECE=1 in the TIMx_SMCR register. 5. Enable the counter by writing CEN=1 in the TIMx_CR1 register. For code example, refer to A.9.2: Up counter on each 2 ETR rising edges code example. The counter counts once each 2 ETR rising edges. The delay between the rising edge on ETR and the actual clock of the counter is due to the resynchronization circuit on the ETRP signal. Figure 139. Control circuit in external clock mode 2 I &.B,17 &17B(1 (75 (753 (75) &RXQWHUFORFN &.B,17 &.B36& &RXQWHUUHJLVWHU 069 17.3.4 Capture/compare channels Each Capture/Compare channel is built around a capture/compare register (including a shadow register), a input stage for capture (with digital filter, multiplexing and prescaler) and an output stage (with comparator and output control). Figure 140 to Figure 142 give an overview of one capture/compare channel. The input stage samples the corresponding TIx input to generate a filtered signal TIxF. Then, an edge detector with polarity selection generates a signal (TIxFPx) which can be used as trigger input by the slave mode controller or as the capture command. It is prescaled before the capture register (ICxPS). 439/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Figure 140. Capture/compare channel (example: channel 1 input stage) 7,)B(' 7RWKHVODYHPRGHFRQWUROOHU 7,)B5LVLQJ 7, )LOWHU 7,) GRZQFRXQWHU I'76 (GJH GHWHFWRU 7,)B)DOOLQJ 7,)3 7,)3 &&3&&13 ,&)>@ 7,0[B&&(5 7,0[B&&05 7,)B5LVLQJ IURPFKDQQHO 7,)B)DOOLQJ IURPFKDQQHO ,& 75& IURPVODYHPRGH FRQWUROOHU ,&36 'LYLGHU &&6>@ ,&36>@ &&( 7,0[B&&05 7,0[B&&(5 069 The output stage generates an intermediate waveform which is then used for reference: OCxRef (active high). The polarity acts at the end of the chain. Figure 141. Capture/compare channel 1 main circuit $3%%XV 5HDG&&5+ 6 5HDG&&5/ KLJK UHDGBLQBSURJUHVV &&6>@ ,&36 ZULWHBLQBSURJUHVV ,QSXW PRGH 6 ZULWH&&5+ &DSWXUHFRPSDUHSUHORDGUHJLVWHU 5 5 FRPSDUHBWUDQVIHU FDSWXUHBWUDQVIHU &&6>@ ORZ LIELW 0&8SHULSKHUDOLQWHUIDFH 2XWSXW PRGH &17!&&5 &RXQWHU &&* &&6>@ 8(9 &RPSDUDWRU &&( &&6>@ 2&3( &DSWXUHFRPSDUHVKDGRZUHJLVWHU &DSWXUH ZULWH&&5/ IURPWLPH EDVHXQLW 2&3( 7,0B&&05 &17 &&5 7,0B(*5 069 DocID025942 Rev 5 440/874 475 General-purpose timers (TIM21/22) RM0377 Figure 142. Output stage of capture/compare channel (channel 1 and 2) (75) 7RWKHPDVWHU PRGHFRQWUROOHU &17!&&5 &17 &&5 2XWSXW PRGH FRQWUROOHU 2&[B5() 2XWSXW HQDEOH FLUFXLW 2&[ &&[3 2&[0>@ 7,0[B&&05 7,0[B&&(5 &&[( 7,0[B&&(5 06Y9 The capture/compare block is made of one preload register and one shadow register. Write and read always access the preload register. In capture mode, captures are actually done in the shadow register, which is copied into the preload register. In compare mode, the content of the preload register is copied into the shadow register which is compared to the counter. 17.3.5 Input capture mode In Input capture mode, the Capture/Compare Registers (TIMx_CCRx) are used to latch the value of the counter after a transition detected by the corresponding ICx signal. When a capture occurs, the corresponding CCXIF flag (TIMx_SR register) is set and an interrupt or a DMA request can be sent if they are enabled. If a capture occurs while the CCxIF flag was already high, then the over-capture flag CCxOF (TIMx_SR register) is set. CCxIF can be cleared by software by writing it to ‘0’ or by reading the captured data stored in the TIMx_CCRx register. CCxOF is cleared when you write it to ‘0’. The following example shows how to capture the counter value in TIMx_CCR1 when TI1 input rises. To do this, use the following procedure: 441/874 1. Select the active input: TIMx_CCR1 must be linked to the TI1 input, so write the CC1S bits to ‘01’ in the TIMx_CCMR1 register. As soon as CC1S becomes different from ‘00’, the channel is configured in input mode and the TIMx_CCR1 register becomes readonly. 2. Program the input filter duration you need with respect to the signal you connect to the timer (when the input is one of the TIx (ICxF bits in the TIMx_CCMRx register). Let’s imagine that, when toggling, the input signal is not stable during at must 5 internal clock cycles. We must program a filter duration longer than these 5 clock cycles. We can validate a transition on TI1 when 8 consecutive samples with the new level have been DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) detected (sampled at fDTS frequency). Then write IC1F bits to ‘0011’ in the TIMx_CCMR1 register. 3. Select the edge of the active transition on the TI1 channel by programming CC1P and CC1NP bits to ‘00’ in the TIMx_CCER register (rising edge in this case). 4. Program the input prescaler. In our example, we wish the capture to be performed at each valid transition, so the prescaler is disabled (write IC1PS bits to ‘00’ in the TIMx_CCMR1 register). 5. Enable capture from the counter into the capture register by setting the CC1E bit in the TIMx_CCER register. 6. If needed, enable the related interrupt request by setting the CC1IE bit in the TIMx_DIER register. For code example, refer to A.9.3: Input capture configuration code example. When an input capture occurs: The TIMx_CCR1 register gets the value of the counter on the active transition. CC1IF flag is set (interrupt flag). CC1OF is also set if at least two consecutive captures occurred whereas the flag was not cleared. An interrupt is generated depending on the CC1IE bit. For code example, refer to A.9.4: Input capture data management code example. In order to handle the overcapture, it is recommended to read the data before the overcapture flag. This is to avoid missing an overcapture which could happen after reading the flag and before reading the data. Note: IC interrupt requests can be generated by software by setting the corresponding CCxG bit in the TIMx_EGR register. DocID025942 Rev 5 442/874 475 General-purpose timers (TIM21/22) 17.3.6 RM0377 PWM input mode This mode is a particular case of input capture mode. The procedure is the same except: Two ICx signals are mapped on the same TIx input. These 2 ICx signals are active on edges with opposite polarity. One of the two TIxFP signals is selected as trigger input and the slave mode controller is configured in reset mode. For example, you can measure the period (in TIMx_CCR1 register) and the duty cycle (in TIMx_CCR2 register) of the PWM applied on TI1 using the following procedure (depending on CK_INT frequency and prescaler value): 1. Select the active input for TIMx_CCR1: write the CC1S bits to ‘01’ in the TIMx_CCMR1 register (TI1 selected). 2. Select the active polarity for TI1FP1 (used both for capture in TIMx_CCR1 and counter clear): program the CC1P and CC1NP bits to ‘00’ (active on rising edge). 3. Select the active input for TIMx_CCR2: write the CC2S bits to ‘10’ in the TIMx_CCMR1 register (TI1 selected). 4. Select the active polarity for TI1FP2 (used for capture in TIMx_CCR2): program the CC2P and CC2NP bits to ‘11’ (active on falling edge). 5. Select the valid trigger input: write the TS bits to ‘101’ in the TIMx_SMCR register (TI1FP1 selected). 6. Configure the slave mode controller in reset mode: write the SMS bits to ‘100’ in the TIMx_SMCR register. 7. Enable the captures: write the CC1E and CC2E bits to ‘1’ in the TIMx_CCER register. For code example, refer to A.9.5: PWM input configuration code example. Figure 143. PWM input mode timing 7, 7,0[B&17 7,0[B&&5 7,0[B&&5 ,&FDSWXUH ,&FDSWXUH UHVHWFRXQWHU ,&FDSWXUH SXOVHZLGWK PHDVXUHPHQW ,&FDSWXUH SHULRG PHDVXUHPHQW DL 1. The PWM input mode can be used only with the TIMx_CH1/TIMx_CH2 signals due to the fact that only TI1FP1 and TI2FP2 are connected to the slave mode controller. 443/874 DocID025942 Rev 5 RM0377 17.3.7 General-purpose timers (TIM21/22) Forced output mode In output mode (CCxS bits = ‘00’ in the TIMx_CCMRx register), each output compare signal (OCxREF and then OCx) can be forced to active or inactive level directly by software, independently of any comparison between the output compare register and the counter. To force an output compare signal (OCXREF/OCx) to its active level, you just need to write ‘101’ in the OCxM bits in the corresponding TIMx_CCMRx register. Thus OCXREF is forced high (OCxREF is always active high) and OCx get opposite value to CCxP polarity bit. For example: CCxP=’0’ (OCx active high) => OCx is forced to high level. The OCxREF signal can be forced low by writing the OCxM bits to ‘100’ in the TIMx_CCMRx register. Anyway, the comparison between the TIMx_CCRx shadow register and the counter is still performed and allows the flag to be set. Interrupt requests can be sent accordingly. This is described in the output compare mode section below. 17.3.8 Output compare mode This function is used to control an output waveform or indicating when a period of time has elapsed. When a match is found between the capture/compare register and the counter, the output compare function: 1. Assigns the corresponding output pin to a programmable value defined by the output compare mode (OCxM bits in the TIMx_CCMRx register) and the output polarity (CCxP bit in the TIMx_CCER register). The output pin can keep its level (OCXM=’000’), be set active (OCxM=’001’), be set inactive (OCxM=’010’) or can toggle (OCxM=’011’) on match. 2. Sets a flag in the interrupt status register (CCxIF bit in the TIMx_SR register). 3. Generates an interrupt if the corresponding interrupt mask is set (CCXIE bit in the TIMx_DIER register). The TIMx_CCRx registers can be programmed with or without preload registers using the OCxPE bit in the TIMx_CCMRx register. In output compare mode, the update event UEV has no effect on OCxREF and OCx output. The timing resolution is one count of the counter. Output compare mode can also be used to output a single pulse (in One-pulse mode). Procedure: 1. Select the counter clock (internal, external, prescaler). 2. Write the desired data in the TIMx_ARR and TIMx_CCRx registers. 3. Set the CCxIE bit if an interrupt request is to be generated. 4. 5. Select the output mode. For example: – Write OCxM = ‘011’ to toggle OCx output pin when CNT matches CCRx – Write OCxPE = ‘0’ to disable preload register – Write CCxP = ‘0’ to select active high polarity – Write CCxE = ‘1’ to enable the output Enable the counter by setting the CEN bit in the TIMx_CR1 register. For code example, refer to A.9.7: Output compare configuration code example. DocID025942 Rev 5 444/874 475 General-purpose timers (TIM21/22) RM0377 The TIMx_CCRx register can be updated at any time by software to control the output waveform, provided that the preload register is not enabled (OCxPE=’0’, else TIMx_CCRx shadow register is updated only at the next update event UEV). An example is given in Figure 144. Figure 144. Output compare mode, toggle on OC1 :ULWH%KLQWKH&&5UHJLVWHU 7,0B&17 7,0B&&5 % $ % % % $ 2&5() 2& 0DWFKGHWHFWHGRQ&&5 ,QWHUUXSWJHQHUDWHGLIHQDEOHG 069 17.3.9 PWM mode Pulse Width Modulation mode allows you to generate a signal with a frequency determined by the value of the TIMx_ARR register and a duty cycle determined by the value of the TIMx_CCRx register. The PWM mode can be selected independently on each channel (one PWM per OCx output) by writing the OCxM bits in the TIMx_CCMRx register. Only the edge-aligned mode is available on TIMER20 and TIMER21. You must enable the corresponding preload register by setting the OCxPE bit in the TIMx_CCMRx register, and eventually the autoreload preload register (in upcounting or center-aligned modes) by setting the ARPE bit in the TIMx_CR1 register. As the preload registers are transferred to the shadow registers only when an update event occurs, before starting the counter, you have to initialize all the registers by setting the UG bit in the TIMx_EGR register. The OCx polarity is software programmable using the CCxP bit in the TIMx_CCER register. It can be programmed as active high or active low. The OCx output is enabled by the CCxE bit in the TIMx_CCER register. Refer to the TIMx_CCERx register description for more details. In PWM mode (1 or 2), TIMx_CNT and TIMx_CCRx are always compared to determine whether TIMx_CNT TIMx_CCRx. 445/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) The timer is able to generate PWM in edge-aligned mode only since the counter is upcounting. Upcounting configuration Upcounting is active when the DIR bit in the TIMx_CR1 register is low. Refer to the Upcounting mode on page 425. In the following example, we consider PWM mode 1. The reference PWM signal OCxREF is high as long as TIMx_CNT < TIMx_CCRx else it becomes low. If the compare value in TIMx_CCRx is greater than the auto-reload value (in TIMx_ARR) then OCxREF is held at ‘1’. If the compare value is 0 then OCxRef is held at ‘0’. Figure 145 shows some edge-aligned PWM waveforms in an example where TIMx_ARR=8. For code example, refer to A.9.8: Edge-aligned PWM configuration example. Figure 145. Edge-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU &&5[ 2&;5() &&[,) 2&;5() &&5[ &&[,) 2&;5() µ¶ &&5[! &&[,) 2&;5() µ¶ &&5[ &&[,) 069 Downcounting configuration Downcounting is active when DIR bit in TIMx_CR1 register is high. Refer to the Downcounting mode on page 429 In PWM mode 1, the reference signal OCxRef is low as long as TIMx_CNT > TIMx_CCRx else it becomes high. If the compare value in TIMx_CCRx is greater than the auto-reload value in TIMx_ARR, then OCxREF is held at ‘1’. 0% PWM is not possible in this mode. DocID025942 Rev 5 446/874 475 General-purpose timers (TIM21/22) RM0377 PWM center-aligned mode Center-aligned mode is active when the CMS bits in TIMx_CR1 register are different from ‘00’ (all the remaining configurations having the same effect on the OCxRef/OCx signals). The compare flag is set when the counter counts up, when it counts down or both when it counts up and down depending on the CMS bits configuration. The direction bit (DIR) in the TIMx_CR1 register is updated by hardware and must not be changed by software. Refer to the Center-aligned mode (up/down counting) on page 432. Figure 146 shows some center-aligned PWM waveforms in an example where: TIMx_ARR=8, PWM mode is the PWM mode 1, The flag is set when the counter counts down corresponding to the center-aligned mode 1 selected for CMS=01 in TIMx_CR1 register. For code example, refer to A.9.9: Center-aligned PWM configuration example. Figure 146. Center-aligned PWM waveforms (ARR=8) &RXQWHUUHJLVWHU 2&[5() &&5[ &06 &06 &06 &&[,) 2&[5() &&5[ &06 RU &&[,) 2&[5() µ¶ &&5[ &&[,) 2&[5() &&5[! µ¶ &06 &06 &06 &&[,) 2&[5() &&5[ &&[,) &06 &06 &06 µ¶ &06 &06 &06 $,E 447/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Hints on using center-aligned mode When starting in center-aligned mode, the current up-down configuration is used. It means that the counter counts up or down depending on the value written in the DIR bit in the TIMx_CR1 register. Moreover, the DIR and CMS bits must not be changed at the same time by the software. Writing to the counter while running in center-aligned mode is not recommended as it can lead to unexpected results. In particular: 17.3.10 – The direction is not updated if you write a value in the counter that is greater than the auto-reload value (TIMx_CNT>TIMx_ARR). For example, if the counter was counting up, it continues to count up. – The direction is updated if you write 0 or write the TIMx_ARR value in the counter but no Update Event UEV is generated. The safest way to use center-aligned mode is to generate an update by software (setting the UG bit in the TIMx_EGR register) just before starting the counter and not to write the counter while it is running. Clearing the OCxREF signal on an external event The OCxREF signal for a given channel can be driven Low by applying a High level to the ETRF input (OCxCE enable bit of the corresponding TIMx_CCMRx register set to ‘1’). The OCxREF signal remains Low until the next update event, UEV, occurs. This function can only be used in output compare and PWM modes, and does not work in forced mode. For example, the ETR signal can be connected to the output of a comparator to be used for current handling. In this case, the ETR must be configured as follow: 1. The External Trigger Prescaler should be kept off: bits ETPS[1:0] of the TIMx_SMCR register set to ‘00’. 2. The external clock mode 2 must be disabled: bit ECE of the TIMx_SMCR register set to ‘0’. 3. The External Trigger Polarity (ETP) and the External Trigger Filter (ETF) can be configured according to the user needs. For code example, refer to A.9.10: ETR configuration to clear OCxREF code example. Figure 147 shows the behavior of the OCxREF signal when the ETRF Input becomes High, for both values of the enable bit OCxCE. In this example, the timer TIMx is programmed in PWM mode. DocID025942 Rev 5 448/874 475 General-purpose timers (TIM21/22) RM0377 Figure 147. Clearing TIMx OCxREF &&5[ &RXQWHU&17 (75) 2&[5() 2&[&( µ¶ 2&[5() 2&[&( µ¶ 2&[5()B&/5 EHFRPHVKLJK 2&[5()B&/5 VWLOOKLJK 069 Note: In case of a PWM with a 100% duty cycle (if CCRx>ARR), then OCxREF is enabled again at the next counter overflow. 17.3.11 One-pulse mode One-pulse mode (OPM) is a particular case of the previous modes. It allows the counter to be started in response to a stimulus and to generate a pulse with a programmable length after a programmable delay. Starting the counter can be controlled through the slave mode controller. Generating the waveform can be done in output compare mode or PWM mode. You select One-pulse mode by setting the OPM bit in the TIMx_CR1 register. This makes the counter stop automatically at the next update event UEV. A pulse can be correctly generated only if the compare value is different from the counter initial value. Before starting (when the timer is waiting for the trigger), the configuration must be as follows: CNT < CCRx ARR (in particular, 0 < CCRx) 449/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Figure 148. Example of one pulse mode 7, 2&5() 2& &RXQWHU 7,0B$55 7,0B&&5 W'(/$< W38/6( W 069 For example you may want to generate a positive pulse on OC1 with a length of tPULSE and after a delay of tDELAY as soon as a positive edge is detected on the TI2 input pin. Use TI2FP2 as trigger 1: 1. Map TI2FP2 to TI2 by writing CC2S=’01’ in the TIMx_CCMR1 register. 2. TI2FP2 must detect a rising edge, write CC2P=’0’ and CC2NP = ‘0’ in the TIMx_CCER register. 3. Configure TI2FP2 as trigger for the slave mode controller (TRGI) by writing TS=’110’ in the TIMx_SMCR register. 4. TI2FP2 is used to start the counter by writing SMS to ‘110’ in the TIMx_SMCR register (trigger mode). The OPM waveform is defined by writing the compare registers (taking into account the clock frequency and the counter prescaler). The tDELAY is defined by the value written in the TIMx_CCR1 register. The tPULSE is defined by the difference between the auto-reload value and the compare value (TIMx_ARR - TIMx_CCR1+1). Let’s say you want to build a waveform with a transition from ‘0’ to ‘1’ when a compare match occurs and a transition from ‘1’ to ‘0’ when the counter reaches the auto-reload value. To do this you enable PWM mode 2 by writing OC1M=’111’ in the TIMx_CCMR1 register. You can optionally enable the preload registers by writing OC1PE=’1’ in the TIMx_CCMR1 register and ARPE in the TIMx_CR1 register. In this case you have to write the compare value in the TIMx_CCR1 register, the auto-reload value in the TIMx_ARR register, generate an update by setting the UG bit and wait for external trigger event on TI2. CC1P is written to ‘0’ in this example. In our example, the DIR and CMS bits in the TIMx_CR1 register should be low. For code example, refer to A.9.16: One-Pulse mode code example. DocID025942 Rev 5 450/874 475 General-purpose timers (TIM21/22) RM0377 You only want 1 pulse (Single mode), so you write '1 in the OPM bit in the TIMx_CR1 register to stop the counter at the next update event (when the counter rolls over from the auto-reload value back to 0). When OPM bit in the TIMx_CR1 register is set to '0', so the Repetitive Mode is selected. Particular case: OCx fast enable In One-pulse mode, the edge detection on TIx input set the CEN bit which enables the counter. Then the comparison between the counter and the compare value makes the output toggle. But several clock cycles are needed for these operations and it limits the minimum delay tDELAY min we can get. If you want to output a waveform with the minimum delay, you can set the OCxFE bit in the TIMx_CCMRx register. Then OCxRef (and OCx) are forced in response to the stimulus, without taking in account the comparison. Its new level is the same as if a compare match had occurred. OCxFE acts only if the channel is configured in PWM1 or PWM2 mode. For code example, refer to A.9.16: One-Pulse mode code example. 17.3.12 Encoder interface mode To select Encoder Interface mode write SMS=‘001 in the TIMx_SMCR register if the counter is counting on TI2 edges only, SMS=010 if it is counting on TI1 edges only and SMS=011 if it is counting on both TI1 and TI2 edges. Select the TI1 and TI2 polarity by programming the CC1P and CC2P bits in the TIMx_CCER register. CC1NP and CC2NP must be kept cleared. When needed, you can program the input filter as well. CC1NP and CC2NP must be kept low. The two inputs TI1 and TI2 are used to interface to an incremental encoder. Refer to Table 72. The counter is clocked by each valid transition on TI1FP1 or TI2FP2 (TI1 and TI2 after input filter and polarity selection, TI1FP1=TI1 if not filtered and not inverted, TI2FP2=TI2 if not filtered and not inverted) assuming that it is enabled (CEN bit in TIMx_CR1 register written to ‘1). The sequence of transitions of the two inputs is evaluated and generates count pulses as well as the direction signal. Depending on the sequence the counter counts up or down, the DIR bit in the TIMx_CR1 register is modified by hardware accordingly. The DIR bit is calculated at each transition on any input (TI1 or TI2), whatever the counter is counting on TI1 only, TI2 only or both TI1 and TI2. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value in the TIMx_ARR register (0 to ARR or ARR down to 0 depending on the direction). So you must configure TIMx_ARR before starting. In the same way, the capture, compare, prescaler, trigger output features continue to work as normal. In this mode, the counter is modified automatically following the speed and the direction of the quadrature encoder and its content, therefore, always represents the encoder’s position. The count direction correspond to the rotation direction of the connected sensor. The table summarizes the possible combinations, assuming TI1 and TI2 don’t switch at the same time. 451/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Table 72. Counting direction versus encoder signals Level on opposite signal (TI1FP1 for TI2, TI2FP2 for TI1) Rising Falling Rising Falling Counting on TI1 only High Down Up No Count No Count Low Up Down No Count No Count Counting on TI2 only High No Count No Count Up Down Low No Count No Count Down Up Counting on TI1 and TI2 High Down Up Up Down Low Up Down Down Up Active edge TI1FP1 signal TI2FP2 signal An external incremental encoder can be connected directly to the MCU without external interface logic. However, comparators are normally be used to convert the encoder’s differential outputs to digital signals. This greatly increases noise immunity. The third encoder output which indicate the mechanical zero position, may be connected to an external interrupt input and trigger a counter reset. Figure 149 gives an example of counter operation, showing count signal generation and direction control. It also shows how input jitter is compensated where both edges are selected. This might occur if the sensor is positioned near to one of the switching points. For this example we assume that the configuration is the following: CC1S= 01 (TIMx_CCMR1 register, TI1FP1 mapped on TI1) CC2S= 01 (TIMx_CCMR2 register, TI2FP2 mapped on TI2) CC1P and CC1NP = ‘0’ (TIMx_CCER register, TI1FP1 noninverted, TI1FP1=TI1) CC2P and CC2NP = ‘0’ (TIMx_CCER register, TI2FP2 noninverted, TI2FP2=TI2) SMS= 011 (TIMx_SMCR register, both inputs are active on both rising and falling edges) CEN= 1 (TIMx_CR1 register, Counter is enabled) For code example, refer to A.9.11: Encoder interface code example. Figure 149. Example of counter operation in encoder interface mode IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU XS GRZQ XS 069 DocID025942 Rev 5 452/874 475 General-purpose timers (TIM21/22) RM0377 Figure 150 gives an example of counter behavior when TI1FP1 polarity is inverted (same configuration as above except CC1P=1). Figure 150. Example of encoder interface mode with TI1FP1 polarity inverted IRUZDUG MLWWHU EDFNZDUG MLWWHU IRUZDUG 7, 7, &RXQWHU GRZQ XS GRZQ 069 The timer, when configured in Encoder Interface mode provides information on the sensor’s current position. You can obtain dynamic information (speed, acceleration, deceleration) by measuring the period between two encoder events using a second timer configured in capture mode. The output of the encoder which indicates the mechanical zero can be used for this purpose. Depending on the time between two events, the counter can also be read at regular times. You can do this by latching the counter value into a third input capture register if available (then the capture signal must be periodic and can be generated by another timer). when available, it is also possible to read its value through a DMA request generated by a Real-Time clock. 17.3.13 TIM21/22 external trigger synchronization The TIM21/22 timers can be synchronized with an external trigger in several modes: Reset mode, Gated mode and Trigger mode. Slave mode: Reset mode The counter and its prescaler can be reinitialized in response to an event on a trigger input. Moreover, if the URS bit from the TIMx_CR1 register is low, an update event UEV is generated. Then all the preloaded registers (TIMx_ARR, TIMx_CCRx) are updated. In the following example, the upcounter is cleared in response to a rising edge on TI1 input: 1. Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S = ‘01’ in the TIMx_CCMR1 register. Program CC1P and CC1NP to ‘00’ in TIMx_CCER register to validate the polarity (and detect rising edges only). 2. Configure the timer in reset mode by writing SMS=’100’ in TIMx_SMCR register. Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register. 3. Start the counter by writing CEN=’1’ in the TIMx_CR1 register. For code example, refer to A.9.12: Reset mode code example. 453/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) The counter starts counting on the internal clock, then behaves normally until TI1 rising edge. When TI1 rises, the counter is cleared and restarts from 0. In the meantime, the trigger flag is set (TIF bit in the TIMx_SR register) and an interrupt request can be sent if enabled (depending on the TIE bit in TIMx_DIER register). The following figure shows this behavior when the auto-reload register TIMx_ARR=0x36. The delay between the rising edge on TI1 and the actual reset of the counter is due to the resynchronization circuit on TI1 input. Figure 151. Control circuit in reset mode 7, 8* &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 Slave mode: Gated mode The counter can be enabled depending on the level of a selected input. In the following example, the upcounter counts only when TI1 input is low: 1. Configure the channel 1 to detect low levels on TI1. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC1F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits select the input capture source only, CC1S=’01’ in TIMx_CCMR1 register. Program CC1P=’1’ and CC1NP= ‘0’ in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in gated mode by writing SMS=’101’ in TIMx_SMCR register. Select TI1 as the input source by writing TS=’101’ in TIMx_SMCR register. 3. Enable the counter by writing CEN=’1’ in the TIMx_CR1 register (in gated mode, the counter doesn’t start if CEN=’0’, whatever is the trigger input level). For code example, refer to A.9.13: Gated mode code example. The counter starts counting on the internal clock as long as TI1 is low and stops as soon as TI1 becomes high. The TIF flag in the TIMx_SR register is set both when the counter starts or stops. The delay between the rising edge on TI1 and the actual stop of the counter is due to the resynchronization circuit on TI1 input. DocID025942 Rev 5 454/874 475 General-purpose timers (TIM21/22) RM0377 Figure 152. Control circuit in gated mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) :ULWH7,) 069 Slave mode: Trigger mode The counter can start in response to an event on a selected input. In the following example, the upcounter starts in response to a rising edge on TI2 input: 1. Configure the external trigger input circuit by programming the TIMx_SMCR register as follows: – ETF = 0000: no filter – ETPS = 00: prescaler disabled – ETP = 0: detection of rising edges on ETR and ECE=1 to enable the external clock mode 2. 1. Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration (in this example, we don’t need any filter, so we keep IC2F=’0000’). The capture prescaler is not used for triggering, so you don’t need to configure it. The CC2S bits are configured to select the input capture source only, CC2S=’01’ in TIMx_CCMR1 register. Program CC2P=’1’ and CC2NP=’0’ in TIMx_CCER register to validate the polarity (and detect low level only). 2. Configure the timer in trigger mode by writing SMS=’110’ in TIMx_SMCR register. Select TI2 as the input source by writing TS=’110’ in TIMx_SMCR register. For code example, refer to A.9.14: Trigger mode code example. When a rising edge occurs on TI2, the counter starts counting on the internal clock and the TIF flag is set. The delay between the rising edge on TI2 and the actual start of the counter is due to the resynchronization circuit on TI2 input. 455/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Figure 153. Control circuit in trigger mode 7, FQWBHQ &RXQWHUFORFN FNBFQW FNBSVF &RXQWHUUHJLVWHU 7,) 069 17.3.14 Timer synchronization (TIM21/22) The timers are linked together internally for timer synchronization or chaining. Refer to Section 16.3.15: Timer synchronization on page 390 for details. 17.3.15 Debug mode When the microcontroller enters debug mode (Cortex®-M0+ core halted), the TIMx counter either continues to work normally or stops, depending on DBG_TIMx_STOP configuration bit in DBG module. For more details, refer to Section 31.16.2: Debug support for timers, watchdog, bxCAN and I2C. DocID025942 Rev 5 456/874 475 General-purpose timers (TIM21/22) 17.4 RM0377 TIM21/22 registers Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 17.4.1 TIM21/22 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 Res. Res. Res. Res. Res. Res. 9 8 CKD[1:0] rw 7 6 ARPE rw rw 5 CMS[1:0] rw rw 4 3 2 1 0 DIR OPM URS UDIS CEN rw rw rw rw rw Bits 15:10 Reserved, must be kept at reset value. Bits 9:8 CKD: Clock division This bit-field indicates the division ratio between the timer clock (CK_INT) frequency and sampling clock used by the digital filters (TIx), 00: tDTS = tCK_INT 01: tDTS = 2 × tCK_INT 10: tDTS = 4 × tCK_INT 11: Reserved Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:5 CMS[1:0]: Center-aligned mode selection 00: Edge-aligned mode. The counter counts up or down depending on the direction bit (DIR). 01: Center-aligned mode 1. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting down. 10: Center-aligned mode 2. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set only when the counter is counting up. 11: Center-aligned mode 3. The counter counts up and down alternatively. Output compare interrupt flags of channels configured in output (CCxS=00 in TIMx_CCMRx register) are set both when the counter is counting up or down. Note: It is not allowed to switch from edge-aligned mode to center-aligned mode as long as the counter is enabled (CEN=1). Bit 4 DIR: Direction 0: Counter used as upcounter 1: Counter used as downcounter Bit 3 OPM: One-pulse mode 0: Counter is not stopped on the update event 1: Counter stops counting on the next update event (clearing the CEN bit). 457/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt if enabled: – Counter overflow – Setting the UG bit 1: Only counter overflow generates an update interrupt if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable update event (UEV) generation. 0: UEV enabled. An UEV is generated by one of the following events: – Counter overflow – Setting the UG bit Buffered registers are then loaded with their preload values. 1: UEV disabled. No UEV is generated, shadow registers keep their value (ARR, PSC, CCRx). The counter and the prescaler are reinitialized if the UG bit is set. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled CEN is cleared automatically in one-pulse mode, when an update event occurs. DocID025942 Rev 5 458/874 475 General-purpose timers (TIM21/22) 17.4.2 RM0377 TIM21/22 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. Res. 6 5 4 MMS[2:0] rw rw 3 2 1 0 Res. Res. Res. Res. rw Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits allow to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as trigger output (TRGO). If the reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in TIMx_SMCR register). 010: Update - The update event is selected as trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. 011: Compare Pulse - The trigger output send a positive pulse when the CC1IF flag is to be set (even if it was already high), as soon as a capture or a compare match occurred. (TRGO) 100: Compare - OC1REF signal is used as trigger output (TRGO) 101: Compare - OC2REF signal is used as trigger output (TRGO) 110: Reserved 111: Reserved Bits 3:0 Reserved, must be kept at reset value. 459/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) 17.4.3 TIM21/22 slave mode control register (TIMx_SMCR) Address offset: 0x08 Reset value: 0x0000 15 14 ETP ECE rw rw 13 12 11 rw rw 10 9 8 ETF[3:0] ETPS[1:0] rw rw 7 6 MSM rw rw rw 5 4 TS[2:0] rw rw 3 2 Res. rw 1 0 SMS[2:0] rw rw rw Bit 15 ETP: External trigger polarity This bit selects whether ETR or ETR is used for trigger operations 0: ETR is non-inverted, active at high level or rising edge. 1: ETR is inverted, active at low level or falling edge. Bit 14 ECE: External clock enable This bit enables External clock mode 2. 0: External clock mode 2 disabled 1: External clock mode 2 enabled. The counter is clocked by any active edge on the ETRF signal. Note: Setting the ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF (SMS=111 and TS=111). It is possible to simultaneously use external clock mode 2 with the following slave modes: reset mode, gated mode and trigger mode. Nevertheless, TRGI must not be connected to ETRF in this case (TS bits must not be 111). If external clock mode 1 and external clock mode 2 are enabled at the same time, the external clock input is ETRF. Bits 13:12 ETPS[1:0]: External trigger prescaler External trigger signal ETRP frequency must be at most 1/4 of TIMxCLK frequency. A prescaler can be enabled to reduce ETRP frequency. It is useful when inputting fast external clocks. 00: Prescaler OFF 01: ETRP frequency divided by 2 10: ETRP frequency divided by 4 11: ETRP frequency divided by 8 DocID025942 Rev 5 460/874 475 General-purpose timers (TIM21/22) RM0377 Bits 11:8 ETF[3:0]: External trigger filter This bit-field then defines the frequency used to sample ETRP signal and the length of the digital filter applied to ETRP. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 0000: No filter, sampling is done at fDTS 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 0011: fSAMPLING=fCK_INT, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 0110: fSAMPLING=fDTS/4, N=6 0111: fSAMPLING=fDTS/4, N=8 1000: fSAMPLING=fDTS/8, N=6 1001: fSAMPLING=fDTS/8, N=8 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 1100: fSAMPLING=fDTS/16, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 1111: fSAMPLING=fDTS/32, N=8 Bit 7 MSM: Master/Slave mode 0: No action 1: The effect of an event on the trigger input (TRGI) is delayed to allow a perfect synchronization between the current timer and its slaves (through TRGO). It is useful in order to synchronize several timers on a single external event. 461/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Bits 6:4 TS: Trigger selection This bitfield selects the trigger input to be used to synchronize the counter. 000: Internal Trigger 0 (ITR0) 001: Internal Trigger 1 (ITR1) 010: Reserved 011: Reserved 100: TI1 Edge Detector (TI1F_ED) 101: Filtered Timer Input 1 (TI1FP1) 110: Filtered Timer Input 2 (TI2FP2) 111: Reserved. See Table 73: TIMx Internal trigger connection on page 462 for more details on the meaning of ITRx for each timer. Note: These bits must be changed only when they are not used (e.g. when SMS=’000’) to avoid wrong edge detections at the transition. Bit 3 Reserved, must be kept at reset value. Bits 2:0 SMS: Slave mode selection When external signals are selected, the active edge of the trigger signal (TRGI) is linked to the polarity selected on the external input (see Input control register and Control register descriptions. 000: Slave mode disabled - if CEN = 1 then the prescaler is clocked directly by the internal clock 001: Encoder mode 1 010: Encoder mode 2 011: Encoder mode 3 100: Reset mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter and generates an update of the registers 101: Gated mode - The counter clock is enabled when the trigger input (TRGI) is high. The counter stops (but is not reset) as soon as the trigger becomes low. Counter starts and stops are both controlled 110: Trigger mode - The counter starts on a rising edge of the trigger TRGI (but it is not reset). Only the start of the counter is controlled 111: External Clock Mode 1 Note: The Gated mode must not be used if TI1F_ED is selected as the trigger input (TS=’100’). Indeed, TI1F_ED outputs 1 pulse for each transition on TI1F, whereas the Gated mode checks the level of the trigger signal. Table 73. TIMx Internal trigger connection(1) Slave TIM ITR0 (TS = 000) ITR1 (TS = 001) TIM21 TIM2 TIM22 TIM22 TIM21 TIM2 1. When a timer is not present in the product, the corresponding trigger ITRx is not available. DocID025942 Rev 5 462/874 475 General-purpose timers (TIM21/22) 17.4.4 RM0377 TIM21/22 Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. TIE Res. Res. Res. CC2IE CC1IE UIE rw rw rw rw Bit 15:7 Reserved, must be kept at reset value. Bit 6 TIE: Trigger interrupt enable 0: Trigger interrupt disabled. 1: Trigger interrupt enabled. Bit 5:3 Reserved, must be kept at reset value. Bit 2 CC2IE: Capture/Compare 2 interrupt enable 0: CC2 interrupt disabled. 1: CC2 interrupt enabled. Bit 1 CC1IE: Capture/Compare 1 interrupt enable 0: CC1 interrupt disabled. 1: CC1 interrupt enabled. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. 17.4.5 TIM21/22 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 Res. Res. Res. Res. Res. 10 rc_w0 Bit 15:11 9 CC2OF CC1OF 8 7 6 5 4 3 2 1 0 Res. Res. TIF Res. Res. Res. CC2IF CC1IF UIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Reserved, must be kept at reset value. Bit 10 CC2OF: Capture/compare 2 overcapture flag refer to CC1OF description Bit 9 CC1OF: Capture/Compare 1 overcapture flag This flag is set by hardware only when the corresponding channel is configured in input capture mode. It is cleared by software by writing it to ‘0’. 0: No overcapture has been detected. 1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set Bits 8:7 463/874 Reserved, must be kept at reset value. DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Bit 6 TIF: Trigger interrupt flag This flag is set by hardware on trigger event (active edge detected on TRGI input when the slave mode controller is enabled in all modes but gated mode. It is set when the counter starts or stops when gated mode is selected. It is cleared by software. 0: No trigger event occurred. 1: Trigger interrupt pending. Bit 5:3 Reserved, must be kept at reset value. Bit 2 CC2IF: Capture/Compare 2 interrupt flag refer to CC1IF description Bit 1 CC1IF: Capture/compare 1 interrupt flag If channel CC1 is configured as output: This flag is set by hardware when the counter matches the compare value. It is cleared by software. 0: No match. 1: The content of the counter TIMx_CNT matches the content of the TIMx_CCR1 register. When the contents of TIMx_CCR1 are greater than the contents of TIMx_ARR, the CC1IF bit goes high on the counter overflow. If channel CC1 is configured as input: This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1 register. 0: No input capture occurred. 1: The counter value has been captured in TIMx_CCR1 register (an edge has been detected on IC1 which matches the selected polarity). Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow and if UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in TIMx_EGR register, if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. – When CNT is reinitialized by a trigger event (refer to the synchro control register description), if URS=’0’ and UDIS=’0’ in the TIMx_CR1 register. DocID025942 Rev 5 464/874 475 General-purpose timers (TIM21/22) 17.4.6 RM0377 TIM21/22 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. TG Res. Res. Res. CC2G CC1G UG w w w w Bits 15:7 Reserved, must be kept at reset value. Bit 6 TG: Trigger generation This bit is set by software in order to generate an event, it is automatically cleared by hardware. 0: No action 1: The TIF flag is set in the TIMx_SR register. Related interrupt can occur if enabled Bits 5:3 Reserved, must be kept at reset value. Bit 2 CC2G: Capture/compare 2 generation refer to CC1G description Bit 1 CC1G: Capture/compare 1 generation This bit is set by software to generate an event, it is automatically cleared by hardware. 0: No action 1: A capture/compare event is generated on channel 1: If channel CC1 is configured as output: the CC1IF flag is set, the corresponding interrupt is sent if enabled. If channel CC1 is configured as input: The current counter value is captured in the TIMx_CCR1 register. The CC1IF flag is set, the corresponding interrupt is sent if enabled. The CC1OF flag is set if the CC1IF flag was already high. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action 1: Re-initializes the counter and generates an update of the registers. The prescaler counter is also cleared and the prescaler ratio is not affected. The counter is cleared. 465/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) 17.4.7 TIM21/22 capture/compare mode register 1 (TIMx_CCMR1) Address offset: 0x18 Reset value: 0x0000 The channels can be used in input (capture mode) or in output (compare mode). The direction of a channel is defined by configuring the corresponding CCxS bits. All the other bits in this register have different functions in input and output modes. For a given bit, OCxx describes its function when the channel is configured in output mode, ICxx describes its function when the channel is configured in input mode. So you must take care that the same bit can have different meanings for the input stage and the output stage. 15 14 Res. rw 13 12 11 10 OC2M[2:0] OC2PE OC2FE IC2F[3:0] IC2PSC[1:0] rw rw rw rw 9 8 CC2S[1:0] rw 7 6 Res. rw rw 5 4 3 2 OC1M[2:0] OC1PE OC1FE IC1F[3:0] IC1PSC[1:0] rw rw rw rw 1 0 CC1S[1:0] rw rw Output compare mode Bit 15 Reserved, must be kept at reset value. Bits 14:12 OC2M[2:0]: Output compare 2 mode Bit 11 OC2PE: Output compare 2 preload enable Bit 10 OC2FE: Output compare 2 fast enable Bits 9:8 CC2S[1:0]: Capture/Compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bit 7 Reserved, must be kept at reset value. DocID025942 Rev 5 466/874 475 General-purpose timers (TIM21/22) RM0377 Bits 6:4 OC1M: Output compare 1 mode These bits define the behavior of the output reference signal OC1REF from which OC1 and OC1N are derived. OC1REF is active high whereas the active levels of OC1 and OC1N depend on the CC1P and CC1NP bits, respectively. 000: Frozen - The comparison between the output compare register TIMx_CCR1 and the counter TIMx_CNT has no effect on the outputs.(this mode is used to generate a timing base). 001: Set channel 1 to active level on match. The OC1REF signal is forced high when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). 010: Set channel 1 to inactive level on match. The OC1REF signal is forced low when the TIMx_CNT counter matches the capture/compare register 1 (TIMx_CCR1). 011: Toggle - OC1REF toggles when TIMx_CNT=TIMx_CCR1 100: Force inactive level - OC1REF is forced low 101: Force active level - OC1REF is forced high 110: PWM mode 1 - In upcounting, channel 1 is active as long as TIMx_CNT<TIMx_CCR1 else it is inactive. In downcounting, channel 1 is inactive (OC1REF=‘0) as long as TIMx_CNT>TIMx_CCR1, else it is active (OC1REF=’1’) 111: PWM mode 2 - In upcounting, channel 1 is inactive as long as TIMx_CNT<TIMx_CCR1 else it is active. In downcounting, channel 1 is active as long as TIMx_CNT>TIMx_CCR1 else it is inactive. Note: In PWM mode 1 or 2, the OCREF level changes only when the result of the comparison changes or when the output compare mode switches from “frozen” mode to “PWM” mode. Bit 3 OC1PE: Output compare 1 preload enable 0: Preload register on TIMx_CCR1 disabled. TIMx_CCR1 can be written at anytime, the new value is taken into account immediately 1: Preload register on TIMx_CCR1 enabled. Read/Write operations access the preload register. TIMx_CCR1 preload value is loaded into the active register at each update event Note: The PWM mode can be used without validating the preload register only in one-pulse mode (OPM bit set in the TIMx_CR1 register). Else the behavior is not guaranteed. Bit 2 OC1FE: Output compare 1 fast enable This bit is used to accelerate the effect of an event on the trigger in input on the CC output. 0: CC1 behaves normally depending on the counter and CCR1 values even when the trigger is ON. The minimum delay to activate the CC1 output when an edge occurs on the trigger input is 5 clock cycles 1: An active edge on the trigger input acts like a compare match on the CC1 output. Then, OC is set to the compare level independently of the result of the comparison. Delay to sample the trigger input and to activate CC1 output is reduced to 3 clock cycles. OC1FE acts only if the channel is configured in PWM1 or PWM2 mode. Bits 1:0 CC1S: Capture/Compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). 467/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Input capture mode Bits 15:12 IC2F: Input capture 2 filter Bits 11:10 IC2PSC[1:0]: Input capture 2 prescaler Bits 9:8 CC2S: Capture/compare 2 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC2 channel is configured as output 01: CC2 channel is configured as input, IC2 is mapped on TI2 10: CC2 channel is configured as input, IC2 is mapped on TI1 11: CC2 channel is configured as input, IC2 is mapped on TRC. This mode works only if an internal trigger input is selected through the TS bit (TIMx_SMCR register) Note: The CC2S bits are writable only when the channel is OFF (CC2E = 0 in TIMx_CCER). Bits 7:4 IC1F: Input capture 1 filter This bitfield defines the frequency used to sample the TI1 input and the length of the digital filter applied to TI1. The digital filter is made of an event counter in which N consecutive events are needed to validate a transition on the output: 1000: fSAMPLING=fDTS/8, N=6 0000: No filter, sampling is done at fDTS 1001: fSAMPLING=fDTS/8, N=8 0001: fSAMPLING=fCK_INT, N=2 0010: fSAMPLING=fCK_INT, N=4 1010: fSAMPLING=fDTS/16, N=5 1011: fSAMPLING=fDTS/16, N=6 0011: fSAMPLING=fCK_INT, N=8 1100: fSAMPLING=fDTS/16, N=8 0100: fSAMPLING=fDTS/2, N=6 0101: fSAMPLING=fDTS/2, N=8 1101: fSAMPLING=fDTS/32, N=5 1110: fSAMPLING=fDTS/32, N=6 0110: fSAMPLING=fDTS/4, N=6 1111: fSAMPLING=fDTS/32, N=8 0111: fSAMPLING=fDTS/4, N=8 Bits 3:2 IC1PSC: Input capture 1 prescaler This bitfield defines the ratio of the prescaler acting on the CC1 input (IC1). The prescaler is reset as soon as CC1E=’0’ (TIMx_CCER register). 00: no prescaler, capture is done each time an edge is detected on the capture input 01: capture is done once every 2 events 10: capture is done once every 4 events 11: capture is done once every 8 events Bits 1:0 CC1S: Capture/Compare 1 selection This bitfield defines the direction of the channel (input/output) as well as the used input. 00: CC1 channel is configured as output 01: CC1 channel is configured as input, IC1 is mapped on TI1 10: CC1 channel is configured as input, IC1 is mapped on TI2 11: CC1 channel is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TS bit (TIMx_SMCR register) Note: The CC1S bits are writable only when the channel is OFF (CC1E = 0 in TIMx_CCER). DocID025942 Rev 5 468/874 475 General-purpose timers (TIM21/22) 17.4.8 RM0377 TIM21/22 capture/compare enable register (TIMx_CCER) Address offset: 0x20 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. CC2NP Res. CC2P CC2E CC1NP Res. CC1P CC1E rw rw rw rw rw rw Bits 15:8 Reserved, must be kept at reset value. Bit 7 CC2NP: Capture/Compare 2 output Polarity refer to CC1NP description Bits 6 Reserved, must be kept at reset value. Bit 5 CC2P: Capture/Compare 2 output Polarity refer to CC1P description Bit 4 CC2E: Capture/Compare 2 output enable refer to CC1E description Bit 3 CC1NP: Capture/Compare 1 complementary output Polarity CC1 channel configured as output: CC1NP must be kept cleared CC1 channel configured as input: CC1NP is used in conjunction with CC1P to define TI1FP1/TI2FP1 polarity (refer to CC1P description). Bits 2 Reserved, must be kept at reset value. Bit 1 CC1P: Capture/Compare 1 output Polarity. CC1 channel configured as output: 0: OC1 active high. 1: OC1 active low. CC1 channel configured as input: CC1NP/CC1P bits select TI1FP1 and TI2FP1 polarity for trigger or capture operations. 00: noninverted/rising edge Circuit is sensitive to TIxFP1 rising edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode, encoder mode). 01: inverted/falling edge Circuit is sensitive to TIxFP1 falling edge (capture, trigger in reset, external clock or trigger mode), TIxFP1 is inverted (trigger in gated mode, encoder mode). 10: reserved, do not use this configuration. Note: 11: noninverted/both edges Circuit is sensitive to both TIxFP1 rising and falling edges (capture, trigger in reset, external clock or trigger mode), TIxFP1 is not inverted (trigger in gated mode). This configuration must not be used for encoder mode. Bit 0 CC1E: Capture/Compare 1 output enable. CC1 channel configured as output: 0: Off - OC1 is not active. 1: On - OC1 signal is output on the corresponding output pin. CC1 channel configured as input: This bit determines if a capture of the counter value can actually be done into the input capture/compare register 1 (TIMx_CCR1) or not. 0: Capture disabled. 1: Capture enabled. 469/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) Table 74. Output control bit for standard OCx channels CCxE bit OCx output state 0 Output disabled (OCx=’0’, OCx_EN=’0’) 1 OCx=OCxREF + Polarity, OCx_EN=’1’ Note: The states of the external I/O pins connected to the standard OCx channels depend on the state of the OCx channel and on the GPIO registers. 17.4.9 TIM21/22 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNT[15:0] rw rw rw rw rw rw rw rw Bits 15:0 CNT[15:0]: Counter value 17.4.10 TIM21/22 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 PSC[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. 17.4.11 TIM21/22 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded into the actual auto-reload register. Refer to the Section 17.3.1: Time-base unit on page 423 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. DocID025942 Rev 5 470/874 475 General-purpose timers (TIM21/22) 17.4.12 RM0377 TIM21/22 capture/compare register 1 (TIMx_CCR1) Address offset: 0x34 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR1[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR1[15:0]: Capture/Compare 1 value If channel CC1 is configured as output: CCR1 is the value to be loaded into the actual capture/compare 1 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR1 register (OC1PE bit). Else the preload value is copied into the active capture/compare 1 register when an update event occurs. The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signaled on the OC1 output. If channel CC1is configured as input: CCR1 is the counter value transferred by the last input capture 1 event (IC1). 17.4.13 TIM21/22 capture/compare register 2 (TIMx_CCR2) Address offset: 0x38 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CCR2[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 CCR2[15:0]: Capture/Compare 2 value If channel CC2 is configured as output: CCR2 is the value to be loaded into the actual capture/compare 2 register (preload value). It is loaded permanently if the preload feature is not selected in the TIMx_CCMR2 register (OC2PE bit). Else the preload value is copied into the active capture/compare 2 register when an update event occurs. The active capture/compare register contains the value to be compared to the TIMx_CNT counter and signalled on the OC2 output. If channel CC2 is configured as input: CCR2 is the counter value transferred by the last input capture 2 event (IC2). 471/874 DocID025942 Rev 5 RM0377 General-purpose timers (TIM21/22) 17.4.14 TIM21 option register (TIM21_OR) Address offset: 0x50 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TI2_RMP rw 4 3 2 TI1_RMP rw rw 1 0 ETR_RMP rw rw rw Bits 15:6 Reserved, must be kept at reset value. Bit 5 TI2_RMP: Timer21 TI2 (connected to TIM21_CH1) remap This bit is set and cleared by software. 0: TIM21 TI2 input connected to GPIO. Refer to the Alternate function mapping table in the device datasheet. 1: TIM21 TI2 input connected to COMP2_OUT Bit 4:2 TI1_RMP: Timer21 TI1 (connected to TIM21_CH1) remap This bit is set and cleared by software. 000: TIM21 TI1 input connected to GPIO. Refer to the Alternate function mapping table in the device datasheet. 001:TIM21 TI1 input connected to RTC WAKEUP interrupt 010: TIM21 TI1 input connected to HSE_RTC clock 011: TIM21 TI1 input connected to MSI clock 100: TIM21 TI1 input connected to LSE clock 101: TIM21 TI1 input connected to LSI clock 110: TIM21 TI1 input connected to COMP1_OUT 111: TIM21 TI1 input connected to MCO clock Bit 1:0 ETR_RMP: Timer21 ETR remap This bit is set and cleared by software. 00: TIM21 ETR input connected to GPIO. Refer to the Alternate function mapping table in the device datasheet. 01: TIM21 ETR input connected to COMP2_OUT 10: TIM21 ETR input connected to COMP1_OUT 11: TIM21 ETR input connected to LSE clock DocID025942 Rev 5 472/874 475 General-purpose timers (TIM21/22) 17.4.15 RM0377 TIM22 option register (TIM22_OR) Address offset: 0x50 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 3 2 TI1_RMP rw rw 1 0 ETR_RMP rw rw Bits 15:4 Reserved, must be kept at reset value. Bit 3:2 TI1_RMP: Timer22 TI1 (connected to TIM22_CH1) remap This bit is set and cleared by software. 00: TIM22 TI1 input connected to GPIO. Refer to the Alternate function mapping table in the device datasheet. 01:TIM22 TI1 input connected to COMP2_OUT 10: TIM22 TI1 input connected to COMP1_OUT 11: TIM22 TI1 input connected to GPIO. Refer to the Alternate function mapping table in the device datasheet. Bits 1:0 ETR_RMP: Timer22 ETR remap This bit is set and cleared by software. 00: TIM22 ETR input connected to GPIO. Refer to the Alternate function mapping table in the device datasheet. 01: TIM22 ETR input connected to COMP2_OUT 10: TIM22 ETR input connected to COMP1_OUT 11: TIM22 ETR input connected to LSE clock 473/874 DocID025942 Rev 5 RM0377 17.4.16 General-purpose timers (TIM21/22) TIM21/22 register map The table below shows TIM21/22 register map and reset values. 3 2 1 0 OPM URS UDIS CEN Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIE Res. Res. 0 Res. Res. Res. Res. Res. TG 0 0 0 0 0 OC1FE Res. CC2S [1:0] 0 0 0 0 IC1PSC [1:0] IC1F[3:0] CC1S [1:0] 0 0 CC1S [1:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CC1E Reset value 0 CC1P TIMx_CNT CC1NP 0 CC2E Reset value CC2P Res. Res. Res. Res. TIMx_CCER Res. Res. Res. 0x1C 0 0 Res. 0 0 0 Res. 0 0 0 CC2NP 0 0 IC2PSC [1:0] IC2F[3:0] 0 0 0 OC1PE 0 OC1M [2:0] 0 Res. 0 CC2S [1:0] 0 Res. 0 OC2FE Res. OC2M [2:0] OC2PE 0 Reset value Reset value Res. TIF Res. 0 Res. Res. Res. CC1OF 0 Res. CC2OF Res. Res. Res. Res. Res. TIMx_EGR 0 Res. Res. Res. Res. Res. Res. TIMx_SR 0 0 UIE TIMx_DIER 0 UIF 0 UG 0 CC1IE 0 CC1IF 0 CC1G 0 CC2IE 0 CC2IF 0 SMS[2:0] CC2G 0 Res. Res. 0 TS[2:0] Res. ECE 0 Res. MSM 0 0 TIMx_CCMR1 Input Capture mode 0x24 0 0 TIMx_CCMR1 Output Compare mode 0x20 0 Reset value ETF[3:0] Reset value 0x18 0 TIMx_SMCR Reset value 0x14 0 ETP ETPS[1:0] 0 Reset value 0x10 0 Res. 0x0C 0 MMS[2:0] Reset value 0x08 4 Res. CMS [1:0] DIR 0 5 6 7 0 Res. ARPE 0 Res. Res. Res. Res. Res. Res. TIMx_CR2 Res. Reset value 0x04 8 10 9 CKD [1:0] Res. 11 Res. 12 Res. 14 13 Res. TIMx_CR1 Res. 0x00 Register Res. Offset 15 Table 75. TIM21/22 register map and reset values 0 0 0 0 CNT[15:0] 0 0 0 0 0 0 DocID025942 Rev 5 0 0 0 0 0 474/874 475 General-purpose timers (TIM21/22) RM0377 1 0 7 8 9 10 11 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR[15:0] 0 0 0 0 0 0 0 0 0 CCR1[15:0] 0 0 0 0 0 0 0 TIMx_CCR2 0 0 CCR2[15:0] 0 0 0 0 0 0x3C to 0x4C 0 0 0 0 Res. 0 0 0 0 0 0 TIM21_OR Res. Res. Res. Res. Res. Res. Res. TI2_RMP Res. Res. Res. Res. Res. Res. Res. Res. TIM22_OR Res. 0x50 Res. Reset value 0 0 Reset value 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. 475/874 DocID025942 Rev 5 ETR_RMP 0 0 ETR_RMP 0 TI1_RMP 0 TI1_RMP 0 Res. 0 Res. Reset value Res. CCR2[15:0] Res. TIMx_CCR2 Res. 0x50 2 0 TIMx_CCR1 Reset value 0x38 3 0 Res. Reset value 0x38 4 0 0x30 0x34 0 PSC[15:0] TIMx_ARR Reset value 5 Reset value 0x2C 13 TIMx_PSC 6 0x28 Register 14 Offset 15 Table 75. TIM21/22 register map and reset values (continued) 0 RM0377 Basic timers (TIM6/7) 18 Basic timers (TIM6/7) 18.1 Introduction The basic timers TIM6, TIM7 consist of a 16-bit auto-reload counter driven by a programmable prescaler. 18.2 TIM6/7 main features Basic timer (TIM6/TIM7) features include: 16-bit auto-reload upcounter 16-bit programmable prescaler used to divide (also “on the fly”) the counter clock frequency by any factor between 1 and 65536 Interrupt/DMA generation on the update event: counter overflow Figure 154. Basic timer block diagram 7,0[&/.IURP5&& ,QWHUQDOFORFN&.B,17 7ULJJHU &RQWUROOHU &RQWURO 8 5HVHWHQDEOH&RXQW $XWRUHORDGUHJLVWHU 6WRSFOHDURUXS &.B36& 75*2 36& &.B&17 SUHVFDOHU 8, 8 &17FRXQWHU 1RWHV 5HJ 3UHORDGUHJLVWHUVWUDQVIHUUHG WRDFWLYHUHJLVWHUVRQ8HYHQW DFFRUGLQJWRFRQWUROELW (YHQW ,QWHUUXSW'0$RXWSXW 06Y9 DocID025942 Rev 5 476/874 488 Basic timers (TIM6/7) RM0377 18.3 TIM6/7 functional description 18.3.1 Time-base unit The main block of the programmable timer is a 16-bit upcounter with its related auto-reload register. The counter clock can be divided by a prescaler. The counter, the auto-reload register and the prescaler register can be written or read by software. This is true even when the counter is running. The time-base unit includes: Counter Register (TIMx_CNT) Prescaler Register (TIMx_PSC) Auto-Reload Register (TIMx_ARR) The auto-reload register is preloaded. The preload register is accessed each time an attempt is made to write or read the auto-reload register. The contents of the preload register are transferred into the shadow register permanently or at each update event UEV, depending on the auto-reload preload enable bit (ARPE) in the TIMx_CR1 register. The update event is sent when the counter reaches the overflow value and if the UDIS bit equals 0 in the TIMx_CR1 register. It can also be generated by software. The generation of the update event is described in detail for each configuration. The counter is clocked by the prescaler output CK_CNT, which is enabled only when the counter enable bit (CEN) in the TIMx_CR1 register is set. Note that the actual counter enable signal CNT_EN is set 1 clock cycle after CEN. Prescaler description The prescaler can divide the counter clock frequency by any factor between 1 and 65536. It is based on a 16-bit counter controlled through a 16-bit register (in the TIMx_PSC register). It can be changed on the fly as the TIMx_PSC control register is buffered. The new prescaler ratio is taken into account at the next update event. Figure 155 and Figure 156 give some examples of the counter behavior when the prescaler ratio is changed on the fly. 477/874 DocID025942 Rev 5 RM0377 Basic timers (TIM6/7) Figure 155. Counter timing diagram with prescaler division change from 1 to 2 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 Figure 156. Counter timing diagram with prescaler division change from 1 to 4 &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) )$ )% )& 8SGDWHHYHQW8(9 3UHVFDOHUFRQWUROUHJLVWHU :ULWHDQHZYDOXHLQ7,0[B36& 3UHVFDOHUEXIIHU 3UHVFDOHUFRXQWHU 069 DocID025942 Rev 5 478/874 488 Basic timers (TIM6/7) 18.3.2 RM0377 Counting mode The counter counts from 0 to the auto-reload value (contents of the TIMx_ARR register), then restarts from 0 and generates a counter overflow event. An update event can be generate at each counter overflow or by setting the UG bit in the TIMx_EGR register (by software or by using the slave mode controller). The UEV event can be disabled by software by setting the UDIS bit in the TIMx_CR1 register. This avoids updating the shadow registers while writing new values into the preload registers. In this way, no update event occurs until the UDIS bit has been written to 0, however, the counter and the prescaler counter both restart from 0 (but the prescale rate does not change). In addition, if the URS (update request selection) bit in the TIMx_CR1 register is set, setting the UG bit generates an update event UEV, but the UIF flag is not set (so no interrupt or DMA request is sent). When an update event occurs, all the registers are updated and the update flag (UIF bit in the TIMx_SR register) is set (depending on the URS bit): The buffer of the prescaler is reloaded with the preload value (contents of the TIMx_PSC register) The auto-reload shadow register is updated with the preload value (TIMx_ARR) The following figures show some examples of the counter behavior for different clock frequencies when TIMx_ARR = 0x36. Figure 157. Counter timing diagram, internal clock divided by 1 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 479/874 DocID025942 Rev 5 RM0377 Basic timers (TIM6/7) Figure 158. Counter timing diagram, internal clock divided by 2 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 159. Counter timing diagram, internal clock divided by 4 &.B36& &17B(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 DocID025942 Rev 5 480/874 488 Basic timers (TIM6/7) RM0377 Figure 160. Counter timing diagram, internal clock divided by N &.B36& 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) 069 Figure 161. Counter timing diagram, update event when ARPE = 0 (TIMx_ARR not preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU )) :ULWHDQHZYDOXHLQ7,0[B$55 069 481/874 DocID025942 Rev 5 RM0377 Basic timers (TIM6/7) Figure 162. Counter timing diagram, update event when ARPE=1 (TIMx_ARR preloaded) &.B36& &(1 7LPHUFORFN &.B&17 &RXQWHUUHJLVWHU ) ) ) ) ) ) &RXQWHURYHUIORZ 8SGDWHHYHQW8(9 8SGDWHLQWHUUXSWIODJ 8,) $XWRUHORDGSUHORDG UHJLVWHU ) $XWRUHORDGVKDGRZ UHJLVWHU ) :ULWHDQHZYDOXHLQ7,0[B$55 18.3.3 069 Clock source The counter clock is provided by the Internal clock (CK_INT) source. The CEN (in the TIMx_CR1 register) and UG bits (in the TIMx_EGR register) are actual control bits and can be changed only by software (except for UG that remains cleared automatically). As soon as the CEN bit is written to 1, the prescaler is clocked by the internal clock CK_INT. Figure 163 shows the behavior of the control circuit and the upcounter in normal mode, without prescaler. DocID025942 Rev 5 482/874 488 Basic timers (TIM6/7) RM0377 Figure 163. Control circuit in normal mode, internal clock divided by 1 ,QWHUQDOFORFN &(1 &17B(1 8* &17B,1,7 &RXQWHUFORFN &.B&17 &.B36& &RXQWHUUHJLVWHU 069 18.3.4 Debug mode When the microcontroller enters the debug mode (Cortex®-M0+ core - halted), the TIMx counter either continues to work normally or stops, depending on the DBG_TIMx_STOP configuration bit in the DBG module. For more details, refer to Section 27.9.2: Debug support for timers, watchdog and I2C. 483/874 DocID025942 Rev 5 RM0377 Basic timers (TIM6/7) 18.4 TIM6/7 registers Refer to Section 1.1: List of abbreviations for registers for a list of abbreviations used in register descriptions. The peripheral registers have to be written by half-words (16 bits) or words (32 bits). Read accesses can be done by bytes (8 bits), half-words (16 bits) or words (32 bits). 18.4.1 TIM6/7 control register 1 (TIMx_CR1) Address offset: 0x00 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. ARPE Res. Res. Res. OPM URS UDIS CEN rw rw rw rw rw Bits 15:8 Reserved, must be kept at reset value. Bit 7 ARPE: Auto-reload preload enable 0: TIMx_ARR register is not buffered. 1: TIMx_ARR register is buffered. Bits 6:4 Reserved, must be kept at reset value. Bit 3 OPM: One-pulse mode 0: Counter is not stopped at update event 1: Counter stops counting at the next update event (clearing the CEN bit). Bit 2 URS: Update request source This bit is set and cleared by software to select the UEV event sources. 0: Any of the following events generates an update interrupt or DMA request if enabled. These events can be: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller 1: Only counter overflow/underflow generates an update interrupt or DMA request if enabled. Bit 1 UDIS: Update disable This bit is set and cleared by software to enable/disable UEV event generation. 0: UEV enabled. The Update (UEV) event is generated by one of the following events: – Counter overflow/underflow – Setting the UG bit – Update generation through the slave mode controller Buffered registers are then loaded with their preload values. 1: UEV disabled. The Update event is not generated, shadow registers keep their value (ARR, PSC). However the counter and the prescaler are reinitialized if the UG bit is set or if a hardware reset is received from the slave mode controller. Bit 0 CEN: Counter enable 0: Counter disabled 1: Counter enabled Note: Gated mode can work only if the CEN bit has been previously set by software. However trigger mode can set the CEN bit automatically by hardware. CEN is cleared automatically in one-pulse mode, when an update event occurs. DocID025942 Rev 5 484/874 488 Basic timers (TIM6/7) 18.4.2 RM0377 TIM6/7 control register 2 (TIMx_CR2) Address offset: 0x04 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 Res. Res. Res. Res. Res. Res. Res. Res. Res. 6 5 4 MMS[2:0] rw rw 3 2 1 0 Res. Res. Res. Res. rw Bits 15:7 Reserved, must be kept at reset value. Bits 6:4 MMS: Master mode selection These bits are used to select the information to be sent in master mode to slave timers for synchronization (TRGO). The combination is as follows: 000: Reset - the UG bit from the TIMx_EGR register is used as a trigger output (TRGO). If reset is generated by the trigger input (slave mode controller configured in reset mode) then the signal on TRGO is delayed compared to the actual reset. 001: Enable - the Counter enable signal, CNT_EN, is used as a trigger output (TRGO). It is useful to start several timers at the same time or to control a window in which a slave timer is enabled. The Counter Enable signal is generated by a logic OR between CEN control bit and the trigger input when configured in gated mode. When the Counter Enable signal is controlled by the trigger input, there is a delay on TRGO, except if the master/slave mode is selected (see the MSM bit description in the TIMx_SMCR register). 010: Update - The update event is selected as a trigger output (TRGO). For instance a master timer can then be used as a prescaler for a slave timer. Bits 3:0 Reserved, must be kept at reset value. 18.4.3 TIM6/7 DMA/Interrupt enable register (TIMx_DIER) Address offset: 0x0C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. UDE Res. Res. Res. Res. Res. Res. Res. UIE rw Bit 15:9 Reserved, must be kept at reset value. Bit 8 UDE: Update DMA request enable 0: Update DMA request disabled. 1: Update DMA request enabled. Bit 7:1 Reserved, must be kept at reset value. Bit 0 UIE: Update interrupt enable 0: Update interrupt disabled. 1: Update interrupt enabled. 485/874 DocID025942 Rev 5 rw RM0377 Basic timers (TIM6/7) 18.4.4 TIM6/7 status register (TIMx_SR) Address offset: 0x10 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 0 UIF rc_w0 Bits 15:1 Reserved, must be kept at reset value. Bit 0 UIF: Update interrupt flag This bit is set by hardware on an update event. It is cleared by software. 0: No update occurred. 1: Update interrupt pending. This bit is set by hardware when the registers are updated: – At overflow or underflow regarding the repetition counter value and if UDIS = 0 in the TIMx_CR1 register. – When CNT is reinitialized by software using the UG bit in the TIMx_EGR register, if URS = 0 and UDIS = 0 in the TIMx_CR1 register. 18.4.5 TIM6/7 event generation register (TIMx_EGR) Address offset: 0x14 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. UG w Bits 15:1 Reserved, must be kept at reset value. Bit 0 UG: Update generation This bit can be set by software, it is automatically cleared by hardware. 0: No action. 1: Re-initializes the timer counter and generates an update of the registers. Note that the prescaler counter is cleared too (but the prescaler ratio is not affected). 18.4.6 TIM6/7 counter (TIMx_CNT) Address offset: 0x24 Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw CNT[15:0] rw rw Bits 15:0 rw rw rw rw rw rw rw CNT[15:0]: Counter value DocID025942 Rev 5 486/874 488 Basic timers (TIM6/7) 18.4.7 RM0377 TIM6/7 prescaler (TIMx_PSC) Address offset: 0x28 Reset value: 0x0000 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw PSC[15:0] rw Bits 15:0 PSC[15:0]: Prescaler value The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). PSC contains the value to be loaded into the active prescaler register at each update event. 18.4.8 TIM6/7 auto-reload register (TIMx_ARR) Address offset: 0x2C Reset value: 0x0000 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw ARR[15:0] rw rw rw rw rw rw rw rw rw Bits 15:0 ARR[15:0]: Auto-reload value ARR is the value to be loaded into the actual auto-reload register. Refer to Section 18.3.1: Time-base unit on page 477 for more details about ARR update and behavior. The counter is blocked while the auto-reload value is null. 487/874 DocID025942 Rev 5 RM0377 18.4.9 Basic timers (TIM6/7) TIM6/7 register map TIMx registers are mapped as 16-bit addressable registers as described in the table below: 6 5 4 3 2 1 0 Res. Res. Res. OPM URS UDIS CEN Res. Res. Res. Res. 7 ARPE Res. Res. Reset value 0 0x18 Res. 0x1C Res. 0x20 Res. 0x24 TIMx_CNT Reset value 0x28 0x2C CNT[15:0] 0 0 0 0 0 0 0 TIMx_PSC Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 PSC[15:0] 0 0 0 0 0 0 0 TIMx_ARR Reset value UG Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. TIMx_EGR Res. 0x14 0 Res. Reset value UIF Res. Res. Res. Res. Res. Res. 0 Res. Res. Res. Res. Res. Res. Res. TIMx_SR Res. 0x10 0 0 Res. Reset value UDE Res. Res. Res. Res. Res. TIMx_DIER Res. 0x0C 0 Res. Res. 0x08 0 UIE 8 Res. Res. Reset value MMS[2:0] Res. 9 Res. Res. Res. Res. Res. Res. Res. TIMx_CR2 Res. 0x04 Res. 10 Res. 0 Res. 11 Res. 0 Res. 12 Res. 0 0 Res. 13 Res. 0 Reset value Res. 14 TIMx_CR1 Res. 0x00 Register 15 Offset Res. Table 76. TIM6/7 register map and reset values 0 0 ARR[15:0] 0 0 0 0 0 0 0 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. DocID025942 Rev 5 488/874 488 Low-power timer (LPTIM) RM0377 19 Low-power timer (LPTIM) 19.1 Introduction The LPTIM is a 16-bit timer that benefits from the ultimate developments in power consumption reduction. Thanks to its diversity of clock sources, the LPTIM is able to keep running in all power modes except for Standby mode. Given its capability to run even with no internal clock source, the LPTIM can be used as a “Pulse Counter” which can be useful in some applications. Also, the LPTIM capability to wake up the system from low-power modes, makes it suitable to realize “Timeout functions” with extremely low power consumption. The LPTIM introduces a flexible clock scheme that provides the needed functionalities and performance, while minimizing the power consumption. 19.2 19.3 LPTIM main features 16 bit upcounter 3-bit prescaler with 8 possible dividing factor (1,2,4,8,16,32,64,128) Selectable clock – Internal clock sources: LSE, LSI, HSI16 or APB clock – External clock source over ULPTIM input (working with no LP oscillator running, used by Pulse Counter application) 16 bit ARR autoreload register 16 bit compare register Continuous/one shot mode Selectable software/hardware input trigger Programmable Digital Glitch filter Configurable output: Pulse, PWM Configurable I/O polarity Encoder mode LPTIM implementation Table 77 describes LPTIM implementation on STM32L0x1 devices. Table 77. STM32L0x1 LPTIM features LPTIM modes/features(1) Encoder mode X 1. X = supported. 489/874 LPTIM1 DocID025942 Rev 5 RM0377 Low-power timer (LPTIM) 19.4 LPTIM functional description 19.4.1 LPTIM block diagram Figure 164. Low-power timer block diagram- /37,0 $3%B,7) .HUQHO 8SGRZQ (QFRGHU XSWRH[W WULJJHU VZ WULJJHU *OLWFK ILOWHU 5&& *OLWFK ILOWHU ,QSXW *OLWFK ILOWHU ,QSXW ELW$55 0X[WULJJHU µ $3%FORFN /6( /6, +6, &/.08; &2817 02'( ELWFRXQWHU 2XW 3UHVFDOHU &.6(/ ELWFRPSDUH 069 19.4.2 LPTIM reset and clocks The LPTIM can be clocked using several clock sources. It can be clocked using an internal clock signal which can be chosen among APB, LSI, LSE or HSI16 sources through the Clock Tree controller (RCC). Also, the LPTIM can be clocked using an external clock signal injected on its external Input1. When clocked with an external clock source, the LPTIM may run in one of these two possible configurations: The first configuration is when the LPTIM is clocked by an external signal but in the same time an internal clock signal is provided to the LPTIM either from APB or any other embedded oscillator including LSE, LSI and HSI16. The second configuration is when the LPTIM is solely clocked by an external clock source through its external Input1. This configuration is the one used to realize Timeout function or Pulse counter function when all the embedded oscillators are turned off after entering a low-power mode. DocID025942 Rev 5 490/874 509 Low-power timer (LPTIM) RM0377 Programming the CKSEL and COUNTMODE bits allows controlling whether the LPTIM will use an external clock source or an internal one. When configured to use an external clock source, the CKPOL bits are used to select the external clock signal active edge. If both edges are configured to be active ones, an internal clock signal should also be provided (first configuration). In this case, the internal clock signal frequency should be at least four time higher than the external clock signal frequency. 19.4.3 Glitch filter The LPTIM inputs, either external or internal, are protected with digital filters that prevent any glitches and noise perturbations to propagate inside the LPTIM. This is in order to prevent spurious counts or triggers. Before activating the digital filters, an internal clock source should first be provided to the LPTIM. This is necessary to guarantee the proper operation of the filters. The digital filters are divided into two groups: Note: The first group of digital filters protects the LPTIM external inputs. The digital filters sensitivity is controlled by the CKFLT bits The second group of digital filters protects the LPTIM internal trigger inputs. The digital filters sensitivity is controlled by the TRGFLT bits. The digital filters sensitivity is controlled by groups. It is not possible to configure each digital filter sensitivity separately inside the same group. The filter sensitivity acts on the number of consecutive equal samples that should be detected on one of the LPTIM inputs to consider a signal level change as a valid transition. Figure 165 shows an example of glitch filter behavior in case of a 2 consecutive samples programmed. Figure 165. Glitch filter timing diagram &/.08; ,QSXW )LOWHURXW FRQVHFXWLYHVDPSOHV FRQVHFXWLYHVDPSOHV )LOWHUHG 069 Note: 491/874 In case no internal clock signal is provided, the digital filter must be deactivated by setting the CKFLT and TRGFLT bits to ‘0’. In that case, an external analog filter may be used to protect the LPTIM external inputs against glitches. DocID025942 Rev 5 RM0377 19.4.4 Low-power timer (LPTIM) Prescaler The LPTIM 16-bit counter is preceded by a configurable power-of-2 prescaler. The prescaler division ratio is controlled by the PRESC[2:0] 3-bit field. The table below lists all the possible division ratios: Table 78. Prescaler division ratios 19.4.5 programming dividing factor 000 /1 001 /2 010 /4 011 /8 100 /16 101 /32 110 /64 111 /128 Trigger multiplexer The LPTIM counter may be started either by software or after the detection of an active edge on one of the 8 trigger inputs. TRIGEN[1:0] is used to determine the LPTIM trigger source: When TRIGEN[1:0] equals ‘00’, The LPTIM counter is started as soon as one of the CNTSTRT or the SNGSTRT bits is set by software. The three remaining possible values for the TRIGEN[1:0] are used to configure the active edge used by the trigger inputs. The LPTIM counter starts as soon as an active edge is detected. When TRIGEN[1:0] is different than ‘00’, TRIGSEL[2:0] is used to select which of the 8 trigger inputs is used to start the counter. The external triggers are considered asynchronous signals for the LPTIM. So after a trigger detection, a two-counter-clock period latency is needed before the timer starts running due to the synchronization. If a new trigger event occurs when the timer is already started it will be ignored (unless timeout function is enabled). Note: The timer must be enabled before setting the SNGSTRT/CNTSTRT bits. Any write on these bits when the timer is disabled will be discarded by hardware. DocID025942 Rev 5 492/874 509 Low-power timer (LPTIM) 19.4.6 RM0377 Operating mode The LPTIM features two operating modes: The Continuous mode: the timer is free running, the timer is started from a trigger event and never stops until the timer is disabled One shot mode: the timer is started from a trigger event and stops when reaching the ARR value. A new trigger event will re-start the timer. Any trigger event occurring after the counter starts and before the counter reaches ARR will be discarded. To enable the one shot counting, the SNGSTRT bit must be set. In case an external trigger is selected, each external trigger event arriving after the SNGSTRT bit is set, and after the counter register has stopped (contains zero value), will start the counter for a new One-shot counting cycle as shown in Figure 166. Figure 166. LPTIM output waveform, Single counting mode configuration $55 &RPSDUH 3:0 ([WHUQDOWULJJHUHYHQW 06Y9 It should be noted that when the WAVE bit-field in the LPTIMx_CFGR register is set, the Set-once mode is activated. In this case, the counter is only started once following the first trigger, and any subsequent trigger event is discarded as shown in Figure 166. Figure 167. LPTIM output waveform, Single counting mode configuration and Set-once mode activated (WAVE bit is set) $55 &RPSDUH 'LVFDUGHGWULJJHU 3:0 ([WHUQDOWULJJHUHYHQW 06Y9 In case of software start (TRIGEN[1:0] = ‘00’), the SNGSTRT setting will start the counter for one shot counting. To enable the continuous counting, the CNTSTRT bit must be set. 493/874 DocID025942 Rev 5 RM0377 Low-power timer (LPTIM) In case an external trigger is selected, an external trigger event arriving after CNTSTRT is set will start the counter for continuous counting. Any subsequent external trigger event will be discarded as shown in Figure 168. In case of software start (TRIGEN[1:0] = ‘00’), setting CNTSTRT will start the counter for continuous counting. Figure 168. LPTIM output waveform, Continuous counting mode configuration 'LVFDUGHGWULJJHUV $55 &RPSDUH 3:0 ([WHUQDOWULJJHUHYHQW 06Y9 SNGSTRT and CNTSTRT bits can only be set when the timer is enabled (The ENABLE bit is set to ‘1’). It is possible to change “on the fly” from One Shot mode to Continuous mode. If the Continuous mode was previously selected, setting SNGSTRT will switch the LPTIM to the One Shot mode. The counter (if active) will stop as soon as it reaches ARR. If the One Shot mode was previously selected, setting CNTSTRT will switch the LPTIM to the Continuous mode. The counter (if active) will restart as soon as it reaches ARR. 19.4.7 Timeout function The detection of an active edge on one selected trigger input can be used to reset the LPTIM counter. This feature is controlled through the TIMOUT bit. The first trigger event will start the timer, any successive trigger event will reset the counter and the timer will restart. A low-power timeout function can be realized. The timeout value corresponds to the compare value; if no trigger occurs within the expected time frame, the MCU is waked-up by the compare match event. DocID025942 Rev 5 494/874 509 Low-power timer (LPTIM) 19.4.8 RM0377 Waveform generation Two 16-bit registers, the LPTIMx_ARR (autoreload register) and LPTIMx_CMP (Compare register), are used to generate several different waveforms on LPTIM output The timer can generate the following waveforms: The PWM mode: the LPTIM output is set as soon as a match occurs between the LPTIMx_CMP and the LPTIMx_CNT registers. The LPTIM output is reset as soon as a match occurs between the LPTIMx_ARR and the LPTIMx_CNT registers The One-pulse mode: the output waveform is similar to the one of the PWM mode for the first pulse, then the output is permanently reset The Set-once mode: the output waveform is similar to the One-pulse mode except that the output is kept to the last signal level (depends on the output configured polarity). The above described modes require that the LPTIMx_ARR register value be strictly greater than the LPTIMx_CMP register value. The LPTIM output waveform can be configured through the WAVE bit as follow: Resetting the WAVE bit to ‘0’ forces the LPTIM to generate either a PWM waveform or a One pulse waveform depending on which bit is set: CNTSTRT or SNGSTRT. Setting the WAVE bit to ‘1’ forces the LPTIM to generate a Set-once mode waveform. The WAVPOL bit controls the LPTIM output polarity. The change takes effect immediately, so the output default value will change immediately after the polarity is re-configured, even before the timer is enabled. Signals with frequencies up to the LPTIM clock frequency divided by 2 can be generated. Figure 169 below shows the three possible waveforms that can be generated on the LPTIM output. Also, it shows the effect of the polarity change using the WAVPOL bit. 495/874 DocID025942 Rev 5 RM0377 Low-power timer (LPTIM) Figure 169. Waveform generation $55 &RPSDUH 3:0 2QHVKRW 3RO 6HWRQFH 3:0 3RO 2QHVKRW 6HWRQFH 069 19.4.9 Register update The LPTIMx_ARR register and LPTIMx_CMP register are updated immediately after the APB bus write operation, or at the end of the current period if the timer is already started. The PRELOAD bit controls how the LPTIMx_ARR and the LPTIMx_CMP registers are updated: When the PRELOAD bit is reset to ‘0’, the LPTIMx_ARR and the LPTIMx_CMP registers are immediately updated after any write access. When the PRELOAD bit is set to ‘1’, the LPTIMx_ARR and the LPTIMx_CMP registers are updated at the end of the current period, if the timer has been already started. The APB bus and the LPTIM use different clocks, so there is some latency between the APB write and the moment when these values are available to the counter comparator. Within this latency period, any additional write into these registers must be avoided. The ARROK flag and the CMPOK flag in the LPTIMx_ISR register indicate when the write operation is completed to respectively the LPTIMx_ARR register and the LPTIMx_CMP register. After a write to the LPTIMx_ARR register or the LPTIMx_CMP register, a new write operation to the same register can only be performed when the previous write operation is completed. Any successive write before respectively the ARROK flag or the CMPOK flag be set, will lead to unpredictable results. DocID025942 Rev 5 496/874 509 Low-power timer (LPTIM) 19.4.10 RM0377 Counter mode The LPTIM counter can be used to count external events on the LPTIM Input1 or it can be used to count internal clock cycles. The CKSEL and COUNTMODE bits control which source will be used for updating the counter. In case the LPTIM is configured to count external events on Input1, the counter can be updated following a rising edge, falling edge or both edges depending on the value written to the CKPOL[1:0] bits. The count modes below can be selected, depending on CKSEL and COUNTMODE values: CKSEL = 0: the LPTIM is clocked by an internal clock source – COUNTMODE = 0 When the LPTIM is configured to be clocked by an internal clock source and the LPTIM counter is configured to be updated by active edges detected on the LPTIM external Input1, the internal clock provided to the LPTIM must be not be prescaled (PRESC[2:0] = ‘000’). – COUNTMODE = 1 The LPTIM external Input1 is sampled with the internal clock provided to the LPTIM. Consequently, in order not to miss any event, the frequency of the changes on the external Input1 signal should never exceed the frequency of the internal clock provided to the LPTIM. CKSEL = 1: the LPTIM is clocked by an external clock source COUNTMODE value is don’t care. In this configuration, the LPTIM has no need for an internal clock source (except if the glitch filters are enabled). The signal injected on the LPTIM external Input1 is used as system clock for the LPTIM. This configuration is suitable for operation modes where no embedded oscillator is enabled. For this configuration, the LPTIM counter can be updated either on rising edges or falling edges of the input1 clock signal but not on both rising and falling edges. Since the signal injected on the LPTIM external Input1 is also used to clock the LPTIM, there is some initial latency (after the LPTIM is enabled) before the counter is incremented. More precisely, the first five active edges on the LPTIM external Input1 (after LPTIM is enable) are lost. For code example, refer to A.10.1: Pulse counter configuration code example. 19.4.11 Timer enable The ENABLE bit located in the LPTIMx_CR register is used to enable/disable the LPTIM. After setting the ENABLE bit, a delay of two counter clock is needed before the LPTIM is actually enabled. The LPTIMx_CFGR and LPTIMx_IER registers must be modified only when the LPTIM is disabled. 497/874 DocID025942 Rev 5 RM0377 19.4.12 Low-power timer (LPTIM) Encoder mode This mode allows handling signals from quadrature encoders used to detect angular position of rotary elements. Encoder interface mode acts simply as an external clock with direction selection. This means that the counter just counts continuously between 0 and the auto-reload value programmed into the LPTIMx_ARR register (0 up to ARR or ARR down to 0 depending on the direction). Therefore you must configure LPTIMx_ARR before starting. From the two external input signals, Input1 and Input2, a clock signal is generated to clock the LPTIM counter. The phase between those two signals determines the counting direction. The Encoder mode is only available when the LPTIM is clocked by an internal clock source. The signals frequency on both Input1 and Input2 inputs must not exceed the LPTIM internal clock frequency divided by 4. This is mandatory in order to guarantee a proper operation of the LPTIM. Direction change is signalized by the two Down and Up flags in the LPTIMx_ISR register. Also, an interrupt can be generated for both direction change events if enabled through the LPTIMx_IER register. To activate the Encoder mode the ENC bit has to be set to ‘1’. The LPTIM must first be configured in Continuous mode. When Encoder mode is active, the LPTIM counter is modified automatically following the speed and the direction of the incremental encoder. Therefore, its content always represents the encoder’s position. The count direction, signaled by the Up and Down flags, correspond to the rotation direction of the connected sensor. According to the edge sensitivity configured using the CKPOL[1:0] bits, different counting scenarios are possible. The following table summarizes the possible combinations, assuming that Input1 and Input2 do not switch at the same time. Table 79. Encoder counting scenarios Active edge Rising Edge Falling Edge Both Edges Level on opposite signal (Input1 for Input2, Input2 for Input1) Input1 signal Input2 signal Rising Falling Rising Falling High Down No count Up No count Low Up No count Down No count High No count Up No count Down Low No count Down No count Up High Down Up Up Down Low Up Down Down Up The following figure shows a counting sequence for Encoder mode where both edges sensitivity is configured. Caution: In this mode the LPTIM must be clocked by an internal clock source, so the CKSEL bit must be maintained to its reset value which is equal to ‘0’. Also, the prescaler division ratio must be equal to its reset value which is 1 (PRESC[2:0] bits must be ‘000’). DocID025942 Rev 5 498/874 509 Low-power timer (LPTIM) RM0377 Figure 170. Encoder mode counting sequence 7 7 &RXQWHU XS 19.5 GRZQ XS 069 LPTIM interrupts The following events generate an interrupt/wake-up event, if they are enabled through the LPTIMx_IER register: Note: 499/874 Compare match Auto-reload match (whatever the direction if encoder mode) External trigger event Autoreload register write completed Compare register write completed Direction change (encoder mode), programmable (up / down / both). if any bit in the LPTIMx_IER register (Interrupt Enable Register) is set after that its corresponding flag in the LPTIMx_ISR register (Status Register) is set, the interrupt is not asserted DocID025942 Rev 5 RM0377 Low-power timer (LPTIM) 19.6 LPTIM registers 19.6.1 LPTIM interrupt and status register (LPTIMx_ISR) Address offset: 0x00 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN UP ARROK CMPOK EXTTRIG r r r r r ARRM CMPM r r Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWN: Counter direction change up to down In Encoder mode, DOWN bit is set by hardware to inform application that the counter direction has changed from up to down. Bit 5 UP: Counter direction change down to up In Encoder mode, UP bit is set by hardware to inform application that the counter direction has changed from down to up. Bit 4 ARROK: Autoreload register update OK ARROK is set by hardware to inform application that the APB bus write operation to the LPTIMx_ARR register has been successfully completed. If so, a new one can be initiated. Bit 3 CMPOK: Compare register update OK CMPOK is set by hardware to inform application that the APB bus write operation to the LPTIMx_CMP register has been successfully completed. If so, a new one can be initiated. Bit 2 EXTTRIG: External trigger edge event EXTTRIG is set by hardware to inform application that a valid edge on the selected external trigger input has occurred. If the trigger is ignored because the timer has already started, then this flag is not set. Bit 1 ARRM: Autoreload match ARRM is set by hardware to inform application that LPTIMx_CNT register’s value reached the LPTIMx_ARR register’s value. Bit 0 CMPM: Compare match The CMPM bit is set by hardware to inform application that LPTIMx_CNT register value reached the LPTIMx_CMP register’s value. DocID025942 Rev 5 500/874 509 Low-power timer (LPTIM) 19.6.2 RM0377 LPTIM interrupt clear register (LPTIMx_ICR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN CF UPCF ARRO KCF ARRM CF CMPM CF w w w w w Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWNCF: Direction change to down Clear Flag Writing 1 to this bit clear the DOWN flag in the LPT_ISR register Bit 5 UPCF: Direction change to UP Clear Flag Writing 1 to this bit clear the UP flag in the LPT_ISR register Bit 4 ARROKCF: Autoreload register update OK Clear Flag Writing 1 to this bit clears the ARROK flag in the LPT_ISR register Bit 3 CMPOKCF: Compare register update OK Clear Flag Writing 1 to this bit clears the CMPOK flag in the LPT_ISR register Bit 2 EXTTRIGCF: External trigger valid edge Clear Flag Writing 1 to this bit clears the EXTTRIG flag in the LPT_ISR register Bit 1 ARRMCF: Autoreload match Clear Flag Writing 1 to this bit clears the ARRM flag in the LPT_ISR register Bit 0 CMPMCF: compare match Clear Flag Writing 1 to this bit clears the CMP flag in the LPT_ISR register 501/874 DocID025942 Rev 5 CMPO EXTTR KCF IGCF w w RM0377 Low-power timer (LPTIM) 19.6.3 LPTIM interrupt enable register (LPTIMx_IER) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWNI E UPIE ARRO KIE rw rw rw CMPO EXTTR ARRMI CMPMI KIE IGIE E E rw rw rw rw Bits 31:7 Reserved, must be kept at reset value. Bit 6 DOWNIE: Direction change to down Interrupt Enable 0: DOWN interrupt disabled 1: DOWN interrupt enabled Bit 5 UPIE: Direction change to UP Interrupt Enable 0: UP interrupt disabled 1: UP interrupt enabled Bit 4 ARROKIE: Autoreload register update OK Interrupt Enable 0: ARROK interrupt disabled 1: ARROK interrupt enabled Bit 3 CMPOKIE: Compare register update OK Interrupt Enable 0: CMPOK interrupt disabled 1: CMPOK interrupt enabled Bit 2 EXTTRIGIE: External trigger valid edge Interrupt Enable 0: EXTTRIG interrupt disabled 1: EXTTRIG interrupt enabled Bit 1 ARRMIE: Autoreload match Interrupt Enable 0: ARRM interrupt disabled 1: ARRM interrupt enabled Bit 0 CMPMIE: Compare match Interrupt Enable 0: CMPM interrupt disabled 1: CMPM interrupt enabled Caution: The LPTIMx_IER register must only be modified when the LPTIM is disabled (ENABLE bit is reset to ‘0’) DocID025942 Rev 5 502/874 509 Low-power timer (LPTIM) 19.6.4 RM0377 LPTIM configuration register (LPTIMx_CFGR) Address offset: 0x0C Reset value: 0x0000 0000 31 30 29 28 27 26 25 Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 Res. TRIGSEL rw rw rw PRESC rw rw 24 ENC 23 22 21 COUNT PRELOAD WAVPOL MODE 20 19 WAVE TIMOUT 18 17 TRIGEN Res. rw rw rw rw rw rw rw rw 8 7 6 5 4 3 2 1 rw rw Res. rw TRGFLT rw rw Res. CKFLT rw 16 CKPOL 0 CKSEL rw rw Bits 31:25 Reserved, must be kept at reset value. Bit 24 ENC: Encoder mode enable The ENC bit controls the Encoder mode 0: Encoder mode disabled 1: Encoder mode enabled Bit 23 COUNTMODE: counter mode enabled The COUNTMODE bit selects which clock source is used by the LPTIM to clock the counter: 0: the counter is incremented following each internal clock pulse 1: the counter is incremented following each valid clock pulse on the LPTIM external Input1 Bit 22 PRELOAD: Registers update mode The PRELOAD bit controls the LPTIMx_ARR and the LPTIMx_CMP registers update modality 0: Registers are updated after each APB bus write access 1: Registers are updated at the end of the current LPTIM period Bit 21 WAVPOL: Waveform shape polarity The WAVEPOL bit controls the output polarity 0: The LPTIM output reflects the compare results between LPTIMx_ARR and LPTIMx_CMP registers 1: The LPTIM output reflects the inverse of the compare results between LPTIMx_ARR and LPTIMx_CMP registers Bit 20 WAVE: Waveform shape The WAVE bit controls the output shape 0: Deactivate Set-once mode, PWM / One Pulse waveform (depending on OPMODE bit) 1: Activate the Set-once mode Bit 19 TIMOUT: Timeout enable The TIMOUT bit controls the Timeout feature 0: a trigger event arriving when the timer is already started will be ignored 1: A trigger event arriving when the timer is already started will reset and restart the counter Bits18:17 TRIGEN: Trigger enable and polarity The TRIGEN bits controls whether the LPTIM counter is started by an external trigger or not. If the external trigger option is selected, three configurations are possible for the trigger active edge: 00: sw trigger (counting start is initiated by software) 01: rising edge is the active edge 10: falling edge is the active edge 11: both edges are active edges Bit 16 Reserved, must be kept at reset value. 503/874 DocID025942 Rev 5 RM0377 Low-power timer (LPTIM) Bits 15:13 TRIGSEL: Trigger selector The TRIGSEL bits select the trigger source that will serve as a trigger event for the LPTIM among the below 8 available sources: 000: ext_trig0 001: ext_trig1 010: ext_trig2 011: ext_trig3 100: ext_trig4 101: ext_trig5 110: ext_trig6 111: ext_trig7 See Table 80: LPTIM external trigger connection on page 505 for more details on the meaning of ITRx for each timer. Bit 12 Reserved, must be kept at reset value. Bits 11:9 PRESC: Clock prescaler The PRESC bits configure the prescaler division factor. It can be one among the following division factors: 000: /1 001: /2 010: /4 011: /8 100: /16 101: /32 110: /64 111: /128 Bit 8 Reserved, must be kept at reset value. Bits 7:6 TRGFLT: Configurable digital filter for trigger The TRGFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an internal trigger before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any trigger active level change is considered as a valid trigger 01: trigger active level change must be stable for at least 2 clock periods before it is considered as valid trigger. 10: trigger active level change must be stable for at least 4 clock periods before it is considered as valid trigger. 11: trigger active level change must be stable for at least 8 clock periods before it is considered as valid trigger. Bit 5 Reserved, must be kept at reset value. DocID025942 Rev 5 504/874 509 Low-power timer (LPTIM) RM0377 Bits 4:3 CKFLT: Configurable digital filter for external clock The CKFLT value sets the number of consecutive equal samples that should be detected when a level change occurs on an external clock signal before it is considered as a valid level transition. An internal clock source must be present to use this feature 00: any external clock signal level change is considered as a valid transition 01: external clock signal level change must be stable for at least 2 clock periods before it is considered as valid transition. 10: external clock signal level change must be stable for at least 4 clock periods before it is considered as valid transition. 11: external clock signal level change must be stable for at least 8 clock periods before it is considered as valid transition. Bits 2:1 CKPOL: Clock Polarity If LPTIM is clocked by an external clock source: When the LPTIM is clocked by an external clock source, CKPOL bits is used to configure the active edge or edges used by the counter: 00: the rising edge is the active edge used for counting 01: the falling edge is the active edge used for counting 10: both edges are active edges. When both external clock signal’s edges are considered active ones, the LPTIM must also be clocked by an internal clock source with a frequency equal to at least four time the external clock frequency. 11: not allowed If the LPTIM is configured in Encoder mode (ENC bit is set): 00: the encoder sub-mode 1 is active 01: the encoder sub-mode 2 is active 10: the encoder sub-mode 3 is active Refer to Section 19.4.12: Encoder mode for more details about Encoder mode sub-modes. Bit 0 CKSEL: Clock selector The CKSEL bit selects which clock source the LPTIM will use: 0: LPTIM is clocked by internal clock source (APB clock or any of the embedded oscillators) 1: LPTIM is clocked by an external clock source through the LPTIM external Input1 Caution: The LPTIMx_CFGR register must only be modified when the LPTIM is disabled (ENABLE bit is reset to ‘0’). Table 80. LPTIM external trigger connection 505/874 TRIGSEL External trigger ext_trig0 GPIO (alternate function LPTIMx_ETR) ext_trig1 RTC alarm A ext_trig2 RTC alarm B ext_trig3 RTC_TAMP1 input detection ext_trig4 RTC_TAMP2 input detection ext_trig5 RTC_TAMP3 input detection ext_trig6 COMP1_OUT ext_trig7 COMP2_OUT DocID025942 Rev 5 RM0377 Low-power timer (LPTIM) 19.6.5 LPTIM control register (LPTIMx_CR) Address offset: 0x10 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNT STRT SNG STRT ENA BLE rw rw rw Bits 31:3 Reserved, must be kept at reset value. Bit 2 CNTSTRT: Timer start in Continuous mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in Continuous mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the timer in Continuous mode as soon as an external trigger is detected. If this bit is set when a single pulse mode counting is ongoing, then the timer will not stop at the next match between the LPTIMx_ARR and LPTIMx_CNT registers and the LPTIM counter keeps counting in Continuous mode. This bit can be set only when the LPTIM is enabled. It will be automatically reset by hardware. Bit 1 SNGSTRT: LPTIM start in Single mode This bit is set by software and cleared by hardware. In case of software start (TRIGEN[1:0] = ‘00’), setting this bit starts the LPTIM in single pulse mode. If the software start is disabled (TRIGEN[1:0] different than ‘00’), setting this bit starts the LPTIM in single pulse mode as soon as an external trigger is detected. If this bit is set when the LPTIM is in continuous counting mode, then the LPTIM will stop at the following match between LPTIMx_ARR and LPTIMx_CNT registers. This bit can only be set when the LPTIM is enabled. It will be automatically reset by hardware. Bit 0 ENABLE: LPTIM enable The ENABLE bit is set and cleared by software. 0:LPTIM is disabled 1:LPTIM is enabled DocID025942 Rev 5 506/874 509 Low-power timer (LPTIM) 19.6.6 RM0377 LPTIM compare register (LPTIMx_CMP) Address offset: 0x14 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CMP[15:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CMP: Compare value CMP is the compare value used by the LPTIM. The LPTIMx_CMP register’s content must only be modified when the LPTIM is enabled (ENABLE bit is set to ‘1’). 19.6.7 LPTIM autoreload register (LPTIMx_ARR) Address offset: 0x18 Reset value: 0x0000 0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ARR[15:0] rw Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 ARR: Auto reload value ARR is the autoreload value for the LPTIM. This value must be strictly greater than the CMP[15:0] value. The LPTIMx_ARR register’s content must only be modified when the LPTIM is enabled (ENABLE bit is set to ‘1’). 507/874 DocID025942 Rev 5 RM0377 Low-power timer (LPTIM) 19.6.8 LPTIM counter register (LPTIMx_CNT) Address offset: 0x1C Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CNT[15:0] r Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 CNT: Counter value When the LPTIM is running with an asynchronous clock, reading the LPTIMx_CNT register may return unreliable values. So in this case it is necessary to perform two consecutive read accesses and verify that the two returned values are identical. It should be noted that for a reliable LPTIM_CNT register read access, two consecutive read accesses must be performed and compared. A read access can be considered reliable when the values of the two consecutive read accesses are equal. DocID025942 Rev 5 508/874 509 0x0C 0x10 0x14 0x18 0x1C 509/874 LPTIMx_CFGR Reset value LPTIMx_CMP LPTIMx_ARR LPTIMx_CNT Reset value DocID025942 Rev 5 0 0 0 0 0 0 0 0 Reset value Reset value 0 0 0 0 0 0 Refer to Section 2.2.2 on page 50 for the register boundary addresses. CKSEL CKPOL CKFLT Res. TRGFLT Res. PRESC Res. TRIGSEL Res. TRIGEN Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 LPTIMx_ISR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWN UP ARROK CMPOK EXTTRIG ARRM CMPM Reset value 0 0 0 0 0 0 0 LPTIMx_ICR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWNCF UPCF ARROKCF CMPOKCF EXTTRIGCF ARRMCF CMPMCF Reset value 0 0 0 0 0 0 0 LPTIMx_IER Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. DOWNIE UPIE ARROKIE CMPOKIE EXTTRIGIE ARRMIE CMPMIE 0x08 Res. Res. Res. Res. Res. Res. Res. ENC COUNTMODE PRELOAD WAVPOL WAVE TIMOUT 0x04 LPTIMx_CR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. CNTSTRT SNGSTRT ENABLE 0x00 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 19.6.9 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Low-power timer (LPTIM) RM0377 LPTIM register map The following table summarizes the LPTIM registers. Table 81. LPTIM register map and reset values Reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Reset value 0 0 0 CMP[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ARR[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 CNT[15:0] 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RM0377 Independent watchdog (IWDG) 20 Independent watchdog (IWDG) 20.1 Introduction The devices feature an embedded watchdog peripheral which offers a combination of high safety level, timing accuracy and flexibility of use. The Independent watchdog peripheral serves to detect and resolve malfunctions due to software failure, and to trigger system reset when the counter reaches a given timeout value. The independent watchdog (IWDG) is clocked by its own dedicated low-speed clock (LSI) and thus stays active even if the main clock fails. The IWDG is best suited to applications which require the watchdog to run as a totally independent process outside the main application, but have lower timing accuracy constraints. For further information on the window watchdog, refer to Section 21 on page 519. 20.2 IWDG main features Free-running downcounter Clocked from an independent RC oscillator (can operate in Standby and Stop modes) Conditional Reset – Reset (if watchdog activated) when the downcounter value becomes less than 0x000 – Reset (if watchdog activated) if the downcounter is reloaded outside the window 20.3 IWDG functional description 20.3.1 IWDG block diagram Figure 171 shows the functional blocks of the independent watchdog module. Figure 171. Independent watchdog block diagram 9'' 3UHVFDOHUUHJLVWHU ,:'*B35 6WDWXVUHJLVWHU ,:'*B65 5HORDGUHJLVWHU ,:'*B5/5 .H\UHJLVWHU ,:'*B.5 ELWUHORDGYDOXH /6, ELW N+] SUHVFDOHU ELWGRZQFRXQWHU ,:'*UHVHW 9''YROWDJHGRPDLQ 06Y9 Note: The watchdog function is implemented in the VDD voltage domain that is still functional in Standby mode. DocID025942 Rev 5 510/874 518 Independent watchdog (IWDG) RM0377 When the independent watchdog is started by writing the value 0x0000 CCCC in the Key register (IWDG_KR), the counter starts counting down from the reset value of 0xFFF. When it reaches the end of count value (0x000) a reset signal is generated (IWDG reset). Whenever the key value 0x0000 AAAA is written in the IWDG_KR register, the IWDG_RLR value is reloaded in the counter and the watchdog reset is prevented. 20.3.2 Window option The IWDG can also work as a window watchdog by setting the appropriate window in the IWDG_WINR register. If the reload operation is performed while the counter is greater than the value stored in the window register (IWDG_WINR), then a reset is provided. The default value of the IWDG_WINR is 0x0000 0FFF, so if it is not updated, the window option is disabled. As soon as the window value is changed, a reload operation is performed in order to reset the downcounter to the IWDG_RLR value and ease the cycle number calculation to generate the next reload. Configuring the IWDG when the window option is enabled Note: 1. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register. 2. Enable register access by writing 0x0000 5555 in the IWDG_KR register. 3. Write the IWDG prescaler by programming IWDG_PR from 0 to 7. 4. Write the reload register (IWDG_RLR). 5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000). 6. Write to the window register IWDG_WINR. This automatically refreshes the counter value IWDG_RLR. Writing the window value allows to refresh the Counter value by the RLR when IWDG_SR is set to 0x0000 0000. For code example, refer to A.11.2: IWDG configuration with window code example. Configuring the IWDG when the window option is disabled When the window option it is not used, the IWDG can be configured as follows: 1. Enable the IWDG by writing 0x0000 CCCC in the IWDG_KR register. 2. Enable register access by writing 0x0000 5555 in the IWDG_KR register. 3. Write the IWDG prescaler by programming IWDG_PR from 0 to 7. 4. Write the reload register (IWDG_RLR). 5. Wait for the registers to be updated (IWDG_SR = 0x0000 0000). 6. Refresh the counter value with IWDG_RLR (IWDG_KR = 0x0000 AAAA) For code example, refer to A.11.1: IWDG configuration code example. 20.3.3 Hardware watchdog If the “Hardware watchdog” feature is enabled through the device option bits, the watchdog is automatically enabled at power-on, and generates a reset unless the Key register is 511/874 DocID025942 Rev 5 RM0377 Independent watchdog (IWDG) written by the software before the counter reaches end of count or if the downcounter is reloaded inside the window. 20.3.4 Behavior in Stop and Standby modes Once running, the IWDG cannot be stopped. 20.3.5 Register access protection Write access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers is protected. To modify them, you must first write the code 0x0000 5555 in the IWDG_KR register. A write access to this register with a different value will break the sequence and register access will be protected again. This implies that it is the case of the reload operation (writing 0x0000 AAAA). A status register is available to indicate that an update of the prescaler or the down-counter reload value or the window value is on going. 20.3.6 Debug mode When the microcontroller enters debug mode (core halted), the IWDG counter either continues to work normally or stops, depending on DBG_IWDG_STOP configuration bit in DBG module. DocID025942 Rev 5 512/874 518 Independent watchdog (IWDG) 20.4 RM0377 IWDG registers Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 20.4.1 Key register (IWDG_KR) Address offset: 0x00 Reset value: 0x0000 0000 (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 w w w w w w w KEY[15:0] w w w w w w w w w Bits 31:16 Reserved, must be kept at reset value. Bits 15:0 KEY[15:0]: Key value (write only, read 0x0000) These bits must be written by software at regular intervals with the key value 0xAAAA, otherwise the watchdog generates a reset when the counter reaches 0. Writing the key value 0x5555 to enable access to the IWDG_PR, IWDG_RLR and IWDG_WINR registers (see Section 20.3.5: Register access protection) Writing the key value CCCCh starts the watchdog (except if the hardware watchdog option is selected) 513/874 DocID025942 Rev 5 RM0377 Independent watchdog (IWDG) 20.4.2 Prescaler register (IWDG_PR) Address offset: 0x04 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. PR[2:0] rw rw rw Bits 31:3 Reserved, must be kept at reset value. Bits 2:0 PR[2:0]: Prescaler divider These bits are write access protected see Section 20.3.5: Register access protection. They are written by software to select the prescaler divider feeding the counter clock. PVU bit of IWDG_SR must be reset in order to be able to change the prescaler divider. 000: divider /4 001: divider /8 010: divider /16 011: divider /32 100: divider /64 101: divider /128 110: divider /256 111: divider /256 Note: Reading this register returns the prescaler value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the PVU bit in the IWDG_SR register is reset. DocID025942 Rev 5 514/874 518 Independent watchdog (IWDG) 20.4.3 RM0377 Reload register (IWDG_RLR) Address offset: 0x08 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. RL[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits11:0 RL[11:0]: Watchdog counter reload value These bits are write access protected see Section 20.3.5. They are written by software to define the value to be loaded in the watchdog counter each time the value 0xAAAA is written in the IWDG_KR register. The watchdog counter counts down from this value. The timeout period is a function of this value and the clock prescaler. Refer to the datasheet for the timeout information. The RVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be up to date/valid if a write operation to this register is ongoing on this register. For this reason the value read from this register is valid only when the RVU bit in the IWDG_SR register is reset. 515/874 DocID025942 Rev 5 RM0377 Independent watchdog (IWDG) 20.4.4 Status register (IWDG_SR) Address offset: 0x0C Reset value: 0x0000 0000 (not reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WVU RVU PVU r r r Bits 31:3 Reserved, must be kept at reset value. Bit 2 WVU: Watchdog counter window value update This bit is set by hardware to indicate that an update of the window value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Window value can be updated only when WVU bit is reset. This bit is generated only if generic “window” = 1 Bit 1 RVU: Watchdog counter reload value update This bit is set by hardware to indicate that an update of the reload value is ongoing. It is reset by hardware when the reload value update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Reload value can be updated only when RVU bit is reset. Bit 0 PVU: Watchdog prescaler value update This bit is set by hardware to indicate that an update of the prescaler value is ongoing. It is reset by hardware when the prescaler update operation is completed in the VDD voltage domain (takes up to 5 RC 40 kHz cycles). Prescaler value can be updated only when PVU bit is reset. Note: If several reload, prescaler, or window values are used by the application, it is mandatory to wait until RVU bit is reset before changing the reload value, to wait until PVU bit is reset before changing the prescaler value, and to wait until WVU bit is reset before changing the window value. However, after updating the prescaler and/or the reload/window value it is not necessary to wait until RVU or PVU or WVU is reset before continuing code execution except in case of low-power mode entry. DocID025942 Rev 5 516/874 518 Independent watchdog (IWDG) 20.4.5 RM0377 Window register (IWDG_WINR) Address offset: 0x10 Reset value: 0x0000 0FFF (reset by Standby mode) 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 11 10 9 8 7 6 5 4 3 2 1 0 rw rw rw rw rw 15 14 13 12 Res. Res. Res. Res. WIN[11:0] rw rw rw rw rw rw rw Bits 31:12 Reserved, must be kept at reset value. Bits11:0 WIN[11:0]: Watchdog counter window value These bits are write access protected see Section 20.3.5. These bits contain the high limit of the window value to be compared to the downcounter. To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x0 The WVU bit in the IWDG_SR register must be reset in order to be able to change the reload value. Note: Reading this register returns the reload value from the VDD voltage domain. This value may not be valid if a write operation to this register is ongoing. For this reason the value read from this register is valid only when the WVU bit in the IWDG_SR register is reset. 517/874 DocID025942 Rev 5 RM0377 20.4.6 Independent watchdog (IWDG) IWDG register map The following table gives the IWDG register map and reset values. 0x00 Register IWDG_KR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Offset 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 82. IWDG register map and reset values 0x04 IWDG_PR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value KEY[15:0] 0x08 IWDG_ RLR 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value IWDG_SR RL[11:0] 1 1 1 1 1 1 1 1 1 1 1 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WVU RVU PVU Reset value 0x0C 0x10 0 0 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Reset value IWDG_ WINR PR[2:0] Reset value WIN[11:0] 1 1 1 1 1 1 1 1 1 1 1 1 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. DocID025942 Rev 5 518/874 518 System window watchdog (WWDG) RM0377 21 System window watchdog (WWDG) 21.1 Introduction The system window watchdog (WWDG) is used to detect the occurrence of a software fault, usually generated by external interference or by unforeseen logical conditions, which causes the application program to abandon its normal sequence. The watchdog circuit generates an MCU reset on expiry of a programmed time period, unless the program refreshes the contents of the downcounter before the T6 bit becomes cleared. An MCU reset is also generated if the 7-bit downcounter value (in the control register) is refreshed before the downcounter has reached the window register value. This implies that the counter must be refreshed in a limited window. The WWDG clock is prescaled from the APB1 clock and has a configurable time-window that can be programmed to detect abnormally late or early application behavior. The WWDG is best suited for applications which require the watchdog to react within an accurate timing window. 21.2 WWDG main features Programmable free-running downcounter Conditional reset 21.3 – Reset (if watchdog activated) when the downcounter value becomes less than 0x40 – Reset (if watchdog activated) if the downcounter is reloaded outside the window (see Figure 173) Early wakeup interrupt (EWI): triggered (if enabled and the watchdog activated) when the downcounter is equal to 0x40. WWDG functional description If the watchdog is activated (the WDGA bit is set in the WWDG_CR register) and when the 7-bit downcounter (T[6:0] bits) is decremented from 0x40 to 0x3F (T6 becomes cleared), it initiates a reset. If the software reloads the counter while the counter is greater than the value stored in the window register, then a reset is generated. 519/874 DocID025942 Rev 5 RM0377 System window watchdog (WWDG) Figure 172. Watchdog block diagram 5(6(7 :DWFKGRJFRQILJXUDWLRQUHJLVWHU::'*B&)5 FRPSDUDWRU ZKHQ 7!: : : : : : : : :ULWH::'*B&5 :DWFKGRJFRQWUROUHJLVWHU::'*B&5 :'*$ 3&/. IURP5&&FORFNFRQWUROOHU 7 7 7 7 7 7 7 ELWGRZQFRXQWHU&17 :'*SUHVFDOHU :'*7% 06Y9 The application program must write in the WWDG_CR register at regular intervals during normal operation to prevent an MCU reset. This operation must occur only when the counter value is lower than the window register value and higher than 0x3F. The value to be stored in the WWDG_CR register must be between 0xFF and 0xC0. 21.3.1 Enabling the watchdog The watchdog is always disabled after a reset. It is enabled by setting the WDGA bit in the WWDG_CR register, then it cannot be disabled again except by a reset. 21.3.2 Controlling the downcounter This downcounter is free-running, counting down even if the watchdog is disabled. When the watchdog is enabled, the T6 bit must be set to prevent generating an immediate reset. The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. The timing varies between a minimum and a maximum value due to the unknown status of the prescaler when writing to the WWDG_CR register (see Figure 173). The Configuration register (WWDG_CFR) contains the high limit of the window: To prevent a reset, the downcounter must be reloaded when its value is lower than the window register value and greater than 0x3F. Figure 173 describes the window watchdog process. Note: The T6 bit can be used to generate a software reset (the WDGA bit is set and the T6 bit is cleared). 21.3.3 Advanced watchdog interrupt feature The Early Wakeup Interrupt (EWI) can be used if specific safety operations or data logging must be performed before the actual reset is generated. The EWI interrupt is enabled by setting the EWI bit in the WWDG_CFR register. When the downcounter reaches the value 0x40, an EWI interrupt is generated and the corresponding interrupt service routine (ISR) can be used to trigger specific actions (such as communications or data logging), before resetting the device. DocID025942 Rev 5 520/874 525 System window watchdog (WWDG) RM0377 In some applications, the EWI interrupt can be used to manage a software system check and/or system recovery/graceful degradation, without generating a WWDG reset. In this case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to avoid the WWDG reset, then trigger the required actions. The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register. Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task, the WWDG reset will eventually be generated. 21.3.4 How to program the watchdog timeout You can use the formula in Figure 173 to calculate the WWDG timeout. Warning: When writing to the WWDG_CR register, always write 1 in the T6 bit to avoid generating an immediate reset. Figure 173. Window watchdog timing diagram 4;=#.4DOWNCOUNTER 7;= X& 2EFRESHNOTALLOWED 2EFRESHALLOWED 4IME 4BIT 2%3%4 AIC The formula to calculate the timeout value is given by: WDGTB[1:0] T 5:0 + 1 t WWDG = t PCLK1 4096 2 where: tWWDG: WWDG timeout tPCLK: APB1 clock period measured in ms 4096: value corresponding to internal divider 521/874 DocID025942 Rev 5 ms RM0377 System window watchdog (WWDG) As an example, lets assume APB1 frequency is equal to 32 MHz, WDGTB[1:0] is set to 3 and T[5:0] is set to 63: t WWDG 3 = 1 32000 4096 2 63 + 1 = 65.54 ms Refer to the datasheet for the minimum and maximum values of the tWWDG. For code example, refer to A.12.1: WWDG configuration code example. 21.3.5 Debug mode When the microcontroller enters debug mode (Cortex®-M0+ core halted), the WWDG counter either continues to work normally or stops, depending on DBG_WWDG_STOP configuration bit in DBG module. For more details, refer to Section 27.9.2: Debug support for timers, watchdog and I2C. DocID025942 Rev 5 522/874 525 System window watchdog (WWDG) 21.4 RM0377 WWDG registers Refer to Section 1.1 on page 43 for a list of abbreviations used in register descriptions. The peripheral registers can be accessed by half-words (16-bit) or words (32-bit). 21.4.1 Control register (WWDG_CR) Address offset: 0x00 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. WDGA T[6:0] rs rw Bits 31:8 Reserved, must be kept at reset value. Bit 7 WDGA: Activation bit This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Bits 6:0 T[6:0]: 7-bit counter (MSB to LSB) These bits contain the value of the watchdog counter. It is decremented every (4096 x 2WDGTB[1:0]) PCLK cycles. A reset is produced when it is decremented from 0x40 to 0x3F (T6 becomes cleared). 523/874 DocID025942 Rev 5 RM0377 System window watchdog (WWDG) 21.4.2 Configuration register (WWDG_CFR) Address offset: 0x04 Reset value: 0x0000 007F 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 8 7 6 5 4 3 2 1 0 rw rw rw 15 14 13 12 11 10 9 Res. Res. Res. Res. Res. Res. EWI rs WDGTB[1:0] rw rw W[6:0] rw rw rw rw Bits 31:10 Reserved, must be kept at reset value. Bit 9 EWI: Early wakeup interrupt When set, an interrupt occurs whenever the counter reaches the value 0x40. This interrupt is only cleared by hardware after a reset. Bits 8:7 WDGTB[1:0]: Timer base The time base of the prescaler can be modified as follows: 00: CK Counter Clock (PCLK div 4096) div 1 01: CK Counter Clock (PCLK div 4096) div 2 10: CK Counter Clock (PCLK div 4096) div 4 11: CK Counter Clock (PCLK div 4096) div 8 Bits 6:0 W[6:0]: 7-bit window value These bits contain the window value to be compared to the downcounter. 21.4.3 Status register (WWDG_SR) Address offset: 0x08 Reset value: 0x0000 0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWIF rc_w0 Bits 31:1 Reserved, must be kept at reset value. Bit 0 EWIF: Early wakeup interrupt flag This bit is set by hardware when the counter has reached the value 0x40. It must be cleared by software by writing ‘0’. A write of ‘1’ has no effect. This bit is also set if the interrupt is not enabled. DocID025942 Rev 5 524/874 525 System window watchdog (WWDG) 21.4.4 RM0377 WWDG register map The following table gives the WWDG register map and reset values. Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0x00 WWDG_ CR Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. WDGA Table 83. WWDG register map and reset values 0x04 WWDG_ CFR 0 1 1 1 1 1 1 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWI WDGTB1 WDGTB0 Reset value WWDG_ SR W[6:0] 0 0 0 1 1 1 1 1 1 1 Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. Res. EWIF Reset value 0x08 T[6:0] Reset value 0 Refer to Section 2.2.2: Memory map and register boundary addresses for the register boundary addresses. 525/874 DocID025942 Rev 5 RM0377 Real-time clock (RTC) 22 Real-time clock (RTC) 22.1 Introduction The RTC provides an automatic wakeup to manage all low-power modes. The real-time clock (RTC) is an independent BCD timer/counter. The RTC provides a timeof-day clock/calendar with programmable alarm interrupts. The RTC includes also a periodic programmable wakeup flag with interrupt capability. Two 32-bit registers contain the seconds, minutes, hours (12- or 24-hour format), day (day of week), date (day of month), month, and year, expressed in binary coded decimal format (BCD). The sub-seconds value is also available in binary format. Compensations for 28-, 29- (leap year), 30-, and 31-day months are performed automatically. Daylight saving time compensation can also be performed. Additional 32-bit registers contain the programmable alarm subseconds, seconds, minutes, hours, day, and date. A digital calibration feature is available to compensate for any deviation in crystal oscillator accuracy. After RTC domain reset, all RTC registers are protected against possible parasitic write accesses. As long as the supply voltage remains in the operating range, the RTC never stops, regardless of the device status (Run mode, low-power mode or under reset). DocID025942 Rev 5 526/874 570 Real-time clock (RTC) 22.2 RM0377 RTC main features The RTC unit main features are the following (see Figure 174: RTC block diagram): Calendar with subseconds, seconds, minutes, hours (12 or 24 format), day (day of week), date (day of month), month, and year. Daylight saving compensation programmable by software. Programmable alarm with interrupt function. The alarm can be triggered by any combination of the calendar fields. Automatic wakeup unit generating a periodic flag that triggers an automatic wakeup interrupt. Reference clock detection: a more precise second source clock (50 or 60 Hz) can be used to enhance the calendar precision. Accurate synchronization with an external clock using the subsecond shift feature. Digital calibration circuit (periodic counter correction): 0.95 ppm accuracy, obtained in a calibration window of several seconds Time-stamp function for event saving Tamper detection event with configurable filter and internal pull-up Maskable interrupts/events: 527/874 – Alarm A – Alarm B – Wakeup interrupt – Time-stamp – Tamper detection 5 backup registers. DocID025942 Rev 5 RM0377 Real-time clock (RTC) 22.3 RTC functional description 22.3.1 RTC block diagram Figure 174. RTC block diagram 57&B7$03 %DFNXSUHJLVWHUV DQG57&WDPSHU FRQWUROUHJLVWHUV 57&B7$03 7$03[) 57&B7$03 57&B76 7LPHVWDPS UHJLVWHUV 76) 57&B5(),1 /6(+] +6( /6, 57&&/. 57&B&$/5 57&B35(5 6PRRWK FDOLEUDWLRQ $V\QFKURQRXV ELWSUHVFDOHU GHIDXOW FNBDSUH GHIDXOW+] 57&B35(5 6\QFKURQRXV ELWSUHVFDOHU GHIDXOW 6KDGRZUHJLVWHU 57&B665 FNBVSUH GHIDXOW+] &DOHQGDU 6KDGRZUHJLVWHUV 57&B75 57&B'5 :8&.6(/>@ 3UHVFDOHU +] 57&B&$/,% +] 57&B$/$50 2XSXW FRQWURO 57&B287 57&B:875 :87) ELWZDNHXS DXWRUHORDGWLPHU 26(/>@ $ODUP$ $/5$) 57&B$/50$5 57&B$/50$665 $ODUP% 57&B$/50%5 57&B$/50%665 $/5%) 069 1. RTC_TAMP3 is available only on category 1, category 2 and category 5 devices. DocID025942 Rev 5 528/874 570 Real-time clock (RTC) RM0377 The RTC includes: Two alarms Up to three tamper events 5 x 32-bit backup registers Alternate function outputs: RTC_OUT which selects one of the following two outputs: 22.3.2 – RTC_CALIB: 512 Hz or 1Hz clock output (with an LSE frequency of 32.768 kHz). This output is enabled by setting the COE bit in the RTC_CR register. – RTC_ALARM: This output is enabled by configuring the OSEL[1:0] bits in the RTC_CR register which select the Alarm A, Alarm B or Wakeup outputs. Alternate function inputs: – RTC_TS: timestamp event – RTC_TAMP1: tamper1 event detection – RTC_TAMP2: tamper2 event detection – RTC_TAMP3: tamper3 event detection (category 1 and 5 devices only) – RTC_REFIN: 50 or 60 Hz reference clock input GPIOs controlled by the RTC RTC_OUT, RTC_TS and RTC_TAMP1 are mapped on the same pin (PC13). PC13 pin configuration is controlled by the RTC, whatever the PC13 GPIO configuration. The output mechanism follows the priority order shown in Table 84. Table 84. RTC pin PC13 configuration(1) OSEL[1:0] bits PC13 Pin configuration (RTC_ALARM and function output enable) COE bit (RTC_CALIB output enable) RTC_OUT _RMP bit 01 or 10 or 11 Don’t care RTC_ALARM output PP 01 or 10 or 11 Don’t care RTC_CALIB output PP 00 1 0 00 0 Don’t care 00 1 01 or 10 or 11 0 00 0 00 1 01 or 10 or 11 0 RTC_TAMP1 input floating RTC_TS and RTC_TAMP1 input floating 529/874 TAMP1E bit (RTC_TAMP1 input enable) (RTC_TS input enable) 0 Don’t care Don’t care 1 Don’t care Don’t care Don’t care Don’t care Don’t care Don’t care 1 0 Don’t care 1 1 0 RTC_ALARM output OD TSE bit RTC_ALARM _TYPE bit 1 0 1 1 Don’t care 1 DocID025942 Rev 5 RM0377 Real-time clock (RTC) Table 84. RTC pin PC13 configuration(1) (continued) OSEL[1:0] bits PC13 Pin configuration (RTC_ALARM and function output enable) RTC_TS input floating Wakeup pin or Standard GPIO COE bit (RTC_CALIB output enable) RTC_OUT 00 0 Don’t care 00 1 01 or 10 or 11 0 00 0 00 1 01 or 10 or 11 0 _RMP bit TSE bit RTC_ALARM _TYPE bit TAMP1E bit (RTC_TAMP1 input enable) (RTC_TS input enable) Don’t care 0 1 Don’t care 0 0 1 Don’t care 1 1. OD: open drain; PP: push-pull. In addition, it is possible to remap RTC_OUT on PB14 pin thanks to RTC_OUT_RMP bit. In this case it is mandatory to configure PB14 GPIO registers as alternate function with the correct type. The remap functions are shown in Table 85. Table 85. RTC_OUT mapping OSEL[1:0] bits 22.3.3 (RTC_ALARM output enable) COE bit (RTC_CALIB output enable) 00 0 00 1 01 or 10 or 11 RTC_OUT_RMP bit RTC_OUT on PC13 RTC_OUT on PB14 - - RTC_CALIB - Don’t care RTC_ALARM - 00 0 - - 00 1 - RTC_CALIB 01 or 10 or 11 0 - RTC_ALARM 01 or 10 or 11 1 RTC_ALARM RTC_CALIB 0 1 Clock and prescalers The RTC clock source (RTCCLK) is selected through the clock controller among the LSE clock, the LSI oscillator clock, and the HSE clock. For more information on the RTC clock source configuration, refer to Section 7: Reset and clock control (RCC). A programmable prescaler stage generates a 1 Hz clock which is used to update the calendar. To minimize power consumption, the prescaler is split into 2 programmable prescalers (see Figure 174: RTC block diagram): A 7-bit asynchronous prescaler configured through the PREDIV_A bits of the RTC_PRER register. A 15-bit synchronous prescaler configured through the PREDIV_S bits of the RTC_PRER register. DocID025942 Rev 5 530/874 570 Real-time clock (RTC) Note: RM0377 When both prescalers are used, it is recommended to configure the asynchronous prescaler to a high value to minimize consumption. The asynchronous prescaler division factor is set to 128, and the synchronous division factor to 256, to obtain an internal clock frequency of 1 Hz (ck_spre) with an LSE frequency of 32.768 kHz. The minimum division factor is 1 and the maximum division factor is 222. This corresponds to a maximum input frequency of around 4 MHz. fck_apre is given by the following formula: f RTCCLK f CK_APRE = --------------------------------------PREDIV_A + 1 The ck_apre clock is used to clock the binary RTC_SSR subseconds downcounter. When it reaches 0, RTC_SSR is reloaded with the content of PREDIV_S. fck_spre is given by the following formula: f RTCCLK f CK_SPRE = --------------------------------------------------------------------------------------------- PREDIV_S + 1 PREDIV_A + 1 The ck_spre clock can be used either to update the calendar or as timebase for the 16-bit wakeup auto-reload timer. To obtain short timeout periods, the 16-bit wakeup auto-reload timer can also run with the RTCCLK divided by the programmable 4-bit asynchronous prescaler (see Section 22.3.6: Periodic auto-wakeup for details). 22.3.4 Real-time clock and calendar The RTC calendar time and date registers are accessed through shadow registers which are synchronized with PCLK (APB clock). They can also be accessed directly in order to avoid waiting for the synchronization duration. RTC_SSR for the subseconds RTC_TR for the time RTC_DR for the date Every two RTCCLK periods, the current calendar value is copied into the shadow registers, and the RSF bit of RTC_ISR register is set (see Section 22.6.4: RTC initialization and status register (RTC_ISR)). The copy is not performed in Stop and Standby mode. When exiting these modes, the shadow registers are updated after up to 2 RTCCLK periods. When the application reads the calendar registers, it accesses the content of the shadow registers. It is possible to make a direct access to the calendar registers by setting the BYPSHAD control bit in the RTC_CR register. By default, this bit is cleared, and the user accesses the shadow registers. When reading the RTC_SSR, RTC_TR or RTC_DR registers in BYPSHAD=0 mode, the frequency of the APB clock (fAPB) must be at least 7 times the frequency of the RTC clock (fRTCCLK). The shadow registers are reset by system reset. 531/874 DocID025942 Rev 5 RM0377 22.3.5 Real-time clock (RTC) Programmable alarms The RTC unit provides programmable alarm: Alarm A and Alarm B. The description below is given for Alarm A, but can be translated in the same way for Alarm B. The programmable alarm function is enabled through the ALRAE bit in the RTC_CR register. The ALRAF is set to 1 if the calendar subseconds, seconds, minutes, hours, date or day match the values programmed in the alarm registers RTC_ALRMASSR and RTC_ALRMAR. Each calendar field can be independently selected through the MSKx bits of the RTC_ALRMAR register, and through the MASKSSx bits of the RTC_ALRMASSR register. The alarm interrupt is enabled through the ALRAIE bit in the RTC_CR register. Caution: If the seconds field is selected (MSK1 bit reset in RTC_ALRMAR), the synchronous prescaler division factor set in the RTC_PRER register must be at least 3 to ensure correct behavior. Alarm A and Alarm B (if enabled by bits OSEL[1:0] in RTC_CR register) can be routed to the RTC_ALARM output. RTC_ALARM output polarity can be configured through bit POL the RTC_CR register. 22.3.6 Periodic auto-wakeup The periodic wakeup flag is generated by a 16-bit programmable auto-reload down-counter. The wakeup timer range can be extended to 17 bits. The wakeup function is enabled through the WUTE bit in the RTC_CR register. The wakeup timer clock input can be: RTC clock (RTCCLK) divided by 2, 4, 8, or 16. When RTCCLK is LSE(32.768kHz), this allows to configure the wakeup interrupt period from 122 µs to 32 s, with a resolution down to 61 µs. ck_spre (usually 1 Hz internal clock) When ck_spre frequency is 1Hz, this allows to achieve a wakeup time from 1 s to around 36 hours with one-second resolution. This large programmable time range is divided in 2 parts: – from 1s to 18 hours when WUCKSEL [2:1] = 10 – and from around 18h to 36h when WUCKSEL[2:1] = 11. In this last case 216 is added to the 16-bit counter current value.When the initialization sequence is complete (see Programming the wakeup timer on page 534), the timer starts counting down.When the wakeup function is enabled, the down-counting remains active in low-power modes. In addition, when it reaches 0, the WUTF flag is set in the RTC_ISR register, and the wakeup counter is automatically reloaded with its reload value (RTC_WUTR register value). The WUTF flag must then be cleared by software. When the periodic wakeup interrupt is enabled by setting the WUTIE bit in the RTC_CR2 register, it can exit the device from low-power modes. The periodic wakeup flag can be routed to the RTC_ALARM output provided it has been enabled through bits OSEL[1:0] of RTC_CR register. RTC_ALARM output polarity can be configured through the POL bit in the RTC_CR register. System reset, as well as low-power modes (Sleep, Stop and Standby) have no influence on the wakeup timer. DocID025942 Rev 5 532/874 570 Real-time clock (RTC) 22.3.7 RM0377 RTC initialization and configuration RTC register access The RTC registers are 32-bit registers. The APB interface introduces 2 wait-states in RTC register accesses except on read accesses to calendar shadow registers when BYPSHAD=0. RTC register write protection After system reset, the RTC registers are protected against parasitic write access by clearing the DBP bit in the PWR_CR register (refer to the power control section). DBP bit must be set in order to enable RTC registers write access. After RTC domain reset, all the RTC registers are write-protected. Writing to the RTC registers is enabled by writing a key into the Write Protection register, RTC_WPR. The following steps are required to unlock the write protection on all the RTC registers except for RTC_TAMPCR, RTC_BKPxR, RTC_OR and RTC_ISR[13:8]. 1. Write ‘0xCA’ into the RTC_WPR register. 2. Write ‘0x53’ into the RTC_WPR register. Writing a wrong key reactivates the write protection. The protection mechanism is not affected by system reset. Calendar initialization and configuration To program the initial time and date calendar values, including the time format and the prescaler configuration, the following sequence is required: 1. Set INIT bit to 1 in the RTC_ISR register to enter initialization mode. In this mode, the calendar counter is stopped and its value can be updated. 2. Poll INITF bit of in the RTC_ISR register. The initialization phase mode is entered when INITF is set to 1. It takes around 2 RTCCLK clock cycles (due to clock synchronization). 3. To generate a 1 Hz clock for the calendar counter, program both the prescaler factors in RTC_PRER register. 4. Load the initial time and date values in the shadow registers (RTC_TR and RTC_DR), and configure the time format (12 or 24 hours) through the FMT bit in the RTC_CR register. 5. Exit the initialization mode by clearing the INIT bit. The actual calendar counter value is then automatically loaded and the counting restarts after 4 RTCCLK clock cycles. When the initialization sequence is complete, the calendar starts counting. Note: After a system reset, the application can read the INITS flag in the RTC_ISR register to check if the calendar has been initialized or not. If this flag equals 0, the calendar has not been initialized since the year field is set at its RTC domain reset default value (0x00). To read the calendar after initialization, the software must first check that the RSF flag is set in the RTC_ISR register. For code example, refer to A.13.1: RTC calendar configuration code example. 533/874 DocID025942 Rev 5 RM0377 Real-time clock (RTC) Daylight saving time The daylight saving time management is performed through bits SUB1H, ADD1H, and BKP of the RTC_CR register. Using SUB1H or ADD1H, the software can subtract or add one hour to the calendar in one single operation without going through the initialization procedure. In addition, the software can use the BKP bit to memorize this operation. Programming the alarm A similar procedure must be followed to program or update the programmable alarms. The procedure below is given for Alarm A but can be translated in the same way for Alarm B. Note: 1. Clear ALRAE in RTC_CR to disable Alarm A. 2. Program the Alarm A registers (RTC_ALRMASSR/RTC_ALRMAR). 3. Set ALRAE in the RTC_CR register to enable Alarm A again. Each change of the RTC_CR register is taken into account after around 2 RTCCLK clock cycles due to clock synchronization. For code example, refer to A.13.2: RTC alarm configuration code example. Programming the wakeup timer The following sequence is required to configure or change the wakeup timer auto-reload value (WUT[15:0] in RTC_WUTR): 1. Clear WUTE in RTC_CR to disable the wakeup timer. 2. Poll WUTWF until it is set in RTC_ISR to make sure the access to wakeup auto-reload counter and to WUCKSEL[2:0] bits is allowed. It takes around 2 RTCCLK clock cycles (due to clock synchronization). 3. Program the wakeup auto-reload value WUT[15:0], and the wakeup clock selection (WUCKSEL[2:0] bits in RTC_CR). Set WUTE in RTC_CR to enable the timer again. The wakeup timer restarts down-counting. The WUTWF bit is cleared up to 2 RTCCLK clock cycles after WUTE is cleared, due to clock synchronization. For code example, refer to A.13.3: RTC WUT configuration code example. 22.3.8 Reading the calendar When BYPSHAD control bit is cleared in the RTC_CR register To read the RTC calendar registers (RTC_SSR, RTC_TR and RTC_DR) properly, the APB1 clock frequency (fPCLK) must be equal to or greater than seven times the RTC clock frequency (fRTCCLK). This ensures a secure behavior of the synchronization mechanism. If the APB1 clock frequency is less than seven times the RTC clock frequency, the software must read the calendar time and date registers twice. If the second read of the RTC_TR gives the same result as the first read, this ensures that the data is correct. Otherwise a third read access must be done. In any case the APB1 clock frequency must never be lower than the RTC clock frequency. The RSF bit is set in RTC_ISR register each time the calendar registers are copied into the RTC_SSR, RTC_TR and RTC_DR shadow registers. The copy is performed every two RTCCLK cycles. To ensure consistency between the 3 values, reading either RTC_SSR or RTC_TR locks the values in the higher-order calendar shadow registers until RTC_DR is DocID025942 Rev 5 534/874 570 Real-time clock (RTC) RM0377 read. In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers. After waking up from low-power mode (Stop or Standby), RSF must be cleared by software. The software must then wait until it is set again before reading the RTC_SSR, RTC_TR and RTC_DR registers. The RSF bit must be cleared after wakeup and not before entering low-power mode. After a system reset, the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. Indeed, a system reset resets the shadow registers to their default values. After an initialization (refer to Calendar initialization and configuration on page 533): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. After synchronization (refer to Section 22.3.10: RTC synchronization): the software must wait until RSF is set before reading the RTC_SSR, RTC_TR and RTC_DR registers. For code example, refer to A.13.4: RTC read calendar code example. When the BYPSHAD control bit is set in the RTC_CR register (bypass shadow registers) Reading the calendar registers gives the values from the calendar counters directly, thus eliminating the need to wait for the RSF bit to be set. This is especially useful after exiting from low-power modes (STOP or Standby), since the shadow registers are not updated during these modes. When the BYPSHAD bit is set to 1, the results of the different registers might not be coherent with each other if an RTCCLK edge occurs between two read accesses to the registers. Additionally, the value of one of the registers may be incorrect if an RTCCLK edge occurs during the read operation. The software must read all the registers twice, and then compare the results to confirm that the data is coherent and correct. Alternatively, the software can just compare the two results of the least-significant calendar register. Note: While BYPSHAD=1, instructions which read the calendar registers require one extra APB cycle to complete. 22.3.9 Resetting the RTC The calendar shadow registers (RTC_SSR, RTC_TR and RTC_DR) and some bits of the RTC status register (RTC_ISR) are reset to their default values by all available system reset sources. On the contrary, the following registers are reset to their default values by a RTC domain reset and are not affected by a system reset: the RTC current calendar registers, the RTC control register (RTC_CR), the prescaler register (RTC_PRER), the RTC calibration register (RTC_CALR), the RTC shift register (RTC_SHIFTR), the RTC timestamp registers (RTC_TSSSR, RTC_TSTR and RTC_TSDR), the RTC tamper and alternate function configuration register (RTC_TAMPCR), the RTC backup registers (RTC_BKPxR), the wakeup timer register (RTC_WUTR), the Alarm A and Alarm B registers 535/874 DocID025942 Rev 5 RM0377 Real-time clock (RTC) (RTC_ALRMASSR/RTC_ALRMAR and RTC_ALRMBSSR/RTC_ALRMBR), and the Option register (RTC_OR). In addition, when it is clocked by the LSE, the RTC keeps on running under system reset if the reset source is different from the RTC domain reset one (refer to the RTC clock section of the Reset an