STM32L051x6 STM32L051x8
Access line ultra-low-power 32-bit MCU ARM®-based Cortex®-M0+,
up to 64 KB Flash, 8 KB SRAM, 2 KB EEPROM, ADC
Datasheet - production data
Features
Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40 to 125 °C temperature range
– 0.27 µA Standby mode (2 wakeup pins)
– 0.4 µA Stop mode (16 wakeup lines)
– 0.8 µA Stop mode + RTC + 8 KB RAM retention
– 88 µA/MHz in Run mode
– 3.5 µs wakeup time (from RAM)
– 5 µs wakeup time (from Flash memory)
Core: ARM® 32-bit Cortex®-M0+ with MPU
– From 32 kHz up to 32 MHz max.
– 0.95 DMIPS/MHz
Reset and supply management
– Ultra-safe, low-power BOR (brownout reset)
with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
Clock sources
– 1 to 25 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– High speed internal 16 MHz factory-trimmed RC
(+/- 1%)
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to
4.2 MHz RC
– PLL for CPU clock
Pre-programmed bootloader
– USART, SPI supported
Development support
– Serial wire debug supported
Up to 51 fast I/Os (45 I/Os 5V tolerant)
Memories
– Up to 64 KB Flash memory with ECC
– 8KB RAM
– 2 KB of data EEPROM with ECC
– 20-byte backup register
– Sector protection against R/W operation
March 2016
This is information on a product in full production.
)%*$
UFQFPN32
5x5 mm
LQFP32 7x7 mm
LQFP48 7x7 mm
LQFP64 10x10 mm
WLCSP36
TFBGA64
5x5mm
Rich Analog peripherals
– 12-bit ADC 1.14 Msps up to 16 channels (down
to 1.65 V)
– 2x ultra-low-power comparators (window mode
and wake up capability, down to 1.65 V)
7-channel DMA controller, supporting ADC, SPI,
I2C, USART, Timers
7x peripheral communication interfaces
– 2x USART (ISO 7816, IrDA), 1x UART (low
power)
– Up to 4x SPI 16 Mbits/s
– 2x I2C (SMBus/PMBus)
9x timers: 1x 16-bit with up to 4 channels, 2x 16-bit
with up to 2 channels, 1x 16-bit ultra-low-power
timer, 1x SysTick, 1x RTC, 1x 16-bit basic, and 2x
watchdogs (independent/window)
CRC calculation unit, 96-bit unique ID
All packages are ECOPACK®2
Table 1. Device summary
Reference
Part number
STM32L051x6
STM32L051C6,
STM32L051K6,
STM32L051R6,
STM32L051T6
STM32L051x8
STM32L051C8,
STM32L051K8,
STM32L051R8,
STM32L051T8
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www.st.com
Contents
STM32L051x6 STM32L051x8
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3
2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.2
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2
Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3
ARM® Cortex®-M0+ core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.4.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.6
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 24
3.7
General-purpose inputs/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.8
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.9
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.10
Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.11
Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.12.1
2/127
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.13
Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 27
3.14
System configuration controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.15.1
General-purpose timers (TIM2, TIM21 and TIM22) . . . . . . . . . . . . . . . . 28
3.15.2
Low-power Timer (LPTIM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.3
Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.4
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.5
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.15.6
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
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Contents
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.16.1
I2C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.16.2
Universal synchronous/asynchronous receiver transmitter (USART) . . 31
3.16.3
Low-power universal asynchronous receiver transmitter (LPUART) . . . 31
3.16.4
Serial peripheral interface (SPI)/Inter-integrated sound (I2S) . . . . . . . . 32
3.17
Cyclic redundancy check (CRC) calculation unit . . . . . . . . . . . . . . . . . . . 32
3.18
Serial wire debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
4
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.1.7
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
6.3.2
Embedded reset and power control block characteristics . . . . . . . . . . . 53
6.3.3
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 54
6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.3.5
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
6.3.10
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
6.3.11
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.12
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
6.3.13
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.14
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
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STM32L051x6 STM32L051x8
6.3.15
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.16
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.17
Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.18
Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
6.3.19
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.1
LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
7.2
TFBGA64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
7.3
LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7.4
WLCSP36 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
7.5
LQFP32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113
7.6
UFQFPN32 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116
7.7
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
7.7.1
Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
8
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
9
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ultra-low-power STM32L051x6/x8 device features and peripheral counts. . . . . . . . . . . . . 11
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 15
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 16
Functionalities depending on the working mode
(from Run/active down to standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
STM32L0xx peripherals interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Internal voltage reference measured values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
STM32L051x6/8 I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
USART implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STM32L051x6/8 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Alternate function port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Alternate function port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Alternate function port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Alternate function port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 53
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Current consumption in Run mode, code with data processing running from Flash. . . . . . 56
Current consumption in Run mode vs code type,
code with data processing running from Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Current consumption in Run mode, code with data processing running from RAM . . . . . . 58
Current consumption in Run mode vs code type,
code with data processing running from RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 62
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 63
Average current consumption during Wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Peripheral current consumption in Run or Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Peripheral current consumption in Stop and Standby mode . . . . . . . . . . . . . . . . . . . . . . . 65
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
16 MHz HSI16 oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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List of tables
Table 46.
Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
Table 83.
Table 84.
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STM32L051x6 STM32L051x8
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 76
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
RAIN max for fADC = 16 MHz . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
USART/LPUART characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
SPI characteristics in voltage Range 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
SPI characteristics in voltage Range 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
SPI characteristics in voltage Range 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
grid array package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
TFBGA64 recommended PCB design rules (0.5 mm pitch BGA). . . . . . . . . . . . . . . . . . . 105
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 108
WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
WLCSP36 recommended PCB design rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data. . . . . . . . . . . 114
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
STM32L051x6/8 ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DocID025938 Rev 6
STM32L051x6 STM32L051x8
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
STM32L051x6/8 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
STM32L051x6/8 LQFP64 pinout - 10 x 10 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
STM32L051x6/8 TFBGA64 ballout - 5x 5 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
STM32L051x6/8 LQFP48 pinout - 7 x 7 mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L051x6/8 WLCSP36 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L051x6/8 LQFP32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STM32L051x6/8 UFQFPN32 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSE, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Low-power run mode, code running
from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled
and running on LSE Low drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled,
all clocks off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
HSI16 minimum and maximum value versus temperature . . . . . . . . . . . . . . . . . . . . . . . . . 72
VIH/VIL versus VDD (CMOS I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
VIH/VIL versus VDD (TTL I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . . 90
Power supply and reference decoupling (VREF+ connected to VDDA). . . . . . . . . . . . . . . . . 91
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 101
LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint . . . . . . . . . . 102
LQFP64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball
grid array package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
,grid array recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
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8
List of figures
Figure 42.
Figure 43.
Figure 44.
Figure 45.
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
8/127
STM32L051x6 STM32L051x8
TFBGA64 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 107
LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 109
LQFP48 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
WLCSP36 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 113
LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint . . . . . . . . . . . . 114
LQFP32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
UFQFPN32 marking example (package top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
DocID025938 Rev 6
STM32L051x6 STM32L051x8
1
Introduction
Introduction
The ultra-low-power STM32L051x6/8 are offered in 6 different package types: from 32 pins
to 64 pins. Depending on the device chosen, different sets of peripherals are included, the
description below gives an overview of the complete range of peripherals proposed in this
family.
These features make the ultra-low-power STM32L051x6/8 microcontrollers suitable for a
wide range of applications:
Gas/water meters and industrial sensors
Healthcare and fitness equipment
Remote control and user interface
PC peripherals, gaming, GPS equipment
Alarm system, wired and wireless sensors, video intercom
This STM32L051x6/8 datasheet should be read in conjunction with the STM32L0x1xx
reference manual (RM0377).
For information on the ARM® Cortex®-M0+ core please refer to the Cortex®-M0+ Technical
Reference Manual, available from the www.arm.com website.
Figure 1 shows the general block diagram of the device family.
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32
Description
2
STM32L051x6 STM32L051x8
Description
The access line ultra-low-power STM32L051x6/8 microcontrollers incorporate the highperformance ARM® Cortex®-M0+ 32-bit RISC core operating at a 32 MHz frequency, a
memory protection unit (MPU), high-speed embedded memories (64 Kbytes of Flash
program memory, 2 Kbytes of data EEPROM and 8 Kbytes of RAM) plus an extensive range
of enhanced I/Os and peripherals.
The STM32L051x6/8 devices provide high power efficiency for a wide range of
performance. It is achieved with a large choice of internal and external clock sources, an
internal voltage adaptation and several low-power modes.
The STM32L051x6/8 devices offer several analog features, one 12-bit ADC with hardware
oversampling, two ultra-low-power comparators, several timers, one low-power timer
(LPTIM), three general-purpose 16-bit timers and one basic timer, one RTC and one
SysTick which can be used as timebases. They also feature two watchdogs, one watchdog
with independent clock and window capability and one window watchdog based on bus
clock.
Moreover, the STM32L051x6/8 devices embed standard and advanced communication
interfaces: up to two I2C, two SPIs, one I2S, two USARTs, a low-power UART (LPUART), .
The STM32L051x6/8 also include a real-time clock and a set of backup registers that
remain powered in Standby mode.
The ultra-low-power STM32L051x6/8 devices operate from a 1.8 to 3.6 V power supply
(down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power supply without
BOR option. They are available in the -40 to +125 °C temperature range. A comprehensive
set of power-saving modes allows the design of low-power applications.
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STM32L051x6 STM32L051x8
2.1
Description
Device overview
Table 2. Ultra-low-power STM32L051x6/x8 device features and peripheral counts
Peripheral
STM32
L051K6
STM32L
051T6
STM32
L051C6
STM32
L051R6
STM32
L051K8
STM32L STM32
051T8 L051C8
Flash (Kbytes)
32
64
Data EEPROM (Kbytes)
2
2
RAM (Kbytes)
8
8
Generalpurpose
3
3
Basic
1
1
LPTIMER
1
1
1/1/1/1
1/1/1/1
Timers
RTC/SYSTICK/IWDG/
WWDG
SPI/I2S
Communication
interfaces
I2C
3(2)(1)/0
3(2)(1)/0
4(2)(1)/1
4(2)(1)/1
3(2)(1)/0
3(2)(1)/1
4(2)(1)/1
4(2)(1)/1
1
2
2
2
1
2
2
2
USART
LPUART
GPIOs
Clocks:
HSE/LSE/HSI/MSI/LSI
12-bit synchronized ADC
Number of channels
2
2
0
1
1
1
0
1
1
1
27(2)
29
37
51(3)
27(2)
29
37
51(3)
0/1/1/1/1
1
10
0/1/1/1/1 1/1/1/1/1 1/1/1/1/1
1
10
1
10
Comparators
0/1/1/1/1
1
16(3)
1
10
0/1/1/1/1 1/1/1/1/1 1/1/1/1/1
1
10
2
1
10
1
16(3)
2
Max. CPU frequency
32 MHz
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
Operating voltage
Ambient temperature: –40 to +125 °C
Junction temperature: –40 to +130 °C
Operating temperatures
Packages
STM32
L051R8
LQFP32,
UFQFPN
32
WLCSP
36
LQFP48
LQFP64
TFBGA
64
LQFP32,
UFQFPN
32
WLCSP
36
LQFP48
LQFP64
TFBGA
64
1. 2 SPI interfaces are USARTs operating in SPI master mode.
2. LQFP32 has two GPIOs, less than UFQFPN32 (27).
3. TFBGA64 has one GPIO, one ADC input and one capacitive sensing channel less than LQFP64.
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32
Description
STM32L051x6 STM32L051x8
Figure 1. STM32L051x6/8 block diagram
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12/127
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STM32L051x6 STM32L051x8
2.2
Description
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of core and features, from 8-bit proprietary
core up to ARM® Cortex®-M4, including ARM® Cortex®-M3 and ARM® Cortex®-M0+. The
STM32Lx series are the best choice to answer your needs in terms of ultra-low-power
features. The STM32 ultra-low-power series are the best solution for applications such as
gaz/water meter, keyboard/mouse or fitness and healthcare application. Several built-in
features like LCD drivers, dual-bank memory, low-power run mode, operational amplifiers,
128-bit AES, DAC, crystal-less USB and many other definitely help you building a highly
cost optimized application by reducing BOM cost. STMicroelectronics, as a reliable and
long-term manufacturer, ensures as much as possible pin-to-pin compatibility between all
STM8Lx and STM32Lx on one hand, and between all STM32Lx and STM32Fx on the other
hand. Thanks to this unprecedented scalability, your legacy application can be upgraded to
respond to the latest market feature and efficiency requirements.
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32
Functional overview
STM32L051x6 STM32L051x8
3
Functional overview
3.1
Low-power modes
The ultra-low-power STM32L051x6/8 support dynamic voltage scaling to optimize its power
consumption in Run mode. The voltage from the internal low-drop regulator that supplies
the logic can be adjusted according to the system’s maximum operating frequency and the
external voltage supply.
There are three power consumption ranges:
Range 1 (VDD range limited to 1.71-3.6 V), with the CPU running at up to 32 MHz
Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
Range 3 (full VDD range), with a maximum CPU frequency limited to 4.2 MHz
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the lowspeed clock (max 131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In Lowpower run mode, the clock frequency and the number of enabled peripherals are both
limited.
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the Run
mode with the regulator on.
Stop mode with RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSE crystal and HSI RC oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The device can be woken up from Stop mode by any of the EXTI line, in 3.5 µs, the
processor can serve the interrupt or resume the code. The EXTI line source can be any
GPIO. It can be the PVD output, the comparator 1 event or comparator 2 event
(if internal reference voltage is on), it can be the RTC alarm/tamper/timestamp/wakeup
events, the USART/I2C/LPUART/LPTIMER wakeup events.
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Functional overview
Stop mode without RTC
The Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, HSE and
LSE crystal oscillators are disabled.
Some peripherals featuring wakeup capability can enable the HSI RC during Stop
mode to detect their wakeup condition.
The voltage regulator is in the low-power mode. The device can be woken up from Stop
mode by any of the EXTI line, in 3.5 µs, the processor can serve the interrupt or
resume the code. The EXTI line source can be any GPIO. It can be the PVD output, the
comparator 1 event or comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USART/I2C/LPUART/LPTIMER wakeup events.
Standby mode with RTC
The Standby mode is used to achieve the lowest power consumption and real time
clock. The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSE crystal and HSI RC oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32 KHz oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
Standby mode without RTC
The Standby mode is used to achieve the lowest power consumption. The internal
voltage regulator is switched off so that the entire VCORE domain is powered off. The
PLL, MSI RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off.
After entering Standby mode, the RAM and register contents are lost except for
registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32 KHz
oscillator, RCC_CSR register).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 3. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Operating power supply
range
ADC operation
Dynamic voltage
scaling range
I/O operation
VDD = 1.65 to 1.71 V
ADC only,
conversion time up
to 570 ksps
Range 2 or
range 3
Degraded speed
performance
VDD = 1.71 to 1.8 V(1)
ADC only,
conversion time up
to 1.14 Msps
Range 1, range 2 or
range 3
Degraded speed
performance
VDD = 1.8 to 2.0 V(1)
Conversion time up
to 1.14 Msps
Range1, range 2 or
range 3
Degraded speed
performance
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32
Functional overview
STM32L051x6 STM32L051x8
Table 3. Functionalities depending on the operating power supply range (continued)
Functionalities depending on the operating power supply range
Operating power supply
range
ADC operation
Dynamic voltage
scaling range
I/O operation
VDD = 2.0 to 2.4 V
Conversion time up
to 1.14 Msps
Range 1, range 2 or
range 3
Full speed operation
VDD = 2.4 to 3.6 V
Conversion time up
to 1.14 Msps
Range 1, range 2 or
range 3
Full speed operation
1. CPU frequency changes from initial to final must respect "fcpu initial <4*fcpu final". It must also respect 5
μs delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2
MHz to 16 MHz, wait 5 μs, then switch from 16 MHz to 32 MHz.
Table 4. CPU frequency range depending on dynamic voltage scaling
CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
Range 2
32 kHz to 4.2 MHz (0ws)
Range 3
Table 5. Functionalities depending on the working mode
(from Run/active down to standby) (1)
Standby
Run/Active
Sleep
CPU
Y
--
Y
--
--
--
Flash memory
O
O
O
O
--
--
RAM
Y
Y
Y
Y
Y
--
Backup registers
Y
Y
Y
Y
Y
Y
EEPROM
O
O
O
O
--
--
Brown-out reset
(BOR)
O
O
O
O
O
DMA
O
O
O
O
--
Programmable
Voltage Detector
(PVD)
O
O
O
O
O
O
-
Power-on/down
reset (POR/PDR)
Y
Y
Y
Y
Y
Y
Y
High Speed
Internal (HSI)
O
O
--
--
(2)
IPs
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DocID025938 Rev 6
Lowpower
sleep
Stop
Lowpower
run
Wakeup
capability
O
Wakeup
capability
O
O
--
--
Y
STM32L051x6 STM32L051x8
Functional overview
Table 5. Functionalities depending on the working mode
(from Run/active down to standby) (continued)(1)
Standby
Run/Active
Sleep
High Speed
External (HSE)
O
O
O
O
--
--
Low Speed Internal
(LSI)
O
O
O
O
O
O
Low Speed
External (LSE)
O
O
O
O
O
O
Multi-Speed
Internal (MSI)
O
O
Y
Y
--
--
Inter-Connect
Controller
Y
Y
Y
Y
Y
--
RTC
O
O
O
O
O
O
O
RTC Tamper
O
O
O
O
O
O
O
O
Auto WakeUp
(AWU)
O
O
O
O
O
O
O
O
USART
O
O
O
O
O(3)
O
--
(3)
O
--
IPs
Lowpower
sleep
Stop
Lowpower
run
Wakeup
capability
LPUART
O
O
O
O
SPI
O
O
O
O
--
I2C
O
O
O
O
O(4)
ADC
O
O
--
--
--
--
Temperature
sensor
O
O
O
O
O
--
Comparators
O
O
O
O
O
16-bit timers
O
O
O
O
--
LPTIMER
O
O
O
O
O
O
IWDG
O
O
O
O
O
O
WWDG
O
O
O
O
--
SysTick Timer
O
O
O
O
GPIOs
O
O
O
O
0 µs
0.36 µs
3 µs
32 µs
Wakeup time to
Run mode
DocID025938 Rev 6
O
Wakeup
capability
-O
O
--
---
O
O
---
O
O
3.5 µs
2 pins
50 µs
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Functional overview
STM32L051x6 STM32L051x8
Table 5. Functionalities depending on the working mode
(from Run/active down to standby) (continued)(1)
IPs
Run/Active
Sleep
Lowpower
run
Stop
Lowpower
sleep
Standby
Wakeup
capability
Wakeup
capability
0.28 µA (No
0.4 µA (No
RTC) VDD=1.8 V RTC) VDD=1.8 V
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to
140 µA/MHz
(from Flash
memory)
Down to
37 µA/MHz
(from Flash
memory)
Down to
8 µA
0.65 µA (with
0.8 µA (with
=1.8
V
RTC)
VDD=1.8 V
RTC)
V
DD
Down to
4.5 µA
0.29 µA (No
0.4 µA (No
RTC) VDD=3.0 V RTC) VDD=3.0 V
1 µA (with RTC)
0.85 µA (with
VDD=3.0 V
RTC) VDD=3.0 V
1. Legend:
“Y” = Yes (enable).
“O” = Optional can be enabled/disabled by software)
“-” = Not available
2. Some peripherals with wakeup from Stop capability can request HSI to be enabled. In this case, HSI is woken up by the
peripheral, and only feeds the peripheral which requested it. HSI is automatically put off when the peripheral does not need
it anymore.
3. UART and LPUART reception is functional in Stop mode. It generates a wakeup interrupt on Start. To generate a wakeup
on address match or received frame event, the LPUART can run on LSE clock while the UART has to wake up or keep
running the HSI clock.
4. I2C address detection is functional in Stop mode. It generates a wakeup interrupt in case of address match. It will wake up
the HSI during reception.
3.2
Interconnect matrix
Several peripherals are directly interconnected. This allows autonomous communication
between peripherals, thus saving CPU resources and power consumption. In addition,
these hardware connections allow fast and predictable latency.
Depending on peripherals, these interconnections can operate in Run, Sleep, Low-power
run, Low-power sleep and Stop modes.
Table 6. STM32L0xx peripherals interconnect matrix
Interconnect
source
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Lowpower
sleep
Stop
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
-
Interconnect action
Run
TIM2,TIM21,
TIM22
Timer input channel,
trigger from analog
signals comparison
Y
Y
LPTIM
Timer input channel,
trigger from analog
signals comparison
Y
TIMx
Timer triggered by other
timer
Y
COMPx
TIMx
LowSleep power
run
Interconnect
destination
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Functional overview
Table 6. STM32L0xx peripherals interconnect matrix (continued)
Interconnect
source
Lowpower
sleep
Stop
Y
Y
-
Y
Y
Y
Y
Y
Y
Y
Y
-
Timer input channel and
trigger
Y
Y
Y
Y
-
LPTIM
Timer input channel and
trigger
Y
Y
Y
Y
Y
ADC
Conversion trigger
Y
Y
Y
Y
-
Interconnect action
Run
TIM21
Timer triggered by Auto
wake-up
Y
Y
LPTIM
Timer triggered by RTC
event
Y
TIMx
Clock source used as
input channel for RC
measurement and
trimming
TIMx
RTC
All clock
source
GPIO
3.3
LowSleep power
run
Interconnect
destination
ARM® Cortex®-M0+ core with MPU
The Cortex-M0+ processor is an entry-level 32-bit ARM Cortex processor designed for a
broad range of embedded applications. It offers significant benefits to developers, including:
a simple architecture that is easy to learn and program
ultra-low power, energy-efficient operation
excellent code density
deterministic, high-performance interrupt handling
upward compatibility with Cortex-M processor family
platform security robustness, with integrated Memory Protection Unit (MPU).
The Cortex-M0+ processor is built on a highly area and power optimized 32-bit processor
core, with a 2-stage pipeline Von Neumann architecture. The processor delivers exceptional
energy efficiency through a small but powerful instruction set and extensively optimized
design, providing high-end processing hardware including a single-cycle multiplier.
The Cortex-M0+ processor provides the exceptional performance expected of a modern 32bit architecture, with a higher code density than other 8-bit and 16-bit microcontrollers.
Owing to its embedded ARM core, the STM32L051x6/8 are compatible with all ARM tools
and software.
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32
Functional overview
STM32L051x6 STM32L051x8
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L051x6/8 embed a nested vectored interrupt controller able to
handle up to 32 maskable interrupt channels and 4 priority levels.
The Cortex-M0+ processor closely integrates a configurable Nested Vectored Interrupt
Controller (NVIC), to deliver industry-leading interrupt performance. The NVIC:
includes a Non-Maskable Interrupt (NMI)
provides zero jitter interrupt option
provides four interrupt priority levels
The tight integration of the processor core and NVIC provides fast execution of Interrupt
Service Routines (ISRs), dramatically reducing the interrupt latency. This is achieved
through the hardware stacking of registers, and the ability to abandon and restart loadmultiple and store-multiple operations. Interrupt handlers do not require any assembler
wrapper code, removing any code overhead from the ISRs. Tail-chaining optimization also
significantly reduces the overhead when switching from one ISR to another.
To optimize low-power designs, the NVIC integrates with the sleep modes, that include a
deep sleep function that enables the entire device to enter rapidly stop or standby mode.
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.4
Reset and supply management
3.4.1
Power supply schemes
3.4.2
VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC reset blocks, RCs
and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively.
Power supply supervisor
The devices have an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
Two versions are available:
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
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STM32L051x6 STM32L051x8
Functional overview
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note:
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The devices feature an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.4.3
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
3.5
MR is used in Run mode (nominal regulation)
LPR is used in the Low-power run, Low-power sleep and Stop modes
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32 KHz oscillator, RCC_CSR).
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
Clock prescaler
To get the best trade-off between speed and current consumption, the clock frequency
to the CPU and peripherals can be adjusted by a programmable prescaler.
Safe clock switching
Clock sources can be changed safely on the fly in Run mode through a configuration
register.
Clock management
To reduce power consumption, the clock controller can stop the clock to the core,
individual peripherals or memory.
System clock source
Three different clock sources can be used to drive the master clock SYSCLK:
–
1-25 MHz high-speed external crystal (HSE), that can supply a PLL
–
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLLMultispeed internal RC oscillator (MSI), trimmable by software, able
to generate 7 frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1
MHz, 4.2 MHz). When a 32.768 kHz clock source is available in the system (LSE),
the MSI frequency can be trimmed by software down to a ±0.5% accuracy.
Auxiliary clock source
Two ultra-low-power clock sources that can be used to drive the real-time clock:
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32
Functional overview
STM32L051x6 STM32L051x8
–
32.768 kHz low-speed external crystal (LSE)
–
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
RTC clock source
The LSI, LSE or HSE sources can be chosen to clock the RTC, whatever the system
clock.
Startup clock
After reset, the microcontroller restarts by default with an internal 2 MHz clock (MSI).
The prescaler ratio and clock source can be changed by the application program as
soon as the code execution starts.
Clock security system (CSS)
This feature can be enabled by software. If an HSE clock failure occurs, the master
clock is automatically switched to HSI and a software interrupt is generated if enabled.
Another clock security system can be enabled, in case of failure of the LSE it provides
an interrupt or wakeup event which is generated if enabled.
Clock-out capability (MCO: microcontroller clock output)
It outputs one of the internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
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STM32L051x6 STM32L051x8
Functional overview
Figure 2. Clock tree
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DocID025938 Rev 6
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32
Functional overview
3.6
STM32L051x6 STM32L051x8
Low-power real-time clock and backup registers
The real time clock (RTC) and the 5 backup registers are supplied in all modes including
standby mode. The backup registers are five 32-bit registers used to store 20 bytes of user
application data. They are not reset by a system reset, or when the device wakes up from
Standby mode.
The RTC is an independent BCD timer/counter. Its main features are the following:
Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format
Automatically correction for 28, 29 (leap year), 30, and 31 day of the month
Two programmable alarms with wake up from Stop and Standby mode capability
Periodic wakeup from Stop and Standby with programmable resolution and period
On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock.
Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.
Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy
2 anti-tamper detection pins with programmable filter. The MCU can be woken up from
Stop and Standby modes on tamper event detection.
Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be
woken up from Stop and Standby modes on timestamp event detection.
The RTC clock sources can be:
3.7
A 32.768 kHz external crystal
A resonator or oscillator
The internal low-power RC oscillator (typical frequency of 37 kHz)
The high-speed external clock
General-purpose inputs/outputs (GPIOs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated alternate function registers. All GPIOs are high current capable.
Each GPIO output, speed can be slowed (40 MHz, 10 MHz, 2 MHz, 400 kHz). The alternate
function configuration of I/Os can be locked if needed following a specific sequence in order
to avoid spurious writing to the I/O registers. The I/O controller is connected to a dedicated
IO bus with a toggling speed of up to 32 MHz.
Extended interrupt/event controller (EXTI)
The extended interrupt/event controller consists of 28 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected
to the 16 configurable interrupt/event lines. The 12 other lines are connected to PVD, RTC,
USARTs, LPUART, LPTIMER or comparator events.
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STM32L051x6 STM32L051x8
3.8
Functional overview
Memories
The STM32L051x6/8 devices have the following features:
8 Kbytes of embedded SRAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
The non-volatile memory is divided into three arrays:
–
32 or 64 Kbytes of embedded Flash program memory
–
2 Kbytes of data EEPROM
–
Information block containing 32 user and factory options bytes plus 4 Kbytes of
system memory
The user options bytes are used to write-protect or read-out protect the memory (with
4 Kbyte granularity) and/or readout-protect the whole memory with the following options:
Level 0: no protection
Level 1: memory readout protected.
The Flash memory cannot be read from or written to if either debug features are
connected or boot in RAM is selected
Level 2: chip readout protected, debug features (Cortex-M0+ serial wire) and boot in
RAM selection disabled (debugline fuse)
The firewall protects parts of code/data from access by the rest of the code that is executed
outside of the protected area. The granularity of the protected code segment or the nonvolatile data segment is 256 bytes (Flash memory or EEPROM) against 64 bytes for the
volatile data segment (RAM).
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.9
Boot modes
At startup, BOOT0 pin and nBOOT1 option bit are used to select one of three boot options:
Boot from Flash memory
Boot from System memory
Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using SPI1(PA4, PA5, PA6, PA7) or SPI2 (PB12, PB13, PB14, PB15), USART1(PA9,
PA10) or USART2(PA2, PA3). See STM32™ microcontroller system memory boot mode
AN2606 for details.
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32
Functional overview
3.10
STM32L051x6 STM32L051x8
Direct memory access (DMA)
The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, LPUART,
general-purpose timers, and ADC.
3.11
Analog-to-digital converter (ADC)
A native 12-bit, extended to 16-bit through hardware oversampling, analog-to-digital
converter is embedded into STM32L051x6/8 device. It has up to 16 external channels and 3
internal channels (temperature sensor, voltage reference). Three channels, PA0, PA4 and
PA5, are fast channels, while the others are standard channels.
The ADC performs conversions in single-shot or scan mode. In scan mode, automatic
conversion is performed on a selected group of analog inputs.
The ADC frequency is independent from the CPU frequency, allowing maximum sampling
rate of 1.14 MSPS even with a low CPU speed. The ADC consumption is low at all
frequencies (~25 µA at 10 kSPS, ~200 µA at 1MSPS). An auto-shutdown function
guarantees that the ADC is powered off except during the active conversion phase.
The ADC can be served by the DMA controller. It can operate from a supply voltage down to
1.65 V.
The ADC features a hardware oversampler up to 256 samples, this improves the resolution
to 16 bits (see AN2668).
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
3.12
Temperature sensor
The temperature sensor (TSENSE) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN18 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
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STM32L051x6 STM32L051x8
Functional overview
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
stored by ST in the system memory area, accessible in read-only mode.
Table 7. Temperature sensor calibration values
Calibration value name
3.12.1
Description
Memory address
TSENSE_CAL1
TS ADC raw data acquired at
temperature of 30 °C,
VDDA= 3 V
0x1FF8 007A - 0x1FF8 007B
TSENSE_CAL2
TS ADC raw data acquired at
temperature of 130 °C
VDDA= 3 V
0x1FF8 007E - 0x1FF8 007F
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (when no external voltage, VREF+, is available
for ADC). The precise voltage of VREFINT is individually measured for each part by ST during
production test and stored in the system memory area. It is accessible in read-only mode.
Table 8. Internal voltage reference measured values
Calibration value name
VREFINT_CAL
3.13
Description
Raw data acquired at
temperature of 25 °C
VDDA = 3 V
Memory address
0x1FF8 0078 - 0x1FF8 0079
Ultra-low-power comparators and reference voltage
The STM32L051x6/8 embed two comparators sharing the same current bias and reference
voltage. The reference voltage can be internal or external (coming from an I/O).
One comparator with ultra low consumption
One comparator with rail-to-rail inputs, fast or slow mode.
The threshold can be one of the following:
–
External I/O pins
–
Internal reference voltage (VREFINT)
–
submultiple of Internal reference voltage(1/4, 1/2, 3/4) for the rail to rail
comparator.
Both comparators can wake up the devices from Stop mode, and be combined into a
window comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
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32
Functional overview
3.14
STM32L051x6 STM32L051x8
System configuration controller
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM21, TIM22 and LPTIM timer input captures. It also controls the
routing of internal analog signals to ADC, COMP1 and COMP2 and the internal reference
voltage VREFINT.
3.15
Timers and watchdogs
The ultra-low-power STM32L051x6/8 devices include three general-purpose timers, one
low- power timer (LPTIM), one basic timer, two watchdog timers and the SysTick timer.
Table 9 compares the features of the general-purpose and basic timers.
Table 9. Timer feature comparison
Timer
Counter
resolution
Counter type
Prescaler factor
DMA
request
generation
TIM2
16-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM21,
TIM22
16-bit
Up, down,
up/down
Any integer between
1 and 65536
No
2
No
TIM6
16-bit
Up
Any integer between
1 and 65536
Yes
0
No
3.15.1
Capture/compare Complementary
channels
outputs
General-purpose timers (TIM2, TIM21 and TIM22)
There are three synchronizable general-purpose timers embedded in the STM32L051x6/8
devices (see Table 9 for differences).
TIM2
TIM2 is based on 16-bit auto-reload up/down counter. It includes a 16-bit prescaler. It
features four independent channels each for input capture/output compare, PWM or onepulse mode output.
The TIM2 general-purpose timers can work together or with the TIM21 and TIM22 generalpurpose timers via the Timer Link feature for synchronization or event chaining. Their
counter can be frozen in debug mode. Any of the general-purpose timers can be used to
generate PWM outputs.
TIM2 has independent DMA request generation.
This timer is capable of handling quadrature (incremental) encoder signals and the digital
outputs from 1 to 3 hall-effect sensors.
TIM21 and TIM22
TIM21 and TIM22 are based on a 16-bit auto-reload up/down counter. They include a 16-bit
prescaler. They have two independent channels for input capture/output compare, PWM or
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STM32L051x6 STM32L051x8
Functional overview
one-pulse mode output. They can work together and be synchronized with the TIM2, fullfeatured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
3.15.2
Low-power Timer (LPTIM)
The low-power timer has an independent clock and is running also in Stop mode if it is
clocked by LSE, LSI or an external clock. It is able to wakeup the devices from Stop mode.
This low-power timer supports the following features:
3.15.3
16-bit up counter with 16-bit autoreload register
16-bit compare register
Configurable output: pulse, PWM
Continuous / one shot mode
Selectable software / hardware input trigger
Selectable clock source
–
Internal clock source: LSE, LSI, HSI or APB clock
–
External clock source over LPTIM input (working even with no internal clock
source running, used by the Pulse Counter Application)
Programmable digital glitch filter
Encoder mode
Basic timer (TIM6)
This timer can be used as a generic 16-bit timebase.
3.15.4
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches ‘0’.
3.15.5
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
3.15.6
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
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32
Functional overview
STM32L051x6 STM32L051x8
3.16
Communication interfaces
3.16.1
I2C bus
two I2C interface (I2C1, I2C2) can operate in multimaster or slave modes.
Each I2C interface can support Standard mode (Sm, up to 100 kbit/s), Fast mode (Fm, up to
400 kbit/s) and Fast Mode Plus (Fm+, up to 1 Mbit/s) with 20 mA output drive on some I/Os.
7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with
configurable mask) are also supported as well as programmable analog and digital noise
filters.
Table 10. Comparison of I2C analog and digital filters
Analog filter
Digital filter
Pulse width of
suppressed spikes
≥ 50 ns
Programmable length from 1 to 15
I2C peripheral clocks
Benefits
Available in Stop mode
1. Extra filtering capability vs.
standard requirements.
2. Stable length
Drawbacks
Variations depending on
temperature, voltage, process
Wakeup from Stop on address
match is not available when digital
filter is enabled.
In addition, I2C1 provides hardware support for SMBus 2.0 and PMBus 1.1: ARP capability,
Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and
ALERT protocol management. I2C1 also has a clock domain independent from the CPU
clock, allowing the I2C1 to wake up the MCU from Stop mode on address match.
Each I2C interface can be served by the DMA controller.
Refer to Table 11 for an overview of I2C interface features.
Table 11. STM32L051x6/8 I2C implementation
I2C features(1)
I2C1
I2C2
7-bit addressing mode
X
X
10-bit addressing mode
X
X
Standard mode (up to 100 kbit/s)
X
X
Fast mode (up to 400 kbit/s)
X
X
Fast Mode Plus with 20 mA output drive I/Os (up to 1 Mbit/s)
X
X(2)
Independent clock
X
-
SMBus
X
-
Wakeup from STOP
X
-
1. X = supported.
2. See for the list of I/Os that feature Fast Mode Plus capability
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STM32L051x6 STM32L051x8
3.16.2
Functional overview
Universal synchronous/asynchronous receiver transmitter (USART)
The two USART interfaces (USART1, USART2) are able to communicate at speeds of up to
4 Mbit/s.
They provide hardware management of the CTS, RTS and RS485 driver enable (DE)
signals, multiprocessor communication mode, master synchronous communication and
single-wire half-duplex communication mode. They also support SmartCard communication
(ISO 7816), IrDA SIR ENDEC, LIN Master/Slave capability, auto baud rate feature and has
a clock domain independent from the CPU clock, allowing to wake up the MCU from Stop
mode using baudrates up to 42 Kbaud.
All USART interfaces can be served by the DMA controller.
Table 12 for the supported modes and features of USART interfaces.
Table 12. USART implementation
USART modes/features(1)
USART1 and USART2
Hardware flow control for modem
X
Continuous communication using DMA
X
Multiprocessor communication
X
Synchronous
mode(2)
X
Smartcard mode
X
Single-wire half-duplex communication
X
IrDA SIR ENDEC block
X
LIN mode
X
Dual clock domain and wakeup from Stop mode
X
Receiver timeout interrupt
X
Modbus communication
X
Auto baud rate detection (4 modes)
X
Driver Enable
X
1. X = supported.
2. This mode allows using the USART as an SPI master.
3.16.3
Low-power universal asynchronous receiver transmitter (LPUART)
The devices embed one Low-power UART. The LPUART supports asynchronous serial
communication with minimum power consumption. It supports half duplex single wire
communication and modem operations (CTS/RTS). It allows multiprocessor
communication.
The LPUART has a clock domain independent from the CPU clock. It can wake up the
system from Stop mode using baudrates up to 46 Kbaud. The Wakeup events from Stop
mode are programmable and can be:
Start bit detection
Or any received data frame
Or a specific programmed data frame
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32
Functional overview
STM32L051x6 STM32L051x8
Only a 32.768 kHz clock (LSE) is needed to allow LPUART communication up to 9600
baud. Therefore, even in Stop mode, the LPUART can wait for an incoming frame while
having an extremely low energy consumption. Higher speed clock can be used to reach
higher baudrates.
LPUART interface can be served by the DMA controller.
3.16.4
Serial peripheral interface (SPI)/Inter-integrated sound (I2S)
Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The USARTs with synchronous capability can also be used as SPI master.
One standard I2S interfaces (multiplexed with SPI2) is available. It can operate in master or
slave mode, and can be configured to operate with a 16-/32-bit resolution as input or output
channels. Audio sampling frequencies from 8 kHz up to 192 kHz are supported. When the
I2S interfaces is configured in master mode, the master clock can be output to the external
DAC/CODEC at 256 times the sampling frequency.
The SPIs can be served by the DMA controller.
Refer to Table 13 for the differences between SPI1 and SPI2.
Table 13. SPI/I2S implementation
SPI features(1)
SPI1
SPI2
Hardware CRC calculation
X
X
I2S mode
-
X
TI mode
X
X
1. X = supported.
3.17
Cyclic redundancy check (CRC) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a
configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at
linktime and stored at a given memory location.
3.18
Serial wire debug port (SW-DP)
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
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STM32L051x6 STM32L051x8
Pin descriptions
9''
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Figure 3. STM32L051x6/8 LQFP64 pinout - 10 x 10 mm
9''
3&
3&26&B,1
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3+26&B,1
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9''
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Pin descriptions
069
1. The above figure shows the package top view.
2. I/O supplied by VDDIO2.
DocID025938 Rev 6
33/127
45
Pin descriptions
STM32L051x6 STM32L051x8
Figure 4. STM32L051x6/8 TFBGA64 ballout - 5x 5 mm
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1. The above figure shows the package top view.
2. I/O supplied by VDDIO2.
34/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Pin descriptions
9''
966 3%
3%
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Figure 5. STM32L051x6/8 LQFP48 pinout - 7 x 7 mm
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9''$
3$
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1. The above figure shows the package top view.
2. I/O supplied by VDDIO2.
Figure 6. STM32L051x6/8 WLCSP36 ballout
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3%
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9''
3&
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1. The above figure shows the package top view.
DocID025938 Rev 6
35/127
45
Pin descriptions
STM32L051x6 STM32L051x8
9''
3&26&B,1
3&26&B287
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1. The above figure shows the package top view.
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STM32L051x6 STM32L051x8
Pin descriptions
Table 14. Legend/abbreviations used in the pinout table
Name
Abbreviation
Unless otherwise specified in brackets below the pin name, the pin function during
and after reset is the same as the actual pin name
Pin name
Pin type
I/O structure
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
FTf
5 V tolerant I/O, FM+ capable
TC
Standard 3.3V I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Unless otherwise specified by a note, all I/Os are set as floating inputs during and
after reset.
Notes
Pin functions
Definition
Alternate
functions
Functions selected through GPIOx_AFR registers
Additional
functions
Functions directly selected/enabled through peripheral registers
Table 15. STM32L051x6/8 pin definitions
WLCSP36(1)
LQFP32
UFQFPN32
B2
1
-
-
-
VDD
S
-
Notes
LQFP48
1
I/O structure
TFBGA64
Pin name
(function
after reset)
Pin type
LQFP64
Pin Number
Alternate functions
Additional
functions
-
-
-
2
A2
2
-
-
-
PC13
I/O
FT
-
-
RTC_TAMP1/
RTC_TS/
RTC_OUT/
WKUP2
3
A1
3
A6
2
2
PC14OSC32_IN
(PC14)
I/O
FT
-
-
OSC32_IN
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45
Pin descriptions
STM32L051x6 STM32L051x8
Table 15. STM32L051x6/8 pin definitions (continued)
LQFP64
TFBGA64
LQFP48
WLCSP36(1)
LQFP32
UFQFPN32
Pin type
I/O structure
Notes
Pin Number
Alternate functions
4
B1
4
B6
3
3
PC15OSC32_OUT
(PC15)
I/O
TC
-
-
OSC32_OUT
5
C1
5
-
-
-
PH0-OSC_IN
(PH0)
I/O
TC
-
-
OSC_IN
6
D1
6
-
-
-
PH1OSC_OUT
(PH1)
I/O
TC
-
-
OSC_OUT
7
E1
7
C6
4
4
NRST
I/O
RST
-
-
-
8
E3
-
-
-
-
PC0
I/O
FT
-
LPTIM1_IN1,
EVENTOUT
ADC_IN10
9
E2
-
-
-
-
PC1
I/O
FT
-
LPTIM1_OUT,
EVENTOUT
ADC_IN11
10
F2
-
-
-
-
PC2
I/O
FT
-
LPTIM1_IN2,
SPI2_MISO/I2S2_M
CK
ADC_IN12
11
-
-
-
-
-
PC3
I/O
FT
-
LPTIM1_ETR,
SPI2_MOSI/I2S2_SD
ADC_IN13
12
F1
8
-
-
-
VSSA
S
-
-
-
-
G1
-
E6
-
-
VREF+
S
-
-
-
13
H1
9
D5
5
5
VDDA
S
-
-
-
-
TIM2_CH1,
USART2_CTS,
TIM2_ETR,
COMP1_OUT
COMP1_INM6,
ADC_IN0,
RTC_TAMP2/WKU
P1
-
EVENTOUT,
TIM2_CH2,
USART2_RTS_DE,
TIM21_ETR
COMP1_INP,
ADC_IN1
-
TIM21_CH1,
TIM2_CH3,
USART2_TX,
COMP2_OUT
COMP2_INM6,
ADC_IN2
14
15
16
38/127
G2
H2
F3
10
11
12
D4
F6
E5
6
7
8
6
7
8
Pin name
(function
after reset)
PA0
PA1
PA2
I/O
I/O
I/O
TC
FT
FT
DocID025938 Rev 6
Additional
functions
STM32L051x6 STM32L051x8
Pin descriptions
Table 15. STM32L051x6/8 pin definitions (continued)
LQFP64
TFBGA64
LQFP48
WLCSP36(1)
LQFP32
UFQFPN32
Pin name
(function
after reset)
Pin type
I/O structure
Notes
Pin Number
Alternate functions
17
G3
13
F5
9
9
PA3
I/O
FT
-
TIM21_CH2,
TIM2_CH4,
USART2_RX
18
C2
-
-
-
-
VSS
S
-
-
-
19
D2
-
-
-
-
VDD
S
-
-
-
20
H3
14
E4
10
10
PA4
I/O
TC
(2)
SPI1_NSS,
USART2_CK,
TIM22_ETR
COMP1_INM4,
COMP2_INM4,
ADC_IN4
21
F4
15
F4
11
11
PA5
I/O
TC
-
SPI1_SCK,
TIM2_ETR,
TIM2_CH1
COMP1_INM5,
COMP2_INM5,
ADC_IN5
-
SPI1_MISO,
LPUART1_CTS,
TIM22_CH1,
EVENTOUT,
COMP1_OUT
ADC_IN6
ADC_IN7
22
G4
16
E3
12
12
PA6
I/O
FT
Additional
functions
COMP2_INP,
ADC_IN3
23
H4
17
F3
13
13
PA7
I/O
FT
-
SPI1_MOSI,
TIM22_CH2,
EVENTOUT,
COMP2_OUT
24
H5
-
-
-
-
PC4
I/O
FT
-
EVENTOUT,
LPUART1_TX
ADC_IN14
25
H6
-
-
-
-
PC5
I/O
FT
-
LPUART1_RX,
ADC_IN15
26
F5
18
D3
14
14
PB0
I/O
FT
-
EVENTOUT
ADC_IN8,
VREF_OUT
27
G5
19
C3
15
15
PB1
I/O
FT
-
LPUART1_RTS_DE
ADC_IN9,
VREF_OUT
28
G6
20
F2
-
16
PB2
I/O
FT
-
LPTIM1_OUT
-
-
TIM2_CH3,
LPUART1_TX,
SPI2_SCK,
I2C2_SCL
-
29
G7
21
E2
-
-
PB10
I/O
FT
DocID025938 Rev 6
39/127
45
Pin descriptions
STM32L051x6 STM32L051x8
Table 15. STM32L051x6/8 pin definitions (continued)
22
D2
-
-
PB11
I/O
FT
-
31
D6
23
-
16
-
VSS
S
-
-
-
-
32
E6
24
F1
17
17
VDD
S
-
-
-
-
33
H8
25
-
-
-
PB12
I/O
FT
-
SPI2_NSS/I2S2_WS,
LPUART1_RTS_DE,
EVENTOUT
-
-
SPI2_SCK/I2S2_CK,
LPUART1_CTS,
I2C2_SCL,
TIM21_CH1
-
-
34
G8
26
-
LQFP32
H7
LQFP48
30
EVENTOUT,
TIM2_CH4,
LPUART1_RX,
I2C2_SDA
TFBGA64
Alternate functions
LQFP64
Notes
I/O structure
Pin name
(function
after reset)
Pin type
UFQFPN32
WLCSP36(1)
Pin Number
-
-
PB13
I/O
FTf
Additional
functions
-
35
F8
27
-
-
-
PB14
I/O
FTf
-
SPI2_MISO/I
2S2_MCK,
RTC_OUT,
LPUART1_RTS_DE,
I2C2_SDA,
TIM21_CH2
36
F7
28
-
-
-
PB15
I/O
FT
-
SPI2_MOSI/I2S2_SD
, RTC_REFIN
-
37
F6
-
-
-
-
PC6
I/O
FT
-
TIM22_CH1
-
38
E7
-
-
-
-
PC7
I/O
FT
-
TIM22_CH2
-
39
E8
-
-
-
-
PC8
I/O
FT
-
TIM22_ETR
-
40
D8
-
-
-
-
PC9
I/O
FT
-
TIM21_ETR
-
41
D7
29
E1
18
18
PA8
I/O
FT
-
MCO, EVENTOUT,
USART1_CK
-
42
C7
30
D1
19
19
PA9
I/O
FT
-
MCO, USART1_TX
-
43
C6
31
C1
20
20
PA10
I/O
FT
-
USART1_RX
-
-
SPI1_MISO,
EVENTOUT,
USART1_CTS,
COMP1_OUT
-
44
40/127
C8
32
C2
21
21
PA11
I/O
FT
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Pin descriptions
Table 15. STM32L051x6/8 pin definitions (continued)
33
B1
22
22
PA12
I/O
FT
-
46
A8
34
A1
23
23
PA13
I/O
FT
-
SWDIO
-
47
D5
35
-
-
-
VSS
S
-
-
-
48
E5
36
-
-
-
VDDIO2
S
-
-
-
49
A7
37
B2
24
24
PA14
I/O
-
SWCLK,
USART2_TX
-
LQFP32
B8
LQFP48
45
SPI1_MOSI,
EVENTOUT,
USART1_RTS_DE,
COMP2_OUT
TFBGA64
Alternate functions
LQFP64
Notes
I/O structure
Pin name
(function
after reset)
Pin type
UFQFPN32
WLCSP36(1)
Pin Number
FT
Additional
functions
-
50
A6
38
A2
25
25
PA15
I/O
FT
-
SPI1_NSS,
TIM2_ETR,
EVENTOUT,
USART2_RX,
TIM2_CH1
51
B7
-
-
-
-
PC10
I/O
FT
-
LPUART1_TX
-
52
B6
-
-
-
-
PC11
I/O
FT
-
LPUART1_RX
-
53
C5
-
-
-
-
PC12
I/O
FT
-
-
-
54
B5
-
-
-
-
PD2
I/O
FT
-
LPUART1_RTS_DE
-
55
A5
39
B3
26
26
PB3
I/O
FT
-
SPI1_SCK,
TIM2_CH2,
EVENTOUT
COMP2_INN
56
A4
40
A3
27
27
PB4
I/O
FT
-
SPI1_MISO,
EVENTOUT,
TIM22_CH1
COMP2_INP
COMP2_INP
57
C4
41
C4
28
28
PB5
I/O
FT
-
SPI1_MOSI,
LPTIM1_IN1,
I2C1_SMBA,
TIM22_CH2
58
D3
42
B4
29
29
PB6
I/O
FTf
-
USART1_TX,
I2C1_SCL,
LPTIM1_ETR
COMP2_INP
59
C3
43
A4
30
30
PB7
I/O
FTf
-
USART1_RX,
I2C1_SDA,
LPTIM1_IN2
COMP2_INP,
PVD_IN
DocID025938 Rev 6
41/127
45
Pin descriptions
STM32L051x6 STM32L051x8
Table 15. STM32L051x6/8 pin definitions (continued)
LQFP48
WLCSP36(1)
LQFP32
UFQFPN32
Pin name
(function
after reset)
60
B4
44
C5
31
31
BOOT0
B
61
B3
45
B5
-
32
PB8
I/O
FTf
-
I2C1_SCL
-
62
A3
46
-
-
-
PB9
I/O
FTf
-
EVENTOUT,
I2C1_SDA,
SPI2_NSS/I2S2_WS
-
63
D4
47
D6
32
-
VSS
S
-
-
-
-
64
E4
48
A5
1
1
VDD
S
-
-
-
-
Notes
TFBGA64
I/O structure
LQFP64
Pin type
Pin Number
Alternate functions
Additional
functions
-
-
-
1. PB9/12/13/14/15, PH0/1 and PC13 GPIOs should be configured as output and driven Low, even if they are not available on
this package.
2. PA4 offers a reduced touch sensing sensitivity. It is thus recommended to use it as sampling capacitor I/O.
42/127
DocID025938 Rev 6
AF0
AF1
AF2
AF3
AF4
AF5
AF6
AF7
SPI1/TIM21/SYS_A
F/EVENTOUT/
-
TIM2/
EVENTOUT/
EVENTOUT
USART1/2/3
TIM2/21/22
EVENTOUT
COMP1/2
PA0
-
-
TIM2_CH1
-
USART2_CTS
TIM2_ETR
-
COMP1_OUT
PA1
EVENTOUT
-
TIM2_CH2
-
USART2_RTS_
DE
TIM21_ETR
-
-
PA2
TIM21_CH1
-
TIM2_CH3
-
USART2_TX
-
-
COMP2_OUT
PA3
TIM21_CH2
-
TIM2_CH4
-
USART2_RX
-
-
-
PA4
SPI1_NSS
-
-
-
USART2_CK
TIM22_ETR
-
-
PA5
SPI1_SCK
-
TIM2_ETR
-
-
TIM2_CH1
-
-
PA6
SPI1_MISO
-
-
-
LPUART1_CTS
TIM22_CH1
EVENTOUT
COMP1_OUT
PA7
SPI1_MOSI
-
-
-
-
TIM22_CH2
EVENTOUT
COMP2_OUT
PA8
MCO
-
-
EVENTOUT
USART1_CK
-
-
-
PA9
MCO
-
-
-
USART1_TX
-
-
-
PA10
-
-
-
-
USART1_RX
-
-
-
PA11
SPI1_MISO
-
EVENTOUT
-
USART1_CTS
-
-
COMP1_OUT
PA12
SPI1_MOSI
-
EVENTOUT
-
USART1_RTS_
DE
-
-
COMP2_OUT
PA13
SWDIO
-
-
-
-
-
-
-
PA14
SWCLK
-
-
-
USART2_TX
-
-
-
PA15
SPI1_NSS
-
TIM2_ETR
EVENTOUT
USART2_RX
TIM2_CH1
-
-
Port
DocID025938 Rev 6
Port A
STM32L051x6 STM32L051x8
Table 16. Alternate function port A
Pin descriptions
43/127
AF1
AF2
AF3
AF4
AF5
AF6
SPI1/SPI2/I2S2/
USART1/
EVENTOUT/
I2C1
LPUART1/LPTIM
/TIM2/SYS_AF/
EVENTOUT
I2C1
I2C1/TIM22/
EVENTOUT/
LPUART1
SPI2/I2S2/I2C2
I2C2/TIM21/
EVENTOUT
PB0
EVENTOUT
-
-
-
-
-
-
PB1
-
-
-
-
LPUART1_RTS_
DE
-
-
PB2
-
-
LPTIM1_OUT
-
-
-
-
PB3
SPI1_SCK
-
TIM2_CH2
-
EVENTOUT
-
-
PB4
SPI1_MISO
-
EVENTOUT
-
TIM22_CH1
-
-
PB5
SPI1_MOSI
-
LPTIM1_IN1
I2C1_SMBA
TIM22_CH2
-
-
PB6
USART1_TX
I2C1_SCL
LPTIM1_ETR
-
-
-
-
PB7
USART1_RX
I2C1_SDA
LPTIM1_IN2
-
-
-
-
PB8
-
-
-
-
I2C1_SCL
-
-
PB9
-
-
EVENTOUT
-
I2C1_SDA
SPI2_NSS/I2S2_
WS
-
PB10
-
-
TIM2_CH3
-
LPUART1_TX
SPI2_SCK
I2C2_SCL
PB11
EVENTOUT
-
TIM2_CH4
-
LPUART1_RX
-
I2C2_SDA
PB12
SPI2_NSS/I2S2_WS
-
LPUART1_RTS_
DE
-
-
-
EVENTOUT
PB13
SPI2_SCK/I2S2_CK
-
-
-
LPUART1_CTS
I2C2_SCL
TIM21_CH1
PB14
SPI2_MISO/I2S2_MCK
-
RTC_OUT
-
LPUART1_RTS_
DE
I2C2_SDA
TIM21_CH2
PB15
SPI2_MOSI/I2S2_SD
-
RTC_REFIN
-
-
-
Port
DocID025938 Rev 6
Port B
STM32L051x6 STM32L051x8
AF0
Pin descriptions
44/127
Table 17. Alternate function port B
AF0
AF1
AF2
LPUART1/LPTIM/TIM21/12/EVENTOUT
-
SPI2/I2S2/LPUART1/EVENTOUT
PC0
LPTIM1_IN1
-
EVENTOUT
PC1
LPTIM1_OUT
-
EVENTOUT
PC2
LPTIM1_IN2
-
SPI2_MISO/I2S2_MCK
PC3
LPTIM1_ETR
-
SPI2_MOSI/I2S2_SD
PC4
EVENTOUT
-
LPUART1_TX
-
LPUART1_RX
Port
PC5
DocID025938 Rev 6
Port C
PC6
TIM22_CH1
-
-
PC7
TIM22_CH2
-
-
PC8
TIM22_ETR
-
-
PC9
TIM21_ETR
-
-
PC10
LPUART1_TX
-
-
PC11
LPUART1_RX
-
-
PC12
-
-
-
PC13
-
-
-
PC14
-
-
-
PC15
-
-
-
STM32L051x6 STM32L051x8
Table 18. Alternate function port C
Table 19. Alternate function port D
AF1
LPUART1
-
Port D
PD2
LPUART1_RTS_DE
-
45/127
Pin descriptions
AF0
Port
Memory mapping
5
STM32L051x6 STM32L051x8
Memory mapping
Figure 9. Memory map
[))))))))
[(
[(
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SHULSKHUDOV
)/0/24
[
RESERVED
[&
[))
!("
[
RESERVED
[$
[
[)))))))
2SWLRQE\WHV
!0"
[
[
6\VWHP
PHPRU\
!0"
[
[
RESERVED
[
3HULSKHUDOV
[
RESERVED
[
)ODVKV\VWHP
PHPRU\
65$0
[
RESERVED
&2'(
[
[
&LASHSYSTEM
MEMORYOR
32!-
DEMENDINGON
"//4
CONFIGURATION
5HVHUYHG
069
46/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V VDD 3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 10. Pin loading conditions
Figure 11. Pin input voltage
0&8SLQ
0&8SLQ
& S)
9,1
DLF
DocID025938 Rev 6
DLF
47/127
100
Electrical characteristics
6.1.6
STM32L051x6 STM32L051x8
Power supply scheme
Figure 12. Power supply scheme
287
*3,2V
,1
/HYHOVKLIWHU
6WDQGE\SRZHUFLUFXLWU\
26&57&:DNHXS
ORJLF57&EDFNXS
UHJLVWHUV
,2
/RJLF
.HUQHOORJLF
&38
'LJLWDO
0HPRULHV
9''
9''
5HJXODWRU
1îQ)
î)
966
9''$
9''$
95()
Q)
)
Q)
)
95()
95()
$'&
$QDORJ
5&3//&203
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966$
06Y9
6.1.7
Current consumption measurement
Figure 13. Current consumption measurement scheme
9''$
,''
1[9''
1îQ)
î)
1[966
06Y9
48/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
6.2
Electrical characteristics
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 20: Voltage characteristics,
Table 21: Current characteristics, and Table 22: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 20. Voltage characteristics
Symbol
VDD–VSS
VIN(2)
Definition
Min
Max
External main supply voltage
(including VDDA, VDDIO2, VDD)(1)
–0.3
4.0
Input voltage on FT and FTf pins
VSS 0.3
VDD+4.0
Input voltage on TC pins
VSS 0.3
4.0
Input voltage on BOOT0
VSS
VDD 4.0
VSS 0.3
4.0
Input voltage on any other pin
|VDD|
Variations between different VDDx power pins
-
50
|VDDA-VDDx|
Variations between any VDDx and VDDA power
pins(3)
-
300
Variations between all different ground pins
-
50
-
0.4
|VSS|
VREF+ –VDDA Allowed voltage difference for VREF+ > VDDA
VESD(HBM)
Electrostatic discharge voltage
(human body model)
Unit
V
mV
V
see Section 6.3.11
1. All main power (VDD,VDDIO2, VDDA) and ground (VSS, VSSA) pins must always be connected to the external
power supply, in the permitted range.
2.
VIN maximum must always be respected. Refer to Table 21 for maximum allowed injected current values.
3. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV
between VDD and VDDA can be tolerated during power-up and device operation. VDDIO2 is independent
from VDD and VDDA: its value does not need to respect this rule.
DocID025938 Rev 6
49/127
100
Electrical characteristics
STM32L051x6 STM32L051x8
Table 21. Current characteristics
Symbol
Ratings
Max.
ΣIVDD(2)
Total current into sum of all VDD power lines (source)(1)
105
ΣIVSS(2)
(1)
Total current out of sum of all VSS ground lines (sink)
105
ΣIVDDIO2
Total current into VDDIO2 power line (source)
25
IVDD(PIN)
Maximum current into each VDD power pin (source)(1)
IVSS(PIN)
IIO
ΣIIO(PIN)
IINJ(PIN)
ΣIINJ(PIN)
100
(1)
Maximum current out of each VSS ground pin (sink)
100
Output current sunk by any I/O and control pin except FTf
pins
16
Output current sunk by FTf pins
22
Output current sourced by any I/O and control pin
-16
Total output current sunk by sum of all IOs and control pins
except PA11 and PA12(2)
90
Total output current sunk by PA11 and PA12
25
Total output current sourced by sum of all IOs and control
pins(2)
-90
Injected current on FT, FFf, RST and B pins
Unit
mA
-5/+0(3)
Injected current on TC pin
± 5(4)
Total injected current (sum of all I/O and control pins)(5)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power
supply, in the permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output
current must not be sunk/sourced between two consecutive power supply pins referring to high pin count
LQFP packages.
3. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN)
must never be exceeded. Refer to Table 20 for maximum allowed input voltage values.
4. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN)
must never be exceeded. Refer to Table 20: Voltage characteristics for the maximum allowed input voltage
values.
5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
Table 22. Thermal characteristics
Symbol
TSTG
TJ
50/127
Ratings
Storage temperature range
Maximum junction temperature
DocID025938 Rev 6
Value
Unit
–65 to +150
°C
150
°C
STM32L051x6 STM32L051x8
Electrical characteristics
6.3
Operating conditions
6.3.1
General operating conditions
Table 23. General operating conditions
Symbol
Parameter
Conditions
Min
Max
Unit
fHCLK
Internal AHB clock frequency
-
0
32
fPCLK1
Internal APB1 clock frequency
-
0
32
fPCLK2
Internal APB2 clock frequency
-
0
32
BOR detector disabled
1.65
3.6
BOR detector enabled, at power
on
1.8
3.6
BOR detector disabled, after
power on
1.65
3.6
Must be the same voltage as
VDD(1)
1.65
3.6
V
1.65
3.6
V
2.0 V VDD 3.6 V
-0.3
5.5
1.65 V VDD 2.0 V
-0.3
5.2
VDD
VDDA
VDDIO2
Standard operating voltage
Analog operating voltage (all features)
Standard operating voltage
-
Input voltage on FT, FTf and RST pins(2)
VIN
Input voltage on BOOT0 pin
-
0
5.5
Input voltage on TC pin
-
-0.3
VDD+0.3
TFBGA64 package
-
327
LQFP64 package
-
444
-
363
-
318
LQFP32 package
-
351
UFQFPN32
-
526
TFBGA64 package
-
81
LQFP64 package
-
111
LQFP48 package
-
91
WLCSP36 package
-
79
LQFP32 package
-
88
UFQFPN32
-
132
Power dissipation at TA = 85 °C (range 6) LQFP48 package
or TA =105 °C (rage 7) (3)
WLCSP36 package
PD
Power dissipation at TA = 125 °C (range
3) (3)
DocID025938 Rev 6
MHz
V
V
mW
51/127
100
Electrical characteristics
STM32L051x6 STM32L051x8
Table 23. General operating conditions (continued)
Symbol
TA
TJ
Parameter
Conditions
Min
Max
Maximum power dissipation
(range 6)
–40
85
Maximum power dissipation
(range 7)
–40
105
Maximum power dissipation
(range 3)
–40
125
Junction temperature range (range 6)
-40 °C TA 85 °
–40
105
Junction temperature range (range 7)
-40 °C TA 105 °C
–40
125
Junction temperature range (range 3)
-40 °C TA 125 °C
–40
130
Temperature range
Unit
°C
1. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up and normal operation.
2. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
3. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 22: Thermal characteristics
on page 50).
52/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
6.3.2
Electrical characteristics
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
ambient temperature condition summarized in Table 23.
Table 24. Embedded reset and power control block characteristics
Symbol
Parameter
Conditions
VDD rise time rate
tVDD(1)
VDD fall time rate
TRSTTEMPO(1) Reset temporization
Min
Typ
Max
BOR detector enabled
0
-
BOR detector disabled
0
-
1000
BOR detector enabled
20
-
BOR detector disabled
0
-
1000
VDD rising, BOR enabled
-
2
3.3
0.4
0.7
1.6
Falling edge
1
1.5
1.65
Rising edge
1.3
1.5
1.65
Falling edge
1.67
1.7
1.74
Rising edge
1.69
1.76
1.8
Falling edge
1.87
1.93
1.97
Rising edge
1.96
2.03
2.07
Falling edge
2.22
2.30
2.35
Rising edge
2.31
2.41
2.44
Falling edge
2.45
2.55
2.6
Rising edge
2.54
2.66
2.7
Falling edge
2.68
2.8
2.85
Rising edge
2.78
2.9
2.95
Falling edge
1.8
1.85
1.88
Rising edge
1.88
1.94
1.99
Falling edge
1.98
2.04
2.09
Rising edge
2.08
2.14
2.18
Falling edge
2.20
2.24
2.28
Rising edge
2.28
2.34
2.38
Falling edge
2.39
2.44
2.48
Rising edge
2.47
2.54
2.58
Falling edge
2.57
2.64
2.69
Rising edge
2.68
2.74
2.79
Falling edge
2.77
2.83
2.88
Rising edge
2.87
2.94
2.99
VDD rising, BOR
VPOR/PDR
Power on/power down reset
threshold
VBOR0
Brown-out reset threshold 0
VBOR1
Brown-out reset threshold 1
VBOR2
Brown-out reset threshold 2
VBOR3
Brown-out reset threshold 3
VBOR4
Brown-out reset threshold 4
VPVD0
Programmable voltage detector
threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
DocID025938 Rev 6
disabled(2)
Unit
µs/V
ms
V
53/127
100
Electrical characteristics
STM32L051x6 STM32L051x8
Table 24. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
VPVD6
Conditions
PVD threshold 6
Hysteresis voltage
Vhyst
Min
Typ
Max
Falling edge
2.97
3.05
3.09
Rising edge
3.08
3.15
3.20
BOR0 threshold
-
40
-
All BOR and PVD thresholds
excepting BOR0
-
100
-
Unit
V
mV
1. Guaranteed by characterization results.
2. Valid for device version without BOR at power up. Please see option "D" in Ordering information scheme for more details.
6.3.3
Embedded internal reference voltage
The parameters given in Table 26 are based on characterization results, unless otherwise
specified.
Table 25. Embedded internal reference voltage calibration values
Calibration value name
Description
Memory address
Raw data acquired at
temperature of 25 °C
VDDA= 3 V
VREFINT_CAL
0x1FF8 0078 - 0x1FF8 0079
Table 26. Embedded internal reference voltage(1)
Symbol
Parameter
VREFINT out(2)
Internal reference voltage
Conditions
Min
Typ
Max
Unit
– 40 °C < TJ < +125 °C
1.202
1.224
1.242
V
TVREFINT
Internal reference startup time
-
-
2
3
ms
VVREF_MEAS
VDDA and VREF+ voltage during
VREFINT factory measure
-
2.99
3
3.01
V
AVREF_MEAS
Accuracy of factory-measured
VREFINT value(3)
Including uncertainties
due to ADC and
VDDA/VREF+ values
-
-
±5
mV
TCoeff(4)
Temperature coefficient
–40 °C < TJ < +125 °C
-
25
100
ppm/°C
ACoeff(4)
Long-term stability
1000 hours, T= 25 °C
-
-
1000
ppm
VDDCoeff(4)
Voltage coefficient
3.0 V < VDDA < 3.6 V
-
-
2000
ppm/V
TS_vrefint(4)(5)
ADC sampling time when
reading the internal reference
voltage
-
5
10
-
µs
TADC_BUF(4)
Startup time of reference
voltage buffer for ADC
-
-
-
10
µs
IBUF_ADC(4)
Consumption of reference
voltage buffer for ADC
-
-
13.5
25
µA
IVREF_OUT(4)
VREF_OUT output current(6)
-
-
-
1
µA
VREF_OUT output load
-
-
-
50
pF
CVREF_OUT
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(4)
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
Table 26. Embedded internal reference voltage(1) (continued)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Consumption of reference
voltage buffer for VREF_OUT
and COMP
-
-
730
1200
nA
VREFINT_DIV1(4)
1/4 reference voltage
-
24
25
26
VREFINT_DIV2(4)
1/2 reference voltage
-
49
50
51
VREFINT_DIV3(4)
3/4 reference voltage
-
74
75
76
ILPBUF(4)
%
VREFINT
1. Refer to Table 38: Peripheral current consumption in Stop and Standby mode for the value of the internal reference current
consumption (IREFINT).
2. Guaranteed by test in production.
3. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
4. Guaranteed by design.
5. Shortest sampling time can be determined in the application by multiple iterations.
6. To guarantee less than 1% VREF_OUT deviation.
6.3.4
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to Dhrystone 2.1 code if not specified
otherwise.
The current consumption values are derived from the tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 23: General operating
conditions unless otherwise specified.
The MCU is placed under the following conditions:
All I/O pins are configured in analog input mode
All peripherals are disabled except when explicitly mentioned
The Flash memory access time and prefetch is adjusted depending on fHCLK
frequency and voltage range to provide the best CPU performance unless otherwise
specified.
When the peripherals are enabled fAPB1 = fAPB2 = fAPB
When PLL is on, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used)
The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 40: High-speed external user clock characteristics
For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins
For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise
The parameters given in Table 47, Table 23 and Table 24 are derived from tests performed
under ambient temperature and VDD supply voltage conditions summarized in Table 23.
DocID025938 Rev 6
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100
Electrical characteristics
STM32L051x6 STM32L051x8
Table 27. Current consumption in Run mode, code with data processing running from Flash
Symbol
Parameter
fHCLK
Typ
Max(1)
1 MHz
165
230
2 MHz
290
360
4 MHz
555
630
4 MHz
0.665
0.74
8 MHz
1.3
1.4
16 MHz
2.6
2.8
8 MHz
1.55
1.7
16 MHz
3.1
3.4
32 MHz
6.3
6.8
65 kHz
36.5
110
524 kHz
99.5
190
4.2 MHz
620
700
Range 2, VCORE=1.5 V,
VOS[1:0]=10,
16 MHz
2.6
2.9
Range 1, VCORE=1.8 V,
VOS[1:0]=01
32 MHz
6.25
7
Conditions
Range 3, VCORE=1.2 V
VOS[1:0]=11
IDD
(Run
from
Flash)
fHSE = fHCLK up to
16 MHz included,
Range 2, VCORE=1.5 V,
fHSE = fHCLK/2 above VOS[1:0]=10,
16 MHz (PLL on)(2)
Supply
current in
Run mode,
code
executed
from Flash
Range 1, VCORE=1.8 V,
VOS[1:0]=01
Range 3, VCORE=1.2 V,
VOS[1:0]=11
MSI clock
HSI clock
Unit
µA
mA
µA
mA
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Table 28. Current consumption in Run mode vs code type,
code with data processing running from Flash
Symbol
IDD
(Run
from
Flash)
Parameter
Supply
current in
Run mode,
code
executed
from Flash
Conditions
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2 above
16 MHz (PLL on)(1)
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
56/127
DocID025938 Rev 6
fHCLK
Typ
Dhrystone
555
CoreMark
585
Fibonacci
4 MHz
440
while(1)
355
while(1), prefetch
off
353
Dhrystone
6.3
CoreMark
6.3
Fibonacci
32 MHz
6.55
while(1)
5.4
while(1), prefetch
off
5.2
Unit
µA
mA
STM32L051x6 STM32L051x8
Electrical characteristics
Figure 14. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSE, 1WS
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Figure 15. IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code running from
Flash memory, Range 2, HSI16, 1WS
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DocID025938 Rev 6
57/127
100
Electrical characteristics
STM32L051x6 STM32L051x8
Table 29. Current consumption in Run mode, code with data processing running from RAM
Symbol
Parameter
fHCLK
Typ
Max(1)
1 MHz
135
170
2 MHz
240
270
4 MHz
450
480
4 MHz
0.52
0.6
8 MHz
1
1.2
16 MHz
2
2.3
8 MHz
1.25
1.4
16 MHz
2.45
2.8
32 MHz
5.1
5.4
65 kHz
34.5
75
524 kHz
83
120
4.2 MHz
485
540
Range 2,
VCORE=1.5 V,
VOS[1:0]=10
16 MHz
2.1
2.3
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
32 MHz
Conditions
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
fHSE = fHCLK up to 16
Range 2,
MHz included,
VCORE=1.5 ,V,
fHSE = fHCLK/2 above
VOS[1:0]=10
16 MHz (PLL on)(2)
IDD (Run
from
RAM)
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
Supply current in
Run mode, code
executed from
RAM, Flash
switched off
MSI clock
HSI16 clock source
(16 MHz)
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
Unit
µA
mA
µA
mA
5.1
5.6
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Table 30. Current consumption in Run mode vs code type,
code with data processing running from RAM(1)
Symbol
Parameter
Conditions
fHCLK
Dhrystone
IDD (Run
from
RAM)
Supply current in
Run mode, code
executed from
RAM, Flash
switched off
fHSE = fHCLK up to
16 MHz included,
fHSE = fHCLK/2 above
16 MHz (PLL on)(2)
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
CoreMark
Fibonacci
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
58/127
DocID025938 Rev 6
4 MHz
575
370
340
Dhrystone
5.1
CoreMark
Fibonacci
Unit
450
while(1)
while(1)
1. Guaranteed by characterization results, unless otherwise specified.
Typ
32 MHz
6.25
4.4
4.7
µA
mA
STM32L051x6 STM32L051x8
Electrical characteristics
Table 31. Current consumption in Sleep mode
Symbol
Parameter
fHCLK
Typ
Max(1)
1 MHz
43.5
90
2 MHz
72
120
4 MHz
130
180
4 MHz
160
210
8 MHz
305
370
16 MHz
590
710
8 MHz
370
430
16 MHz
715
860
32 MHz
1650
1900
65 kHz
18
65
524 kHz
31.5
75
4.2 MHz
140
210
Range 2,
VCORE=1.5 V,
VOS[1:0]=10
16 MHz
665
830
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
32 MHz
1750
2100
1 MHz
57.5
130
2 MHz
84
170
4 MHz
150
280
4 MHz
170
310
8 MHz
315
420
16 MHz
605
770
8 MHz
380
460
16 MHz
730
950
32 MHz
1650
2400
65 kHz
29.5
110
524 kHz
44.5
130
4.2 MHz
150
270
Range 2,
VCORE=1.5 V,
VOS[1:0]=10
16 MHz
680
950
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
32 MHz
1750
2100
Conditions
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
fHSE = fHCLK up to
Range 2,
16 MHz included,
VCORE=1.5 V,
fHSE = fHCLK/2 above
VOS[1:0]=10
16 MHz (PLL on)(2)
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
Supply current
in Sleep
mode, Flash
off
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
MSI clock
HSI16 clock source
(16 MHz)
IDD (Sleep)
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
fHSE = fHCLK up to
Range 2,
16 MHz included,
=1.5 V,
CORE
fHSE = fHCLK/2 above
VOS[1:0]=10
(2)
16 MHz (PLL on)
Range 1,
VCORE=1.8 V,
VOS[1:0]=01
Supply current
in Sleep
mode, Flash
on
Range 3,
VCORE=1.2 V,
VOS[1:0]=11
MSI clock
HSI16 clock source
(16 MHz)
Unit
µA
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
DocID025938 Rev 6
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Electrical characteristics
STM32L051x6 STM32L051x8
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
Table 32. Current consumption in Low-power run mode
Symbol
Parameter
Typ
Max(1)
TA = − 40 to 25°C
8.5
10
TA = 85 °C
11.5
48
TA = 105 °C
15.5
53
TA = 125 °C
27.5
130
TA =-40 °C to 25 °C
10
15
TA = 85 °C
15.5
50
TA = 105 °C
19.5
54
TA = 125 °C
31.5
130
TA = − 40 to 25°C
20
25
TA = 55 °C
23
50
TA = 85 °C
25.5
55
TA = 105 °C
29.5
64
TA = 125 °C
40
140
TA = − 40 to 25°C
22
28
TA = 85 °C
26
68
TA = 105 °C
31
75
TA = 125 °C
44
95
TA = − 40 to 25°C
27.5
33
TA = 85 °C
31.5
73
TA = 105 °C
36.5
80
TA = 125 °C
49
100
TA = − 40 to 25°C
39
46
TA = 55 °C
41
80
TA = 85 °C
44
86
TA = 105 °C
49.5
100
TA = 125 °C
60
120
Conditions
MSI clock = 65 kHz,
fHCLK = 32 kHz
All peripherals
off, code
executed from
RAM, Flash
switched off,
VDD from 1.65
to 3.6 V
MSI clock= 65 kHz,
fHCLK = 65 kHz
MSI clock= 131 kHz,
fHCLK = 131 kHz
IDD
(LP Run)
Supply
current in
Low-power
run mode
MSI clock= 65 kHz,
fHCLK = 32 kHz
All peripherals
off, code
executed from
Flash, VDD
from 1.65 V to
3.6 V
MSI clock = 65 kHz,
fHCLK = 65 kHz
MSI clock =
131 kHz,
fHCLK = 131 kHz
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
60/127
DocID025938 Rev 6
Unit
µA
STM32L051x6 STM32L051x8
Electrical characteristics
Figure 16. IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Low-power run mode, code running
from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS
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06Y9
Table 33. Current consumption in Low-power sleep mode
Symbol
Parameter
Typ
Max(1)
TA = − 40 to 25°C
4.7(2)
-
TA = − 40 to 25°C
17
23
TA = 85 °C
19.5
63
TA = 105 °C
23
69
TA = 125 °C
32.5
90
TA = − 40 to 25°C
17
23
TA = 85 °C
20
63
TA = 105 °C
23.5
69
TA = 125 °C
32.5
90
TA = − 40 to 25°C
19.5
36
TA = 55 °C
20.5
64
TA = 85 °C
22.5
66
TA = 105 °C
26
72
TA = 125 °C
35
95
Conditions
MSI clock = 65 kHz,
fHCLK = 32 kHz,
Flash off
MSI clock = 65 kHz,
fHCLK = 32 kHz,
Flash on
Supply
current in
IDD
(LP Sleep) Low-power
sleep mode
All peripherals
off, VDD from
1.65 to 3.6 V
MSI clock =65 kHz,
fHCLK = 65 kHz,
Flash on
MSI clock = 131 kHz,
fHCLK = 131 kHz,
Flash on
Unit
µA
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
2. As the CPU is in Sleep mode, the difference between the current consumption with Flash on and off (nearly 12 µA) is the
same whatever the clock frequency.
DocID025938 Rev 6
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Electrical characteristics
STM32L051x6 STM32L051x8
Table 34. Typical and maximum current consumptions in Stop mode
Symbol
Parameter
Max(1) Unit
Conditions
Typ
TA = − 40 to 25°C
0.41
1
TA = 55°C
0.63
2.1
TA= 85°C
1.7
4.5
TA = 105°C
4
9.6
TA = 125°C
11
24(2)
IDD (Stop) Supply current in Stop mode
µA
1. Guaranteed by characterization results at 125 °C, unless otherwise specified.
2. Guaranteed by test in production.
Figure 17. IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled
and running on LSE Low drive
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Figure 18. IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with RTC disabled,
all clocks off
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62/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
Table 35. Typical and maximum current consumptions in Standby mode
Symbol
Parameter
Typ
Max(1)
TA = − 40 to 25°C
1.3
1.7
TA = 55 °C
-
2.9
TA= 85 °C
-
3.3
TA = 105 °C
-
4.1
TA = 125 °C
-
8.5
TA = − 40 to 25°C
0.29
0.6
TA = 55 °C
0.32
0.9
TA = 85 °C
0.5
2.3
TA = 105 °C
0.94
3
TA = 125 °C
2.6
7
Conditions
Independent watchdog
and LSI enabled
Supply current in Standby
IDD
(Standby)
mode
Independent watchdog
and LSI off
Unit
µA
1. Guaranteed by characterization results at 125 °C, unless otherwise specified
Table 36. Average current consumption during Wakeup
System frequency
Current
consumption
during wakeup
HSI
1
HSI/4
0,7
MSI clock = 4,2 MHz
0,7
MSI clock = 1,05 MHz
0,4
MSI clock = 65 KHz
0,1
Reset pin pulled down
-
0,21
BOR on
-
0,23
IDD (Wakeup from With Fast wakeup set
StandBy)
With Fast wakeup disabled
MSI clock = 2,1 MHz
0,5
MSI clock = 2,1 MHz
0,12
Symbol
parameter
IDD (Wakeup from Supply current during Wakeup from
Stop)
Stop mode
IDD (Reset)
IDD (Power-up)
DocID025938 Rev 6
Unit
mA
63/127
100
Electrical characteristics
STM32L051x6 STM32L051x8
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following tables. The
MCU is placed under the following conditions:
all I/O pins are in input mode with a static value at VDD or VSS (no load)
all peripherals are disabled unless otherwise mentioned
the given value is calculated by measuring the current consumption
–
with all peripherals clocked off
–
with only one peripheral clocked on
Table 37. Peripheral current consumption in Run or Sleep mode(1)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Peripheral
APB1
64/127
Low-power
sleep and
run
CRS
2.5
2
2
2
I2C1
11
9.5
7.5
9
I2C2
4
3.5
3
2.5
LPTIM1
10
8.5
6.5
8
LPUART1
8
6.5
5.5
6
SPI2
9
4.5
3.5
4
USART2
14.5
12
9.5
11
TIM2
10.5
8.5
7
9
TIM6
3.5
3
2.5
2
WWDG
3
2
2
2
ADC1(2)
5.5
5
3.5
4
4
3
3
2.5
USART1
14.5
11.5
9.5
12
TIM21
7.5
6
5
5.5
TIM22
7
6
5
6
FIREWALL
1.5
1
1
0.5
DBGMCU
1.5
1
1
0.5
SYSCFG
2.5
2
2
1.5
SPI1
APB2
Range 2,
Range 3,
Range 1,
VCORE=1.8 V VCORE=1.5 V VCORE=1.2 V
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11
DocID025938 Rev 6
Unit
µA/MHz
(fHCLK)
µA/MHz
(fHCLK)
STM32L051x6 STM32L051x8
Electrical characteristics
Table 37. Peripheral current consumption in Run or Sleep mode(1) (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 2,
Range 3,
Range 1,
VCORE=1.8 V VCORE=1.5 V VCORE=1.2 V
VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11
Peripheral
Low-power
sleep and
run
Unit
GPIOA
3.5
3
2.5
2.5
Cortex- GPIOB
M0+ core
I/O port GPIOC
3.5
2.5
2
2.5
8.5
6.5
5.5
7
1
0.5
0.5
0.5
CRC
1.5
1
1
1
FLASH
0(3)
0(3)
0(3)
0(3)
DMA1
10
8
6.5
8.5
All enabled
279
221.5
219.5
215
µA/MHz
(fHCLK)
PWR
2.5
2
2
1
µA/MHz
(fHCLK)
GPIOD
AHB
µA/MHz
(fHCLK)
µA/MHz
(fHCLK)
1. Data based on differential IDD measurement between all peripherals off an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is off for this measure.
3. Current consumption is negligible and close to 0 µA.
Table 38. Peripheral current consumption in Stop and Standby mode(1)
Symbol
IDD(PVD / BOR)
-
IREFINT
-
-
-
Typical consumption, TA = 25 °C
Peripheral
(2)
LSE Low drive
LPTIM1, Input 100 Hz
VDD=1.8 V
VDD=3.0 V
0.7
1.2
-
1.4
0,1
0,1
0,01
0,01
Unit
µA
-
LPTIM1, Input 1 MHz
6
6
-
LPUART1
0,2
0,2
-
RTC
0,3
0,48
1. LPTIM peripheral cannot operate in Standby mode.
DocID025938 Rev 6
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100
Electrical characteristics
2.
STM32L051x6 STM32L051x8
LSE Low drive consumption is the difference between an external clock on OSC32_IN and a quartz between OSC32_IN
and OSC32_OUT.-
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI or HSI16 RC
oscillator. The clock source used to wake up the device depends on the current operating
mode:
Sleep mode: the clock source is the clock that was set before entering Sleep mode
Stop mode: the clock source is either the MSI oscillator in the range configured before
entering Stop mode, the HSI16 or HSI16/4.
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under ambient temperature and VDD supply
voltage conditions summarized in Table 23.
Table 39. Low-power mode wakeup timings
Symbol
Parameter
tWUSLEEP
Wakeup from Sleep mode
tWUSLEEP_LP
tWUSTOP
66/127
Conditions
Wakeup from Low-power sleep mode,
fHCLK = 262 kHz
Typ
Max
fHCLK = 32 MHz
7
8
fHCLK = 262 kHz
Flash memory enabled
7
8
fHCLK = 262 kHz
Flash memory switched OFF
9
10
fHCLK = fMSI = 4.2 MHz
Wakeup from Stop mode, regulator in Run
fHCLK = fHSI = 16 MHz
mode
fHCLK = fHSI/4 = 4 MHz
5.0
8
4.9
7
8.0
11
fHCLK = fMSI = 4.2 MHz
Voltage range 1
5.0
8
fHCLK = fMSI = 4.2 MHz
Voltage range 2
5.0
8
fHCLK = fMSI = 4.2 MHz
Voltage range 3
5.0
8
7.3
13
13
23
28
38
fHCLK = fMSI = 262 kHz
51
65
fHCLK = fMSI = 131 kHz
100
120
fHCLK = MSI = 65 kHz
190
260
fHCLK = fHSI = 16 MHz
4.9
7
fHCLK = fHSI/4 = 4 MHz
8.0
11
fHCLK = fHSI = 16 MHz
Wakeup from Stop mode, regulator in lowfHCLK = fHSI/4 = 4 MHz
power mode, code running from RAM
fHCLK = fMSI = 4.2 MHz
4.9
7
7.9
10
4.7
8
fHCLK = fMSI = 2.1 MHz
Wakeup from Stop mode, regulator in lowfHCLK = fMSI = 1.05 MHz
power mode
fHCLK = fMSI = 524 kHz
DocID025938 Rev 6
Unit
Number
of clock
cycles
µs
STM32L051x6 STM32L051x8
Electrical characteristics
Table 39. Low-power mode wakeup timings (continued)
Symbol
tWUSTDBY
6.3.6
Parameter
Conditions
Typ
Max
Unit
Wakeup from Standby mode, FWU bit = 1 fHCLK = MSI = 2.1 MHz
65
130
µs
Wakeup from Standby mode, FWU bit = 0 fHCLK = MSI = 2.1 MHz
2.2
3
ms
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.12. However, the
recommended clock input waveform is shown in Figure 19.
Table 40. High-speed external user clock characteristics(1)
Symbol
fHSE_ext
Parameter
User external clock source
frequency
Conditions
Min
Typ
Max
Unit
CSS is on or
PLL is used
1
8
32
MHz
CSS is off, PLL
not used
0
8
32
MHz
VHSEH
OSC_IN input pin high level voltage
0.7VDD
-
VDD
VHSEL
OSC_IN input pin low level voltage
VSS
-
0.3VDD
tw(HSE)
tw(HSE)
OSC_IN high or low time
12
-
-
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
-
-
20
OSC_IN input capacitance
-
2.6
-
pF
45
-
55
%
-
-
±1
µA
Cin(HSE)
IL
ns
-
DuCy(HSE) Duty cycle
OSC_IN Input leakage current
VSS VIN VDD
V
1. Guaranteed by design.
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Electrical characteristics
STM32L051x6 STM32L051x8
Figure 19. High-speed external clock source AC timing diagram
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Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions
summarized in Table 23.
Table 41. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
Typ
Max
Unit
1
32.768
1000
kHz
0.7VDD
-
VDD
VSS
-
0.3VDD
fLSE_ext
User external clock source
frequency
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
tw(LSE)
tw(LSE)
OSC32_IN high or low time
465
-
-
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time
-
-
10
-
-
0.6
-
pF
-
45
-
55
%
VSS VIN VDD
-
-
±1
µA
CIN(LSE)
V
-
ns
OSC32_IN input capacitance
DuCy(LSE) Duty cycle
IL
OSC32_IN Input leakage current
1. Guaranteed by design, not tested in production
68/127
Min
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
Figure 20. Low-speed external clock source AC timing diagram
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 25 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 42. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 42. HSE oscillator characteristics(1)
Symbol
Parameter
fOSC_IN Oscillator frequency
RF
Feedback resistor
Gm
Maximum critical crystal
transconductance
tSU(HSE)
(2)
Startup time
Conditions
Min Typ
-
1
-
-
Startup
VDD is stabilized
Max Unit
25
MHz
200
-
k
-
-
700
µA
/V
-
2
-
ms
1. Guaranteed by design.
2. Guaranteed by characterization results. tSU(HSE) is the startup time measured from the moment it is
enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard
crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 21). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
DocID025938 Rev 6
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Electrical characteristics
STM32L051x6 STM32L051x8
Figure 21. HSE oscillator circuit diagram
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Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 43. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 43. LSE oscillator characteristics(1)
Symbol
fLSE
Gm
Parameter
Conditions(2)
Min(2)
Typ
Max
Unit
-
32.768
-
kHz
LSEDRV[1:0]=00
lower driving capability
-
-
0.5
LSEDRV[1:0]= 01
medium low driving capability
-
-
0.75
LSEDRV[1:0] = 10
medium high driving capability
-
-
1.7
LSEDRV[1:0]=11
higher driving capability
-
-
2.7
VDD is stabilized
-
2
-
LSE oscillator frequency
Maximum critical crystal
transconductance
tSU(LSE)(3) Startup time
µA/V
1. Guaranteed by design.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator design guide for
ST microcontrollers”.
3. Guaranteed by characterization results. tSU(LSE) is the startup time measured from the moment it is enabled (by software)
to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer. To increase speed, address a lower-drive quartz with a high- driver mode.
Note:
70/127
For information on selecting the crystal, refer to the application note AN2867 “Oscillator
design guide for ST microcontrollers” available from the ST website www.st.com.
DocID025938 Rev 6
s
STM32L051x6 STM32L051x8
Electrical characteristics
Figure 22. Typical application with a 32.768 kHz crystal
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Note:
An external resistor is not required between OSC32_IN and OSC32_OUT and it is forbidden
to add one.
DocID025938 Rev 6
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100
Electrical characteristics
6.3.7
STM32L051x6 STM32L051x8
Internal clock source characteristics
The parameters given in Table 44 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 23.
High-speed internal 16 MHz (HSI16) RC oscillator
Table 44. 16 MHz HSI16 oscillator characteristics
Symbol
fHSI16
TRIM
(1)(2)
ACCHSI16
(2)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
VDD = 3.0 V
-
16
-
MHz
HSI16 usertrimmed resolution
Trimming code is not a multiple of 16
-
0.4
0.7
%
Trimming code is a multiple of 16
-
Accuracy of the
factory-calibrated
HSI16 oscillator
-
1.5
%
VDDA = 3.0 V, TA = 25 °C
-1(3)
-
1(3)
%
VDDA = 3.0 V, TA = 0 to 55 °C
-1.5
-
1.5
%
VDDA = 3.0 V, TA = -10 to 70 °C
-2
-
2
%
VDDA = 3.0 V, TA = -10 to 85 °C
-2.5
-
2
%
VDDA = 3.0 V, TA = -10 to 105 °C
-4
-
2
%
-5.45
-
3.25
%
VDDA = 1.65 V to 3.6 V
TA = − 40 to 125 °C
tSU(HSI16)(2)
HSI16 oscillator
startup time
-
-
3.7
6
µs
IDD(HSI16)(2)
HSI16 oscillator
power consumption
-
-
100
140
µA
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results.
3. Guaranteed by test in production.
Figure 23. HSI16 minimum and maximum value versus temperature
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72/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
Low-speed internal (LSI) RC oscillator
Table 45. LSI oscillator characteristics
Symbol
Parameter
Min
Typ
Max
Unit
fLSI(1)
LSI frequency
26
38
56
kHz
DLSI(2)
LSI oscillator frequency drift
0°C TA 85°C
-10
-
4
%
LSI oscillator startup time
-
-
200
µs
LSI oscillator power consumption
-
400
510
nA
tsu(LSI)(3)
IDD(LSI)
(3)
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design.
Multi-speed internal (MSI) RC oscillator
Table 46. MSI oscillator characteristics
Symbol
fMSI
ACCMSI
DTEMP(MSI)(1)
DVOLT(MSI)(1)
Parameter
Condition
Typ
MSI range 0
65.5
-
MSI range 1
131
-
MSI range 2
262
-
MSI range 3
524
-
MSI range 4
1.05
-
MSI range 5
2.1
-
MSI range 6
4.2
-
Frequency error after factory calibration
-
0.5
-
MSI oscillator frequency drift
0 °C TA 85 °C
-
3
-
MSI range 0
− 8.9
+7.0
MSI range 1
− 7.1
+5.0
MSI range 2
− 6.4
+4.0
MSI range 3
− 6.2
+3.0
MSI range 4
− 5.2
+3.0
MSI range 5
− 4.8
+2.0
MSI range 6
− 4.7
+2.0
-
-
2.5
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
MSI oscillator frequency drift
VDD = 3.3 V, − 40 °C TA 110 °C
MSI oscillator frequency drift
1.65 V VDD 3.6 V, TA = 25 °C
DocID025938 Rev 6
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MHz
%
%
%/V
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Electrical characteristics
STM32L051x6 STM32L051x8
Table 46. MSI oscillator characteristics (continued)
Symbol
IDD(MSI)(2)
tSU(MSI)
tSTAB(MSI)(2)
fOVER(MSI)
Parameter
MSI oscillator power consumption
MSI oscillator startup time
MSI oscillator stabilization time
MSI oscillator frequency overshoot
Condition
Typ
MSI range 0
0.75
-
MSI range 1
1
-
MSI range 2
1.5
-
MSI range 3
2.5
-
MSI range 4
4.5
-
MSI range 5
8
-
MSI range 6
15
-
MSI range 0
30
-
MSI range 1
20
-
MSI range 2
15
-
MSI range 3
10
-
MSI range 4
6
-
MSI range 5
5
-
MSI range 6,
Voltage range 1
and 2
3.5
-
MSI range 6,
Voltage range 3
5
-
MSI range 0
-
40
MSI range 1
-
20
MSI range 2
-
10
MSI range 3
-
4
MSI range 4
-
2.5
MSI range 5
-
2
MSI range 6,
Voltage range 1
and 2
-
2
MSI range 3,
Voltage range 3
-
3
Any range to
range 5
-
4
Any range to
range 6
-
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results.
74/127
DocID025938 Rev 6
Max Unit
µA
µs
µs
MHz
6
STM32L051x6 STM32L051x8
6.3.8
Electrical characteristics
PLL characteristics
The parameters given in Table 47 are derived from tests performed under ambient
temperature and VDD supply voltage conditions summarized in Table 23.
Table 47. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
-
24
MHz
PLL input clock duty cycle
45
-
55
%
fPLL_OUT
PLL output clock
2
-
32
MHz
tLOCK
PLL input = 16 MHz
PLL VCO = 96 MHz
-
115
160
µs
Jitter
Cycle-to-cycle jitter
-
600
ps
IDDA(PLL)
Current consumption on VDDA
-
220
450
IDD(PLL)
Current consumption on VDD
-
120
150
fPLL_IN
µA
1. Guaranteed by characterization results.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
6.3.9
Memory characteristics
RAM memory
Table 48. RAM and hardware registers
Symbol
VRM
Parameter
Conditions
Data retention mode(1)
STOP mode (or RESET)
Min
Typ
Max
Unit
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
Flash memory and data EEPROM
Table 49. Flash memory and data EEPROM characteristics
Symbol
Conditions
Min
Typ
Max(1)
Unit
-
1.65
-
3.6
V
Erasing
-
3.28
3.94
Programming
-
3.28
3.94
Parameter
VDD
Operating voltage
Read / Write / Erase
tprog
Programming time for
word or half-page
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Electrical characteristics
STM32L051x6 STM32L051x8
Table 49. Flash memory and data EEPROM characteristics
Symbol
IDD
Min
Typ
Max(1)
Unit
Average current during
the whole programming /
erase operation
-
500
700
µA
Maximum current (peak) TA25 °C, VDD = 3.6 V
during the whole
programming / erase
operation
-
1.5
2.5
mA
Parameter
Conditions
1. Guaranteed by design.
Table 50. Flash memory and data EEPROM endurance and retention
Value
Symbol
Parameter
Cycling (erase / write)
Program memory
NCYC(2)
Cycling (erase / write)
EEPROM data memory
Cycling (erase / write)
Program memory
Cycling (erase / write)
EEPROM data memory
Data retention (program memory) after
10 kcycles at TA = 85 °C
Data retention (EEPROM data memory)
after 100 kcycles at TA = 85 °C
tRET(2)
Data retention (program memory) after
10 kcycles at TA = 105 °C
Data retention (EEPROM data memory)
after 100 kcycles at TA = 105 °C
Data retention (program memory) after
200 cycles at TA = 125 °C
Data retention (EEPROM data memory)
after 2 kcycles at TA = 125 °C
Conditions
Min(1)
10
TA-40°C to 105 °C
100
kcycles
0.2
TA-40°C to 125 °C
2
30
TRET = +85 °C
30
TRET = +105 °C
years
10
TRET = +125 °C
1. Guaranteed by characterization results.
2. Characterization is done according to JEDEC JESD22-A117.
6.3.10
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
76/127
Unit
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 51. They are based on the EMS levels and classes
defined in application note AN1709.
Table 51. EMS characteristics
Symbol
Parameter
Conditions
Level/
Class
VFESD
VDD 3.3 V, LQFP64, TA +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK 32 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
3B
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
VDD3.3 V, LQFP64, TA +25 °C,
fHCLK 32 MHz
conforms to IEC 61000-4-4
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
Corrupted program counter
Unexpected reset
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
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Electrical characteristics
STM32L051x6 STM32L051x8
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 52. EMI characteristics
Symbol Parameter
SEMI
78/127
Conditions
VDD 3.6 V,
Peak level TA 25 °C,
compliant with IEC
61967-2
Monitored
frequency band
Max vs. fosc/fCPU
8 MHz/ 8 MHz/ 8 MHz/
4 MHz 16 MHz 32 MHz
0.1 to 30 MHz
-21
-15
-12
30 to 130 MHz
-14
-12
-1
130 MHz to 1GHz
-10
-11
-7
1
1
1
EMI Level
DocID025938 Rev 6
Unit
dBµV
-
STM32L051x6 STM32L051x8
6.3.11
Electrical characteristics
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the ANSI/JEDEC standard.
Table 53. ESD absolute maximum ratings
Symbol
VESD(HBM)
Ratings
Conditions
Class
Maximum
value(1)
2
2000
TA +25 °C,
Electrostatic discharge
conforming to
voltage (human body model)
ANSI/JEDEC JS-001
TA +25 °C,
conforming to
ANSI/ESD STM5.3.1.
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
Unit
V
C4
500
1. Guaranteed by characterization results.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
A supply overvoltage is applied to each power supply pin
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 54. Electrical sensitivities
Symbol
LU
Parameter
Static latch-up class
Conditions
TA +125 °C conforming to JESD78A
DocID025938 Rev 6
Class
II level A
79/127
100
Electrical characteristics
6.3.12
STM32L051x6 STM32L051x8
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation).
The test results are given in the Table 55.
Table 55. I/O current injection susceptibility
Functional susceptibility
Symbol
IINJ
Description
Negative
injection
Positive
injection
Injected current on BOOT0
-0
NA
Injected current on PA0, PA4, PA5, PA11,
PA12, PC15, PH0 and PH1
-5
0
Injected current on any other FT, FTf pins
-5 (1)
NA
Injected current on any other pins
-5 (1)
+5
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
80/127
DocID025938 Rev 6
Unit
mA
STM32L051x6 STM32L051x8
6.3.13
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under the conditions summarized in Table 23. All I/Os are CMOS and TTL
compliant.
Table 56. I/O static characteristics
Symbol
VIL
VIH
Vhys
Ilkg
RPU
Parameter
Input low level voltage
Input high level voltage
I/O Schmitt trigger voltage hysteresis
(2)
Input leakage current (4)
Weak pull-up equivalent resistor(5)
RPD
Weak pull-down equivalent resistor
CIO
I/O pin capacitance
(5)
Conditions
Min
Typ
Max
Unit
TC, FT, FTf, RST
I/Os
-
-
0.3VDD
BOOT0 pin
-
-
0.14VDD(1)
All I/Os
0.7 VDD
-
-
Standard I/Os
-
10% VDD(3)
-
BOOT0 pin
-
0.01
-
VSS VIN VDD
All I/Os except for
PA11, PA12, BOOT0
and FTf I/Os
-
-
±50
VSS VIN VDD,
PA11 and PA12 I/Os
-
-
-50/+250
VSS VIN VDD
FTf I/Os
-
-
±100
VDDVIN 5 V
All I/Os except for
PA11, PA12, BOOT0
and FTf I/Os
-
-
200
VDDVIN 5 V
FTf I/Os
-
-
500
VDDVIN 5 V
PA11, PA12 and
BOOT0
-
-
10
µA
VIN VSS
30
45
60
k
VIN VDD
30
45
60
k
-
-
5
-
pF
V
nA
nA
1. Guaranteed by characterization.
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results.
3. With a minimum of 200 mV. Guaranteed by characterization results.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This
MOS/NMOS contribution to the series resistance is minimum (~10% order).
DocID025938 Rev 6
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100
Electrical characteristics
STM32L051x6 STM32L051x8
Figure 24. VIH/VIL versus VDD (CMOS I/Os)
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9,/9,+9
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9
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±15 mA with the non-standard VOL/VOH specifications given in Table 57.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
82/127
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 21).
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 21).
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
Output voltage levels
Unless otherwise specified, the parameters given in Table 57 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 23. All I/Os are CMOS and TTL compliant.
Table 57. Output voltage characteristics
Symbol
Parameter
VOL(1)
Output low level voltage for an I/O
pin
VOH(3)
Output high level voltage for an I/O
pin
Conditions
Min
Max
CMOS port(2),
IIO = +8 mA
2.7 V VDD 3.6 V
-
0.4
VDD-0.4
-
(1)
Output low level voltage for an I/O
pin
TTL port(2),
IIO =+ 8 mA
2.7 V VDD 3.6 V
-
0.4
(3)(4)
Output high level voltage for an I/O
pin
TTL port(2),
IIO = -6 mA
2.7 V VDD 3.6 V
2.4
-
VOL(1)(4)
Output low level voltage for an I/O
pin
IIO = +15 mA
2.7 V VDD 3.6 V
-
1.3
VOH(3)(4)
Output high level voltage for an I/O
pin
IIO = -15 mA
2.7 V VDD 3.6 V
VDD-1.3
-
VOL(1)(4)
Output low level voltage for an I/O
pin
IIO = +4 mA
1.65 V VDD < 3.6 V
-
0.45
VOH(3)(4)
Output high level voltage for an I/O
pin
IIO = -4 mA
V -0.45
1.65 V VDD 3.6 V DD
VOL
VOH
Output low level voltage for an FTf
VOLFM+(1)(4)
I/O pin in Fm+ mode
Unit
V
-
IIO = 20 mA
2.7 V VDD 3.6 V
-
0.4
IIO = 10 mA
1.65 V VDD 3.6 V
-
0.4
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 21.
The sum of the currents sunk by all the I/Os (I/O ports and control pins) must always be respected and
must not exceed ΣIIO(PIN).
2. TTL and CMOS outputs are compatible with JEDEC standards JESD36 and JESD52.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 21. The sum of the currents sourced by all the I/Os (I/O ports and control pins) must always be
respected and must not exceed ΣIIO(PIN).
4. Guaranteed by characterization results.
DocID025938 Rev 6
83/127
100
Electrical characteristics
STM32L051x6 STM32L051x8
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 26 and
Table 58, respectively.
Unless otherwise specified, the parameters given in Table 58 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 23.
Table 58. I/O AC characteristics(1)
OSPEEDRx[1:0]
bit value(1)
Symbol
fmax(IO)out
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
fmax(IO)out
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
00
01
Fmax(IO)out Maximum frequency(3)
10
tf(IO)out
tr(IO)out
Output rise and fall time
Fmax(IO)out Maximum frequency(3)
11
Fm+
configuration(4)
-
Min
Max(2)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
400
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
100
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
125
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
320
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
2
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
0.6
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
30
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
65
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
10
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
2
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
13
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
28
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
35
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
10
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
6
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
17
-
1
-
10
Parameter
tf(IO)out
tr(IO)out
Output rise and fall time
fmax(IO)out
Maximum frequency(3)
Conditions
tf(IO)out
Output fall time
tr(IO)out
Output rise time
-
30
Maximum frequency(3)
-
350
-
15
-
60
8
-
fmax(IO)out
tf(IO)out
Output fall time
tr(IO)out
Output rise time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
CL = 50 pF, VDD = 2.5 V to 3.6 V
CL = 50 pF, VDD = 1.65 V to 3.6 V
-
Unit
kHz
ns
MHz
ns
MHz
ns
MHz
ns
MHz
ns
KHz
ns
ns
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the line reference manual for a description of GPIO Port
configuration register.
2. Guaranteed by design.
3. The maximum frequency is defined in Figure 26.
4. When Fm+ configuration is set, the I/O speed control is bypassed. Refer to the line reference manual for a detailed
description of Fm+ I/O configuration.
84/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
Figure 26. I/O AC characteristics definition
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6.3.14
DLG
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU , except when it is internally driven low (see Table 59).
Unless otherwise specified, the parameters given in Table 59 are derived from tests
performed under ambient temperature and VDD supply voltage conditions summarized in
Table 23.
Table 59. NRST pin characteristics
Symbol
VIL(NRST)
(1)
Parameter
Conditions
Min
Typ
NRST input low level voltage
-
VSS
-
0.8
-
1.4
-
VDD
IOL = 2 mA
2.7 V < VDD < 3.6 V
-
-
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
-
-
-
-
10%VDD(2)
-
mV
Weak pull-up equivalent
resistor(3)
VIN VSS
30
45
60
k
NRST input filtered pulse
-
-
-
50
ns
NRST input not filtered pulse
-
350
-
-
ns
VIH(NRST)(1) NRST input high level voltage
NRST output low level
VOL(NRST)(1)
voltage
Vhys(NRST)(1)
RPU
VF(NRST)(1)
VNF(NRST)
(1)
NRST Schmitt trigger voltage
hysteresis
Max Unit
V
0.4
1. Guaranteed by design.
2. 200 mV minimum value
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to
the series resistance is around 10%.
DocID025938 Rev 6
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100
Electrical characteristics
STM32L051x6 STM32L051x8
Figure 27. Recommended NRST pin protection
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1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 59. Otherwise the reset will not be taken into account by the device.
6.3.15
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 60 are derived from tests
performed under ambient temperature, fPCLK frequency and VDDA supply voltage conditions
summarized in Table 23: General operating conditions.
Note:
It is recommended to perform a calibration after each power-up.
Table 60. ADC characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
VDDA
Analog supply voltage for
ADC on
Fast channel
1.65
-
3.6
Standard channel
1.75(1)
-
3.6
VREF+
Positive reference voltage
-
1.65
Current consumption of the
ADC on VDDA and VREF+
1.14 Msps
-
200
-
10 ksps
-
40
-
Current consumption of the
ADC on VDD(2)
1.14 Msps
-
70
-
10 ksps
-
1
-
Voltage scaling Range 1
0.14
-
16
Voltage scaling Range 2
0.14
-
8
Voltage scaling Range 3
0.14
-
4
Sampling rate
12-bit resolution
0.01
-
1.14
MHz
External trigger frequency
fADC = 16 MHz,
12-bit resolution
-
-
941
kHz
-
-
-
17
1/fADC
IDDA (ADC)
fADC
fS(3)
fTRIG(3)
ADC clock frequency
VDDA
V
V
µA
MHz
VAIN
Conversion voltage range
-
0
-
VREF+
V
RAIN(3)
External input impedance
See Equation 1 and
Table 61 for details
-
-
50
k
-
-
-
1
k
RADC(3)(4)
86/127
Sampling switch resistance
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
Table 60. ADC characteristics (continued)
Symbol
Parameter
CADC(3)
Internal sample and hold
capacitor
tCAL(3)(5)
Calibration time
Conditions
Min
Typ
Max
Unit
-
-
-
8
pF
fADC = 16 MHz
5.2
µs
-
83
1/fADC
1.5 ADC
cycles + 2
fPCLK cycles
-
1.5 ADC
cycles + 3
fPCLK cycles
-
ADC clock = PCLK/2
-
4.5
-
fPCLK
cycle
ADC clock = PCLK/4
-
8.5
-
fPCLK
cycle
ADC clock = HSI16
WLATENCY(6)
tlatr(3)
JitterADC
tS(3)
tUP_LDO(3)(5)
tSTAB(3)(5)
tConV(3)
ADC_DR register write
latency
Trigger conversion latency
fADC = fPCLK/2 = 16 MHz
0.266
µs
fADC = fPCLK/2
8.5
1/fPCLK
fADC = fPCLK/4 = 8 MHz
0.516
µs
fADC = fPCLK/4
16.5
1/fPCLK
fADC = fHSI16 = 16 MHz
0.252
-
0.260
µs
fADC = fHSI16
-
1
-
1/fHSI16
fADC = 16 MHz
0.093
-
10.03
µs
-
1.5
-
160.5
1/fADC
Internal LDO power-up time
-
-
-
10
µs
ADC stabilization time
-
ADC jitter on trigger
conversion
Sampling time
Total conversion time
(including sampling time)
fADC = 16 MHz,
12-bit resolution
12-bit resolution
14
0.875
-
1/fADC
10.81
14 to 173 (tS for sampling +12.5
for successive approximation)
µs
1/fADC
1. VDDA minimum value can be decreased in specific temperature conditions. Refer to Table 61: RAIN max for fADC = 16 MHz.
2. A current consumption proportional to the APB clock frequency has to be added (see Table 37: Peripheral current
consumption in Run or Sleep mode).
3. Guaranteed by design.
4. Standard channels have an extra protection resistance which depends on supply voltage. Refer to Table 61: RAIN max for
fADC = 16 MHz.
5. This parameter only includes the ADC timing. It does not take into account register access latency.
6. This parameter specifies the latency to transfer the conversion result into the ADC_DR register. EOC bit is set to indicate the
conversion is complete and has the same latency.
DocID025938 Rev 6
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Electrical characteristics
STM32L051x6 STM32L051x8
Equation 1: RAIN max formula
TS
- – R ADC
R AIN ------------------------------------------------------------N+2
f ADC C ADC ln 2
The simplified formula above (Equation 1) is used to determine the maximum external
impedance allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution).
Table 61. RAIN max for fADC = 16 MHz(1)
Ts
(cycles)
tS
(µs)
RAIN max for
fast channels
(k)
1.5
0.09
3.5
RAIN max for standard channels (k)
VDD > 1.65 V VDD > 1.65 V
and
and
TA > 10 °C
TA > 25 °C
VDD >
2.7 V
VDD >
2.4 V
VDD >
2.0 V
VDD >
1.8 V
VDD >
1.75 V
0.5
< 0.1
NA
NA
NA
NA
NA
NA
0.22
1
0.2
< 0.1
NA
NA
NA
NA
NA
7.5
0.47
2.5
1.7
1.5
< 0.1
NA
NA
NA
NA
12.5
0.78
4
3.2
3
1
NA
NA
NA
NA
19.5
1.22
6.5
5.7
5.5
3.5
NA
NA
NA
< 0.1
39.5
2.47
13
12.2
12
10
NA
NA
NA
5
79.5
4.97
27
26.2
26
24
< 0.1
NA
NA
19
160.5
10.03
50
49.2
49
47
32
< 0.1
< 0.1
42
1. Guaranteed by design.
Table 62. ADC accuracy(1)(2)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
ET
Total unadjusted error
-
2
4
EO
Offset error
-
1
2.5
EG
Gain error
-
1
2
EL
Integral linearity error
-
1.5
2.5
ED
Differential linearity error
-
1
1.5
10.2
11
11.3
12.1
-
Effective number of bits
1.65 V < VDDA = VREF+ < 3.6 V,
range 1/2/3
ENOB
Effective number of bits (16-bit mode
oversampling with ratio =256)(4)
SINAD
Signal-to-noise distortion
63
69
-
Signal-to-noise ratio
63
69
-
SNR
Signal-to-noise ratio (16-bit mode
oversampling with ratio =256)(4)
70
76
-
THD
Total harmonic distortion
-
-85
-73
88/127
DocID025938 Rev 6
Unit
LSB
bits
dB
STM32L051x6 STM32L051x8
Electrical characteristics
Table 62. ADC accuracy(1)(2)(3)
Symbol
Parameter
Conditions
Min
Typ
Max
ET
Total unadjusted error
-
2
5
EO
Offset error
-
1
2.5
EG
Gain error
-
1
2
EL
Integral linearity error
-
1.5
3
-
1
2
1.65 V < VREF+ < VDDA < 3.6 V,
range 1/2/3
ED
Differential linearity error
ENOB
Effective number of bits
10.0
11.0
-
SINAD
Signal-to-noise distortion
62
69
-
SNR
Signal-to-noise ratio
61
69
-
THD
Total harmonic distortion
-
-85
-65
Unit
LSB
bits
dB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of the standard (non-robust) analog input
pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog
input. It is recommended to add a Schottky diode (pin to ground) to standard analog pins which may potentially inject
negative current.
Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.12 does not affect the ADC
accuracy.
3. Better performance may be achieved in restricted VDDA, frequency and temperature ranges.
4. This number is obtained by the test board without additional noise, resulting in non-optimized value for oversampling mode.
Figure 28. ADC accuracy characteristics
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DocID025938 Rev 6
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Electrical characteristics
STM32L051x6 STM32L051x8
Figure 29. Typical connection diagram using the ADC
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1. Refer to Table 60: ADC characteristics for the values of RAIN, RADC and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 30 or Figure 31,
depending on whether VREF+ is connected to VDDA or not. The 10 nF capacitors should be
ceramic (good quality). They should be placed as close as possible to the chip.
Figure 30. Power supply and reference decoupling (VREF+ not connected to VDDA)
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DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
Figure 31. Power supply and reference decoupling (VREF+ connected to VDDA)
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6.3.16
Temperature sensor characteristics
Table 63. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C, VDDA= 3 V
TS_CAL2
TS ADC raw data acquired at
0x1FF8 007E - 0x1FF8 007F
temperature of 130 °C, VDDA= 3 V
0x1FF8 007A - 0x1FF8 007B
Table 64. Temperature sensor characteristics
Symbol
TL(1)
Avg_Slope
Parameter
VSENSE linearity with temperature
(1)
Average slope
±5°C(2)
Min
Typ
Max
Unit
-
1
2
°C
1.48
1.61
1.75
mV/°C
640
670
700
mV
µA
V130
Voltage at 130°C
IDDA(TEMP)(3)
Current consumption
-
3.4
6
tSTART(3)
Startup time
-
-
10
TS_temp(4)(3)
ADC sampling time when reading the temperature
10
-
-
µs
1. Guaranteed by characterization results.
2. Measured at VDD = 3 V ±10 mV. V130 ADC conversion result is stored in the TS_CAL2 byte.
3. Guaranteed by design.
4. Shortest sampling time can be determined in the application by multiple iterations.
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Electrical characteristics
6.3.17
STM32L051x6 STM32L051x8
Comparators
Table 65. Comparator 1 characteristics
Symbol
Parameter
Conditions
Min(1)
Typ
Max(1)
Unit
3.6
V
VDDA
Analog supply voltage
-
1.65
R400K
R400K value
-
-
400
-
R10K
R10K value
-
-
10
-
Comparator 1 input voltage
range
-
0.6
-
VDDA
Comparator startup time
-
-
7
10
-
-
3
10
-
-
3
10
mV
Comparator offset variation in VDDA 3.6 V, VIN+ 0 V,
worst voltage stress conditions VIN- VREFINT, TA = 25 C
0
1.5
10
mV/1000 h
Current consumption(3)
-
160
260
nA
VIN
tSTART
td
Propagation
Voffset
dVoffset/dt
ICOMP1
delay(2)
Comparator offset
-
k
V
µs
1. Guaranteed by characterization.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to
the reference.
3. Comparator consumption only. Internal reference voltage not included.
Table 66. Comparator 2 characteristics
Symbol
VDDA
VIN
Conditions
Min
Typ
Max(1)
Unit
Analog supply voltage
-
1.65
-
3.6
V
Comparator 2 input voltage range
-
0
-
VDDA
V
Fast mode
-
15
20
Slow mode
-
20
25
1.65 V VDDA 2.7 V
-
1.8
3.5
2.7 V VDDA 3.6 V
-
2.5
6
1.65 V VDDA 2.7 V
-
0.8
2
2.7 V VDDA 3.6 V
-
1.2
4
-
4
20
mV
VDDA 3.3V, TA = 0 to 50 C,
V- = VREFINT,
3/4 VREFINT,
1/2 VREFINT,
1/4 VREFINT.
-
15
30
ppm
/°C
Fast mode
-
3.5
5
Slow mode
-
0.5
2
Parameter
tSTART
Comparator startup time
td slow
Propagation delay(2) in slow mode
td fast
Propagation delay(2) in fast mode
Voffset
Comparator offset error
dThreshold/
dt
ICOMP2
Threshold voltage temperature
coefficient
Current consumption(3)
µs
µA
1. Guaranteed by characterization results.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-inverting input set to
the reference.
3. Comparator consumption only. Internal reference voltage (required for comparator operation) is not included.
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6.3.18
Electrical characteristics
Timer characteristics
TIM timer characteristics
The parameters given in the Table 67 are guaranteed by design.
Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate
function characteristics (output compare, input capture, external clock, PWM output).
Table 67. TIMx characteristics(1)
Symbol
Parameter
tres(TIM)
Conditions
Timer resolution time
fTIMxCLK = 32 MHz
Timer external clock frequency on CH1
to CH4
fEXT
ResTIM
tCOUNTER
Max
Unit
1
-
tTIMxCLK
31.25
-
ns
0
fTIMxCLK/2
MHz
0
16
MHz
16
bit
65536
tTIMxCLK
2048
µs
fTIMxCLK = 32 MHz
Timer resolution
-
16-bit counter clock period when
internal clock is selected (timer’s
prescaler disabled)
-
tMAX_COUNT Maximum possible count
Min
1
fTIMxCLK = 32 MHz 0.0312
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 32 MHz
-
134.2
s
1. TIMx is used as a general term to refer to the TIM2, TIM6, TIM21, and TIM22 timers.
6.3.19
Communications interfaces
I2C interface characteristics
The I2C interface meets the timings requirements of the I2C-bus specification and user
manual rev. 03 for:
Standard-mode (Sm) : with a bit rate up to 100 kbit/s
Fast-mode (Fm) : with a bit rate up to 400 kbit/s
Fast-mode Plus (Fm+) : with a bit rate up to 1 Mbit/s.
The I2C timing requirements are guaranteed by design when the I2C peripheral is properly
configured (refer to the reference manual for details). The SDA and SCL I/O requirements
are met with the following restrictions: the SDA and SCL I/O pins are not "true" open-drain.
When configured as open-drain, the PMOS connected between the I/O pin and VDDIOx is
disabled, but is still present. Only FTf I/O pins support Fm+ low level output current
maximum requirement (refer to Section 6.3.13: I/O port characteristics for the I2C I/Os
characteristics).
All I2C SDA and SCL I/Os embed an analog filter (see Table 68 for the analog filter
characteristics).
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Electrical characteristics
STM32L051x6 STM32L051x8
The analog spike filter is compliant with I2C timings requirements only for the following
voltage ranges:
Fast mode Plus: 2.7 V VDD 3.6 V and voltage scaling Range 1
Fast mode:
–
2 V VDD 3.6 V and voltage scaling Range 1 or Range 2.
–
VDD < 2 V, voltage scaling Range 1 or Range 2, Cload < 200 pF.
In other ranges, the analog filter should be disabled. The digital filter can be used instead.
Note:
In Standard mode, no spike filter is required.
Table 68. I2C analog filter characteristics(1)
Symbol
Parameter
Conditions
Min
tAF
Range 2
Unit
100(3)
Range 1
Maximum pulse width of spikes that
are suppressed by the analog filter
Max
50(2)
Range 3
-
ns
-
1. Guaranteed by characterization results.
2. Spikes with widths below tAF(min) are filtered.
3. Spikes with widths above tAF(max) are not filtered
USART/LPUART characteristics
The parameters given in the following table are guaranteed by design.
Table 69. USART/LPUART characteristics
Symbol
tWUUSART
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Parameter
Wakeup time needed to
calculate the maximum
USART/LPUART baudrate
allowing to wake up from
Stop mode
Conditions
Typ
Max
Stop mode with main regulator in
Run mode, Range 2 or 3
-
8.7
Stop mode with main regulator in
Run mode, Range 1
-
8.1
Unit
µs
Stop mode with main regulator in
low-power mode, Range 2 or 3
-
12
Stop mode with main regulator in
low-power mode, Range 1
-
11.4
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Electrical characteristics
SPI characteristics
Unless otherwise specified, the parameters given in the following tables are derived from
tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage
conditions summarized in Table 23.
Refer to Section 6.3.12: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 70. SPI characteristics in voltage Range 1 (1)
Symbol
Parameter
Conditions
Min
Typ
-
-
Slave mode
Transmitter
1.71<VDD<3.6V
-
-
12(2)
Slave mode
Transmitter
2.7<VDD<3.6V
-
-
16(2)
Master mode
Slave mode
receiver
fSCK
1/tc(SCK)
SPI clock frequency
Max
16
16
Duty(SCK)
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
tsu(NSS)
NSS setup time
Slave mode, SPI
presc = 2
4*Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI
presc = 2
2*Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-2
Tpclk
Tpclk+
2
Master mode
0
-
-
Slave mode
3
-
-
Master mode
7
-
-
Slave mode
3.5
-
-
tsu(MI)
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
ta(SO
Data output access time
Slave mode
15
-
36
tdis(SO)
Data output disable time
Slave mode
10
-
30
Slave mode
1.65 V<VDD<3.6 V
-
18
41
Slave mode
2.7 V<VDD<3.6 V
-
18
25
Master mode
-
4
7
Slave mode
10
-
-
Master mode
0
-
-
tv(SO)
Data output valid time
tv(MO)
th(SO)
th(MO)
Data output hold time
Unit
MHz
%
ns
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI)
which has to fit into SCK low or high phase preceding the SCK sampling edge. This value can be
achieved when the SPI communicates with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
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Electrical characteristics
STM32L051x6 STM32L051x8
Table 71. SPI characteristics in voltage Range 2 (1)
Symbol
Parameter
Conditions
Min
Typ
Master mode
fSCK
1/tc(SCK)
SPI clock frequency
Slave mode Transmitter
1.65<VDD<3.6V
Max
8
-
-
Slave mode Transmitter
2.7<VDD<3.6V
8
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4*Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2*Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-2
Tpclk
Tpclk+2
Master mode
0
-
-
Slave mode
3
-
-
Master mode
11
-
-
Slave mode
4.5
-
-
tsu(SI)
th(MI)
th(SI)
Data input setup time
Data input hold time
ta(SO
Data output access time
Slave mode
18
-
52
tdis(SO)
Data output disable time
Slave mode
12
-
42
Slave mode
-
20
56.5
Master mode
-
5
9
Slave mode
13
-
-
Master mode
3
-
-
tv(SO)
Data output valid time
tv(MO)
th(SO)
th(MO)
Data output hold time
MHz
8(2)
Duty(SCK)
tsu(MI)
Unit
%
ns
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
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STM32L051x6 STM32L051x8
Electrical characteristics
Table 72. SPI characteristics in voltage Range 3 (1)
Symbol
Parameter
Min
Typ
fSCK
1/tc(SCK)
SPI clock frequency
-
-
Duty(SCK)
Duty cycle of SPI clock
frequency
Slave mode
30
50
70
tsu(NSS)
NSS setup time
Slave mode, SPI presc = 2
4*Tpclk
-
-
th(NSS)
NSS hold time
Slave mode, SPI presc = 2
2*Tpclk
-
-
tw(SCKH)
tw(SCKL)
SCK high and low time
Master mode
Tpclk-2
Tpclk
Tpclk+2
Master mode
1.5
-
-
Slave mode
6
-
-
Master mode
13.5
-
-
Slave mode
16
-
-
tsu(MI)
Conditions
Data input setup time
tsu(SI)
th(MI)
Data input hold time
th(SI)
Master mode
Slave mode
Max
2
2(2)
ta(SO
Data output access time
Slave mode
30
-
70
tdis(SO)
Data output disable time
Slave mode
40
-
80
Slave mode
-
30
70
Master mode
-
7
9
Slave mode
25
-
-
Master mode
8
-
-
tv(SO)
Data output valid time
tv(MO)
th(SO)
Data output hold time
th(MO)
Unit
MHz
%
ns
1. Guaranteed by characterization results.
2. The maximum SPI clock frequency in slave transmitter mode is determined by the sum of tv(SO) and tsu(MI) which has to fit
into SCK low or high phase preceding the SCK sampling edge. This value can be achieved when the SPI communicates
with a master having tsu(MI) = 0 while Duty(SCK) = 50%.
Figure 32. SPI timing diagram - slave mode and CPHA = 0
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Electrical characteristics
STM32L051x6 STM32L051x8
Figure 33. SPI timing diagram - slave mode and CPHA = 1(1)
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Figure 34. SPI timing diagram - master mode(1)
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
98/127
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STM32L051x6 STM32L051x8
Electrical characteristics
I2S characteristics
Table 73. I2S characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
fMCK
I2S Main clock output
-
256 x 8K
256xFs (2)
MHz
fCK
I2S clock frequency
Master data: 32 bits
-
64xFs
Slave data: 32 bits
-
64xFs
DCK
I2S clock frequency duty
cycle
Slave receiver
30
70
tv(WS)
WS valid time
Master mode
-
15
th(WS)
WS hold time
Master mode
11
-
tsu(WS)
WS setup time
Slave mode
6
-
th(WS)
WS hold time
Slave mode
2
-
Master receiver
0
-
Slave receiver
6.5
-
Master receiver
18
-
Slave receiver
15.5
-
Slave transmitter (after enable edge)
-
77
Master transmitter (after enable edge)
-
8
Slave transmitter (after enable edge)
18
-
Master transmitter (after enable edge)
1.5
-
tsu(SD_MR)
tsu(SD_SR)
th(SD_MR)
th(SD_SR)
tv(SD_ST)
tv(SD_MT)
th(SD_ST)
th(SD_MT)
Data input setup time
Data input hold time
Data output valid time
Data output hold time
MHz
%
ns
1. Guaranteed by characterization results.
2. 256xFs maximum value is equal to the maximum clock frequency.
Note:
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
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Electrical characteristics
STM32L051x6 STM32L051x8
Figure 35. I2S slave timing diagram (Philips protocol)(1)
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1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 36. I2S master timing diagram (Philips protocol)(1)
TF#+
TR#+
#+OUTPUT
TC#+
#0/,
TW#+(
#0/,
TV73
TH73
TW#+,
73OUTPUT
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"ITNTRANSMIT
TH3$?-4
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"ITNRECEIVE
,3"RECEIVE
AIB
1. Guaranteed by characterization results.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
100/127
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STM32L051x6 STM32L051x8
7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at www.st.com.
ECOPACK® is an ST trademark.
LQFP64 package information
Figure 37. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
PP
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1. Drawing is not to scale.
Table 74. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
DocID025938 Rev 6
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121
Package information
STM32L051x6 STM32L051x8
Table 74. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
c
0.090
-
0.200
0.0035
-
0.0079
D
-
12.000
-
-
0.4724
-
D1
-
10.000
-
-
0.3937
-
D3
-
7.500
-
-
0.2953
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
E3
-
7.500
-
-
0.2953
-
e
-
0.500
-
-
0.0197
-
K
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 38. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat recommended footprint
AIC
1. Dimensions are expressed in millimeters.
102/127
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STM32L051x6 STM32L051x8
Package information
Device marking for LQFP64
The following figure gives an example of topside marking versus pin 1 position identifier
location.
Figure 39. LQFP64 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
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Package information
7.2
STM32L051x6 STM32L051x8
TFBGA64 package information
Figure 40. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch thin profile fine pitch ball
grid array package outline
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1. Drawing is not to scale.
Table 75. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
grid array package mechanical data
inches(1)
millimeters
Symbol
104/127
Min
Typ
Max
Min
Typ
Max
A
-
-
1.200
-
-
0.0472
A1
0.150
-
-
0.0059
-
-
A2
-
0.200
-
-
0.0079
-
A4
-
-
0.600
-
-
0.0236
b
0.250
0.300
0.350
0.0098
0.0118
0.0138
D
4.850
5.000
5.150
0.1909
0.1969
0.2028
D1
-
3.500
-
-
0.1378
-
E
4.850
5.000
5.150
0.1909
0.1969
0.2028
E1
-
3.500
-
-
0.1378
-
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Package information
Table 75. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
grid array package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
e
-
0.500
-
-
0.0197
-
F
-
0.750
-
-
0.0295
-
ddd
-
-
0.080
-
-
0.0031
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 41. TFBGA64 – 64-ball, 5 x 5 mm, 0.5 mm pitch, thin profile fine pitch ball
,grid array recommended footprint
'SDG
'VP
069
Table 76. TFBGA64 recommended PCB design rules (0.5 mm pitch BGA)
Dimension
Note:
Recommended values
Pitch
0.5
Dpad
0.27 mm
Dsm
0.35 mm typ. (depends on the soldermask
registration tolerance)
Solder paste
0.27 mm aperture diameter.
Non solder mask defined (NSMD) pads are recommended.
4 to 6 mils solder paste screen printing process.
DocID025938 Rev 6
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121
Package information
STM32L051x6 STM32L051x8
Device marking for TFBGA64
The following figure gives an example of topside marking versus ball A 1 position identifier
location.
Figure 42. TFBGA64 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
106/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
LQFP48 package information
Figure 43. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
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1. Drawing is not to scale.
DocID025938 Rev 6
107/127
121
Package information
STM32L051x6 STM32L051x8
Table 77. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.500
-
-
0.2165
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.500
-
-
0.2165
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
108/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Package information
Figure 44. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat recommended footprint
AID
1. Dimensions are expressed in millimeters.
Device marking for LQFP48
The following figure gives an example of topside marking versus pin 1 position identifier
location.
Figure 45. LQFP48 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID025938 Rev 6
109/127
121
Package information
7.4
STM32L051x6 STM32L051x8
WLCSP36 package information
Figure 46. WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale
package outline
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EEE =
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1. Drawing is not to scale.
Table 78. WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale
mechanical data
inches(1)
millimeters
Symbol
110/127
Min
Typ
Max
Min
Typ
Max
A
0.525
0.555
0.585
0.0207
0.0219
0.0230
A1
-
0.175
-
-
0.0069
-
A2
-
0.380
-
-
0.0150
-
A3(2)
-
0.025
-
-
0.0010
-
b(3)
0.220
0.250
0.280
0.0087
0.0098
0.0110
D
2.561
2.596
2.631
0.1008
0.1022
0.1036
E
2.833
2.868
2.903
0.1115
0.1129
0.1143
e
-
0.400
-
-
0.0157
-
e1
-
2.000
-
-
0.0787
-
e2
-
2.000
-
-
0.0787
-
F
-
0.298
-
-
0.0117
-
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Package information
Table 78. WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale
mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
G
-
0.434
-
-
0.0171
-
aaa
-
-
0.100
-
-
0.0039
bbb
-
-
0.100
-
-
0.0039
ccc
-
-
0.100
-
-
0.0039
ddd
-
-
0.050
-
-
0.0020
eee
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Back side coating.
3. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 47. WLCSP36 - 2.596 x 2.868 mm, 0.4 mm pitch wafer level chip scale
recommended footprint
'SDG
'VP
069
Table 79. WLCSP36 recommended PCB design rules
Dimension
Recommended values
Pitch
0.4 mm
Dpad
260 µm max. (circular)
220 µm recommended
Dsm
300 µm min. (for 260 µm diameter pad)
PCB pad design
Non-solder mask defined via underbump allowed
DocID025938 Rev 6
111/127
121
Package information
STM32L051x6 STM32L051x8
Device marking for WLCSP36
The following figure gives an example of topside marking versus ball A 1 position identifier
location.
Figure 48. WLCSP36 marking example (package top view)
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qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
112/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
LQFP32 package information
Figure 49. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline
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1. Drawing is not to scale.
DocID025938 Rev 6
113/127
121
Package information
STM32L051x6 STM32L051x8
Table 80. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.300
0.370
0.450
0.0118
0.0146
0.0177
c
0.090
-
0.200
0.0035
-
0.0079
D
8.800
9.000
9.200
0.3465
0.3543
0.3622
D1
6.800
7.000
7.200
0.2677
0.2756
0.2835
D3
-
5.600
-
-
0.2205
-
E
8.800
9.000
9.200
0.3465
0.3543
0.3622
E1
6.800
7.000
7.200
0.2677
0.2756
0.2835
E3
-
5.600
-
-
0.2205
-
e
-
0.800
-
-
0.0315
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.100
-
-
0.0039
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 50. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint
1. Dimensions are expressed in millimeters.
114/127
DocID025938 Rev 6
6?&0?6
STM32L051x6 STM32L051x8
Package information
Device marking for LQFP32
The following figure gives an example of topside marking versus pin 1 position identifier
location.
Figure 51. LQFP32 marking example (package top view)
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
DocID025938 Rev 6
115/127
121
Package information
7.6
STM32L051x6 STM32L051x8
UFQFPN32 package information
Figure 52. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package outline
'
$
H
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$
$
GGG &
&
6($7,1*
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E
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'
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1. Drawing is not to scale.
116/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Package information
Table 81. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
package mechanical data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.500
0.550
0.600
0.0197
0.0217
0.0236
A1
0.000
0.020
0.050
0.0000
0.0008
0.0020
A3
-
0.152
-
-
0.0060
-
b
0.180
0.230
0.280
0.0071
0.0091
0.0110
D
4.900
5.000
5.100
0.1929
0.1969
0.2008
D1
3.400
3.500
3.600
0.1339
0.1378
0.1417
D2
3.400
3.500
3.600
0.1339
0.1378
0.1417
E
4.900
5.000
5.100
0.1929
0.1969
0.2008
E1
3.400
3.500
3.600
0.1339
0.1378
0.1417
E2
3.400
3.500
3.600
0.1339
0.1378
0.1417
e
-
0.500
-
-
0.0197
-
L
0.300
0.400
0.500
0.0118
0.0157
0.0197
ddd
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 53. UFQFPN32 - 32-pin, 5x5 mm, 0.5 mm pitch ultra thin fine pitch quad flat
recommended footprint
$%B)3B9
1. Dimensions are expressed in millimeters.
DocID025938 Rev 6
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121
Package information
STM32L051x6 STM32L051x8
Device marking for UFQFPN32
The following figure gives an example of topside marking versus pin 1 position identifier
location.
Figure 54. UFQFPN32 marking example (package top view)
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'DWHFRGH <HDUZHHN
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity.
118/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
7.7
Package information
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × JA)
Where:
TA max is the maximum ambient temperature in C,
JA is the package junction-to-ambient thermal resistance, in C/W,
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = (VOL × IOL) + ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 82. Thermal characteristics
Symbol
JA
Parameter
Value
Thermal resistance junction-ambient
TFBGA64 - 5 x 5 mm / 0.5 mm pitch
61
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
45
Thermal resistance junction-ambient
WLCSP36 - 0.4 mm pitch
63
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm / 0.5 mm pitch
55
Thermal resistance junction-ambient
LQFP32 - 7 x 7 mm / 0.8 mm pitch
57
Thermal resistance junction-ambient
UFQFPN32 - 5 x 5 mm / 0.5 mm pitch
38
DocID025938 Rev 6
Unit
°C/W
119/127
121
Package information
STM32L051x6 STM32L051x8
Figure 55. Thermal resistance
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Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
120/127
DocID025938 Rev 6
STM32L051x6 STM32L051x8
8
Part numbering
Part numbering
Table 83. STM32L051x6/8 ordering information scheme
Example:
STM32 L
051
R
8
T
6
D TR
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
L = Low power
Device subfamily
051 = Access line
Pin count
K = 32 pins
T = 36 pins
C = 48/49 pins
R = 64 pins
Flash memory size
6 = 32 Kbytes
8 = 64 Kbytes
Package
T = LQFP
H = TFBGA
U = UFQFPN
Y = WLCSP pins
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
3 = Industrial temperature range, –40 to 125 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
DocID025938 Rev 6
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121
Revision history
9
STM32L051x6 STM32L051x8
Revision history
Table 84. Document revision history
Date
Revision
13-Feb-2014
1
Initial release.
2
Added WLCSP36 package. Updated Table 2: Ultra-low-power
STM32L051x6/x8 device features and peripheral counts
Updated Table 5: Functionalities depending on the working mode (from
Run/active down to standby). Added Section 3.2: Interconnect matrix.
Updated Figure 4: STM32L051x6/8 TFBGA64 ballout - 5x 5 mm
Replaced TTa I/O structure by TC, updated PA0/4/5, PC5/14, BOOT0
and NRST I/O structure in Table 15: STM32L051x6/8 pin definitions.
Updated Table 23: General operating conditions, Table 20: Voltage
characteristics and Table 21: Current characteristics.
Modified conditions in Table 26: Embedded internal reference voltage.
Updated Table 27: Current consumption in Run mode, code with data
processing running from Flash, Table 29: Current consumption in Run
mode, code with data processing running from RAM, Table 31: Current
consumption in Sleep mode, Table 32: Current consumption in Lowpower run mode, Table 33: Current consumption in Low-power sleep
mode, Table 34: Typical and maximum current consumptions in Stop
mode and Table 35: Typical and maximum current consumptions in
Standby mode. Added Figure 14: IDD vs VDD, at TA= 25/55/85/105 °C,
Run mode, code running from Flash memory, Range 2, HSE, 1WS,
Figure 15: IDD vs VDD, at TA= 25/55/85/105 °C, Run mode, code
running from Flash memory, Range 2, HSI16, 1WS, Figure 16: IDD vs
VDD, at TA= 25/55/ 85/105/125 °C, Low-power run mode, code running
from RAM, Range 3, MSI (Range 0) at 64 KHz, 0 WS, Figure 17: IDD
vs VDD, at TA= 25/55/ 85/105/125 °C, Stop mode with RTC enabled
and running on LSE Low drive and Figure 18: IDD vs VDD, at TA=
25/55/85/105/125 °C, Stop mode with RTC disabled, all clocks off.
Updated Table 42: HSE oscillator characteristics and Table 43: LSE
oscillator characteristics. Added Figure 23: HSI16 minimum and
maximum value versus temperature.
Updated Table 53: ESD absolute maximum ratings, Table 55: I/O
current injection susceptibility and Table 56: I/O static characteristics,
and added Figure 24: VIH/VIL versus VDD (CMOS I/Os) and Figure 25:
VIH/VIL versus VDD (TTL I/Os). Updated Table 57: Output voltage
characteristics, Table 58: I/O AC characteristics and Figure 26: I/O AC
characteristics definition.
Updated Table 60: ADC characteristics, Table 62: ADC accuracy, and
Figure 29: Typical connection diagram using the ADC. Updated
Table 64: Temperature sensor characteristics.
Updated Table 70: SPI characteristics in voltage Range 1 and Table 73:
I2S characteristics.
Added Figure 55: Thermal resistance.
29-Apr-2014
122/127
Changes
DocID025938 Rev 6
STM32L051x6 STM32L051x8
Revision history
Table 84. Document revision history (continued)
Date
25-Jun-2014
Revision
Changes
3
Cover page: changed LQFP32 size, updated core speed. updated core
speed, added minimum supply voltage for ADC and comparators.
ADC now guaranteed down to 1.65 V.
Updated list of applications in Section 1: Introduction. Changed number
of I2S interfaces to one in Section 2: Description.
Updated Table 2: Ultra-low-power STM32L051x6/x8 device features
and peripheral counts.
Updated Table 3: Functionalities depending on the operating power
supply range.
Updated RTC/TIM21 in Table 6: STM32L0xx peripherals interconnect
matrix.
Added note related to UFQFPN32 and note related to WLCSP36 in
Table 15: STM32L051x6/8 pin definitions. Split LQFP32/UFQFPN32
pinout schematics into two distinct figures: Figure 7 and Figure 8.
Updated VDDA in Table 23: General operating conditions.
Split Table Current consumption in Run mode, code with data
processing running from Flash into Table 27 and Table 28 and content
updated. Split Table Current consumption in Run mode, code with data
processing running from RAM into Table 29 and Table 30 and content
updated. Updated Table 31: Current consumption in Sleep mode,
Table 32: Current consumption in Low-power run mode, Table 33:
Current consumption in Low-power sleep mode, Table 34: Typical and
maximum current consumptions in Stop mode, Table 35: Typical and
maximum current consumptions in Standby mode, and added Table 36:
Average current consumption during Wakeup.
Updated Table 37: Peripheral current consumption in Run or Sleep
mode and added Table 38: Peripheral current consumption in Stop and
Standby mode.
Updated tLOCK in Table 47: PLL characteristics.
Removed note 1 below Figure 21: HSE oscillator circuit diagram.
Updated Table 49: Flash memory and data EEPROM characteristics
and Table 50: Flash memory and data EEPROM endurance and
retention.
Updated Table 58: I/O AC characteristics.
Updated Table 60: ADC characteristics.
Updated Figure 55: Thermal resistance and added note 1.
DocID025938 Rev 6
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126
Revision history
STM32L051x6 STM32L051x8
Table 84. Document revision history (continued)
Date
05-Sep-2014
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Revision
Changes
4
Extended operating temperature range to 125 °C.
Updated minimum ADC operating voltage to 1.65 V.
Updated Section 3.4.1: Power supply schemes.
Replaced USART3 by LPUART1 and updated I/O structure for PC5
and PC15 pins in Table 15: STM32L051x6/8 pin definitions.
Replaced LPUART by LPUART1 in Table 16: Alternate function port A,
Table 17: Alternate function port B, Table 18: Alternate function port C
and Table 19: Alternate function port D.
Updated temperature range in Section 2: Description, Table 2: Ultralow-power STM32L051x6/x8 device features and peripheral counts.
Updated PD, TA and TJ to add range 3 in Table 23: General operating
conditions. Added range 3 in Table 50: Flash memory and data
EEPROM endurance and retention, Table 83: STM32L051x6/8
ordering information scheme. Update note 1 in Table 27: Current
consumption in Run mode, code with data processing running from
Flash, Table 29: Current consumption in Run mode, code with data
processing running from RAM, Table 31: Current consumption in Sleep
mode, Table 32: Current consumption in Low-power run mode,
Table 33: Current consumption in Low-power sleep mode, Table 34:
Typical and maximum current consumptions in Stop mode, Table 35:
Typical and maximum current consumptions in Standby mode and
Table 39: Low-power mode wakeup timings. Updated Figure 55:
Thermal resistance and removed note 1. Updated Table 60: ADC
characteristics and Table 62: ADC accuracy.
Updated Figure 16: IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Lowpower run mode, code running from RAM, Range 3, MSI (Range 0) at
64 KHz, 0 WS, Figure 17: IDD vs VDD, at TA= 25/55/ 85/105/125 °C,
Stop mode with RTC enabled and running on LSE Low drive,
Figure 18: IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with
RTC disabled, all clocks off.
Updated Table 35: Typical and maximum current consumptions in
Standby mode.
Updated SYSCFG in Table 37: Peripheral current consumption in Run
or Sleep mode.
Updated Table 38: Peripheral current consumption in Stop and Standby
mode and Table 39: Low-power mode wakeup timings.
Updated ACCHSI16 temperature conditions in Table 44: 16 MHz HSI16
oscillator characteristics.
Updated VF(NRST) and VNF(NRST) in Table 59: NRST pin characteristics.
Updated Table 60: ADC characteristics and Table 62: ADC accuracy.
Added range 3 in Table 83: STM32L051x6/8 ordering information
scheme.
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Revision history
Table 84. Document revision history (continued)
Date
08-Sep-2015
Revision
Changes
5
Updated LQFP64, TFBGA64 and LQFP48 pinout/ballout schematics to
highlight pin/ball supplied through VDDIO2.
Updated current consumption in Run mode in Section : Features.
Updated Figure 6: STM32L051x6/8 WLCSP36 ballout and Figure 4:
STM32L051x6/8 TFBGA64 ballout - 5x 5 mm to change bump to top
view. Renamed BOOT1 into nBOOT1. Changed USARTx_RTS into
USARTx_RTS_DE and LPUARTx_RTS into LPUARTx_RTS_DE.
Changed I/O structure to FT for PC15 in Table 15: STM32L051x6/8 pin
definitions
ADC no more available in Low-power run and Low-power Sleep modes
in Table 5: Functionalities depending on the working mode (from
Run/active down to standby).
Updated Figure 7: STM32L051x6/8 LQFP32 pinout (PC14).
Suppressed I2C2_SMBA alternate function for PB12 in Table 15:
STM32L051x6/8 pin definitions and Table 17: Alternate function port B.
In whole Section 6: Electrical characteristics, modified notes related to
characteristics guaranteed by design and by tests during
characterization.
Added ΣIVDDIO2 and updated ΣIIO(PIN) in Table 21: Current
characteristics. Updated Table 20: Voltage characteristics.
Changed temperature condition in Table 8: Internal voltage reference
measured values and Table 25: Embedded internal reference voltage
calibration values.
Updated TCoeff in Table 26: Embedded internal reference voltage.
Updated Figure 16: IDD vs VDD, at TA= 25/55/ 85/105/125 °C, Lowpower run mode, code running from RAM, Range 3, MSI (Range 0) at
64 KHz, 0 WS, Figure 17: IDD vs VDD, at TA= 25/55/ 85/105/125 °C,
Stop mode with RTC enabled and running on LSE Low drive and
Figure 18: IDD vs VDD, at TA= 25/55/85/105/125 °C, Stop mode with
RTC disabled, all clocks off.
Added note related to Standby mode in Table 38: Peripheral current
consumption in Stop and Standby mode.
Updated Table 39: Low-power mode wakeup timings
Updated MSI oscillator temperature frequency drift in Table 46: MSI
oscillator characteristics.
Updated Table 55: I/O current injection susceptibility, Table 56: I/O
static characteristics and Table 58: I/O AC characteristics.
Section : I2C interface characteristics: updated introduction, Table 68:
I2C analog filter characteristics.
updated Figure 32: SPI timing diagram - slave mode and CPHA = 0.
Updated Table 51: EMS characteristics and Table 52: EMI
characteristics.
Added tUP_LDO in Table 60: ADC characteristics.
Added Section : Device marking for LQFP64 and Section : Device
marking for WLCSP36. Updated Section : Device marking for
TFBGA64, Section : Device marking for LQFP48, Section : Device
marking for LQFP32 and Section : Device marking for UFQFPN32.
Updated note below marking schematics in Section 7: Package
information. Added Figure 46: WLCSP36 - 2.596 x 2.868 mm, 0.4 mm
pitch wafer level chip scale package outline.
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Revision history
STM32L051x6 STM32L051x8
Table 84. Document revision history (continued)
Date
17-Mar-2016
126/127
Revision
Changes
6
Updated number of SPIs on cover page and in Table 2: Ultra-lowpower STM32L051x6/x8 device features and peripheral counts.
Changed minimum comparator supply voltage to 1.65 V on cover page.
Added number of fast and standard channels in Section 3.11: Analogto-digital converter (ADC).
Updated Section 3.16.2: Universal synchronous/asynchronous receiver
transmitter (USART) and Section 3.16.4: Serial peripheral interface
(SPI)/Inter-integrated sound (I2S) to mention the fact that USARTs with
synchronous mode feature can be used as SPI master interfaces.
Added baudrate allowing to wake up the MCU from Stop mode in
Section 3.16.2: Universal synchronous/asynchronous receiver
transmitter (USART) and Section 3.16.3: Low-power universal
asynchronous receiver transmitter (LPUART).
In Section 6: Electrical characteristics, updated notes related to values
guaranteed by characterization.
Changed VDDA minimum value to 1.65 V in Table 23: General operating
conditions.
Section 6.3.15: 12-bit ADC characteristics:
– Table 60: ADC characteristics:
Distinction made between VDDA for fast and standard channels;
added note 1.
Added note 4. related to RADC.
Updated fTRIG. and VAIN maximum value.
Updated tS and tCONV.
Added VREF+.
– Updated equation 1 description.
– Updated Table 61: RAIN max for fADC = 16 MHz for fADC = 16 MHz
and distinction made between fast and standard channels.
Added Table 69: USART/LPUART characteristics.
Updated Figure 45: LQFP48 marking example (package top view).
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