ONSEMI MC33157DW

MC33157
Half Bridge Controller and
Driver for Industrial
Linear Tubes
The MC33157 includes the oscillator circuit and two output
channels to control a half–bridge power stage.
One of the channels is ground–referenced. The second one is
floating to provide a bootstrap operation for the high side switch.
http://onsemi.com
Dedicated Driver for Industrial Linear Tubes
• Main oscillator is current controlled, making it easy to set up by a
•
•
•
R ENDSWP
•
•
16
1
SO–16L
DW SUFFIX
CASE 751G
PIN CONNECTIONS AND
MARKING DIAGRAM
VDD
1
16 VHS
+Vref
2
15 VHO
CPH
3
14 VOUT
RPH
4
CSWEEP
5
COP
6
11 GND
ICO
7
10 RESET
DTA
8
9 SD
C SWEEP
R PH
C PH
C OP
R OP
MC33157DW
AWLYYWW
•
•
single external resistor. On top of that, such a feature is useful to
implement a dimming function by frequency shift.
Filament pre–heating time control built–in.
The strike sequence is controllable by external passive components,
the resonnant frequency being independently adjustable. This
frequency can be made different from the pre–heating and the steady
state values. A frequency sweep between two defined values makes
this IC suitable for any series resonnant topologies.
Dedicated internal comparator provides an easy lamp strike detection
implementation.
Digital RESET pin provides a fast reset of the system (less than 10µs).
Both output MOSFET are set to “OFF” state when RESET is zero.
Adjustable dead time makes the product suitable for any snubber
capacitor and size of MOSFET used as power switches.
Designed to be used with standard setting capacitors ≤ 470nF.
A voltage reference, derived from the internal bandgap, is provided
for external usage. This voltage is 100% trimmed at probe level
yielding a 2% tolerance over the temperature range.
12 VLO
V DD
4
5
+Vref
3
Iph
15 V
6
(Top View)
PREHEAT
& STRIKE CONTROL
Iph
Ifstrike
Iop
+Vref
(+7 V)
Latch
Q
CONTROL LOGIC
C
10
HIGH SIDE
BUFFER
LOW SIDE
BUFFER
INHIBIT
 Semiconductor Components Industries, LLC, 1999
November, 1999 – Rev. 1
LEVEL
SHIFTER
Strike Detection
Clear
RESET
ORDERING INFORMATION
+Vref
ENABLE
Dead Time
Vth
R
R
8
Strike 9
Detection
AWL = Manufacturing Code
YYWW = Date Code
2 +Vref
R
+Vref
DT adjust
ICO
ē
UVLO
BAND GAP
REFERENCE
7
COMPARATOR
1
1
Device
Package
Shipping
MC33157DW
Plastic SO–16L
47 Units / Rail
16 VHS
15 VHO
14 VOUT
13 NC
12 VLO
11 GND
Publication Order Number:
MC33157/D
MC33157
MAXIMUM RATINGS
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Rating
Symbol
Value
Unit
VHS
600
V
Differential Max Voltage VHS – VOUT
DVHS
16
V
High Side Output Voltage Range
VHO
VOUT–0.3 to VHS+0.3
V
Low Side Output Voltage Range
VLO
–0.3 to +16
V
Max VHS Allowable Slew Rate
dVHS/dt
±10
V/ns
dVHO/dt, dVLO/dt
±10
V/ns
16
600
140
–40 to +150
V
mW
°C/W
°C
Storage Temperature Range
VDD
PD
RθJA
TJ
Tstg
–65 to +150
°C
Electrostatic Discharge [HBMI]
ESD
2.0
kV
High Side Max Voltage
Max VHO/VLO Allowable Slew Rate
Supply Voltage (Note 1)
Maximum Power Dissipation @ TA = 50°C
Thermal Resistance Junction–to–Air
Operating Junction Temperature
ELECTRICAL CHARACTERISTICS (VDD = 14V. All parameters are specified for –20°C to 85°C ambient temperature
unless otherwise noted.)
Characteristic
Symbol
Min
Typ
Max
Unit
UVON
UVOFF
11
8.0
12
8.5
12.8
9.0
V
V
VCLAMP
15
16
16.5
V
SUPPLY VOLTAGE
Input Threshold Voltage
Turn–On
Turn–Off
Clamp Voltage @ ICLAMP = 10 mA
Supply Current (Note 2)
IS
12
mA
Standby Current at No Load @ VDD < UVOFF
ISTDBY
1.5
mA
Quiescent Current at No Load @ VDD > UVON
IQ
2.5
mA
OUTPUT DRIVERS (VLO, VHO)
High Side VDSON @ Source current = 250 mA
VDS(P)
–
880
1500
mV
Low Side VDSON @ Sink current = 300 mA
VDS(N)
–
880
1500
mV
High Side / Low Side rise time @ COUT = 2 nF
tr
40
ns
High Side / Low Side fall time @ COUT = 2 nF
tf
35
ns
OSCILLATOR
Output Max Frequency
fOSC
Internal Master Clock Duty Cycle
System operation programming recommended values
DC
–
ROP
RPH
RENDSWEEP
RDTA
COP
68
68
68
10
100
50
250
kHz
–
%
560
560
2200
250
560
kW
kW
kW
kW
pF
VCOP High threshold
–
4.2
–
V
VCOP Low threshold
–
2.8
–
V
ICOP discharging current
–
400
–
µA
ICOP over IROP current ratio
–
2.0
–
http://onsemi.com
2
MC33157
ELECTRICAL CHARACTERISTICS (continued) (VDD = 14V. All parameters are specified for –20°C to 85°C ambient temperature
unless otherwise noted.)
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Characteristic
Symbol
Min
Typ
Max
Unit
Preheat timing capacitor pulsed charging current
(Duty Cycle=1/16)
ItPH
14
16
17
µA
Filament preheat time with CPH = 0.47 µF
tPH
–
2.0
–
s
Strike sequence recycling time with CPH = 0.47 µF
tSK
–
125
–
ms
∂
–
1/16
–
Strike sequence restart blanking time with CPH = 470nF
tbk
–
10
–
ms
Dead time: externally adjustable by Rdt
dt
0.3
–
2.5
µs
Dead time adjust resistance (Recommended range)
Rdt
10
–
220
kW
Dead time tolerance
dtTol
TIMING
CPH charging current ratio
±10
%
VOLTAGE REFERENCE
Voltage reference @ ILOAD = 500 µA, TJ = 25°C
VREF
–
7.0
–
V
–
10
–
mV
–
10
–
mV
IREFMAX
–
–
25
mA
VREF
6.85
7.0
7.15
V
Strike detect high voltage threshold
VTHSDHI
–
4.0
–
V
Strike detect low voltage threshold
VTHSDLO
–
3.75
–
V
Maximum current on strike detect input @ Regulation level
ISDHI
–
–
10
nA
Maximum voltage on strike detect @ Regulation level
VSDHI
–
–
7.0
V
DVREF
DVREF
Line regulation @ ILOAD = 500 µA, TJ = 25°C
Load regulation @ ILOAD = 500 µA to 5 mA
Maximum load current
Total VREF variation over Line, Temperature, Load
INPUT
Maximum current on strike detect input @ Low level
ISDLO
–
–
10
nA
VSDNEG
–
–
–0.3
V
Strike detect minimum pulse width
SDPW
50
100
–
ns
RESET high voltage
RSTHI
–
1.8
2.2
V
RESET low voltage
RSTLO
1.6
1.8
–
V
RESET input current @ high voltage
–
–20
–
µA
RESET input current @ low voltage
–
–20
–
µA
RESET maximum voltage
–
–
7.0
V
RESET maximum negative voltage
–
–
–0.3
V
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Maximum strike detect voltage negative input
NOTES:
(1) Since this device has a built–in zener, one cannot use a low impedance supply to drive this pin. Having a current limit mode by external
means is mandatory.
(2) Test Conditions: COUT = 2.2 nF, f = 100 kHz, VDD = 15V.
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3
MC33157
PIN FUNCTION DESCRIPTION
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Pin
Symbol
Function
Description
1
VDD
Supply voltage
input
This pin provides the DC supply to the circuit. The voltage is internally clamped by a zener
connected to the ground. It is NOT allowed to use a DC low impedance power supply to feed this
pin, but limiting the current by an external resistor is mandatory. It is recommended to damp this pin
to ground by an electrolytic capacitor connected close to pin 1.
2
+Vref
Voltage
reference
output
This pin provides a +7V voltage reference derived from the internal bandgap. The +Vref can supply
up to 25 mA and shall be decoupled to ground by a 220nF ceramic capacitor
3
CPH
Preheat timing
capacitor
This capacitor sets two timings: filaments preheat time (tPH) and strike sequence recycle time (tSK).
It is charged with a constant current and cares must be observed to minimize the leakage current
at this pin to get the expected timing. Typically, a 0.47 µF capacitor will give a 2 seconds
pre–heating time and a 125 ms strike sequence recycle time. (See details given by figure 9)
4
RPH
Preheat and
Strike
frequencies
adjustment
resistors
The RPH resistor together with RENDSWEEP and COP defines the frequency used to preheat the
filaments (fPH = f1). RENDSWEEP defines the strike frequency (fENDSWEEP = f2). During the sweep
timing, the frequency will sweep from the high pre–heating f1 to the low strike f2 values. Normally,
f1 is far from the LC resonance but f2 is close enough to generate the high voltage across the
fluorescent tube. (See details given by figure 9)
5
CSWEEP
Frequency
sweep timing
capacitor
This timing define the sweep time from f1 to f2. Since the timing capacitor is charged with a low
constant current, cares must be observed to minimize the leakage current at this pin to get the
expected timing. Since this capacitor is charged through resistor RPH, the voltage rises according
to an exponential and the frequency shifts with the same law.
6
COP
Oscillator
capacitor
7
ICO
Steady state
operating
frequency
adjustment
current input
Since the circuit uses a Current Controlled Oscillator (ICO), the current forced into this pin will
control the operating frequency. The allowable current range is from 1 µA to 500 µA. The +Vref
output can be used to provide the voltage across ROP. An auxiliary voltage source can be used to
implement a dimming function.
8
DTA
Dead Time
Adjust
This pin provides an access to the internal timing system to adjust the dead time between the gate
drive of the High and Low power switches connected, respectively, to pin VHO and VLO.
9
SD
Strike detection
input
This pin drives a comparator, with an internal fixed reference, and acknowledges the tube strike.
When a negative going slope (across the internal reference) is detected, the system considers the
lamp has struck and the oscillator jumps from the present frequency value, which is within the
window defined by RPH and RENDSWEEP to the steady state value defined by ROP. If no negative
going slope is detected on this pin, the system will repeat the sweep and strike sequence four
times, then stops. The circuit will re–start from either a RESET, or by pulling +VDD to ground. The
input signal can be either a logic level or an analog voltage ramping up from zero to +Vref followed
by a negative going slope to zero. In any case, the positive pulse width must be 1 µs minimum. The
pcb layout must be designed to minimize the noise at this pin. (See details given by figures 8, 9, &
10)
10
RESET
Master reset
input
Forcing a logic zero to this pin (HCMOS low level) will reset the circuit, initializing a frequency sweep
and lamp strike sequence. The master reset does not include the pre–heating timing. The minimum
pulse width requested is 10µs to guarantee a reset state. However, this pin has no built in filtering
and a shorter pulse may initialize a reset sequence: it is the responsibility of the designer to make
sure that no noise or parasitic pulse are developed at the RESET input. A full re–start of the
sequence, including the pre–heating time, can be initialized by pulling the +VDD pin to ground. In this
case, +VDD and RESET must be simultaneously released to a high state. When RESET is asserted
low (active) both outputs MOS are biased in the off condition. An internal 20µA pull up current forces
the pin to logic one, allowing the designer to left this pin open if the RESET function is not used. In
order to avoid any uncontrolled state of the output drivers, it is recommended to set up a 10ms low
level at pin 10. The reset is activated in less than 10 microsecond, but releasing this pin while the Vcc
supply is high (above 300V) can generate a random operation, depending upon the dv/dt coming
from the power supply.
This pin defines the steady state operation frequency (f3 = fOP) of the controller. Since this timing
capacitor is charged with a low constant current, cares must be observed to minimize the leakage
current at this pin to get the expected frequency. Film type capacitor are recommended
(polycarbonate).
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4
MC33157
PIN FUNCTION DESCRIPTION (continued)
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Pin
Symbol
Function
Description
11
GND
Ground
(zero voltage
reference)
Since high and fast currents circulate in the circuit, it is mandatory to build a single ground point in
the system.
12
VLO
Low side driver
output
13
NC
Not Connected
14
VOUT
High side
common point /
Half bridge
output
This pin is connected to the output of the half bridge and is referenced for the High side switch.
15
VHO
High side driver
output
This pin provides the VGS to drive the High side power MOSFET.
16
VHS
High voltage
boost supply
The gate drive of the High side switch is derived from this voltage.
This pin provides the VGS to drive the Low side power MOSFET.
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5
MC33157
+Vref
6
Internal
Circuits
2K
COP
External
10 V
ESD
10 V
ESD
Figure 1. PIN 6 COP INPUT
+Vref
ISWP
(8 UA)
IPH
ph/swp Switch
CAN’T READ
3
2K
10 V
ESD
Iblanking
(200 uA)
CPH
(external)
10 V
ESD
Figure 2. PIN 3 CPH INPUT
+Vref
Internal
Circuits
5V
10
2K
0V
10 V
ESD
10 V
ESD
Figure 3. PIN 10 RESET
+Vref
4V
Internal
Circuits
0.0 V
9
2K
10 V
ESD
10 V
ESD
Hysteresis Switch
Figure 4. PIN 9 SD
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6
MC33157
+Vref
8
1
I
I/8
2K
Internal
Circuits
8
10 V
ESD
RDTA
(external)
10 V
ESD
Figure 5. PIN 8 DTA
+Vref
10 V
ESD
2
ROP
(external)
I
2K
7
6
10 V
ESD
2I
10 V
ESD
1 kW
(internal)
COP
(external)
1 kW
(internal)
Figure 6. PIN ICO
+Vref
10 V
ESD
2
ph/swp switch
CSWP
(external)
2K
5
10 V
ESD
10 V
ESD
RENDSWEEP
(external)
RPH
(external)
I
4
10 V
ESD
10 V
ESD
2K
6
2I
1 kW
(internal)
COP
(external)
1 kW
(internal)
Figure 7. PIN 2, 4 & 5 Vref, RPH & CSWP
V
T
w1 ms
SD max
SDHIVth
4 V typ
SDLOVth
3.75 V typ
Internal Hysterisis
t
The Strike Detect is acknowledged as soon as the input
voltage drops below SDLOVth. It is not necessary to pull
the input voltage to zero volt or to a negative bias
SDNEG max
Figure 8. STRIKE DETECTION
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7
MC33157
Rise time
wlms
V DD
U VON
9.2 V typ
U VLO
3.8 V typ
U VLO RESET
7.0 V typ
V ref
tph
V CPH
(PREHEAT)
Frequency
SWEEP
STRIKE
DETECTION
t
w1 m s
STRIKE
F1
F2
F3
FSwp
Output
Frequency OFF STATE
status
FSwp
1
RESET 0
F1
OFF STATE
F2
F3
time
f1 = fPH, preheating frequency adjusted by RPH and RENDSWEEP
f2 = fENDSWEEP, end of sweep frequency, adjusted by RENDSWEEP (pin 2). In any case f1
w f2
f3 = fOP, operating frequency controlled by the ICO current (pin 7) and capacitor COP
tPH = (CPH * 2/3 * Vref) / ( * ItPH)
ē
“OFF” state: High side switch OFF, Low side switch ON
Figure 9. TIMING DIAGRAM (Normal startup sequence and UVLO reset)
w10 ms
1
RESET 0
V CSWP repeats indefinitely
No further logic action activated
+V ref
V CSWP
SD HIGH
STRIKE
DETECTION
Output Frequency
status
F3
SD LOW
FSweep
OFF STATE
F3
time
Previous On state
When RESET pin is released to a logic one, the system jumps to the preheat frequency as defined by RPH,
then executes a frequency sweep down to fENDSWEEP, as defined by RENDSWEEP, and waits until a strike
detection signal is applied to pin 9. There is no preheating timing performed after a reset coming from pin 10.
RESET logic level is CMOS compatible.
Note: Strike detection lever can be either digital – CMOS or analog as depicted here above, as long as the
signal fulfills the SDHIGH and SDLOW values and timing.
OFF STATE: both output MOSFET are biased in the off condition.
Figure 10. TIMING DIAGRAM (External reset)
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8
MC33157
1
RESET 0
End of preheating sequence
Blanking 10 ms typ
@ C PH = 470 nF
+V ref
Blanking
Last restrike valid cycle
V CSWP
tF
V
t FEND
t SK
w+Vref
SD HIGH
SD LOW
STRIKE
DETECTION
Output
Frequency status
F2 F1 FSweep F2 F1 FSweep F2 F1 FSweep
FSweep
F2
F3
time
tSF: Sweep Frequency time. This time is given by the RC network built with CSWEEP and RPH.
tSK: Sweep sequence recycle time. This time is derived by integrating a constant DC current in capacitor
CPH. There is a fixed ratio ( ) between the preheating time tPH and strike sequence recycle time tSK.
tfEND: Time during which f = (fENDSWP). This time is equal to tSK – tSF.
ē
The controller repeats the fSWEEP and the strike sequence until there is a STRIKE signal coming from the external circuit, or until FOUR sequences have been counted.
Following a non strike situation, the controller goes in a full STOP and can be reinitialized by either pulling the VDD pin 1 to ground or by forcing a low to the RESET
pin 9. The controller assumes the lamp has struck when a negative going transient is applied on the STRIKE detection pin 10. On the other hand, in order to avoid false
strike information, the controller force a blank time between the end of tSWEEP and the start of the next sequence.
Figure 11. TIMING DIAGRAM (no strike conditions)
5
4.5
I = V/√ [(R2 + (Lw – 1/Cw)2]
4
I = V/√ [(R2 + (Lw)2]
Z @ RLCF
3.5
2.5
2
1.5
1
0.5
Frequency (F)
Figure 12. OUTPUT = f (freq) @ Lc = 1.5 mH, Cs = 6.8 nF
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9
97000
89000
85000
81000
93000
77000
73000
69000
65000
61000
57000
53000
49000
45000
41000
37000
33000
29000
25000
21000
17000
13000
9000
0
5000
Current (A)
Z = Lw
3
MC33157
+400 V
U1
MC33157
V OUT
12
Np
D3
1N4148
D TA
GND
11
SD
9
C11
RESET
10
Typical Values for FPH = 70 kHz, FOP = 45 kHz, tPH = 2 s, tSWEEP = 125 ms
T1 Np =
R1 390 kW
C1
470 nF/25 V/Polyester
Ns =
R2 62 kW
C2
470 pF/2%/50 ppm
Lp = 150 mH
R3 100 kW – 0.5 W
C3
10 mF/25 V/Electrolytic
Q1 MTP6N60E
R4 100 kW
C4
220 nF/Polyester
Q2 MTP6N60E
R5 82 KW
C5
100 nF/63 V/Polyester
D1 MUR160RL
R6 1 MW
C6
220 nF/25 V/Polyester
D2 MUR120RL
R7 68 KW
C7
6.8 nF/5%/1000 V
D3 1N4148
R8 68 kW
C8
100 nF/400 V/Polyester
U1 MC33157
R9 22 W
C9
100 nF/400 V/Polyester
C10 22 mF/450 V/Electrolytic
C11
100 nF/25 V/Polyester
C12 330 pF/500 V/Polyester
TO SEE: AN1682 (Using the MC33157 Electronic Ballast Controller)
Figure 13. Typical Application Schematic Diagram
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10
22 m F/450 V
100 nF/400 V C9
C7
T1
14
R7
R5
8
Ns
Q2
MTP6N60E
V LO
C SWP
15
100 nF
5
C6
Q1
MTP6N60E
C8
V HO
R1
R2
V HS
R6
C1
16
R8
C2
1
+V REF V DD
100 nF
2
IC
6
0
C OP
3
C PH
4
R PH
C5
7
MUR160
330 pF
D1
R4
C10
R9
C4
100 nF/400 V
R3
C12
C3
10 m F/25 V
MC33157
PACKAGE DIMENSIONS
SO–16L
DW SUFFIX
PLASTIC PACKAGE
CASE 751G–03
ISSUE B
A
D
9
1
8
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INLCUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
h X 45 _
E
0.25
16X
M
T A
S
B
S
14X
e
L
A
0.25
B
B
A1
H
8X
M
B
M
16
q
SEATING
PLANE
T
DIM
A
A1
B
C
D
E
e
H
h
L
q
C
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11
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
10.15
10.45
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC33157
ON Semiconductor and
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12
MC33157/D