PDF Data Sheet Rev. D

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1 GHz to 11 GHz, GaAs, HEMT,
MMIC Low Noise Amplifier
HMC753
Data Sheet
NC
NC
NC
NC
GND
21
20
19
HMC753
18 GND
14 GND
GND 6
13 GND
GND 12
15 GND
GND 5
NC 11
16 RFOUT
GND 4
VDD 10
17 GND
RFIN 3
VGG1 9
GND 2
13494-001
GND 1
22
GND
Noise figure: 1.5 dB at 4 GHz (see Figure 10)
Gain
16.5 dB at 1 GHz to 6 GHz
14 dB at 6 GHz to 11 GHz
Output power for 1 dB compression (P1dB): 18 dBm
at 1 GHz to 6 GHz
Supply voltage (VDD): 5 V at 55 mA
Output third-order intercept (IP3): 30 dBm at 1 GHz to 6 GHz
50 Ω matched input/output (I/O)
24-lead lead frame chip scale package (LFCSP): 16 mm2
23
FUNCTIONAL BLOCK DIAGRAM
24
FEATURES
GND 7
VGG2 8
Product
Overview
Figure 1.
APPLICATIONS
Point to point radios
Point to multipoint radios
Military and space
Test instrumentation
GENERAL DESCRIPTION
The HMC753 is a gallium arsenide (GaAs), monolithic
microwave integrated circuit (MMIC), low noise, wideband
amplifier housed in a leadless, 4 mm × 4 mm LFCSP. The amplifier
operates between 1 GHz and 11 GHz, providing up to 16.5 dB
of small signal gain at 1 GHz to 6 GHz, a 1.5 dB noise figure at
4 GHz (see Figure 10), and an output IP3 of 30 dBm at 1 GHz to
6 GHz, while requiring only 55 mA from a 5 V supply.
Rev. D
The P1dB output power of up to 18 dBm at 1 GHz to 6 GHz
enables the low noise amplifier (LNA) to function as a local
oscillator (LO) driver for balanced, I/Q, or image rejection
mixers. The HMC753 also features I/Os that are dc blocked and
internally matched to 50 Ω, making the device ideal for high
capacity microwave radios or very small aperture terminal (VSAT)
applications.
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Tel: 781.329.4700
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TABLE OF CONTENTS
Features .............................................................................................. 1
Interface Schematics .....................................................................6
Applications ....................................................................................... 1
Typical Performance Characteristics ..............................................7
Functional Block Diagram .............................................................. 1
Theory of Operation .........................................................................9
General Description ......................................................................... 1
Applications Information .............................................................. 10
Revision History ............................................................................... 2
Biasing Procedures ..................................................................... 10
Specifications..................................................................................... 3
Evaluation PCB ........................................................................... 11
Electrical Specifications ............................................................... 3
Outline Dimensions ....................................................................... 13
Absolute Maximum Ratings ............................................................ 4
Ordering Guide .......................................................................... 13
ESD Caution .................................................................................. 4
Pin Configuration and Function Descriptions ............................. 5
REVISION HISTORY
9/15—Rev. 03.0111 to Rev. D
This Hittite Microwave Products data sheet has been reformatted
to meet the styles and standards of Analog Devices, Inc.
Changes to Features Section and General Description Section ...... 1
Changes to Table 1 ............................................................................ 3
Added Table 2; Renumbered Sequentially .................................... 3
Changes to Table 3 ............................................................................ 4
Changes to Table 4 ............................................................................ 5
Added Figure 3, Figure 4, Figure 5, Figure 6, and Figure 7;
Renumbered Sequentially................................................................ 6
Added Theory of Operation Section and Figure 19 .................... 9
Added Applications Information Section, Figure 20, and Biasing
Procedures Section ......................................................................... 10
Changes to Table 5 .......................................................................... 11
Changes to Ordering Guide .......................................................... 13
Rev. D | Page 2 of 13
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HMC753
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
TA = 25°C, VDD = 5 V, IDD = 55 mA.
Table 1.
Parameter
FREQUENCY RANGE
PERFORMANCE
Gain
Gain Variation over Temperature
Noise Figure
Input Return Loss
Output Return Loss
Output Power for 1 dB Compression (P1dB)
Saturated Output Power (PSAT)
Output Third Order Intercept (IP3)
POWER SUPPLY
Supply Current (IDD)
Min
1
Typ
14
16.5
0.004
1.5
11
18
18
20
30
Max
6
2
55
Unit
GHz
Test Conditions/Comments
dB
dB/°C
dB
dB
dB
dBm
dBm
dBm
mA
VDD = 5 V, set VGG2 = 1.5 V, VGG1 = −0.8 V typical
Unit
GHz
Test Conditions/Comments
Table 2.
Parameter
FREQUENCY RANGE
PERFORMANCE
Gain
Gain Variation over Temperature
Noise Figure
Input Return Loss
Output Return Loss
Output Power for 1 dB Compression (P1dB)
Saturated Output Power (PSAT)
Output Third Order Intercept (IP3)
POWER SUPPLY
Supply Current (IDD)
Min
6
Typ
10
14
0.008
2
8
12
15
17
28
Max
11
2.7
55
Rev. D | Page 3 of 13
dB
dB/°C
dB
dB
dB
dBm
dBm
dBm
mA
VDD = 5 V, set VGG2 = 1.5 V, VGG1 = −0.8 V typical
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ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
Drain Bias Voltage
RF Input Power
Gate Bias Voltage
VGG1
VGG2
Channel Temperature
Continuous PDISS (TA) = 85°C), Derate
8.4 mW/°C Above 85°C
Thermal Resistance (Channel to Die Bottom)
Storage Temperature Range
Operating Temperature Range
ESD Sensitivity
Human Body Model (HBM)
Rating
6.0 V
12 dBm
−1 V to +0.3 V
0 V to 2.5 V
180°C
0.8 W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
119°C/W
−65°C to +150°C
−40°C to +85°C
Class 0, Passed
100 V
Rev. D | Page 4 of 13
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HMC753
19 GND
20 NC
21 NC
22 NC
23 NC
24 GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
GND 1
18 GND
GND 2
17 GND
HMC753
GND 4
TOP VIEW
(Not to Scale)
16 RFOUT
15 GND
9
VGG1
GND 12
8
VDD 10
NC 11
7
13 GND
GND
14 GND
GND 6
VGG2
GND 5
NOTES
1. NC = NOT CONNECTED INTERNALLY. THESE PINS ARE
NOT INTERNALLY CONNECTED; HOWEVER, ALL DATA
SHOWN IS MEASURED WITH THESE PINS CONNECTED
EXTERNALLY TO RF/DC GROUND.
2. EXPOSED PAD. THE EXPOSED PAD MUST BE
CONNECTED TO RF/DC GROUND.
13494-002
RFIN 3
Figure 2. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1, 2, 4 to 7, 12 to 15, 17
to 19, 24
3
8, 9
Mnemonic
GND
10
11, 20 to 23
VDD
NC
16
RFOUT
EPAD
RFIN
VGG2, VGG1
Description
Ground. The package bottom has an exposed metal pad that must be connected to RF/dc
ground.
RF Input. This pad is ac-coupled and matched to 50 Ω.
Gate Control for the Amplifier. Follow the biasing procedures described in the Biasing
Procedure section. See Figure 22 for required external components.
Power Supply Voltage for the Amplifier. See Figure 22 for required external components.
Not Internally Connected. These pins are not internally connected; however, all data shown is
measured with these pins connected externally to RF/dc ground.
RF Output. This pad is ac-coupled and matched to 50 Ω.
Exposed Pad. The exposed pad must be connected to RF/dc ground.
Rev. D | Page 5 of 13
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INTERFACE SCHEMATICS
13494-006
13494-003
VDD
GND
Figure 3. GND Interface
Figure 6. VDD Interface
13494-007
RFIN
13494-004
RFOUT
Figure 4. RFIN Interface
13494-005
VGG1, VGG2
Figure 7. RFOUT Interface
Figure 5. VGG1, VGG2 Interface
Rev. D | Page 6 of 13
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HMC753
25
18
15
16
S11
S21
S22
–5
–15
2
4
6
8
10
12
14
FREQUENCY (GHz)
+85°C
+25°C
–40°C
8
13494-008
0
1
3
5
7
9
11
FREQUENCY (GHz)
Figure 8. Broadband Gain and Return Loss (Board Loss Subtracted out for
Gain, Power, and Noise Figure Measurements)
Figure 11. Gain vs. Frequency for Various Temperatures (Board Loss
Subtracted out for Gain, Power, and Noise Figure Measurements)
0
0
+85°C
+25°C
–40°C
+85°C
+25°C
–40°C
–5
RETURN LOSS (dB)
–5
–10
–15
–20
–10
–15
1
3
5
7
9
11
FREQUENCY (GHz)
–25
13494-009
–25
Figure 9. Input Return Loss vs. Frequency for Various Temperatures
1
3
5
7
9
11
FREQUENCY (GHz)
13494-012
–20
Figure 12. Output Return Loss vs. Frequency for Various Temperatures
35
10
+85°C
+25°C
–40°C
8
30
IP3 (dBm)
25
6
20
4
15
2
+85°C
+25°C
–40°C
0
1
3
5
7
FREQUENCY (GHz)
9
11
13494-010
10
Figure 10. Noise Figure vs. Frequency for Various Temperatures (Board Loss
Subtracted out for Gain, Power, and Noise Figure Measurements)
Rev. D | Page 7 of 13
5
1
3
5
7
9
11
FREQUENCY (GHz)
Figure 13. Output IP3 vs. Frequency for Various Temperatures
13494-013
RETURN LOSS (dB)
12
10
–25
NOISE FIGURE (dB)
14
13494-011
5
GAIN (dB)
RESPONSE (dB)
TYPICAL PERFORMANCE CHARACTERISTICS
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25
24
POUT (dBm), GAIN (dB), PAE (%)
20
15
10
+85°C
+25°C
–40°C
7
9
11
FREQUENCY (GHz)
Figure 14. P1dB vs. Frequency for Various Temperatures (Board Loss
Subtracted out for Gain, Power, and Noise Figure Measurements)
–4
–20
–10
–5
22
20
GAIN (dB), P1dB (dBm)
–20
–30
–40
+85°C
+25°C
–40°C
–60
1
3
5
7
9
11
FREQUENCY (GHz)
Figure 15. Reverse Isolation vs. Frequency for Various Temperatures
16
12
3
5
7
9
11
FREQUENCY (GHz)
13494-016
+85°C
+25°C
–40°C
1
6
5
16
4
14
3
12
2
10
1
5.0
0
5.5
Figure 18. Gain, Noise Figure, and Power vs. Supply Voltage (VDD) at 6 GHz
(Board Loss Subtracted out for Gain, P1dB, and Noise Figure Measurements)
20
4
7
P1dB
GAIN
NOISE FIGURE
VDD (V)
24
8
5
18
8
4.5
13494-015
–50
0
Figure 17. Power Compression at 6 GHz (Board Loss Subtracted out for Gain,
Power, and Noise Figure Measurements)
–10
ISOLATION (dB)
–15
INPUT POWER (dBm)
0
PSAT (dBm)
4
13494-017
5
13494-014
3
8
0
0
1
12
NOISE FIGURE (dB)
5
16
13494-018
P1dB (dBm)
20
POUT
GAIN
PAE
Figure 16. PSAT vs. Frequency for Various Temperatures (Board Loss
Subtracted out for Gain, Power, and Noise Figure Measurements)
Rev. D | Page 8 of 13
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THEORY OF OPERATION
The circuit architecture of the HMC753 wideband, low noise
amplifier is shown in Figure 19. The HMC753 uses a single gain
stage to form an amplifier with typical gain of 16.5 dB at 1 GHz
to 6 GHz and 14 dB at the 6 GHz to 11 GHz frequency band.
HMC753
Both RF input and RF output ports have on-chip dc block
capacitors, which eliminates the need for external ac coupling
capacitors.
It is critical to supply very low inductance ground connections
to the ground pins as well as to the backside exposed paddle.
This ensures stable operation.
RFOUT
13494-022
RFIN
The input and output impedances are sufficiently stable over
variations in temperature and supply voltage that no impedance
matching compensation is required.
Figure 19. Wideband Low Noise Amplifier Circuit Architecture
The HMC753 has single-ended input and output ports whose
impedances are nominally equal to 50 Ω over the frequency
range of 1 GHz to 11 GHz. Consequently, the HMC753 can be
directly inserted into a 50 Ω system with no impedance
matching circuitry required. In addition, multiple HMC753
amplifiers can be cascaded back to back without the need of
external matching circuitry.
To achieve the best performance out of the HMC753 and not to
damage the device, the recommended biasing sequence must be
followed; see the Applications Information section for further
details.
Rev. D | Page 9 of 13
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APPLICATIONS INFORMATION
The HMC753 is a GaAs, MMIC, high electron mobility
transistor (HEMT), low noise, wideband amplifier.
BIASING PROCEDURES
The amplifier uses two field effect transistors (FETs) in series,
source to drain. The basic schematic for a fundamental cell is
shown in Figure 20.
VDD
RFOUT
VGG2
The recommended biasing procedure during power-up is as
follows:
1.
2.
3.
4.
5.
6.
VGG1
13494-021
RFIN
Connect GND.
Set VGG1 to −1 V.
Set VDD to 5 V.
Set VGG2 to 1.5 V.
Increase VGG1 to achieve a typical quiescent current (IDQ) =
55 mA.
Apply the RF signal.
The recommended biasing procedure during power-down is as
follows:
Figure 20. Fundamental Cell Schematic
All measurements for this device are taken using the evaluation
printed circuit board (PCB) in its default configuration.
1.
2.
3.
4.
5.
Turn off the RF signal.
Decrease VGG1 to −1 V to achieve IDQ = 0 mA.
Decrease VGG2 to 0 V.
Decrease VDD to 0 V.
Increase VGG1 to 0 V.
The VDD = 5 V and IDQ = 55 mA bias conditions are the operating
points recommended to optimize the overall performance.
Unless otherwise noted, the data shown is taken using the
recommended bias conditions. Operation of the HMC753 at
different bias conditions may result in performance that differs
from the Typical Performance Characteristics shown in the data
sheet. Biasing the HMC753 for higher drain current typically
results in higher P1dB and output IP3 at the expense of
increased power consumption.
Rev. D | Page 10 of 13
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HMC753
EVALUATION PCB
J5
J6
H753
XXXX
C3
C1
GND
J3
VGG2
U1
C7
C8
J2
VGG1
J1
13494-020
C9
J4
C4
C5C2
C6
VDD
VGG1
20
19
22
18
2
17
3
16
4
15
C9
4.7µF
C6
1000pF
C3
100pF
C8
4.7µF
C5
1000pF
C2
100pF
11
12
9
13
10
14
6
8
5
RFOUT
C1
100pF
C4
1000pF
Figure 22. Typical Application Circuit
Rev. D | Page 11 of 13
C7
4.7µF
VDD
13494-019
VGG2
21
24
1
7
RFIN
23
Figure 21. 122826-HMC753LP4E Evaluation PCB
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Table 5. List of Materials for Evaluation PCB
122826-HMC753LP4E1
Item
J5, J6
J1 to J4
C1 to C3
C4 to C6
C7 to C9
U1
PCB2
Discussion
Description
SMA connectors
DC pins
100 pF capacitors, 0402 package
10,000 pF capacitors, 0603 package
4.7 µF capacitors, tantalum
HMC753 amplifier
122824-2 evaluation PCB
It is recommended that the circuit board used in this application
use RF circuit design techniques. It is also recommended that
signal lines have a 50 Ω impedance, and the package ground
leads and exposed pad be connected directly to the ground
plane, as shown in Figure 22. Use a sufficient number of via
holes to connect the top and bottom ground planes. Mount the
evaluation board to an appropriate heat sink. The evaluation
circuit board shown is available from Analog Devices, Inc.,
upon request.
Reference this number when ordering the complete evaluation PCB.
Circuit board material: Rogers 4350 or Arlon 25FR.
Rev. D | Page 12 of 13
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HMC753
OUTLINE DIMENSIONS
4.10
4.00 SQ
3.90
PIN 1
INDICATOR
0.31
0.25
0.19
1
18
0.50
BSC
2.85
2.70 SQ
2.55
EXPOSED
PAD
13
0.95
0.85
0.75
0.50
0.40
0.30
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
PKG-000000
SEATING
PLANE
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
08-07-2015-A
TOP VIEW
PIN 1
INDICATOR
24
19
Figure 23. 24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
4 mm × 4 mm Body, Very Thin Quad
(HCP-24-3)
Dimensions shown in millimeters
ORDERING GUIDE
Model
HMC753LP4E
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package Option
HCP-24-3
HMC753LP4ETR
24-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
HCP-24-3
122826-HMC753LP4E
Evaluation Board
1
XXXX is the 4 digit lot number.
©2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13494-0-9/15(D)
Rev. D | Page 13 of 13
Package Marking1
753
XXXX
753
XXXX