Schematic drawing for Smart Gateway 857 base board

A
4
3
IRQ
===
IRQ0#
IRQ1#
IRQ2#
IRQ3#
IRQ4#
IRQ5#
IRQ6#
IRQ7#
CS
==
CS0#
CS1#
CS2#
CS3#
CS4#
CS5#
CS6#
CS7#
B
UNUSED
MPC180
UNUSED
ADSL
DSP SODIMM
ALCATEL ADSL nGASP-INT
Analong Line Card
MII-TX_CLK
Port A (PA0 - PA15)
===================
PA0, 1
PA4
PA6
PA7
PA8
PA9
PA12
PA13
PA14
PA15
FLASH
MPC180
ADSL
Analong Line Card
DSP SODIMM
SDRAM
Used by PCMCIA_B as CE1_B
Used by PCMCIA_B as CE2_B
Port B (PB14 - PB31)
====================
PB14
PB15
PB16
PB17
PB18
PB19
PB20
PB21
PB22
PB23
PB24
PB25
PB26
PB27
PB28
PB29
PB30
SPICLK
GPCM
=====
ADSL
UPM
===
UPMB
SDRAM
SPLL Reset Configuration
========================
MODCK[1,2] = 10; 1:1 ext. CLK (40/50MHz)
2
Power-On Configuration word
===========================
IIP = 1:Exception Prefix=0x000n_nnnn
BPS = 00:32-bit port size
ISB = 10:0xFF000000
PCMCIA
======
A
B
SW. HUB:MII
PCMCIA
IDMA
====
1(PC15)
2(PC14)
Used by UTOPIA
Shared by PCMCIA & MPC180
C
D
SCC1
===
10M Ethernet mode
Port C (PC4 - PC15)
===================
PC4
PC5
PC6
PC10
PC11
PC12
PC13
PC14
PC15
1
E
NOTE:
VCC = 5 V
VDD = 3. 3V
VCORE= 1. 8V
TIMER 4
ETH_RX_CLK
ETH_TX_CLK
Not used
Not used
Not used
ALC/CH3 RINGING
ALC/CH3 REVPOL
ETH_TXD
ETH_RXD
Port D (PD3 - PD15)
===================
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
SPARE1 (CRS)
SPARE2 (MDIO)
SPARE3 (TX_EN)
SPARE4 (COL)
ETH_LOOP
UTOPIA
ETPFLDL
ETPSQEL
ALC/CH2 RINGING
ETH_TENA
UTOPIA
UTOPIA
ALC/CH0 RINGING
RS232 EXT. SYNC. I/P
RS232 RXD
RS232 TXD
ADSL CONN
ALC CONN
ALC/SPIMISO
ALC/SPIMOSI
ALC/CH0 REVPOL;
4
UTOPIA
UTOPIA
UTOPIA
UTOPIA
UTOPIA
ALC/CH2 REVPOL
UTOPIA
UTOPIA
UTOPIA
UTOPIA
UTOPIA
UTOPIA
UTOPIA
SW. HUB:MII
Unused
SW. HUB:MII
SW. HUB:MII
3
DATA Buffer (D0~D15)
====================
1. PCMCIA
2. DSP SODIMM
3. Analong Line Card(DTMF Receiver)
4. Chip-Select Decoders
5. ADSL
2
*Connect to 860 Data Bus directly*
1. Flash EEprom
2. SDRAM
3. MPC180
Not used
Reserved I/O
Reserved I/O
ETH_RENA
ETH_CLSN
ALC/CH1 RINGING
ALC/CH1 REVPOL
IDMA2
UTOPIA
Address Buffer (A8~A31)
========================
1. DSP SODIMM
2. Flash EEprom
3. Analog Line Card
4. ADSL
1
Title
MPC857T IAD Platform
Size
B
Date:
A
B
C
D
Document Number
APPENDIX
Tuesday, November 12, 2002
Rev
0.2a
Sheet
E
1
of
19
A
B
PWR-ON-RESET CLOCK
VDD
MODCK setting is made configurable for testing purposes.
Default state (with no jumpers set) is for 1:1 operation.
CONFIGURATION
VDD
C
D
E
Rev. 0.2a
MPC857 50MHz OSC
========= CLK distribution =========
* EXTCLK.CPU derives from OSC directly
* CLKOUT.CPU distributes to:
1. SDRAM X 2
2. MPC 180
3. ADSL Connector
VDD
Note: 3.3V Oscillator should be used
PORESET#
G19
2
3
MODCK1
4
OSC 50MHz
12
10K
VDD
4
R129
1
C216
0.1uF
4
<3,6>
R106
5
<6,9>
6
MODCK2
4
<6,9>
VDD
3
OSC
EXTCLK
<6>
0R0
12
G18
Rev. 0.2a
U53A
U36
MC74LCX125DT
10K
MC74LCX125DT
C153
0.1uF
U53B
R130
Rev. 0.2a
VDD
POWER ON RESET
CIRCUIT
D[0..15]
RESET CONFIGURATION
U45A
IN
RESET
1
1
GND
2
D[0..15]
VDD
R118
10k
U44
VDD
<3,4,6,8,10>
+
C202
10uF
1
MC74LCX14D
2
PORESET#
RSTCONF#
3
R108
10K
<3,6>
MC74ACT05D
R119
10K
G15
4
MC34164D-3
2
<6>
Rev. 0.2a
R122
10K
U49A
12
3
VDD
D14: High for Half
Speed bus
VDD
C206
0.1uF
HRESET
CIRCUIT
VCC
VCC
2
4
6
8
11
13
15
17
R120
10k
2
10K
10K
U45B
<3,4,6,9>
<6,10>
U49B
S1
3
4
3
4
HRESET#
<6,10,11,12,18>
WE0#
WR#
<6,10,11,12,18>
1
19
HRESET#
Tact SW.
C157
10uF
+
MC74LCX14D
MC74ACT05D
PLL CIRCUIT
VDD
<6>
L9
1
VDDSYN
<6>
8.2mH
1206
C167
0.1uF
+
XFC
VSSSYN
<6>
FRZ
Rev. 0.2a
VSSSYN1
<6>
<6,10,11,12,18>
<3,6>
33nF
VDD
R125
10K
HRESET#
R110
10
C166
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1G
2G
VDD
TRST#
PORESET#
<6>
<6>
VSSSYN
<3,6>
NOTE:
HRESET# pulled up
at the HRESET
circuit
VDD VDD
B
D1
D7
D14
VDD
ONCE_TRST#
BWE0#
BWR#
VDD
<11>
2
<18>
<8,9,11,18>
C205
0.1uF
C212
0.1uF
20
R132
100
R126
10K
VDD
R134
10K
BACKGROUND DEBUG MODE (BDM)
PORT
R128
10K
J6
1
3
5
7
9
SRESET#
DSCK
FRZ
DSDI
DSDO
2
4
6
8
10
CON10A
R133
R127
1K
NOTE:
Solder either R133 (default) or R134 to
DSDI for different development mode
m
1
Title
MPC857T IAD Platform
Size
B
Date:
C
<6>
<6>
<6>
<6>
<6>
10K
R123
A
18
16
14
12
9
7
5
3
MC74LCX244DT (TSSOP)
VDD
MPC857
C204
0.1uF
Rev. 0.2a
U46
R121
C169
10uF
VDD
D
Document Number
Rev
0.2a
Misc.
Tuesday, November 12, 2002
Sheet
E
2
of
19
A
B
<8,11,16>
C
D
E
BA[0..31]
U56
4
Rev. 0.2a
BA29
BA28
BA27
BA26
BA25
BA24
BA23
BA22
BA21
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
32-Bit Fl ash
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
10
13
<6>
CS0#
<2,4,6,9>
<4,6,11,18>
VDD
WE0#
OE#
26
11
28
37
3
VDD
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
(A19)
(A20)
NC2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
RESET
RY/BY
BYTE
(WP/ACC)
CE
WE
OE
VSS2
VSS1
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
12
15
47
14
PORESET#
4
VDD
<2,6>
46
27
3
VCC
AM29LV320DT90EI
C211
0.1uF
C220
0.1uF
U48
Rev. 0.2a
BA29
BA28
BA27
BA26
BA25
BA24
BA23
BA22
BA21
BA20
BA19
BA18
BA17
BA16
BA15
BA14
BA13
BA12
BA11
BA10
BA9
2
25
24
23
22
21
20
19
18
8
7
6
5
4
3
2
1
48
17
16
9
10
13
<6>
CS0#
<4,6,9>
<4,6,11,18>
VDD
WE2#
OE#
26
11
28
37
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
(A19)
(A20)
NC2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15/A-1
RESET
RY/BY
BYTE
(WP/ACC)
CE
WE
OE
VSS2
VSS1
29
31
33
35
38
40
42
44
30
32
34
36
39
41
43
45
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
12
15
47
14
PORESET#
2
VDD
<2,6>
46
27
VCC
AM29LV320DT90EI
D[0..31]
<2,4,6,8,10>
1
1
m
Title
MPC857T IAD Platform
Size
B
Date:
A
B
C
D
Document Number
Flash EEprom
Tuesday, November 12, 2002
Rev
0.2a
Sheet
E
3
of
19
A
<2,3,6,8,10>
B
D[0:31]
C
D
E
D[0:31]
VDD
Rev. 0.2a
<6,10,18>
U38
38
37
CLKOUT
4
<6>
CS5#
<3,6,11,18>
<6>
<6>
OE#
GPL_A2#
GPL_A3#
<6>
<6,8,9,10,18>
GPL_A0#
A[0:31]
<2,3,6,9>
<6,9>
A[0:31]
CS5#
19
OE#
GPL_A2#
18
17
GPL_A3#
16
39
15
WE0#
WE1#
3
A18
GPL_A0#
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
36
35
22
34
33
32
31
30
29
26
25
24
23
A8
BA1
20
21
28
41
54
CLK
CKE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CS
RAS
CAS
WE
UDQM
LDQM
NC
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
BA0
BA1
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
53
51
50
48
47
45
44
42
13
11
10
8
7
5
4
2
40
4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
VDD
1
14
27
3
9
43
49
3
VDD
6
12
46
52
C175
0.1uF
C180
0.1uF
C183
0.1uF
C190
0.1uF
C201
0.1uF
K4S281632C
Decoupling Cap
VDD
VDD
U39
38
37
2
<3,6,9>
<6,9>
CS5#
19
OE#
GPL_A2#
18
17
GPL_A3#
16
39
15
WE2#
WE3#
A18
GPL_A0#
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
G14 Rev. 0.2a
G13
21
21
A7
A9
1
A8
BA1
36
35
22
34
33
32
31
30
29
26
25
24
23
20
21
28
41
54
CLK
CKE
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
CS
RAS
CAS
WE
UDQM
LDQM
NC
A11
A10/AP
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
NC
VDD
VDD
VDD
VDDQ
VDDQ
VDDQ
VDDQ
BA0
BA1
VSSQ
VSSQ
VSSQ
VSSQ
VSS
VSS
VSS
53
51
50
48
47
45
44
42
13
11
10
8
7
5
4
2
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
40
VDD
C176
0.1uF
C179
0.1uF
C200
0.1uF
2
1
14
27
3
9
43
49
6
12
46
52
1
m
Title
K4S281632C
MPC857T IAD Platform
Size
B
Date:
B
C191
0.1uF
Decoupling Cap
BA0&BA1 Selection:
A7,A8 for 32MByte(K4S281632 X 2)
A9,A8 for 16MByte(K4S641632 X 2)
A
C184
0.1uF
C
D
Document Number
Rev
0.2a
SDRAM
Tuesday, November 12, 2002
Sheet
E
4
of
19
A
B
C
D
E
4
4
VDD
C171
+
C148
0.1uF
+
3
C173
C174
10uF
3
25
+
24
10uF
PB24
<6>
PB23
<6>
PB25
C5+
C2+
C5-
C2-
C1+
RIMON
C1STB
22
21
20
18
16
19
17
15
DO1
DO2
DO3
DO4
DO5
RX1
RX2
RX3
RX4
RX5
DI1
DI2
DI3
TX1
TX2
TX3
28
+
26
C172
10uF
3
4
6
7
8
9
11
13
5
9
4
8
3
7
2
6
1
10
12
14
P2
VSS
<6>
VEE
U40
1
23
10uF
CON_DB9 (Female DB9)
5
MC145583VF
2
2
C198
10uF
C193
0.1uF
+
1
1
m
Title
MPC857T IAD Platform
Size
B
Date:
A
B
C
D
Document Number
Rev
0.2a
Console Port
Tuesday, November 12, 2002
Sheet
E
5
of
19
A
B
C
D
E
Pull Hign Resistors
D[0..31]
4
<2,3,4,8,10>
D[0..31]
<4,8,9,10,18>
A[0..31]
4
R107
SRESET#
R116
IRQ0#
R98
IRQ1#
R103
IRQ2#
R101
3
<18>
IRQ3#
<11>
IRQ4#
R117
R113
IRQ5#
R111
<14>
IRQ6#
<12>
IRQ7#
R115
R95
SPARE2
R91
<2,10>
WR#
R114
IP_A5
Rev. 0 .2a
i.e.: Ad ded a
termina tion
resistor . Put
closer to
857.
2
<4,10,18>
47 <2>
<12>
<2,9>
<2,9>
U53D
MC74LCX125DT
11
<2>
<2>
<2,3>
<2>
12
EXTCLK
TEXP
OP0
OP1
MODCK2
MODCK1
TMS
DSDI
DSCK
TRST#
DSDO
A8
H19
M1
W8
P15
T14
P5
N5
M5
13
BCLKOUT
XFC
CLKOUT
P1
N1
T2
W3
N2
N3
L4
L2
M4
L1
G18
H17
H16
G19
G17
IP_B0/IWP0/VFLS0
IP_B1/IWP1/VFLS1
IP_B2/IOIS16_B/AT2
IP_B3/IWP2/VF2
IP_B4/LWP0/VF0
IP_B5/LWP1/VF1
IP_B6/DSDI/AT0
IP_B7/PTR/AT3
ALE_B/DSCK/AT1
WAIT_B
PC4/CD4/L1RSYNCA
PC5/CTS4/L1TSYNCA/SDACK1
PC6/CD3/L1RSYNCB
PC7/CTS3/L1TSYNCB/SDACK2
PC8/CD2/TGATE2
PC9/CTS2
PC10/CD1/TGATE1
PC11/CTS1
PC12/L1RQA/L1ST4
PC13/L1RQB/L1ST3
PC14/DREQ1/RTS2/L1ST2
PC15/DREQ0/RTS1/L1ST1
KAPWR
PD3/REJECT4 {TXD[1]}
PD4/REJECT3 {TXD[2]}
PD5/REJECT2 {TXD[3]}
PD6/RTS4 {RX_DV}
PD7/RTS3 {RX_ER}
PD8/TXD4 {RX_CLK}
PD9/RXD4 {TXD[0]}
PD10/TXD3 {RXD[0]}
PD11/RXD3 {TX_ER}
PD12/L1RSYNCB {MDC}
PD13/L1TSYNCB {RXD[1]}
PD14/L1RSYNCA {RXD[2]}
PD15/L1TSYNCA {RXD[3]}
SPARE1 {CRS}
SPARE2 {MDIO}
SPARE3 {TX_EN}
SPARE4 {COL}
XTAL
EXTAL
XFC
CLKOUT
EXTCLK
TEXP
OP0
OP1
OP3/MODCK2/DSDO
OP2/MODCK1/STS
TMS
TDI/DSDI
TCK/DSCK
TRST
TDO/DSDO
<8,9>
<8,9>
<4>
<8,11>
<8,16>
<8,18>
<10>
<3>
<15,17 >
CS7#
<5>
CS6#
<5>
CS5#
<5>
<18 >
CS4#
<15>
CS3#
<15 >
CS2#
<15 >
CS1#
<15,17
CS0#>
<11,15,16,18PB>14
<11,18
PB>15
<11,18
PB>16
PB 17
PB 18
PB>19
<15,17
PB>20
<15,17
PB>21
<18
PB>22
<18
PB 23
PB24
<18 >
PB
<1825>
PB
<1826>
PB
27
<18>
PB 28
<15,17
>
PB
<1829>
PB
30
<18>
PB31
<18 >
PA 0
PA 1
PA 2
PA 3
PA4
PA 5
PA 6
PA7
PA 8
PA 9
PA 10
PA 11
PA 12
PA13
<15
>
PA 14
<16
>
PA 15
<18>
U19
T19
R18
P17
P19
N18
M17
M19
L17
K18
J17
G16
F17
E17
D17
C18
C4
D5
B4
A4
E4
D4
A2
C3
CS7/CE(2)B
CS6/CE(1)B
CS5
CS4
CS3
CS2
CS1
CS0
CE1_A
CE2_A
IP_A0
IP_A1
IP_A2/IOIS16_A
IP_A3
IP_A4
IP_A5
IP_A6
IP_A7
ALE_A
WAIT_A
VDDSYN
VSSSYN
VSSSYN1
VDDL
VDDL
VDDL
VDDL
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
E5
E6
E7
E8
E9
E10
E11
E12
E13
E14
E15
G15
H15
J15
K15
L15
M15
N15
L5
K5
J5
H5
G5
R15
R14
R13
R12
R11
R10
R9
F5
F15
U37
MPC857T BGA
U18
R17
N16
P18
N17
N19
L16
K16
L19
K17
J18
J16
F19
E19
D19
E16
C19
C17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A1 1
A1 2
A1 3
A1 4
A1 5
A1 6
A1 7
A1 8
A1 9
A20
A2 1
A2 2
A2 3
A2 4
A2 5
A2 6
A2 7
A2 8
A2 9
A30
A3 1
R112
<2>
Rev. 0 .2a
BR
BG
BB
TSIZ0/REG
TSIZ1
RD/WR
BURST
BI
BDIP/GPL_B5
TS
TA
TEA
AS
RSV/IRQ2
KR/RETRY/IRQ4/SPKROUT
CR/IRQ3
DP0/IRQ3
DP1/IRQ4
DP2/IRQ5
DP3/IRQ6
FRZ/IRQ6
IRQ0
IRQ1
IRQ7 {TX_CLK}
WE0/BS_B0/IORD
WE1/BS_B1/IOWR
WE2/BS_B2/PCOE
WE3/BS_B3/PCWE
BS_A0
BS_A1
BS_A2
BS_A3
GPL_A0/GPL_B0
OE/GPL_A1/GPL_B1
GPL_A2/GPL_B2/CS2
GPL_A3/GPL_B3/CS3
UPWAITB/GPL_B4
UPWAITA/GPL_A4
GPL_A5
PORESET
RSTCONF
HRESET
SRESET
RSTRT1/PB14
BRGO3/PB15
L1RQA/L1ST4/PB16
L1RQB/L1ST3/PB17
RTS2/L1ST2/PB18
RTS1/L1ST1/PB19
SMRXD2/L1CLKOA/PB20
SMTXD2/L1CLKOB/PB21
SMSYN2/SDACK2/PB22
SMSYN1/SDACK1/PB23
PB24/SMRXD1
PB25/SMTXD1
PB26/I2CSCL/BRGO2
PB27/I2CSDA/BRGO1
SPIMISO/BRGO4/PB28
SPIMOSI/PB29
RSTRT2/SPICLK/PB30
SPISEL/REJECT1/PB31
R109
G4
E2
E1
B9
C9
B2
F1
E3
D2
F3
C2
D1
L3
H3
K1
F2
V3
V5
W4
V4
G3
V14
U14
W15
C7
A6
B6
A5
D8
C8
A7
B8
D7
C6
B5
C5
B1
C1
D3
R2
P3
N4
P2
CLK8/TOUT4/L1TCLKB/PA0
CLK7/TIN4/BRGO4/PA1
CLK6/TOUT3/L1RCLKB/BRGCLK2/PA2
CLK5/TIN3/BRGOUT3/PA3
CLK4/TOUT2/PA4
CLK3/TIN2/L1TCLKA/BRGOUT2/PA5
CLK2/TOUT1/BRGCLK1/PA6
CLK1/TIN1/L1RCLKA/BRGO1/PA7
L1RXDA/PA8
L1TXDA/PA9
L1RXDB/PA10
L1TXDB/PA11
TXD2/PA12
RXD2/PA13
TXD1/PA14
RXD1/PA15
AS#
<10>
BR#
BG#
BB#
REG#
TSIZ1
10K
<2,10>
WR#
<10>
BURST#
10K
BI#
BDIP#
10K
<10,18> TS#
<10,18> TA#
10K
TEA#
AS#
10K
IRQ2#
RETRY#
10K
<18> IRQ3#
DP0
10K
<11> IRQ4#
IRQ5#
10K
<14> IRQ6#
<2> FRZ
10K
IRQ0#
<10> IRQ1#
10K
<12> IRQ7#
<2,3,4,9> WE0#
<4,9> WE1#
<3,4,9> WE2#
10K
<4,9> WE3#
BS_A0#
10K
BS_A1#
BS_A2#
BS_A3#
<4>
GPL_A0#
10K
<3,4,11,18>
OE#
<4>
GPL_A2#
<4>
GPL_A3#
GPL_B4#
GPL_A4#
GPL_A5#
<2,3> PORESET#
<2> RSTCONF#
<2,10,11,12,18>
HRESET#
<2> SRESET#
<9>
WAIT_A#
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
10K
W14
W12
W11
W10
W13
W9
W7
W6
U13
T11
V11
U11
T13
V13
V10
T10
U10
T12
V9
U9
V8
U8
T9
U12
V7
T8
U7
V12
V6
W5
U6
T7
10K
R104
BI#
BR#
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
10K
R105
Rev. 0 .2a
K4
M2
M3
10K
R97
BADDR30/REG
BADDR29
BADDR28
1K
R100
TEA#
B3
A3
T5
T4
U3
W2
U4
U5
T6
T3
K2
R3
CE1_A#
CE2_A#
IP_A0
IP_A1
IP_A2
IP_A3
IP_A4
IP_A5
IP_A6
IP_A7
ALE_A
WAIT_A#
<12>
<12>
<12>
<12>
<12>
<12>
<12>
H2
J3
J2
G1
G2
J4
K3
H1
J1
R4
T17
T18
R19
M16
M18
L18
K19
J19
F18
E18
D18
D16
R1
VFLS0
VFLS1
AT2
VF2
VF0
VF1
AT0
AT3
AT1
WAIT_B#
PC4
PC5
PC6
PC7
PC8
PC9
PC10
PC11
PC12
PC13
PC14
PC15
VDD
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<11,15,18>
<18>
<18>
T1
U1
V1
VDDSYN
VSSSYN
VSSSYN1
W16
U16
U15
V16
T15
W17
V17
W18
T16
R16
V18
V19
U17
B7
H18
V15
H4
PD3
PD4
PD5
PD6
PD7
PD8
PD9
PD10
PD11
PD12
PD13
PD14
PD15
SPARE1
SPARE2
SPARE3
SPARE4
R8
R7
R6
R5
P16
F16
F4
P4
<12>
<12>
3
<18>
<18>
<15,17>
<15,17>
<9,10>
<18>
<2>
<2>
<2>
<18>
<18>
<18>
<18>
<18>
<15,17>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<12>
2
<12>
<12>
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
10K
R93
TA#
B19
B18
A18
C16
B17
A17
B16
A16
D15
C15
B15
A15
C14
B14
A14
D12
C13
B13
D9
D11
C12
B12
B10
B11
C11
D10
C10
A13
A10
A12
A11
A9
<10,18>
F6
F7
F8
F9
F10
F11
F12
F13
F14
G6
G7
G8
G9
G10
G11
G12
G13
G14
H6
H7
H8
H9
H10
H11
H12
H13
H14
J6
J7
J8
J9
J10
J11
J12
J13
J14
K6
K7
K8
K9
K10
K11
K12
K13
K14
L6
L7
L8
L9
L10
L11
L12
L13
L14
M6
M7
M8
M9
M10
M11
M12
M13
M14
N6
N7
N8
N9
N10
N11
N12
N13
N14
P6
P7
P8
P9
P10
P11
P12
P13
P14
R102
TS#
BB#
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
A31
10K
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
<10,18>
R99
BADDR30
BADDR29
BADDR28
VDD
VDD
1
1
VDD
m
C129
0.1uF
C147
0.1uF
C170
0.1uF
C182
0.1uF
C168
0.1uF
C160
0.1uF
C127
0.1uF
C134
0.1uF
C178
0.1uF
C146
0.1uF
C144
0.1uF
C159
0.1uF
C130
0.1uF
C126
0.1uF
C145
0.1uF
C177
0.1uF
Title
MPC857T IAD Platform
Decoupling Cap
Size
Document Number
Custom
MPC857T BGA
Date:
A
B
C
D
Rev
0.2a
Tuesday, November 12, 2002
Sheet
E
6
of
19
A
B
C
D
E
Rev. 0.2a
3.3VDC
4
MIC29502BU (TO-263)
4
VDD
A3V3_ETH
L2
2
C18
+
C21
10uF
5
C32
+
C50
+
10uF
C34
10uF
0.1uF
1
C51
R7
480
0.1uF
R4
300
3
C12 0.1uF
10uF
0.1uF
ADJ
FB 0805
4
2
C13
Floppy CON
IN
+
VOUT
GND
IN
2
1
1
2
3
4
ps. Remember to
cut the back
holder.
U12
VCC
1
12V
J1
3
3
1.8VDC
1
12V
2
C17
C7
0.1uF
VCORE
U11 MIC29302BU/MIC29152BU (TO-263)
VCC
+
C20
10uF
IN
VOUT
3
1000U/25V
IN
GND
Rev. 0.2a
ADJ
5
R10
800
R11
330
12V
4
R6
150
+
C31
0.1uF
R3
300
C33
VCC
R12
10uF
220
LED-Y
D3
0
LED-Y
D4
VDD
R13
VCORE
D1
LED-Y
D2
LED-Y
2
2
3
VCC
12V
2
4
1
5
JP1
CIRDIN_5-P(Female)
1
1
m
Title
MPC857T IAD Platform
Size
B
Date:
A
B
C
D
Document Number
Rev
0.2a
POWER
Tuesday, November 12, 2002
Sheet
E
7
of
19
A
B
C
D
E
U42
D[0..31]
4
D0
D1
D2
D3
D4
D5
D6
D7
2
3
5
6
8
9
11
12
D8
D9
D10
D11
D12
D13
D14
D15
13
14
16
17
19
20
22
23
1
48
CS_BUF#
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1DIR
1OE/
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2DIR
2OE/
47
46
44
43
41
40
38
37
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
36
35
33
32
30
29
27
26
24
25
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
BD[0..31]
<9,11,14,18>
<4,6,9,10,18>
A[8..31]
U55
A31
A30
A29
A28
A27
A26
A25
A24
2
4
6
8
11
13
15
17
1
19
<6,16>
<3,11,16>
4
1G
2G
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
BA23
BA22
BA21
BA20
BA19
BA18
BA17
BA16
18
16
14
12
9
7
5
3
1G
2G
MC74LCX244DT (TSSOP)
BWR#
A15
A14
A13
A12
A11
A10
A9
A8
U43A
<6,18>
BA[8..31]
BA31
BA30
BA29
BA28
BA27
BA26
BA25
BA24
18
16
14
12
9
7
5
3
U52
2
4
6
8
11
13
15
17
1
19
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
MC74LCX244DT (TSSOP)
A23
A22
A21
A20
A19
A18
A17
A16
MC74LCX16245DT
TSSOP
<2,9,11,18>
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
CS2#
1
CS3#
2
3
U50
2
4
6
8
11
13
15
17
1
19
MC74LCX08D (SOIC)
U43B
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
BA15
BA14
BA13
BA12
BA11
BA10
BA9
BA8
18
16
14
12
9
7
5
3
3
1G
2G
MC74LCX244DT (TSSOP)
U43C
4
6
9
5
8
CS_BUF#
10
MC74LCX08D (SOIC)
U43D
<6,9>
CS6#
12
<6,9>
CS7#
13
MC74LCX08D (SOIC)
11
MC74LCX08D (SOIC)
<6,11>
CS4#
U53C
MC74LCX125DT
VDD
2
R131
10K
2
8
C192
0.1uF
10
9
C199
0.1uF
C185
0.1uF
C195
0.1uF
C219
0.1uF
C215
0.1uF
C213
0.1uF
C203
0.1uF
Decoupling Cap
1
1
m
Title
MPC857T IAD Platform
Size
A
Date:
A
B
C
D
Document Number
Address & Data buffers
Tuesday, November 12, 2002
Rev
0.2a
Sheet
E
8
of
19
1
2
3
4
5
6
7
8
U41
A
<6,8>
CS6#
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
2
3
5
6
8
9
11
12
BD8
BD9
BD10
BD11
BD12
BD13
BD14
BD15
13
14
16
17
19
20
22
23
1
48
CE1_B#
1B1
1B2
1B3
1B4
1B5
1B6
1B7
1B8
1A1
1A2
1A3
1A4
1A5
1A6
1A7
1A8
2B1
2B2
2B3
2B4
2B5
2B6
2B7
2B8
1DIR
1OE/
2A1
2A2
2A3
2A4
2A5
2A6
2A7
2A8
2DIR
2OE/
47
46
44
43
41
40
38
37
P1D7
P1D6
P1D5
P1D4
P1D3
P1D2
P1D1
P1D0
36
35
33
32
30
29
27
26
24
25
P1D15
P1D14
P1D13
P1D12
P1D11
P1D10
P1D9
P1D8
CE2_B#
J5A
<6>
CS7#
AT3
<6,8>
MC74LCX16245DT
TSSOP
BWR#
U54
Rev. 0.2a
B
<4,6,8,10,18>
<4,6,8,10,18>
<4,6,8,10,18>
<4,6,8,10,18>
47
46
44
43
A20
A21
A22
A23
<6,8,18>
<6,8,18>
<4,6,8,10,18>
<6,8,10,18>
A16
A17
A18
A19
41
40
38
37
<4,6,8,10,18>
<4,6,8,10,18>
<4,6,8,10,18>
<4,6,8,10,18>
A24
A25
A26
A27
36
35
33
32
A28
A29
A30
A31
30
29
27
26
<4,6,8,10,18>
<4,6,8,10,18>
<6,8,18>
<6,8,18>
<2,6>
<6>
1
48
MODCK1
AT1
ALE_B
1D1
1D2
1D3
1D4
1Q1
1Q2
1Q3
1Q4
2D1
2D2
2D3
2D4
2Q1
2Q2
2Q3
2Q4
3D1
3D2
3D3
3D4
3Q1
3Q2
3Q3
3Q4
4D1
4D2
4D3
4D4
4Q1
4Q2
4Q3
4Q4
1OE
1LE
2OE
2LE
PCCA11
PCCA10
PCCA9
PCCA8
2
3
5
6
8
9
11
12
PCCA15
PCCA14
PCCA13
PCCA12
13
14
16
17
PCCA7
PCCA6
PCCA5
PCCA4
19
20
22
23
PCCA3
PCCA2
PCCA1
PCCA0
24
25
ALE_B
<6>
Rev. 0.2a
PCCA16
PCCA15
PCCA12
PCCA7
PCCA6
PCCA5
PCCA4
PCCA3
PCCA2
PCCA1
PCCA0
P1D0
P1D1
P1D2
IOIS16_B
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
CD1_BP1D11
P1D12
P1D13
P1D14
P1D15
PC_CE2AVS1_B
IORD_AIOWR_APCCA17
PCCA18
PCCA19
PCCA20
PCCA21
VF0
<6>
VFLS0
<6>
A
VDD VCC
G16 G17
VCC
CARD_PWR
PCCA22
PCCA23
PCCA24
PCCA25
VS2_B
RESET_AWAIT_B#
INPAKB2REG_ABD2_BBD1_BP1D8
P1D9
P1D10
CD2_B-
R124
VFLS1
<6>
PC14
<6,10>
10K
0603
WAIT_B#
VF1
AT0
<6>
<6>
VF2
<6>
<6>
B
PCMCIA(3.3V)
68pin
U51
1
MODCK1 19
VDD
MODCK1
AT1
<2,6>
<6>
MC74LCX16373DT
TSSOP
C
AT2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
P1D3
P1D4
P1D5
P1D6
P1D7
PC_CE1APCCA10
PCOE_APCCA11
PCCA9
PCCA8
PCCA13
PCCA14
PCWE_ARDYBSY_B
CARD_PWR
12
BD[0..15]
12
8,11,14,18>
<6,8>
<6,8>
<2,6>
<2,3,4,6>
<4,6>
<3,4,6>
<4,6>
9
8
7
6
5
4
3
2
CS6#
CS7#
MODCK2
WE0#
WE1#
WE2#
WE3#
VDD
DIR
G
A8
A7
A6
A5
A4
A3
A2
A1
B8
B7
B6
B5
B4
B3
B2
B1
11
12
13
14
15
16
17
18
OP0:
OP1:
OP2:
OP3:
PC_CE1APC_CE2ARESET_AIORD_AIOWR_APCOE_APCWE_A-
RESET_A
POE_A
POE_B (MODCK1)
RESET_B (MODCK2)
C214
0.1uF
C
U47
<6,8>
<6,8>
<6,8>
<6,8>
A14
A12
A13
A11
47
46
44
43
<6,8>
<4,6,8>
<6,8>
<4,6,8>
A10
A9
A15
A8
41
40
38
37
<4,6>
<6>
A7
A6
36
35
33
32
30
29
27
26
TSIZE0
<2,6> D
<6> REG#
MODCK1
<6>
AT1
MODCK1
1
48
1D1
1D2
1D3
1D4
1Q1
1Q2
1Q3
1Q4
2D1
2D2
2D3
2D4
2Q1
2Q2
2Q3
2Q4
3D1
3D2
3D3
3D4
3Q1
3Q2
3Q3
3Q4
4D1
4D2
4D3
4D4
4Q1
4Q2
4Q3
4Q4
1OE
1LE
2OE
2LE
2
3
5
6
PCCA17
PCCA19
PCCA18
PCCA20
8
9
11
12
PCCA21
PCCA22
PCCA16
PCCA23
13
14
16
17
PCCA24
PCCA25
REG_A-
MC74LCX245DT
TSSOP
VDD
C186
0.1uF
C196
0.1uF
C187
0.1uF
19
20
22
23
C197
0.1uF
C207
0.1uF
C209
0.1uF
C208
0.1uF
C210
0.1uF
C218
0.1uF
C222
0.1uF
C217
0.1uF
C221
0.1uF
Decoupling Cap
MODCK1
24
25
D
AT1
m
<6>
MC74LCX16373DT
TSSOP
Title
MPC857T IAD Platform
Size
B
Date:
1
2
3
4
5
6
Document Number
Rev
0.2a
PCMCIA SLOT
Tuesday, November 12, 2002
7
Sheet
of
9
8
19
A
B
C
D
E
4
4
100
76
51
50
49
27
26
NC
NC
NC
NC
NC
NC
NC
IVDD
IVDD
IVDD
IVDD
IVDD
IVDD
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
R/W
BURST
CS
TA
TS
IRQ
RESET
DREQ2
DREQ1
CLK
MPC180LMB
TDI
TCK
TMS
TRST
TDO
8
19
39
58
69
91
2
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
CONFIG
ENDIAN
PSDVAL
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
OVSS
3
38
32
28
18
12
6
99
92
37
31
24
17
11
4
98
90
36
30
22
16
9
2
96
89
34
29
20
14
7
1
94
87
U34
A[18..29]
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
62
64
66
67
68
70
72
73
74
75
77
78
54
55
56
61
53
85
52
84
83
59
3
WR#
BURST#
CS1#
TA#
TS#
IRQ1#
HRESET#
R94
R92
<4,6,8,9,18>
0R0
0R0
<2,6>
<6>
<6>
<6,18>
<6,18>
<6>
<2,6,11,12,18>
PC14
48
47
46
45
44
Rev. 0.2a
<6,9>
R84
R83
CLKOUT
BCLKOUT
0R0
0R0
VDD
R82
R96
R90
57
40
82
4.7K
4.7K
4.7K
J4
C149
0.1uF
C152
0.1uF
1
2
1
2
3
4
5
6
7
8
JP2
1 = BIG ENDIAN *
0 = LITTLE ENDIAN
VCORE
<4,6,18>
<6,18>
VDD
3
13
23
33
42
63
79
80
86
95
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
OVDD
D[0..31]
IVSS
IVSS
IVSS
IVSS
IVSS
IVSS
<2,3,4,6,8>
93
71
60
41
21
10
VCORE
97
88
81
65
43
35
25
15
5
VDD
Header 1X8
VDD
C131
0.1uF
C133
0.1uF
C156
0.1uF
C164
0.1uF
C162
0.1uF
C125
0.1uF
C155
0.1uF
C158
0.1uF
C165
0.1uF
C163
0.1uF
C161
0.1uF
C154
0.1uF
C150
0.1uF
C132
0.1uF
1
m
Decoupling Cap
Decoupling Cap
Title
MPC857T IAD Platform
Size
B
Date:
A
B
C
D
Document Number
Rev
0.2a
MPC180
Tuesday, November 12, 2002
Sheet
E
10
of
19
A
B
C
D
E
U31
Rev. 0.2a
VCORE
VCORE
<3,8>
N14
M13
M14
L13
L14
K13
K14
J13
J12
J14
H13
H14
G14
G12
F13
F14
E13
E12
302 Mode: BCS4# for HDS#; BWR# for HRW#
ISA Mode: BWR# for HDS#; BOE# for HRW#
BA[28..31]
VDD
VDD
U20
BA31
BA30
BA29
Rev. 0. 2a
CS4#
BWR#
J2
<6,8>
<2,8,9,18>
FS_0B
CLK2M
GND
VCC
VCORE
HCS0
HRRQ0
HTRQ0
RST0
GND
TIO0
CLKOUT0
GND
TX0A
RX0A
TX0B
RX0B
GND
VCC
VCORE
HCS1
HRRQ1
HTRQ1
RST1
GND
TIO1
CLKOUT1
GND
TX1A
RX1A
TX1B
RX1B
GND
MID0
MID2
GND
DSP_CLK
GND
VCC
VCC
VCORE
HCS6
HRRQ6
HTRQ6
RST6
GND
TIO6
CLKOUT6
GND
HRD
HA0
HA2
H1
H3
H5
H7
GND
SCK2
GND
GND
TCK
TDI
TDO
GND
VCC
VCORE
HCS7
HRRQ7
HTRQ7
RST7
GND
TIO7
CLKOUT7
GND
GND
MID1
MID3
GND
DSP_CLK
GND
VCC
VCC
VCORE
HCS2
HRRQ2
HTRQ2
RST2
GND
TIO2
CLKOUT2
GND
HWR
HA1
H0
H2
H4
H6
GND
GND
TX2
RX2
GND
TMS
TRST
DE
GND
VCC
VCORE
HCS3
HRRQ3
HTRQ3
RST3
GND
TIO3
CLKOUT3
GND
<3,4,6,18>
OE#
Rev. 0. 2a
i.e.: DSP Operati ng Mode:
Upper: IS A Mode
Lower: 30 2 Mode
HA0
HA1
HA2
18
16
14
12
9
7
5
3
BCS4#
G6
G5
G4
G3
HDS#
21
21
21
21
VDD
HRW#
R66
RN11
Rev. 0 .2a
1
19
DSP_0_HCS#
DSP_0_HRRQ
DSP_0_HTRQ
DSP_0_RST#
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
8
7
6
5
1G
2G
MC74LCX244DT (TSSOP)
CLK4M
3
Rev. 0. 2a
HDS#
HA0
HA2
DSPH1
DSPH3
DSPH5
DSPH7
Rev. 0. 2a
ONCE_TCK
SODIMM_TDI
ONCE_TDO
2
G12
G 1 1 21
21
10K R-PACK
C93
DSP_0_TIO
C4
A5
C5
B5
DSP_0_PCAP
DR
DX
MODA/IRQA
MODB/IRQB
MODC/IRQC
MODD/IRQD
1800p
<15>
<15>
R65
10K
N13
P12
P7
N7
VDD
DSP_1_HCS#
HRRQ1
HTRQ1
DSP_1_RST#
VDD
ONCE_TCK
ONCE_TDI
DSP_1_TIO
SODIMM_TDI
ONCE_TMS#
ONCE_TRST#
ONCE_DE#
R76 10K
ONCE_TDO
R77 10K
ESSI0_TX
ESSI0_RX
RN12
Rev. 0. 2a
i.e.: Upper R: populated when no on-board DSP
JTAG path: ONCE->R -> SODIMM->ONCE
============================== ==============
Lower R: populated wh en no SODIMM
JTAG path: ONCE->on-boar d DSP->R ->ONCE
unpopulated when in seri es with SODIMM
JTAG path: ONCE ->on-board
DSP->SODIMM- >ONCE
RN8
10K R-PACK
1
2
3
4
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
96
98
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
CLK4M
1
2
3
4
10K R-PACK
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
95
97
99
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
10K
DSP_0_NMI#
DSP_0_BB#
DSP_0_BG#
DSP_0_TA#
1
2
3
4
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
OnCE PORT
<16,18>
ONCE_TDI
ONCE_TDO
ONCE_TCK
1
3
5
7
9
11
13
ONCE_RESET#
Rev. 0 .2a
ONCE_DE#
DSP_2_TIO
2
4
6
8
10
12
14
M12
M11
N11
P10
P13
P11
N8
N10
M10
DSP_0_TA#
DSP_0_BG#
DSP_0_BB#
M9
P5
D1
DSP_0_PCAP
DSP_0_NMI#
J3
DSP_2_HCS#
HRRQ2
HTRQ2
DSP_2_RST#
C3
B3
A4
A3
B4
D3
AA0/RAS0
AA1/RAS1
AA2/RAS2
AA3/RAS3
H0/HAD0/PB0
H1/HAD1/PB1
H2/HAD2/PB2
H3/HAD3/PB3
H4/HAD4/PB4
H5/HAD5/PB5
H6/HAD6/PB6
H7/HAD7/PB7
TCK
TDI
TDO
TMS
TRST
DE
HA0/HAS/PB8
HA1/HA8/PB9
HA2/HA9/PB10
HCS/HA10/PB13
8
7
6
5
Rev. 0. 2a
GND
VCC
VCORE
HCS4
HRRQ4
HTRQ4
RST4
GND
TIO4
CLKOUT4
GND
FS0A
SCK0A
FS0B
SCK0B
GND
VCC
VCORE
HCS5
HRRQ5
HTRQ5
RST5
GND
TIO5
CLKOUT5
GND
FS1A
SCK1A
FS1B
SCK1B
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
8
7
6
5
4
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
2
4
6
8
11
13
15
17
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A16
A17
<16,18>
M8
P8
CLK4M
DSP_0_RST#
ONCE_TMS#
ONCE_TRST#
ONCE_TRST#
N5
RD
WR
BR
TA
BG
BB
CAS
BCLK
BCLK
HRW/HRD/PB11
HDS/HWR/PB12
HREQ/HTRQ/PB14
HACK/HRRQ/PB15
SC00/PC0
SC01/PC1
SC02/PC2
SCK0/PC3
SRD0/PC4
STD0/PC5
CLKOUT
PCAP
PINIT/NMI
EXTAL
XTAL
SC10/PD0
SC11/PD1
SC12/PD2
SCK1/PD3
SRD1/PD4
STD1/PD5
RESET
<2>
HEADER 7X2
HRW#
HA1
DSPH0
DSPH2
DSPH4
DSPH6
A1
A14
B14
P1
P14
VCORE
NC
NC
NC
NC
NC
RXD/PE0
TXD/PE1
SCLK/PE2
TIO0
TIO1
TIO2
VDD
RN7
4
3
2
1
1
1
2
DSP_1_TIO
2
DSP_2_TIO
2
DSP_3_TIO
1
RN9
10K R-PACK
DSP_0_RSTa#
DSP_1_RSTa#
DSP_2_RSTa#
DSP_3_RSTa#
LED-Y
Rev. 0 .2a
SODIMM-144
5
6
7
8
4
3
2
1
HTRQ0
HTRQ1
HTRQ2
HTRQ3
5
6
7
8
4
3
2
1
HRRQ0
HRRQ1
HRRQ2
HRRQ3
M3
M1
M2
L1
HA0
HA1
HA2
OB_DSP_HCS#
J2
J3
K2
J1
HRW#
HDS#
OB_DSP_HTRQ#
OB_DSP_HRRQ#
F3
D2
C1
H3
E3
E1
FS_0B
CLK2M
DX
DR
F2
A2
B2
G1
B1
C2
3
ESSI0_TX
ESSI0_RX
F1
G3
G2
DSP_0_TIO
L3
L2
K3
U19
LED-Y
D23
Rev. 0 .2a
DSP_3_TIO
Rev. 0. 2a
DSPH0
DSPH1
DSPH2
DSPH3
DSPH4
DSPH5
DSPH6
DSPH7
DSP56L307PBGA
LED-Y
D22
1
VDD
DSP_0_TIO
M5
P4
N4
P3
N3
P2
N1
N2
LED-Y
D11
330 R-PAK
DSP_3_HCS#
HRRQ3
HTRQ3
DSP_3_RST#
2
4
C91
0.1uF
D10
5
6
7
8
ONCE_TMS#
ONCE_TRST#
ONCE_DE#
E14
D12
D13
C13
C14
B13
C12
A13
B12
A12
B11
A11
C10
B10
A10
B9
A9
B8
C8
A8
B7
B6
C6
A6
ONCE_RESET#
U45C
U7D
12
11
<2,6,10,12,18>
MC74LCX14D
5
6
1
19
13
HRESET#
2
4
6
8
11
13
15
17
MC74LCX08D (SOIC)
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
DSP_0_RST#
DSP_1_RST#
DSP_2_RST#
DSP_3_RST#
DSP_0_RST#
DSP_1_RST#
DSP_2_RST#
DSP_3_RST#
18
16
14
12
9
7
5
3
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
2
1G
2G
MC74LCX244DT (TSSOP)
10K R-PACK
RN10
Rev. 0. 2a
i.e.: Upper: On-b oard DSP
Lower: S ODIMM
OB_DSP_HTRQ#
DSP_0_HTRQ
OB_DSP_HRRQ#
DSP_0_HRRQ
VDD
HTRQ0
HTRQ0
1
HTRQ1
2
18
16
14
12
3
5
7
9
1
20
VDD
3
U22B
4
HRRQ0
HTRQ2
9
HTRQ3
10
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
VDD
1G
2G
2
4
6
8
17
15
13
11
5
8
U17
U22D
12
<3,8>
<3,8>
<3,8>
11
13
BA27
BA26
BA25
IRQ4#
U21A
HRRQ0
1
HRRQ1
2
74LCX08
3
BA27
BA26
BA25
<6>
1
2
3
Rev. 0. 2a
6
4
5
BCS4#
U21B
HRRQ2
DSPREQ#
<16>
U24
<8,9,14,18>
BD[0..31]
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
A
B
C
G1
G2A
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
OB_DSP_HCS#
DSP_0_HCS#
Rev. 0. 2a
i.e.: Upper: On-b oard DSP
Lower: S ODIMM
DSP_1_HCS#
DSP_2_HCS#
DSP_3_HCS#
DSP_0_RSTa#
DSP_1_RSTa#
DSP_2_RSTa#
DSP_3_RSTa#
18
17
16
15
14
13
12
11
20
B1
B2
B3
B4
B5
B6
B7
B8
A1
A2
A3
A4
A5
A6
A7
A8
VDD
G
DIR
2
3
4
5
6
7
8
9
DSPH7
DSPH6
DSPH5
DSPH4
DSPH3
DSPH2
DSPH1
DSPH0
19
1
BCS4#
BWR#
MC74LCX245DT
TSSOP
Rev. 0. 2a
6
1
5
9
8
HRRQ3
10K
MC74LCX138D(SOIC)
4
U21C 74LCX08
1
19
R8
10K
G2
G1
21
21
10K
74LCX08
74LCX08
HTRQ0
HTRQ1
HTRQ2
HTRQ3
HRRQ0
HRRQ1
HRRQ2
HRRQ3
R9
R14
6
U22C 74LCX08
U30
BD0
BD1
BD2
BD3
BD4
BD5
BD6
BD7
VDD
Rev. 0 .2a
U22A
G8
G7
21
21
G10
G9
21
21
74LCX08
10
MC74LCX244DT (TSSOP)
74LCX08
VDD
VDD
C36
0.1uF
C37
0.1uF
C38
0.1uF
C28
0.1uF
C40
0.1uF
C35
0.1uF
C99
0.1uF
VCORE
m
Title
C41
0.1uF
C43
0.1uF
C69
0.1uF
C46
0.1uF
C71
0.1uF
C48
0.1uF
C66
0.1uF
C64
0.1uF
C45
0.1uF
C68
0.1uF
C42
0.1uF
C44
0.1uF
C47
0.1uF
C49
0.1uF
C72
0.1uF
C70
0.1uF
C67
0.1uF
C65
0.1uF
C139
0.1uF
C117
0.1uF
C116
0.1uF
C141
0.1uF
C138
0.1uF
C136
0.1uF
C135
0.1uF
MPC857T IAD Platform
Size
C
Date:
A
B
C
D
Document Number
DSP SODIMM
Rev
0.2a
Tuesday, November 12, 2002
E
Sheet
11
of
19
<6,15,18
<6,15,16,18>
<15>
<15>
5
4
3
2
1
DVDD
Note:
R38
R42
R47
10K
10K
10K
C73
C81
C88
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
R39
10K
DVDD
R46
10K
MII-TXD3
MII-TXD2
R49
10K
R52
ENBKPRS
10K
ENFCTRL
A3V3_ETH
C
<13>
<13>
<13>
LED_DUP0
LED_ACT0
LED_SPD0
<13>
<13>
<13>
<13>
<13>
LED_DUP1
LED_ACT1
LED_SPD1
LED_DUP2
LED_ACT2
<13>
LED_SPD2
<13>
<13>
<13>
<13>
<13>
<13>
RVDD
LED_DUP3
LED_ACT3
LED_SPD3
LED_DUP4
LED_ACT4
LED_SPD4
Q1
R57
10K
PIN69
1.96K R32
2SB1197K
R30
0R0
LED_BLNK_TIME
<13>
<13>
RD-0
RD+0
LED_DUP[0]
LED_ACT[0]
LED_SPD[0]
VDD
LED_DUP[1]
LED_ACT[1]
LED_SPD[1]
LED_DUP[2]
LED_ACT[2]
GND
LED_SPD[2]
VDD
LED_DUP[3]
LED_ACT[3]
LED_SPD[3]
LED_DUP[4]
LED_ACT[4]
LED_SPD[4]
TEST#
GND
AGND
IBREF
AVDD
RVDD
RX-[0]
RX+[0]
0.1uF
CE2_A#
CE1_A#
D
SGND
MRXD[1]
VDD
MRXD[0]
MRXDV
MRXC
MCOL
MTXD[3]
MTXD[2]
MTXD[1]
MTXD[0]
VDD
MTXEN
MTXC
GND
P4LNKSTA#
P4DUPSTA#
P4SPDSTA#
P4FLCTRL#
X2
X1
VDD
TESTDATA
TESTCLK
RESET#
GND
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
MII-TXD1
10K
ALE_A
MII-TXD0
MII-TX_EN
MII-TX_CLK
MII-COL
MII-RXD3
MII-RXD2
MII-RXD1
MII-RXD0
MII-CRS
MII-RXDV
MII-RX_CLK
R69
R74
R70
R71
<6>
OP0
SPARE3
IRQ7#
SPARE4
IP_A0
IP_A1
IP_A2
IP_A3
SPARE1
IP_A7
IP_A4
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
<6>
10K
10K
10K
10K
C
HRESET#
<2,6,10,11,18>
L5
ENBRDCTRL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
R50
C122
10uF
<6>
<6>
RGND
TGND
TX+[0]
TX-[0]
TVDD
TVDD
TX-[1]
TX+[1]
TGND
RGND
RX+[1]
RX-[1]
RVDD
RVDD
RX-[2]
RX+[2]
RGND
TGND
TX+[2]
TX-[2]
TVDD
TVDD
TX-[3]
TX+[3]
TGND
RGND
RX+[3]
RX-[3]
RVDD
RVDD
RX-[4]
RX+[4]
RGND
TGND
TX+[4]
TX-[4]
TVDD
SVDD
R44
10K
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
C106
0.1uF
U29
GND
NC
VDD
NC
P4MODE[0]
P4MODE[1]
NC
NC
GND
NC
NC
ENP4LED
DIS_RST_BLNK#
LED_BLNK_TIME
NC
VDD
NC
NC
NC
NC
NC
NC
ENBRDCTRL
GND
ENBKPRS
ENFCTRL
NWAYHALF#
NC
NC
NC
NC
CK25MOUT
VDD
RESERVED
SELMIIMAC#
MRXD[3]
MRXD[2]
GND
D
C105
0.1uF
DVDD
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
C60
10uF
C56
PIN69
R36
10K
C57
C104
0.1uF
E
ENBKPRS
ENFCTRL
NWAYHALF#
DVDD
DVDD
C103
R55 R54
10K 10K
ENBRDCTRL
DIS_RST_BLNK#
LED_BLNK_TIME
E
DVDD
(1) All RTL8305S option pins have internal pull-up resistors.
(2) Pin 69,76,77,89,90 should be floating by default.
(3) Pin 80 should be strapped low using 10K Ohm resistor by default.
R72
33
RTL8305S
U33
3
R51
B
10K
B
C62
10uF
A
VDD
A3V3_ETH
C61
0.1uF
A3V3_ETH
C98
10uF
C55
10uF
0.1uF
0.1uF
<13 >
<13>
<13>
<13 >
C58
C77
C82
C87
C89
C59
C74
C76
C83
C85
C100
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
10uF
1
C123
0.1uF
m
C108
C109
C120
0.1uF
0.1uF
0.1uF
C124
C92
C80
C96
C110
0.1uF
0.1uF
0.1uF
0.1uF
0.1uF
4
A
Title
MPC857T IAD Platform
Size
B
Date:
5
4
OSC 25MHz(HALF)
A3V3_ETH
C94
C63
10uF
FB 0805
VDD
VDD
VDD
C102
C121
10uF
<13>
RD+3
RD-3
<13>
<13 >
L4
RD+1
RD-1
<13 >
<13>
RD-2
RD+2
<13 >
<13 >
TD+2
TD-2
<13>
<13 >
TD-3
TD+3
<13 >
R33
0R0
DIS_RST_BLNK#
TD-1
TD+1
10K
TD+0
TD-0
L6
R41
2
NWAYHALF#
3
2
Document Number
SW. HUB - RTL 8035S/8305SB
Tuesday, November 12, 2002
Rev
0.2a
Sheet
1
12
of
19
4
3
VDD
DIGITAL/ANALOG POWER
2
1
FRAME SIDE
36
5
P1
P3REF
A3V3_ETH
R21
330
D13
R16
330
D6
R26
330
D18
LED-G
LED-R
LED-Y
R22
330
D14
R17
330
D7
R27
330
D19
LED_DUP0
LED_ACT1
C151
0.1uF/1KV
<12>
<12>
LED_SPD1
<12>
LED_DUP1
<12>
LED_ACT2
<12>
LED-R
LED_SPD2
<12>
LED_DUP2
<12>
75
R88
75
TX-3
T X +3
RX-3
RX+3
MAG1
<12>
<12>
<12>
C107 0.1uF
RD-3
RD+3
TD+3
<12>
<12>
C95
0.1uF
TD-3
TD-2
<12>
<12>
<12>
<12>
<12>
<12>
C78
0.1uF
TD+2
RD+2
RD-2
RD-1
RD+1
TD+1
<12>
<12> 0.1uF
C84
TD-1
TD-0
<12>
<12>
<12>
LED-G
R89
R87
75 1%
D17
LED-Y
C
<12>
TD+0
RD+0
RD-0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
RD1+
RD1TD1+
TCT1
TD1TD2TCT2
TD2+
RD2RD2+
RD3+
RD3TD3+
TCT3
TD3TD4TCT4
TD4+
RD4RD4+
TX1+
CMT1
TX1RX1+
RX1TX2CMT2
TX2+
RX2RX2+
TX3+
CMT3
TX3RX3+
RX3TX4CMT4
TX4+
RX4RX4+
T X +3
P3REF
TX-3
RX-3
RX+3
TX-2
P2REF
T X +2
RX+2
RX-2
T X +1
P1REF
TX-1
RX-1
RX+1
TX-0
P0REF
T X +0
RX+0
RX-0
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
35
P2REF
R81
75
R80
75
R79
75 1%
C128
0.1uF/1KV
TX-2
T X +2
RX-2
RX+2
34
P1REF
R64
75
R63
75
R61
75 1%
C101
0.1uF/1KV
TX-1
T X +1
RX-1
RX+1
40ST1053
C119
R68
49.9 1%
RD+3
TD+3
R73
49.9 1%
RD-3
R78
49.9 1%
TD-2
R67
49.9 1%
RD+2
R60
49.9 1%
TD+2
R62
49.9 1%
RD-2
R59
49.9 1%
TD-3
R75
49.9 1%
R34
P0REF
C54
0.1uF/1KV
XX1
TX-0
R31
XX2
LED-R
R28
330
<12>
LED_SPD3
<12>
LED_DUP3
<12>
D20
LED-Y
B
LED_ACT3
MII Port
R24
330
REF
REF
TXREF
REF
TX+
RXRX+
.
TD-1
R48
49.9 1%
RD+1
R56
49.9 1%
TD+1
R53
49.9 1%
RD-1
R58
49.9 1%
TD-0
R45
49.9 1%
RD+0
R40
49.9 1%
R43
49.9 1%
RD-0
Port 2
PG
.
.
.
.
.
.
.
.
REF
REF
TXREF
REF
TX+
RXRX+
C
Port 1
PG
.
.
.
.
.
.
.
.
REF
REF
TXREF
REF
TX+
RXRX+
C86
Port 0
PHJ8x4
0.1uF
B
P3
0.1uF
D16
LED_ACT4
<12>
LED_SPD4
<12>
LED_DUP4
<12>
TD+0
R37
49.9 1%
D9
LED-R
R29
330
0.1uF
PG
.
.
.
.
.
.
.
.
.
D
Port 3
C75
LED-G
R19
330
T X +0
RX-0
RX+0
.
REF
REF
TXREF
REF
TX+
RXRX+
.
LED-G
75
8
7
6
5
4
3
2
1
.
.
.
.
.
.
.
.
.
D8
75
R35
75 1%
C90
R18
330
16
15
14
13
12
11
10
9
A3V3_ETH
0.1uF
D15
24
23
22
21
20
19
18
17
33
LED-Y
R23
330
32
31
30
29
28
27
26
25
PG
LED-R
R25
330
LED_SPD0
D5
9
R15
330
<12>
L3
XX1
RX-0
L1
XX2
RX+0
TX-0
T X +0
D21
.
.
.
.
.
.
.
.
REF
REF
TXREF
REF
TX+
RXRX+
UpLink
PHJ8x1
A
10
.
LED-Y
8
7
6
5
4
3
2
1
PG
D
LED_ACT0
37
LED-G
PG
.
D12
PG
R20
330
A
L7
m
L8
Title
MPC857T IAD Platform
Size
B
Date:
5
4
3
2
Document Number
Rev
0.2a
SW. HUB - Transformer, Phone Jack & LED
Tuesday, November 12, 2002
Sheet
1
13
of
19
A
B
C
D
E
VDD
RN2
5
6
7
8
4
3
2
1
RN6
5
6
7
8
10K R-PACK
4
3
2
1
<8,9,11,18>
10K R-PACK
U3A
4
<15>
1
StD0_B
<15>
<15>
<15>
<15>
2
U23
3
4
7
8
13
14
17
18
Q1_0_B
Q2_0_B
Q3_0_B
Q4_0_B
MC74LCX14
U7A
U3B
<15>
3
StD1_B
StD0_B#
1
StD1_B#
2
3
4
<16>
U7B
CS0B#
StD0_B#
1
11
4
MC74LCX08D (SOIC)
U7C
MC74LCX14
StD2_B#
U3C
<15>
StD2_B
5
IRQ6#
<6>
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE
CP
VDD
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
2
5
6
9
12
15
16
19
4
20
74LVX373
VDD
MC74LCX08D (SOIC)
StD3_B# 10
6
RN5
MC74LCX08D (SOIC)
5
6
7
8
MC74LCX14
U3D
<15>
D0
D1
D2
D3
D4
D5
D6
D7
9
8
5
6
BD[0..7]
9
StD3_B
4
3
2
1
<8,9,11,18>
10K R-PACK
8
<15>
<15>
<15>
<15>
MC74LCX14
U16
3
4
7
8
13
14
17
18
Q1_1_B
Q2_1_B
Q3_1_B
Q4_1_B
3
<16>
<8,9,11,18>
CS1B#
BD[0..7]
StD1_B#
1
11
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE
CP
VDD
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
2
5
6
9
12
15
16
19
3
20
74LVX373
BD[0..7]
VDD
U14
StD0_B#
StD1_B#
StD2_B#
StD3_B#
<15,17>
<15,17>
<15,17>
<15,17>
2
4
6
8
11
13
15
17
NSTAT0_B
NSTAT1_B
NSTAT2_B
NSTAT3_B
<16>
1
19
CS4B#
1A1
1A2
1A3
1A4
2A1
2A2
2A3
2A4
1Y1
1Y2
1Y3
1Y4
2Y1
2Y2
2Y3
2Y4
18
16
14
12
9
7
5
3
RN4
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
5
6
7
8
4
3
2
1
<8,9,11,18>
10K R-PACK
<15>
<15>
<15>
<15>
1G
2G
U15
3
4
7
8
13
14
17
18
Q1_2_B
Q2_2_B
Q3_2_B
Q4_2_B
MC74LCX244DT (TSSOP)
2
<16>
CS2B#
BD[0..7]
StD2_B#
1
11
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE
CP
VDD
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
2
5
6
9
12
15
16
19
2
20
74LVX373
VDD
VDD
RN3
VDD
C25
0.1uF
5
6
7
8
C3
0.1uF
C10
0.1uF
C39
0.1uF
C30
0.1uF
C27
0.1uF
C26
0.1uF
4
3
2
1
<8,9,11,18>
10K R-PACK
<15>
<15>
<15>
<15>
U13
3
4
7
8
13
14
17
18
Q1_3_B
Q2_3_B
Q3_3_B
Q4_3_B
Decoupling Cap
<16>
1
CS3B#
BD[0..7]
StD3_B#
1
11
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
OE
CP
VDD
2
5
6
9
12
15
16
19
BD7
BD6
BD5
BD4
BD3
BD2
BD1
BD0
1
20
74LVX373
m
Title
MPC857T IAD Platform
Size
A
Date:
A
B
C
D
Document Number
DTMF Latch and Buffer
Tuesday, November 12, 2002
Rev
0.2a
Sheet
E
14
of
19
A
B
C
D
E
PMC Connector for
Analog Line Card Module
VCC
Alcatel's Analog Line Card need
to pull Pin 1 of JN1 down for
program's recognition.
4
SPI Interface for
Alcatel's Codec
MTC-20233.
Rev. 0.2a
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
B2_0_B
DR
B2_1_B
DX
<14>
<14>
<14>
<14>
StD0_B
StD1_B
StD2_B
StD3_B
Ch2. DTMF data
<14>
<14>
<14>
<14>
Q4_2_B
Q3_2_B
Q2_2_B
Q1_2_B
Ch0. DTMF data
<14>
<14>
<14>
<14>
Q4_0_B
Q3_0_B
Q2_0_B
Q1_0_B
Frame sync's for each codec
JN1
(SPIMISO) PB28
(SPIMOSI) PB29
(SPICLK) PB30
PB27
<17>
<11>
<17>
<11>
Presents a logic high when a
received DTMF has been
registered and could be read
from output pins, Q1~Q4
3
R1
100K
<6>
<6>
<6,17>
<6>
Data Trassmission(DX)
and Receiving (DR)
Pins
GPIO ChX/Ring
<6,17>
<6,17>
<6,17>
<6,11,18>
GPIO ALC/ChX RevPol
FS_0B
FS_3B
PB30
FS_2B
PC13
FS_1B
PD8
FS_0B
PB22
PC12
PB18
PA12
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
VDD
B2_2_B
B2_3_B
CLK2M
RING0_B
RING1_B
RING2_B
RING3_B
Q4_3_B
Q3_3_B
Q2_3_B
Q1_3_B
Q4_1_B
Q3_1_B
Q2_1_B
Q1_1_B
NSTAT0_B
NSTAT1_B
NSTAT2_B
NSTAT3_B
Rev. 0.2a
PA13
12V
The B2 pin is a state input signal with internal
pull up. Its function depends on the state of the
pin ¡§RNGNG¡¨. When the ¡§RNGNG¡¨ signal is logic
low, (i.e. the analog line is not ringing), a
logic high at ¡§B2¡¨ sets the channel to forward
battery talk mode (TIP is positive with respect to
<6,17>
RING). A logic low at ¡§B2¡¨ sets the channel to
<6,17>
reverse battery talk mode (TIP is negative with
<6,17>
respect to RING). In contrast, when the ¡§RNGNG¡¨
<6,17>
is high (ringing), the input to ¡§B2¡¨ controls
the ringing frequency to the telephone. Typically,
<17>
a 20Hz input signal is applied to ¡§B2¡¨for normal
<17>
ringing.
<6,11,16,18>
A logic high sets the channel to ringing
<17>state while a logic low sets the channel to
<17>normal mode.
<17>
<17>
4
Ch3. DTMF data
<14>
<14>
<14>
<14>
Ch1. DTMF data
<14>
<14>
<14>
<14> Output pins from the SLIC which indicates the
off-hook status of the analog line. It is an
<14,17>
active low signal with internal pull up.
<14,17>
<14,17>
<14,17>
<6,17>
3
AMP 120521-1
Rev. 0.2a
8KHz frame sync signal
comes from Timer4/PA0
U3F
U10
<6>
2
13
PA0
12
MC74LCX14
Rev. 0.2a
<6,11,16,18>
FS_0B
1DQ0
1DQ1
1DQ2
1DQ3
1DQ4
1DQ5
1DQ6
3
4
7
8
13
14
17
18
1
11
CLK2M
D0
D1
D2
D3
D4
D5
D6
D7
U4
2
5
6
9
12
15
16
19
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
1DQ0
1DQ1
1DQ2
1DQ3
1DQ4
1DQ5
1DQ6
FS_1B
2DQ0
2DQ1
2DQ2
2DQ3
2DQ4
2DQ5
2DQ6
1
11
OE
CP
MC74LCX374
Decoupling Cap
VDD
1
C16
0.1uF
C4
0.1uF
C11
0.1uF
VCC
C6
10uF
C5
10uF
3
4
7
8
13
14
17
18
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
2DQ0
2DQ1
2DQ2
2DQ3
2DQ4
2DQ5
2DQ6
U8
FS_2B
3DQ0
3DQ1
3DQ2
3DQ3
3DQ4
3DQ5
3DQ6
3
4
7
8
13
14
17
18
1
11
OE
CP
MC74LCX374
D0
D1
D2
D3
D4
D5
D6
D7
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
2
5
6
9
12
15
16
19
3DQ0
3DQ1
3DQ2
3DQ3
3DQ4
3DQ5
3DQ6
FS_3B
2
OE
CP
MC74LCX374
1
12V
C14
10uF
C19
0.1uF
m
C23
10uF
Title
MPC857T IAD Platform
Size
A
Date:
A
B
C
D
Document Number
Analog Line Card connector & Frame Sync Generator
Tuesday, November 12, 2002
Sheet
E
15
Rev
0.2a
of
19
A
B
C
D
E
CLK4M
VDD
<11,18>
VDD
Connect to the input of Timer4 for
generating 8KHz Frame Sync signal
VDD
Rev. 0.2a
VDD
PA1
U25
16.384MHz OSC
3
Q
11
CLK
Q
6
PR
D
D
2
D
3
CLK
1
13
MC74LCX74D (SOIC)
Q
9
4
U28A
VDD
VDD
Q
PR
8
12
Q
CL
OSC
5
Q
5
CLK2M
<6,11,15,18>
CLK
8
MC74LCX74D (SOIC)
6
MC74LCX74D (SOIC)
1
GND
2
CL
7
U27B
10
4
U27A
11
PR
VDD
4
4
CL
VDD
<6>
14
VDD
CLK16M
VCC
3
3
2
TR
4
Q
DIS
C15
0.1uF
5
CV
R2
270
CS3#
BA19
BA20
BA21
BA22
BA23
R
VCC
VCC
8
Ra
<6,8>
<3,8>
<3,8>
<3,8>
<3,8>
<3,8>
THR
3
20Hz
<17>
7
6
U9
MC1455D (SOIC)
Rb
R5
360K
U18
C24
0.1uF
Cf
1
2
3
C22
0.1uF
6
4
5
2
F=1.44/(Ra+2Rb)Cf
D.C.=Rb/Ra+2Rb
A
B
C
G1
G2A
G2B
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
15
14
13
12
11
10
9
7
CS0B#
CS1B#
CS2B#
CS3B#
CS4B#
DSPREQ#
<14>
<14>
<14>
<14>
<14>
<11>
2
MC74LCX138D(SOIC)
Address assignment:(Assume A16~A19 are 0s.)
CS3#+0x0800~0x0FFF
VDD
C53
0.1uF
C79
0.1uF
C52
0.1uF
C29
0.1uF
1
1
m
Title
SOHO Gateway H/W Platform
Size
A
Date:
A
B
C
D
Document Number
ALC - CS Decoder & CLK
Tuesday, November 12, 2002
Rev
0.2a
Sheet
E
16
of
19
A
B
C
U6A
<6,15>
1
5
3
<16>
D
PB30
U2A
20Hz_0_1_B
5
1
2
20Hz
3
U6B
MC74ACT08D (SOIC)
E
2
B2_0_B
<15>
4
6
Rev. 0.2a
MC74ACT86D (SOIC)
Ch. 0
5
U6C
<14,15>
Rev. 0.2a
9
NSTAT0_B
<6,15>
PB22
MC74ACT08D (SOIC)
8
ALC_PHR0 10
RING0_B
<15>
MC74ACT08D (SOIC)
<6,15>
5
6
7
8
4
PC13
20Hz_0_1_B
RN1
4
3
2
1
U2B
4
6
ALC_PHR0
ALC_PHR1
ALC_PHR2
ALC_PHR3
U6D
5
B2_1_B
<15>
4
12
MC74ACT86D (SOIC)
11
Rev. 0.2a
13
Ch. 1
U5A
10K R-PACK
<14,15>
<6,15>
PC12
MC74ACT08D (SOIC)
1
NSTAT1_B
ALC_PHR1
3
RING1_B
2
<15>
MC74ACT08D (SOIC)
3
3
U5D
<6,15>
PD8
U2D
12
11
<16>
12
20Hz_2_3_B
11
13
20Hz
U1A
13
B2_2_B
<15>
1
MC74ACT08D (SOIC)
MC74ACT86D (SOIC)
3
2
Rev. 0.2a
Ch. 2
U1B
<14,15>
4
NSTAT2_B
<6,15>
PB18
ALC_PHR3
MC74ACT08D (SOIC)
6
RING2_B
5
<15>
MC74ACT08D (SOIC)
2
2
VCC
<6,15>
C1
0.1uF
C8
0.1uF
C2
0.1uF
PA13
U2C
20Hz_2_3_B
C9
0.1uF
9
8
U5B
10
B2_3_B
<15>
4
6
MC74ACT86D (SOIC)
Ch. 3
5
Rev. 0.2a
U5C
<14,15>
NSTAT3_B
9
PA12
ALC_PHR2 10
<6,15>
MC74ACT08D (SOIC)
8
RING3_B
1
<15>
m
MC74ACT08D (SOIC)
1
Title
MPC857T IAD Platform
Size
B
Date:
A
B
C
D
Document Number
Rev
0.2a
Analog Line Card - Ring & Off-hook Logic
Tuesday, November 12, 2002
Sheet
E
17
of
19
VDD
VCORE VDD
JN3
JN2
<11,16>
<6,11,15>
<6,11>
<6,11>
CLK4M
PC4
PA8
PA9
<6>
<6>
<6>
<6>
PD4
PD5
PD6
PD7
(UTPB[3])
(UTPB[2])
(UTPB[1])
(UTPB[0])
PD12
PD13
PD14
PD15
(SOC)
PD3
(UTPCLK)
PD9
(TXENB) PD10
(RXENB) PD11
<6>
<6>
<6>
<6>
PB15
PC15
PB20
PB21
(Txclav)
(Rxclav)
(PHSEL[0])
(PHSEL[1])
<2,6,10,11,12>
HRESET#
PB26
IRQ5#
BWE0#
<6>
<2>
VCC
BD7
BD6
<6>
<6>
<3,4,6,11>
<6,8>
IRQ3#
TA#
<6>
<6,10>
BD[0..15]
BD5
BD4
BD3
BD2
BD1
BD0
A31
A30
A[0..31]
A29
A28
A27
A26
A25
A24
A23
A22
A21
12V
<8,9,11,14>
<6>
<6>
Reserved
Reserved
PC6
PC5
<4,6,8,9,10>
<6>
ETPSQEL#(Optional) PB17
ETPFLDL#(Optional)
<6>
ETHLOOP(Optional) PB16
<6>
PB14
<6>
E_CLSN
PC11
<6>
<6>
E_RENA
E_TENA
PC10
PB19
<6>
<6>
ETHRX
ETHTX
PA15
PA14
ETHRCK
ETHTCK
PA4
PA6
<6,11,15,16>
<6>
12V
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
BWR#
TS#
<2,8,9,11>
<6,10>
BD[0..15]
BD15
BD14
BD13
BD12
BD11
BD10
BD9
BD8
A[0..31]
A20
A19
A18
A17
A16
Processor Interface
UTOPIA
Control
Signals
<6>
<6>
<6>
<6>
(UTPB[7])
(UTPB[6])
(UTPB[6])
(UTPB[4])
PC5
PB16
OE#
CS2#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
Processor Interface
UTOPIA
Data
Bus
<6>
<6>
<6>
<6>
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
<8,9,11,14>
<4,6,8,9,10>
12V
AMP 120521-1
AMP 120521-1
R85 0R0
CLKOUT
BCLKOUT
R86 0R0
VDD
C188
1
C181
1
C194
1
C189
1
C115
1
C137
1
C140
1
C142
1
C143
1
C111
1
C113
1
C112
1
C118
1
C114
1
1
VDD
C97
+
2
10uF
m
2
2
2
2
2
2
2
2
2
2
2
2
2
2
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
Title
MPC857T IAD Platform
Size
B
Date:
Document Number
ADSL Module Connector
Tuesday, November 12, 2002
Rev
0.2a
Sheet
18
of
19
5
4
3
2
1
Layout Placement of MPC857T IAD Platform Rev.0.2a
25.5 cm
D
D
PMC Con
OnCE
POWER BLOCK
DSP SODIMM
PMC Con
C
ADSL Module Ca rd
C
PMC Con
BDM
18 cm
PCMCIA SLOT
DSP
56L307
B
MPC857
RTL8305S
SDRAM
B
MPC180
SDRAM
Flash M em
Ethernet
Transformer
Ethernet Connectors
Flash M em
LED Block
Analog Line Ca rd
COM
m
7.4 cm
A
A
Title
MPC857T IAD Platform
Size
A
Date:
5
4
3
Document Number
Layout Placement
Tuesday, November 12, 2002
2
Rev
0.2a
Sheet
19
of
1
19