0.25 dB LSB, 7-Bit, Silicon Digital Attenuator, 0.1 GHz to 6.0 GHz HMC1119 Preliminary Technical Data GND 4 ATTNIN 5 GND 6 D3 D4 D5 D6 SERIAL/ PARALLEL CONTROL 7-BIT DIGITAL ATTENUATOR 7 8 9 10 11 18 SERNIN 17 CLK 16 LE 15 GND 14 ATTNOUT 13 GND 12 PACKAGE BASE GND 12962-001 3 19 GND P/S 20 GND 2 21 GND VDD 22 GND 1 23 GND D0 24 GND Attenuation range: 0.25 dB LSB steps to 31.75 dB Low insertion loss: 1.1 dB at 1.0 GHz 1.3 dB at 2.0 GHz Typical step error: less than ±0.1 dB Excellent attenuation accuracy: less than ±0.2 dB Low phase shift error: 6° phase shift at 1.0 GHz Safe state transitions High linearity 1 dB compression (P1dB): 31 dBm typical Input third-order intercept (IP3): 54 dBm typical RF settling time (0.05 dB final RF output): 250 ns Single supply operation: 3.3 V to 5.0 V ESD rating: Class 2 (2 kV human body model (HBM)) 24-lead, 4 mm × 4 mm LFCSP package: 16 mm2 D2 FUNCTIONAL BLOCK DIAGRAM D1 FEATURES Figure 1. APPLICATIONS Cellular infrastructure Microwave radios and very small aperture terminals (VSATs) Test equipment and sensors IF and RF designs GENERAL DESCRIPTION The HMC1119 is a broadband, highly accurate, 7-bit digital attenuator, operating from 0.1 GHz to 6.0 GHz with 31.5 dB attenuation control range in 0.25 dB steps. The HMC1119 is implemented in a silicon process, offering very fast settling time, low power consumption, and high ESD robustness. The device features safe state transitions and is optimized for excellent step accuracy and high linearity over frequency and temperature range. The RF input and output are JOUFSOBMMZNBUDIFEUP͙BOEEPOPUSFRVJSFBOZFYUFSOBM matching components. The design is bidirectional; therefore, the RF input and output are interchangeable. Rev PrA The HMC1119 has an on-chip regulator that can support a wide supply operating range from 3.3 V to 5.0 V with no performance change in electrical characteristics. The HMC1119 incorporates a driver that supports serial (3-wire) and parallel controls of the attenuator. The HMC1119 comes in a RoHS-compliant, compact, 4 mm × 4 mm LFCSP package. A fully populated evaluation board is available. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother rightsofthird parties thatmayresult from itsuse. Specificationssubjectto change withoutnotice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC1119 Preliminary Technical Data TABLE OF CONTENTS Features .............................................................................................. 1 Input Power Compression and Third-Order Intercept............9 Applications....................................................................................... 1 Theory of Operation ...................................................................... 10 Functional Block Diagram .............................................................. 1 Serial Control Interface ............................................................. 10 General Description ......................................................................... 1 Parallel Control Interface .......................................................... 10 Revision History ............................................................................... 2 RF Input Output ......................................................................... 10 Specifications..................................................................................... 3 Power-Up Sequence ................................................................... 10 Electrical Specifications............................................................... 3 Applications Information .............................................................. 13 Absolute Maximum Ratings ....................................................... 4 Evaluation Printed Circuit Board............................................. 13 ESD Caution.................................................................................. 4 Packaging and Ordering Information ......................................... 15 Pin Configuration and Function Descriptions............................. 5 Outline Dimensions................................................................... 15 Interface Schematics..................................................................... 6 Ordering Guide .......................................................................... 15 Typical Performance Characteristics ............................................. 7 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase................................................................................ 7 REVISION HISTORY 3/31 —Rev PrA: Preliminary Rev. PrA | Page 2 of 15 Preliminary Technical Data HMC1119 SPECIFICATIONS ELECTRICAL SPECIFICATIONS VDD = 3.3 V to 5.0 V, TA¡$ȿTZTUFNVOMFTTPUIFSXJTFOPUFE Table 1. Parameter Test Conditions/Comments FREQUENCY RANGE INSERTION LOSS ATTENUATION Range Accuracy Step Error Overshoot RETURN LOSS ATTNIN, ATTNOUT RELATIVE PHASE SWITCHING CHARACTERISTICS tRISE, tFALL tON, tOFF Settling Time INPUT LINEARITY 0.1 dB Compression (P0.1dB) 1 dB Compression (P1dB) Input Third-Order Intercept (IP3) SUPPLY CURRENT (IDD) CONTROL VOLTAGE THRESHOLD Low High RECOMMENDED OPERATING CONDITIONS Supply Voltage Range (VDD) Digital Control Voltage Range RF Input Power Case Temperature (TCASE) 0.1 GHz to 1.0 GHz 0.1 GHz to 2.0 GHz 0.1 GHz to 4.0 GHz 0.1 GHz to 6.0 GHz 0.2 GHz to 6.0 GHz Delta between minimum and maximum attenuation states Referenced to insertion loss; all attenuation states Min 0.1 Typ Max 6.0 1.1 1.3 1.6 2.0 1.8 2.0 2.3 2.8 31.75 ¦ 4% of attenuation setting) Unit GHz dB dB dB dB dB +(0.05 + 4% of attenuation setting) dB All attenuation states Between all attenuation states All attenuation states 1.0 GHz 2.0 GHz 4.0 GHz 6.0 GHz 1.0 GHz 2.0 GHz 4.0 GHz 6.0 GHz ±0.1 ź 23 22 19 17 6 18 38 58 dBm dBm dBm dBm Degrees Degrees Degrees Degrees 10%/90% RF output 50% CTL to 10%/90% RF output 50% CTL to 0.05 dB final RF output 50% CTL to 0.10 dB final RF output All attenuation states, 0.2 GHz to 6 GHz 60 150 250 200 ns ns ns ns 30 31 54 dBm dBm dBm 0.3 0.6 mA mA 5XPUPOFJOQVUQPXFSE#NUPOFƅG = 1 MHz VDD = 3.3 V VDD = 5.0 V <1 µA typical VDD = 3.3 V VDD = 5.0 V VDD = 3.3 V VDD = 5.0 V For P/S, CLK, SERNIN, LE, D0 to D6 pins All attenuation states, TCASE = 85°C 0 0 2.0 3.5 0.5 0.8 3.3 5.0 V V V V 3.0 0 5.4 VDD 24 +85 V V dBm °C ¦ Rev. PrA | Page 3 of 15 dB dB HMC1119 Preliminary Technical Data ABSOLUTE MAXIMUM RATINGS Table 2. Parameter RF Input Power (TCASE = 85°C) Digital Control Inputs (P/S, CLK, SERNIN, LE, D0 to D6) Supply Voltage (VDD) Continuous Power Dissipation (PDISS) Thermal Resistance (at Maximum Power Dissipation) Temperature Channel Temperature Storage Maximum Reflow Temperature ESD Sensitivity (HBM) Rating 25 dBm ¦7UP7DD + 0.5 V ¦7UP7 0.31 W 156°C/W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. ESD CAUTION 135°C ¦¡$UP¡$ 260°C (MSL3 Rating) 2 kV (Class 2) Rev. PrA | Page 4 of 15 Preliminary Technical Data HMC1119 D2 D3 D4 D5 D6 24 23 22 21 20 19 D0 1 18 SERNIN VDD 2 17 CLK P/S 3 16 LE 15 GND HMC1119 TOP VIEW (Not to Scale) 14 ATTNOUT GND 6 13 GND 8 GND GND 7 9 10 11 12 GND 5 GND ATTNIN GND 4 GND GND NOTES 1. THE EXPOSED PAD AND GND PINS MUST BE CONNECTED TO RF DC GROUND. 12962-002 D1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1, 19 to 24 Mnemonic D0, D6 to D1 2 3 VDD P/S 4, 6 to 13, 15 GND 5 ATTNIN 14 "55/065 16 LE 17 CLK 18 SERNIN EPAD Description Parallel Control Voltage Inputs. These pins attain the required attenuation (see Table 5). There is no internal pull-up or pull-down on these pins; therefore, these pins must always be kept at a valid logic level (VIH or VIL) and must not be left floating. Supply Voltage Pin. Parallel/Serial Control Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. For parallel mode, set Pin 3 to low; for serial mode, set Pin 3 to high. Ground. The package bottom has an exposed metal pad that must connect to the printed circuit board (PCB) RF/dc ground. See Figure 4 for the GND interface schematic. "UUFOVBUPS*OQVU5IJTQJOJTEDDPVQMFEBOENBUDIFEUPƆ"CMPDLJOHDBQBDJUPSJTSFRVJSFE4FMFDU the value of the capacitor based on the lowest frequency of operation. See Figure 5. "UUFOVBUPS0VUQVU5IJTQJOJTEDDPVQMFEBOENBUDIFEUPƆ"CMPDLJOHDBQBDJUPSJTSFRVJSFE4FMFDU the value of the capacitor based on the lowest frequency of operation. See Figure 5. Serial/Parallel Interface Latch Enable Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. See the Theory of Operation section for more information. Serial Interface Clock Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. See the Theory of Operation section for more information. Serial interface Data Input. There is no internal pull-up or pull-down on this pin; therefore, this pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. See the Theory of Operation section for more information. Exposed Pad. The exposed pad must be connected to RF/dc ground. Rev. PrA | Page 5 of 15 HMC1119 Preliminary Technical Data VDD ATTIN, ATTOUT 12962-023 INTERFACE SCHEMATICS 12962-021 D0 TO D5 Figure 3. D0 to D6 Interface Figure 5. ATTIN and ATTOUT Interface VDD 12962-022 GND P/S, LE, CLK, SERNIN 12962-024 Figure 4. GND Interface Figure 6. P/S, LE, CLK, and SERNIN Interface Rev. PrA | Page 6 of 15 Preliminary Technical Data HMC1119 TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE 0 +85°C +25°C –40°C NORMALIZED ATTENUATION (dB) INSERTION LOSS (dB) 0 –1 –2 –3 –5 –10 –15 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB –20 –25 0 1 2 3 4 5 6 FREQUENCY (GHz) –35 12962-003 0 4 5 6 0 –10 –20 –30 IL 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB 0 1 2 3 4 5 –30 IL 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB –40 –50 6 FREQUENCY (GHz) –60 12962-004 –40 –20 0 5 6 1GHz 2GHz 3GHz 4GHz 5GHz 6GHz 0.8 0.8 0.4 STATE ERROR (dB) 0.6 0.4 0 –0.4 –0.8 0.2 0 –0.2 –0.4 –0.6 –1.6 –0.8 –2.0 8 12 16 20 24 28 32 ATTENUATION STATE (dB) 12962-007 –1.2 4 4 1 1.2 0 3 Figure 11. Output Return Loss (Major States Only) 100MHz 200MHz 400MHz 500MHz 1.6 2 FREQUENCY (GHz) Figure 8. Input Return Loss (Major States Only) 2.0 1 12962-006 OUTPUT RETURN LOSS (dB) –10 INPUT RETURN LOSS (dB) 3 Figure 10. Normalized Attenuation (Major States Only) 0 STATE ERROR (dB) 2 FREQUENCY (GHz) Figure 7. Insertion Loss vs. Frequency at Various Temperatures –50 1 –1 0 4 8 12 16 20 24 28 ATTENUATION STATE (dB) Figure 12. State Error vs. Attentuation State, 1 GHz to 6 GHz Figure 9. State Error vs. Attentuation State, 0.1 GHz to 0.5 GHz Rev. PrA | Page 7 of 15 32 12962-009 –4 12962-005 –30 Preliminary Technical Data HMC1119 2.0 1.0 1.5 0.8 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB 0.6 STEP ERROR (dB) 0.5 0 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB –1.0 –1.5 –2.0 0 1 2 3 4 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 5 6 FREQUENCY (GHz) –1.0 0 20 0 –20 –40 –60 0 1 2 3 4 5 6 FREQUENCY (GHz) 12962-011 RELATIVE PHASE (deg) 40 3 4 5 Figure 15. Step Error vs. Frequency, Major States Only 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB 31.75dB 60 2 FREQUENCY (GHz) Figure 13. State Error vs. Frequency, Major States Only 80 1 Figure 14. Relative Phase vs. Frequency, Major States Only Rev. PrA | Page 8 of 15 6 12962-010 –0.5 12962-008 STATE ERROR (dB) 1.0 Preliminary Technical Data HMC1119 INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT 40 40 +85°C +25°C –40°C 35 P1dB (dBm) 30 25 20 25 0.2 0.4 0.6 0.8 1.0 FREQUENCY (GHz) 15 12962-012 0 Figure 16. P1dB vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.05 GHz to 1 GHz 0 3 4 5 6 Figure 19. P1dB vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.05 GHz to 6 GHz 40 +85°C +25°C –40°C +85°C +25°C –40°C 35 P0.1dB (dBm) 35 30 25 20 30 25 0.2 0.4 0.6 0.8 1.0 FREQUENCY (GHz) 15 12962-013 0 Figure 17. P0.1dB vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.05 GHz to 1 GHz 0 1 2 3 4 5 6 FREQUENCY (GHz) 12962-016 20 15 Figure 20. P0.1dB vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.05 GHz to 6 GHz 70 70 +85°C +25°C –40°C +85°C +25°C –40°C 60 IP3 (dBm) 60 50 40 50 40 0 0.2 0.4 0.6 0.8 1.0 FREQUENCY (GHz) 30 12962-014 IP3 (dBm) 2 FREQUENCY (GHz) 40 30 1 12962-015 20 15 P0.1dB (dBm) 30 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 18. IP3 vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.1 GHz to 1 GHz Figure 21. IP3 vs. Frequency at Various Temperatures, Minimum Attentuation State, 0.1 GHz to 6 GHz Rev. PrA | Page 9 of 15 12962-017 P1dB (dBm) 35 +85°C +25°C –40°C Preliminary Technical Data HMC1119 THEORY OF OPERATION The HMC1119 incorporates a 7-bit fixed attenuator array that offers an attenuation range of 0.25 dB to 31.75 dB, with 0.25 dB steps. An integrated driver provides both serial and parallel mode control of the attenuator array (see Figure 22). The HMC1119 can be in either serial or parallel mode control by setting the P/S pin to high or low, respectively (see Table 4). The 7-bit data, loaded in either serial or parallel mode, then latches with the control signal, LE, to determine the attenuator value. 1 Setting P/S to low enables parallel mode. There are two modes of parallel operation: direct parallel mode and latched parallel mode. Direct Parallel Mode For direct parallel mode, the latch enable (LE) pin must be kept high. Change the attenuation state using the control voltage inputs (D0 to D6) directly. This mode is ideal for manual control of the attenuator and using hardware, switches, or a jumper. Table 4. Mode Selection Table1 P/S Pin State Low High kept at a valid logic level (VIH or VIL) and must not be left floating. It is recommended to connect the serial control inputs to ground and to use pull-down resistors on all parallel control input lines if the device driving these input lines goes high impedance during hibernation. Control Mode Parallel Serial The P/S pin must always be kept at a valid logic level (VIH or VIL) and must not be left floating. SERIAL CONTROL INTERFACE The HMC1119 utilizes a 3-wire serial to parallel (SPI) configuration, as shown in the serial mode timing diagram (see Figure 23): serial data input (SERIN), clock (CLK), and latch enable (LE). The serial control interface activates when the P/S pin is set to high. In serial mode, the 7-bit SERIN data is clocked MSB first on rising CLK edges into the shift register; then, LE must be toggled high to latch the new attenuation state into the device. The LE must be set low to clock a set of 7-bit data into the shift register because CLK is masked to prevent the attenuator value from changing if LE is kept high. In serial mode operation, both the serial control inputs (LE, CLK, SERNIN) and the parallel control inputs (D0 to D6) must always be kept at a valid logic level (VIH or VIL) and must not be left floating. It is recommended to connect the parallel control inputs to ground and to use pull-down resistors on all serial control input lines if the device driving these input lines goes high impedance during hibernation. PARALLEL CONTROL INTERFACE The parallel control interface has seven digital control input lines (D6 to D0) to set the attenuation value. D6 is the most significant bit (MSB) that selects the 16 dB attenuator stage, and D0 is the least significant bit (LSB) that selects the 0.25 dB attenuator stage (see Figure 22). In parallel mode operation, both the serial control inputs (LE, CLK, SERNIN) and the parallel control inputs (D0 to D6) must always be Latched Parallel Mode The latch enable (LE) pin must be low when changing the control voltage inputs (D0 to D6) to set the attenuation state. When the desired state is set, LE must be toggled high to transfer the 7-bit data to the bypass switches of the attenuator array, then toggled low to latch the change into the device (see Figure 24). RF INPUT OUTPUT The attenuator in the HMC1119 is bidirectional; the ATTNIN and ATTNOUT pins are interchangeable as the RF input and PVUQVUQPSUT5IFBUUFOVBUPSJTJOUFSOBMMZNBUDIFEUP͙BUCPUI input and output; therefore, no external matching components are required. The RF pins are dc-coupled; therefore, dc blocking capacitors are required on RF lines. POWER-UP SEQUENCE The ideal power-up sequence is as follows: 1. 2. 3. 4. Power up GND. Power up VDD. Power up the digital control inputs (the relative order of the digital control inputs is not important). Power up the RF input. For latched parallel mode operation, LE must be toggled. The relative order of the digital inputs is not important as long as the inputs are powered up after GND and VDD. Power-Up States The logic state of the device is at maximum attenuation when, at power up, LE is set to low. The attenuator latches in the desired power-up state approximately 200 ms after power up. Rev. PrA | Page 10 of 15 Preliminary Technical Data D0 SERNIN DQ HMC1119 D1 DQ D2 DQ D3 DQ D4 DQ D6 D5 DQ DQ P/S P/S SELECT LE 7-BIT LATCH RF INPUT 0.25dB 0.5dB 1dB 2dB 4dB 8dB 16dB RF OUTPUT Figure 22. Attenuator Array Functional Block Diagram Table 5. Truth Table Digital Control Input1 D6 Low Low Low Low Low Low Low High High 1 D5 Low Low Low Low Low Low High Low High D4 Low Low Low Low Low High Low Low High D3 Low Low Low Low High Low Low Low High D2 Low Low Low High Low Low Low Low High D1 Low Low High Low Low Low Low Low High D0 Low High Low Low Low Low Low Low High Attenuation State (dB) 0 (reference) 0.25 0.5 1.0 2.0 4.0 8.0 16.0 31.75 Any combination of the control voltage input states shown in Table 5 provides an attenuation equal to the sum of the bits selected. Rev. PrA | Page 11 of 15 12962-018 CLK Preliminary Technical Data HMC1119 SERIN CLK X MSB [FIRST IN] X tCS D6 MSB [FIRST IN] tCH D5 D4 D3 D2 D1 D0 D[6:0] NEXT WORD X tLEW tLN X tCKN tSCK 12962-019 P/S tLES LE Figure 23. Serial Control Timing Diagram P/S X tPS D6 TO D0 X tPH D[6:0] PARALLEL CONTROL X 12962-020 tLEW LE Figure 24. Latched Parallel Mode Timing Diagram Table 6. Timing Specifications Parameter tSCK tCS tCH tLN tLEW tLES tCKN tPH tPS Description Minimum serial period, see Figure 23 Control setup time, see Figure 23 Control hold time, see Figure 23 LE setup time, see Figure 23 Minimum LE pulse width, see Figure 24 Minimum LE pulse spacing, see Figure 23 Serial clock hold time from LE, see Figure 23 Hold time, see Figure 24 Setup time, see Figure 24 Rev. PrA | Page 12 of 15 Min 70 15 Typ 20 15 10 630 0 10 2 Max Unit ns ns ns ns ns ns ns ns ns Preliminary Technical Data HMC1119 APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD 12962-026 The schematic of the evaluation board, EV2HMC1119LP4M, is shown in Figure 25. The PCB is four-layer material with a copper thickness of 0.7 mils on each layer. Each copper layer is separated with a dielectric material. The top dielectric material is 10-mil RO4350 with a typical dielectric constant of 3.48. The middle and bottom dielectric materials are FR-4 material, used for mechanical strength and to meet the overall board thickness of approximately 62 mils, which allows SMA connectors to be slipped in at board edges. All RF and dc traces are routed on the top copper layer. The RF transmission lines are designed using coplanar waveguide model (CPWG) with a width of 18 mils, spacing of 17 mils, and dielectric UIJDLOFTTPGNJMTUPNBJOUBJOȿDIBSBDUFSJTUJDJNQFEBODF The inner and bottom layers are solid ground planes. For optimal electrical and thermal performance, an ample number of vias are populated around the transmission lines and under the package exposed pad. The evaluation board layout serves as a recommendation for the optimal performance on both electrical and thermal aspects. Figure 25. EV2HMC1119LP4M Evaluation PCB Table 7. Bill of Materials Item J1, J2 J3 TP1, TP2 C1, C3 C6 C7 R1 to R11 R12 to R25 SW1, SW2 U1 PCB3 Value1 100 pF Ʌ' 1000 pF Ɔ LƆ Description PCB mount SMA connector 18-pin dc connector Through hole mount test point Capacitor, 0402 package Capacitor, 0603 package Capacitor, 0402 package Resistor, 0402 package Resistor, 0402 package SPDT four-position DIP switch HMC1119 digital attenuator 600-00963-00 evaluation PCB 1 Manufacturer2 Analog Devices, Inc. EV2HMC1119LP4M4 from Analog Devices Blank cells in the Value column indicate that there is no specific value recommendation for the listed component. Blank cells in the Manufacturer column indicate that there is no specific manufacturer recommendation for the listed component. 3 Circuit board material is Arlon 25FR. 4 Reference this number when ordering the full evaluation PCB. See the Ordering Guide section. 2 Rev. PrA | Page 13 of 15 Preliminary Technical Data HMC1119 12962-027 Figure 26. Applications Circuit Rev. PrA | Page 14 of 15 Preliminary Technical Data HMC1119 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 0.30 0.25 0.18 1 18 0.50 BSC 2.85 2.70 SQ 2.55 EXPOSED PAD 13 TOP VIEW 1.00 0.90 0.80 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PKG-000000 0.50 0.40 0.30 PIN 1 INDICATOR 24 19 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 01-13-2015-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8. Figure 27. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.90 mm Package Height (CP-24-16) Dimensions shown in millimeters ORDERING GUIDE Model1 ).$-1.& Temperature Range ¦¡$UP¡$ MSL Rating2 MSL3 ).$-1.&53 ¦¡$UP¡$ MSL3 EV2HMC1119LP4M Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] 24-Lead Lead Frame Chip Scale Package [LFCSP] Package Option CP-24-16 CP-24-16 Evaluation Board 1 HMC1119LP4ME and HMC1119LP4METR are RoHS compliant parts. See the Absolute Maximum Ratings section. 3 XXXX is the 4-digit lot number. 2 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR12962-0-4/16(PrA) www.analog.com/HMC1119 Rev. PrA | Page 15 of 15 Branding3 H1119 XXXX H1119 XXXX