0.1 GHz to 6.0 GHz, 0.5 dB LSB, 6-Bit, Silicon Digital Attenuator HMC1122 Data Sheet LE 4 GND 5 ATTIN 6 D2 D3 D4 D5 19 SERIAL/ PARALLEL INTERFACE 6-BIT/ DIGITAL ATTENUATOR GND 7 8 9 10 11 18 VDD 17 PUP1 16 PUP2 15 SEROUT 14 GND 13 ATTOUT 12 PACKAGE BASE GND 13719-001 3 20 GND SERIN 21 GND 2 22 GND CLK 23 GND 1 24 GND P/S D1 FUNCTIONAL BLOCK DIAGRAM Attenuation range: 0.5 dB LSB steps to 31.5 dB Low insertion loss 1.1 dB at 1 GHz 1.3 dB at 2 GHz Typical step error: less than ±0.1 dB Excellent attenuation accuracy Safe state transitions High linearity Input 0.1dB compression (P0.1dB): 30 dBm typical Input third-order intercept (IP3): 55 dBm typical RF settling time (0.05 dB final RF output): 250 ns Low phase shift error: 6° at 1 GHz Single supply operation: 3.3 V to 5 V ESD rating: Class 2 (2 kV HBM) 24-lead, 4 mm × 4 mm LFCSP package: 16 mm2 Pin compatible to the HMC624A D0 FEATURES Figure 1. APPLICATIONS Cellular infrastructure Microwave radios and very small aperture terminals (VSATs) Test equipment and sensors IF and RF designs GENERAL DESCRIPTION The HMC1122 is a 6-bit digital attenuator operating from 0.1 GHz to 6 GHz with a 31.5 dB attenuation control range in 0.5 dB steps. The HMC1122 is implemented in a silicon process, offering very fast settling time, low power consumption, and high ESD robustness. The device features safe state transitions and optimized for excellent step accuracy and high linearity over frequency and temperature range. The RF input and output are internally matched to 50 Ω and do not require any external matching components. The design is bidirectional; therefore, the RF input and output are interchangeable. Rev. 0 The HMC1122 operates on a single supply ranging from 3.3 V to 5 V with no performance change due to an on-chip regulator. The device incorporates a driver that provides both serial and parallel control of the attenuator. The device also features a userselectable power-up state and a serial output port for cascading other serial controlled components. The HMC1122 comes in a RoHS compliant, compact, 4 mm × 4 mm LFCSP package, and is pin compatible to the HMC624A. A fully populated evaluation board is available. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com HMC1122 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Input Power Compression and Third-Order Intercept ............9 Applications ....................................................................................... 1 Theory of Operation ...................................................................... 10 Functional Block Diagram .............................................................. 1 Power Supply............................................................................... 10 General Description ......................................................................... 1 RF Input and Output ................................................................. 10 Revision History ............................................................................... 2 Serial or Parallel Mode Selection ............................................. 10 Specifications..................................................................................... 3 Serial Mode Interface ................................................................. 10 Absolute Maximum Ratings ............................................................ 5 Parallel Mode Interface .............................................................. 11 ESD Caution .................................................................................. 5 Power-Up Interface .................................................................... 11 Pin Configuration and Function Descriptions ............................. 6 Applications Information .............................................................. 12 Interface Schematics..................................................................... 6 Evaluation Printed Circuit Board............................................. 12 Typical Performance Characteristics ............................................. 7 Evaluation Board Schematic and Artwork ............................. 13 Insertion Loss, Return Loss, State Error, Step Error, and Relative Phase................................................................................ 7 Outline Dimensions ....................................................................... 15 Ordering Guide .......................................................................... 15 REVISION HISTORY 4/16—Revision 0: Initial Version Rev. 0 | Page 2 of 15 Data Sheet HMC1122 SPECIFICATIONS VDD = 3.3 V to 5 V, TA = 25°C, 50 Ω system, unless otherwise noted. Table 1. Parameter FREQUENCY RANGE INSERTION LOSS Symbol At 0.2 GHz to 1.0 GHz At 1.0 GHz to 2.0 GHz At 2.0 GHz to 4.0 GHz At 4.0 GHz to 6.0 GHz At 0.2 GHz to 6 GHz Between minimum and maximum attenuation states Between any successive attenuation states Between any successive attenuation states All attenuation states; referenced to insertion loss state ATTENUATION Range Step Size Step Error Accuracy Overshoot RETURN LOSS (ATTIN and ATTOUT) RELATIVE PHASE SWITCHING CHARACTERISTICS Rise and Fall Time On and Off Time 0.1 dB Settling Time tRISE, tFALL tON, tOFF 0.05 dB Settling Time INPUT LINEARITY Input 0.1 dB Compression Input Third-Order Intercept SUPPLY CURRENT Test Conditions/Comments P0.1dB IP3 IDD Between all attenuation states At 1.0 GHz, minimum attenuation (worst case) At 2.0 GHz, minimum attenuation (worst case) At 4.0 GHz, minimum attenuation (worst case) At 6.0 GHz, maximum attenuation (worst case) Between minimum and maximum attenuation states At 1.0 GHz At 2.0 GHz At 4.0 GHz At 6.0 GHz Between all attenuation states 10% to 90% of RF output 50% VCTL to 90% of RF output 50% VCTL to 0.1 dB of final RF output 50% VCTL to 0.05 dB of final RF output All attenuation states, 0.2 GHz to 6 GHz Two-tone input power = 15 dBm each tone, Δf = 1 MHz VDD = 3.3 V VDD = 5.0 V Rev. 0 | Page 3 of 15 Min 0.1 Typ 1.1 1.3 1.7 2.0 Max 6.0 1.8 2.0 2.4 2.8 Unit GHz dB dB dB dB 31.5 dB 0.5 dB <±0.1 dB −(0.1 + 4% of attenuation state) +(0.1 + 4% of attenuation state) dB <0.1 24 dB dB 22 dB 22 dB 21 dB 6 18 38 58 Degrees Degrees Degrees Degrees 60 150 200 ns ns ns 250 ns 30 55 dBm dBm 0.3 0.4 mA mA HMC1122 Parameter DIGITAL CONTROL INPUTS Input Voltage Low High Low and High Input Current DIGITAL CONTROL OUTPUT Output Voltage Low High Low and High Output Current RECOMMENDED OPERATING CONDITONS Supply Voltage Digital Control Voltage Range RF Input Power Case Temperature Data Sheet Symbol Test Conditions/Comments P/S, CLK, SERIN, LE, D0 to D5, PUP1, and PUP2 pins Min VINL VDD = 3.3 V VDD = 5.0 V VDD = 3.3 V VDD = 5.0 V VDD = 3.3 V to 5 V SEROUT 0 0 2.0 3.5 VINH IINL, IINH Max Unit 0.5 0.8 3.3 5.0 V V V V µA <1 VOUTL VOUTH IOUTL, IOUTH ±0.1 VDD ± 0.1 VDD VCTL PIN TCASE Typ 1 V V mA 3.0 0 5.4 VDD V V −40 24 +85 dBm °C All attenuation states, TCASE = 85°C Rev. 0 | Page 4 of 15 Data Sheet HMC1122 ABSOLUTE MAXIMUM RATINGS Table 2. Parameter RF Input Power, PIN (TCASE = 85°C) Supply Voltage Digital Control Input Voltage Continuous Power Dissipation, PDISS Junction to Case Thermal Resistance, θJC (at Maximum Power Dissipation) Temperature Junction, TJ Storage Reflow ESD Sensitivity Human Body Model (HBM) Rating 25 dBm −0.3 V to +5.5 V −0.3 V to VDD + 0.5 V 0.31 W 156°C/W 135°C −65°C to +150°C 260°C (MSL3 Rating) Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Only one absolute maximum rating can be applied at any one time. ESD CAUTION 2 kV (Class 2) Rev. 0 | Page 5 of 15 HMC1122 Data Sheet D0 D1 D2 D3 D4 D5 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 23 22 21 20 19 1 18 VDD CLK 2 17 PUP1 SERIN 3 16 PUP2 LE 4 15 SEROUT GND 5 14 GND ATTIN 6 13 ATTOUT HMC1122 7 8 9 10 11 12 GND GND GND GND GND GND TOP VIEW (Not to Scale) NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 13719-002 P/S Figure 2. Pin Configuration (Top View) Table 3. Pin Function Descriptions Pin No. 1 Mnemonic P/S 2 3 4 5, 7 to 12, 14 6 CLK SERIN LE GND ATTIN 13 ATTOUT 15 16, 17 SEROUT PUP2, PUP1 18 19 to 24 VDD D5 to D0 EPAD Description Parallel/Serial Mode Select. For parallel mode operation, set this pin to low. For serial mode operation, set this pin to high. Serial Interface Clock Input. Serial Interface Data Input. Latch Enable Input. Ground. These pins must be connected to ground. Attenuator RF Input. This pin can also be used as an output because the design is bidirectional. ATTIN is dc-coupled and matched to 50 Ω. An external dc blocking capacitor is required. Attenuator RF Output. This pin can also be used as an input because the design is bidirectional. ATTOUT is dc-coupled and matched to 50 Ω. An external dc blocking capacitor is required. Serial Interface Data Output. Serial input data is delayed by six clock cycles. Power-Up State Selection Bits. These pins set the attenuation value at power-up (see Table 7). There is no internal pull-up or pull-down resistor on these pins; therefore, they must always be kept at a valid logic level (VIH or VIL) and not be left floating. Power Supply. Parallel Control Voltage Inputs. These pins select the required attenuation (see Table 5). There is no internal pull-up or pull-down resistor on these pins; therefore, they must always be kept at a valid logic level (VIH or VIL) and not be left floating. Exposed Pad. The exposed pad must be connected to ground for proper operation. INTERFACE SCHEMATICS VDD VDD PUP1, PUP2, D0 TO D5 13719-021 100kΩ Figure 5. P/S, LE, CLK, and SERIN Interface Schematic Figure 3. PUP1, PUP2, and D0 to D5 Interface Schematic GND 13719-022 13719-023 ATTIN, ATTOUT 13719-024 P/S, LE, CLK, SERNIN Figure 4. ATTIN, ATTOUT Interface Schematic Figure 6. GND Interface Schematic Rev. 0 | Page 6 of 15 Data Sheet HMC1122 TYPICAL PERFORMANCE CHARACTERISTICS INSERTION LOSS, RETURN LOSS, STATE ERROR, STEP ERROR, AND RELATIVE PHASE 0 NORMALIZED ATTENUATION (dB) –0.5 –1.0 –1.5 –2.0 –2.5 –3.0 3 2 4 6 5 Figure 7. Insertion Loss vs. Frequency over Temperature –20 0.5dB 2dB 8dB 31.5dB 0dB 1dB 4dB 16dB –25 –35 0 1 3 2 5 4 6 FREQUENCY (GHz) Figure 10. Normalized Attenuation vs. Frequency over Major Attenuation States 0 0 –10 RETURN LOSS (dB) –20 –30 –40 0dB 1dB 4dB 16dB –60 0 2 3 4 5 6 FREQUENCY (GHz) Figure 8. Input Return Loss vs. Frequency over Major Attenuation States 2.0 1.2 –40 –60 4 3 5 6 1GHz 3GHz 5GHz 2GHz 4GHz 6GHz 1.2 STATE ERROR (dB) 0 –0.4 –0.8 0.8 0.4 0 –0.4 –0.8 –1.2 –1.2 –1.6 –1.6 8 12 16 20 24 28 ATTENUATION STATE (dB) 32 –2.0 13719-005 4 2 Figure 11. Output Return Loss vs. Frequency over Major Attenuation States 1.6 0.4 0 1 2.0 0.8 –2.0 0 FREQUENCY (GHz) 100MHz 200MHz 400MHz 500MHz 1.6 –30 –50 0.5dB 2dB 8dB 31.5dB 1 –20 13719-007 –50 0.5dB 2dB 8dB 31.5dB 0dB 1dB 4dB 16dB –10 13719-004 RETURN LOSS (dB) –15 13719-006 1 13719-003 0 FREQUENCY (GHz) STATE ERROR (dB) –10 –30 –3.5 –4.0 –5 0 4 8 12 16 20 24 28 32 ATTENUATION STATE (dB) Figure 9. State Error vs. Attenuation State over Frequency (100 MHz to 500 MHz) Figure 12. State Error vs. Attenuation State Over Frequency (1 GHz to 6 GHz) Rev. 0 | Page 7 of 15 13719-008 INSERTION LOSS (dB) 0 +85°C +25°C –40°C HMC1122 1.0 100MHz 200MHz 400MHz 500MHz 0.8 STEP ERROR (dB) 0.4 0.2 0 –0.2 0.2 0 –0.2 –0.4 –0.4 –0.6 –0.6 –0.8 –0.8 4 8 12 16 20 24 28 –1.0 13719-009 STEP ERROR (dB) 0.4 0 2GHz 4GHz 6GHz 0.6 0.6 –1.0 1GHz 3GHz 5GHz 0.8 32 ATTENUATION STATE (dB) 0 4 8 Figure 13. Step Error vs. Attenuation State over Frequency (100 MHz to 500 MHz) 0.5dB 2dB 8dB 31.5dB 0dB 1dB 4dB 16dB 1.5 16 20 24 28 32 Figure 16. Step Error vs. Attenuation State over Frequency (1 GHz to 6 GHz) 1.0 2.0 12 ATTENUATION STATE (dB) 13719-012 1.0 Data Sheet 0dB 1dB 4dB 16dB 0.8 0.6 0.5dB 2dB 8dB 31.5dB 0.4 STEP ERROR (dB) STATE ERROR (dB) 1.0 0.5 0 –0.5 0.2 0 –0.2 –0.4 –1.0 –0.6 –1.5 1 2 3 4 5 6 –1.0 FREQUENCY (GHz) 3 4 6 5 Figure 17. Step Error vs. Frequency over Major Attenuation States 80 80 0dB 1dB 4dB 16dB 0.5dB 2dB 8dB 31.5dB 0.1GHz 1GHz 3GHz 5GHz 60 RELATIVE PHASE (Degrees) 60 40 20 0 –20 –40 0.5GHz 2GHz 4GHz 6GHz 40 20 0 –20 –40 –60 –60 1 2 3 FREQUENCY (GHz) 4 5 6 –80 13719-011 0 0 4 8 12 16 20 24 28 32 ATTENUATION STATE (dB) Figure 15. Relative Phase vs. Frequency over Major Attenuation States Figure 18. Relative Phase vs. Attenuation States over Frequency Rev. 0 | Page 8 of 15 13719-014 RELATIVE PHASE (Degrees) 2 FREQUENCY (GHz) Figure 14. State Error vs. Frequency over Major Attenuation States –80 1 0 13719-013 0 13719-010 –2.0 –0.8 Data Sheet HMC1122 INPUT POWER COMPRESSION AND THIRD-ORDER INTERCEPT 40 40 +85°C +25°C –40°C +85°C +25°C –40°C 35 P0.1dB (dBm) 30 25 20 0.2 0.4 0.6 0.8 1.0 15 Figure 19. Input P0.1dB vs. Frequency (0.1 GHz to 1 GHz) at Minimum Attenuation State over Temperature 0 70 60 4 5 6 +85°C +25°C –40°C 60 IP3 (dBm) 50 40 50 40 0.4 0.6 0.8 1.0 FREQUENCY (GHz) 30 13719-016 0.2 0 1 2 3 5 4 6 FREQUENCY (GHz) Figure 20. Input IP3 vs. Frequency (0.1 GHz to 1 GHz) at Minimum Attenuation State over Temperature Figure 23. Input IP3 vs. Frequency (0.1 GHz to 6 GHz) at Minimum Attenuation State over Temperature 70 70 0.5dB 2dB 8dB 31.5dB 0dB 1dB 4dB 16dB 0 13719-019 IP3 (dBm) 3 Figure 22. Input P0.1dB vs. Frequency (0.1 GHz to 6 GHz) at Minimum Attenuation State over Temperature +85°C +25°C –40°C 60 0.5dB 2dB 8dB 31.5dB 0dB 1dB 4dB 16dB IP3 (dBm) 60 50 40 50 40 0 0.2 0.4 0.6 0.8 1.0 FREQUENCY (GHz) 30 13719-017 IP3 (dBm) 2 FREQUENCY (GHz) 70 30 1 13719-018 0 FREQUENCY (GHz) 30 25 20 13719-015 15 30 0 1 2 3 4 5 6 FREQUENCY (GHz) Figure 21. Input IP3 vs. Frequency (0.1 GHz to 1 GHz) over Major Attenuation States Figure 24. Input IP3 vs. Frequency (0.1 GHz to 6 GHz) over Major Attenuation States Rev. 0 | Page 9 of 15 13719-020 P0.1dB (dBm) 35 HMC1122 Data Sheet THEORY OF OPERATION The HMC1122 incorporates a 6-bit fixed attenuator array that offers an attenuation range of 31.5 dB in 0.5 dB steps. An integrated driver enables both serial and parallel mode control of the attenuator array (see Figure 25). Table 4. Mode Selection P/S Low High POWER SUPPLY SERIAL MODE INTERFACE The HMC1122 requires a single dc voltage applied to the VDD pin. The ideal power-up sequence is as follows: 1. 2. 3. 4. The HMC1122 has a 3-wire serial peripheral interface (SPI): serial data input (SERIN), clock (CLK), and latch enable (LE). The serial control interface is activated when P/S is set to high. Connect the GND pin to a ground reference. Apply a supply voltage to the VDD pin. Power up the digital control inputs. The relative order of the digital control inputs is not important. Apply an RF input signal to ATTIN or ATTOUT. In serial mode, the 6-bit SERIN data is clocked MSB first on the rising CLK edges into the shift register and then LE must be toggled high to latch the new attenuation state into the device. LE must be set to low to clock new 6-bit data into the shift register because CLK is masked to prevent the attenuator value from changing if LE is kept high. See Figure 26 in conjunction with Table 5 and Table 6. RF INPUT AND OUTPUT The attenuator in the HMC1122 is bidirectional; ATTIN and ATTOUT pins are interchangeable as the RF input and output ports. The attenuator is internally matched to 50 Ω at both the input and the output; therefore, no external matching components are required. RF pins are dc-coupled; therefore, dc blocking capacitors are required on the RF lines. The HMC1122 also features a serial data output pin, SEROUT, that outputs serial input data delayed by six clock cycles to control the cascaded attenuator using a single SPI bus. In serial mode operation, the parallel control inputs must always be kept at a valid logic level (VIH or VIL) and not be left floating. It is recommended to connect all parallel control inputs (D0 to D5) to ground. SERIAL OR PARALLEL MODE SELECTION The HMC1122 can be controlled in either serial or parallel mode by setting the P/S pin to high or low, respectively (see Table 4). D0 SERIN D1 D2 DQ DQ DQ Control Mode Parallel Serial D3 DQ D4 DQ D5 DQ P/S P/S SELECT LE 6-BIT LATCH RF INPUT 0.5dB 1dB 2dB 4dB 8dB 16dB RF OUTPUT 13719-028 CLK Figure 25. Functional Block Diagram Table 5. D5 to D0 Truth Table D5 High High High High High High Low Low 1 D4 High High High High High Low High Low Digital Control Input1 D3 D2 High High High High High High High Low Low High High High High High Low Low D1 High High Low High High High High Low D0 High Low High High High High High Low Attenuation State (dB) 0 (Reference) 0.5 1.0 2.0 4.0 8.0 16.0 31.5 Any combination of the control voltage input states shown in Table 5 provides an attenuation equal to the sum of the bits selected. Rev. 0 | Page 10 of 15 Data Sheet P/S SERIN HMC1122 X MSB [FIRST IN] X tCS D5 MSB [FIRST IN] tCH D4 D3 D2 D1 D0 D[5:0] NEXT WORD X tLN tLEW X tCKN tSCK 13719-029 CLK tLES LE Figure 26. Serial Mode Timing Diagram Table 6. Timing Specifications Description Minimum serial period, see Figure 26 Control setup time, see Figure 26 Control hold time, see Figure 26 LE setup time, see Figure 26 Minimum LE pulse width, see Figure 26 and Figure 27 Minimum LE pulse spacing, see Figure 26 Serial clock hold time from LE, see Figure 26 Hold time, see Figure 27 Setup time, see Figure 27 PARALLEL MODE INTERFACE Min 70 15 There are two modes of parallel operation: direct parallel and latched parallel. Direct Parallel Mode The LE pin must be kept high. The attenuation state is changed by the control voltage inputs (D0 to D5) directly. This mode is ideal for manual control of the attenuator. Latched Parallel Mode The LE pin must be kept low when changing the control voltage inputs (D0 to D5) to set the attenuation state. When the desired state is set, LE must be toggled high to transfer the 6-bit data to the bypass switches of the attenuator array, and then toggled low to latch the change into the device until the next desired attenuation change (see Figure 27 in conjunction with Table 6). Max Unit ns ns ns ns ns ns ns ns ns 20 15 10 630 0 10 2 P/S The HMC1122 has six digital control inputs, D0 (LSB) to D5 (MSB), to select the desired attenuation state in parallel mode, as shown in Table 5. The parallel control interface is activated when P/S is set to low. In parallel mode operation, the parallel control inputs (D0 to D5) must always be kept at a valid logic level (VIH or VIL). It is recommended to use pull-down resistors on all parallel control input lines if the device driving them goes to a high impedance state during hibernation. Typ X tPS D5 TO D0 X tPH D[5:0] PARALLEL CONTROL X tLEW 13719-030 Parameter tSCK tCS tCH tLN tLEW tLES tCKN tPH tPS LE Figure 27. Latched Parallel Mode Timing Diagram POWER-UP INTERFACE The HMC1122 uses the PUP1 and PUP2 control voltage inputs to set the attenuation value to a known value at power-up before the initial control data word is provided in either serial or parallel mode. When the attenuator powers up with LE = low, the state of PUP1 and PUP2 determines the power-up state of the device per the truth table shown in Table 7. The attenuator latches in the desired power-up state approximately 200 ms after power-up. Table 7. PUPx Truth Table1 Attenuation State 31.5 dB 24.0 dB 16.0 dB 0 dB (Reference) Determined by D0 to D5 1 LE Low Low Low Low High PUP1 Low High Low High Don’t care PUP2 Low Low High High Don’t care The PUPx pins must always be kept at a valid logic level (VIH or VIL) and not be left floating. Rev. 0 | Page 11 of 15 HMC1122 Data Sheet APPLICATIONS INFORMATION EVALUATION PRINTED CIRCUIT BOARD The schematic of the HMC1122 evaluation board is shown in Figure 28. The HMC1122 evaluation board is constructed of a 4-layer material with a copper thickness of 0.7 mil on each layer. Every copper layer is separated with a dielectric material. The top dielectric material is 10 mil RO4350. The middle and bottom dielectric materials are FR-4, used for mechanical strength and overall board thickness of approximately 62 mil, which allows SMA connectors to be slipped in at the board edges. All RF and dc traces are routed on the top copper layer. The RF transmission lines are designed using a coplanar waveguide (CPWG) model, with a width of 18 mil, spacing of 13 mil, and dielectric thickness of 10 mil, to have a characteristic impedance of 50 Ω. The inner and bottom layers are grounded planes to provide a solid ground for the RF transmission lines. For optimal electrical and thermal performance, as many vias as possible are arranged around transmission lines and under the package exposed pad. The evaluation board layout shown in Figure 29 serves as a recommendation for optimal and stable performance, as well as for improvement of thermal efficiency. The evaluation board is grounded from the dc test point, TP1. The dc supply must be connected to the dc test point, TP2, of the evaluation board. Three decoupling capacitors are populated on the supply trace to filter high frequency noise. The RF input and output ports (ATTIN and ATTOUT) are connected through 50 Ω transmission lines to the SMA connectors, J1 and J2, respectively. The ATTIN and ATTOUT ports are ac-coupled with capacitors of an appropriate value to ensure broadband performance. A thru calibration line connects J4 and J5; this transmission line is used to estimate the loss of the PCB over the environmental conditions being evaluated. All the digital control pins are connected through digital signal traces to the 2 × 9-pin header, J3. On the digital signal traces, provisions for an RC filter are made to clean any potential coupled noise. In normal operation, series resistors are 0 Ω and shunt capacitors are open. The HMC1122 evaluation board also uses two dual inline package (DIP), four-position single-pole dual-throw (SPDT) switches for the manual control of the device in direct parallel mode. Rev. 0 | Page 12 of 15 Data Sheet HMC1122 EVALUATION BOARD SCHEMATIC AND ARTWORK 13719-025 Figure 28. Evaluation Board Schematic Rev. 0 | Page 13 of 15 Data Sheet 13719-026 HMC1122 Figure 29. Evaluation Board Layout—Top View Table 8. Evaluation Board Components Component J1, J2 J3 J4, J5 TP1, TP2 C1, C2 C3 C4 C7 C5, C6 C8 to C20 SW1, SW2 R1 to R13 R14 to R25 U1 PCB Default Value Not applicable Not applicable Do not insert Not applicable 100 pF 100 pF 10 μF 1 nF Do not insert Do not insert Not applicable 0Ω 100 kΩ HMC1122 EV2HMC1122LP4M Description SMA connector 2 × 9-pin header SMA connector Through hole mount test point Capacitor, 0402 package Capacitor, 0402 package Capacitor, 0603 package Capacitor, 0402 package Capacitor, 0402 package Capacitor, 0402 package SPDT four-position DIP switch Resistor, 0402 package Resistor, 0402 package HMC1122 digital attenuator, Analog Devices, Inc. 600-01281-00-1 evaluation PCB, Analog Devices Rev. 0 | Page 14 of 15 Data Sheet HMC1122 OUTLINE DIMENSIONS 0.30 0.25 0.18 1 18 0.50 BSC 2.85 2.70 SQ 2.55 EXPOSED PAD 13 TOP VIEW 1.00 0.90 0.80 6 12 7 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE PKG-000000 0.50 0.40 0.30 PIN 1 INDICATOR 24 19 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-8. 01-13-2015-A PIN 1 INDICATOR 4.10 4.00 SQ 3.90 Figure 30. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 mm × 4 mm Body and 0.90 mm Package Height (CP-24-16) Dimensions shown in millimeters ORDERING GUIDE Model1 HMC1122LP4ME Temperature Range −40°C to +85°C MSL Rating2 MSL3 Package Description 24-Lead Lead Frame Chip Scale Package [LFCSP] Package Option CP-24-16 HMC1122LP4METR −40°C to +85°C MSL3 24-Lead Lead Frame Chip Scale Package [LFCSP] CP-24-16 EV2HMC1122LP4M Evaluation Board 1 HMC1122LP4ME and HMC1122LP4METR are RoHS compliant parts. See the Absolute Maximum Ratings section. 3 XXXX is the 4-digit lot number. 2 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D13719-0-4/16(0) Rev. 0 | Page 15 of 15 Branding3 H1122 XXXX H1122 XXXX