400 MHz to 4000 MHz Low Noise Amplifier ADL5523 Data Sheet FUNCTIONAL BLOCK DIAGRAM Operation from 400 MHz to 4000 MHz Noise figure of 0.8 dB at 900 MHz Requires few external components Integrated active bias control circuit Integrated dc blocking capacitors Adjustable bias for low power applications Single-supply operation from 3 V to 5 V Gain of 21.5 dB at 900 MHz OIP3 of 34.0 dBm at 900 MHz P1dB of 21.0 dBm at 900 MHz Small footprint LFCSP Pin-compatible version with 20.8 dB gain available VBIAS 1 ACTIVE BIAS RFIN 2 NC 3 8 VPOS 7 RFOUT ADL5523 6 NC 5 NC NC 4 NC = NO CONNECT 06829-001 FEATURES Figure 1. GENERAL DESCRIPTION The ADL5523 is a high performance GaAs pHEMT low noise amplifier. It provides high gain and low noise figure for singledownconversion IF sampling receiver architectures as well as direct-downconversion receivers. The ADL5523 is easy to tune, requiring only a few external components. The device can support operation from 3 V to 5 V, and the current draw can be adjusted with the external bias resistor for applications requiring very low power consumption. The ADL5523 provides a high level of integration by incorporating the active bias and the dc blocking capacitors, making it very easy to use while not sacrificing design flexibility. The ADL5523 comes in a compact, thermally enhanced, 3 mm × 3 mm LFCSP and operates over the temperature range of −40°C to +85°C. A fully populated evaluation board is also available. Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2008–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADL5523 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 900 MHz, VPOS = 3 V .............................................................. 11 Functional Block Diagram .............................................................. 1 1950 MHz, VPOS = 3 V ............................................................ 12 General Description ......................................................................... 1 2600 MHz, VPOS = 3 V ............................................................ 13 Revision History ............................................................................... 2 3500 MHz, VPOS = 3 V ............................................................ 14 Specifications..................................................................................... 3 DC Characteristics ..................................................................... 15 AC Specifications.......................................................................... 3 Basic Connections .......................................................................... 16 DC Specifications ......................................................................... 4 Evaluation Board ............................................................................ 17 De-Embedded S-Parameters, VPOS = 3 V to 5 V, RFIN = Port 1, VPOS = Port 2, RFOUT = Port 3 .................................. 4 Soldering Information and Recommended PCB Land Pattern .......................................................................................... 17 Absolute Maximum Ratings............................................................ 5 Tuning the ADL5523 for Optimal Noise Figure ........................ 18 ESD Caution .................................................................................. 5 Tuning S22................................................................................... 18 Pin Configuration And Function Descriptions ............................ 6 Tuning the LNA Input for Optimal Gain ................................ 19 Typical Performance Characteristics ............................................. 7 Tuning the LNA Input for Optimal Noise Figure .................. 19 900 MHz, VPOS = 5 V................................................................. 7 S11 of the LNA with S22 Matched ........................................... 20 1950 MHz, VPOS = 5 V .............................................................. 8 Outline Dimensions ....................................................................... 21 2600 MHz, VPOS = 5 V .............................................................. 9 Ordering Guide .......................................................................... 21 3500 MHz, VPOS = 5 V ............................................................ 10 REVISION HISTORY 11/13—Rev. A to Rev. B Added Figure 52, Renumbered Sequentially .............................. 15 9/09—Rev. 0 to Rev. A Updated Maximum Junction Temperature Unit (Table 4) ......... 5 10/08—Revision 0: Initial Version Rev. B | Page 2 of 24 Data Sheet ADL5523 SPECIFICATIONS AC SPECIFICATIONS TA = 25°C, R1 = 1.3 kΩ; parameters include matching circuit, matched for optimal noise, unless otherwise noted. Table 1. Parameter FREQUENCY = 900 MHz Gain (S21) vs. Frequency vs. Temperature Noise Figure 1 Output Third-Order Intercept (OIP3) Output 1 dB Compression Point (P1dB) Input Return Loss (S11) Output Return Loss (S22) Isolation (S12) FREQUENCY = 1950 MHz Gain (S21) vs. Frequency vs. Temperature Noise Figure1 Output Third-Order Intercept (OIP3) Output 1 dB Compression Point (P1dB) Input Return Loss (S11) Output Return Loss (S22) Isolation (S12) FREQUENCY = 2600 MHz Gain (S21) vs. Frequency vs. Temperature Noise Figure1 Output Third-Order Intercept (OIP3) Output 1 dB Compression Point (P1dB) Input Return Loss (S11) Output Return Loss (S22) Isolation (S12) FREQUENCY = 3500 MHz Gain (S21) vs. Frequency vs. Temperature Noise Figure1 Output Third-Order Intercept (OIP3) Output 1 dB Compression Point (P1dB) Input Return Loss (S11) Output Return Loss (S22) Isolation (S12) 1 Conditions Min ±50 MHz −40°C ≤ TA ≤ +85°C Δf = 1 MHz, POUT = 0 dBm per tone ±30 MHz −40°C ≤ TA ≤ +85°C Δf = MHz, POUT = 0 dBm per tone ±100 MHz −40°C ≤ TA ≤ +85°C Δf = 1 MHz, POUT = 0 dBm per tone ±100 MHz −40°C ≤ TA ≤ +85°C Δf = 1 MHz, POUT = 0 dBm per tone Noise figure de-embedded to first matching component on input side. Rev. B | Page 3 of 24 3V Typ Max Min 21.0 ±0.35 ±0.60 0.8 28.0 17.8 −7.5 −10.5 −24.0 16.5 ±0.06 ±0.50 0.9 28.0 17.7 −9.0 −17.0 −20.5 5V Typ Max 21.5 ±0.37 ±0.51 0.8 34.0 21.0 −8.0 −11.0 −25.5 15.8 17.0 ±0.08 ±0.47 1.0 34.0 21.2 −10.0 −20.0 −21.5 Unit dB dB dB dB dBm dBm dB dB dB 18.0 dB dB dB dB dBm dBm dB dB dB 12.8 ±0.35 ±0.45 0.9 30.0 17.0 −5.0 −10.0 −21.5 13.2 ±0.36 ±0.44 0.9 35.0 21.2 −5.0 −10.0 −22.0 dB dB dB dB dBm dBm dB dB dB 10.6 ±0.73 ±0.78 1.0 30.0 17.3 −11.0 −10.0 −19.0 11.0 ±0.78 ±0.77 1.0 33.5 20.1 −11.5 −10.5 −19.5 dB dB dB dB dBm dBm dB dB dB ADL5523 Data Sheet DC SPECIFICATIONS Table 2. Parameter Supply Current vs. Temperature Conditions Min −40°C ≤ TA ≤ +85°C 3V Typ 30 ±4 Max Min 5V Typ 60 ±7 Max Unit mA mA DE-EMBEDDED S-PARAMETERS, VPOS = 3 V TO 5 V, RFIN = PORT 1, VPOS = PORT 2, RFOUT = PORT 3 Table 3. Frequency (GHz) 0.125 0.25 0.375 0.5 0.625 0.75 0.875 1.0 1.125 1.25 1.375 1.5 1.625 1.75 1.875 2.0 2.125 2.25 2.375 2.5 2.625 2.75 2.875 3.0 3.125 3.25 3.375 3.5 3.625 3.75 3.875 4.0 S11 (dB/Ang) −4.2/−12.9 −5.8/−18.8 −7.6/−20.4 −9.5/−18.4 −11.4/−14.0 −13.2/−7.2 −15.1/+2.3 −16.8/+13.9 −18.2/+27.3 −19.3/+42.3 −19.9/+57.4 −20.0/+71.1 −20.2/+82.7 −20.1/+92.5 −19.9/+101 −19.7/+107 −19.6/+113 −19.3/+116 −19.0/+117 −18.6/+117 −18.1/+118 −17.5/+117 −16.8/+118 −15.9/+117 −14.9/+118 −13.9/+120 −13.0/+121 −12.0/+124 −11.3/+127 −10.7/+131 −10.4/+138 −9.3/+152 S12 (dB/Ang) −37.1/−21.9 −40.0/−30.6 −42.0/−31.1 −43.9/−28.2 −46.5/−27.4 −48.8/−24.6 −51.1/−19.3 −56.6/−17.6 −64.4/−15.8 −66.5/−173 −56.2/+160 −52.2/+153 −49.0/+165 −46.7/+160 −45.3/+167 −44.6/+173 −43.5/+176 −42.3/−180 −41.8/−172 −41.2/−166 −40.0/−156 −39.3/−146 −38.6/−136 −37.6/−126 −37.1/−115 −36.5/−105 −35.8/−95.4 −35.1/−88.7 −33.7/−85.0 −31.4/−86.9 −28.6/−99.9 −27.3/−136 S13 (dB/Ang) −40.6/+45.2 −38.3/+40.5 −37.5/+38.4 −36.7/+40.2 −36.2/+42.3 −35.8/+44.5 −35.4/+47.8 −35.1/+51.1 −34.6/+53.9 −34.5/+56.7 −34.1/+60.1 −33.9/+63.1 −33.5/+66.2 −33.3/+70.3 −32.9/+72.5 −32.6/+75.1 −32.1/+78.2 −31.7/+80.6 −31.5/+83.1 −31.1/+84.7 −30.8/+86.7 −30.4/+89.0 −30.3/+90.4 −30.0/+91.7 −29.8/+92.0 −29.4/+92.3 −29.3/+92.2 −29.3/+92.3 −29.6/+91.2 −30.5/+89.4 −32.9/+95.9 −30.9/+132 S21 (dB/Ang) +19.3/+132 +15.4/+104 +11.4/+87.9 +7.6/+77.4 +3.84/+70.2 +0.0/+65.3 −4.2/+62.6 −9.7/+61.7 −19.0/+70.9 −22.0/−161 −13.6/−147 −10.2/−147 −8.5/−148 −7.4/−149 −6.8/−148 −6.4/−147 −6.1/−144 −6.0/−140 −5.9/−135 −5.7/−129 −5.6/−122 −5.4/−115 −5.1/−106 −5.0/−97.7 −4.9/−88.5 −4.9/−79.2 −4.7/−71.8 −4.4/−66.4 −3.6/−63.6 −1.9/−67.1 +0.7/−83.0 +1.3/−120 S22 (dB/Ang) −6.2/+89.1 −2.3/+68.6 −1.1/+63.5 −0.6/+63.3 −0.3/+64.8 −0.2/+66.5 −0.1/+68.0 +0.0/+68.5 +0.1/+67.5 +0.2/+66.0 +0.3/+63.4 +0.4/+61.1 +0.5/+61.1 +0.6/+62.8 +0.6/+67.4 +0.6/+73.6 +0.7/+82.7 +0.7/+93.9 +0.7/+107 +0.7/+122 +0.7/+139 +0.7/+158 +0.8/+178 +0.8/−161 +0.7/−138 +0.5/−116 +0.1/−95.2 −0.3/−76.7 −0.8/−60.6 −1.7/−47.8 −4.9/−35.8 −6.3/+42.3 Rev. B | Page 4 of 24 S23 (dB/Ang) −10.6/+8.9 −13.2/−33.8 −16.2/−42.8 −19.0/−45.9 −21.7/−46.0 −24.6/+45.6 −27.8/−42.8 −32.3/−40.3 −41.4/−31.5 −45.0/+118 −34.3/+130 −30.0/+133 −27.5/+134 −25.9/+137 −24.5/+139 −23.5/+142 −22.7/+148 −22.0/+154 −21.3/+161 −20.6/+169 −20.0/+178 −19.3/−173 −18.6/+162 −18.0/−152 −17.5/−141 −16.8/−129 −16.3/−121 −15.4/−115 −14.2/−111 −12.1/−114 −8.9/−129 −7.8/−164 S31 (dB/Ang) +15.9/−161 +16.6/+174 +16.0/+158.2 +14.9/+147 +13.8/+140 +12.8/+135 +11.8/+132 +10.9/+129 +10.1/+127 +9.3/+126 +8.6/+125 +7.9/+124 +7.3/+125 +6.8/+124 +6.3/+124 +5.8/+125 +5.4/+125 +5.0/+125 +4.7/+125 +4.3/+125 +4.0/+125 +3.6/+125 +3.3/+125 +2.9/+125 +2.6/+124 +2.2/+123 +1.7/+122 +1.2/+120 +0.4/+118 −0.9/+116 −3.9/+124 −1.4/+155 S32 (dB/Ang) −10.5/−9.0 −13.2/−33.9 −16.2/−43.2 −19.0/−46.0 −21.7/−46.7 −24.5/−45.8 −27.8/−44.5 −32.5/−42.4 −41.6/−38.6 −42.8/+129 −33.8/+132 −29.8/+133 −27.2/+134 −25.5/+135 −24.2/+139 −23.3/+143 −22.5/+148 −21.8/+154 −21.1/+161 −20.5/+169 −19.8/+178 −19.1/−172 −18.5/−162 −17.8/−152 −17.3/−140 −16.7/−130 −16.2/−121 −15.3/−115 −14.1/−111 −11.9/−113 −8.8/−129 −7.7/−165 S33 (dB/Ang) −8.6/−30.4 −11.0/−6.4 −11.3/+6.4 −11.7/+16.2 −12.1/+25.3 −12.5/+34.3 −12.8/+43.2 −13.1/+52.3 −13.4/+60.8 −13.6/+69.3 −13.9/+77.5 −14.0/+85.3 −14.2/+92.8 −14.4/+100 −14.5/+107 −14.6/+114 −14.7/+121 −14.8/+127 −14.8/+133 −14.8/+140 −14.8/+145 −14.7/+151 −14.7/+158 −14.7/+164 −14.5/+172 −14.4/+180 −14.0/−172 −13.4/−162 −12.4/−152 −10.8/−141 −7.9/−137 −5.8/−150 Data Sheet ADL5523 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter Supply Voltage, VPOS RF Input Level RF Input Level (with 8 Ω Series Resistor on VPOS) Internal Power Dissipation θJA (Junction to Air) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 7 dBm 20 dBm 500 mW 50°C/W 150°C −40°C to +85°C −65°C to +150°C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD CAUTION Rev. B | Page 5 of 24 ADL5523 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RFIN 2 ADL5523 TOP VIEW (Not to Scale) 7 RFOUT 6 NC NC 3 NC 4 8 VPOS EXPOSED PAD 5 NC NOTES 1. NC = NO CONNECT. 2. CONNECT THE EXPOSED PAD TO A LOW IMPEDANCE GROUND PLANE. 06829-002 VBIAS 1 Figure 2. Pin Configuration Table 5. Pin Function Descriptions Pin No. 1 2 3, 4, 5, 6 7 8 Mnemonic VBIAS RFIN NC RFOUT VPOS 9 (EPAD) Exposed Pad (EPAD) Description Internal DC Bias. This pin should be connected to VPOS through the R1 resistor. RF Input. This is the input to the LNA. No Connection. No internal connection. RF Output. Supply Voltage. DC bias needs to be bypassed to ground using a low inductance capacitor. This pin is also used for output matching. See the Basic Connections section. GND. Connect the exposed pad to a low impedance ground plane. Rev. B | Page 6 of 24 Data Sheet ADL5523 TYPICAL PERFORMANCE CHARACTERISTICS 900 MHz, VPOS = 5 V Matched for optimal noise figure, external matching circuit included. 25 2.0 S21 20 1.8 15 1.6 NOISE FIGURE (dB) 5 0 S11 –5 –10 –15 S22 –20 0.8 0.6 40 OIP3 35 30 12 25 P1dB 8 20 6 15 4 10 890 900 910 920 930 940 21.5 20.5 22 +25°C 19.5 0 950 19.0 850 860 34 OIP3 (dBm) +85°C +25°C 0.8 –40°C 890 900 910 920 930 940 18 950 +25°C –40°C 32 30 +85°C 28 26 0.4 24 0.2 22 920 940 960 FREQUENCY (MHz) 980 1000 06829-005 NOISE FIGURE (dB) 880 FREQUENCY (MHz) 1.4 900 870 Figure 7. Gain, OIP3, and P1dB vs. Temperature 36 880 20 +85°C 1.6 860 24 P1dB –40°C 38 840 26 +85°C GAIN 40 820 28 +25°C 21.0 1.8 0 800 30 –40°C 2.0 0.6 OIP3 20.0 FREQUENCY (MHz) 1.0 1000 32 –40°C Figure 4. Noise Figure, Gain, OIP3, and P1dB vs. Frequency 1.2 980 34 22.0 06829-004 880 960 36 22.5 5 NOISE FIGURE 870 940 OIP3 AND P1dB (dBm) 45 GAIN (dB) 18 860 920 +85°C +25°C 23.0 OIP3 AND P1dB (dBm) 50 2 900 23.5 55 20 10 880 06829-007 60 GAIN 14 860 Figure 6. Noise Figure vs. Frequency at 25°C, Multiple Devices 24 16 840 FREQUENCY (MHz) Figure 3. Typical S-Parameters, Log Magnitude 22 820 06829-006 FREQUENCY (MHz) 0 800 06829-003 –35 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 NOISE FIGURE AND GAIN (dB) 1.0 0.2 –30 0 850 1.2 0.4 S12 –25 1.4 Figure 5. Noise Figure vs. Temperature 20 –4 –2 0 2 4 6 8 10 12 14 16 18 20 POUT PER TONE (dBm) Figure 8. OIP3 vs. Output Power (POUT) and Temperature Rev. B | Page 7 of 24 22 06829-008 S-PARAMETERS (dB) 10 ADL5523 Data Sheet 1950 MHZ, VPOS = 5 V Matched for optimal noise figure, external matching circuit included. 20 2.0 S21 15 1.8 10 1.6 0 –5 S11 –10 –15 S12 –20 1.4 NOISE FIGURE (dB) S-PARAMETERS (dB) 5 1.2 1.0 0.8 0.6 –25 0.4 S22 1900 1950 2000 2050 2100 2150 2200 FREQUENCY (MHz) 0 1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 FREQUENCY (MHz) Figure 9. Typical S-Parameters, Log Magnitude 45 18 GAIN 38 19.5 35 25 10 P1dB 8 20 6 15 32 +85°C 18.0 –40°C +25°C 17.0 16.5 –40°C 1930 1940 1950 1960 1970 0 1980 FREQUENCY (MHz) +85°C 1930 1940 1960 1970 16 1980 FREQUENCY (MHz) 1.8 40 –40°C 38 1.6 36 +85°C +25°C 34 OIP3 (dBm) 1.2 +25°C –40°C 32 30 +85°C 28 26 0.6 24 0.4 22 0.2 FREQUENCY (MHz) Figure 11. Noise Figure vs. Temperature 18 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 POUT PER TONE (dBm) Figure 14. OIP3 vs. Output Power (POUT) and Temperature Rev. B | Page 8 of 24 06829-014 20 0 1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 06829-011 NOISE FIGURE (dB) 1950 Figure 13. Gain, OIP3, and P1dB vs. Temperature 42 0.8 20 18 14.5 1920 2.0 1.0 22 +25°C Figure 10. Noise Figure, Gain, OIP3, and P1dB vs. Frequency 1.4 24 15.0 06829-010 0 1920 28 26 +85°C P1dB GAIN 16.0 5 NOISE FIGURE 30 17.5 15.5 2 34 18.5 10 4 36 +25°C 19.0 GAIN (dB) 30 12 40 OIP3 –40°C 20.0 40 OIP3 14 20.5 OIP3 AND P1dB (dBm) 16 NOISE FIGURE AND GAIN (dB) Figure 12. Noise Figure vs. Frequency at 25°C, Multiple Devices OIP3 AND P1dB (dBm) 1850 06829-009 –40 1800 06829-012 0.2 –35 06829-013 –30 Data Sheet ADL5523 2600 MHz, VPOS = 5 V Matched for optimal noise figure, external matching circuit included. 20 2.0 S21 1.8 10 1.6 5 1.4 NOISE FIGURE (dB) 0 S11 –5 S22 –10 –15 –20 1.2 1.0 0.8 0.6 0.4 S12 0.2 2400 2500 2600 2700 2800 2900 FREQUENCY (MHz) 0 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700 FREQUENCY (MHz) Figure 15. Typical S-Parameters, Log Magnitude 16 Figure 18. Noise Figure vs. Frequency at 25°C, Multiple Devices GAIN 14 40 16.5 50 –40°C 16.0 45 38 +25°C 12 40 35 8 30 6 25 P1dB 4 36 34 15.0 +85°C 14.5 GAIN (dB) OIP3 10 OIP3 AND P1dB (dBm) NOISE FIGURE AND GAIN (dB) 15.5 32 OIP3 14.0 26 +85°C 12.5 15 P1dB –40°C 18 11.0 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700 06829-016 FREQUENCY (MHz) FREQUENCY (MHz) Figure 19. Gain, OIP3, and P1dB vs. Temperature 2.0 42 1.8 40 –40°C 38 1.6 +25°C +85°C 34 OIP3 (dBm) 1.2 +25°C –40°C +85°C 32 30 28 26 0.6 24 0.4 22 0.2 20 0 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700 FREQUENCY (MHz) 06829-017 NOISE FIGURE (dB) 36 0.8 20 +85°C Figure 16. Noise Figure, Gain, OIP3, and P1dB vs. Frequency 1.0 22 +25°C 11.5 0 10 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700 1.4 24 GAIN 12.0 NOISE FIGURE 28 +25°C 13.0 20 2 30 –40°C 13.5 OIP3 AND P1dB (dBm) 2300 06829-019 2200 06829-015 –30 2100 06829-018 –25 Figure 17. Noise Figure vs. Temperature 18 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 POUT PER TONE (dBm) Figure 20. OIP3 vs. Output Power (POUT) and Temperature Rev. B | Page 9 of 24 22 06829-020 S-PARAMETERS (dB) 15 ADL5523 Data Sheet 3500 MHz, VPOS = 5 V Matched for optimal noise figure, external matching circuit included. 15 2.0 S21 1.8 10 1.6 0 S11 –5 1.4 NOISE FIGURE (dB) –10 1.2 1.0 0.8 0.6 S22 –15 0.4 S12 –20 3000 3100 3200 3300 3400 3500 3600 3700 FREQUENCY (MHz) 0 3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600 06829-021 2900 FREQUENCY (MHz) Figure 21. Typical S-Parameters, Log Magnitude 14 Figure 24. Noise Figure vs. Frequency at 25°C, Multiple Devices 19 45 –40°C 18 NOISE FIGURE AND GAIN (dB) 12 GAIN 40 17 30 6 25 P1dB 20 15 +85°C OIP3 13 –40°C +25°C 11 P1dB +85°C GAIN 9 2 NOISE FIGURE 37 35 31 27 25 23 21 –40°C 8 15 39 29 12 10 41 33 14 GAIN (dB) 8 OIP3 AND P1dB (dBm) 35 4 +25°C 16 OIP3 10 06829-024 0.2 –25 2800 OIP3 AND P1dB (dBm) S-PARAMETERS (dB) 5 19 +25°C 17 +85°C 15 6 3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600 06829-022 0 10 3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600 FREQUENCY (MHz) FREQUENCY (MHz) Figure 22. Noise Figure, Gain, OIP3, and P1dB vs. Frequency 42 1.8 40 36 1.4 +25°C 34 OIP3 (dBm) 1.2 +25°C 0.8 –40°C 0.6 32 +85°C 30 28 26 0.4 24 0.2 22 0 3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600 FREQUENCY (MHz) Figure 23. Noise Figure vs. Temperature 20 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 POUT PER TONE (dBm) Figure 26. OIP3 vs. Output Power (POUT) and Temperature Rev. B | Page 10 of 24 06829-026 1.0 –40°C 38 +85°C 06829-023 NOISE FIGURE (dB) Figure 25. Gain, OIP3, and P1dB vs. Temperature 2.0 1.6 06829-025 7 Data Sheet ADL5523 900 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included. 25 2.0 S21 20 1.8 15 1.6 5 S11 0 –5 –10 1.4 NOISE FIGURE (dB) S22 –15 –20 1.2 1.0 0.8 0.6 S12 –25 0.4 FREQUENCY (MHz) 0 800 06829-027 –35 600 650 700 750 800 850 900 950 1000 1050 1100 1150 1200 34 30 16 28 14 26 12 24 10 22 8 20 P1dB 18 4 900 910 920 930 940 1000 30 +25°C 22.0 –40°C 28 +85°C 21.5 26 OIP3 24 21.0 +25°C +85°C 20.5 20.0 P1dB 22 20 –40°C GAIN 18 19.5 +25°C 19.0 12 950 FREQUENCY (MHz) 16 +85°C 18.5 850 860 870 880 890 900 910 920 930 940 14 950 FREQUENCY (MHz) Figure 31. Gain, OIP3, and P1dB vs. Temperature 2.0 32 –40°C 31 1.8 30 1.6 29 1.4 28 +25°C OIP3 (dBm) 27 1.2 +85°C 1.0 +25°C 0.8 +85°C 26 25 24 23 –40°C 0.6 22 21 0.4 20 0.2 19 820 840 860 880 900 920 940 960 FREQUENCY (MHz) 980 1000 06829-029 NOISE FIGURE (dB) 980 32 Figure 28. Noise Figure, Gain, OIP3, and P1dB vs. Frequency 0 800 960 22.5 14 NOISE FIGURE 890 940 –40°C 16 880 920 OIP3 AND P1dB (dBm) OIP3 870 900 06829-031 18 860 880 23.0 GAIN (dB) 32 OIP3 AND P1dB (dBm) GAIN 06829-028 NOISE FIGURE AND GAIN (dB) 20 0 850 860 Figure 30. Noise Figure vs. Frequency at 25°C, Multiple Devices 22 2 840 FREQUENCY (MHz) Figure 27. Typical S-Parameters, Log Magnitude 6 820 06829-030 0.2 –30 Figure 29. Noise Figure vs. Temperature 18 –4 –2 0 2 4 6 8 10 12 14 16 18 POUT PER TONE (dBm) Figure 32. OIP3 vs. Output Power (POUT) and Temperature Rev. B | Page 11 of 24 20 06829-032 S-PARAMETERS (dB) 10 ADL5523 Data Sheet 1950 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included. 2.0 S21 15 1.8 10 1.6 5 0 S11 –10 –15 S12 –20 1.2 1.0 0.8 0.6 0.4 –25 1850 1900 1950 2000 2050 2100 2150 2200 FREQUENCY (MHz) 0 1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 FREQUENCY (MHz) Figure 33. Typical S-Parameters, Log Magnitude 18 18.5 30 OIP3 24 8 22 6 20 P1dB 2 0 1920 1930 1940 1950 1970 16.5 16.0 14.5 1920 1930 1940 1950 1960 14 1980 1970 FREQUENCY (MHz) Figure 37. Gain, OIP3, and P1dB vs. Temperature 30 1.8 29 –40°C 28 1.6 27 +85°C +25°C 26 OIP3 (dBm) 1.2 +25°C 0.8 –40°C +85°C 25 24 23 22 0.6 21 0.4 20 0.2 FREQUENCY (MHz) Figure 35. Noise Figure vs. Temperature 18 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 POUT PER TONE (dBm) Figure 38. OIP3 vs. Output Power (POUT) and Temperature Rev. B | Page 12 of 24 18 06829-038 19 0 1800 1820 1840 1860 1880 1900 1920 1940 1960 1980 2000 06829-035 NOISE FIGURE (dB) 16 +85°C 2.0 1.0 18 +25°C Figure 34. Noise Figure, Gain, OIP3, and P1dB vs. Frequency 1.4 20 P1dB –40°C 15.0 FREQUENCY (MHz) 22 +85°C 15.5 14 1980 24 +25°C GAIN 16 1960 –40°C 17.0 18 NOISE FIGURE 26 +85°C OIP3 GAIN (dB) 10 17.5 OIP3 AND P1dB (dBm) 26 28 +25°C 28 12 4 18.0 06829-034 14 30 –40°C 16 NOISE FIGURE AND GAIN (dB) Figure 36. Noise Figure vs. Frequency at 25°C, Multiple Devices 32 GAIN 06829-036 0.2 S22 06829-033 –35 1800 OIP3 AND P1dB (dBm) –30 06829-037 –5 1.4 NOISE FIGURE (dB) S-PARAMETERS (dB) 20 Data Sheet ADL5523 2600 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included. 20 2.0 S21 1.8 10 1.6 5 1.4 NOISE FIGURE (dB) 0 S11 –5 S22 –10 –15 1.2 1.0 0.8 0.6 S12 –20 0.4 2400 2500 2600 2700 2800 2900 FREQUENCY (MHz) 0 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700 FREQUENCY (MHz) Figure 39. Typical S-Parameters, Log Magnitude Figure 42. Noise Figure vs. Frequency at 25°C, Multiple Devices 32 18 33 15.5 –40°C OIP3 30 GAIN 28 12 26 10 24 8 22 6 20 4 P1dB 2 NOISE FIGURE +25°C 14.5 13.5 13.0 12.0 P1dB 17 06829-040 FREQUENCY (MHz) Figure 43. Gain, OIP3, and P1dB vs. Temperature 1.8 1.6 +85°C OIP3 (dBm) 1.2 +25°C 0.8 –40°C 0.6 0.4 0.2 06829-041 NOISE FIGURE (dB) 19 +25°C –40°C 15 11.0 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700 2.0 FREQUENCY (MHz) 21 +85°C GAIN +85°C FREQUENCY (MHz) 0 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700 23 +25°C 11.5 16 25 –40°C Figure 40. Noise Figure, Gain, OIP3, and P1dB vs. Frequency 1.0 27 12.5 18 0 14 2500 2520 2540 2560 2580 2600 2620 2640 2660 2680 2700 1.4 29 OIP3 +85°C 14.0 GAIN (dB) 14 31 15.0 OIP3 AND P1dB (dBm) NOISE FIGURE AND GAIN (dB) 16 OIP3 AND P1dB (dBm) 2300 06829-043 2200 06829-039 –30 2100 06829-042 0.2 –25 Figure 41. Noise Figure vs. Temperature 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 –6 –40°C +25°C +85°C –4 –2 0 2 4 6 8 10 12 14 16 POUT PER TONE (dBm) Figure 44. OIP3 vs. Output Power (POUT) and Temperature Rev. B | Page 13 of 24 18 06829-044 S-PARAMETERS (dB) 15 ADL5523 Data Sheet 3500 MHz, VPOS = 3 V Matched for optimal noise figure, external matching circuit included. 15 2.0 S21 1.8 10 1.6 0 S11 –5 –10 1.2 1.0 0.8 0.6 S22 0.4 S12 –20 3100 3200 3300 3400 3500 3600 3700 FREQUENCY (MHz) 0 3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600 FREQUENCY (MHz) Figure 45. Typical S-Parameters, Log Magnitude 32 16 14 12 GAIN –40°C 30 15 28 14 26 24 10 8 22 20 6 33 16 29 +85°C 9 2 NOISE FIGURE 16 8 21 GAIN 19 P1dB –40°C 17 +25°C +85°C 15 7 3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600 06829-046 0 14 3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600 FREQUENCY (MHz) FREQUENCY (MHz) Figure 46. Noise Figure, Gain, OIP3, and P1dB vs. Frequency Figure 49. Gain, OIP3, and P1dB vs. Temperature 2.0 33 –40°C 32 1.8 31 1.6 +25°C 30 +85°C 29 1.2 28 OIP3 (dBm) 1.4 +25°C 0.8 –40°C +85°C 27 26 25 24 23 0.4 22 0.2 21 0 3400 3420 3440 3460 3480 3500 3520 3540 3560 3580 3600 FREQUENCY (MHz) 06829-047 NOISE FIGURE (dB) 23 +85°C 10 18 25 +25°C 11 P1dB 0.6 27 OIP3 –40°C 12 4 1.0 31 +25°C 13 GAIN (dB) OIP3 OIP3 AND P1dB (dBm) 18 NOISE FIGURE AND GAIN (dB) Figure 48. Noise Figure vs. Frequency at 25°C, Multiple Devices OIP3 AND P1dB (dBm) 3000 06829-049 2900 06829-048 0.2 06829-045 –25 2800 Figure 47. Noise Figure vs. Temperature 20 –14 –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12 14 16 POUT PER TONE (dBm) Figure 50. OIP3 vs. Output Power (POUT) and Temperature Rev. B | Page 14 of 24 06829-050 –15 1.4 NOISE FIGURE (dB) S-PARAMETERS (dB) 5 Data Sheet ADL5523 DC CHARACTERISTICS 75 120 5V, 5V, 5V, 3V, 3V, 3V, 70 SUPPLY CURRENT (mA) 60 55 50 45 40 35 VPOS = 3V 30 80 60 40 20 20 –40 –30 –20 –10 0 10 20 30 40 50 60 70 80 TEMPERATURE (°C) 90 Figure 51. Supply Current vs. Temperature, 3 V and 5 V 0 –6 –4 –2 0 2 4 6 8 10 12 14 16 18 20 22 POUT (dBm) Figure 52. Supply Current vs. POUT and Temperature, 3 V and 5 V Rev. B | Page 15 of 24 06829-100 25 06829-051 SUPPLY CURRENT (mA) 100 VPOS = 5V 65 +25°C –40°C +85°C +25°C –40°C +85°C ADL5523 Data Sheet BASIC CONNECTIONS The basic connections for operating the ADL5523 are shown in Figure 53. Capacitor C5 provides the power supply decoupling. Inductor L1 (Coilcraft 0403HQ or 0402HP series) and Capacitor C1 (Murata High-Q GJM series or equivalent) provide the input impedance matching, and the output impedance matching is provided by either L2 or C3. Resistor R1 is used to set the supply current, and the value of R1 is indirectly proportional to the supply current (that is, increasing the value of R1 reduces the supply current). The recommended external components for selected frequencies are listed in Table 7. R2 L2 W1 GND C5 100nF TR1 TR2 R1 C3 ADL5523 RFIN L1 1 VBIAS VPOS 8 2 RFIN C1 RFOUT RFOUT 7 3 NC NC 6 4 NC NC 5 06829-052 For 5 V applications where the input power exceeds the input compression point of approximately 7 dBm, a series resistor (R2) of at least 8 Ω, with a high power rating (0.2 W minimum), should be inserted on the VPOS line to protect the device from the input power overdrive. In this case, reduce Resistor R1 from 1.3 kΩ to 600 Ω to keep the supply current at around 60 mA. With R2 = 8.2 Ω (Susumu RP1608S-8R2-F) and R1 = 600 Ω, the gain and noise figure for the ADL5523 are mostly unchanged. Table 6 lists OIP3 and P1dB at selected frequencies. For 3 V power supply applications, a series resistor is not necessary for the expected input overdrive powers up to 20 dBm. VPOS Z1 Figure 53. ADL5523 Basic Connections Table 6. ADL5523 Performance at VPOS = 5 V, 25°C with R2 = 8.2 Ω and R1 = 600 Ω Frequency (MHz) 900 1950 2600 3500 Rev. B | Page 16 of 24 Noise Figure (dB) 0.8 1.0 0.9 1.0 Gain (dB) 21.5 17.0 13.5 11.3 P1dB (dBm) 20.3 20.7 20.5 20.1 OIP3 (dBm) (POUT = 0 dBm) 32.5 34.0 35.0 35.0 Data Sheet ADL5523 EVALUATION BOARD Figure 54 shows the schematic of the ADL5523 evaluation board. The board is powered by a single supply, and dc bias can be applied to the board through clip-on leads at VPOS and GND or through a 2-pin connector, W1. VPOS L2 R1 GND W1 R2 06829-054 The evaluation board comes optimized at 1950 MHz from the factory, but it can be easily modified to work at any frequency between 400 MHz and 4 GHz. Table 7 lists the recommended components at various frequencies. Figure 56. Evaluation Board Layout (Bottom View) C5 100nF TR1 C4 DNP TR2 C3 SOLDERING INFORMATION AND RECOMMENDED PCB LAND PATTERN Figure 57 shows the recommended land pattern for ADL5523. To minimize thermal impedance, the exposed pad on the package underside is soldered down to a ground plane. If multiple ground layers exist, they are stitched together using vias (a minimum of five vias is recommended). Pin 3 to Pin 6 can be left unconnected or can be connected to ground. For more information on land pattern design and layout, refer to the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP). ADL5523 1 VBIAS L1 VPOS 8 2 RFIN C1 RFOUT RFOUT 7 3 NC NC 6 4 NC NC 5 C2 0Ω 2.03mm 06829-152 RFIN Z1 8 1 1.78mm 4 5 06829-055 0.5mm 1.85mm Figure 54. Evaluation Board Schematic 1.53mm 0.71mm 06829-053 Figure 57. Recommended Land Pattern Figure 55. Evaluation Board Layout (Top View) Table 7. Recommended Components and Positions of Matching Components for Basic Connections Tuned for Optimal Noise Frequency (MHz) 500 900 1300 1950 2140 2600 3500 C1 1 (Size 0402) Open 2.4 pF 2.7 pF 1.6 pF 1.6 pF 0.75 pF 0.5 pF C2 (Size 0402) 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω C3 (Size 0402) Open Open 1.0 nF 1.0 nF 1.0 nF 1.0 nF 1.0 nF C4 (Size 0402) Open Open Open Open Open Open Open C5 (Size 0402) 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF 100 nF L1 2 (Size 0403) 9 nH 8.2 nH 3.4 nH 1.0 nH 1.0 nH 1.0 nH 2.4 pF 5 L22 Size 0403) 12 nH 3.4 nH 0Ω 0Ω 0Ω 0Ω 0Ω The Murata GJM High-Q series capacitor is recommended for C1. The Coilcraft High Q 0403HQ or 0402HP inductors are recommended for L1 and L2. If R2 = 8 Ω, reduce R1 to 600 Ω. 4 If R2 = 8 Ω, use a high power resistor (0.2 W rating minimum). 5 Note that at 3500 MHz, a capacitor, not an inductor, is used at L1. 1 2 3 Rev. B | Page 17 of 24 R1 3 (Size 0603) 1.3 kΩ 1.3 kΩ 1.3 kΩ 1.3 kΩ 1.3 kΩ 1.3 kΩ 1.3 kΩ R2 4 (Size 0603) 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω 0Ω TR1 (mm) 0 0 0 2.5 × 0.6 5.0 × 0.6 8.0 × 0.6 7.0 × 0.6 TR2 (mm) 0 0 8.0 × 0.6 5.5 × 0.6 3.0 × 0.6 0 1 × 0.6 C1 Position C1 C1 C1 C1 C1 C1 C1 C3 Position N/A N/A 6 4 2 C3 1 ADL5523 Data Sheet TUNING THE ADL5523 FOR OPTIMAL NOISE FIGURE The ADL5523 is a monolithic low noise amplifier (LNA) in a 3 mm × 3 mm LFCSP. The evaluation board, as shipped from the factory, gives a noise figure of 0.9 dB over a bandwidth of several hundred megahertz. The specific frequency where optimal noise is reached depends on the tuning. The bandwidth of the ADL5523 is 400 MHz to 4 GHz, although noise figure degrades above 2.5 GHz as the gain begins to roll off. This section is based on Analog Devices, Inc., lab measurements. Although there are plots in which the Agilent Advanced Design System (ADS) environment is used, the data in these plots come entirely from Analog Devices lab measurements. TUNING S22 Tuning of the LNA begins with S22 (output tuning). Tuning of the LNA output is done by placing reactive components on the bias line, referred to in the schematic in Figure 54 as VPOS. On the LNA evaluation board, S22 tuning is achieved by either the use of an inductor (L2) on the bias line or a shunt capacitor (C3) on the bias line to ground. Typically, either L2 is required or C3 but not both. The slider is seen in the LNA PCB layout in Figure 58 as the area near the red arrows to the right of the bias line. With a 0 Ω resistor in place of L2, moving a 1 nF capacitor from the top to the bottom effectively tunes S22 from 1400 MHz to 3500 MHz. Table 8 shows the component values and placement required for S22 tuning from 800 MHz to 3200 MHz. For lower frequencies, higher values of L2 can be used to tune S22, and for frequencies from 3.2 GHz to 4.0 GHz, smaller values of capacitors can be used on the slider. Table 8. Capacitor and Inductor Tuning and Placement for LNA S22 Tuning Frequency (MHz) 800 1400 2000 2400 2800 3200 L2 (nH) 3.4 0Ω 0Ω 0Ω 0Ω 0Ω C3 (nF) Open 1 nF 1 nF 1 nF 1 nF 1 nF C3 Placement N/A 6 4 3 2 1 The evaluation board uses a slider on the bias line to make tuning for S22 as easy as possible. The slider is an area of ground etch adjacent to the bias line that is clear of solder mask. The bias line in this area is also free of solder mask. This allows a capacitor (C3) to be placed anywhere on the bias line to ground, which provides easy and accurate tuning for S22. 06829-056 Note that the PCB layout shows two capacitors, C3 and C4. Typically, only one of these capacitors is needed for good S22 tuning. Figure 58. PCB Layout for LNA Evaluation Board (Note Slider on Bias Line with Capacitor Placement for S22 Tuning Noted by Arrows) Rev. B | Page 18 of 24 Data Sheet ADL5523 TUNING THE LNA INPUT FOR OPTIMAL GAIN LNAs are generally tuned for either gain or noise optimization, or some trade-off between the two. One figure of merit of an LNA is how much trade-off must be made for one of these parameters to optimize the other. With the ADL5523, an S11 of 6 dB to 8 dB at the input to the matching network can still be achieved typically when optimizing for noise. For optimal gain matching, the goal is to use a matching network that converts the input impedance of the LNA to the characteristic impedance of the system, typically 50 Ω. Correct tuning for gain matching results in a conjugate match. That is, the impedance of the matching network at the LNA input, looking back toward the generator, is always the complex conjugate of the LNA input impedance when matched for gain. Once S11*, the complex conjugate of S11, is known, a matching circuit must be found that transforms the 50 Ω system impedance into the conjugate S11 impedance. To do this, the designer starts at the origin of the Smith Chart circle and finds components that move the 50 Ω match to S11*. The related impedances for gain matching are shown in Figure 59. A Smith Chart representation of the conjugate match is shown in Figure 60. 50Ω MATCHING NETWORK 50Ω LNA S11* 06829-057 S11 Figure 59. Matching LNA Input for Gain TUNING THE LNA INPUT FOR OPTIMAL NOISE FIGURE The point in the Smith Chart at which matching for optimal noise occurs is typically referred to as gamma optimal or ΓOPT. Typically, it is significantly different from the gain matching point; finding ΓOPT is not as obvious as the gain match. ΓOPT is a function of the semiconductor structure and characteristics of the LNA. The fabrication facility that produces the LNA typically has this information. ΓOPT can also be determined by doing source pull testing in the lab. Noise matching for the ADL5523 is actually very easy because the area of the Smith Chart where the noise figure is optimal or near optimal is not confined to a narrow area around ΓOPT. This is very advantageous because it means that component variations play a smaller part in the board-to-board variation of noise figure. The matching area for optimal noise for the ADL5523 is shown in Figure 61. Note that textbooks usually define noise circles as a conjugate match. However, for the purpose of this data sheet, the circle is a direct match. To find the correct matching circuit, the designer must start with the S11 of the LNA and select components that move the S11 to within this circle. An important aspect of the overall ADL5523 ease of tuning is that as long as S22 is matched for a particular frequency, the noise matching area remains very consistent in its placement for that frequency. If S22 is matched, take the measured S11 and move it into the red circle shown in Figure 61 for optimal noise matching. 1 0.5 S11* 0.2 5 10 0.2 0.5 1 5 10 10 S11 06829-058 0.2 5 1 Figure 61. Area of Optimal Noise Matching for ADL5523 Rev. B | Page 19 of 24 06829-059 0.5 Figure 60. Smith Chart Representation of Conjugate Match ADL5523 Data Sheet S11 OF THE LNA WITH S22 MATCHED A shunt capacitor can then be added to move the match along a constant admittance line, down and to the right, directly into the center of the noise circle given in Figure 61. The solution for the structure of the match for the examples in Figure 63 and Figure 64 is a series L to the input of the LNA and a shunt capacitor at the generator end of this inductor. The recommended components for matching at various frequencies are shown in Table 7. An example of the effect of the series L, shunt C match, based on the 800 MHz example, is given in Figure 62. This example uses the output from the Agilent ADS Smith Chart tool. M1 FREQUENCY 400MHz S11 = 0.877/–44.639 IMPEDANCE = Z0 × (0.443 – j2.365) M2 FREQUENCY 2GHz S11 = 0.615/–170.569 IMPEDANCE = Z0 × (0.240 – j0.078) M2 M1 06829-061 To determine the correct matching circuit for optimal noise, look at the results of S11 for the various frequencies at which S22 was tuned earlier in the Tuning S22 section. Once S11 is determined for a particular frequency, find the matching components that provided that match. Figure 63 and Figure 64 show S11 for the various frequencies. Again, these measurements are all based on S22 being matched at that particular frequency. Note that, for the examples shown in Figure 63 and Figure 64, S11 is either in the lower left quadrant of the Smith Chart or slightly into the upper left. To move the impedance in the given noise circle, a series L component at the LNA input is required. The L values in the examples differ but a correct L value moves the match along the constant R circle up into the upper left quadrant of the Smith Chart. FREQUENCY (400MHz TO 4GHz) Figure 63. S11 of ADL5523 with S22 Matched at 2 GHz M1 FREQUENCY 400MHz S11 = 0.864/–40.186 IMPEDANCE = Z0 × (0.594 – j2.615) M2 M2 FREQUENCY 3.2GHz S11 = 0.595/163.164 IMPEDANCE = Z0 × (0.259 + j0.138) FREQUENCY (400MHz TO 4GHz) 06829-060 Figure 64. S11 of ADL5523 with S22 Matched at 3.2 GHz Figure 62. Example of Series L, Shunt C Matching Network for ΓOPT Rev. B | Page 20 of 24 06829-062 M1 Data Sheet ADL5523 OUTLINE DIMENSIONS 0.60 MAX 0.50 BSC 0.60 MAX 5 2.95 2.75 SQ 2.55 TOP VIEW PIN 1 INDICATOR 8 4 12° MAX 0.90 MAX 0.85 NOM 0.05 MAX 0.01 NOM 0.30 0.23 0.18 SEATING PLANE 1 0.50 0.40 0.30 0.70 MAX 0.65 TYP 0.20 REF 1.60 1.45 1.30 EXPOSED PAD (BOTTOM VIEW) 1.89 1.74 1.59 PIN 1 INDICATOR FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 072408-B 3.25 3.00 SQ 2.75 Figure 65. 8-Lead Lead Frame Chip Scale Package [LFCSP_VD] 3 mm × 3 mm Body, Very Thin, Dual Lead (CP-8-2) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADL5523ACPZ-R7 ADL5523-EVALZ 1 Temperature Range −40°C to +85°C Package Description 8-Lead LFCSP_VD, 7” Tape and Reel Evaluation Board Z = RoHS Compliant Part. Rev. B | Page 21 of 24 Package Option CP-8-2 Branding Q1J ADL5523 Data Sheet NOTES Rev. B | Page 22 of 24 Data Sheet ADL5523 NOTES Rev. B | Page 23 of 24 ADL5523 Data Sheet NOTES ©2008–2013 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06829-0-11/13(B) Rev. B | Page 24 of 24