IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide for Software v10.1 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide Table of Contents Introduction . . . . . . . . . . . . . . . . . . . . . .5 AND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AND2A. . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AND2B. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AND3A. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AND3B. . . . . . . . . . . . . . . . . . . . . . . . . . . 14 AND3C . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 AO12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AO13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 AO14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AO15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 AO16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AO17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 AO18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AO1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 AO1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AO1C. . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 AO1D. . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AO1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 AOI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AOI1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 AOI1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AOI1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 AOI1D . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AOI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 AX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AX1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AX1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AX1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 AX1D . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AX1E . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AXO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AXO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 AXO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AXO5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 AXO6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AXO7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 AXOI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AXOI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 AXOI3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AXOI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 AXOI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 AXOI7 . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 BUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 BUFD. . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 CLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DFN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN1C1 . . . . . . . . . . . . . . . . . . . . . . . . . DFN0C1 . . . . . . . . . . . . . . . . . . . . . . . . . DFN1C0 . . . . . . . . . . . . . . . . . . . . . . . . . DFI1C1 . . . . . . . . . . . . . . . . . . . . . . . . . . DFN0C0 . . . . . . . . . . . . . . . . . . . . . . . . . DFI0C1 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0C0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFN1E1 . . . . . . . . . . . . . . . . . . . . . . . . . DFN1E0 . . . . . . . . . . . . . . . . . . . . . . . . . DFN0E0 . . . . . . . . . . . . . . . . . . . . . . . . . DFN1E1C0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1C0 . . . . . . . . . . . . . . . . . . . . . . . DFN1E0C0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E0C0 . . . . . . . . . . . . . . . . . . . . . . . DFN1E1C1 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1C1 . . . . . . . . . . . . . . . . . . . . . . . DFN1E0C1 . . . . . . . . . . . . . . . . . . . . . . . DFN0E0C1 . . . . . . . . . . . . . . . . . . . . . . . DFN1E1P1 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1P1 . . . . . . . . . . . . . . . . . . . . . . . DFN1E0P1 . . . . . . . . . . . . . . . . . . . . . . . DFN0E0P1 . . . . . . . . . . . . . . . . . . . . . . . DFN1E1P0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1P0 . . . . . . . . . . . . . . . . . . . . . . . DFN1E0P0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E0P0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1 . . . . . . . . . . . . . . . . . . . . . . . . . DFN1P1 . . . . . . . . . . . . . . . . . . . . . . . . . DFI1E1 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0E1 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1E0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0E0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1E1C1 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E1C1 . . . . . . . . . . . . . . . . . . . . . . . . DFI1E0C1 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E0C1 . . . . . . . . . . . . . . . . . . . . . . . . DFI1E1C0 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E1C0 . . . . . . . . . . . . . . . . . . . . . . . . DFI1E0C0 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E0C0 . . . . . . . . . . . . . . . . . . . . . . . . DFI1E1P1 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E1P1 . . . . . . . . . . . . . . . . . . . . . . . . 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 2 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide DFI1E0P1 . . . . . . . . . . . . . . . . . . . . . . . . .59 DFI0E0P1 . . . . . . . . . . . . . . . . . . . . . . . . .60 DFI1E1P0 . . . . . . . . . . . . . . . . . . . . . . . . .60 DFI0E1P0 . . . . . . . . . . . . . . . . . . . . . . . . .61 DFI1E0P0 . . . . . . . . . . . . . . . . . . . . . . . . .61 DFI0E0P0 . . . . . . . . . . . . . . . . . . . . . . . . .62 DFN0P1 . . . . . . . . . . . . . . . . . . . . . . . . . .62 DFN1P0 . . . . . . . . . . . . . . . . . . . . . . . . . .63 DFI1P1 . . . . . . . . . . . . . . . . . . . . . . . . . . .63 DFN0P0 . . . . . . . . . . . . . . . . . . . . . . . . . .64 DFI1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . .64 DFI0P1 . . . . . . . . . . . . . . . . . . . . . . . . . . .65 DFI0P0 . . . . . . . . . . . . . . . . . . . . . . . . . . .65 DFN1P1C1 . . . . . . . . . . . . . . . . . . . . . . . .66 DFI1P1C1 . . . . . . . . . . . . . . . . . . . . . . . . .66 DFN0P1C1 . . . . . . . . . . . . . . . . . . . . . . . .67 DFI0P1C1 . . . . . . . . . . . . . . . . . . . . . . . . .67 DLN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 DLI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 DLN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 DLI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 DLN1C0 . . . . . . . . . . . . . . . . . . . . . . . . . .70 DLN1C1 . . . . . . . . . . . . . . . . . . . . . . . . . .70 DLN0C1 . . . . . . . . . . . . . . . . . . . . . . . . . .71 DLI1C1 . . . . . . . . . . . . . . . . . . . . . . . . . .71 DLI0C1 . . . . . . . . . . . . . . . . . . . . . . . . . . .72 DLN0C0 . . . . . . . . . . . . . . . . . . . . . . . . . .72 DLI1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . .73 DLI0C0 . . . . . . . . . . . . . . . . . . . . . . . . . . .73 DLN1P1 . . . . . . . . . . . . . . . . . . . . . . . . . .74 DLN0P1 . . . . . . . . . . . . . . . . . . . . . . . . . .74 DLN1P0 . . . . . . . . . . . . . . . . . . . . . . . . . .75 DLN0P0 . . . . . . . . . . . . . . . . . . . . . . . . . .75 DLI1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . .76 DLI0P0 . . . . . . . . . . . . . . . . . . . . . . . . . . .76 DLI1P1 . . . . . . . . . . . . . . . . . . . . . . . . . . .77 DLI0P1 . . . . . . . . . . . . . . . . . . . . . . . . . . .77 DLN1P1C1 . . . . . . . . . . . . . . . . . . . . . . . .78 DLI1P1C1 . . . . . . . . . . . . . . . . . . . . . . . . .78 DLN0P1C1 . . . . . . . . . . . . . . . . . . . . . . . .79 DLI0P1C1 . . . . . . . . . . . . . . . . . . . . . . . . .79 GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 INV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MAJ3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MAJ3X . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 MAJ3XI . . . . . . . . . . . . . . . . . . . . . . . . . . 82 MIN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 MIN3X . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 MIN3XI. . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MX2A. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 MX2B. . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 MX2C. . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 NAND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 NAND2A. . . . . . . . . . . . . . . . . . . . . . . . . . 87 NAND2B. . . . . . . . . . . . . . . . . . . . . . . . . . 87 NAND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 NAND3A. . . . . . . . . . . . . . . . . . . . . . . . . . 88 NAND3B. . . . . . . . . . . . . . . . . . . . . . . . . . 89 NAND3C . . . . . . . . . . . . . . . . . . . . . . . . . 89 NOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 NOR2A. . . . . . . . . . . . . . . . . . . . . . . . . . . 90 NOR2B. . . . . . . . . . . . . . . . . . . . . . . . . . . 91 NOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 NOR3A. . . . . . . . . . . . . . . . . . . . . . . . . . . 92 NOR3B. . . . . . . . . . . . . . . . . . . . . . . . . . . 92 NOR3C. . . . . . . . . . . . . . . . . . . . . . . . . . . 93 OA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 OA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 OA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 OA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 OAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 OR2A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 OR2B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 OR3A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 OR3B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 OR3C . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 XA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 XA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 XA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 XA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 XAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 XAI1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 XNOR2. . . . . . . . . . . . . . . . . . . . . . . . . . 103 XNOR3. . . . . . . . . . . . . . . . . . . . . . . . . . 103 XO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 XO1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 XOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 XOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 ZOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 ZOR3I. . . . . . . . . . . . . . . . . . . . . . . . . . . 106 RAM4K9 and RAM512X18 . . . . . . . . . . 108 FLEXRAM4K9 and FLEXRAM512X18 . 111 FIFO4K18 . . . . . . . . . . . . . . . . . . . . . . . 114 Flash Memory Block. . . . . . . . . . . . . . . . 117 Analog System Builder. . . . . . . . . . . . . . 121 Voltage Regulator and Power Supply Monitor (VRPSM) . . . . . . . . . . . . . . . . . . . . . . . . 136 BIBUF. . . . . . . . . . . . . . . . . . . . . . . . . . . 139 CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . 139 CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . 140 INBUF . . . . . . . . . . . . . . . . . . . . . . . . . . 140 OUTBUF . . . . . . . . . . . . . . . . . . . . . . . . 141 TRIBUFF . . . . . . . . . . . . . . . . . . . . . . . . 141 3 Table of Contents INBUF_X . . . . . . . . . . . . . . . . . . . . . . . . BIBUF_X . . . . . . . . . . . . . . . . . . . . . . . . CLKBUF_X . . . . . . . . . . . . . . . . . . . . . . OUTBUF_X . . . . . . . . . . . . . . . . . . . . . . TRIBUFF_X . . . . . . . . . . . . . . . . . . . . . . INBUF_LVDS; INBUF_LVPECL . . . . . . CLKBUF_LVDS; CLKBUF_LVPECL . . . OUTBUF_LVDS; OUTBUF_LVPECL . . BIBUF_LVDS. . . . . . . . . . . . . . . . . . . . . TRIBUFF_LVDS . . . . . . . . . . . . . . . . . . SIMBUF . . . . . . . . . . . . . . . . . . . . . . . . . DDR_REG . . . . . . . . . . . . . . . . . . . . . . . DDR_OUT . . . . . . . . . . . . . . . . . . . . . . . PLL for ProASIC3 / IGLOO . . . . . . . . . . PLL for Fusion . . . . . . . . . . . . . . . . . . . . 142 144 146 148 150 152 152 153 153 154 154 155 155 157 159 A Product Support . . . . . . . . . . . . . . . . .172 4 DYNCCC for IGLOO and ProASIC3 . . . FAB_CCC . . . . . . . . . . . . . . . . . . . . . . . FAB_CCC_DYN. . . . . . . . . . . . . . . . . . . PLLINT . . . . . . . . . . . . . . . . . . . . . . . . . . UJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . UFROM . . . . . . . . . . . . . . . . . . . . . . . . . UFROMH . . . . . . . . . . . . . . . . . . . . . . . . ULSICC . . . . . . . . . . . . . . . . . . . . . . . . . RCOSC . . . . . . . . . . . . . . . . . . . . . . . . . XTLOSC. . . . . . . . . . . . . . . . . . . . . . . . . CLKSRC. . . . . . . . . . . . . . . . . . . . . . . . . CLKDLY . . . . . . . . . . . . . . . . . . . . . . . . . CLKDIVDLY . . . . . . . . . . . . . . . . . . . . . . CLKDIVDLY1 . . . . . . . . . . . . . . . . . . . . . NGMUX . . . . . . . . . . . . . . . . . . . . . . . . . 161 162 164 166 166 167 167 168 168 169 169 170 170 171 171 Introduction This macro library guide supports only the IGLOO, ProASIC3, SmartFusion and Fusion families. IGLOO indicates IGLOO nano, IGLOO PLUS, IGLOO and IGLOOe families; ProASIC3 indicates ProASIC3 nano, ProASIC3E, ProASIC3L and ProASIC3 families. For information on macros available in other familes, see the appropriate Macro Library Guide. ProASIC3 introduced a new naming convention for sequential macros that is unambiguous and extensible, making it possible to understand the function of the macros by their name alone. The first two mandatory characters of the macro name will indicate the basic macro function: • DF - D-type flip-flop • TF - Toggle flip-flop • JF - JK flip-flop • DL - D-type latch The next mandatory character indicates the output polarity: • I - output inverted (QN with bubble) • N - output non-inverted (Q without bubble) The next mandatory number indicates the polarity of the clock or gate: • 1 - rising edge triggered flip-flop or transparent high latch (non-bubbled) • 0 - falling edge triggered flip-flop or transparent low latch (bubbled) The next two optional characters indicate the polarity of the Enable pin, if present: • E0 - active low enable (bubbled) • E1 - active high enable (non-bubbled) The next two optional characters indicate the polarity of the asynchronous Preset pin, if present: • P0 - active low preset (bubbled) • P1 - active high preset (non-bubbled) The next two optional characters indicate the polarity of the asynchronous Clear pin, if present: • C0 - active low preset (bubbled) • C1 - active high preset (non-bubbled) Combinatorial macros all use one tile in the SmartFusion, Fusion and ProASIC3 families. 5 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide List of Combinational Macros AND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 AND2A . . . . . . . . . . . . . . . . . . . . . . . . . . .12 AND2B . . . . . . . . . . . . . . . . . . . . . . . . . . .13 AND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 AND3A . . . . . . . . . . . . . . . . . . . . . . . . . . .14 AND3B . . . . . . . . . . . . . . . . . . . . . . . . . . .14 AND3C . . . . . . . . . . . . . . . . . . . . . . . . . . .15 AO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 AO12 . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 AO13 . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 AO14 . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 AO15 . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 AO16 . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AO17 . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 AO18 . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 AO1A . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 AO1B . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 AO1C . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 AO1D . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 AO1E . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 AOI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 AOI1A . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 AOI1B . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 AOI1C . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 AOI1D . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 AOI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 AX1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 AX1A . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 AX1B . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 AX1C . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 AX1D . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 AX1E . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 AXO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 AXO2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 AXO3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 AXO5 . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 AXO6 . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 AXO7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 AXOI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 AXOI2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 AXOI3 . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 AXOI4 . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 AXOI5 . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 AXOI7 . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 BUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 BUFD . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 CLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . .35 GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 INV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MAJ3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 MAJ3X . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 MAJ3XI . . . . . . . . . . . . . . . . . . . . . . . . . . 82 MIN3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 MIN3X . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 MIN3XI . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 MX2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 MX2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 MX2C . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 NAND2 . . . . . . . . . . . . . . . . . . . . . . . . . . 86 NAND2A . . . . . . . . . . . . . . . . . . . . . . . . . 87 NAND2B . . . . . . . . . . . . . . . . . . . . . . . . . 87 NAND3 . . . . . . . . . . . . . . . . . . . . . . . . . . 88 NAND3A . . . . . . . . . . . . . . . . . . . . . . . . . 88 NAND3B . . . . . . . . . . . . . . . . . . . . . . . . . 89 NAND3C . . . . . . . . . . . . . . . . . . . . . . . . . 89 NOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 NOR2A . . . . . . . . . . . . . . . . . . . . . . . . . . 90 NOR2B . . . . . . . . . . . . . . . . . . . . . . . . . . 91 NOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 NOR3A . . . . . . . . . . . . . . . . . . . . . . . . . . 92 NOR3B . . . . . . . . . . . . . . . . . . . . . . . . . . 92 NOR3C . . . . . . . . . . . . . . . . . . . . . . . . . . 93 OA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 OA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 OA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 OA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 OAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 OR2A . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 OR2B . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 OR3A . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 OR3B . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 OR3C . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 XA1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 XA1A . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 XA1B . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 XA1C . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 XAI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 XAI1A . . . . . . . . . . . . . . . . . . . . . . . . . . 102 XNOR2 . . . . . . . . . . . . . . . . . . . . . . . . . 103 XNOR3 . . . . . . . . . . . . . . . . . . . . . . . . . 103 XO1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Revision 3 6 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide XO1A XOR2 XOR3 ZOR3 ZOR3I . . . . . . . . . . . . . . . . . . . . . . . . . . .104 . . . . . . . . . . . . . . . . . . . . . . . . . . .105 . . . . . . . . . . . . . . . . . . . . . . . . . . .105 . . . . . . . . . . . . . . . . . . . . . . . . . . .106 . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Revision 3 7 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide List of Sequential Macros DFN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN1C1. . . . . . . . . . . . . . . . . . . . . . . . . . DFN0C1. . . . . . . . . . . . . . . . . . . . . . . . . . DFN1C0. . . . . . . . . . . . . . . . . . . . . . . . . . DFI1C1 . . . . . . . . . . . . . . . . . . . . . . . . . . DFN0C0. . . . . . . . . . . . . . . . . . . . . . . . . . DFI0C1 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0C0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFN1E1. . . . . . . . . . . . . . . . . . . . . . . . . . DFN1E0. . . . . . . . . . . . . . . . . . . . . . . . . . DFN0E0. . . . . . . . . . . . . . . . . . . . . . . . . . DFN1E1C0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1C0 . . . . . . . . . . . . . . . . . . . . . . . DFN1E0C0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E0C0 . . . . . . . . . . . . . . . . . . . . . . . DFN1E1C1 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1C1 . . . . . . . . . . . . . . . . . . . . . . . DFN1E0C1 . . . . . . . . . . . . . . . . . . . . . . . DFN0E0C1 . . . . . . . . . . . . . . . . . . . . . . . DFN1E1P1 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1P1 . . . . . . . . . . . . . . . . . . . . . . . DFN1E0P1 . . . . . . . . . . . . . . . . . . . . . . . DFN0E0P1 . . . . . . . . . . . . . . . . . . . . . . . DFN1E1P0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1P0 . . . . . . . . . . . . . . . . . . . . . . . DFN1E0P0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E0P0 . . . . . . . . . . . . . . . . . . . . . . . DFN0E1. . . . . . . . . . . . . . . . . . . . . . . . . . DFN1P1. . . . . . . . . . . . . . . . . . . . . . . . . . DFI1E1 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0E1 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1E0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0E0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1E1C1 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E1C1 . . . . . . . . . . . . . . . . . . . . . . . . DFI1E0C1 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E0C1 . . . . . . . . . . . . . . . . . . . . . . . . DFI1E1C0 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E1C0 . . . . . . . . . . . . . . . . . . . . . . . . DFI1E0C0 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E0C0 . . . . . . . . . . . . . . . . . . . . . . . . DFI1E1P1 . . . . . . . . . . . . . . . . . . . . . . . . DFI0E1P1 . . . . . . . . . . . . . . . . . . . . . . . . DFI1E0P1 . . . . . . . . . . . . . . . . . . . . . . . . 36 36 37 37 38 38 39 39 40 40 41 41 42 42 43 43 44 44 45 45 46 46 47 47 48 48 49 49 50 50 51 51 52 52 53 53 54 54 55 55 56 56 57 57 58 58 59 59 DFI0E0P1. . . . . . . . . . . . . . . . . . . . . . . . . DFI1E1P0. . . . . . . . . . . . . . . . . . . . . . . . . DFI0E1P0. . . . . . . . . . . . . . . . . . . . . . . . . DFI1E0P0. . . . . . . . . . . . . . . . . . . . . . . . . DFI0E0P0. . . . . . . . . . . . . . . . . . . . . . . . . DFN0P1 . . . . . . . . . . . . . . . . . . . . . . . . . . DFN1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN0P0 . . . . . . . . . . . . . . . . . . . . . . . . . . DFI1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . DFI0P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . DFN1P1C1. . . . . . . . . . . . . . . . . . . . . . . . DFI1P1C1 . . . . . . . . . . . . . . . . . . . . . . . . DFN0P1C1. . . . . . . . . . . . . . . . . . . . . . . . DFI0P1C1 . . . . . . . . . . . . . . . . . . . . . . . . DLN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLI1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLN0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLI0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DLN1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . DLN1C1 . . . . . . . . . . . . . . . . . . . . . . . . . . DLN0C1 . . . . . . . . . . . . . . . . . . . . . . . . . . DLI1C1 . . . . . . . . . . . . . . . . . . . . . . . . . . DLI0C1 . . . . . . . . . . . . . . . . . . . . . . . . . . . DLN0C0 . . . . . . . . . . . . . . . . . . . . . . . . . . DLI1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . DLI0C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . DLN1P1 . . . . . . . . . . . . . . . . . . . . . . . . . . DLN0P1 . . . . . . . . . . . . . . . . . . . . . . . . . . DLN1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . DLN0P0 . . . . . . . . . . . . . . . . . . . . . . . . . . DLI1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . DLI0P0 . . . . . . . . . . . . . . . . . . . . . . . . . . . DLI1P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . DLI0P1 . . . . . . . . . . . . . . . . . . . . . . . . . . . DLN1P1C1 . . . . . . . . . . . . . . . . . . . . . . . . DLI1P1C1. . . . . . . . . . . . . . . . . . . . . . . . . DLN0P1C1 . . . . . . . . . . . . . . . . . . . . . . . . DLI0P1C1. . . . . . . . . . . . . . . . . . . . . . . . . Revision 3 60 60 61 61 62 62 63 63 64 64 65 65 66 66 67 67 68 68 69 69 70 70 71 71 72 72 73 73 74 74 75 75 76 76 77 77 78 78 79 79 8 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide List of RAM Macros RAM4K9 and RAM512X18 . . . . . . . . . . 108 FLEXRAM4K9 and FLEXRAM512X18 . 111 FIFO4K18 . . . . . . . . . . . . . . . . . . . . . . . 114 Revision 3 9 IGLOO, ProASIC3, SmartFusion and Fusion Macro Library Guide List of Input/Output Macros Flash Memory Block . . . . . . . . . . . . . . . 117 Analog System Builder . . . . . . . . . . . . . 121 Voltage Regulator and Power Supply Monitor (VRPSM) . . . . . . . . . . . . . . . . . . . . . . . . 136 BIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . 139 CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . 139 CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . 140 INBUF . . . . . . . . . . . . . . . . . . . . . . . . . . 140 OUTBUF . . . . . . . . . . . . . . . . . . . . . . . . 141 TRIBUFF . . . . . . . . . . . . . . . . . . . . . . . . 141 INBUF_X . . . . . . . . . . . . . . . . . . . . . . . . 142 BIBUF_X . . . . . . . . . . . . . . . . . . . . . . . . 144 CLKBUF_X . . . . . . . . . . . . . . . . . . . . . . 146 OUTBUF_X . . . . . . . . . . . . . . . . . . . . . . 148 TRIBUFF_X . . . . . . . . . . . . . . . . . . . . . . 150 INBUF_LVDS; INBUF_LVPECL . . . . . . 152 CLKBUF_LVDS; CLKBUF_LVPECL . . . 152 OUTBUF_LVDS; OUTBUF_LVPECL . . 153 BIBUF_LVDS. . . . . . . . . . . . . . . . . . . . . 153 TRIBUFF_LVDS . . . . . . . . . . . . . . . . . . 154 SIMBUF . . . . . . . . . . . . . . . . . . . . . . . . . 154 DDR_REG . . . . . . . . . . . . . . . . . . . . . . . 155 DDR_OUT . . . . . . . . . . . . . . . . . . . . . . . 155 PLL for ProASIC3 / IGLOO . . . . . . . . . . 157 PLL for Fusion . . . . . . . . . . . . . . . . . . . . 159 DYNCCC for IGLOO and ProASIC3 . . . 161 FAB_CCC . . . . . . . . . . . . . . . . . . . . . . . 162 FAB_CCC_DYN . . . . . . . . . . . . . . . . . . 164 PLLINT . . . . . . . . . . . . . . . . . . . . . . . . . 166 UJTAG. . . . . . . . . . . . . . . . . . . . . . . . . . 166 UFROM . . . . . . . . . . . . . . . . . . . . . . . . . 167 UFROMH. . . . . . . . . . . . . . . . . . . . . . . . 167 ULSICC . . . . . . . . . . . . . . . . . . . . . . . . . 168 RCOSC . . . . . . . . . . . . . . . . . . . . . . . . . 168 XTLOSC . . . . . . . . . . . . . . . . . . . . . . . . 169 CLKSRC . . . . . . . . . . . . . . . . . . . . . . . . 169 CLKDLY. . . . . . . . . . . . . . . . . . . . . . . . . 170 CLKDIVDLY. . . . . . . . . . . . . . . . . . . . . . 170 CLKDIVDLY1. . . . . . . . . . . . . . . . . . . . . 171 NGMUX . . . . . . . . . . . . . . . . . . . . . . . . . 171 Revision 3 10 Combinational/Sequential Macros Macro Library Guide 11 Combinational, AND AND2 IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input AND Truth Table A Y B A B Y X 0 0 0 X 0 1 1 1 Output Y Input A, B Family Tiles All 1 AND2A IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input AND with active low A Input Truth Table A Y B Output Y Input A, B 12 Family Tiles All 1 A B X 0 Y 0 0 1 1 1 X 0 AND2B IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input AND with active low Inputs Truth Table A Y B A B Y 0 0 1 X 1 0 1 X 0 Output Y Input A, B Family Tiles All 1 AND3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND A Truth Table B Y C A B C X X 0 Y 0 X 0 X 0 0 X X 0 1 1 1 1 Output Y Input A, B,C Family Tiles All 1 Macro Library Guide 13 AND3A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND with active low A-Input A Truth Table A B Y C B C Y X X 0 0 X 0 X 0 0 1 1 1 1 X X 0 Output Y Input A, B, C Family Tiles All 1 AND3B IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND with active low A- and B-Inputs A Truth Table B Y C Output Y Input A, B,C 14 Family Tiles All 1 A B C X X 0 Y 0 0 0 1 1 X 1 X 0 1 X X 0 AND3C IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND with active low Inputs A Truth Table B Y C A B C Y 0 0 0 1 X X 1 0 X 1 X 0 1 X X 0 Output Y Input A, B, C Family Tiles All 1 Combinational AO1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR Truth Table A A B Y C B C Y X 0 0 0 X X 1 1 0 X 0 0 1 1 X 1 Output Y Input A, B, C Family Tiles All 1 Macro Library Guide 15 Combinational, AND-OR AO12 IGLOO, ProASIC3, SmartFusion, Fusion Function A 3-Input AND-OR B Truth Table C Y Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 0 AO13 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR A B Truth Table Y C Output Y Input A, B, C 16 Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 1 AO14 IGLOO, ProASIC3, SmartFusion, Fusion Function A 3-Input AND-OR B Truth Table C Y Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 1 AO15 IGLOO, ProASIC3, SmartFusion, Fusion Function A 3-Input AND-OR B C Truth Table Y Output Y Input A, B, C Family Tiles All 1 Macro Library Guide A B C Y 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 0 17 AO16 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR A B Truth Table C Y Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 0 AO17 IGLOO, ProASIC3, SmartFusion, Fusion Function A 3-Input AND-OR B C Truth Table Y Output Y Input A, B, C 18 Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 1 AO18 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR A B Truth Table Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 0 AO1A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR with active low A-Input A Truth Table B Y C A B C Y X 0 0 0 X X 1 1 0 1 X 1 1 X 0 0 Output Y Input A, B, C Family Tiles All 1 Macro Library Guide 19 AO1B IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR with active low C-Input A Truth Table B A B X X 0 1 X 0 1 0 0 X 1 0 1 1 X 1 Y C C Y Output Y Input A, B, C Family Tiles All 1 AO1C IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR with active low A- and C-Inputs A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 Combinational, AND-OR-INVERT 20 A B C X X 0 Y 1 X 0 1 0 0 1 X 1 1 X 1 0 AO1D IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR with active low A- and B-Inputs A Truth Table B Y C A B C Y 0 0 X 1 X 1 0 0 X X 1 1 1 X 0 0 Output Y Input A, B, C Family Tiles All 1 AO1E IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR with active low Inputs A Truth Table B Y C A B C X X 0 Y 1 0 0 X 1 X 1 1 0 1 X 1 0 Output Y Input A, B, C Family Tiles All 1 Combinational, AND-OR-INVERT Combinational, AND-XOR Combinational, AND-XOR-INVERT Macro Library Guide 21 AOI1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR-INVERT A Truth Table B Y C A B C Y X 0 0 1 X X 1 0 0 X 0 1 1 1 X 0 Output Y Input A, B, C Family Tiles All 1 AOI1A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR-INVERT with active low A-Input A Truth Table A B Y C Output Y Input A, B, C 22 Family Tiles All 1 B C Y X 0 0 1 X X 1 0 0 1 X 0 1 X 0 1 AOI1B IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR-INVERT with active low C-Input A Truth Table B Y C A B C X X 0 Y 0 X 0 1 1 0 X 1 1 1 1 X 0 Output Y Input A, B, C Family Tiles All 1 AOI1C IGLOO, ProASIC3, SmartFusion, Fusion Function 3 Input AND-OR-INVERT with active low A- and B-Inputs A Truth Table B Y C A B C Y 0 0 X 0 X 1 0 1 X X 1 0 1 X 0 1 Output Y Input A, B, C Family Tiles All 1 Combinational, 3-Input Gate Macro Library Guide 23 AOI1D IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR-INVERT with active low Inputs A Truth Table B Y C A B C X X 0 Y 0 0 0 X 0 X 1 1 1 1 X 1 1 Output Y Input A, B, C Family Tiles All 1 AOI5 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-OR-INVERT A B C Truth Table Y Output Y Input A, B, C 24 Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 AX1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-XOR with active low A-Input A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y X 0 0 0 X 0 1 1 0 1 0 1 0 1 1 0 1 X 0 0 1 X 1 1 AX1A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-XOR-INVERT with active low A-Input A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 Macro Library Guide A B C Y X 0 0 1 X 0 1 0 0 1 0 0 0 1 1 1 1 X 0 1 1 X 1 0 25 AX1B IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-XOR with active low A- and B-Inputs A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 0 0 1 0 X 1 0 0 X 1 1 1 1 X 0 0 1 X 1 1 AX1C IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-XOR A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 Buffers 26 A B C Y X 0 0 0 X 0 1 1 0 X 0 0 0 X 1 1 1 1 0 1 1 1 1 0 AX1D IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-XNOR A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 0 AX1E IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input AND-XNOR A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 1 Clock Interface Macro Library Guide 27 AXO1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 1 AXO2 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C 28 Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 AXO3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 AXO5 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 Macro Library Guide A B C Y 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 29 AXO6 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 AXO7 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C 30 Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 0 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 AXOI1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 0 AXOI2 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 Macro Library Guide A B C Y 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 1 31 AXOI3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A B Truth Table Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 AXOI4 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C 32 Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 AXOI5 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 0 1 1 1 0 AXOI7 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input Combinatorial Gate A Truth Table B Y C Output Y Input A, B, C Family Tiles All 1 Macro Library Guide A B C Y 0 0 0 0 1 0 0 1 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 1 1 1 1 1 33 BUFF IGLOO, ProASIC3, SmartFusion, Fusion Function Buffer Truth Table A Y A Y 0 0 1 1 Output Y Input A Family Tiles All 1 BUFD IGLOO, ProASIC3, SmartFusion, Fusion Function Buffer NOTE: The Combiner will not remove this macro A Y Output Y Input A 34 Family Tiles All 1 Truth Table A Y 0 0 1 1 CLKINT IGLOO, ProASIC3, SmartFusion, Fusion Function Internal Clock Interface A Input A Y Truth Table A Y 0 0 1 1 Output Y NOTE: CLKINT does not use any tiles. For more information on the Global Clock Network, refer to the latest Actel datasheet. Macro Library Guide 35 Sequential, D-Type Flip-Flop DFN1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop D Q Truth Table CLK Qn+1 D CLK Output Q Input D, CLK Family Tiles All 1 DFI1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with inverted Output QN D CLK Output QN Input D, CLK 36 Family Tiles All 1 Truth Table CLK QNn+1 !D DFN0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Clock Q D Truth Table CLK Qn+1 D CLK Output Q Input D, CLK Family Tiles All 1 DFI0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Clock and inverted Output D QN Truth Table CLK CLK QNn+1 !D Output QN Input D, CLK Family Tiles All 1 Macro Library Guide 37 DFN1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Clear Q D Truth Table CLK CLR CLR CLK Qn+1 1 X 0 0 D Output Q Input CLR, D, CLK Family Tiles All 1 DFN0C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Q D D-Type Flip-Flop with active high Clear and active low Clock Truth Table CLK CLR Output Q Input CLR, D, CLK 38 Family Tiles All 1 CLR CLK Qn+1 1 X 0 0 D IGLOO, ProASIC3, SmartFusion, Fusion ACT 1, ACT 2/1200XL, ACT 3, 3200DX, 40MX, 42MX, 54SX, Sxa DFN1C0 Function D-Type Flip-Flop with active low Clear Q D Truth Table CLK CLR CLR CLK Qn+1 0 X 0 1 D Output Q Input CLR, D, CLK Family Tiles All 1 DFI1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Clear and Clock QN D Truth Table CLK CLR CLR CLK QNn+1 1 X 1 0 !D Output QN Input CLR, D, CLK Family Tiles All 1 Macro Library Guide 39 IGLOO, ProASIC3, SmartFusion, Fusion DFN0C0 Function D-Type Flip-Flop with active low Clear and Clock Q D Truth Table CLK CLR CLR CLK Qn+1 0 X 0 1 D Output Q Input CLR, D, CLK Family Tiles All 1 DFI0C1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Clear, active low Clock and inverted Output QN D Truth Table CLK CLR Output QN Input CLR, D, CLK 40 Family Tiles All 1 CLR CLK QNn+1 1 X 1 0 !D DFI1C0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Clear and inverted Output QN D Truth Table CLK CLR CLR CLK QNn+1 0 X 1 1 !D Output QN Input CLR, D, CLK Family Tiles All 1 DFI0C0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Clear, Clock and inverted Output D QN Truth Table CLK CLR CLR CLK QN 0 X 1 1 !D Output QN Input CLR, D, CLK Family Tiles All 1 Macro Library Guide 41 Sequential D-Type Flip-Flop with Inverted Output DFN1E1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable Q D E CLK Truth Table E CLK Qn+1 0 X Q 1 D Output Q Input D, E, CLK Family Tiles All 1 IGLOO, ProASIC3, SmartFusion, Fusion DFN1E0 Function D-Type Flip-Flop with active low Enable D Q E CLK Output Q Input D, E, CLK 42 Family Tiles All 1 Truth Table E CLK Qn+1 1 X Q 0 D IGLOO, ProASIC3, SmartFusion, Fusion DFN0E0 Function D-Type Flip-Flop with active low Enable and Clock D Q Truth Table E CLK Qn+1 1 X Q 0 D E CLK Output Q Input D, E, CLK Family Tiles All 1 DFN1E1C0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop, with Enable and active low Clear D Q E CLK CLR Truth Table CLR E CLK Qn+1 0 X X 0 1 0 X Q 1 1 D Output Q Input CLR, D, E, CLK Family Tiles All 1 Macro Library Guide 43 DFN0E1C0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with Enable and active low Clear and Clock D Q E CLK CLR Truth Table CLR E CLK Qn+1 0 X X 0 1 0 X Q 1 1 D Output Q Input CLR, D, E, CLK Family Tiles All 1 IGLOO, ProASIC3, SmartFusion, Fusion DFN1E0C0 Function D-Type Flip-Flop with Active Low Enable and Clear Q D E CLK CLR Output Q Input CLR, D, E, CLK 44 Family Tiles All 1 Truth Table CLR E CLK Qn+1 0 X X 0 1 1 X Q 1 0 D IGLOO, ProASIC3, SmartFusion, Fusion DFN0E0C0 Function D-Type Flip-Flop with active low Enable, Clear and Clock D Q E CLK CLR Truth Table CLR E CLK Qn+1 0 X X 0 1 1 X Q 1 0 D Output Q Input CLR, D, E, CLK Family Tiles All 1 DFN1E1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop, with Enable and active high Clear D Q E CLK CLR Truth Table CLR E CLK Qn+1 1 X X 0 0 0 X Q 0 1 D Output Q Input CLR, D, E, CLK Family Tiles All 1 Macro Library Guide 45 DFN0E1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with Enable and active high Clear and active low Clock D Q Truth Table E CLK CLR CLR E CLK Qn+1 1 X X 0 0 0 X Q 0 1 D Output Q Input CLR, D, E, CLK Family Tiles All 1 IGLOO, ProASIC3, SmartFusion, Fusion DFN1E0C1 Function D-Type Flip-Flop with Active Low Enable and active high Clear Q D E CLK CLR Output Q Input CLR, D, E, CLK 46 Family Tiles All 1 Truth Table CLR E CLK Qn+1 1 X X 0 0 1 X Q 0 0 D IGLOO, ProASIC3, SmartFusion, Fusion DFN0E0C1 Function D-Type Flip-Flop with active low Enable, Clock and active high Clear D Q E CLK CLR Truth Table CLR E CLK Qn+1 1 X X 0 0 1 X Q 0 0 D Output Q Input CLR, D, E, CLK Family Tiles All 1 DFN1E1P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable and Preset Truth Table PRE D Q E CLK PRE E CLK Qn+1 1 X X 1 0 0 X Q 0 1 D Output Q Input D, E, PRE, CLK Family Tiles All 1 Macro Library Guide 47 DFN0E1P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable and Preset, and active low Clock PRE D Q Truth Table PRE E CLK 1 X X 1 0 0 X Q 0 1 D E CLK Qn+1 Output Q Input D, E, PRE, CLK Family Tiles All 1 DFN1E0P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Enable, and active high Preset Truth Table PRE D Q E CLK Output Q Input D, E, PRE, CLK 48 Family Tiles All 1 PRE E CLK Qn+1 1 X X 1 0 1 X Q 0 0 D DFN0E0P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Enable and Clock, and active high Preset PRE Q D E CLK Truth Table PRE E CLK Qn+1 1 X X 1 0 1 X Q 0 0 D Output Q Input D, E, PRE, CLK Family Tiles All 1 DFN1E1P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable and active low Preset Truth Table PRE D Q E CLK PRE E CLK Qn+1 0 X X 1 1 0 X Q 1 1 D Output Q Input D, E, PRE, CLK Family Tiles All 1 Macro Library Guide 49 DFN0E1P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable and active low Preset and Clock PRE D Q Truth Table PRE E CLK Qn+1 0 X X 1 1 0 X Q 1 1 D E CLK Output Q Input D, E, PRE, CLK Family Tiles All 1 DFN1E0P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Enable and Preset Truth Table PRE D Q E CLK Output Q Input D, E, PRE, CLK 50 Family Tiles All 1 PRE E CLK Qn+1 0 X X 1 1 1 X Q 1 0 D DFN0E0P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Enable, Clock, and Preset Truth Table PRE Q D E CLK PRE E CLK Qn+1 0 X X 1 1 1 X Q 1 0 D Output Q Input D, E, PRE, CLK Family Tiles All 1 DFN0E1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop, with Enable, and active low Clock Q D E CLK Truth Table E CLK Qn+1 0 X Q 1 D Output Q Input D, E, CLK Family Tiles All 1 Macro Library Guide 51 Sequential, D-Type Flip-Flop DFN1P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Preset Truth Table PRE Q D PRE CLK Qn+1 1 X 1 0 D CLK Output Q Input D, PRE, CLK Family Tiles All 1 DFI1E1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable and inverted output QN D E CLK Output QN Input D, E, CLK 52 Family Tiles All 1 Truth Table E CLK QNn+1 0 X QN 1 !D DFI0E1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop, with Enable, and active low Clock and inverted ouput QN D E CLK Truth Table E CLK QNn+1 0 X QN 1 !D Output QN Input D, E, CLK Family Tiles All 1 IGLOO, ProASIC3, SmartFusion, Fusion DFI1E0 Function D-Type Flip-Flop with active low Enable and inverted output D QN E CLK Truth Table E CLK QNn+1 1 X QN 0 !D Output QN Input D, E, CLK Family Tiles All 1 Macro Library Guide 53 IGLOO, ProASIC3, SmartFusion, Fusion DFI0E0 Function D-Type Flip-Flop with active low Enable and Clock and inverted output D QN E Truth Table E CLK QNn+1 1 X QN 0 !D CLK Output QN Input D, E, CLK Family Tiles All 1 DFI1E1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop, with Enable and active high Clear and inverted output D QN Truth Table E CLK CLR Output QN Input CLR, D, E, CLK 54 Family Tiles All 1 CLR E CLK QNn+1 1 X X 1 0 0 X QN 0 1 !D DFI0E1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with Enable and active high Clear and active low Clock and inverted output D QN Truth Table E CLK CLR CLR E CLK QNn+1 1 X X 1 0 0 X QN 0 1 !D Output QN Input CLR, D, E, CLK Family Tiles All 1 IGLOO, ProASIC3, SmartFusion, Fusion DFI1E0C1 Function D-Type Flip-Flop with Active Low Enable and anctive high Clear and inverted output QN D Truth Table E CLK CLR CLR E CLK QNn+1 1 X X 1 0 1 X QN 0 0 !D Output QN Input CLR, D, E, CLK Family Tiles All 1 Macro Library Guide 55 IGLOO, ProASIC3, SmartFusion, Fusion DFI0E0C1 Function D-Type Flip-Flop with active low Enable, Clock, active high Clear, and inverted output QN D Truth Table E CLK CLR CLR E CLK QNn+1 1 X X 1 0 1 X QN 0 0 !D Output QN Input CLR, D, E, CLK Family Tiles All 1 DFI1E1C0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop, with Enable and active low Clear and inverted output D QN Truth Table E CLK CLR Output QN Input CLR, D, E, CLK 56 Family Tiles All 1 CLR E CLK QNn+1 0 X X 1 1 0 X QN 1 1 !D DFI0E1C0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with Enable and active low Clear and Clock and inverted output D QN Truth Table E CLK CLR CLR E CLK QNn+1 0 X X 1 1 0 X QN 1 1 !D Output QN Input CLR, D, E, CLK Family Tiles All 1 IGLOO, ProASIC3, SmartFusion, Fusion DFI1E0C0 Function D-Type Flip-Flop with Active Low Enable and Clear and inverted output QN D Truth Table E CLK CLR CLR E CLK QNn+1 0 X X 1 1 1 X QN 1 0 !D Output QN Input CLR, D, E, CLK Family Tiles All 1 Macro Library Guide 57 IGLOO, ProASIC3, SmartFusion, Fusion DFI0E0C0 Function D-Type Flip-Flop with active low Enable, Clear, Clock and inverted output D QN Truth Table E CLK CLR CLR E CLK QNn+1 0 X X 1 1 1 X QN 1 0 !D Output QN Input CLR, D, E, CLK Family Tiles All 1 DFI1E1P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable and Preset and inverted output PRE D QN E CLK Output QN Input D, E, PRE, CLK 58 Family Tiles All 1 Truth Table PRE E CLK QNn+1 1 X X 0 0 0 X QN 0 1 !D DFI0E1P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable and Preset, active low Clock and inverted output PRE D QN Truth Table PRE E CLK QNn+1 1 X X 0 0 0 X QN 0 1 !D E CLK Output QN Input D, E, PRE, CLK Family Tiles All 1 DFI1E0P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Enable, active high Preset and inverted output PRE D Q E CLK Truth Table PRE E CLK QNn+1 1 X X 0 0 1 X QN 0 0 !D Output QN Input D, E, PRE, CLK Family Tiles All 1 Macro Library Guide 59 DFI0E0P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Enable and Clock, active high Preset and inverted output PRE QN D E CLK Truth Table PRE E CLK QNn+1 1 X X 0 0 1 X QN 0 0 !D Output QN Input D, E, PRE, CLK Family Tiles All 1 DFI1E1P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable, active low Preset, and inverted output PRE D QN E CLK Output QN Input D, E, PRE, CLK 60 Family Tiles All 1 Truth Table PRE E CLK QNn+1 0 X X 0 1 0 X QN 1 1 !D DFI0E1P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Enable, active low Preset and Clock, and inverted output PRE QN D Truth Table PRE E CLK QNn+1 0 X X 0 1 0 X QN 1 1 !D E CLK Output QN Input D, E, PRE, CLK Family Tiles All 1 DFI1E0P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Enable and Preset, and inverted output PRE D QN E CLK Truth Table PRE E CLK QNn+1 0 X X 0 1 1 X QN 1 0 !D Output QN Input D, E, PRE, CLK Family Tiles All 1 Macro Library Guide 61 DFI0E0P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Enable, Clock, and Preset, and inverted output PRE D QN E CLK Truth Table PRE E CLK QNn+1 0 X X 0 1 1 X QN 1 0 !D Output QN Input D, E, PRE, CLK Family Tiles All 1 DFN0P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Preset, and active low Clock Truth Table PRE Q D CLK Output Q Input D, PRE, CLK 62 Family Tiles All 1 PRE CLK Qn+1 1 X 1 0 D DFN1P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Preset Truth Table PRE Q D PRE CLK Qn+1 0 X 1 1 D CLK Output Q Input D, PRE, CLK Family Tiles All 1 DFI1P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Preset, and inverted Output Truth Table PRE QN D PRE CLK QNn+1 1 X 0 0 !D CLK Output QN Input D, PRE, CLK Family Tiles All 1 Macro Library Guide 63 DFN0P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Preset and Clock Truth Table PRE Q D PRE CLK Qn+1 0 X 1 1 D CLK Output Q Input D, PRE, CLK Family Tiles All 1 DFI1P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Preset and inverted Output Truth Table PRE D QN CLK Output QN Input D, PRE, CLK 64 Family Tiles All 1 PRE CLK QNn+1 0 X 0 1 !D DFI0P1 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active high Preset, and active low Clock and inverted Output PRE D Truth Table QN PRE CLK QNn+1 1 X 0 0 !D CLK Output QN Input D, PRE, CLK Family Tiles All 1 DFI0P0 IGLOO, ProASIC3, SmartFusion, Fusion Function D-Type Flip-Flop with active low Preset, Clock and inverted Output Truth Table PRE QN D PRE CLK QNn+1 0 X 0 1 !D CLK Output QN Input D, PRE, CLK Family Tiles All 1 Macro Library Guide 65 DFN1P1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Rising Edge Triggered D-Type Flip-Flop with Active High Preset and Clear D PRE Q Truth Table CLK CLK CLR PRE CLR Qn+1 X 1 0 1 X X 1 0 0 0 D Output Q Input CLR, PRE, CLK, D Family Tiles All 4 DFI1P1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Rising Edge Triggered D-Type Flip-Flop with Active High Preset and Clear and inverted Output D PRE Truth Table CLK QN CLR Output QN Input CLR, PRE, CLK, D 66 Family Tiles All 4 CLK PRE CLR QNn+1 X 1 0 0 X X 1 1 0 0 !D DFN0P1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Falling Edge Triggered D-Type Flip-Flop with Active High Preset and Clear D PRE Q Truth Table CLK CLK CLR PRE CLR Qn+1 X 1 0 1 X X 1 0 0 0 D Output Q Input CLR, PRE, CLK, D Family Tiles All 4 DFI0P1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Falling Edge Triggered D-Type Flip-Flop with Active High Preset and Clear and inverted Output D PRE Truth Table CLK QN CLR CLK PRE CLR QNn+1 X 1 0 0 X X 1 1 0 0 !D Output QN Input CLR, PRE, CLK, D Family Tiles All 4 Macro Library Guide 67 Sequential, Data Latch DLN1 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch Q D Truth Table G G Qn+1 0 Q 1 D Output Q Input D, G Family Tiles All 1 DLI1 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with inverted Output D QN Truth Table G Output QN Input D, G 68 Family Tiles All 1 G QNn+1 0 QN 1 !D DLN0 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active low Clock Q D Truth Table G G Qn+1 1 Q 0 D Output Q Input D, G Family Tiles All 1 DLI0 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch, with active low Clock and inverted Output QN D Truth Table G G QNn+1 1 QN 0 !D Output QN Input D, G Family Tiles All 1 Sequential, Data Latch with Clear Macro Library Guide 69 DLN1C0 IGLOO, ProASIC3, SmartFusion, Fusion Function Q D Data Latch with active low Clear Truth Table G CLR CLR G Qn+1 0 X 0 1 0 Q 1 1 D Output Q Input CLR, D, G Family Tiles All 1 DLN1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active high Clear Q D Truth Table G CLR Output Q Input CLR, D, G 70 Family Tiles All 1 CLR G Qn+1 1 X 0 0 0 Q 0 1 D DLN0C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active high Clear and active low Clock Q D Truth Table G CLR CLR G Qn+1 1 X 0 0 1 Q 0 0 D Output Q Input CLR, D, G Family Tiles All 1 DLI1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active high Clear and inverted Output QN D Truth Table G CLR CLR G QNn+1 1 X 1 0 0 QN 0 1 !D Output QN Input CLR, D, G Family Tiles All 1 Macro Library Guide 71 DLI0C1 IGLOO, ProASIC3, SmartFusion, Fusion Function D QN Data Latch with active high Clear and active low Clock and inverted Output Truth Table G CLR CLR G QNn+1 1 X 1 0 1 QN 0 0 !D Output QN Input CLR, D, G Family Tiles All 1 DLN0C0 IGLOO, ProASIC3, SmartFusion, Fusion Function Q D Data Latch with active low Clear and Clock Truth Table G CLR Output Q Input CLR, D, G 72 Family Tiles All 1 CLR G Qn+1 0 X 0 1 1 Q 1 0 D DLI1C0 IGLOO, ProASIC3, SmartFusion, Fusion Function QN D Data Latch with active low Clear and inverted output Truth Table G CLR CLR G QNn+1 0 X 1 1 0 QN 1 1 !D Output QN Input CLR, D, G Family Tiles All 1 DLI0C0 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active low Clear, Clock, and inverted Output D QN Truth Table G CLR CLR G QNn+1 0 X 1 1 1 QN 1 0 !D Output QN Input CLR, D, G Family Tiles All 1 Macro Library Guide 73 Sequential, Data Latch with Preset DLN1P1 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active high Preset and Clock D PRE Truth Table Q G PRE G Qn+1 1 X 1 0 0 Q 0 1 D Output Q Input D, G, PRE Family Tiles All 1 DLN0P1 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active high Preset and active low Clock PRE D Truth Table Q G Output Q Input D, G, PRE 74 Family Tiles All 1 PRE G Qn+1 1 X 1 0 1 Q 0 0 D DLN1P0 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active low Preset and active high Clock Truth Table PRE D Q G PRE G Qn+1 0 X 1 1 0 Q 1 1 D Output Q Input D, G, PRE Family Tiles All 1 DLN0P0 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active low Preset and Clock Truth Table PRE D Q G PRE G Qn+1 0 X 1 1 1 Q 1 0 D Output Q Input D, G, PRE Family Tiles All 1 Macro Library Guide 75 Sequential DLI1P0 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active low Preset and Output, and active high Clock Truth Table PRE D QN G PRE G QNn+1 0 X 0 1 0 QN 1 1 !D Output QN Input D, G, PRE Family Tiles All 1 DLI0P0 IGLOO, ProASIC3, SmartFusion, Fusion Function Data Latch with active low Preset, Clock, and inverted Output Truth Table PRE D QN G Output QN Input D, G, PRE 76 Family Tiles All 1 PRE G QNn+1 0 X 0 1 0 !D 1 1 QN DLI1P1 IGLOO, ProASIC3, SmartFusion, Fusion Function Active High Latch with Active High Preset and inverted Output D Truth Table PRE G QN G PRE QNn+1 X 1 0 0 0 QN 1 0 !D Output QN Input PRE, G, D Family Tiles All 1 DLI0P1 IGLOO, ProASIC3, SmartFusion, Fusion Function Active Low Latch with Active High Preset and inverted Output D Truth Table PRE G QN G PRE QNn+1 X 1 0 0 0 !D 1 0 QN Output QN Input PRE, G, D Family Tiles All 1 Macro Library Guide 77 DLN1P1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Active High Latch with Active High Preset and Clear D G PRE Truth Table Q CLR G PRE CLR Qn+1 X 1 0 1 X X 1 0 1 0 0 D 0 0 0 Q Output Q Input CLR, PRE, G, D Family Tiles All 2 DLI1P1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Active High Latch with Active High Preset and Clear and inverted Output D PRE Truth Table G QN G CLR Output QN Input CLR, PRE, G, D 78 Family Tiles All 2 PRE CLR QNn+1 X 1 0 0 X X 1 1 1 0 0 !D 0 0 0 QN DLN0P1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Active Low Latch with Active High Preset and Clear D G PRE Truth Table Q CLR G PRE CLR Qn+1 X 1 0 1 X X 1 0 0 0 0 D 1 0 0 Q Output Q Input CLR, PRE, G, D Family Tiles All 2 DLI0P1C1 IGLOO, ProASIC3, SmartFusion, Fusion Function Active Low Latch with Active High Preset and Clear and inverted Output D PRE Truth Table G QN G CLR Output QN Input CLR, PRE, G, D Family Tiles All 2 Macro Library Guide PRE CLR QNn+1 X 1 0 0 X X 1 1 0 0 0 !D 1 0 0 QN 79 GND IGLOO, ProASIC3, SmartFusion, Fusion Function Ground Y Output Y Input NOTE: Ground does not use any tiles. Combinational, Inverters INV IGLOO, ProASIC3, SmartFusion, Fusion Function Inverter with active low Output Truth Table A Y Output Y Input A 80 Family Tiles All 1 A Y 0 1 1 0 INVD IGLOO, ProASIC3, SmartFusion, Fusion Function Inverter with active low Output NOTE: The Combiner will not remove this macro Truth Table A Y A Y 0 1 1 0 Output Y Input A Family Tiles All 1 Combinational, AND-OR MAJ3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input majority function A Truth Table A B Y C Output Y Input A, B, C Family Tiles All 1 Macro Library Guide B C Y X 0 0 0 0 0 X 0 0 X 0 0 X 1 1 1 1 X 1 1 1 1 X 1 81 MAJ3X IGLOO, ProASIC3, SmartFusion, Fusion Function 2 of 3 function A Truth Table B C Y Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 0 MAJ3XI IGLOO, ProASIC3, SmartFusion, Fusion Function 2 of 3 function with active low output A B Truth Table C Y Output Y Input A, B, C 82 Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 1 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 1 MIN3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input minority function A B Truth Table A Y B C Y X 0 0 1 0 0 X 1 C Output Y Input A, B, C Family Tiles All 1 0 X 0 1 X 1 1 0 1 X 1 0 1 1 X 0 MIN3X IGLOO, ProASIC3, SmartFusion, Fusion Function 1 of 3 function A B Truth Table C A B C Y 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 0 Y Output Y Input A, B, C Family 54SX, 54SX-A, 54SX-S, eX Modules Seq Comb 1 Combinational, AND-OR-INVERT Combinational, Multiplexer Macro Library Guide 83 MIN3XI IGLOO, ProASIC3, SmartFusion, Fusion Function A 1 of 3 function with active low output B Truth Table C Y Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 1 MX2 IGLOO, ProASIC3, SmartFusion, Fusion Function 2 to 1 Multiplexer A S Truth Table Y B Output Y Input A, B, S 84 Family Tiles All 1 S Y 0 A 1 B MX2A IGLOO, ProASIC3, SmartFusion, Fusion Function 2 to 1 Multiplexer with active low A-Input A S Truth Table Y B S Y 0 !A 1 B Output Y Input A, B, S Family Tiles All 1 MX2B IGLOO, ProASIC3, SmartFusion, Fusion Function 2 to 1 Multiplexer with active low B-Input S A Truth Table Y B S Y 0 A 1 !B Output Y Input A, B, S Family Tiles All 1 Combinational, NAND Macro Library Guide 85 MX2C IGLOO, ProASIC3, SmartFusion, Fusion Function 2 to 1 Multiplexer with active low Output A S Truth Table Y B S Y 0 !A 1 !B Output Y Input A, B, S Family Tiles All 1 NAND2 IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input NAND Truth Table A Y B Output Y Input A, B 86 Family Tiles All 1 A B Y X 0 1 0 X 1 1 1 0 NAND2A IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input NAND with active low A-Input Truth Table A Y B A B Y X 0 1 0 1 0 1 X 1 Output Y Input A, B Family Tiles All 1 NAND2B IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input NAND with active low Inputs Truth Table A Y B A B Y 0 0 0 X 1 1 1 X 1 Output Y Input A, B Family Tiles All 1 Combinational, NOR Macro Library Guide 87 NAND3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input NAND A Truth Table Y B C A B C Y X X 0 1 X 0 X 1 0 X X 1 1 1 1 0 Output Y Input A, B, C Family Tiles All 1 NAND3A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input NAND with active low A-Input A Truth Table Y B C Output Y Input A, B, C 88 Family Tiles All 1 A B C Y X X 0 1 X 0 X 1 0 1 1 0 1 X X 1 NAND3B IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input NAND with active low A- and B-Inputs A Truth Table Y B C A B C Y X X 0 1 0 0 1 0 X 1 X 1 1 X X 1 Output Y Input A, B, C Family Tiles All 1 NAND3C IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input NAND with active low Inputs A Truth Table Y B C A B C Y 0 0 0 0 X X 1 1 X 1 X 1 1 X X 1 Output Y Input A, B, C Family Tiles All 1 Macro Library Guide 89 NOR2 IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input NOR Truth Table A Y B A B Y 0 0 1 X 1 0 1 X 0 Output Y Input A, B Family Tiles All 1 NOR2A IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input NOR with active low A-Input Truth Table A Y B Output Y Input A, B Family Tiles All 1 Combinational, OR-AND 90 A B Y 0 X 0 1 0 1 X 1 0 NOR2B IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input NOR with active low Inputs Truth Table A Y B A B Y X 0 0 0 X 0 1 1 1 Output Y Input A, B Family Tiles All 1 NOR3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input NOR A Truth Table Y B C A B C Y 0 0 0 1 X X 1 0 X 1 X 0 1 X X 0 Output Y Input A, B, C Family Tiles All 1 Combinational, OR-AND-INVERT Macro Library Guide 91 NOR3A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input NOR with active low A-Input A Truth Table Y B C A B C Y 0 X X 0 1 0 0 1 X X 1 0 X 1 X 0 Output Y Input A, B, C Family Tiles All 1 NOR3B IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input NOR with active low A- and B-Inputs A Truth Table Y B C Output Y Input A, B, C 92 Family Tiles All 1 A B C Y X 0 X 0 0 X X 0 1 1 0 1 X X 1 0 NOR3C IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input NOR with active low Inputs A Truth Table Y B C A B C Y X X 0 0 X 0 X 0 0 X X 0 1 1 1 1 Output Y Input A, B, C Family Tiles All 1 OA1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3 Input OR-AND Truth Table A B Y C A B C Y X X 0 0 0 0 X 0 X 1 1 1 1 X 1 1 Output Y Input A, B, C Family Tiles All 1 Macro Library Guide 93 OA1A IGLOO, ProASIC3, SmartFusion, Fusion Function 3 Input OR-AND with active low A-Input A Truth Table B Y C A B C Y X X 0 0 0 X 1 1 1 0 X 0 X 1 1 1 Output Y Input A, B, C Family Tiles All 1 OA1B IGLOO, ProASIC3, SmartFusion, Fusion Function 3 Input OR-AND with active low C-Input A Truth Table B Y C Output Y Input A, B, C 94 Family Tiles All 1 A B C Y 0 0 X 0 X 1 0 1 X X 1 0 1 X 0 1 OA1C IGLOO, ProASIC3, SmartFusion, Fusion Function 3 Input OR-AND with active low A- and C-Inputs A Truth Table B Y C A B C Y 0 X 0 1 X X 1 0 1 0 X 0 X 1 0 1 Output Y Input A, B, C Family Tiles All 1 OAI1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input OR-AND-INVERT A Truth Table B Y C A B C Y X X 0 1 0 0 X 1 X 1 1 0 1 X 1 0 Output Y Input A, B, C Family Tiles All 1 Macro Library Guide 95 Combinational, OR OR2 IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input OR Truth Table A Y B A B Y 0 0 0 X 1 1 1 X 1 Output Y Input A, B Family Tiles All 1 OR2A IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input OR with active low A-Input Truth Table A Y B Output Y Input A, B 96 Family Tiles All 1 A B Y 0 X 1 1 0 0 X 1 1 OR2B IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input OR with active low Inputs Truth Table A Y B A B Y X 0 1 0 X 1 1 1 0 Output Y Input A, B Family Tiles All 1 OR3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input OR A Truth Table A B Y C B C Y 0 0 0 0 X X 1 1 X 1 X 1 1 X X 1 Output Y Input A, B, C Family Tiles All 1 Macro Library Guide 97 OR3A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input OR with active low A-Input A Truth Table B Y C A B C Y 0 X X 1 1 0 0 0 X X 1 1 X 1 X 1 Output Y Input A, B, C Family Tiles All 1 OR3B IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input OR with active low A- and B-Inputs A Truth Table A B Y C Output Y Input A, B, C 98 Family Tiles All 1 B C Y X 0 X 1 0 X X 1 1 1 0 0 X X 1 1 OR3C IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input OR with active low Inputs A Truth Table B Y C A B C Y X X 0 1 X 0 X 1 0 X X 1 1 1 1 0 Output Y Input A, B, C Family Tiles All 1 VCC IGLOO, ProASIC3, SmartFusion, Fusion Function Power Y Input Output Y NOTE: VCC does not use any modules. Macro Library Guide 99 Combinational, XOR-AND XA1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XOR-AND A Truth Table B Y C A B C Y X X 0 0 0 0 X 0 0 1 1 1 1 0 1 1 1 1 X 0 Output Y Input A, B, C Family Tiles All 1 XA1A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XNOR-AND Truth Table A B Y C Output Y Input A, B, C 100 Family Tiles All 1 A B C Y X X 0 0 0 0 1 1 0 1 X 0 1 0 X 0 1 1 1 1 Combinational, XNOR-AND XA1B IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XNOR-AND with active low C-input Truth Table A B Y C A B C X X 1 Y 0 0 0 X 0 1 0 0 1 0 1 0 1 1 1 X 0 Output Y Input A, B, C Family Tiles All 1 XA1C IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XNOR-AND with active low C-input Truth Table A B Y C A B C Y X X 1 0 0 0 0 1 1 0 X 0 0 1 X 0 1 1 0 1 Output Y Input A, B, C Family Tiles All 1 Macro Library Guide 101 Combinational, XNOR-NAND XAI1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XNOR-NAND Truth Table A B Y C A B C Y X X 0 1 0 0 X 1 1 0 1 0 0 1 1 0 1 1 X 1 Output Y Input A, B, C Family Tiles All 1 XAI1A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XNOR-NAND Truth Table A B Y C Output Y Input A, B, C 102 Family Tiles All 1 A B C X X 0 Y 1 0 0 1 0 1 0 X 1 0 1 X 1 1 1 1 0 Combinational, XNOR XNOR2 IGLOO, ProASIC3, SmartFusion, Fusion Function 2- Input XNOR Truth Table A Y B A B Y 0 0 1 0 1 0 1 0 0 1 1 1 Output Y Input A, B Family Tiles All 1 XNOR3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XNOR Truth Table A B Y C Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 1 0 0 1 0 1 0 1 1 0 1 1 1 1 1 1 0 Combinational, XOR-OR Macro Library Guide 103 XO1 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XOR-OR A Truth Table A B Y C B C Y 0 0 0 0 X X 1 1 0 1 X 1 1 0 X 1 1 1 0 0 Output Y Input A, B, C Family Tiles All 1 XO1A IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XNOR-OR A Truth Table A B Y C Output Y Input A, B, C Family Tiles All 1 Combinational, XOR 104 B C Y 1 0 0 0 X X 1 1 0 1 0 0 1 0 0 0 1 1 0 1 XOR2 IGLOO, ProASIC3, SmartFusion, Fusion Function 2-Input XOR Truth Table A Y B A B Y 0 0 0 0 1 1 1 0 1 1 1 0 Output Y Input A, B Family Tiles All 1 XOR3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input XOR Truth Table A B Y C Output Y Input A, B, C Family Tiles All 1 Macro Library Guide A B C Y 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 1 105 Combinational, Gate ZOR3 IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input function A Truth Table B C Y Output Y Input A, B, C Family Tiles All 1 A B C Y 0 0 0 1 1 0 0 0 0 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 0 1 1 0 1 1 1 1 ZOR3I IGLOO, ProASIC3, SmartFusion, Fusion Function 3-Input function A B Truth Table C Y Output Input A, B, C 106 Y Family Tiles All 1 A B C Y 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 0 1 1 0 1 1 1 1 1 1 0 RAM and FIFO Macros Macro Library Guide 107 RAM Macros RAM4K9 and RAM512X18 IGLOO, ProASIC3, SmartFusion, Fusion Function RAM4K9 RAM512X18 DOUTA8 DOUTA7 . . . DOUTA0 ADDRA11 ADDRA10 . . . ADDRA0 RD17 RD16 . . . RD0 RADDR8 RADDR7 . . . RADDR0 RAM4K9 is a fully synchronous, true dual-port RAM with an optional pipeline stage; RAM512X18 is a fully synchronous, two-port RAM with an optional pipeline stage DINA8 DINA7 . . . DINA0 RW1 RW0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA Truth tables are listed below. PIPE REN RCLK DOUTB8 DOUTB7 . . . DOUTB 0 ADDRB11 ADDRB10 . . . ADDRB0 WADDR8 WADDR7 . . . WADDR0 DINB8 DINB7 . . . DINB0 WD17 WD16 . . . WD0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WW1 WW0 WEN WCLK Reset Reset Input Inputs are shown on the left of the diagrams. For example, ADDRA11, ADDRA10, ... , ADDRA0. Output Outputs are shown at the right on the diagrams. For example, DOUTA8, DOUT7, ... , DOUT0. There are two RAM macros in the ProASIC3/ProASIC3E library: RAM4K9 and RAM512X18. The RAM4K9 is a fully synchronous, true dual-port RAM with an optional pipeline stage. It can be used for word widths up to 9 bits. Both ports are capable of reading and writing, making it possible to write with both ports or read with both ports simultaneously. You can also read from one port while writing to the other. Each port also has an optional pipeline stage that can be controlled separately via the PIPE pins. The RAM512X18 is a fully synchronous, two-port RAM with an optional pipeline stage. You can use it for word widths of 9 or 18 bits. It has one dedicated read port and one dedicated write port (you can read from one port while writing to the other). The read port also has an optional pipeline stage that you can control separately via the PIPE pin. During the write operation of the RAM4K9, the WMODE pins control the data that appears on the read pins of the same port. When WMODE is high, the same data appears on the read and write ports at the rising CLK edge. When WMODE is low, the old data stored in the current memory location being addressed appears on the read port. There are no WMODE pins on the RAM512X18. The aspect ratio of each port can be specified independently via the WIDTHA and WIDTHB pins. For the RAM512X18, the allowable values are 18 x 256 and 9 x 512. For the RAM4K9, the allowable values are 9 x 512, 4 x 1K, 2 x 2K, and 1 x 4K. Although it is possible to dynamically reconfigure the aspect ratios, the RAM was designed with only static configuration in mind, so the timing is unknown and you are discouraged from performing such operations. The same is true for the WMODE and PIPE configuration pins. The RAM4K9 only needs 2 bits to configure the WIDTH. The allowable RAM4K9 WIDTHA and WIDTHB values are shown in the table below. RAM4K9 WIDTHA and WIDTHB Values 108 WIDTHA1, WIDTHA0 WIDTHB1, WIDTHB0 WxD 00 00 1 x 4K 01 01 2 x 2K 10 10 4 x 1K 11 11 9 x 512 The RAM512X18 also needs 2 bits to configure the read and write widths. The allowable RAM512X18 WW and RW values are shown in the table below. RAM512x18 WW and RW Values WW1, WW0 RW1, RW0 WxD 01 01 9 x 512 10 10 18 x 256 00, 11 00, 11 Illegal When specifying a width that is less than the maximum (e.g. 1), the upper unused data input pins (e.g. DINA8 - DINA1) must be connected to GND. When specifying a depth that is less than the maximum (e.g. 512), the upper unused address pins (e.g. ADDRA11 - ADDRA9) must also be connected to GND. When widths of 1, 2, and 4 are used, the ninth bit is skipped. This can cause counter-intuitive effects when these widths are used for read operations and larger widths are used for write operations (or vice versa). For example, if a width of 9 is used for writing and a width of 1 for reading, every 9th bit will be dropped. This effect may be desirable for removing parity bits. If a write width of 4 and read width of 9 is used, the 9th bit may either contain garbage or remnants of previous write operations when a write width of 9 or higher was being used. For this reason, SmartGen only supports the following aspect ratio combinations when one of the ports is configured with a 1-, 2-, or 4-bit width using the RAM4K9. SmartGen Supported Aspect Ratio Combinations for the RAM4K9 READ WRITE 1 x 4K 1 x 4K 1 x 4K 2 x 2K 1 x 4K 4 x 1K 2 x 2K 1 x 4K 2 x 2K 2 x 2K 2 x 2K 4 x 1K 4 x 1K 1 x 4K 4 x 1K 2 x 2K 4 x 1K 4 x 1K The RAM4K9 can still be used for 9-bit width applications, but no other bit-width can be used with it other than 9-bits. SmartGen Supported Aspect Ratios for 9-bit Width Applications READ WRITE 9 x 512 9 x 512 There are several restrictions that apply when you use an 18 x 256 aspect ratio. For this reason, SmartGen uses the RAM512X18 whenever 18-bit widths are specified. The only allowable combinations of read and write configurations for the RAM512X18 are as follows: RAM512X18 Read and Write Combinations READ WRITE 18 x 256 18 x 256 18 x 256 9 x 512 9 x 512 18 x 256 The RADDR pins are always used for the read address in the above configurations and the WADDR pins are used for the write address. The RW pin is used to specify the read width and the WW pin for the write width. The WD pins are used for writing data and the RD pins for reading data. RAM4K9 Truth Table Operation Address CLK BLK WMODE WEN RESET DI DO Deselect X X H X X H X Data-Last Reset X X X X X L X L Read ADDR Rising Edge L L H H X Data Write (0) ADDR Rising Edge L L L H WData Data-Last Write (1) ADDR Rising Edge L H L H WData WData Macro Library Guide 109 When deserted, the BLK pins will cause the DO outputs to hold their last value. When asserted, the WEN pins can be used to switch each port between write and read mode. The RESET pin sets all outputs low but does not reset the memory. The WMODE pins are used to either allow the write data to appear immediately on the output pins or to hold the last value. RAM512x18 Truth Table Operation Address WCLK REN WEN RESET WD Reset X X X X L X RD L Read RADDR Rising Edge L X H X Stored Data Write WADDR Rising Edge X L H WData Data-Last Use SmartGen to configure the RAM for typical use. SmartGen will not support dynamic reconfiguration or cascading width-wise. Customers who wish to use such features must instantiate and configure the RAM macro manually. You can configure your RAM dynamically if you use the FlexRAM macros in the next section. Warnings • Simultaneous write and read to same address is detected and if timing requirements are not met, read data is driven to X. Write operation is not affected. • Simultaneous write to the same address from both ports is possible, but the results are undefined. Avoid writing to the same address simultaneously from both ports. • Dynamic reconfiguration of any pins possible but not supported by SmartGen. • Cascading is possible and limited only by the number of available RAM blocks in a row, which is device dependent. SmartGen prompts you for device type information in order to correctly calculate the maximum. • RESET has priority over BLKA and BLKB. • In read mode (i.e. when WEN high) WMODE is ignored. • Dual-port operation not possible unless both ports have the same aspect ratio. 110 FLEXRAM4K9 and FLEXRAM512X18 Fusion Function FLEXRAM4K9 FLEXRAM4K9 is a fully synchronous, true dual-port RAM with an optional pipeline stage; FLEXRAM512X18 is a fully synchronous, two-port RAM with an optional pipeline stage RD17 RD16 . . . RD0 RADDR8 RADDR7 . . . RADDR0 DOUTA8 DOUTA7 . . . DOUTA0 ADDRA11 ADDRA10 . . . ADDRA0 FLEXRAM512X18 DINA8 DINA7 . . . DINA0 RW1 RW0 WIDTHA1 WIDTHA0 PIPEA WMODEA BLKA WENA CLKA Truth tables are listed below. PIPE REN RCLK WADDR8 WADDR7 . . . WADDR0 DOUTB8 DOUTB7 . . . DOUTB 0 ADDRB11 ADDRB10 . . . ADDRB0 DINB8 DINB7 . . . DINB0 WD17 WD16 . . . WD0 WIDTHB1 WIDTHB0 PIPEB WMODEB BLKB WENB CLKB WW1 WW0 WEN WCLK Reset Reset Input Inputs are shown on the left of the diagrams. For example, ADDRA11, ADDRA10, ... , ADDRA0. Output Outputs are shown at the right on the diagrams. For example, DOUTA8, DOUT7, ... , DOUT0. There are two dynamically reconfigurable RAM macros in the Fusion library: FLEXRAM4K9 and FLEXRAM512X18. The FLEXRAM4K9 is a fully synchronous, true dual-port RAM with an optional pipeline stage. It can be used for word widths up to 9 bits. Both ports are capable of reading and writing, making it possible to write with both ports or read with both ports simultaneously. You can also read from one port while writing to the other. Each port also has an optional pipeline stage that can be controlled separately via the PIPE pins. The FLEXRAM512X18 is a fully synchronous, two-port RAM with an optional pipeline stage. You can use it for word widths of 9 or 18 bits. It has one dedicated read port and one dedicated write port (you can read from one port while writing to the other). The read port also has an optional pipeline stage that you can control separately via the PIPE pin. During the write operation of the FLEXRAM4K9, the WMODE pins control the data that appears on the read pins of the same port. When WMODE is high, the same data appears on the read and write ports at the rising CLK edge. When WMODE is low, the old data stored in the current memory location being addressed appears on the read port. There are no WMODE pins on the FLEXRAM512X18. The aspect ratio of each port can be specified independently via the WIDTHA and WIDTHB pins. For the FLEXRAM512X18, the allowable values are 18 x 256 and 9 x 512. For the FLEXRAM4K9, the allowable values are 9 x 512, 4 x 1K, 2 x 2K, and 1 x 4K. Actel recommends that you do not change the WMODE and pipe configuration pins dynamically because the timing is unknown. The FLEXRAM4K9 only needs 2 bits to configure the WIDTH. The allowable FLEXRAM4K9 WIDTHA and WIDTHB values are shown in the table below. FLEXRAM4K9 WIDTHA and WIDTHB Values Macro Library Guide WIDTHA1, WIDTHA0 WIDTHB1, WIDTHB0 WxD 00 00 1 x 4K 01 01 2 x 2K 10 10 4 x 1K 11 11 9 x 512 111 The FLEXRAM512X18 also needs 2 bits to configure the read and write widths. The allowable FLEXRAM512X18 WW and RW values are shown in the table below. FLEXRAM512x18 WW and RW Values WW1, WW0 RW1, RW0 WxD 01 01 9 x 512 10 10 18 x 256 00, 11 00, 11 Illegal When specifying a width that is less than the maximum (e.g. 1), the upper unused data input pins (e.g. DINA8 - DINA1) must be connected to GND. When specifying a depth that is less than the maximum (e.g. 512), the lower unused address pins (e.g. ADDRA2 ADDRA0) must also be connected to GND. When widths of 1, 2, and 4 are used, the ninth bit is skipped. This can cause counter-intuitive effects when these widths are used for read operations and larger widths are used for write operations (or vice versa). For example, if a width of 9 is used for writing and a width of 1 for reading, every 9th bit will be dropped. This effect may be desirable for removing parity bits. If a write width of 4 and read width of 9 is used, the 9th bit may either contain garbage or remnants of previous write operations when a write width of 9 or higher was being used. For this reason, Actel recommends that you use only the following aspect ratio combinations when one of the ports is configured with a 1-, 2-, or 4-bit width using the FLEXRAM4K9. Recommended Aspect Ratio Combinations for the FLEXRAM4K9 READ WRITE 1 x 4K 1 x 4K 1 x 4K 2 x 2K 1 x 4K 4 x 1K 2 x 2K 1 x 4K 2 x 2K 2 x 2K 2 x 2K 4 x 1K 4 x 1K 1 x 4K 4 x 1K 2 x 2K 4 x 1K 4 x 1K The FLEXRAM4K9 can still be used for 9-bit width applications, but no other bit-width can be reliably used with it other than 9-bits. Recommended Aspect Ratios for 9-bit Width Applications READ WRITE 9 x 512 9 x 512 There are several restrictions that apply when you use an 18 x 256 aspect ratio. For this reason, Actel recommends that you use the FLEXRAM512X18 whenever 18-bit widths are specified. The only allowable combinations of read and write configurations for the FLEXRAM512X18 are as follows: FLEXRAM512X18 Read and Write Combinations READ WRITE 18 x 256 18 x 256 18 x 256 9 x 512 9 x 512 18 x 256 The RADDR pins are always used for the read address in the above configurations and the WADDR pins are used for the write address. The RW pin is used to specify the read width and the WW pin for the write width. The WD pins are used for writing data and the RD pins for reading data. FLEXRAM4K9 Truth Table Operation 112 Address CLK BLK WMODE WEN RESET DI DO Data-Last Deselect X X H X X H X Reset X X X X X L X L Read ADDR Rising Edge L L H H X Data Write (0) ADDR Rising Edge L L L H WData Data-Last FLEXRAM4K9 Truth Table Operation Address CLK BLK WMODE WEN RESET DI DO Write (1) ADDR Rising Edge L H L H WData WData When deserted, the BLK pins will cause the DO outputs to hold their last value. When asserted, the WEN pins can be used to switch each port between write and read mode. The RESET pin sets all outputs low but does not reset the memory. The WMODE pins are used to either allow the write data to appear immediately on the output pins or to hold the last value. FLEXRAM512x18 Truth Table Operation Address WCLK REN WEN RESET WD RD Reset X X X X L X L Read RADDR Rising Edge L X H X Stored Data Write WADDR Rising Edge X L H WData Data-Last SmartGen does not support FlexRAM macros; you must instantiate and configure the FlexRAM macros manually. Warnings • Simultaneous write and read to same address is detected and if timing requirements are not met, read data is driven to X. Write operation is not affected. • Simultaneous write to the same address from both ports is possible, but the results are undefined. Avoid writing to the same address simultaneously from both ports. • RESET has priority over BLKA and BLKB. • In read mode (i.e. when WEN high) WMODE is ignored. • Dual-port operation not possible unless both ports have the same aspect ratio. Macro Library Guide 113 FIFO Macros FIFO4K18 IGLOO, ProASIC3, SmartFusion, Fusion Function RD17 RD16 ... ... RD0 RW2 RW1 RW0 WW2 WW0 ESTOP FSTOP FIFO4K18 is fully synchronous and has its own built-in controller, capable of variable aspect ratios. FULL AFULL EMPTY AEMPTY AEVAL11 AEVAL10 ... ... AEVAL0 Truth tables are listed below. AFVAL11 AFVAL10 ... ... AFVAL0 REN RBLK RCLK WD17 WD16 ... ... WD0 WEN WBLK WCLK RPIPE RESET Input Inputs are shown on the left of the diagram. For example, AEVAL11, AEVAL10, ... , AEVAL0. Output Outputs are shown at the right on the diagram. For example, RD17, RD16, ... , RD0. FIFO4K18 is fully synchronous and has its own built-in controller. Like the RAM, the FIFO can have different write and read aspect ratios that can be configured dynamically. The WW and RW pins are used to specify one of five allowable aspect ratios, as shown below. FIFO4K18 Aspect Ratios WW2, WW1, WW0 and RW2, RW1, RW0 WxH 000 1 x 4K 001 2 x 2K 010 4 x 1K 011 9 x 512 100 18 x 256 101, 110, 111 Illegal The AEVAL and AFVAL pins are used to specify the almost empty and almost full threshold values, respectively. In order to handle different read and write aspect ratios, the values specified by the AEVAL and AFVAL pins are to be interpreted as the address of the last word stored in the FIFO. The FIFO actually contains separate write address (WADDR) and read address (RADDR) counters. These counters calculate the 12-bit memory address that is a function of WW and RW, respectively. WADDR is incremented every time a write operation is performed and RADDR is incremented every time a read operation is performed. Whenever the difference between WADDR and RADDR is greater than or equal to AFVAL, the AFULL output is raised. Likewise, whenever the difference between WADDR and RADDR is less than or equal to AEVAL, the AEMPTY output is raised. Therefore AEVAL and AFVAL must be left-justified for widths greater than one (i.e. unused lsb’s must be grounded). Aspect Ratio and Related Bits to Ground 114 Aspect ratio AEVAL/AFVAL bits to ground 1 x 4K none Aspect Ratio and Related Bits to Ground Aspect ratio AEVAL/AFVAL bits to ground 2 x 2K 0 4 x 1K 1:0 9 x 512 2:0 18 x 256 3:0 When the number of words stored in the FIFO reaches the amount specified by AEVAL while reading, the AEMPTY output will go high. Likewise when the number of words stored in the FIFO reaches the amount specified by AFVAL while writing, the AFULL output will go high. The FULL and EMPTY outputs will go high when the FIFO is completely full or empty, respectively. It should be noted that the internal memory size is 512 X 9. When widths of 1, 2, and 4 are specified, the 9th bit is skipped. The ESTOP pin is used to stop the read counter from counting any further once the FIFO is empty (i.e. the EMPTY flag goes high). Likewise, the FSTOP pin is used to stop the write counter from counting any further once the FIFO is full (i.e. the FULL flag goes high). These are configuration pins that should not be dynamically reconfigured. SmartGen treats them as static configuration pins and always ties them high. Independent read and write operations are allowed, however only the read port can be pipelined. Data on the appropriate WD pins are written to the FIFO every rising WCLK edge as long as WEN and WBLK are low. Data is read from the FIFO and output on the appropriate RD pins every rising RCLK edge as long as REN is high and RBLK is low. The active low RESET pin is used to asynchronously clear the outputs of the FIFO and reset the internal read and write address counters. It sets all the RD pins low, the FULL and AFULL pins low, and the EMPTY and AEMPTY pins high, however the contents of the memory remain unchanged. RESET has priority over RBLK and WBLK. When instantiating the FIFO4K18, all unused input pins must be connected to GND. Warnings • The WW, RW, AEVAL, and AFVAL pins can be dynamically configured, but only static configuration will be supported by SmartGen. • The RPIPE signal can be dynamically configured, but only static configuration will be supported by SmartGen. • No pipeline on the write port. • Cascading allowed and supported in the width direction only by SmartGen. Cascading in the depth direction requires the use of a soft controller (i.e. implemented with core logic). • ESTOP and FSTOP applications not clear. The effect of activating ESTOP is to allow the read pointer to wrap around, allowing the memory contents to be read over and over again with rewriting after EMPTY. The effect of activating FSTOP is not clear, however, since the write pointer could wrap around allowing overwriting of data which is never read. Therefore SmartGen will always tie these pins off high. Macro Library Guide 115 Flash Memory Block Macro Macro Library Guide 116 Flash Memory Block Fusion Flash Memory Block RD[31:0] BUSY STATUS[1:0] ADDR[17:0] WD[31:0] Function Flash memory block builder for use with SmartGen and Fusion DATAWIDTH[1:0] REN READNEXT PAGESTATUS WEN ERASEPAGE PROGRAM SPAREPAGE AUXBLOCK UNPROTECTPAGE OVERWRITEPAGE DISCARDPAGE OVERWRITEPROTECT PAGELOSSPROTECT PIPE LOCKREQUEST CLK RESET Inputs / Outputs See the description below for an explanation of the inputs and outputs available on the Flash memory block macro. Each Flash Memory block holds 256 kb of data. Although it is functionally similar to a large single-port synchronous RAM, it has several significant differences, including: 1. Address bits are MSB justified, unlike RAM4K9 and RAM512X18 in which the address bits are LSB justified. 2. Write operation updates write data into the block buffer ONLY. To store data permanently into the Flash Memory Block array writes to a page must be followed by a program operation of the same page. 3. The simulation models always execute copy page from Flash memory block array (internal operation) in 65 clock cycles; in silicon the behavior is non-deterministic (63-67 clock cycles). This mismatch is reflected in the number of cycles BUSY is asserted. Operations on Flash memory block are synchronous to rising-edge of CLK. Flash Memory Block Pin Description All Flash memory block signals are active high, except for RESET which is active low. The Flash memory block is a completely synchronous model sensitive to rising edge of CLK input. NAME ADDR[17:0] Macro Library Guide FUNCTION Byte-offset into the Flash memory block array or block buffer of page buffer 117 NAME FUNCTION WD[31:0] Write data DATAWIDTH[31:0] 00 = 1-byte in data_in/out[7:0] 01 = 2-bytes in data_in/out[15:0] 10/11 = 4-bytes in data_in/out[31:0] REN When asserted, initiates a read operation READNEXT When asserted with REN, initiates a read from next address after read to current address is complete. PAGESTATUS When asserted with read, initiates a read page status operation WEN When asserted, interface data is stored into the assembly buffer. ERASEPAGE When asserted, erase addressed page (program all zeroes). PROGRAM When asserted, write the contents of the assembly buffer into the cell array page addressed. SPAREPAGE When asserted, the sector addressed is used to access the spare page within that sector. AUXBLOCK When asserted, the page addressed is used to access the auxiliary block within that page. UNPROTECTPAGE When asserted, the page addressed is copied into the AB and the AB made writeable. OVERWRITEPAGE When asserted, the page addressed is overwritten with the contents of the AB if the page is writeable. DISCARDPAGE When asserted, the contents of the AB are discarded so that a new page write can be started. OVERWRITEPROTECT When asserted, all program operations will set the overwrite protect bit in the auxiliary block of the page being programmed. PAGELOSSPROTECT When asserted, a modified assembly buffer must be programmed or discarded before accessing a new page. PIPE When asserted with REN, read operation completes in 6 cycles. Required to be asserted for CLK speeds above 50MHz. LOCKREQUEST Request to lock user access to Flash memory block array. CLK Input clock. All operations and status are synchronous to rising-edge of this clock. RESET When asserted resets the state of the Flash memory block. RD[31:0] Read data to be sampled when BUSY=0. STATUS[1:0] Status of the last operation completed: 00 = successful completion 01 = Read: single error detected and corrected Write: operation addressed a write-protected page Erase-Page/Program: AB is unmodified 10 = Read: two or more errors detected Erase-Page/Program: Compare operation failed 11 = Write: attempt to write to another page before Programming current page. Functional Description The Fusion datasheet, available here, http://www.actel.com/techdocs/ds/default.aspx, contains a detailed functional description of the entire Flash Memory Block. Simulation Details for Flash Memory Block The Flash memory block array can be pre-loaded with user-defined data. For simulation purposes, you can specify a memory initialization file by over-riding the parameter "MEMORYFILE" in the Verilog netlist and the generic "MEMORYFILE" in Vital netlist. 118 The memory array declared in simulation models stores data that is one block wide. It is 64k x 140 bits. The addressing scheme for accessing this array consists of 16 bits, as shown in the figure below. Block ADDR Page ADDR Sector ADDR ADDR[17:12] SPAREPAGE ADDR[11:7] AUXBLOCK ADDR[6:4] Addressing Scheme for Accessing the Flash Memory Block Memory Array ADDR[17:0] is the Flash memory block interface address, SPAREPAGE and AUXBLOCK are input signals. The memory file for pre-loading an Flash memory block array consists of "strings of address and data in hexadecimal notation with address delimiters (@)" and MUST conform to the rules shown below: 1. Each line MUST contain a string of fixed length (=35 characters) and start with an "@" if it corresponds to an address. 2. Each line following the address line corresponds to a block of data starting at the block address specified in the address line. This applies until the next line with an address specifier (@) is encountered. 3. Each data block consists of 35 hex chars. Hex[31:0] are the data characters corresponding to 16 bytes of user data with Hex[1:0] corresponding to Byte0 and Hex[31:30] corresponding to Byte15. Hex[34:32] are ECC related bits and must be addressed manually. Based on these rules, the format looks like: @Block_Address_0 Block_Data_0 ( required ) Block_Data_1 ( optional ) Block_Data_2 ( optional ) ... ... Block_Data_8 ( Aux block data for this page, optional ) @Block_Address_n Block_Data_n ( required ) Block_Data_n+1 ( optional ) Block_Data_n+2 ( optional ) ... ... ... Block_Data_n+8 ( Aux block data for this page, optional ) A typical memory file looks like: @000…0000 // beginning with @, start address in hex. format. 0s to be padded // between @ and hex address, to get a string of length 35. Macro Library Guide 119 ab101fd01… // 35 hexadecimal characters corresponding to each block of Flash memory block cell eab9c4…… @000…4030 // start address for next data stream c805489e…. // 35 hexadecimal characters corresponding to each block of Flash memory block cell 96986391… User Controlled Generics FAST_SIM - The generic/parameter FAST_SIM is included in pre-synthesis and pre-layout simulation models to reduce cycles wasted in executing the PROGRAM operation. The default is '1', which means the PROGRAM operation is executed with a 4 s simulated delay. You can chose to deactivate the operation by overriding FAST_SIM to 0, in which case PROGRAM is executed with a delay close to real time of 8.4 ms. You can also choose this mode for post-layout simulations. WR_THR - When the number of writes to a page in the Flash memory block array (program operation) exceeds the write threshold specified in the data sheet, the status returned is non-zero. Since the threshold is a huge value, WR_THR is provided to simulate this failure at a reduced number of writes. You can override the generic with any non-zero count (such as 10 or 12). The write threshold exceeded condition is produced on the 10th write to the same page in the Flash memory block array. Note: The string assigned to the generic/parameter MEMORYFILE is preserved through synthesis and place-and-route. But for FAST_SIM and WR_THR generics/parameters, you must reassign the desired value each time after synthesis and place-and-route. 120 Analog System Builder Macro Analog System Builder Analog System Builder VAREF GNDREF AV0 AC0 AT0 DATAOUT0 DATAOUT0 DATAOUT0 AV9 AC9 AT9 ATRTN0 Fusion Function Analog system builder for use Fusion. See the Fusion datasheet for a thorough description of the Analog System Builder. DATAOUT9 DATAOUT9 DATAOUT9 AG0 AG1 ATRTN4 DENAV0 DENAC0 DENAT0 AG9 DENAV0 DENAC0 DENAT0 CMSTB0 CSMTB9 GDON0 GDON9 TMSTB0 TMSTB9 MODE[3:0] TVC[7:0] STC[7:0] CHNUMBER[4:0] BUSY CALIBRATE DATAVALID SAMPLE RESULT[11:0] RTCMATCH RTCXTLMODE RTCXTLSEL RTCPSMMATCH TMSTINT ADCSTART VAREFSEL PWRDWN ADCRESET RTCCLK SYSCLK ACMWEN ACMRESET ACMWDATA[7:0] ACMADDR ACMCLK ACMRDATA[7:0] AB Inputs / Outputs Inputs are listed on the left, outputs on the right. See the description below for an explanation of the inputs and outputs available on the Analog System Builder. For a complete description of the features in the ASB, see the Fusion datasheet. Macro Library Guide 121 Analog System Builder Pin Description Analog System Builder Pin Description Number of bits Direction VAREF 1 Inout External voltage ref.; used as either input or output, depending on VREFSEL GNDREF 1 Input External ground ref. MODE[3:0] 4 Input ADC operating mode Signal Name Function SYSCLK 1 Input External system clock TVC[7:0] 8 Input Clock divide control STC[7:0] 8 Input Sample time control CHNUMBER[4:0] 5 Input Analog input channel select ADCSTART 1 Input Start of conversion PWRDWN 1 Input Comparator power-down if 1 ADCRESET 1 Input ADC initialize if 1 BUSY 1 Output 1 – Running conversion CALIBRATE 1 Output 1 – Power-up calibration DATAVALID 1 Output 1 – Valid conversion result RESULT[11:0] 12 Output Conversion result - MSB justified TMSTBINT 1 Input SAMPLE 1 Output CMSTB0 to CMSTB9 10 Input Current monitor strobe – 1 per quad, active high GDON0 to GDON9 10 Input Control to power MOS – 1 per quad TMSTB0 to TMSTB9 10 Input Temperature monitor strobe – 1 per quad; active high DAVOUT0, DACOUT0, DATOUT0 to DAVOUT9, DACOUT9, DATOUT9 30 Output DENAV0, DENAC0, DENAT0 to DENAV9, DENAC9, DENAT9 30 Input Digital input enables – 3 per quad ACMCLK 1 Input ACM clock ACMWEN 1 Input ACM write enable – active high ACMRESET 1 Input ACM reset – active low ACMWDATA[7:0] 8 Input ACM write data ACMRDATA[7:0] 8 Output ACM read data ACMADDR[7:0] 8 Input ACM address VAREFSEL 1 Input 0 = Output internal voltage reference (2.56 V) to VAREF Internal temp. monitor strobe 1 – Analog input is sampled Digital outputs – 3 per quad 1 = Input external voltage reference from VAREF and GNDREF AV0 122 1 Input Analog Quad 0 Analog System Builder Pin Description (Continued) Number of bits Direction AC0 1 Input AG0 1 Output AT0 1 Input ATRTN0 1 Input Temperature monitor return shared by Analog Quads 0 and 1 AV1 1 Input Analog Quad 1 AC1 1 Input AG1 1 Output AT1 1 Input AV2 1 Input AC2 1 Input AG2 1 Output AT2 1 Input ATRTN1 1 Input Temperature monitor return shared by Analog Quads 2 and 3 Analog Quad 3 Signal Name AV3 1 Input AC3 1 Input AG3 1 Output AT3 1 Input Function Analog Quad 2 AV4 1 Input AC4 1 Input AG4 1 Output AT4 1 Input ATRTN2 1 Input Temperature monitor return shared by Analog Quads 4 and 5 AV5 1 Input Analog Quad 5 AC5 1 Input AG5 1 Output AT5 1 Input AV6 1 Input AC6 1 Input AG6 1 Output AT6 1 Input ATRTN3 1 Input Temperature monitor return shared by Analog Quads 6 and 7 Analog Quad 7 AV7 1 Input AC7 1 Input AG7 1 Output Macro Library Guide Analog Quad 4 Analog Quad 6 123 Analog System Builder Pin Description (Continued) Number of bits Direction AT7 1 Input AV8 1 Input AC8 1 Input AG8 1 Output AT8 1 Input ATRTN4 1 Input Temperature monitor return shared by Analog Quads 8 and 9 AV9 1 Input Analog Quad 9 AC9 1 Input AG9 1 Output AT9 1 Input RTCMATCH 1 Output MATCH RTCPSMMATCH 1 Output MATCH connected to VRPSM RTCXTLMODE[1:0] 2 Output Drives XTLOSC RTCMODE[1:0] pins RTCXTLSEL 1 Output Drives XTLOSC MODESEL pin RTCCLK 1 Input Signal Name Function Analog Quad 8 RTC clock input Functional Description The Fusion datasheet, available at http://www.actel.com/techdocs/ds/default.aspx, contains a detailed functional description of the entire Analog System Builder. Connecting Analog Ports Each analog port must be connected to one of the following “virtual pads”: INBUF_A. INBUF_DA or OUTBUF_A. AV0, AC0, AT0, …, AV9, AC9 and AT9 are analog inputs that can be used either as analog or digital inputs. When used as an analog input, the analog input signal (e.g. AV0) must be connected to an INBUF_A, and the corresponding digital input enable (e.g. DENAV0) must be tied to 0. When used as a digital input, the analog input must be connected to an INBUF_DA, and the corresponding digital input enable must be tied to 1. All other analog inputs (ATRETURN01, ATRETURN23, ATRETURN45, ATRETURN67, and ATRETURN89) must be connected to an INBUF_A. Note: ATRETURN01, ATRETURN23, ATRETURN45, ATRETURN67, and ATRETURN89 must be connected to an INBUF_A, even though they have no function in the simulation model. Analog outputs (AG0, …, AG9) must be connected to an OUTBUF_A instance. VAREF is an inout pad and does not need to be connected to INBUF_A or OUTBUF_A. Serialization The analog ports are represented by a 1-bit wide port in both the Verilog and VHDL simulation models. Verilog modules and VHDL functions were developed to drive a real value through a 1-bit port and to read an analog value from a 1-bit port. The Analog System Builder macro contains embedded read and drive logic to read from the analog input and drive the analog output, respectively. 124 The drive module/function converts a real value into a 64-bit value, serializes it and streams it in zero simulation time, using delta delays. The read module/function deserializes a 64-bit stream into a 64-bit value and converts it into a real value. Connecting Analog Ports with Verilog Two Verilog modules (drive_analog_io and read_analog_io) are available to drive an analog input and read an analog output. You must instantiate a drive_analog_io for each analog input and a read_analog_io for each analog output. The read_analog_io starts as soon as there is a non 'Z' data bit on the module input pin. All read and drive operations happen in zero time (delta delays). drive_analog_input is a new module with the same functionality as drive_analog_io and can be used interchangeably to drive analog inputs. Example: drive_analog_io with an INBUF_A and OUTBUF_A instantiation wire AV0_stream_pad, AV0_stream_y, AG0_d, AG0_pad; wire [63:0] AG0_VECTOR; real AV0_real; drive_analog_io drive_AV0 ( $realtobits(AV0_real), AV0_stream_pad ); INBUF_A inbuf_AV0 ( .Y(AV0_stream_y), .PAD (AV0_stream_pad) ); AB ab_inst ( … .AV0 (AV0_stream_y), … .AG0 (AG0_d), … ); OUTBUF_A outbuf_AG0 ( .PAD(AG0_pad), . D (AG0_d) ); initial begin AV0_real <= 1.28; end Connecting Analog Ports with VHDL Similarly, two VHDL functions (drive_analog_input and read_analog_input) are available to drive an analog input and read an analog output. These functions are part of the analog_io VHDL package. The read_analog_input starts as soon as there is a non 'Z' data bit on the function input pin. All read and drive operations happen in zero time (delta delays). Example: drive_analog_input and read_analog_input with an INBUF_A instantiation use work.analog_io.all; … signal varef_real : real signal AV0_real : real signal varef_serial_out : std_logic; signal AV0_stream_pad : std_logic; signal AV0_stream_y : std_logic; component INBUF_A port( … ); end component; component AB port( … Macro Library Guide 125 ); end component; read_varef : process begin wait until varef_serial_out /= 'Z'; read_analog_input( varef_serial_out, varef_real); end process read_varef; -- concurrent procedural call drive_analog_input( AV0_real, AV0_stream_pad ); drive_quads : process begin AV0_real <= 2.18; end process drive_quads; -- INBUF_A instance inbuf_at0 : INBUF_A port map ( PAD => AV0_stream_pad, Y => AV0_stream_y, … ); -- AB instance ab_inst: AB port map ( VAREF => varef_serial_out, … AV0 => AV0_stream_y, … ); drive_temperature_quad and drive_current_monitor In addition to the standard Verilog drive_analog_io modules and VHDL drive_analog_input procedures used to drive the analog quads, two Verilog modules and VHDL procedures are also available to drive the AC and AT quads. The first Verilog module / VHDL procedure, drive_temperature_quad, takes a temperature in Celsius, converts it into a voltage, and drives it over the digital input. This can be used regardless of which input is selected by the Analog MUX - T-prescaler, temperature monitor or T-direct analog input. The equation is: AT(V) = (Temperature(C) + 273.15 ) * ( 2.30258 * 0.000087248) The second Verilog module / VHDL procedure, drive_current_monitor, can only be used when driving an AC quad that will be used for Current Monitoring. As an input it takes the corresponding AV quad voltage (e.g. AV3's voltage, if driving AC3), the Resistor (in Ohm) and Current (in A) values, to calculate the voltage on the AC quad (see the Fusion datasheet for more information). The resistor must be between the 0.01 and 10 Ohm, and (AV - AC) has to be less than 250 mV. The equation is: AC(V) = AV(V) - (Resistor(Ohm) * Current(A) ) If the analog MUX selects the C-prescaler or the C-direct input, then use the standard VHDL procedure drive_analog_input or Verilog drive_analog_io modules to drive the AC quad. drive_temperature_quad and drive_current_monitor Verilog Example real voltage0, resistor0, current0, temperature0; wire AV0_i, AC0_i, AT0_i; 126 wire AV0_o, AC0_o, AT0_o; drive_analog_io drive_AV0 ( $realtobits(voltage0), AV0_i ); drive_current_monitor drive_CM_AC0 ( $realtobits(voltage0), $realtobits(resistor0), $realtobits(current0), AC0_ i ); drive_temperature_quad drive_AT0 ( $realtobits(temperature0), AT0_ i ); INBUF_A inbuf_a_voltage0 ( .Y(AV0_o), .PAD (AV0_i) ); INBUF_A inbuf_a_current0 ( .Y(AC0_ o), .PAD (AC0_ i) ); INBUF_A inbuf_a_temperature0 ( .Y(AT0_ o), .PAD (AT0_ i) ); AB ab_inst … .AV0 (AV0_ .AC0 (AC0_ .AT0 (AT0_ … ); ( o), o), o), initial begin voltage0 resistor0 current0 temperature0 … End <= <= <= <= 1.00032; 1.0; 1.031; -70.0; drive_temperature_quad and drive_current_monitor VHDL Example component INBUF_A port( PAD : in STD_ULOGIC; Y : out STD_ULOGIC); end component; component AB port( VAREF : INOUT STD_LOGIC ; GNDREF : IN STD_LOGIC ; AV0 : IN STD_LOGIC ; … RTCMATCH : OUT STD_LOGIC ; ACMRDATA : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ) ; end component; signal voltage0_pad, current0_pad, temperature0_pad, voltage0_y, current0_y, temperature0_y, : std_logic; signal voltage0, current0, resistor0, temperature0 : real; -- concurrent procedure calls for driving voltage0_pad, current0_pad, temperature0_pad drive_analog_input( voltage0, voltage0_pad ); drive_current_monitor ( voltage0, resistor0, current0, current0_pad ); drive_temperature_quad(temperature0, temperature0_pad ); drive_aq : process Macro Library Guide 127 begin voltage0 <= 1.00032; resistor0 <= 1.0; current0 <= 1.031; temperature0 <= -70.0; … end process drive_aq; inbuf_a_voltage0 : INBUF_A port map ( PAD => voltage0_pad, Y => voltage0_y ); inbuf_a_current0 : INBUF_A port map ( PAD => current0_pad, Y => current0_y ); inbuf_a_temperature0 : INBUF_A port map ( PAD => ato_pad, Y => temperature0_y ); top: AB port map ( … AV0 => voltage0_y, AC0 => current0_y, AT0 => temperature0_y, … ); drive_current_inputs This module/procedure has been added to both Verilog and VHDL libraries to drive both the pads of an AV/AC pair when configured as a current monitor. Voltage for AV, resistor and current are the inputs, serialized AV and AC are the outputs. You can use this module/procedure to replace a pair of drive_analog_input and drive_current_monitor instances, as shown in the example below. drive_current_inputs Verilog Example Two drivers for driving inputs to voltage and current pads: drive_analog_io drive_AV0 ( $realtobits(voltage0), AV0_i ); drive_current_monitor drive_CM_AC0 ( $realtobits(voltage0), $realtobits(resistor0), $realtobits(current0), AC0_i ); drive_current_inputs can drive inputs to both AV and AC pads. For example: drive_current_inputs drive_AV0_AC0 ( $realtobits(voltage0), $realtobits(resistor0), $realtobits(current0), AV0_i, AC0_i ); 128 drive_current_inputs VHDL Example Two drivers for driving inputs to voltage and current pads: drive_analog_io( voltage0, voltage0_pad ); drive_current_monitor ( voltage0, resistor0, current0, current0_pad ); drive_current_inputs can drive inputs to both AV and AC pads. For example: drive_current_inputs ( voltage0, resistor0, current0, voltage0_pad, current0_pad ); drive_differential_inputs This module/procedure has been added to both Verilog and VHDL libraries to drive both the pads of an AV/AC pair when configured for differential inputs. Voltage for AV, AV-AC delta are the inputs, serialized AV and AC are the outputs. drive_varef_out Use this module to drive external VAREF onto VAREF inout pin. Since the applied voltage is serialized, you must ensure that the receiving logic in AB model is ready to receive the serial stream. Actel recommends that you wait until the RESET signal is deasserted (inactive) before assigning the external voltage to VAREF. This module is available in Verilog only. Use drive_analog_input in VHDL to drive external VAREF. For example, driving VAREF externally by instantiating drive_varef_out module/procedure: drive_varef_out Verilog Example drive_varef_out i_VAREF ( .parallel_in($realtobits(val_varef)), .en_out(!SYS_RESET), .serial_out(VAREF) ); initial begin wait(!SYS_RESET); val_varef = 3.00; end drive_varef_out VHDL example … use work.analog_io.all; … signal varef_real : real signal VAREF : std_logic; component AB port( … ); -- concurrent procedure call drive_analog_input( varef_real, varef_pad ); drive_quads : process begin wait until ( SYS_RESET = '1' ); varef_real <= 3.00; Macro Library Guide -- active low reset 129 ... end process drive_quads; ab_inst: AB port map ( VAREF => varef_pad, … … ); drive_analog_input A new module with the same functionality as drive_analog_io has been added to Verilog library (for naming consistency with VHDL). The table below lists procedures/modules available for driving specific Analog System Builder analog input pins in both Verilog and VHDL libraries. Analog input procedure-module AV0…AV9 AC0…AC9 AT0…AT 9 drive_analog_input X X X X X drive_analog_io (Verilog only) X X X X X drive_temperature_quad X drive_current_inputs X drive_differential_inputs drive_current_monitor AV/AC pair GNDREF VAREF X X drive_varef_out (Verilog only) X Each of the AV, AC, and AT pins may be independently configured to be used as a digital input. An AV/ AC pair refers to the AV and AC associated with a specific quad. When used as a pair these inputs will both be driven from one function/module. For example: • AV0 and AC0 can both be driven using drive_current_monitor • AV9 and AC9 can both be driven using drive_differential_voltage Note: Make sure that the Flash Memory System Builder's INIT_DONE output is '1' before you drive the analog block (AB) analog quads (AV0-9, AC0-9 and AT0-9) in the stimulus file. For example: 130 ENTITY testbench IS END testbench; Architecture stimuli of testbench is ... begin ... drive_analog_input ( real(AV0_real), AV0_serial ); ... serial_AV0 : process begin wait until ( INIT_DONE = '1' ); AV0_real <= 1.2; … … end process serial_AV0; Polarity Each quad has a polarity bit, Bx[6], (e.g. B0[6] for AV0-polarity and B4[6] for AV1-polarity). The default polarity is Positive, Bx[6] = '0'. Polarity error occurs when the polarity bit is inconsistent with the quad sign (e.g. AV0 > 0 and AV0-polarity = '1'). AT-quad can only be positive and therefore its polarity can only be set to Positive, Bx[6] = '0'. For ATquad, polarity error occurs if AT is negative or if AT-polarity is set to Negative, Bx[6] = '1'. Prescaler Each quad has a Prescaler Opamp mode bit, Bx[7], (e.g. B0[7] for AV0- prescaler op-amp and B4[7] for AV1 prescaler op-amp). Default is Powerdown, Bx[7] = '0'. If the factor of the prescaler input and scaling factor is greater than the internal reference voltage, the prescaler output will saturate and the prescaler output will be equal to the internal reference voltage (default 2.56V). If a Polarity error occurs (e.g. AV0 > 0 and AV0-polarity = '1'), the prescaler output will be '0.0'. Current Monitor Each C-quad has a Current Monitor Switch bit (B0[4] for AC0, B4[4] for AC1, etc.). This switch needs to be 'ON' if the analog MUX selects the Current Monitor, otherwise the analog MUX output will be '0.0'. Default is Off, B0[4] = '0'. The current monitor output is the difference between the AV and AC multiplied by a factor of 10. CMSTB9 enables the current monitor for analog quads 0-9. Additionally, each C-quad has a Current-Monitor Switch (B0[4]) which enables you to switch the current monitor on or off. This switch needs to be 'ON' if the analog MUX selects the Current Monitor input, otherwise the analog MUX output will be '0.0'. The default setting is off. The following requirements must be met in order to use the current monitor: • ABS(AV) needs to be greater than ABS(AC), otherwise the Current Monitor returns a value of 0.0 • AV and AC must have the same sign and polarity. If not, they are invalid Current monitor inputs, and the current monitor output will be 0.0 • If a Polarity error occurs (e.g. AV0 > 0 and AV0-polarity = '1', or AC0 < 0 and AC0-polarity = '0'), the current monitor output will be 0.0 • If the difference between the AV and AC multiplied by a factor of 10 is greater than the internal reference voltage, the current monitor output saturates and the current monitor output is equal to the Macro Library Guide 131 internal reference voltage (default 2.56V). Temperature Monitor The temperature monitor output is the AT-quad value multiplied by a factor of 12.5. TMSTB0-9 enables the temperature monitor for analog quads 0-9. AT quad only accepts positive voltages, and T-pad polarity has to be set to 0 (Positive) If the AT-quad value multiplied by 12.5 is greater than the internal reference voltage, the temperature monitor output saturates and the temperature monitor output is equal to the internal reference voltage (default 2.56V). When using the temperature monitor, to reflect a temperature change, the value applied to AT should be a differential voltage. AT (delta V) = T (K) * (0.0595 / 300) AT (delta V) = T (K) * 1.983E-4 Using ADC in the Temperature Monitor Using the previous equation, 300K (room temperature) should correspond to 59.5mV (0.0595 on AT, therefore 0.748 at the temperature monitor output / ADC input). When doing a 10-bit ADC conversion using a 2.56V reference voltage, 0.0595 on AT (T=300K) will give a RESULT of 300 (decimal). In this case, 1LSB change on RESULT corresponds to 1K temperature change. Direct Analog Input Each V, C and T-quad has a Direct Analog Input Switch (B0[5] for AV0, B1[5] for AC0, and B3[5] for AT0) which enables you to switch the direct analog input ON or OFF. This switch must be ON if the analog MUX selects the direct analog input, otherwise the analog MUX output will be 0.0. The default setting is OFF. Analog Quad Switch Conditions For the V-quad, the analog MUX can choose the V-prescaler or the V-direct analog input; for the Cquads, the analog MUX can select the C-prescaler, C-direct analog input or current monitor; for the Tquads, the analog MUX can choose the T-prescaler, the T-direct analog input or the Temperature Monitor. Set the V, C and T-prescaler Opamp, V, C and T-direct analog input switches and Current Monitor switch need be set according to the table below for power efficiency and/or ADC conversion accuracy. Selected MUX input Switch \ VPrescaler V-Direct analog input CPrescaler C-Direct analog input Current Monitor TPrescaler T-Direct analog input Temp. Monitor VPrescale Op Amp ON OFF X X X X X X V-Direct analog input switch OFF ON X X "OFF" or "ON and 0<AV<var ef" X X X CPrescale Op-Amp X X ON OFF OFF X X X C-Direct analog input switch X X OFF ON OFF X X X 132 Current Monitor switch X X OFF OFF ON X X X TPrescaler Op-Amp X X X X X ON OFF OFF T-Direct input switch X X X X X OFF ON OFF If you do not meet the switch conditions above, the analog MUX output is 0.0 and an error message appears. In addition, when you the AV direct analog input, the scaling factor for the V-prescaler (B0[2-0]) must be 000 to avoid accidental damage if high voltages are applied. The same restriction applies when you select the AC direct input; the scaling factor for the C-prescaler (B1[2-0]) must be 000. This restriction does not apply to the AT direct analog input. When you do not use an analog input quad as an analog input or a digital input, it must tied to GND (1’b0 in Verilog and ‘0’ in VHDL). The corresponding configuration byte must be set to “00000000”. ADC The Fusion datasheet, available at http://www.actel.com/techdocs/ds/default.aspx, contains a detailed description of the ADC. The power-up calibration time after ADC comes out of reset is 3840 ADC_CLK cycles. The conversion time can vary greatly depending on the SYSCLK frequency, ADCCLK frequency (determined by TVC), the STC settings, and the conversion bit-resolution (MODE). t_conv = t_sync_read + t_sample + t_distrib + t_post_cal + t_sync_write t_conv = SYSCLK period + ((2 + STC) * ADCCLK period) + (8, 10 or 12 * ADCCLK period) + (2 * ADCCLK period) + SYSCLK period t_sync_read: Time for latching the input data t_sample: Time for sampling the analog signal t_distrib: Time for charge distribution t_post_cal: Time for post-calibration t_sync_write: Time for latching the output data A Verilog parameter / VHDL generic enables faster conversion time. See the “User Parameter / Generics” on page 134 for more information. RTC When you use the RTC, you must first write the CTRL_STAT register. Refer to the Fusion datasheet for more information on the functionality of each CTRL_STAT register’s bit. If do not use the RTC, Actel recommends that you write the CTRL_STAT register to “00000000”. When doing a byte-read from the counter, the match register, or the individual match bits, byte 0 must be read before other bytes can be read. A byte 0 read latches the 5-byte register into a 40-bit capture register. The following read operations are made from the 40-bit capture register. For the counter, the match register or the individual match bits, if bytes 1 through 4 are read before byte 0 is read, the read data (ACMRDATA) is irrelevant. Example: Proper read sequence Read COUNTER0 Macro Library Guide 133 Read Read Read Read Read Read Read COUNTER4 COUNTER3 MATCHREG0 MATCHREG2 MATCHBITS0 MATCHBITS2 MATCHBITS3 Register Read and Write Conditions Use ACMADDR, ACWEN and ACMCLK (and ACMWDATA for write) to control RTC read and write operations. Besides setting those control signals properly, the following conditions need to be met before the read or write on the chosen register byte can be executed. COUNTER write: rstb_cnt = '1', cntr_en = '0' and rtm_rst = '0' MATCHREG write: rtm_rst = '0' MATCHBITS can not be overwritten COUNTER read: rstb_cnt = '1' and rtm_rst = '0' MATCHREG read: rtm_rst = '0' MATCHBITS read: rstb_cnt = '1' and rtm_rst = '0' User Parameter / Generics MEMORYFILE This feature enables loading of the memory initial values. This can especially help with the AQ-ACM and RTC configurations. In Verilog the MEMORY is defined as an array of 8 bits by 90, and the memory init file format needs to be of a similar type. In VHDL, the MEMORY is defined as a 720-bit vector, and the memory init file needs to be of a similar type. Default is an empty string (i.e. no memory init file). WARNING_MSGS_ON This feature enables you to disable the warning messages display. Default is ON ('True' in VHDL and '1' in Verilog). FAST_ADC_CONV_SIM Setting FAST_ADC_CONV_SIM to True enables much faster ADC conversion time; In this fast simulation mode, the time for latching input and output data (one SYSCLK period each), and the time for sampling the analog input signal ((2 + STC) * ADCCLK period) are not accounted for. The default is OFF ('False' in VHDL and '0' in Verilog). Set FAST_ADC_CONV_SIM to 'True' in VHDL and to '1' in Verilog to enable this fast simulation mode. Note: This is in simulation mode only. There is no equivalent mode on silicon. 134 Voltage Regulator and Power Supply Monitor Macro Macro Library Guide 135 Voltage Regulator and Power Supply Monitor Voltage Regulator and Power Supply Monitor (VRPSM) Fusion Function The Voltage Regulator and Power Supply Monitor were combined into one macro because the VR and power supply logic work together to control the power-up state of the FPGA core. PUB FPGAGOOD VRPU VRINITSTATE PUCORE RTCPSMMATCH Inputs / Outputs Inputs are listed on the left, outputs on the right. See the VRPSM signal description below for an explanation of the inputs and outputs. The VR generates a 1.5 V power supply (500 mA max) from the 3.3 V power supply. The 1.5 V output is intended to supply all 1.5 V needs of the Fusion product. This regulator requires an external bipolar pass transistor. Enable for this block is generated in the VR logic block, or from an external pad. The 1.5 V is not supplied internally to the Fusion device. It must be routed externally to the VCC pins on the device. Therefore the user is not required to use the V-Reg and can use an off-chip 1.5 V supply if desired. The VRPSM can be enabled from several sources: the PUB pin, RTCMATCH signal from the Analog Block's RTC, or triggered by the PUP0 (RTINIT1 and RTINIT1, PC bits). In the simulation library, PUP0 is represented by VRINITSTATE. VRINITSTATE is FPGAGOOD initial power-up value. It enables you to drive FPGAGOOD to '1' or '0', before the 3.3V is up. The PUCORE output is the Power-Up Bar (PUB) input inverted. Once triggered the VRPSM remains on because of the latching functions of RS flip-flops. Only the FPGA fabric can reset these flip-flops and turn off the VRPSM. Once the FPGAGOOD signal is established, this VRPSM enable mechanism is no longer active. See the tables below for signal descriptions and recommended power-up sequences. VRPSM Signal Description and Power-Up Sequences The signals for the VPRSM macro are listed in the table below. The PUB input comes from the PUB pin on the device and can be pulled high by a signal external to the Fusion device. This can be used to wake up from a standby condition. The inputs VRINITSTATE and RTCPSMMTACH come from the VR Init and RTC blocks respectively and either can initiate a VR power up. NAME Number of Bits Direction FUNCTION PUB 1 INPUT Power-up bar VRPU 1 INPUT Voltage regulator power-up VRINITSTATE 1 INPUT FPGAGOOD initial value (set by 2 flash bits in the FPGA) RTCPSMMATCH 1 INPUT Connected to RTCMATCH signal from RTC FPGAGOOD 1 OUTPUT Indicates that the FPGA is logically functional PUCORE 1 OUTPUT Power-up to core 136 Recommended power up sequences are listed below. ? indicates a don’t care value. PUB VRINITSTATE VRPU RTCPSMMATCH FPGAGOOD ? 1 ? ? 1 ? 0 ? ? 0 1 ? 0 0 0 0 ? 0 0 1 1 ? 1 0 1 1 ? 0 0 0 1 ? 0 0 0 1 ? 0 1 1 1 ? 1 0 1 1 ? 0 0 0 Initial power-up Sequence Sequence Functional Description The Fusion datasheet, available at http://www.actel.com/techdocs/ds/default.aspx, contains a detailed functional description of the entire VRPSM and its uses. Macro Library Guide 137 I/O Macros 138 Input/Output, General Use BIBUF IGLOO, ProASIC3, SmartFusion, Fusion Function Bidirectional Buffer, High Slew (with Hidden Buffer at Y pin). Note: During simulation, when "E" = 0, Y will be shown as "X" as the state of input is unknown. E D PAD Truth Table MODE Y E D PAD Y OUTPUT 1 X D D INPUT 0 X X PAD Attribute Default Values Family I/O Tiles All Default Value Attribute Output PAD, Y Input D, E, PAD ProASIC3 ProASIC3E IO_THRESH LVTTL LVTTL OUT_DRIVE 12 12 SLEW HIGH HIGH 1 SKEW OFF OFF IN_DELAY N/A OFF SCHMITT_TRIGGER N/A OFF RES_PULL NONE NONE CLKBIBUF IGLOO, ProASIC3, SmartFusion, Fusion Function Bidirectional with Input Dedicated to routed Clock Network Truth Table D E PAD Y Output PAD, Y Input D, E, PAD D E PAD Y X 0 Z X X 0 0 0 X 0 1 1 0 1 0 0 1 1 1 1 Attribute Default Values Attribute Default Value ProASIC3 ProASIC3E Family I/O Tiles IO_THRESH LVTTL LVTTL All 1 OUT_DRIVE 12 12 Macro Library Guide SLEW HIGH HIGH SKEW OFF OFF IN_DELAY N/A OFF SCHMITT_TRIGGER N/A OFF RES_PULL NONE NONE 139 CLKBUF IGLOO, ProASIC3, SmartFusion, Fusion Function Input for Dedicated Routed Clock Network Truth Table PAD Y PAD Y 0 0 1 1 Attribute Default Values Attribute Output Y Input PAD Family I/O Tiles All 1 Default Value ProASIC3 ProASIC3E IO_THRESH LVTTL LVTTL IN_DELAY N/A OFF SCHMITT_TRIGGER N/A OFF RES_PULL NONE NONE NOTE 1: For an internal Clock net, refer to the CLKINT macro. INBUF IGLOO, ProASIC3, SmartFusion, Fusion Function Input Buffer Truth Table PAD Y PAD Y 0 0 1 1 Attribute Default Values Attribute Output Y Input PAD 140 Family I/O Tiles All 1 Default Value ProASIC3 ProASIC3E IO_THRESH LVTTL LVTTL OFF IN_DELAY N/A SCHMITT_TRIGGER N/A OFF RES_PULL NONE NONE OUTBUF IGLOO, ProASIC3, SmartFusion, Fusion Function Output Buffer, High Slew Truth Table D PAD D PAD 0 0 1 1 Attribute Default Values Attribute Output PAD Input D Family I/O Tiles All 1 Default Value ProASIC3 ProASIC3E IO_THRESH LVTTL LVTTL OUT_DRIVE 12 12 SLEW HIGH HIGH RES_PULL NONE NONE TRIBUFF IGLOO, ProASIC3, SmartFusion, Fusion Function Tristate Output, High Slew Truth Table E D PAD E PAD 0 Z 1 D Attribute Default Values Attribute Output PAD Input D, E Family I/O Tiles All 1 Macro Library Guide Default Value ProASIC3 ProASIC3E IO_THRESH LVTTL LVTTL OUT_DRIVE 12 12 HIGH SLEW HIGH SKEW OFF OFF RES_PULL NONE NONE 141 IGLOO, Fusion and ProASIC3 Input I/O Macros Names for the input buffers are composed of up to 4 parts: • A base name indicating the type of buffer: INBUF • I/O Technology like LVCMOS • An optional number code 33, 25, 18 or 15 indicating a 3.3, 2.5, 1.8 OR 1.5 voltage level. • An optional one character code (U/D) designating a pull-up/down resistor. When the buffer has no resistor, this code is omitted. For example: • INBUF_LVCMOS25U - An input LVCMOS buffer with 2.5 CMOS voltage levels, pull-up resistor. • INBUF_PCIX - An input PCIX buffer IGLOO, ProASIC3, SmartFusion, Fusion INBUF_X Function Global Input Buffer 1.2V I/Os are not available for Fusion, ProASIC3 or ProASIC3E PAD Y Truth Table Input PAD Output Y PAD Y 0 0 1 1 Family I/O Tiles All 1 Available INBUF_X Macro Types Name INBUF_LVCMOS5 INBUF_LVCMOS5D INBUF_LVCMOS5U INBUF_LVCMOS33 INBUF_LVCMOS33U INBUF_LVCMOS33D INBUF_LVCMOS25 INBUF_LVCMOS25U INBUF_LVCMOS25D INBUF_LVCMOS18 INBUF_LVCMOS18U INBUF_LVCMOS18D INBUF_LVCMOS15 INBUF_LVCMOS15U INBUF_LVCMOS15D INBUF_LVCMOS12 142 Description LVCMOS Input buffer with 2.5V CMOS voltage level, 5.0V tolerant; the A3P030 device does not support INBUF_LVCMOS5, INBUF_LVCMOS5D, or INBUF_LVCMOS5U † LVCMOS Input buffer with 2.5V CMOS voltage level, pull-down resistor, 5.0V tolerant; the A3P030 device does not support INBUF_LVCMOS5, INBUF_LVCMOS5D, or INBUF_LVCMOS5U † LVCMOS Input buffer with 2.5V CMOS voltage level, pull-up resistor, 5.0V tolerant; the A3P030 device does not support INBUF_LVCMOS5, INBUF_LVCMOS5D, or INBUF_LVCMOS5U † LVCMOS Input buffer with 3.3 CMOS voltage level LVCMOS Input buffer with 3.3 CMOS voltage level, pull-up resistor LVCMOS Input buffer with 3.3 CMOS voltage level, pull-down resistor LVCMOS Input buffer with 2.5 CMOS voltage level* LVCMOS Input buffer with 2.5 CMOS voltage level, pull-up resistor* LVCMOS Input buffer with 2.5 CMOS voltage level, pull-down resistor* LVCMOS Input buffer with 1.8 CMOS voltage level LVCMOS Input buffer with 1.8 CMOS voltage level, pull-up resistor LVCMOS Input buffer with 1.8 CMOS voltage level, pull-down resistor LVCMOS Input buffer with 1.5 CMOS voltage level LVCMOS Input buffer with 1.5 CMOS voltage level, pull-up resistor LVCMOS Input buffer with 1.5 CMOS voltage level, pull-down resistor LVCMOS Input buffer with 1.2 CMOS voltage level - EXCEPT Fusion, ProASIC3 and ProASIC3E Available INBUF_X Macro Types (Continued) Name INBUF_LVCMOS12U INBUF_LVCMOS12D INBUF_PCI INBUF_PCIX INBUF_GTL25 INBUF_GTL33 INBUF_GTLP25 INBUF_GTLP33 INBUF_HSTL_I INBUF_HSTL_II INBUF_SSTL2_I INBUF_SSTL2_II INBUF_SSTL3_I INBUF_SSTL3_II INBUF_A INBUF_DA INBUF_FF Description LVCMOS Input buffer with 1.2 CMOS voltage level, pull-up resistor - EXCEPT Fusion, ProASIC3 and ProASIC3E LVCMOS Input buffer with 1.5 CMOS voltage level, pull-down resistor - EXCEPT Fusion, ProASIC3 and ProASIC3E PCI Input buffer † PCIX Input buffer † GTL Input buffer with 2.5 CMOS voltage level* † GTL Input buffer with 3.3 CMOS voltage level* † GTLP Input buffer with 2.5 CMOS voltage level* † GTLP Input buffer with 3.3 CMOS voltage level* † HSTL Class I Input buffer* † HSTL Class II Input buffer* † SSTL2 Class I Input buffer* † SSTL2 Class II Input buffer* † SSTL3 Class I Input buffer* † SSTL3 Class II Input buffer* † Analog input buffer; you must connect the GNDREF and ATRTN01 - ATRTN89 pads (in the Analog System Builder) to this buffer. You cannot use a generic INBUF in place of INBUF_A. Digital or analog input buffer; you must connect the voltage, current, and temperature monitoring pads (from the Analog System Builder) to this macro. You cannot use a generic INBUF in place of INBUF_DA. Flash*Freeze input buffer; Flash*Freeze is available only for low power devices: IGLOO PLUS, IGLOOe, IGLOO and ProASIC3L. See the Flash*Freeze section of the device handbook or the Libero IDE online help for more information on this macro and its implementation. † = not supported in IGLOO PLUS or SmartFusion * = LVCMOS 2.5 V and LVCMOS 2.5 V / 5.0 V I/O standards are identical in the ProASIC3 family. For the A3P030 device, these standards have no clamp diode; therefore, they both behave like a LVCMOS 2.5 V standard. For other ProASIC3 devices, these standards have a clamp diode; therefore, they both behave like a LVCMOS 2.5 V / 5.0 V input standard. Macro Library Guide 143 Bi-Directional I/O Macros Names for the bi-directional buffers are composed of up to 4 parts: • A base name indicating the type of buffer: BIBUF • Optional IO Technology like LVCMOS • An optional number code indicating drive strength in milli-amps. • An optional one character code (S/F) indicating high(F) slew or low(S) slew • An optional one character code (U/D) designating a pull-up/down resistor. When the buffer has no resistor, this code is omitted. For example: • BIBUF_LVCMOS25U - A bi-directional LVCMOS buffer with 2.5 CMOS voltage levels, pull-up resistor • BIBUF_S_8- A bi-directional buffer with low slew and 8 mA drive strength IGLOO, ProASIC3, SmartFusion, Fusion BIBUF_X Function Bidirectional Buffer (with Hidden Buffer at Y pin) 1.2V I/Os are not available for Fusion, ProASIC3 or ProASIC3E E D PAD Y Input D, E, PAD Output Y, PAD Truth Table MODE E D PAD Y OUTPUT 1 X D D INPUT 0 X X PAD Family Family I/O Tiles All 1 BIBUF_X Macro Types Name BIBUF_LVCMOS33 BIBUF_LVCMOS33U BIBUF_LVCMOS33D BIBUF_LVCMOS25 BIBUF_LVCMOS25U BIBUF_LVCMOS25D BIBUF_LVCMOS18 BIBUF_LVCMOS18U BIBUF_LVCMOS18D BIBUF_LVCMOS15 BIBUF_LVCMOS15U BIBUF_LVCMOS15D BIBUF_LVCMOS12 BIBUF_LVCMOS12U BIBUF_LVCMOS12D BIBUF_PCI 144 Description LVCMOS bi-directional buffer with 3.3 CMOS voltage level LVCMOS bi-directional buffer with 3.3 CMOS voltage level, pull-up resistor LVCMOS bi-directional buffer with 3.3 CMOS voltage level, pull-down resistor LVCMOS Bi-directional buffer with 2.5 CMOS voltage level LVCMOS Bi-directional buffer with 2.5 CMOS voltage level, pull-up resistor LVCMOS Bi-directional buffer with 2.5 CMOS voltage level, pull-down resistor LVCMOS Bi-directional buffer with 1.8 CMOS voltage level LVCMOS Bi-directional buffer with 1.8 CMOS voltage level, pull-up resistor LVCMOS Bi-directional buffer with 1.8 CMOS voltage level, pull-down resistor LVCMOS Bi-directional buffer with 1.5 CMOS voltage level LVCMOS Bi-directional buffer with 1.5 CMOS voltage level, pull-up resistor LVCMOS Bi-directional buffer with 1.5 CMOS voltage level, pull-down resistor LVCMOS Bi-directional buffer with 1.2 CMOS voltage level - EXCEPT Fusion, ProASIC3 and ProASIC3E LVCMOS Bi-directional buffer with 1.2 CMOS voltage level, pull-up resistor - EXCEPT Fusion, ProASIC3 and ProASIC3E LVCMOS Bi-directional buffer with 1.2 CMOS voltage level, pull-down resistor - EXCEPT Fusion, ProASIC3 and ProASIC3E PCI Bi-directional buffer † BIBUF_X Macro Types (Continued) Name BIBUF_PCIX BIBUF_SSTL2_I BIBUF_SSTL2_II BIBUF_SSTL3_I BIBUF_SSTL3_II BIBUF_HSTL_I BIBUF_HSTL_II BIBUF_GTL25 BIBUF_GTL33 BIBUF_GTLP25 BIBUF_GTLP33 BIBUF_F_2 BIBUF_F_2U BIBUF_F_2D BIBUF_F_4 BIBUF_F_4U BIBUF_F_4D BIBUF_F_6 BIBUF_F_6U BIBUF_F_6D BIBUF_F_8 BIBUF_F_8U BIBUF_F_8D BIBUF_F_12 BIBUF_F_12U BIBUF_F_12D BIBUF_F_16 BIBUF_F_16U BIBUF_F_16D BIBUF_F_24 BIBUF_F_24U BIBUF_F_24D BIBUF_S_2 BIBUF_S_2U BIBUF_S_2D BIBUF_S_4 BIBUF_S_4U BIBUF_S_4D BIBUF_S_6 BIBUF_S_6U BIBUF_S_6D BIBUF_S_8 BIBUF_S_8U BIBUF_S_8D BIBUF_S_12 BIBUF_S_12U BIBUF_S_12D BIBUF_S_16 BIBUF_S_16U BIBUF_S_16D BIBUF_S_24 BIBUF_S_24U BIBUF_S_24D Description PCIX Bi-directional buffer † SSTL2 class I bi-directional buffer* † SSTL2 class II bi-directional buffer* † SSTL3 class I bi-directional buffer † SSTL3 class II bi-directional buffer* † HSTL class I bi-directional buffer* † HSTL class II bi-directional buffer* † GTL bi-directional buffer* † GTL bi-directional buffer* † GTLP Bi-directional buffer with 2.5 CMOS voltage level* † GTLP Bi-directional buffer with 3.3 CMOS voltage level* † Bi-directional buffer with high slew Bi-directional buffer with high slew and pull-up resistor Bi-directional buffer with high slew and pull-down resistor Bi-directional buffer with high slew Bi-directional buffer with high slew and pull-up resistor Bi-directional buffer with high slew and pull-down resistor Bi-directional buffer with high slew Bi-directional buffer with high slew and pull-up resistor Bi-directional buffer with high slew and pull-down resistor Bi-directional buffer with high slew Bi-directional buffer with high slew and pull-up resistor Bi-directional buffer with high slew and pull-down resistor Bi-directional buffer with high slew Bi-directional buffer with high slew and pull-up resistor Bi-directional buffer with high slew and pull-down resistor Bi-directional buffer with high slew Bi-directional buffer with high slew and pull-up resistor Bi-directional buffer with high slew and pull-down resistor Bi-directional buffer with high slew † Bi-directional buffer with high slew and pull-up resistor † Bi-directional buffer with high slew and pull-down resistor † Bi-directional buffer with low slew Bi-directional buffer with low slew and pull-up resistor Bi-directional buffer with low slew and pull-down resistor Bi-directional buffer with low slew Bi-directional buffer with low slew and pull-up resistor Bi-directional buffer with low slew and pull-down resistor Bi-directional buffer with low slew Bi-directional buffer with low slew and pull-up resistor Bi-directional buffer with low slew and pull-down resistor Bi-directional buffer with low slew Bi-directional buffer with low slew and pull-up resistor Bi-directional buffer with low slew and pull-down resistor Bi-directional buffer with low slew Bi-directional buffer with low slew and pull-up resistor Bi-directional buffer with low slew and pull-down resistor Bi-directional buffer with low slew Bi-directional buffer with low slew and pull-up resistor Bi-directional buffer with low slew and pull-down resistor Bi-directional buffer with low slew † Bi-directional buffer with low slew and pull-up resistor † Bi-directional buffer with low slew and pull-down resistor † * = not supported in ProASIC3 † = not supported in IGLOO PLUS or SmartFusion Macro Library Guide 145 Clock Buffers Names for the input buffers are composed of up to 3 parts: • A base name indicating the type of buffer: CLKBUF • IO Technology like LVCMOS • An optional number code 33, 25, 18 or 15 indicating a 3.3, 2.5, 1.8 OR 1.5 voltage level IGLOO, ProASIC3, SmartFusion, Fusion CLKBUF_X Function Input for Dedicated Routed Clock Network 1.2V I/Os are not available for Fusion, ProASIC3 or ProASIC3E PAD Y Input PAD Output Y Truth Table PAD Y 0 0 1 1 Family Family I/O Tiles All 1 NOTE 1: For an internal Clock net, refer to the CLKINT macro. Available CLKBUF_X Macro Types Name CLKBUF_LVCMOS5 CLKBUF_LVCMOS33 CLKBUF_LVCMOS25 CLKBUF_LVCMOS18 CLKBUF_LVCMOS15 CLKBUF_LVCMOS12 CLKBUF_PCI CLKBUF_PCIX CLKBUF_GTL25 CLKBUF_GTL33 CLKBUF_GTLP25 CLKBUF_GTLP33 CLKBUF_ HSTL _I CLKBUF_ HSTL _II CLKBUF_SSTL2_I CLKBUF_SSTL2_II CLKBUF_SSTL3_I CLKBUF_SSTL3_II Description LVCMOS Clock buffer with 2.5V CMOS voltage level, 5.0V tolerant; the A3P030 device does not support CLKBUF_LVCMOS5 † LVCMOS Clock buffer with 3.3 CMOS voltage level LVCMOS Clock buffer with 2.5 CMOS voltage level * LVCMOS Clock buffer with 1.8 CMOS voltage level LVCMOS Clock buffer with 1.5 CMOS voltage level LVCMOS Clock buffer with 1.2 CMOS voltage level - EXCEPT Fusion, ProASIC3 and ProASIC3E PCI Clock buffer † PCIX Clock buffer † GTL Clock buffer with 2.5 CMOS voltage level * † GTL Clock buffer with 3.3 CMOS voltage level* † GTLP Clock buffer with 2.5 CMOS voltage level * † GTLP Clock buffer with 3.3 CMOS voltage level * † HSTL Class I Clock buffer * † HSTL Class II Clock buffer * † SSTL2 Class I Clock buffer * † SSTL2 Class II Clock buffer * † SSTL3 Class I Clock buffer * † SSTL3 Class II Clock buffer * † † = not supported in IGLOO PLUS or SmartFusion * = LVCMOS 2.5 V and LVCMOS 2.5 V / 5.0 V I/O standards are identical in the ProASIC3 family. For the A3P030 device, these standards have no clamp diode; therefore, they both behave like a LVCMOS 2.5 V standard. For other ProASIC3 devices, these standards have a clamp diode; therefore, they both behave like a LVCMOS 2.5 V / 5.0 V input standard. 146 Output Buffers Names for the bi-directional buffers are composed of up to 4 parts: • A base name indicating the type of buffer: OUTBUF • Optional IO Technology like LVCMOS • An optional number code indicating drive strength in milli-amps. • An optional one character code (S/F) indicating high (F) slew or low (S) slew Macro Library Guide 147 IGLOO, ProASIC3, SmartFusion, Fusion OUTBUF_X Function Output Buffer 1.2V I/Os are not available for Fusion, ProASIC3 or ProASIC3E D PAD Truth Table D PAD 0 0 1 1 Family Input D Output PAD Family I/O Tiles All 1 Available OUTBUF_X Macro Types Name OUTBUF_LVCMOS5 Description LVCMOS Output buffer with 2.5V CMOS voltage level, 5.0V tolerant; the A3P030 device does not support OUTBUF_LVCMOS5†; see Table 1 on page 149 for a list of devices that support this macro. OUTBUF_LVCMOS33 LVCMOS Output buffer with 3.3 CMOS voltage level; Actel recommends that you use this buffer to drive a 5.0V receiver OUTBUF_LVCMOS25 LVCMOS Output buffer with 2.5 CMOS voltage level OUTBUF_LVCMOS18 LVCMOS Output buffer with 1.8 CMOS voltage level OUTBUF_LVCMOS15 LVCMOS Output buffer with 1.5 CMOS voltage level OUTBUF_LVCMOS12 LVCMOS Output buffer with 1.2 CMOS voltage level - EXCEPT Fusion, ProASIC3 and ProASIC3E OUTBUF_PCI PCI Output buffer † OUTBUF_PCIX PCIX Output buffer † OUTBUF_ HSTL _I HSTL Class I Output buffer * † OUTBUF_ HSTL _II HSTL Class II Output buffer * † OUTBUF_SSTL2_I SSTL2 Class I Output buffer * † OUTBUF_SSTL2_II SSTL2 Class II Output buffer * † OUTBUF_SSTL3_I SSTL3 Class I Output buffer * † OUTBUF_SSTL3_II SSTL3 Class II Output buffer * † OUTBUF_GTL25 GTL Output buffer with 2.5 CMOS voltage level * † OUTBUF_GTL33 GTL Output buffer with 3.3 CMOS voltage level * † OUTBUF_GTLP25 GTLP Output buffer with 2.5 CMOS voltage level * † OUTBUF_GTLP33 GTLP Output buffer with 3.3 CMOS voltage level * † OUTBUF_F_2 Output buffer with high slew OUTBUF_F_4 Output buffer with high slew OUTBUF_F_6 Output buffer with high slew OUTBUF_F_8 Output buffer with high slew OUTBUF_F_12 Output buffer with high slew OUTBUF_F_16 Output buffer with high slew OUTBUF_F_24 Output buffer with high slew † OUTBUF_S_2 Output buffer with low slew OUTBUF_S_4 Output buffer with low slew† OUTBUF_S_6 Output buffer with low slew OUTBUF_S_8 Output buffer with low slew OUTBUF_S_12 Output buffer with low slew OUTBUF_S_16 Output buffer with low slew OUTBUF_S_24 Output buffer with low slew † OUTBUF_A Analog output buffer. You must use this output buffer to indicate your analog outputs. You cannot use a generic OUTBUF in place of OUTBUF_A. † = not supported in IGLOO PLUS or SmartFusion 148 OUTBUF_LVCMOS5 support is device-dedpendent. See Table 1 for a list of supported devices and macros. Table 1: OUTBUF_LVCMOS5 Support by Family Device IGLOO IGLOOe IGLOO+ ProASIC3 ProASIC3E/Fusion ProASIC3L Macro Library Guide N010, N015, N020, N060, N125, N250, 015, 030 All others All All N010, N015, N020, N030Z, 015, 030 All others All 250, 600, and 1000 E600 and E3000 Macro OUTBUF_LVCMOS25 OUTBUF_LVCMOS5 OUTBUF_LVCMOS5 and OUTBUF_LVCMOS25 OUTBUF_LVCMOS25 OUTBUF_LVCMOS25 OUTBUF_LVCMOS5 OUTBUF_LVCMOS5 and OUTBUF_LVCMOS25 OUTBUF_LVCMOS5 OUTBUF_LVCMOS5 and OUTBUF_LVCMOS25 149 Tri-State Buffer Macros Names for the tri-state outputs are composed of up to 4 parts: • A base name indicating the type of buffer: TRIBUFF • Optional IO Technology like LVCMOS • An optional number code indicating drive strength in milli-amps. • An optional one character code (S/F) indicating high(F) slew or low(S) slew • An optional one character code (U/D) designating a pull-up/down resistor. When the buffer has no resistor, this code is omitted. For example: • TRIBUFF_LVCMOS25U - A tri-state LVCMOS output with 2.5 CMOS voltage levels, pullup resistor • TRIBUFF_S_8- A tri-state output with low slew and 8 mA drive strength IGLOO, ProASIC3, SmartFusion, Fusion TRIBUFF_X E D PAD Function Tristate Output 1.2V I/Os are not available for Fusion, ProASIC3 or ProASIC3E Truth Table Input D, E Output PAD Family E PAD 0 Z 1 D Family I/O Tiles All 1 TRIBUFF_X Macro Types Name TRIBUFF_LVCMOS33 TRIBUFF_LVCMOS25 TRIBUFF_LVCMOS18 TRIBUFF_LVCMOS15 TRIBUFF_LVCMOS12 TRIBUFF_LVCMOS12U TRIBUFF_LVCMOS12D TRIBUFF_PCI TRIBUFF_PCIX TRIBUFF_GTL25 TRIBUFF_GTL33 TRIBUFF_GTLP25 TRIBUFF_GTLP33 TRIBUFF_ HSTL _I TRIBUFF_ HSTL _II TRIBUFF_SSTL2_I TRIBUFF_SSTL2_II TRIBUFF_SSTL3_I TRIBUFF_SSTL3_II 150 Description LVCMOS tri-state output with 3.3 CMOS voltage level - Actel recommends that you use this buffer to drive a 5.0V receiver LVCMOS tri-state output with 2.5 CMOS voltage level LVCMOS tri-state output with 1.8 CMOS voltage level LVCMOS tri-state output with 1.5 CMOS voltage level LVCMOS tri-state output with 1.2 CMOS voltage level- EXCEPT Fusion, ProASIC3 and ProASIC3E LVCMOS tri-state output with 1.2 CMOS voltage level, pull-up resistor- EXCEPT Fusion, ProASIC3 and ProASIC3E LVCMOS tri-state output with 1.2 CMOS voltage level, pull-down resistor- EXCEPT Fusion, ProASIC3 and ProASIC3E PCI tri-state output † PCIX tri-state output † GTL tri-state output with 2.5 CMOS voltage level * † GTL tri-state output with 3.3 CMOS voltage level * † GTLP tri-state output with 2.5 CMOS voltage level * † GTLP tri-state output with 3.3 CMOS voltage level * † HSTL Class I tri-state output buffer * † HSTL Class II tri-state output buffer * † SSTL2 Class I tri-state output buffer * † SSTL2 Class II tri-state output buffer * † SSTL3 Class I tri-state output buffer * † SSTL3 Class II tri-state output buffer * † TRIBUFF_X Macro Types (Continued) Name Description TRIBUFF_F_2 Tri-state output with high slew TRIBUFF_F_4 Tri-state output with high slew TRIBUFF_F_6 Tri-state output with high slew TRIBUFF_F_8 Tri-state output with high slew TRIBUFF_F_12 Tri-state output with high slew TRIBUFF_F_16 Tri-state output with high slew TRIBUFF_F_24 Tri-state output with high slew* † TRIBUFF_S_2 Tri-state output with low slew TRIBUFF_S_4 Tri-state output with low slew TRIBUFF_S_6 Tri-state output with low slew TRIBUFF_S_8 Tri-state output with low slew TRIBUFF_S_12 Tri-state output with low slew TRIBUFF_S_16 Tri-state output with low slew TRIBUFF_S_24 Tri-state output with low slew * † † = not supported in IGLOO PLUS or SmartFusion * = not supported in ProASIC3 Macro Library Guide 151 Differential I/O Macros IGLOO, ProASIC3, SmartFusion, Fusion INBUF_LVDS; INBUF_LVPECL Function INBUF_LVDS and INBUF_LVPECL Except IGLOO PLUS PADP Y PADN Input PADP; PADN Output Y Available Differential Macro Types Name Description INBUF_LVDS INBUF_LVPECL IGLOO, ProASIC3, SmartFusion, Fusion CLKBUF_LVDS; CLKBUF_LVPECL Function CLKBUF_LVDS and CLKBUF_LVPECL Except IGLOO PLUS PADP Y PADN Input PADP; PADN Output Y Available Differential Macro Types Name CLKBUF_LVDS CLKBUF_LVPECL 152 Description IGLOO, ProASIC3, SmartFusion, Fusion OUTBUF_LVDS; OUTBUF_LVPECL PADP Function OUTBUF_LVDS and OUTBUF_LVPECL Except IGLOO PLUS D PADN Input D Output PADP, PADN Available Differential Macro Types Name Description OUTBUF_LVDS OUTBUF_LVPECL IGLOO, ProASIC3, SmartFusion, Fusion BIBUF_LVDS Function Bi-directional differential I/O, high slew Except IGLOO PLUS E Y PADP D PADN Input D, E, PADP, PADN Output PADP, PADN, Y Truth Table Mode E D PADP PADN Y Output 1 x D !D D Input 0 x x !PADP PADP Family Family I/O Tiles All 2 Attribute Default Values Attribute IO_THRESH OUT_DRIVE SLEW SKEW IN_DELAY SCHMITT_TRIGGER RES_PULL Macro Library Guide Default Value LVDS 24 HIGH OFF OFF NONE NONE 153 IGLOO, ProASIC3, SmartFusion, Fusion TRIBUFF_LVDS Function Tri-state differential output, high slew Except IGLOO PLUS E PADP D PADN Input D, E Truth Table E D PADP PADN 0 x Z Z 1 x D !D Family Family I/O Tiles All 2 Output PADP, PADN, Attribute Default Values Attribute Default Value IO_THRESH OUT_DRIVE SLEW SKEW RES_PULL LVDS 24 HIGH OFF NONE IGLOO, ProASIC3, SmartFusion, Fusion SIMBUF Function SIMBUF is a VIRTUAL I/O used to bring out internal nets that are going to be connected to a top port in the design. This port will be used exclusively for simulation. This virtual I/O is removed by Designer during compile, then re-added in the back-annotated netlist. D PAD Truth Table Output PAD Input D Family I/O Tiles All listed 0 154 D PAD 0 0 1 1 DDR Macros IGLOO, ProASIC3, SmartFusion, Fusion DDR_REG Function DDR (DDR) Register; please refer to the Fusion or ProASIC3 datasheets for more information on the DDR_REG D QR CLK CLR QF Truth Table CLR CLK QR(n+1) 1 X 0 QF(n+1) 0 0 D QF(n) 0 QR(n) D Output QR, QF Input D, CLK, CLR Family Family I/O Tiles All 1 IGLOO, ProASIC3, SmartFusion, Fusion DDR_OUT Function DDR (DDR) output; please refer to the Fusion or ProASIC3 datasheets for more information on the DDR_OUT DR DF Q CLK CLR Truth Table CLR CLK Q 1 X 0 0 DR 0 DF Output Q Input DR, DF, CLK, CLR Family Family I/O Tiles All 1 Macro Library Guide 155 Clocking Resources 156 PLL Macros IGLOO, ProASIC3 PLL for ProASIC3 / IGLOO CLKA EXTFB POWERDOWN Function Static PLL GLA LOCK GLB YB GLC YC Actel recommends that you use SmartGen to generate your PLLs; SmartGen calculates the settings for all the pins in the PLL for the required input-output frequency combinations. OADIV[4:0] OAMUX[2:0] OBMUX[2:0] DLYGLA[4:0] OBDIV[4:0] DLYYB[4:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYYC[4:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL VCOSEL[2:0] Refer to the latest Actel datasheets on PLLs for ProASIC3 / ProASIC3E for more information. They are available at http://www.actel.com. Inputs / Outputs See the description below for an explanation of the inputs and outputs available on the Static PLL for ProASIC3/E; all inputs are shown on the left, and ouputs are to the right. The static PLL supports only a single input. The Combiner is able to combine the PLL with the regular CLKBUF macros and any of the CCC macros to utilize available unused globals. In the symbol shown above, all the required user-accessible inputs and outputs are above the top horizontal line. Optional inputs and outputs are below the top line. The static configuration inputs are below the second line. These pins can only be connected to GND or VCC. The table below summarizes the configuration control bits. Configuration Control Bits Summary NAME FUNCTION FINDIV<6:0> 7-BIT INPUT DIVIDER (/N) FBDIV<6:0> 7-BIT FEEDBACK DIVIDER (/M) OADIV<4:0> 5-BIT OUTPUT DIVIDER (/U) OBDIV<4:0> 5-BIT OUTPUT DIVIDER (/V) OCDIV<4:0> 5-BIT OUTPUT DIVIDER (/W) OAMUX<2:0> 3-BIT POST-PLL MUXA (BEFORE DIVIDER /U) OBMUX<2:0> 3-BIT POST-PLL MUXB (BEFORE DIVIDER /V) Macro Library Guide 157 Configuration Control Bits Summary (Continued) NAME FUNCTION OCMUX<2:0> 3-BIT POST-PLL MUXC (BEFORE DIVIDER /W) FBSEL<1:0> 2-BIT PLL FEEDBACK MUX FBDLY<4:0> FEEDBACK DELAY XDLYSEL 1-BIT PLL FEEDBACK MUX DLYGLA<4:0> DELAY ON GLOBAL A DLYGLB<4:0> DELAY ON GLOBAL B DLYGLC<4:0> DELAY ON GLOBAL C DLYB<4:0> DELAY ON YB DLYC<4:0> DELAY ON YC VCOSEL<2:0> 3-BIT VCO GEAR CONTROL (4 FREQUENCY RANGES) Static Clock with Divider and/or Delay The Combiner is able to combine the clock conditioning circuit macro with the regular CLKBUF macros and the PLL to utilize available unused globals. CLK GL DLYGL[4:0] The CLKDLY is essentially a CLKBUF with a delay. The PLLINT macro is included to unambiguously show Designer which routing resources are required to connect the REFCLK input: The PLLINT is used when REFCLK is driven by a pad in a different I/O tile. 158 Fusion PLL for Fusion CLKA EXTFB POWERDOWN OADIVRST Function Static PLL GLA LOCK GLB YB GLC YC Actel recommends that you use SmartGen to generate your PLLs; SmartGen calculates the settings for all the pins in the PLL for the required input-output frequency combinations. Refer to the latest Actel datasheets on Clocking Resources for Fusion for more information. They are available at http://www.actel.com. OADIVHALF OADIV[4:0] OAMUX[2:0] DLYGLA[4:0] OBDIV[4:0] OBMUX[2:0] DLYYB[4:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYYC[4:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL VCOSEL[2:0] Inputs / Outputs See the description below for an explanation of the inputs and outputs available on the Static PLL for Fusion; all inputs are shown on the left, and ouputs are to the right. The static PLL supports only a single input. The Combiner is able to combine the PLL with the regular CLKBUF macros and any of the CCC macros to utilize available unused globals. In the diagram shown above, all the required user-accessible inputs and outputs are above the top horizontal line. The ones below the top line are optional inputs and outputs. The static configuration inputs are below the third line. These pins can only be connected to GND or VCC. OADIVRST may only be used when you bypass the PLL core (i.e. OAMUX = 001). The purpose of the O(A/B/C)DIVRDST signals is to reset the output of the final clock divider in order to synchronize it with the input to that divider when the PLL is bypassed. The signal is active on a low to high transition. The signal must be low for at least one divider input clock frequency, and then shifted high for at least 3 input clock cycles for the reset operation to work correctly. The table below summarizes the configuration control bits. Configuration Control Bits Summary NAME FUNCTION FINDIV<6:0> 7-BIT INPUT DIVIDER (/N) FBDIV<6:0> 7-BIT FEEDBACK DIVIDER (/M) OADIVHALF* Division by half (see Fusion datasheet for more information) Macro Library Guide 159 Configuration Control Bits Summary (Continued) NAME FUNCTION OADIV<4:0> 5-BIT OUTPUT DIVIDER (/U) OBDIV<4:0> 5-BIT OUTPUT DIVIDER (/V) OCDIV<4:0> 5-BIT OUTPUT DIVIDER (/W) OAMUX<2:0> 3-BIT POST-PLL MUXA (BEFORE DIVIDER /U) OBMUX<2:0> 3-BIT POST-PLL MUXB (BEFORE DIVIDER /V) OCMUX<2:0> 3-BIT POST-PLL MUXC (BEFORE DIVIDER /W) FBSEL<1:0> 2-BIT PLL FEEDBACK MUX FBDLY<4:0> FEEDBACK DELAY XDLYSEL 1-BIT PLL FEEDBACK MUX DLYGLA<4:0> DELAY ON GLOBAL A DLYGLB<4:0> DELAY ON GLOBAL B DLYGLC<4:0> DELAY ON GLOBAL C DLYB<4:0> DELAY ON YB DLYC<4:0> DELAY ON YC VCOSEL<2:0> 3-BIT VCO GEAR CONTROL (4 FREQUENCY RANGES) * OADIVHALF may only be used when you bypass the PLL core (i.e. OAMUX = 001) and the RC Oscillator (RCOSC) drives the CLKA input. Static Clock with Divider and/or Delay The Combiner is able to combine the clock conditioning circuit macro with the regular CLKBUF macros and the PLL to utilize available unused globals. CLK GL DLYGL[4:0] The CLKDLY is essentially a CLKBUF with a delay. The PLLINT macro is included to unambiguously show Designer which routing resources are required to connect the REFCLK input: The PLLINT is used when REFCLK is driven by a pad in a different I/O tile. 160 Dynamic CCC DYNCCC for IGLOO and ProASIC3 CLKA EXTFB POWERDOWN CLKB CLKC SDIN SCLK SSHIFT SUPDATE MODE GLA LOCK GLB YB GLC YC SDOUT IGLOO, ProASIC3 Function Dynamic PLL / Clock Conditioning Circuitry Actel recommends that you use SmartGen to generate your DYNCCCs; SmartGen calculates the settings for all the pins in the DYNCCC for the required input-output frequency combinations. Refer to the latest Actel datasheets on PLLs for ProASIC3 / ProASIC3E for more information. They are available at http://www.actel.com. OADIV[4:0] OAMUX[2:0] DLYGLA[4:0] OBDIV[4:0] OBMUX[2:0] DLYYB[4:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYYC[4:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL VCOSEL[2:0] Inputs / Outputs See the datasheet for an explanation of the inputs and outputs available on the Dynamic CCC for ProASIC3/E; all inputs are shown on the left, and ouputs are to the right. Macro Library Guide 161 SmartFusion FAB_CCC CLKA EXTFB PLLEN OADIVRST GLA LOCK CLKB CLKC OBDIVRST OCDIVRST GLB YB GLC YC Function SmartFusion clock conditioning circuitry Refer to the latest Actel datasheets on CCCs for SmartFusion for more information. They are available at http://www.actel.com. OADIV[4:0] OADIVHALF OBDIVHALF OCDIVHALF OAMUX[2:0] DLYGLA[4:0] DLYGLAFAB OBDIV[4:0] OBMUX[2:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL GLMUXSEL GLMUXCFG BYPASSA BYPASSB BYPASSC Inputs / Outputs In the diagram above, inputs are listed on the left, and outputs on the right; see the SmartFusion datasheet for a full explanation of all inputs and outputs. In the diagram shown above, all the required user-accessible inputs and outputs are above the top horizontal line. The ones below the top line are optional inputs and outputs. OADIVRST may only be used when you bypass the PLL core (i.e. OAMUX = 001). The purpose of the O(A/B/C)DIVRDST signals is to reset the output of the final clock divider in order to synchronize it with the input to that divider when the PLL is bypassed. The signal is active on a low to high transition. The signal must be low for at least one divider input clock frequency, and then shifted high for at least 3 input clock cycles for the reset operation to work correctly. Port Name Direction Source/Sink Description CLKA Input PAD/FPGA/RCOSC/ XTLOSC Primary Reference Clock EXTFB Input PAD/FPGA/GND External feedback clock. When connected to GND, the feedback is internal CLKB input PAD/FPGA/RCOSC/ XTLOSC Secondary Reference Clock (bypass if used) CLKC Input PAD/FPGA/RCOSC/ RTCXTL Secondary Reference Clock (bypass if used) 162 Port Name Direction Source/Sink Description GLA Output FPGA Primary global output driving the FPGA LOCK Output FPGA PLL user lock GLB Output FPGA Secondary global output driving the FPGA Secondary routed output driving the FPGA; logically equivalent to GLB with a different delay insertion YB Output FPGA GLC Output FPGA Secondary global output driving the FPGA FPGA Secondary routed output driving the FPGA; logically equivalent to GLC with a different delay insertion YC Output OADIV Input DSS Primary output clock divider OADIVHALF Input DSS Primary output clock divider OAMUX Input DSS Primary output clock source selection BYPASSA Input DSS Primary output clock bypass source selection. It used to be equal to OAMUX != 000 in Fusion1 and G3. In Fusion2 it is an independent setting DLYGLA Input DSS GLA delay DLYGLAFA B Input DSS GLA output delay selection OBDIV Input DSS Secondary output clock divider OBDIVHALF Input DSS Secondary output clock divider OBMUX Input DSS Secondary output clock source selection Secondary output clock bypass source selection. It used to be equal to OBMUX != 000 in Fusion1 and G3. In Fusion2 it is an independent setting BYPASSB Input DSS DLYGLB Input DSS GLB output delay selection OCDIV Input DSS Secondary output clock divider OCDIVHAL F Input DSS Secondary output clock divider OCMUX Input DSS Secondary output clock source selection BYPASSC Input DSS Secondary output clock bypass source selection. It used to be equal to OCMUX != 000 in Fusion1 and G3. In Fusion2 it is an independent setting DLYGLC Input DSS GLC output delay selection FINDIV Input DSS PLL reference clock divider FBDIV Input DSS PLL feedback clock divider FBDLY Input DSS PLL feedback clock programmable delay selection FBSEL Input DSS PLL feedback clock source selection XDLYSEL Input DSS PLL feedback clock fixed delay selection GLMUXSEL Input DSS Glitchless mux selection GLMUXCFG Input DSS Glitchless mux configuration Macro Library Guide 163 SmartFusion FAB_CCC_DYN CLKA EXTFB PLLEN OADIVRST GLA LOCK CLKB CLKC OBDIVRST OCDIVRST GLB YB GLC YC SDIN SCLK SSHIFT SUPDATE MODE Function SmartFusion dynamic clock conditioning circuitry Refer to the latest Actel datasheets on CCCs for SmartFusion for more information. They are available at http://www.actel.com. SDOUT OADIV[4:0] OADIVHALF OBDIVHALF OCDIVHALF OAMUX[2:0] DLYGLA[4:0] DLYGLAFAB OBDIV[4:0] OBMUX[2:0] DLYGLB[4:0] OCDIV[4:0] OCMUX[2:0] DLYGLC[4:0] FINDIV[6:0] FBDIV[6:0] FBDLY[4:0] FBSEL[1:0] XDLYSEL BYPASSA BYPASSB BYPASSC GLMUXSEL GLMUXCFG Inputs / Outputs In the diagram above, inputs are listed on the left, and outputs on the right; see the SmartFusion datasheet for a full explanation of all inputs and outputs. In the diagram shown above, all the required user-accessible inputs and outputs are above the top horizontal line. The ones below the top line are optional inputs and outputs. OADIVRST may only be used when you bypass the PLL core (i.e. OAMUX = 001). The purpose of the O(A/B/C)DIVRDST signals is to reset the output of the final clock divider in order to synchronize it with the input to that divider when the PLL is bypassed. The signal is active on a low to high transition. The signal must be low for at least one divider input clock frequency, and then shifted high for at least 3 input clock cycles for the reset operation to work correctly. Ports are the same as the FAB_CCC macro but with the addition of the following: Port Name 164 Direction SDIN Input SCLK Input SSHIFT Input SUPDATE Input MODE Input SDOUT Output External Feedback for PLL and DYNCCC External feedback is implemented by relying on self-synchronization in-out on GLA. Since GLA is in the PLL loop, it automatically synchronizes to the incoming clock, and the additional synchronization circuits on divider U are disabled when external feedback is enabled. GLB and GLC still have to rely on synchronization circuits for dividers V and W. As a result, GLA, GLB, and GLC are synchronized when LOCK goes high. External feedback comes with the following restrictions: • Only GLA (the primary global) may be used as the signal for the external feedback loop. • Division factor N is defined as: N = U*a where a= 1, 2, 3, ... • Division factor M is defined as: M >= 5 • Total sum of delays in the feedback loop must be less than 1 VCO period and less than 1 CLKA (incoming clock) period. This restriction only applies to cases where V and or W dividers are used. • M*U < 233 EXTFB must come from an I/O. This I/O is placed at one fixed location per CCC. Please refer to the Fusion datasheet, IGLOO datasheet, or ProASIC3 datasheet for more information. External feedback is supported on both PLL and DYNCCC cells for IGLOO, ProASIC3, SmartFusion and Fusion families. Macro Library Guide 165 Fusion, IGLOO, ProASIC3 PLLINT Function PLL Int A Y Input A Output Y Truth Table A Y 0 0 1 1 Use PLLINT to connect a signal from the FPGA array to the PLL reference clock (CLKA). The input to PLLINT may come from an I/O (excluding the dedicated I/Os for the PLL being driven), local routing, or a global resource. Refer to the latest Actel datasheets on PLLs and Clock Conditioning Circuits (CCC) application notes for more information. They are available at http://www.actel.com. Fusion, IGLOO, ProASIC3 UJTAG UTDO TMS TDI TCK TRSTB Input 166 URSTB UDRCK UDRCAP UDRSH UDRUPD UTDI UIREG0 UIREG1 UIREG2 UIREG3 UIREG4 UIREG6 UIREG7 TDO Output Function The UJTAG macro is a special purpose macro. It is provided to allow users access to the user JTAG circuitry on board the chip. You must instantiate a UJTAG macro in their design if they plan to make use of the user JTAG feature. It is identical to the APA and A500K UJTAG macro. Fusion, IGLOO, ProASIC3 UFROM ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 CLK Input ADDR[0:6], CLK DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Function The UFROM is the USER FlashROM macro. It is a simple 128 X 8 synchronous read-only memory. There is only one UFROM per chip. New data appears on the DO pins after the falling edge of the clock pin. The UFROM can only be programmed by the user via the JTAG pins. There is currently no support for programming the UFROM in any of the CAE tools or libraries, however the simulation models will utilize a memory initialization file so users can specify the contents of the memory for simulation purposes. The memory initialization file will be an ASCII format text file containing exactly 128 lines of 8-character binary strings. Output DO[7:0] Data outputs always transition to X on the rising edge of the input CLK. Please refer to the datasheet for more information. Fusion, IGLOO, ProASIC3 UFROMH ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 CLK Input ADDR[0:6], CLK Macro Library Guide DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 Function UFROMH is a fixed placement version of the UFROM macro. Actel highly recommends that you use this macro instead of UFROM. Output DO[7:0] 167 Fusion, ProASIC3 ULSICC Function Low standby ICC configuration macro. Refer to the Fusion, ProASIC3, or ProASIC3E datasheet (at http:// www.actel.com) for more information on this macro. LSICC Input LSICC Output Fusion RCOSC Function On-chip free-running clock source that generates a 100 Mhz clock. CLKOUT Input 168 Output CLKOUT Refer to the Clocking Resources of the Fusion datasheet for more information on this macro. The Fusion datasheet is available at http:// www.actel.com. Fusion XTLOSC Function On-chip crystal oscillator circuit that works with an off-chip crystal to generate a high-precision clock. XTL SELMODE CLKOUT Refer to the Clocking Resources of the Fusion datasheet for more information on this macro. The Fusion datasheet is available at http:// www.actel.com. RTCMODE[1:0] MODE[1:0] Input Output CLKOUT The XTLOSC requires a physical connection to an external crystal, ceramic resonator, or a resistor/ capacitor network. For simulation purposes you can use the XTL pin to provide a clock signal running at the desired input frequency. Fusion CLKSRC Function Clock buffer used to connect either the RCOSC or the XTLOSC to the core. A Input A Macro Library Guide Y Refer to the Clocking Resources of the Fusion datasheet for more information on this macro. The Fusion datasheet is available at http:// www.actel.com. Output Y 169 Fusion, IGLOO, ProASIC3 CLKDLY Function Static clock with delay. CLK GL Refer to the Clocking Resources of the Fusion and ProASIC3/E datasheets for more information on this macro. They are available at http:// www.actel.com. DLYGL[4:0] Input CLK, DLYGL[4:0] Output GL Fusion CLKDIVDLY Function Static clock with divider and/or delay with global output driver only. CLK RESET GL ODIVHALF ODIV[4:0] DLYGL[4:0] Input CLK, RESET, ODIVHALF, ODIV[4:0], DLYGL[4:0] 170 Output GL Refer to the Clocking Resources of the Fusion and ProASIC3/E datasheets for more information on this macro. They are available at http:// www.actel.com. Fusion CLKDIVDLY1 CLK RESET GL Y Refer to the Clocking Resources of the Fusion datasheet for more information on this macro. It is available at http://www.actel.com. ODIVHALF ODIV[4:0] DLYY[4:0] DLYGL[4:0] Input CLK, RESET, ODIVHALF, ODIV[4:0], DLYY[4:0], DLYGL[4:0] Function Static clock with divider and/or delay with both global output driver and regular net driver. Output GL, Y Fusion NGMUX Function No-glitch MUX. NGMUX provides a special switching sequence between two asynchronous clock domains to avoid generating any unwanted narrow clock pulses. CLK0 CLK1 S Input CLK0, CLK1, S GL Refer to the Clocking Resources of the Fusion datasheet for more information on this macro. It is available at http://www.actel.com. Output GL Transition S from high to low to initiate a switch to CLK0, and from low to high to initiate a switch to CLK1. The output of NGMUX is undefined if S switches again before the previous switch operation has completed. Macro Library Guide 171 A – Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. This appendix contains information about contacting Microsemi SoC Products Group and using these support services. Customer Service Contact Customer Service for non-technical product support, such as product pricing, product upgrades, update information, order status, and authorization. From North America, call 800.262.1060 From the rest of the world, call 650.318.4460 Fax, from anywhere in the world, 408.643.6913 Customer Technical Support Center Microsemi SoC Products Group staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware, software, and design questions about Microsemi SoC Products. The Customer Technical Support Center spends a great deal of time creating application notes, answers to common design cycle questions, documentation of known issues, and various FAQs. So, before you contact us, please visit our online resources. It is very likely we have already answered your questions. Technical Support Visit the Customer Support website (www.microsemi.com/soc/support/search/default.aspx) for more information and support. Many answers available on the searchable web resource include diagrams, illustrations, and links to other resources on the website. Website You can browse a variety of technical and non-technical information on the SoC home page, at www.microsemi.com/soc. Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center. The Technical Support Center can be contacted by email or through the Microsemi SoC Products Group website. Email You can communicate your technical questions to our email address and receive answers back by email, fax, or phone. Also, if you have design problems, you can email your design files to receive assistance. We constantly monitor the email account throughout the day. When sending your request to us, please be sure to include your full name, company name, and your contact information for efficient processing of your request. The technical support email address is [email protected]. 172 My Cases Microsemi SoC Products Group customers may submit and track technical cases online by going to My Cases. Outside the U.S. Customers needing assistance outside the US time zones can either contact technical support via email ([email protected]) or contact a local sales office. Sales office listings can be found at www.microsemi.com/soc/company/contact/default.aspx. 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