RTG4 Macro Library User Guide RTG4 Macro Library User Guide Table of Contents - All Macros AND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 AND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 ARI1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 BIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 BIBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . . . 38 BUFD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 BUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 CLKBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . 40 CLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CLKINT_PRESERVE . . . . . . . . . . . . . . . . . . 15 DDR_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 DDR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 DFN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DFN1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DFN1E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DFN1E1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DFN1E1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DFN1P0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 FCEND_BUFF. . . . . . . . . . . . . . . . . . . . . . . . 19 FCINIT_BUFF . . . . . . . . . . . . . . . . . . . . . . . . 20 INBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 INBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . . . 41 INV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 MACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 MX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 NAND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 NAND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 NAND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 NOR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 NOR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 NOR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 OR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 OUTBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 OUTBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . 42 RAM1K18_RT . . . . . . . . . . . . . . . . . . . . . . . . 48 RAM64x18_RT . . . . . . . . . . . . . . . . . . . . . . . 55 RCLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 RCOSC_50MHz . . . . . . . . . . . . . . . . . . . . . . 20 SLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SYSCTRL_RESET_STATUS . . . . . . . . . . . . 21 SYSRESET . . . . . . . . . . . . . . . . . . . . . . . . . . 20 TRIBUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRIBUFF_DIFF . . . . . . . . . . . . . . . . . . . . . . . UJTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 43 36 32 33 34 35 2 RTG4 Macro Library User Guide Table of Contents - Combinatorial Logic AND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ARI1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFD. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INV. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INVD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MX4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NAND2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NAND3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NAND4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NOR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . OR4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XOR8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 12 13 17 14 13 26 26 27 27 28 28 29 29 30 30 31 31 32 32 33 34 35 3 RTG4 Macro Library User Guide Table of Contents - Sequential Logic DFN1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 DFN1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DFN1E1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DFN1E1C0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DFN1E1P0 . . . . . . . . . . . . . . . . . . . . . . . . . . 24 DFN1P0. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4 RTG4 Macro Library User Guide Table of Contents - RAM Blocks RAM1K18_RT . . . . . . . . . . . . . . . . . . . . . . . . 48 RAM64x18_RT . . . . . . . . . . . . . . . . . . . . . . . 55 5 RTG4 Macro Library User Guide Table of Contents - Math Blocks MACC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 6 RTG4 Macro Library User Guide Table of Contents - I/Os BIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . BIBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . . . CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . DDR_IN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DDR_OUT . . . . . . . . . . . . . . . . . . . . . . . . . . . INBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . INBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . . . OUTBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . OUTBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . TRIBUFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . TRIBUFF_DIFF . . . . . . . . . . . . . . . . . . . . . . . 38 38 39 39 40 44 46 41 41 42 42 43 43 7 RTG4 Macro Library User Guide Table of Contents - Clocking CLKBIBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKBUF . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKBUF_DIFF . . . . . . . . . . . . . . . . . . . . . . . CLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CLKINT_PRESERVE . . . . . . . . . . . . . . . . . . RCLKINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . RCOSC_50MHz . . . . . . . . . . . . . . . . . . . . . . 39 39 40 14 15 15 20 8 RTG4 Macro Library User Guide Table of Contents - Special FCEND_BUFF. . . . . . . . . . . . . . . . . . . . . . . . FCINIT_BUFF . . . . . . . . . . . . . . . . . . . . . . . . SYSCTRL_RESET_STATUS . . . . . . . . . . . . SYSRESET . . . . . . . . . . . . . . . . . . . . . . . . . . UJTAG. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 20 21 20 36 9 Introduction This macro library guide supports the RTG4 family. See the Microsemi website for macro guides for other families. This guide follows a naming convention for sequential macros that is unambiguous and extensible, making it possible to understand the function of the macros by their name alone. The first two mandatory characters of the macro name will indicate the basic macro function: • DF - D-type flip-flop The next mandatory character indicates the output polarity: • I - output inverted (QN with bubble) • N - output non-inverted (Q without bubble) The next mandatory number indicates the polarity of the clock or gate: • 1 - rising edge triggered flip-flop or transparent high latch (non-bubbled) • 0 - falling edge triggered flip-flop or transparent low latch (bubbled) The next two optional characters indicate the polarity of the Enable pin, if present: • E0 - active low enable (bubbled) • E1 - active high enable (non-bubbled) The next two optional characters indicate the polarity of the asynchronous Preset pin, if present: • P0 - active low asynchronous preset (bubbled) • P1 - active high asynchronous preset (non-bubbled) The next two optional characters indicate the polarity of the asynchronous Clear pin, if present: • C0 - active low asynchronous clear (bubbled) • C1 - active high asynchronous clear (non-bubbled) All sequential and combinatorial macros (except MX4 and XOR8) use one logic element in the RTG4 family. As an example, the macro DFN1E1C0 indicates a D-type flip-flop (DF) with a non-inverted (N) Q output, positive-edge triggered (1), with Active High Clock Enable (E1) and Active Low Asychronous Clear (C0). See Figure 1. 10 Figure 1 • Naming Convention 11 RTG4 Macro Library User Guide AND2 2-Input AND A Y B Figure 2 • AND2 Inputs Output A, B Y Truth Table A B Y X 0 0 0 X 0 1 1 1 AND3 3-Input AND A B C Figure 3 • AND3 Input Output A, B, C Y Truth Table 12 A B C Y X X 0 0 X 0 X 0 0 X X 0 1 1 1 1 Y RTG4 Macro Library User Guide AND4 4-Input AND A B Y C D Figure 4 • AND4 Input Output A, B, C, D Y Truth Table A B C D Y X X X 0 0 X X 0 X 0 X 0 X X 0 0 X X X 0 1 1 1 1 1 BUFF Buffer A Y Figure 5 • BUFF Input Output A Y Truth Table A Y 0 0 1 1 13 RTG4 Macro Library User Guide BUFD Buffer. Note that Compile optimization will not remove this macro. A Y Figure 6 • BUFD Input Output A Y Truth Table A Y 0 0 1 1 CLKINT Macro used to route an internal fabric signal to global network. A Figure 7 • CLKINT Input Output A Y Truth Table 14 A Y 0 0 1 1 Y RTG4 Macro Library User Guide CLKINT_PRESERVE Macro used to route an internal fabric signal to global network. It has the same functionality as CLKINT, except that this clock always stay on the global clock network and will not be demoted during design implementation. A Y Figure 8 • CLKINT_PRESERVE Input Output A Y Truth Table A Y 0 0 1 1 RCLKINT Macro used to route an internal fabric signal to a row global buffer, thus creating a local clock. A Y Figure 9 • RCLKINT Input Output A Y Truth Table A Y 0 0 1 1 15 RTG4 Macro Library User Guide SLE Sequential Logic Element. Figure 10 • Sequential Logic Element (SLE) Input Name D CLK EN ALn ADn* SLn SD* LAT* Output Function Data input Clock input Active High CLK enable Asynchronous Load. This active low signal either sets the register or clears the register depending on the value of ADn. Static asynchronous load data. When ALn is active, Q goes to the complement of ADn. Synchronous load. This active low signal either sets the register or clears the register depending on the value of SD. Static synchronous load data. When SLn is active (i.e.low), Q goes to the value of SD at the rising edge of CLK. LAT is always tied to low. Q output is invalid when LAT=1. Q *Note: ADn, SD and LAT are static signals defined at design time and need to be tied to 0 or 1. Truth Table ALn ADn LAT CLK EN SLn SD D Qn+1 0 ADn X X X X X X !ADn 1 X 0 Not rising X X X X Qn 1 X 0 0 X X X Qn 1 X 0 1 0 SD X SD 1 X 0 1 1 X D D X X 1 X X X X X Invalid 16 RTG4 Macro Library User Guide ARI1 The ARI1 macro is responsible for representing all arithmetic operations in the pre-layout phase A B Y C S D FCO FCI Figure 11 • ARI1 Input Output A, B, C, D, FCI Y, S, FCO The ARI1 cell has a 20bit INIT string parameter that is used to configure its functionality. The interpretation of the 16 LSB of the INIT string is shown in the table below. F0 is the value of Y when A = 0 and F1 is the value of Y when A = 1. Table 1 • Interpretation of 16 LSB of the INIT String for ARI1 ADCB Y 0000 INIT[0] 0001 INIT[1] 0010 INIT[2] 0011 INIT[3] 0100 INIT[4] 0101 INIT[5] 0110 INIT[6] 0111 INIT[7] 1000 INIT[8] 1001 INIT[9] 1010 INIT[10] 1011 INIT[11] 1100 INIT[12] 1101 INIT[13] 1110 INIT[14] 1111 INIT[15] F0 F1 17 RTG4 Macro Library User Guide Table 2 • Truth Table for S Y FCI S 0 0 0 0 1 1 1 0 1 1 1 0 Figure 12 • ARI1 Logic The 4 MSB of the INIT string controls the output of the carry bits. The carry is generated using carry propagation and generation bits, which are evaluated according to the tables below. Table 3 • ARI1 INIT[17:16] String Interpretation INIT[17] INIT[16] G 0 0 0 0 1 F0 1 0 1 1 1 F1 18 RTG4 Macro Library User Guide Table 4 • ARI1 INIT[19:18] String Interpretation INIT[19] INIT[18] P 0 0 0 0 1 Y 1 X 1 Table 5 • FCO Truth Table P G FCI FCO 0 G X G 1 X FCI FCI FCEND_BUFF Buffer, driven by the FCO pin of the last macro in the Carry-Chain. A Y Figure 13 • FCEND_BUFF Input Output A Y Truth Table A Y 0 0 1 1 19 RTG4 Macro Library User Guide FCINIT_BUFF Buffer, used to initialize the FCI pin of the first macro in the Carry-Chain. A Y Figure 14 • FCINIT_BUFF Input Output A Y RCOSC_50MHz The RCOSC_50MHz oscillator is an RC oscillator that provides a free running clock of 50MHz at CLKOUT. CLKOUT Figure 15 • RCOSC_50MHz SYSRESET SYSRESET is a special-purpose macro. The Output POWER_ON_RESET_N goes low at power up and when DEVRST_N goes low. Figure 16 • SYSRESET 20 Input Output DEVRST_N POWER_ON_RESET_N RTG4 Macro Library User Guide Truth Table DEVRST_N POWER_ON_RESET_N 0 1 0 1 SYSCTRL_RESET_STATUS This is a special-purpose macro to check the status of the System Controller. The output port RESET_STATUS goes high if the System Controller is in reset.This macro is enabled by selecting the "Enable System Controller Suspend Mode" option in the "Configure Programming Bitstream Settings" tool within Libero. After programming, the device will enter "System Controller Suspend Mode" if TRSTB is tied low during device power up. This macro is not supported in simulation. Figure 17 • SYSCTRL_RESET_STATUS DFN1 D-Type Flip-Flop D Q CLK Figure 18 • DFN1 Input Output D, CLK Q Truth Table CLK D Qn+1 not Rising X Qn D D 21 RTG4 Macro Library User Guide DFN1C0 D-Type Flip-Flop with active low Clear Q D CLK CLR Figure 19 • DFN1C0 Input Output D, CLK, CLR Q Truth Table CLR CLK D Qn+1 0 X X 0 1 not Rising X Qn 1 D D DFN1E1 D-Type Flip-Flop with active high Enable Q D E CLK Figure 20 • DFN1E1 Input Output D, E, CLK Q Truth Table 22 E CLK D Qn+1 0 X X Qn 1 not Rising X Qn 1 D D RTG4 Macro Library User Guide DFN1E1C0 D-Type Flip-Flop, with active high Enable and active low Clear. D Q E CLK CLR Figure 21 • DFN1E1C0 Input Output CLR, D, E, CLK Q Truth Table CLR E CLK D Qn+1 0 X X X 0 1 0 X X Qn 1 1 not Rising X Qn 1 1 D D 23 RTG4 Macro Library User Guide DFN1E1P0 D-Type Flip-Flop with active high Enable and active low Preset. PRE D Q E CLK Figure 22 • DFN1E1P0 Input Output D, E, PRE, CLK Q Truth Table 24 PRE E CLK D Qn+1 0 X X X 1 1 0 X X Qn 1 1 not Rising X Qn 1 1 D D RTG4 Macro Library User Guide DFN1P0 D-Type Flip-Flop with active low Preset. PRE D Q CLK Figure 23 • DFN1P0 Input Output D, PRE, CLK Q Truth Table PRE CLK D Qn+1 0 X X 1 1 not Rising X Qn 1 D D 25 RTG4 Macro Library User Guide INV Inverter A Y Figure 24 • INV Input Output A Y Truth Table A Y 0 1 1 0 INVD Inverter; note that Compile optimization will not remove this macro. A Figure 25 • INVD Input Output A Y Truth Table 26 A Y 0 1 1 0 Y RTG4 Macro Library User Guide MX2 2 to 1 Multiplexer A S Y B Figure 26 • MX2 Input Output A, B, S Y Truth Table A B S Y A X 0 A X B 1 B MX4 4 to 1 Multiplexer This macro uses two logic modules. D0 S0 S1 D1 Y D2 D3 Figure 27 • MX4 Input Output D0, D1, D2, D3, S0, S1 Y Truth Table D3 D2 D1 D0 S1 S0 Y X X X D0 0 0 D0 X X D1 X 0 1 D1 X D2 X X 1 0 D2 D3 X X X 1 1 D3 27 RTG4 Macro Library User Guide NAND2 2-Input NAND A Y B Figure 28 • NAND2 Input Output A, B Y Truth Table A B Y X 0 1 0 X 1 1 1 0 NAND3 3-Input NAND A Y B C Figure 29 • NAND3 Input Output A, B, C Y Truth Table 28 A B C Y X X 0 1 X 0 X 1 0 X X 1 1 1 1 0 RTG4 Macro Library User Guide NAND4 4-input NAND A B Y C D Figure 30 • NAND4 Input Output A, B, C, D Y Truth Table A B C D Y X X X 0 1 X X 0 X 1 X 0 X X 1 0 X X X 1 1 1 1 1 0 NOR2 2-input NOR A Y B Figure 31 • NOR2 Input Output A, B Y Truth Table A B Y 0 0 1 X 1 0 1 X 0 29 RTG4 Macro Library User Guide NOR3 3-input NOR A Y B C Figure 32 • NOR3 Input Output A, B, C Y Truth Table A B C Y 0 0 0 1 X X 1 0 X 1 X 0 1 X X 0 NOR4 4-input NOR A B Y C D Figure 33 • NOR4 Input Output A, B, C, D Y Truth Table 30 A B C D Y 0 0 0 0 1 1 X X X 0 X 1 X X 0 X X 1 X 0 X X X 1 0 RTG4 Macro Library User Guide OR2 2-input OR A Y B Figure 34 • OR2 Input Output A, B Y Truth Table A B Y 0 0 0 X 1 1 1 X 1 OR3 3-input OR A B Y C Figure 35 • OR3 Input Output A, B, C Y Truth Table A B C Y 0 0 0 0 X X 1 1 X 1 X 1 1 X X 1 31 RTG4 Macro Library User Guide OR4 4-input OR A B Y C D Figure 36 • OR4 Input Output A, B, C, D Y Truth Table A B C D Y 0 0 0 0 0 1 X X X 1 X 1 X X 1 X X 1 X 1 X X X 1 1 XOR2 2-input XOR A Y B Figure 37 • XOR2 Input Output A, B Y Truth Table 32 A B Y 0 0 0 0 1 1 1 0 1 1 1 0 RTG4 Macro Library User Guide XOR3 3-input XOR A B Y C Figure 38 • XOR3 Input Output A, B, C Y Truth Table A B C Y 0 0 0 0 1 0 0 1 0 1 0 1 1 1 0 0 0 0 1 1 1 0 1 0 0 1 1 0 1 1 1 1 33 RTG4 Macro Library User Guide XOR4 4-input XOR A B Y C D Figure 39 • XOR4 Input Output A, B, C, D Y Truth Table 34 A B C D Y 0 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 0 1 0 0 1 0 1 0 1 0 0 1 1 0 0 0 1 1 1 1 1 0 0 0 1 1 0 0 1 0 1 0 1 0 0 1 0 1 1 1 1 1 0 0 0 1 1 0 1 1 1 1 1 0 1 1 1 1 1 0 RTG4 Macro Library User Guide XOR8 8-input XOR This macro uses two logic modules. A B C D Y E F G H Figure 40 • XOR8 Input Output A, B, C, D, E, F, G, H Y Truth Table If you have an odd number of inputs that are High, the output is High (1). If you have an even number of inputs that are High, the output is Low (0). For example: A B C D E F G H Y 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 35 RTG4 Macro Library User Guide UJTAG The UJTAG macro is a special purpose macro. It allows access to the user JTAG circuitry on board the chip. You must instantiate a UJTAG macro in your design if you plan to make use of the user JTAG feature. The TMS, TDI, TCK, TRSTB and TDO pins of the macro must be connected to top level ports of the design. UTDO TMS TDI TCK TRSTB URSTB UDRCK UDRCAP UDRSH UDRUPD UTDI UIREG[7:0] Figure 41 • UJTAG Table 6: Ports and Descriptions Port Direction Polarity UIREG[7:0] Output — Output Low Output — Input — Output High Output High Output — Output High URSTB UTDI UTDO UDRSH UDRCAP UDRCK UDRUPD 36 Description This 8-bit bus carries the contents of the JTAG instruction register of each device. Instruction values 16 to 127 are not reserved and can be employed as userdefined instructions URSTB is an Active Low signal and is asserted when the TAP controller is in TestLogic-Reset mode. URSTB is asserted at power-up, and a power-on reset signal resets the TAP controller state. This port is directly connected to the TAP's TDI signal This port is the user TDO output. Inputs to the UTDO port are sent to the TAP TDO output MUX when the IR addess is in user range. Active High signal enabled in the Shift_DR TAP state. Active High signal enabled in the Capture_DR_TAP state. This port is directly connected to the TAP's TCK signal. Active High signal enabled in the Update_DR_TAP state. RTG4 Macro Library User Guide Table 6: Ports and Descriptions (Continued) Port Direction Polarity TCK Input — Input — Output — Input — Input Low TDI TDO TMS TRSTB Description Test Clock Serial input for JTAG boundary scan, ISP, and UJTAG. The TCK pin does not have an internal pull-up/pulldown resistor. Connect TCK to GND or +3.3 V through a resistor (500-1 KΩ) placed closed to the FPGA pin to prevent totem-pole current on the input buffer and TMS from entering into an undesired state. If JTAG is not used, connect it to GND. Test Data in. Serial input for JTAG boundary scan. There is an internal weak pull-up resistor on the TDI pin. Test Data Out. Serial output for JTAG boundary scan. The TDO pin does not have an internal pull-up/pull-down resistor. Test mode select. The TMS pin controls the use of the IEEE1532 boundary scan pins (TCK, TDI, TDO, and TRST). There is an internal weak pullup resistor on the TMS pin. Test reset. The TRSTB pin is an active low input . It synchronously initializes (or resets) the boundary scan circuitry. There is an internal weak pull-up resistor on the TRSTB pin. To hold the JTAG in reset mode and prevent it from entering into undesired states in critical applications, connect TRSTB to GND through a 1 KΩ resistor (placed close to the FPGA pin). 37 RTG4 Macro Library User Guide BIBUF Bidirectional Buffer E D PAD Y Figure 42 • BIBUF Input Output D, E, PAD PAD, Y Truth Table MODE E D PAD Y OUTPUT 1 D D D INPUT 0 X Z X INPUT 0 X PAD PAD BIBUF_DIFF Bidirectional Buffer, Differential I/O E PADP D PADN Y Figure 43 • BIBUF_DIFF Input Output D, E, PADP, PADN PADP, PADN, Y Truth Table MODE E D PADP PADN Y OUTPUT 1 0 0 1 0 OUTPUT 1 1 1 0 1 INPUT 0 X Z Z X INPUT 0 X 0 0 X INPUT 0 X 1 1 X INPUT 0 X 0 1 0 INPUT 0 X 1 0 1 38 RTG4 Macro Library User Guide CLKBIBUF Bidirectional Buffer with Input to global network. Figure 44 • CLKBIBUF Input Output D, E, PAD PAD, Y Truth Table D E PAD Y X 0 Z X X 0 0 0 X 0 1 1 0 1 0 0 1 1 1 1 CLKBUF Input Buffer to global network PAD Y Figure 45 • CLKBUF Input Output PAD Y Truth Table PAD Y 0 0 1 1 39 RTG4 Macro Library User Guide CLKBUF_DIFF Differential I/O macro to global network, Differential I/O PADP Y PADN Figure 46 • INBUF_DIFF Input Output PADP, PADN Y Truth Table 40 PADP PADN Y Z Z Y 0 0 X 1 1 X 0 1 0 1 0 1 RTG4 Macro Library User Guide INBUF Input Buffer PAD Y Figure 47 • INBUF Input Output PAD Y Truth Table PAD Y Z X 0 0 1 1 INBUF_DIFF Input Buffer, Differential I/O PADP Y PADN Figure 48 • INBUF_DIFF Input Output PADP, PADN Y Truth Table PADP PADN Y Z Z X 0 0 X 1 1 X 0 1 0 1 0 1 41 RTG4 Macro Library User Guide OUTBUF Output buffer D PAD Figure 49 • OUTBUF Input Output D PAD Truth Table D PAD 0 0 1 1 OUTBUF_DIFF Output buffer, Differential I/O PADP D PADN Figure 50 • OUTBUF_DIFF Input Output D PADP, PADN Truth Table D 42 PADP PADN 0 0 1 1 1 0 RTG4 Macro Library User Guide TRIBUFF Tristate output buffer E D PAD Figure 51 • TRIBUFF Input Output D, E PAD Truth Table D E PAD X 0 Z D 1 D TRIBUFF_DIFF Tristate output buffer, Differential I/O E PADP D PADN Figure 52 • TRIBUFF_DIFF Input Output D, E PADP, PADN Truth Table D E PADP PADN X 0 Z Z 0 1 0 1 1 1 1 0 43 RTG4 Macro Library User Guide DDR_IN The DDR_IN macro is available for both pre-layout and post-layout simulation flows. It consists of two SLE macros and a latch. The iinput D must be connected to an I/O. Figure 53 • DDR_IN Input Output D, CLK, EN, ALn, ADn, SLn, SD QR, QF Input Name D CLK EN ALn ADn* SLn SD* Function Data Clock Enable Asynchronous Load (Active Low) Asynchronous Data (Active Low) Synchronous Load (Active Low) Synchronous Data Name QR QF Output Function Q (Rising Edge) Q (Falling Edge) *Note: ADn and SD are static inputs defined at design time and need to be tied to 0 or 1. 44 RTG4 Macro Library User Guide Truth Table ALn CLK EN SLn df (Internal Signal) QR(n+1) QF(n+1) 1 Not rising X X df QRn QFn 1 0 X df QRn QFn 1 1 df D dfn X X D QRn QFn 1 1 0 df SD SD 0 X X X !ADn !ADn !ADn 1 1 45 RTG4 Macro Library User Guide DDR_OUT The DDR_OUT macro is an output DDR cell and is available for pre-layout simulation. It consists of two SLE macros. The output Q must be connected to an I/O. Figure 54 • DDR_OUT Input Name DR DF CLK EN ALn ADn* SLn SD* Output Function Data (Rising Edge) Data (Falling Edge) Clock Enable Asynchronous Load (Active Low) Asynchronous Data (Active Low) Synchronous Load (Active Low) Synchronous Data Q *Note: ADn and SD are static inputs defined at design time and need to be tied to 0 or 1. 46 RTG4 Macro Library User Guide Truth Table ALn CLK EN SLn Qn+1 1 not rising X X Qn 0 X Qn 1 1 DRn 1 1 DFn 1 1 0 SD 0 X X X !ADn 1 1 1 47 RTG4 Macro Library User Guide RAM1K18_RT The RAM1K18_RT block contains 24,576 (18,432 with ECC) memory bits and is a true dual-port memory. The RAM1K18_RT memory can also be configured in two-port mode. All read/write operations to the RAM1K18_RT memory are synchronous. To improve the read-data delay, an optional pipeline register at the output is available. Besides the feed-through write mode option to enable immediate access to the write-data, RAM1K18_RT has a Readbefore-write option in the dual-port mode. RAM1K18_RT also adds a Read-enable control to both dual-port and twoport modes. The RAM1K18_RT memory has two data ports which can be independently configured in any combination shown below. 1. ECC Dual-Port RAM with the following configuration: – 1Kx18 on both ports 2. Non-ECC Dual-Port RAM with the following configurations: – Any of 1Kx18 or 2Kx9 on each port – 2Kx12 on both ports 3. ECC Two-Port RAM with the following configurations: – Any of 512x36 or 1Kx18 on each port 4. Non-ECC Two-Port RAM with the following configurations: – Any of 512x36, 1Kx18 or 2Kx9 on each port – 2Kx12 on both ports Functionality The main features of the RAM1K18_RT memory block are as follows: • A RAM1K18_RT block has 18,432 bits with ECC and 24,576 bits without ECC. • A RAM1K18_RT block provides two independent data ports A and B. • RAM1K18_RT has an ECC dual-port mode, for which both ports have word widths equal to 18 bits. – • In non-ECC dual-port mode, each port can be independently configured to any of the following depth/width: 1Kx18 or 2Kx9. In addition, both ports can be configured to 2Kx12. There are 4 unique combinations of nonECC dual-port aspect ratios: – 1Kx18/1Kx18 – 1Kx18/2Kx9 – 2Kx9/1Kx18 – 2Kx12/2Kx12 • RAM1K18_RT also has a two-port mode. In this case, Port A will become the read port and Port B becomes the write port. • RAM1K18_RT has an ECC two-port mode, for which both ports have word widths equal to either 36 or 18 bits. There are 4 unique combinations of ECC two-port aspect ratios: • 48 1Kx18/1Kx18 – 512x36/512x36 – 512x36/1Kx18 – 1Kx18/512x36 – 1Kx18/1Kx18 In non-ECC two-port mode, each port can be independently configured to any of the following depth/width: 512x36, 1Kx18, or 2Kx9. In addition, both ports can be configured to 2Kx12. There are 9 unique combinations of non-ECC two-port aspect ratios: – 512x36/512x36 – 512x36/1Kx18 – 512x36/2Kx9 – 1Kx18/512x36 – 1Kx18/1Kx18 RTG4 Macro Library User Guide – 1Kx18/2Kx9 – 2Kx9/512x36 – 2Kx9/1Kx18 – 2Kx12/2Kx12 • RAM1K18_RT performs synchronous operation for setting up the address as well as writing and reading the data. • RAM1K18_RT has a Read-enable control to both dual-port and two-port modes. • The address, data, block-port select, write-enable and read-enable inputs are registered. • An optional pipeline register with a separate enable and synchronous-reset is available at the read-data port to improve the clock-to-out delay. • The registers in RAM1K18_RT block have an option to mitigate Single-event transients. • There is an independent clock for each port. The memory will be triggered at the rising edge of the clock. • The true dual-port mode supports an optional Read-before-write mode or a feed-through write mode, where the write-data also appears on the corresponding read-data port. • Read from both ports at the same location is allowed. • Read and write on the same location at the same time results in unknown data to be read. There is no collision prevention or detection. However, correct data is expected to be written into the memory. • When ECC is enabled, each port of the RAM1K18_RT memory can raise flags to indicate single-bit-correct and double-bit-detect. Figure 55 shows a simplified block diagram of the RAM1K18_RT memory block and Table 8 gives the port descriptions. The simplified block illustrates the two independent data ports, the read-data pipeline registers, readbefore-write selection and feed-through multiplexors. Figure 55 • Simplified Block Diagram of RAM1K18_RT 49 RTG4 Macro Library User Guide Table 7 • Port List for RAM1K18_RT 50 Pin Name Pin Direction Type Description Polarity A_ADDR[10:0] Input Dynamic Port A address A_BLK[2:0] Input Dynamic Port A block selects High A_CLK Input Dynamic Port A clock Rising A_DIN[17:0] Input Dynamic Port A write-data A_DOUT[17:0] Output Dynamic Port A read-data A_WEN[1:0] Input Dynamic Port A write-enables (per byte) High A_REN Input Dynamic Port A read-enable High A_WIDTH[1:0] Input Static Port A width/depth mode select A_WMODE[1:0] Input Static Port A Read-before-write and Feed-through High write selects A_DOUT_BYPASS Input Static Port A pipeline register select Low A_DOUT_EN Input Dynamic Port A pipeline register enable High A_DOUT_SRST_N Input Dynamic Port A pipeline register synchronous-reset Low B_ADDR[10:0] Input Dynamic Port B address B_BLK[2:0] Input Dynamic Port B block selects High B_CLK Input Dynamic Port B clock Rising B_DIN[17:0] Input Dynamic Port B write-data B_DOUT[17:0] Output Dynamic Port B read-data B_WEN[1:0] Input Dynamic Port B write-enables (per byte) High B_REN Input Dynamic Port B read-enable High B_WIDTH[1:0] Input Static Port B width/depth mode select B_WMODE[1:0] Input Static Port B Read-before-write and Feed-through High write selects B_DOUT_BYPASS Input Static Port B pipeline register select Low B_DOUT_EN Input Dynamic Port B pipeline register enable High B_DOUT_SRST_N Input Dynamic Port B pipeline register synchronous-reset Low ARST_N Input Global Pipeline registers asynchronous-reset Low ECC Input Static Enable ECC High ECC_DOUT_BYPASS Input Static ECC pipeline register select Low A_SB_CORRECT Output Dynamic Port A single-bit correct flag High A_DB_DETECT Output Dynamic Port A double-bit detect flag High RTG4 Macro Library User Guide Table 7 • Port List for RAM1K18_RT (Continued) Pin Name Pin Direction Type Description Polarity B_SB_CORRECT Output Dynami Port B single-bit correct flag High B_DB_DETECT Output Dynami Port B double-bit detect flag High DELEN Input Static Enable SET mitigation High SECURITY Input Static Lock access to SII High Dynami Busy signal from SII High BUSY Output Note: Static inputs are defined at design time and need to be tied to 0 or 1. Port Description A_WIDTH and B_WIDTH Table 8 lists the width/depth mode selections for each port. Two-port mode is in effect when the width of at least one port is 36, and A_WIDTH indicates the read width while B_WIDTH indicates the write width. Table 8 • Width/Depth Mode Selection Depth x Width A_WIDTH/B_WIDTH 2Kx9, 2Kx12 00 1Kx18 01 512x36 (Two-port) 10 A_WEN and B_WEN Table 9 lists the write/read control signals for each port. Two-port mode is in effect when the width of at least one port is 36, and read operation is always enabled. Table 9 • Write/Read Operation Select Depth x Width A_WEN/B_WEN Result 2Kx9, 2Kx12, 00 Perform a read operation 2Kx9, 2Kx12 11 Perform a write operation 1Kx18 01 Write [8:0] 10 Write [17:9] 11 Write [17:0] B_WEN[0] = 1 Write B_DIN[8:0] B_WEN[1] = 1 Write B_DIN[17:9] A_WEN[0] = 1 Write A_DIN[8:0] A_WEN[1] = 1 Write A_DIN[17:9] 512x36 (Two-port write) 51 RTG4 Macro Library User Guide A_ADDR and B_ADDR Table 10 lists the address buses for the two ports. 11 bits are needed to address the 2K independent locations in x9 mode. In wider modes, fewer address bits are used. The required bits are MSB justified and unused LSB bits must be tied to 0. A_ADDR is synchronized by A_CLK while B_ADDR is synchronized to B_CLK. Two-port mode is in effect when the width of at least one port is 36, and A_ADDR provides the read-address while B_ADDR provides the writeaddress. Table 10 • Address Bus Used and Unused Bits A_ADDR/B_ADDR Depth x Width Used Bits Unused Bits (must be tied to 0) 2Kx9, 2Kx12 [10:0] None 1Kx18 [10:1] [0] 512x36 (Two-port) [10:2] [1:0] A_DIN and B_DIN Table 11 lists the data input buses for the two ports. The required bits are LSB justified and unused MSB bits must be tied to 0. Two-port mode is in effect when the width of at least one port is 36, and A_DIN provides the MSB of the writedata while B_DIN provides the LSB of the write-data. Table 11 • Data Input Buses Used and Unused Bits A_DIN/B_DIN Depth x Width Unused Bits (must be tied to 0) Used Bits 2Kx9 [8:0] [17:9] 2Kx12 [11:0] [17:12] 1Kx18 [17:0] None 512x36 A_DIN[17:0] is [35:18] B_DIN[17:0] is [17:0 ] None (Two-port write) A_DOUT and B_DOUT Table 12 lists the data output buses for the two ports. The required bits are LSB justified. Two-port mode is in effect when the width of at least one port is 36, and A_DOUT provides the MSB of the read-data while B_DOUT provides the LSB of the read-data. Table 12 • Data Output Buses Used and Unused Bits A_DOUT/B_DOUT Depth x Width Unused Bits 2Kx9 [8:0] [17:9] 2Kx12 [11:0] [17:12] 1Kx18 [17:0] None 512x36 A_DOUT[17:0] is [35:18] B_DOUT[17:0] is [17:0 ] None (Two-port read) 52 Used RTG4 Macro Library User Guide A_BLK and B_BLK Table 13 lists the block-port select control signals for the two ports. A_BLK is synchronized by A_CLK while B_BLK is synchronized to B_CLK. Two-port mode is in effect when the width of at least one port is 36, and A_BLK controls the read operation while B_BLK controls the write operation. Table 13 • Block-port Select Block-port Select Signal Value Result A_BLK[2:0] 111 Perform read or write operation on Port A. In 36 width mode, perform a read operation from both ports A and B. A_BLK[2:0] Any one bit is 0 No operation in memory from Port A. Port A read-data will be forced to 0. In 36 width mode, the read-data from both ports A and B will be forced to 0. B_BLK[2:0] 111 Perform read or write operation on Port B. In 36 width mode, perform a write operation to both ports A and B. B_BLK[2:0] Any one bit is 0 No operation in memory from Port B. Port B read-data will be forced to 0, unless it is a 36 width mode and write operation to both ports A and B is gated. A_WMODE and B_WMODE In true dual-port write mode, each port has a feed-through write option: • Logic 00 = Read-data port holds the previous value. • Logic 01 = Feed-through, i.e. write-data appears on the corresponding read-data port. This setting is invalid when the width of at least one port is 36 and the two-port mode is in effect. • Logic 10 = Read-before-write, i.e. previous content of the memory appears on the corresponding read-data port before it is overwritten. This setting is invalid when the width of at least one port is 36 and the two-port mode is in effect. A_CLK and B_CLK All signals in ports A and B are synchronous to the corresponding port clock. All address, data, block-port select, writeenable and read-enable inputs must be set up before the rising edge of the clock. The read or write operation begins with the rising edge. Two-port mode is in effect when the width of at least one port is 36, and A_CLK provides the read clock while B_CLK provides the write clock. A_REN and B_REN Enables read operation from the memory on the corresponding port. Read-data Pipeline Register Control signals A_DOUT_BYPASS and B_DOUT_BYPASS A_DOUT_EN and B_DOUT_EN A_DOUT_SRST_N and B_DOUT_SRST_N Two-port mode is in effect when the width of at least one port is 36, and the A_DOUT register signals control the MSB of the read-data while the B_DOUT register signals control the LSB of the read-data. Table 14 describes the functionality of the control signals on the A_DOUT and B_DOUT pipeline registers. Table 14 • Truth Table for A_DOUT and B_DOUT Registers ARST_N _BYPASS _CLK 0 X X 1 0 Not rising _EN _SRST_N D Qn+1 X X X 0 X X X Qn 53 RTG4 Macro Library User Guide Table 14 • Truth Table for A_DOUT and B_DOUT Registers (Continued) ARST_N _BYPASS _CLK 1 0 ↑ 1 0 1 1 _EN _SRST_N D Qn+1 0 X X Qn ↑ 1 0 X 0 0 ↑ 1 1 D D 1 X X X D D ARST_N Connects the Read-data pipeline registers to the global Asynchronous-reset signal. ECC and ECC_DOUT_BYPASS Controls ECC operation. • ECC = 0: Disable ECC. • ECC = 1, ECC_DOUT_BYPASS = 0: Enable ECC Pipelined. • – ECC Pipelined mode inserts an additional clock cycle to Read-data. – In addition, Write-feed-thru and Read-before-write modes add another clock cycle to Read-data. ECC = 1, ECC_DOUT_BYPASS = 1: Enable ECC Non-pipelined. A_SB_CORRECT and B_SB_CORRECT Output flag indicates single-bit correction was performed on the corresponding port. A_DB_DETECT and B_DB_DETECT Output flag indicates double-bit detection was performed on the corresponding port. DELEN Enable Single-event Transient mitigation. SECURITY Control signal, when 1 locks the entire RAM1K18_RT memory from being accessed by the SII. BUSY This output indicates that the RAM1K18_RT memory is being accessed by the SII. 54 RTG4 Macro Library User Guide RAM64x18_RT The RAM64x18_RT block contains 1,536 (1,152 with ECC) memory bits and is a three-port memory providing one write port and two read ports. Write operations to the RAM64x18_RT memory are synchronous. Read operations can be asynchronous or synchronous for setting up the address and reading out the data. Enabling synchronous operation at the read-address port improves setup timing for the read-address and its enable signals. Enabling synchronous operation at the read-data port improves clock-to-out delay. Each data port on the RAM64x18_RT memory can be independently configured in any combination shown below. 1. ECC Three-Port RAM with the following configuration: – 64x18 on all three ports 2. Non-ECC Three-Port RAM with the following configurations: – Any of 64x18 or 128x9 on each port – 128x12 on all three ports Functionality The main features of the RAM64x18_RT memory block are as follows. • There are two independent read-data ports A and B, and one write-data port C. • The write operation is always synchronous. The write-address, write-data, C block-port select and write-enable inputs are registered. • For both read-data ports, setting up the address can be synchronous or asynchronous. • The two read-data ports have address registers with a separate enable and synchronous-reset for synchronous mode operation, which can also be bypassed for asynchronous mode operation. • The two read-data ports have output registers with a separate enable and synchronous-reset for pipeline mode operation, which can also be bypassed for asynchronous mode operation. • Therefore, there are four read operation modes for ports A and B: – Synchronous read-address without read-data pipeline registers (sync-async) – Synchronous read-address with read-data pipeline registers (sync-sync) – Asynchronous read-address without read-data pipeline registers (async-async) – Asynchronous read-address with read-data pipeline registers (async-sync) • In ECC mode, all ports have word widths equal to 18 bits. • In non-ECC mode, each port can be independently configured to any of the following depth/width: 64x18 or 128x9. In addition, all the ports can be configured to 128x12. • The registers in RAM64x18_RT block have an option to mitigate Single-event transients. • There is an independent clock for each port. The memory will be triggered at the rising edge of the clock. • Read from both ports A and B at the same location is allowed. • Read and write on the same location at the same time results in unknown data to be read. • There is no collision prevention or detection. However, correct data is expected to be written into the memory. • When ECC is enabled, each port of the RAM64x18_RT memory can raise flags to indicate single-bit-correct and double-bit-detect. Figure 56 shows a simplified block diagram of the RAM64x18_RT memory block and Table 9 gives the port descriptions. The simplified block diagram illustrates the three independent read/write ports and the pipeline registers on the read port. 55 RTG4 Macro Library User Guide Figure 56 • Simplified Block Diagram of RAM64x18_RT Table 15 • Port List for RAM64x18_RT Pin Name Type Description Polarity A_ADDR[6:0] Input Dynamic Port A read-address A_BLK[1:0] Input Dynamic Port A block selects A_WIDTH Input Static Port A width/depth mode Output Dynamic Port A read-data A_DOUT_EN Input Dynamic Port A read-data pipeline High A_DOUT_BYPASS Input Static Port A read-data pipeline Low A_DOUT_SRST_N Input Dynamic Port A read-data pipeline register synchronous-reset Low A_CLK Input Dynamic Port A registers clock A_ADDR_EN Input Dynamic Port A read-address register A_DOUT[17:0] 56 Pin Direction High Rising High RTG4 Macro Library User Guide Table 15 • Port List for RAM64x18_RT (Continued) Pin Name Pin Direction Type Description Polarity A_ADDR_BYPASS Input Static Port A read-address register Low A_ADDR_SRST_N Input Dynamic Port A read-address register synchronous-reset Low B_ADDR[6:0] Input Dynamic Port B read-address B_BLK[1:0] Input Dynamic Port B block selects B_WIDTH Input Static Port B width/depth mode Output Dynamic Port B read-data B_DOUT_EN Input Dynamic Port B read-data pipeline High B_DOUT_BYPASS Input Static Port B read-data pipeline Low B_DOUT_SRST_N Input Dynamic Port B read-data pipeline register synchronous-reset Low B_CLK Input Dynamic Port B registers clock B_ADDR_EN Input Dynamic Port B read-address register High B_ADDR_BYPASS Input Static Port B read-address register Low B_ADDR_SRST_N Input Dynamic Port B read-address register synchronous-reset Low C_ADDR[6:0] Input Dynamic Port C address C_CLK Input Dynamic Port C clock C_DIN[17:0] Input Dynamic Port C write-data C_WEN Input Dynamic Port C write-enable High C_BLK[1:0] Input Dynamic Port C block selects High C_WIDTH Input Static Port C width/depth mode ARST_N Input Global ECC Input Static Read-address and Read-data pipeline registers asynchronousEnable ECC High ECC_DOUT_BYPAS Input Static ECC pipeline register select Low B_DOUT[17:0] High Rising Rising Low A_SB_CORRECT Output Dynamic Port A single-bit correct flag High A_DB_DETECT Output Dynamic Port A double-bit detect flag High B_SB_CORRECT Output Dynamic Port B single-bit correct flag High B_DB_DETECT Output Dynamic Port B double-bit detect flag High DELEN Input Static Enable SET mitigation High SECURITY Input Static Lock access to SII High Dynamic Busy signal from SII High BUSY Output Note: Static inputs are defined at design time and need to be tied to 0 or 1. 57 RTG4 Macro Library User Guide Port Description A_WIDTH, B_WIDTH and C_WIDTH Table 16 lists the width/depth mode selections for each port. Table 16 • Width/Depth Mode Selection Depth x Width A_WIDTH/B_WIDTH/C_WIDTH 128x9, 128x12 0 64x16, 64x18 1 C_WEN This is the write-enable signal for port C. A_ADDR, B_ADDR and C_ADDR Table 17 lists the address buses for each port. 7 bits are required to address 128 independent locations in x9 mode. In wider modes, fewer address bits are used. The required bits are MSB justified and unused LSB bits must be tied to 0. Table 17 • Address Buses Used and Unused Bits A_ADDR/B_ADDR/C_ADDR Depth x Width Used Bits Unused Bits (must be tied to zero) 128x9, [6:0] None 64x18 [6:1] [0] C_DIN Table 18 lists the write-data input for port C. The required bits are LSB justified and unused MSB bits must be tied to 0. Table 18 • Data Input Bus Used and Unused Bits C_DIN Used Bits Unused Bits (must be tied to 0) 128x9 [8:0] [17:9] 128x12 [11:0] [17:12] 64x18 [17:0] None Depth x Width 58 RTG4 Macro Library User Guide A_DOUT and B_DOUT Table 19 lists the read-data output buses for ports A and B. The required bits are LSB justified. Table 19 • Data Output Used and Unused Bits A_DOUT/B_DOUT Depth x Width Used Bits Unused Bits 128x9 [8:0] [17:9] 128x12 [11:0] [17:12] 64x18 [17:0] None A_BLK, B_BLK and C_BLK Table 20 lists the block-port select control signals for the ports. Table 20 • Block-port Select Block-port Select Signal Value Any one bit is 0 A_BLK[1:0] 11 Any one bit is 0 B_BLK[1:0] 11 Any one bit is 0 Result Port A is not selected and its read-data will be forced to zero. Perform read operation from port A. Port B is not selected and its read-data will be forced to zero. Perform read operation from port B. Port C is not selected. C_BLK[1:0] 11 Perform write operation to port C. C_CLK All signals on port C are synchronous to this clock signal. All write-address, write-data, C block-port select and writeenable inputs must be set up before the rising edge of the clock. The write operation begins with the rising edge. Read-address and Read-data Pipeline Register Control signals A_DOUT_BYPASS, A_ADDR_BYPASS, B_DOUT_BYPASS and B_ADDR_BYPASS A_DOUT_EN, A_ADDR_EN, B_DOUT_EN and B_ADDR_EN A_DOUT_SRST_N, A_ADDR_SRST_N, B_DOUT_SRST_N and B_ADDR_SRST_N 59 RTG4 Macro Library User Guide Table 21 describes the functionality of the control signals on the A_ADDR, B_ADDR, A_DOUT and B_DOUT registers. Table 21 • Truth Table for A_ADDR, B_ADDR, A_DOUT and B_DOUT Registers ARST_N _BYPASS _CLK _EN _SRST_N D Qn+1 0 X X X X X 0 1 0 Not rising X X X Qn 1 0 ↑ 0 X X Qn 1 0 ↑ 1 0 X 0 1 0 ↑ 1 1 D D 1 1 X X X D D ARST_N Connects the read-address and read-data pipeline registers to the global Asynchronous-reset signal. ECC and ECC_DOUT_BYPASS Controls ECC operation. • ECC = 0: Disable ECC. • ECC = 1, ECC_DOUT_BYPASS = 0: Enable ECC Pipelined. • ECC = 1, ECC_DOUT_BYPASS = 1: Enable ECC Non-pipelined. – ECC Pipelined mode inserts an additional clock cycle to Read-data. A_SB_CORRECT and B_SB_CORRECT Output flag indicates single-bit correction was performed on the corresponding port. A_DB_DETECT and B_DB_DETECT Output flag indicates double-bit detection was performed on the corresponding port. DELEN Enable Single-event Transient mitigation. SECURITY Control signal, when 1 locks the entire RAM64x18_RT memory from being accessed by the SII. BUSY This output indicates that the RAM64x18_RT memory is being accessed by the SII. 60 RTG4 Macro Library User Guide MACC 18 bit x 18 bit multiply-accumulate MACC block The MACC block can accumulate the current multiplication product with a previous result, a constant, a dynamic value, or a result from another MACC block. Each MACC block can also be configured to perform a Dot-product operation. All the signals of the MACC block (except CDIN and CDOUT) have optional registers. Figure 57 • MACC Ports 61 RTG4 Macro Library User Guide Table 22 • Ports Port Name Direction Type Polarity Dot-product mode. When DOTP = 1, MACC block performs Dotproduct of two pairs of 9-bit operands. When DOTP = 0, it is called the normal mode. DOTP Input Static SIMD Input Static Reserved. Must be 0. Rising Dynamic edge Input clocks. • CLK[1] is the clock for A[17:9], B[17:9], C[43:18], P[43:18], OVFL_CARRYOUT, ARSHFT17, CDSEL, FDBKSEL and SUB registers. CLK[1:0] Input High Description • CLK[0] is the clock for A[8:0], B[8:0], C[17:0], CARRYIN and P[17:0]. In normal mode, ensure CLK[1] = CLK[0]. A[17:0] Input Dynamic High Input data A. Bypass data A registers. • A_BYPASS[1] is for A[17:9]. Connect to 1, if not registered. A_BYPASS[1:0] Input Static High • A_BYPASS[0] is for A[8:0]. Connect to 1, if not registered. In normal mode, ensure A_BYPASS[0] = A_BYPASS[1]. A_ARST_N[1:0] Input Dynamic Low Asynchronous reset for data A registers. Connect both A_ARST_N[1] and = A_ARST_N[0] to 1 or to the global Asynchronous reset of the design Synchronous reset for data A registers. • A_SRST_N[1] is for A[17:9]. Connect to 1, if not registered. A_SRST_N[1:0] Input Dynamic Low • A_SRST_N[0] is for A[8:0]. Connect to 1, if not registered. In normal mode, ensure A_SRST_N[1] = A_SRST_N[0]. A_EN[1:0] Input Dynamic High Enable for data A registers. • A_EN[1] is for A[17:9]. Connect to 1, if not registered. • A_EN[0] is for A[8:0]. Connect to 1, if not registered. In normal mode, ensure A_EN[1] = A_EN[0]. 62 RTG4 Macro Library User Guide Table 22 • Ports (Continued) Port Name B[17:0] Direction Input Type Polarity Dynamic High Description Input data B. Bypass data B registers. • B_BYPASS[1] is for B[17:9]. Connect to 1, if not registered. B_BYPASS[1:0] Input Static High • B_BYPASS[0] is for B[8:0]. Connect to 1, if not registered. In normal mode, ensure B_BYPASS[0] = B_BYPASS[1]. B_ARST_N[1:0] Input Dynamic Low Asynchronous reset for data B registers. In normal mode, ensure • Connect both B_ARST_N[1] and B_ARST_N[0] to 1 or to the global Asynchronous reset of the design. Synchronous reset for data B registers. • B_SRST_N[1] is for B[17:9]. Connect to 1, if not registered. B_SRST_N[1:0] Input Dynamic Low • B_SRST_N[0] is for B[8:0]. Connect to 1, if not registered. In normal mode, ensure B_SRST_N[1] = B_SRST_N[0]. B_EN[1:0] Input Dynamic High Enable for data B registers. • B_EN[1] is for B[17:9]. Connect to 1, if not registered. • B_EN[0] is for B[8:0]. Connect to 1, if not registered. In normal mode, ensure B_EN[1] = B_EN[0]. Result data. Normal mode • P = D + (CARRYIN + C) + (A * B), when SUB = 0 • P[43:0] Output High P = D + (CARRYIN + C) - (A * B), when SUB = 1 Dot-product mode • P = D + (CARRYIN + C) + 512 * ((AL * BH) + (AH * BL)), when SUB = 0 • P = D + (CARRYIN + C) - 512 * ((AL * BH) + (AH * BL)), when SUB = 1 Notation: • AL = A[8:0], AH = A[17:9] • BL = B[8:0], BH = B[17:9] Refer to Table 25 on page 69 to see how operand D is obtained from P, CDIN or 0. 63 RTG4 Macro Library User Guide Table 22 • Ports (Continued) Port Name OVFL_CARRYOUT Direction Type Output Polarity High Description Overflow or CarryOut • Overflow when OVFL_CARRYOUT_SEL = 0 OVFL_CARRYOUT = (SUM[45] ^ SUM[44]) | (SUM[44] ^ SUM[43]) • P_BYPASS[1:0] Input Static High CarryOut when OVFL_CARRYOUT_SEL = 1 OVFL_CARRYOUT = C[43] ^ D[43] ^ SUM[44] Bypass result P registers. • P_BYPASS[1] is for P[43:18] and OVFL_CARRYOUT. Connect to 1, if not registered. • P_BYPASS[0] is for P[17:0]. Connect to 1, if not registered. In normal mode, ensure P_BYPASS[0] = P_BYPASS[1]. P_ARST_N[1:0] P_SRST_N[1:0] Input Input Dynamic Low Dynamic Low Asynchronous reset for result P registers. Connect both P_ARST_N[1] and P_ARST_N[0] to 1 or to the global Asynchronous reset of the design Synchronous reset for result P registers. • P_SRST_N[1] is for P[43:18] and OVFL_CARRYOUT. Connect to 1, if not registered. • P_SRST_N[0] is for P[17:0]. Connect to 1, if not registered. In normal mode, ensure P_SRST_N[1] = P_SRST_N[0]. P_EN[1:0] Input Dynamic High Enable for result P registers. • P_EN[1] is for P[43:18] and OVFL_CARRYOUT. Connect to 1, if not registered. • P_EN[0] is for P[17:0]. Connect to 1, if not registered. In normal mode, ensure P_EN[1] = P_EN[0]. CDOUT[43:0] Output Cascade High Cascade output of result P. CDOUT is the same as P. The entire bus must either be dangling or drive an entire CDIN of another MACC block in cascaded mode. CARRYIN Input Dynamic High CarryIn for operand C. 64 RTG4 Macro Library User Guide Table 22 • Ports (Continued) Port Name C[43:0] Direction Input Type Polarity Dynamic High Description Routed input for operand C. In Dot-product mode, connect C[8:0] to the CARRYIN. Bypass data C registers. • C_BYPASS[1] is for C[43:18]. Connect to 1, if not registered. C_BYPASS[1:0] Input Static High • C_BYPASS[0] is for C[17:0] and CARRYIN. Connect to 1, if not registered. In normal mode, ensure C_BYPASS[0] = C_BYPASS[1]. C_ARST_N[1:0] Input Dynamic Low Asynchronous reset for data C registers. • Connect both C_ARST_N[1] and C_ARST_N[0] to 1 or to the global Asynchronous reset of the design. Synchronous reset for data C registers. • C_SRST_N[1] is for C[43:18]. Connect to 1, if not registered. C_SRST_N[1:0] Input Dynamic Low • C_SRST_N[0] is for C[17:0] and CARRYIN. Connect to 1, if not registered. In normal mode, ensure C_SRST_N[1] = C_SRST_N[0]. C_EN[1:0] Input Dynamic High Enable for data C registers. • C_EN[1] is for C[43:18]. Connect to 1, if not registered. • C_EN[0] is for C[17:0] and CARRYIN. Connect to 1, if not registered. In normal mode, ensure C_EN[1] = C_EN[0]. CDIN[43:0] Input Cascade High Cascaded input for operand D. The entire bus must be driven by an entire CDOUT of another MACC block. In Dotproduct mode the CDOUT must also be generated by a MACC block in Dot-product mode. Refer to Table 25 on page 69 to see how CDIN is propagated to operand D. ARSHFT17 Input ARSHFT17_BYPASS Input Dynamic High Arithmetic right-shift for operand D. When asserted, a 17-bit arithmetic right-shift is performed on operand D going into the accumulator. Refer to Table 25 on page 69 to see how operand D is obtained from P, CDIN or 0. Static Bypass ARSHFT17 register. Connect to 1, if not registered. High 65 RTG4 Macro Library User Guide Table 22 • Ports (Continued) Port Name Direction Type Polarity Description ARSHFT17_AL_N Input Dynamic Low Asynchronous load for ARSHFT17 register. Connect to 1 or to the global Asynchronous reset of the design. When asserted, ARSHFT17 register is loaded with ARSHFT17_AD. ARSHFT17_AD Input Static Asynchronous load data for ARSHFT17 register. ARSHFT17_SL_N Input Dynamic Low Synchronous load for ARSHFT17 register. Connect to 1, if not registered. See Table 23 on page 67. ARSHFT17_SD_N Input Static Synchronous load data for ARSHFT17 register. See Table 23 on page 67. ARSHFT17_EN Input Dynamic High Enable for ARSHFT17 register. Connect to 1, if not registered. See Table 23 on page 67. High Low CDSEL Input Dynamic High Select CDIN for operand D. When CDSEL = 1, propagate CDIN. When CDSEL = 0, propagate 0 or P depending on FDBKSEL. Refer to Table 23 on page 67 to see how operand D is obtained from P, CDIN or 0. CDSEL_BYPASS Input Static Bypass CDSEL register. Connect to 1, if not registered. High CDSEL_AL_N Input Dynamic Low Asynchronous load for CDSEL register. Connect to 1 or to the global Asynchronous reset of the design. When asserted, CDSEL register is loaded with CDSEL_AD. CDSEL_AD Input Static High Asynchronous load data for CDSEL register. CDSEL_SL_N Input Dynamic Low Synchronous load for CDSEL register. Connect to 1, if not registered. See Table 23 on page 67. CDSEL_SD_N Input Static Synchronous load data for CDSEL register. See Table 23 on page 67. CDSEL_EN Input Dynamic High Enable for CDSEL register. Connect to 1, if not registered. See Table 23 on page 67. Dynamic High Select the feedback from P for operand D. When FDBKSEL = 1, propagate the current value of result P register. Ensure P_BYPASS[1] = 0 and CDSEL = 0. When FDBKSEL = 0, propagate 0. Ensure CDSEL = 0. Refer to Table 25 on page 69 to see how operand D is obtained from P, CDIN or 0. FDBKSEL 66 Input Low RTG4 Macro Library User Guide Table 22 • Ports (Continued) Port Name Direction FDBKSEL_BYPASS Input Type Static Polarity High Description Bypass FDBKSEL register. Connect to 1, if not registered. FDBKSEL_AL_N Input Dynamic Low Asynchronous load for FDBKSEL register. Connect to 1 or to the global Asynchronous reset of the design. When asserted, FDBKSEL register is loaded with FDBKSEL_AD. FDBKSEL_AD Input Static Asynchronous load data for FDBKSEL register. FDBKSEL_SL_N Input Dynamic Low Synchronous load for FDBKSEL register. Connect to 1, if not registered. See Table 23 on page 67. FDBKSEL_SD_N Input Static Low Synchronous load data for FDBKSEL register. See Table 23 on page 67. FDBKSEL_EN Input Dynamic High Enable for FDBKSEL register. Connect to 1, if not registered. See Table 23 on page 67. SUB Input Dynamic High Subtract operation. SUB_BYPASS Input Static Bypass SUB register. Connect to 1, if not registered. High High SUB_AL_N Input Dynamic Low Asynchronous load for SUB register. Connect to 1 or to the global Asynchronous reset of the design. When asserted, SUB register is loaded with SUB_AD. SUB_AD Input Static Asynchronous load data for SUB register. SUB_SL_N Input Dynamic Low Synchronous load for SUB register. Connect to 1, if not registered. See Table 23. SUB_SD_N Input Static Synchronous load data for SUB register. See Table 23. SUB_EN Input Dynamic High High Low Enable for SUB register. Connect to 1, if not registered. See Table 23. Table 23 • Truth Table for Control Registers ARSHFT17, CDSEL, FDBKSEL and SUB _AL_N _AD _BYPASS _CLK _EN _SL_N _SD_N D Qn+1 0 AD X X X X X X AD 1 X 0 Not rising X X X X Qn 1 X 0 0 X X X Qn 1 X 0 1 0 SDn X !SDn 67 RTG4 Macro Library User Guide Table 23 • Truth Table for Control Registers ARSHFT17, CDSEL, FDBKSEL and SUB (Continued) _AL_N 68 _AD _BYPASS _CLK _EN _SL_N _SD_N D Qn+1 1 X 0 1 1 X D D 1 X 1 X 0 X X X Qn 1 X 1 X 1 0 SDn X !SDn 1 X 1 X 1 1 X D D RTG4 Macro Library User Guide Table 24 • Truth Table - Data Registers A, B, C, CARRYIN, P and OVFL_CARRYOUT _ARST_N _BYPASS _CLK _EN _SRST_N D Qn+1 0 X X X X X 0 1 0 Not rising X X X Qn 1 0 0 X X Qn 1 0 1 0 X 0 1 0 1 1 D D 1 1 X 0 X X Qn 1 1 X 1 0 X 0 1 1 X 1 1 D D Table 25 • Truth Table - Propagating Data to Operand D FDBKSEL CDSEL ARSHFT17 Operand D 0 0 x 44'b0 x 1 0 CDIN[43:0] x 1 1 {{17{CDIN[43]}},CDIN[43:17]} 1 0 0 P[43:0] 1 0 1 {{17{P[43]}},P[43:17]} 69 A – Product Support Microsemi SoC Products Group backs its products with various support services, including Customer Service, Customer Technical Support Center, a website, electronic mail, and worldwide sales offices. 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