RF/IF Vector Multiplier ADL5390 FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM VPRF QBBP OBBM VPS2 INMQ INPQ RFOP CMRF RFOM INPI INMI CMOP IBBP IBBM DSOP 04954-001 Matched pair of multiplying VGAs Broad frequency range 20 MHz to 2.4 GHz Continuous magnitude control from +5 dB to −30 dB Output third-order intercept 24 dBm Output 1 dB compression point 11 dBm Output noise floor −148 dBm/Hz Adjustable modulation bandwidth up to 230 MHz Fast output power disable Single-supply voltage 4.75 V to 5.25 V Figure 1. PA linearization and predistortion Amplitude and phase modulation Variable matched attenuator and/or phase shifter Cellular base stations Radio links Fixed wireless access Broadband/CATV RF/IF analog multiplexer GENERAL DESCRIPTION The ADL5390 vector multiplier consists of a matched pair of broadband variable gain amplifiers whose outputs are summed. The separate gain controls for each amplifier are linear-inmagnitude. If the two input RF signals are in quadrature, the vector multiplier can be configured as a vector modulator or as a variable attenuator/phase shifter by using the gain control pins as Cartesian variables. In this case, the output amplitude can be controlled from a maximum of +5 dB to less than –30 dB, and the phase can be shifted continuously over the entire 360° range. Since the signal paths are linear, the original modulation on the inputs is preserved. If the two signals are independent, then the vector multiplier can function as a 2:1 multiplexer or can provide fading from one channel to another. The ADL5390 operates over a wide frequency range of 20 MHz to 2400 MHz. For a maximum gain setting on one channel at 380 MHz, the ADL5390 delivers an OP1dB of 11 dBm, an OIP3 of 24 dBm, and an output noise floor of −148 dBm/Hz. The gain and phase matching between the two VGAs is better than 0.5 dB and 1°, respectively, over most of the operating range. The gain control inputs are dc-coupled with a +/−500 mV differential full-scale range centered about a 500 mV common mode. The maximum modulation bandwidth is 230 MHz, which can be reduced by adding external capacitors to limit the noise bandwidth on the control lines. Both the RF inputs and outputs can be used differentially or single-ended and must be ac-coupled. The impedance of each VGA RF input is 250 Ω to ground, and the differential output impedance is nominally 50 Ω over the operating frequency range. The DSOP pin allows the output stage to be disabled quickly to protect subsequent stages from overdrive. The ADL5390 operates off supply voltages from 4.75 V to 5.25 V while consuming 135 mA. The ADL5390 is fabricated on Analog Devices’ proprietary, high performance 25 GHz SOI complementary bipolar IC process. It is available in a 24-lead, Pb-free CSP package and operates over a −40°C to +85°C temperature range. Evaluation boards are available. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 © 2004 Analog Devices, Inc. All rights reserved. ADL5390 TABLE OF CONTENTS Specifications..................................................................................... 3 RF Output and Matching .......................................................... 13 Absolute Maximum Ratings............................................................ 5 Driving the I-Q Baseband Gain Controls ............................... 13 ESD Caution.................................................................................. 5 Interfacing to High Speed DACs.............................................. 14 Pin Configuration and Function Descriptions............................. 6 Generalized Modulator ............................................................. 15 Typical Performance Characteristics ............................................. 7 Vector Modulator ....................................................................... 15 General Structure ........................................................................... 11 Vector Modulator Example—CDMA2000 ............................. 15 Theory of Operation .................................................................. 11 Quadrature Modulator .............................................................. 17 Noise and Distortion.................................................................. 11 RF Multiplexer ............................................................................ 18 Applications..................................................................................... 12 Evaluation Board ............................................................................ 19 Using the ADL5390.................................................................... 12 Outline Dimensions ....................................................................... 23 RF Input and Matching.............................................................. 12 Ordering Guide .......................................................................... 23 REVISION HISTORY 10/04—Revision 0: Initial Version Rev. 0 | Page 2 of 24 ADL5390 SPECIFICATIONS VS = 5 V, TA = 25°C, ZO = 50 Ω, FRF = 380 MHz, single-ended source drive to INPI and INPQ, and INMI and INMQ are ac-coupled to common, unless otherwise noted. 66.5 Ω termination resistors before ac-coupling capacitors on INPI and INPQ. The specifications refer to one active channel with the other channel input terminated in 50 Ω. The common-mode level for the gain control inputs is 0.5 V. A maximum gain setpoint of 1.0 refers to a differential gain control voltage of 0.5 V. Table 1. Parameter OVERALL FUNCTION Frequency Range Gain Control Range GAIN CONTROL INTERFACE (I and Q) Gain Scaling Modulation Bandwidth Second Harmonic Distortion Third Harmonic Distortion Step Response FRF = 70 MHz Maximum Gain Gain Conformance Output Noise Floor Output IP3 Output 1 dB Compression Point Input 1 dB Compression Point Gain Flatness Gain Matching Phase Matching Input Impedance Output Return Loss FRF = 140 MHz Maximum Gain Gain Conformance Output Noise Floor Output IP3 Output 1 dB Compression Point Input 1 dB Compression Point Gain Flatness Gain Matching Phase Matching Input Impedance Output Return Loss FRF = 380 MHz Maximum Gain Gain Conformance Conditions Min Typ Max Unit 2400 35 MHz dB 3.5 230 1/V MHz 45 dBc 55 dBc 45 47 ns ns Maximum gain setpoint Over gain setpoint of 0.2 to 1.0 Maximum gain setpoint, no RF input RF PIN = −5 dBm, frequency offset = 20 MHz FRF1 = 70 MHz, FRF2 = 72.5 MHz, maximum gain setpoint Maximum gain setpoint Gain setpoint = 0.1 Over any 60 MHz bandwidth At maximum gain setpoint At maximum gain setpoint INPI, INMI, INMQ, INMP (Pins 20, 21, 22, 23) RFOP, RFOM (Pins 9, 10) measured through balun 4.6 0.25 −149 −146 23 dB dB dBm/Hz dBm/Hz dBm 10.7 6.7 0.25 0.5 ±0.25 250||1 9.7 dBm dBm dB dB Degrees Ohms||pF dB Maximum gain setpoint Over gain setpoint of 0.2 to 1.0 Maximum gain setpoint, no RF input RF PIN = −5 dBm, frequency offset = 20 MHz FRF1 = 140 MHz, FRF2 = 142.5 MHz, maximum gain setpoint Maximum gain setpoint Gain setpoint = 0.1 Over any 60 MHz bandwidth At maximum gain setpoint At maximum gain setpoint INPI, INMI, INMQ, INMP (Pins 20, 21, 22, 23) RFOP, RFOM (Pins 9, 10) measured through balun 4.5 0.25 −144 −145 24.4 dB dB dBm/Hz dBm/Hz dBm 11 7.1 0.25 0.5 ±0.25 250||1 9.6 dBm dBm dB dB Degrees Ohms||pF dB Maximum gain setpoint Over gain setpoint of 0.2 to 1.0 4.1 0.25 dB dB 20 Relative to maximum gain QBBP, QBBM, IBBM, IBBP (Pins 4, 5, 14, 15) 500 mV p-p, sinusoidal baseband input singleended 500 mV p-p, 1 MHz, sinusoidal baseband input differential 500 mV p-p, 1 MHz, sinusoidal baseband input differential For gain from −15 dB to +5 dB For gain from +5 dB to −15 dB Rev. 0 | Page 3 of 24 ADL5390 Parameter Output Noise Floor Output IP3 Output 1 dB Compression Point Input 1 dB Compression Point Gain Flatness Gain Matching Phase Matching Input Impedance Output Return Loss FRF = 900 MHz Maximum Gain Gain Conformance Output Noise Floor Output IP3 Output 1 dB Compression Point Input 1 dB Compression Point Gain Flatness Gain Matching Phase Matching Input Impedance Output Return Loss FRF = 2400 MHz Maximum Gain Gain Conformance Output Noise Floor Output IP3 Output 1 dB Compression Point Input 1 dB Compression Point Gain Flatness Gain Matching Phase Matching Input Impedance Output Return Loss POWER SUPPLY Positive Supply Voltage Total Supply Current OUTPUT DISABLE Disable Threshold Maximum Attenuation Enable Response Time Disable Response Time Conditions Maximum gain setpoint, no RF input RF PIN = −5 dBm, frequency offset = 20 MHz FRF1 = 380 MHz, FRF2 = 382.5 MHz, maximum gain setpoint Maximum gain setpoint Gain setpoint = 0.1 Over any 60 MHz bandwidth At maximum gain setpoint At maximum gain setpoint INPI, INMI, INMQ, INMP (Pins 20, 21, 22, 23) RFOP, RFOM (Pins 9, 10) measured through balun Min Typ −147.5 −146 24.2 Max Unit dBm/Hz dBm/Hz dBm 11.3 8.3 0.25 0.5 ±0.5 200||1 8.5 dBm dBm dB dB Degrees Ohms||pF dB Maximum gain setpoint Over gain setpoint of 0.2 to 1.0 Maximum gain setpoint, no RF input RF PIN = −5 dBm, frequency offset = 20 MHz FRF1 = 900 MHz, FRF2 = 902.5 MHz, maximum gain setpoint Maximum gain setpoint Gain setpoint = 0.1 Over any 60 MHz bandwidth At maximum gain setpoint At maximum gain setpoint INPI, INMI, INMQ, INMP (Pins 20, 21, 22, 23) RFOP, RFOM (Pins 9, 10) measured through balun 4.5 0.4 −149.5 −148 23.3 dB dB dBm/Hz dBm/Hz dBm 11.5 8.5 0.25 0.6 ±1 180||0.6 6.8 dBm dBm dB dB Degrees Ohms||pF dB Maximum gain setpoint Over gain setpoint of 0.2 to 1.0 Maximum gain setpoint, no RF input RF PIN = −5 dBm, frequency offset = 20 MHz FRF1 = 2400 MHz, FRF2 = 2402.5 MHz, maximum gain setpoint Maximum gain setpoint Gain setpoint = 0.1 Over any 60 MHz bandwidth At maximum gain setpoint At maximum gain setpoint INPI, INMI, INMQ, INMP (Pins 20, 21, 22, 23) RFOP, RFOM (Pins 9, 10) measured through balun VPRF, VPS2 (Pin 1, 18, 6); RFOP, RFOM (Pins 9, 10) 7.0 0.5 −147 −144 18.7 dB dB dBm/Hz dBm/Hz dBm 9.6 4.3 0.25 0.8 ±2.5 140||0.5 13.5 dBm dBm dB dB Degrees Ohms||pF dB 4.75 Includes load current DSOP (Pin 13) DSOP = 5 V Delay following high-to-low transition until device meets full specifications Delay following low-to-high transition until device produces full attenuation Rev. 0 | Page 4 of 24 5 135 5.25 V mA 2.5 40 15 V dB ns 10 ns ADL5390 ABSOLUTE MAXIMUM RATINGS Table 2. Parameters Supply Voltage VPRF, VPS2 DSOP IBBP, IBBM, QBBP, QBBM RFOP, RFOM RF Input Power at Maximum Gain (INPI or INPQ, Single-Ended Drive) Equivalent Voltage Internal Power Dissipation θJA (With Pad Soldered to Board) Maximum Junction Temperature Operating Temperature Range Storage Temperature Range Rating 5.5 V 5.5 V 2.5 V 5.5 V 10 dBm for 50 Ω Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2.0 V p-p 825 mW 59°C/W 125°C −40°C to +85°C −65°C to +150°C ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. 0 | Page 5 of 24 ADL5390 CMRF INPQ INMQ INMI INPI CMRF PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 24 23 22 21 20 19 VPRF 1 18 VPRF QFLP 2 16 IFLM TOP VIEW (Not to Scale) QBBP 4 15 IBBP QBBM 5 14 IBBM VPS2 6 8 9 10 11 12 RFOP RFOM CMOP CMOP CMOP 7 CMOP 13 DSOP 04954-002 QFLM 17 IFLP ADL5390 3 Figure 2. LFCSP Pin Configuration Table 3. Pin Function Descriptions Pin No. 2, 3 Mnemonic QFLP, QFLM 4, 5 6, 1, 18 7, 8, 11, 12, 19, 24 9, 10 13 14, 15 16, 17 QBBP, QBBM VPS2, VPRF CMOP, CMRF RFOP, RFOM DSOP IBBM, IBBP IFLM, IFLP 20, 21 INPI, INMI 22, 23 INMQ, INPQ Exposed Paddle GND Description Q Baseband Input Filter Pins. Connect optional capacitor to reduce Q baseband gain control channel lowpass corner frequency. Q Channel Differential Baseband Gain Control Inputs. Typical common-mode bias level of 0.5 V. Positive Supply Voltage. VP of 4.75 V to 5.25 V. Device Common. Connect via lowest possible impedance to external circuit common. Differential RF Outputs. Must be ac-coupled. Differential impedance 50 Ω nominal. Output Disable. Pull high to disable output stage. Connect to common for normal operation. I Channel Differential Baseband Gain Control Inputs. Typical common-mode bias level of 0.5 V. I Baseband Input Filter Pins. Connect optional capacitor to reduce I baseband gain control channel lowpass corner frequency. I Channel Differential RF Inputs. Must be ac-coupled. 250 Ω impedance to common on each pin. These inputs can be driven single-ended without any performance degradation. Q Channel Differential RF Inputs. Must be ac-coupled. 250 Ω impedance to common on each pin. These inputs can be driven single-ended without any performance degradation. The exposed paddle on the underside of the package should be soldered to a low thermal and electrical impedance ground plane. Rev. 0 | Page 6 of 24 ADL5390 TYPICAL PERFORMANCE CHARACTERISTICS 10 5 4 CHANNEL GAIN MATCH (dB) 5 0 FRF = 70MHz FRF = 140MHz FRF = 380MHz FRF = 900MHz FRF = 2400MHz GAIN (dB) –5 –10 –15 –20 3 2 +3σ 1 0 –1 –3σ –2 04954-003 –30 0 0.25 0.50 GAIN SETPOINT 0.75 04954-006 –3 –25 –4 –5 1.00 0 300 600 900 1200 1500 FREQUENCY (MHz) 1800 2100 2400 Figure 6. Channel Gain Matching (I to Q) vs. RF Frequency, Gain Setpoint = 1.0 Figure 3. Gain Magnitude vs. Gain Setpoint, RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz (Channel I or Channel Q) 9 10 TEMP = –40°C TEMP = +25°C TEMP = +85°C 5 TEMP = –40°C 8 TEMP = +25°C 7 0 GAIN (dB) –10 –15 4 TEMP = +85°C –25 1 04954-004 2 0 0.1 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT 0.7 0.8 0.9 0 1.0 Figure 4. Gain Magnitude vs. Gain Setpoint, Temp = +85°C, +25°C, −40°C, RF Frequency = 380 MHz (Channel I or Channel Q) 04954-007 3 –20 –30 0 5 +3σ = DASH LINE –3σ = SOLID LINE FRF = 70MHz FRF = 140MHz FRF = 380MHz FRF = 900MHz FRF = 2400MHz 2 1 600 900 1200 1500 FREQUENCY (MHz) 0 –1 –2 04954-005 –4 0 0.25 0.50 GAIN SETPOINT 0.75 2100 2400 +3σ = DASH LINE –3σ = SOLID LINE –5 –10 FRF = 70MHz FRF = 140MHz FRF = 380MHz FRF = 900MHz FRF = 2400MHz –15 –3 1800 0 PHASE ERROR (Degrees) 3 300 Figure 7. Channel Gain vs. RF Frequency, Temp = +85°C, +25°C, −40°C, Gain Setpoint = 1.0 4 GAIN ERROR (dB) 5 –20 1.0 Figure 5. Gain Conformance Error vs. Gain Setpoint, RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz 0 0.25 0.50 GAIN SETPOINT 0.75 04954-008 GAIN (dB) 6 –5 1.0 Figure 8. Single-Channel Phase Deviation vs. Gain Setpoint, Normalized to Gain Setpoint = 1.0, RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz Rev. 0 | Page 7 of 24 ADL5390 –142 25 +3σ = DASH LINE –3σ = SOLID LINE 15 –144 –145 NOISE (dBm/Hz) 10 –143 5 0 –5 0.2 0.4 0.6 GAIN SETPOINT 0.8 –152 1.0 04954-012 04954-009 0 NO CARRIER PIN = –15dBm –151 Figure 9. Channel-to-Channel Phase Matching vs. Gain Setpoint, RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz 0 0.1 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT 0.7 0.8 0.9 1.0 Figure 12. Output Noise Floor vs. Gain Setpoint, No Carrier, with Carrier (20 MHz Offset), RF PIN = −5, −10, −15, No Carrier, RF Frequency = 380 MHz 10 –142 +3σ = DASH LINE –3σ = SOLID LINE TEMP = –40°C TEMP = +25°C TEMP = +85°C 8 6 –143 –144 4 0 –2 –146 –147 –148 –4 –149 –6 –150 –8 –10 0 600 1200 FREQUENCY (MHz) 1800 –151 –152 2400 Figure 10. Channel-to-Channel Phase Matching vs. RF Frequency, Temp = +85°C, +25°C, −40°C, Gain Setpoint = 1.0 0 400 800 1200 1600 FREQUENCY (MHz) 2000 2400 Figure 13. Output Noise Floor vs. RF Frequency, Gain Setpoint = 1.0, No RF Carrier 10 –142 FRF = 70MHz FRF = 140MHz FRF = 380MHz FRF = 900MHz FRF = 2400MHz –143 –144 –145 GAIN SETPOINT = 1.0 5 GAIN SETPOINT = 0.5 0 GAIN (dB) –146 –147 –148 –5 –10 –149 GAIN SETPOINT = 0.1 –150 04954-011 –15 –151 –152 GAIN SETPOINT = 1.0 04954-013 NOISE (dBm/Hz) –145 2 04954-010 PHASE DIFFERENCE (Degrees) –148 –150 –15 NOISE (dBm/Hz) PIN = –10dBm –147 –149 –10 –20 PIN = –5dBm –146 0 0.1 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT 0.7 0.8 0.9 –20 1.0 04954-014 PHASE DIFFERRENCE (Degrees) 20 FRF = 70MHz FRF = 140MHz FRF = 380MHz FRF = 900MHz FRF = 2400MHz 0 400 800 1200 1600 FREQUENCY (MHz) 2000 2400 Figure 14. Gain vs. RF Frequency, Gain Setpoint = 1.0, 0.5, 0.1 Figure 11. Output Noise Floor vs. Gain Setpoint, No RF Carrier, RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz Rev. 0 | Page 8 of 24 ADL5390 0 FUNDAMENTAL –10 –5 1V p-p BASEBAND INPUT SIDEBAND POWER (dBm) –20 –40 –50 2ND HARMONIC –60 –70 –80 –15 –20 500mV p-p BASEBAND INPUT –25 3RD HARMONIC –90 –100 –10 0 100 200 300 400 500 600 700 800 DIFF. BASEBAND INPUT LEVEL (mV p-p) 900 –35 1000 Figure 15. Baseband Harmonic Distortion, (Channel I and Channel Q), RF PIN = −5 dBm, (Balun and Cable Losses Not Included) 12 250mV p-p BASEBAND INPUT –30 0 50 100 150 200 250 BB FREQUENCY (MHz) 04954-018 –30 04954-015 RF OUTPUT SIDEBAND POWER (dBm) 0 300 350 400 Figure 18. IQ Modulation Bandwidth vs. Baseband Magnitude 15 TEMP = –40°C TEMP = +25°C 10 11 5 OP1dB (dBm) OP1dB (dBm) 10 TEMP = +85°C 9 FRF = 70MHz FRF = 140MHz FRF = 380MHz FRF = 900MHz FRF = 2400MHz 0 –5 –10 8 –15 7 0 400 800 1200 1600 FREQUENCY (MHz) 2000 04954-019 04954-016 6 –20 –25 0 2400 0.1 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT 0.7 0.8 0.9 1.0 Figure 19. Output 1 dB Compression vs. Gain Setpoint, RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz Figure 16. Output 1 dB Compression Point vs. RF Frequency, Temp = +85°C, +25°C, −40°C, Gain Setpoint = 1.0 30 30 28 25 TEMP = –40°C 26 20 24 15 OIP3 (dBm) 20 TEMP = +85°C 18 5 0 16 –5 04954-017 14 12 10 FRF = 70MHz FRF = 140MHz FRF = 380MHz FRF = 900MHz FRF = 2400MHz 10 0 400 800 1200 1600 FREQUENCY (MHz) 2000 –10 –15 2400 Figure 17. Output IP3 vs. RF Frequency, Temp = +85°C, +25°C, −40°C, Gain Setpoint = 1.0 04954-020 OIP3 (dBm) TEMP = +25°C 22 0 0.1 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT 0.7 0.8 0.9 1.0 Figure 20. Output IP3 vs. Gain Setpoint, RF Frequency = 70 MHz, 140 MHz, 380 MHz, 900 MHz, 2400 MHz Rev. 0 | Page 9 of 24 ADL5390 1.25 300 0 1.00 SHUNT CAPACITANCE (pF) 200 0.75 SHUNT RESISTANCE (Ω) 0.50 150 0.25 100 –10 RF OUTPUT POWER (dBm) 250 INPUT SHUNT CAPACITANCE (pF) INPUT SHUNT RESISTANCE (Ω) –5 –15 –20 –25 –30 –35 –40 –45 –50 –55 –60 04954-024 –65 220 420 620 820 1020 1220 1420 1620 1820 2020 2220 FRF (MHz) 04954-021 –70 50 20 0 –75 0.5 1.0 1.5 2.0 2.5 3.0 3.5 DSOP VOLTAGE (V) 4.0 4.5 5.0 Figure 24. Power Shutdown Attenuation, RF = 380 MHz Figure 21. S11 of RF Input (Shunt R/C Representation) TEK RUN 1 ADL5390 SDD22 90 ENVELOPE 12 AUG 04 16:48:01 60 120 150 → |GRIDZ| 0 30 2.7GHz 0 S 11TERMANGI 3GHz 180 0 10MHz 210 04954-025 1 330 CH1 500mV Ω CH3 2.0V Ω DS 10MHz 240 300 04954-022 IMPEDANCE CIRCLE SDD22 NOM WFR DUT 1 270 ARG(GRIDZ), RADS(S 11TERMANG) S22 NOM WFR I Figure 22. S22 of RF Output (Differential and Single-Ended through Balun) 139 Vp = 5.25 137 Vp = 5 136 135 134 Vp = 4.75 133 04954-023 SUPPLY CURRENT (mA) 138 132 –40 –25 M 10.0ns 5.0GS/s ET 200ps/pt A CH3 760mV –10 5 20 35 TEMPERATURE (°C) 50 65 80 Figure 23. Supply Current vs. Temperature Rev. 0 | Page 10 of 24 Figure 25. Power Shutdown Response Time, RF = 380 MHz ADL5390 GENERAL STRUCTURE I CHANNEL BASEBAND INPUT VIBB THEORY OF OPERATION VIRF, I CHANNEL SINGLE-ENDED OR DIFFERENTIAL V-I LINEAR ATTENUATOR SINGLE-ENDED OR DIFFERENTIAL 50Ω OUTPUT I-V VQRF, Q CHANNEL SINGLE-ENDED OR DIFFERENTIAL V-I LINEAR ATTENUATOR OUTPUT DISABLE VQBB Q CHANNEL BASEBAND INPUT Since the two independent RF/IF inputs can be combined in arbitrary proportions, the overall function can be termed “vector multiplication” as expressed by 04954-026 The simplified block diagram given in Figure 26 shows a matched pair of variable gain channels whose outputs are summed and presented to the final output. The RF/IF signals propagate from the left to the right, while the baseband gain controls are placed above and below. The proprietary linearresponding variable attenuators offer excellent linearity, low noise, and greater immunity from mismatches than other commonly used methods. Figure 26. Simplified Architecture of the ADL5390 NOISE AND DISTORTION where: VIRF and VQRF are the RF/IF input vectors. VIBB and VQBB are the baseband input scalars. VO is the built-in normalization factor, which is designed to be 0.285 V (1/3.5 V). The overall voltage gain, in linear terms, of the I and Q channels is proportional to its control voltage and scaled by the normalization factor, i.e., a full-scale gain of 1.75 (5 dB) for VI (Q)BB of 500 mV. A full-scale voltage gain of 1.75 defines a gain setpoint of 1.0. Due to its versatile functional form and wide signal dynamic range, the ADL5390 can form the core of a variety of useful functions such as quadrature modulators, gain and phase adjusters, and multiplexers. At maximum gain on one channel, the output 1 dB compression point and noise floor referenced to 50 Ω are 11 dBm and −148 dBm/Hz, respectively. The broad frequency response of the RF/IF and gain control ports allows the ADL5390 to be used in a variety of applications at different frequencies. The bandwidth for the RF/IF signal path extends from approximately 20 MHz to beyond 2.4 GHz, while the gain controls signals allow for modulation rates greater than 200 MHz. The signal path for a particular channel of the ADL5390 consists basically of a preamplifier followed by a variable attenuator and then an output driver. Each subblock contributes some level of noise and distortion to the desired signal. As the channel gain is varied, these relative contributions change. The overall effect is a dependence of output noise floor and output distortion levels on the gain setpoint. For the ADL5390, the distortion is always determined by the preamplifier. At the highest gain setpoint, the signal capacity, as described by the 1 dB compression point (P1dB) and the thirdorder intercept (OIP3), are at the highest levels. As the gain is reduced, the P1dB and OIP3 are reduced in exact proportion. At the higher gain setpoints, the output noise is dominated by the preamplifier as well. At lower gains, the contribution from the preamplifier is correspondingly reduced and eventually a noise floor, set by the output driver, is reached. As Figure 27 illustrates, the overall dynamic range defined as a ratio of OIP3 to output noise floor remains constant for the higher gain setpoints. At some gain level, the noise floor levels off and the dynamic range degrades commensurate with the gain reduction. Matching between the two gain channels is ensured by careful layout and design. Since they are monolithic and arranged symmetrically on the die, thermal and process gradients are minimized. Typical gain and phase mismatch at maximum gain are <0.5 dB and <0.5°. 175 DYNAMIC RANGE = OIP3 – (OUTPUT NOISE FLOOR (NO CARRIER)) 170 DYNAMIC RANGE (dB × Hz) VOUT = VIRF × (VIBB/VO) + VQRF × (VQBB/VO) 165 160 155 150 140 04954-027 145 0 0.1 0.2 0.3 0.4 0.5 0.6 GAIN SETPOINT 0.7 0.8 0.9 Figure 27. Dynamic Range Variation with Gain Setpoint Rev. 0 | Page 11 of 24 1.0 ADL5390 APPLICATIONS level of the ADL5390 inputs is not affected, as shown in Figure 29. Capacitive reactance at the RF inputs can be compensated for with series inductance. In fact, the customer evaluation board has high impedance line traces between the shunt termination pads and the device input pins, which provides series inductance and improves the return loss at 1.9 GHz to better than −15 dB with the shunt termination removed, as shown in Figure 28. USING THE ADL5390 The ADL5390 is designed to operate in a 50 Ω impedance system. Figure 29 illustrates an example where the RF/IF inputs are driven in a single-ended fashion, while the differential RF output is converted to a single-ended output with a RF balun. The baseband gain controls for the I and Q channels are typically driven from differential DAC outputs. The power supplies, VPRF and VPS2, should be bypassed appropriately with 0.1 µF and 100 pF capacitors. Low inductance grounding of the CMOP and CMRF common pins is essential to prevent unintentional peaking of the gain. The exposed paddle on the underside of the package should be soldered to a low thermal and electrical impedance ground plane. 0 S11 MATCH WITHOUT 66.5Ω TERMINATION –5 –10 –15 dB RF INPUT AND MATCHING –20 The RF/IF inputs present 250 Ω resistive terminations to ground. In general, the input signals should be ac-coupled through dc-blocking capacitors. The inputs may be driven differentially or single-ended, in which case the unused inputs are connected to common via the dc-blocking capacitors. The ADL5390’s performance is not degraded by driving these inputs single-ended. The input impedance can be reduced by placing external shunt termination resistors to common on the source side of the dc-blocking capacitors so that the quiescent dc-bias S11 MATCH WITH TERMINATION –25 20.0 115.2 210.4 305.6 400.8 496.0 591.2 686.4 781.6 876.8 972.0 1067.2 1162.4 1257.6 1352.8 1448.0 1543.2 1638.4 1733.6 1828.8 1924.0 2019.2 2114.4 2209.6 2304.8 2400.0 –35 04954-028 –30 FREQUENCY (MHz) Figure 28. ADL5390 Customer Evaluation Board RF Input Return Loss. IBBP IBBM VP C7 0.1µF C8 100pF C12 (SEE TEXT) SW1 B VP RFIN_I C1 10nF C2 10nF C6 10nF L2 0Ω RFIN_Q IBBM IBBP INPI INMI C18 10nF RFOM 1 5 ADL5390 IPMQ RFOP L4 120nH CMOP QBBM QBBP VPRF QFLM CMRF QFLP C5 10nF DSOP CMOP CMOP INPQ R22 66.5Ω A C17 L3 10nF 120nH 4 3 T1 ETC1-1-13 (M/A-COM) RFOP CMOP C14 0.1µF VPS2 VP VP C4 0.1µF C3 100pF C11 (SEE TEXT) C10 100pF C9 0.1µF QBBP QBBM Figure 29. Basic Connections Rev. 0 | Page 12 of 24 04954-029 R2 66.5Ω IFLM VPRF CMRF L1 0Ω IFLP R8 10kΩ ADL5390 RF OUTPUT AND MATCHING 10 The RF/IF outputs of the ADL5390, RFOP and RFOM, are open collectors of a transimpedance amplifier that need to be pulled up to the positive supply, preferably with RF chokes, as shown in Figure 30. The nominal output impedance looking into each individual output pin is 25 Ω. Consequently, the differential output impedance is 50 Ω. RL2 = OPEN 8 6 GAIN (dB) RL2 = 50Ω 4 2 RL2 = SHORT 0 VP –2 0.1µF RT RFOM ±ISIG GM RL = 50Ω –10 10 10pF 1:1 10pF RF OUTPUT 04954-030 50Ω DIFFERENTIAL 100 1000 FREQUENCY (MHz) 10000 Figure 31. Gain of the ADL5390 Using a Single-Ended Output with Different Dummy Loads, RL2 on the Unused Output, Gain Setpoint = 1.0 RFOP RT 04954-043 –4 120nH Figure 30. RF Output Interface to the ADL5390 Showing Coupling Capacitors, Pull-Up RF Chokes, and Balun Since the output dc levels are at the positive supply, ac-coupling capacitors are usually needed between the ADL5390 outputs and the next stage in the system. A 1:1 RF broadband output balun, such as the ETC1-1-13 (M/ACOM), converts the differential output of the ADL5390 into a single-ended signal. Note that the loss and balance of the balun directly impact the apparent output power, noise floor, and gain/ phase errors of the ADL5390. In critical applications, narrow-band baluns with low loss and superior balance are recommended. If the output is taken in a single-ended fashion directly into a 50 Ω load through a coupling capacitor, there will be an impedance mismatch. This can be resolved with a 1:2 balun to convert the single-ended 25 Ω output impedance to 50 Ω. If loss of signal swing is not critical, a 25 Ω back termination in series with the output pin can also be used. The unused output pin must still be pulled up to the positive supply. The user may load it through a coupling capacitor with a dummy load to preserve balance. The mismatched gain of the ADL5390 when the output is singleended varies slightly with dummy load value, as shown in Figure 31. The RF output signal can be disabled by raising the DSOP pin to the positive supply. The output disable function provides >40 dB attenuation of the input signal, even at full gain. The interface to DSOP is high impedance and the output disable and output enable response times are <100 ns. If the output disable function is not needed, the DSOP should be tied to ground. DRIVING THE I-Q BASEBAND GAIN CONTROLS The I and Q gain control inputs to the ADL5390 set the gain for each channel. These inputs are differential and should normally have a common-mode level of 0.5 V. However, when differentially driven, the common mode can vary from 250 mV to 750 mV while still allowing full gain control. Each input pair has a nominal input swing of ±0.5 V differential around the common-mode level. The maximum gain is achieved if the differential voltage is equal to +500 mV or −500 mV. So with a common-mode level of 500 mV, IBBP and IBBM will each swing between 250 mV and 750 mV. The I and Q gain control inputs can also be driven with a singleended signal. In this case, one side of each input should be tied to a low noise 0.5 V voltage source (a 0.1 µF decoupling capacitor located close to the pin is recommended), while the other input swings from 0 V to 1 V. Low speed, single-ended drive can easily be achieved using 12-bit voltage output DACs such as AD8303 (serial SPI® interface) or AD8582 (parallel interface) DACs. A reference voltage should also be supplied. Differential drive generally offers superior even-order distortion and lower noise than single-ended drive. The bandwidth of the baseband controls exceeds 200 MHz even at full-scale baseband drive. This allows for very fast gain modulation of the RF input signal. In cases where lower modulation bandwidths are acceptable or desired, external filter capacitors can be connected across Pins IFLP to IFLM and Pins QFLP to QFLM to reduce the ingress of baseband noise and spurious signal into the control path. Rev. 0 | Page 13 of 24 ADL5390 The 3 dB bandwidth is set by choosing CFLT according to the following equation: f 3 dB ≈ AD9777 ADL5390 IBBP IOUTA1 45 kHz × 10 nF R1 C external + 0.5 pF R2 OPTIONAL LOW-PASS FILTER R3 IOUTB1 IBBM This equation has been verified for values of CFLT from 10 pF to 0.1 µF (bandwidth settings of approximately 4.5 kHz to 43 MHz). IOUTA2 INTERFACING TO HIGH SPEED DACs The AD977x family of dual DACs is well suited to driving the I and Q gain controls of the ADL5390 with fast modulating signals. While these inputs can in general be driven by any DAC, the differential outputs and bias level of the ADI TxDAC® family allows for a direct connection between DAC and modulator. Bias Level = Average Output Current × R1 For example, if the full-scale current from each output is 20 mA, each output will have an average current of 10 mA. Therefore, to set the bias level to the recommended 0.5 V, R1 and R2 should be set to 50 Ω each. R1 and R2 should always be equal. If R3 is omitted, this will result in an available swing from the DAC of 2 V p-p differential, which is twice the maximum voltage range required by the ADL5390. DAC resolution can be maximized by adding R3, which scales down this voltage according to the following equation: ⎡ R2 ⎤ 2 × I MAX (R1 || (R2 + R3)) × ⎢1 − ⎥ ⎢⎣ R2 + R3 ⎥⎦ OPTIONAL LOW-PASS FILTER R3 IOUTB2 04954-032 QBBM Figure 32. Basic AD9777-to-ADL5390 Interface 1.15 1.13 1.10 1.08 1.05 1.02 1.00 0.97 0.95 0.92 0.90 0.88 0.85 0.82 0.80 0.77 0.75 0.72 0.70 50 55 60 65 70 75 80 85 90 95 100 105 110 115 120 125 130 R3 (Ω) 04954-033 The basic interface between the AD9777 DAC outputs and the ADL5390 I and Q gain control inputs is shown in Figure 32. Resistors R1 and R2 (R1 = R2) set the dc bias level according to the following equation: R2 DIFFERENTIAL PEAK-PEAK SWING (R3) (V p-p) The AD977x family of dual DACs has differential current outputs. The full-scale current is user programmable and is usually set to 20 mA, that is each output swings from 0 mA to 20 mA. Full Scale Swing = QBBP R1 Figure 33. Peak-Peak DAC Output Swing vs. Swing Scaling Resistor R3 (R1 = R2 = 50 Ω) Figure 33 shows the relationship between the value of R3 and the peak baseband voltage with R1 and R2 equal to 50 Ω. As shown in Figure 33, a value of 100 Ω for R3 will provide a peak-peak swing of 1 V p-p differential into the ADL5390’s I and Q inputs. When using a DAC, low-pass image reject filters are typically used to eliminate the Nyquist images produced by the DAC. They also provide the added benefit of eliminating broadband noise that might feed into the modulator from the DAC. Rev. 0 | Page 14 of 24 ADL5390 GENERALIZED MODULATOR The ADL5390 can be configured as a traditional IQ quadrature modulator or as a linear vector modulator by applying signals that are in quadrature to the RF/IF input channels. Since the quadrature generation is performed externally, its accuracy and bandwidth are determined by the user. The user-defined bandwidth is attractive for multioctave or lower IF applications where on-chip, high accuracy quadrature generation is traditionally difficult or impractical. The gain control pins (IBBP/M and QBBP/M) become the in-phase (I) and quadrature (Q) baseband inputs for the quadrature modulator and the gain/phase control for the vector modulator. The wide modulation bandwidths of the gain control interface allow for high fidelity baseband signals to be generated for the quadrature modulator and for high speed gain and phase adjustments to be generated for the vector modulator. RF/IF signals can be introduce to the ADL5390 in quadrature by using a two-way 90o power splitter such as the Mini-Circuits QCN-12. Each output of an ideal 90o power splitter is 3 dB smaller than the input and has a 90o phase difference from the other output. In reality, the 90o power splitter will have its own insertion loss, which can be different for each output, causing a magnitude imbalance. Furthermore, quadrature output will not be maintained over a large frequency range, introducing a phase imbalance. The type of 90o power splitter that should be used for a particular application will be determined by the frequency, bandwidth, and accuracy needed. In some applications minor magnitude and phase imbalances can be adjusted for in the I/Q gain control inputs. VECTOR MODULATOR inputs VIBB and VQBB. The resultant of their vector sum represents the vector gain, which can also be expressed as a magnitude and phase. By applying different combinations of baseband inputs, any vector gain within the unit circle can be programmed. The magnitude and phase (with respect to 90o) accuracy of the 90o power splitter will directly affect this representation and could be seen as an offset and skew of the circle. A change in sign of VIBB or VQBB can be viewed as a change in sign of the gain or as a 180° phase change. The outermost circle represents the maximum gain magnitude. The circle origin implies, in theory, a gain of 0. In practice, circuit mismatches and unavoidable signal feedthrough limit the minimum gain to approximately −30 dB. The phase angle between the resultant gain vector and the positive x-axis is defined as the phase shift. Note that there is a nominal, systematic insertion phase through the ADL5390 to which the phase shift is added. In the following discussions, the systematic insertion phase is normalized to 0°. The correspondence between the desired gain and phase and the Cartesian inputs VIBB and VQBB is given by simple trigonometric identities Gain = [(V IBB ( / VO )2 + VQBB / VO )] 2 Phase = arctan(VQBB / VIBB ) where: VO is the baseband scaling constant (285 mV). VIBB and VQBB are the differential I and Q baseband voltages centered around 500 mV, respectively (VIBB = VIBBP − VIBBM; VQBB = VQBBP − VQBBM). Vq MAX GAIN = 5dB Note that when evaluating the arctangent function, the proper phase quadrant must be selected. For example, if the principal value of the arctangent (known as arctangent(x)) is used, quadrants 2 and 3 would be interpreted mistakenly as quadrants 4 and 1, respectively. In general, both VIBB and VQBB are needed in concert to modulate the gain and the phase. +0.5 A |A| +0.5 MIN GAIN < –30dB –0.5 Vi 04954-034 θ –0.5 Figure 34. Vector Gain Representation The ADL5390 can be used as a vector modulator by driving the RF I and Q inputs single-ended through a 90o power splitter. By controlling the relative amounts of I and Q components that are summed, continuous magnitude and phase control of the gain is possible. Consider the vector gain representation of the ADL5390 expressed in polar form in Figure 34. The attenuation factors for the RF I and Q signal components are represented on the x-axis and y-axis, respectively, by the baseband gain control Pure amplitude modulation is represented by radial movement of the gain vector tip at a fixed angle, while pure phase modulation is represented by rotation of the tip around the circle at a fixed radius. Unlike traditional I-Q modulators, the ADL5390 is designed to have a linear RF signal path from input to output. Traditional I-Q modulators provide a limited LO carrier path through which any amplitude information is removed. VECTOR MODULATOR EXAMPLE—CDMA2000 The ADL5390 can be used as a vector modulator by driving the RF I and Q inputs (INPI and INPQ) single-ended through a 90o power splitter and controlling the magnitude and phase using the gain control inputs. To demonstrate operation as a vector modulator, an 880 MHz single-carrier CDMA2000 test model signal (forward pilot, sync, paging, and six traffic as per Rev. 0 | Page 15 of 24 ADL5390 ACP is still in compliance with the standard (<−45 dBc @ 750 kHz and <−60 dBc @ 1.98 MHz) even with output powers greater than +3 dBm. At low output power levels, ACP at 1.98 MHz carrier offset degrades as the noise floor of the ADL5390 becomes the dominant contributor to measured ACP. Measured noise at 4 MHz carrier offset begins to increase sharply above 2 dBm output power. This increase is not due to noise, but results from increased carrier-induced distortion. As output power drops below 2 dBm, the noise floor drops towards −90 dBm. 3GPP2 C.S0010-B, Table 6.5.2.1) was applied to the ADL5390. A cavity-tuned filter was used to reduce noise from the signal source being applied to the device. The 4.6 MHz pass band of this filter is apparent in the subsequent spectral plots. Figure 35 shows the output signal spectrum for a programmed gain and phase of 5 dB and 45 o. POUT is equal to 0 dBm and VIBB = VQBB = 0.353 V (centered around 500 mV), i.e., VIBBP − VIBBM = VQBBP − VQBBM = 0.353 V. Adjacent channel power is measured in 30 kHz resolution bandwidth at 750 kHz and 1.98 MHz carrier offset. Noise floor is measured at ±4 MHz carrier offset in a 1 MHz resolution bandwidth. MARKER 1 [T1] –14.38dBm 880.00755511MHz RBW 30kHz VWB 300kHz SWT 2s RF ATT MIXER UNIT 20dB –10dBm dB 1 [T1] –14.38dBm 880.00755511MHz CH PWR 1 [T1] –14.38dBm 880.00755511MHz CH PWR 0.13dBm ACP UP –62.00dB ACP LOW –61.98dB ALT1 UP –87.02dB ALT1 LOW –87.04dB –10 1 –20 –30 1AVG A VOUT vs. VIBB/VQBB RF OUTPUT POWER (dBm) EXT –60 –70 C0 C0 Cl2 Cl2 –80 Cl1 Cl1 –100 04954-035 CU1 CU1 –90 CU2 CU2 CENTER 880MHz 500kHz/ –40 –2 1RM –40 –50 –30 5 –50 –9 ACP: 750kHz OFFSET, 30kHz RBW –60 –16 –70 –23 ACP: 1.98MHz OFFSET, 30kHz RBW –80 –30 –90 –37 SPAN 5MHz NOISE: 4MHz OFFSET, 1MHz RBW Figure 35. Output Spectrum, Single-Carrier CDMA2000 Test Model at −5 dBm, VI = VQ = 0.353 V, ACP Measured at 750 kHz and 1.98 MHz Carrier Offset, Input Signal–Filtered Using a Cavity-Tuned Filter (Pass Band = 4.6 MHz) –30 –40 –40 –50 –50 ACP (dBc) ACP: 750kHz OFFSET, 30kHz RBW –60 –60 –70 –70 ACP: 1.98MHz OFFSET, 30kHz RBW –80 –80 –90 –90 NOISE: 4MHz OFFSET, 1MHz RBW –100 –30 –100 –25 –20 –15 –10 –5 OUTPUT POWER (dBm) 0 0.1 0.2 0.3 0.4 –100 0.5 VI(Q)BB Figure 37. Output Power, Noise, and ACP vs. I and Q Control Voltages, CDMA2000 Test Model, VI = VQ, ACP Measured in 30 kHz RBW at ±750 MHz and ±1.98 MHz Carrier Offset, Noise Measured at ±4 MHz Carrier Offset In contrast to Figure 36, Figure 37 shows that for a fixed input power, ACP remains fairly constant as gain and phase are changed (this is not true for very high RF input powers) until the noise floor of the ADL5390 becomes the dominant contributor to the measured ACP. 04954-044 –30 0 NOISE (dBm @ 4MHz Carrier Offset) Holding the I and Q gain control voltages steady at 0.353 V, input power was swept. Figure 36 shows the resulting output power, noise floor, and adjacent channel power ratio. The noise floor is presented as noise in a 1 MHz bandwidth as defined by the 3GPP2 specification. –44 NOISE (dBm @ 4MHz Carrier Offset) ACP (dBc) REF LVL 5dBm 0.7dB OFFSET 04954-045 0 With a fixed input power of 2.16 dBm, the output power was again swept by changing VIBB and VQBB from 0 V to 500 mV. The resulting output power, ACP, and noise floor are shown in Figure 37. 5 Figure 36. Noise and ACP vs. Output Power, Single-Carrier CDMA2000 Test Model, VI = VQ = 0.353, ACP Measured in 30 kHz RBW at ±750 kHz and ±1.98 MHz Carrier Offset, Noise Measured at ±4 MHz Carrier Offset Rev. 0 | Page 16 of 24 ADL5390 * RBW QUADRATURE MODULATOR REF 7dBm The ADL5390 can be used as a quadrature modulator by driving the RF I and Q inputs (INPI and INPQ) single-ended through a 90o phase splitter to serve as the LO input. I/Q modulation is applied to the baseband I and Q gain control inputs (IBBP/IBBM and QBBP/QBBM). A simplified schematic is shown in Figure 38. 3kHz VWB 10kHz SWT 780ms ATT 35dB DESIRED SIDEBAND 0 –16.20dBm A 900.998397436MHz 1 AP CLRWR –10 UNDESIRED SIDEBAND –20 –30 –40 –50 I DATA 1 –23.27dB –1.996794872MHz THIRD BASEBAND HARMONIC –37.38dB –4.004807692MHz 2 LO FEEDTHROUGH –41.27dB –998.397435897kHz 3 4 –60 IBBP SUM PORT 10nF PORT 1 -80 INPI 66.5Ω 04954-039 LO IN IBBM –70 RFOM 10nF 1 -90 5 CENTER 900MHz QCN-12 90° PHASE SPLITTER 4 ROFP QBBM 66.5Ω 50Ω 3 ETC1-1-13 (M/A-COM) INPQ 700kHz/ SPAN 7MHz 10nF RFOP 10nF PORT 2 QBBP TERM PORT ADL5390 Figure 39. SSB Quadrature Modulator Result Using External 90° Phase Splitter, RF PIN = −15 dBm, VIBB = VQBB = 0.5 V (With Reference to a Common-Mode Voltage of 0.5 V) * RBW REF 7dBm 0 –16.78dBm A 900.998397436MHz 1 AP CLRWR Figure 38. Quadrature Modulator Application 3kHz VWB 10kHz SWT 780ms DESIRED SIDEBAND 04954-038 Q DATA ATT 35dB –10 UNDESIRED SIDEBAND 1 –51.81dB –20 –1.996794872MHz THIRD BASEBAND HARMONIC –38.45dB –30 –4.004807692MHz LO FEEDTHROUGH –40 –41.49dB –998.397435897kHz –50 3 4 –60 2 –70 –80 04954-046 Single sideband performance of a quadrature modulator is determined by the magnitude and phase balance (compared to a 90o offset) at the summation point of the I and Q signals. Because the ADL5390 has matched amplifiers and mixers in the I and Q channel, most of the single sideband performance will be determined by the external 90o phase splitter. Good single sideband performance can be achieved by choosing a well-balanced 90o phase splitter. However, phase and magnitude differences in the 90o phase splitter can be corrected by adjusting the magnitude and phase of the I and Q data. Figure 39 shows the performance of the ADL5390 used in conjunction with MiniCircuits QCN-12 90o power splitter. Figure 40 shows the single sideband improvement as the I and Q data is adjusted in magnitude and phase to achieve better single sideband performance. –90 CENTER 900MHz 700kHz/ SPAN 7MHz Figure 40. SSB Modulator Applications with Gain and Phase Errors Corrected, RF Pin = −15 dBm, VIBB = VQBB = 0.5 V (With Reference to a Common-Mode Voltage of 0.5 V), I/Q Phase Offset by 3o, and Magnitude Offset by 0.5 V For maximum dynamic range, the ADL5390 should be driven as close to the output 1 dB compression point as possible. The output power of the ADL5390 increases linearly with the RF (LO) input power and baseband gain control input voltage until the ADL5390 reaches compression. At the 1 dB compression point, the lower sideband starts to increase. Figure 41 demonstrates the output spectrum of a 3-carrier CDMA2000 signal applied to the I/Q baseband gain control inputs. As the RF (LO) power is increased, the relative amount of noise is reduced until the ADL5390 goes into compression. At this point, the relative noise increases, as shown in Figure 42. Analog Devices has several quadrature/vector modulators that have highly accurate integrated 90o phase splitters—AD8340, AD8341, AD8345, AD8346, AD8349—that cover a variety of frequency bands. Rev. 0 | Page 17 of 24 ADL5390 REF –26.6dBm –30 *ATT 5dB *RBW 10kHz *VBW 300kHz *SWT 4s RF MULTIPLEXER POS –26.623dBm A –40 –50 1 RM AVG * –60 –70 –80 –90 NOR –100 –110 The ADL5390 may also be used as an RF multiplexer. In this application, two RF signals are applied to the INPI and INPQ inputs, and the baseband voltages control which of the two RF signals appears at the output. Figure 43 illustrates this application and shows that with VIBB = 0.5 and VQBB = 0.0 (with reference to a common-mode voltage of 0.5 V). The INPI signal is presented to the output. Then, when VIBB transitions to VIBB = 0.0 and VQBB remains equal to zero, there is no RF output. Lastly, as VQBB transitions to 0.5 V, the INPQ signal appears at the output. With VIBB = 0.0 and VQBB = 0.0, the isolation to the output is typically >40 dB at 380 MHz. –120 TEK STOPPED 1.29MHz/ STANDARD: CDMA IS95C CLASS 0 FWD ADJACENT CHANNEL Tx CHANNELS LOWER UPPER CH1 (REF) CH2 CH3 –22.93dBm –22.83dBm –22.95dBm TOTAL –18.13dBm 200 Acqs 24 AUG 04 11:08:40 SPAN 12.9MHz –59.25dB –59.43dB CH2 ALTERNATE CHANNEL LOWER UPPER –62.79dB –63.11dB VIBB 04954-037 CENTER 880MHz 2ND ALTERNATE CHANNEL LOWER UPPER –60.71dB –60.32dB Figure 41. ADL5390 as a Quadrature Modulator with the Use of an External 90° Phase Splitter, RF/LO Power = −1 dBm and Gain Control Inputs Driven Differentially with 0.353 VP-P, 3-Carrier CDMA2000 I/Q Data –69 2 CH3 VQBB CH1 3 1 RF OUTPUT 04954-047 NOISE (dBc) - 8MHz OFFSET - 1MHz RBW CH1 200mV Ω CH2 500mV Ω DS M 40.0ns 1.25GS/s 800ps/pt CH3 500mV Ω DS A CH2 780mV –71 –72 Figure 43. ADL5390 in RF Multiplexer Application –73 –74 –75 –76 –77 –78 –25 04954-031 NOISE (dBC) (1MHz RBW) –70 –20 –15 –10 OUTPUT POWER (dBm) –5 0 Figure 42. Noise vs. Output Power Rev. 0 | Page 18 of 24 ADL5390 EVALUATION BOARD The evaluation board circuit schematic for the ADL5390 is shown in Figure 44. The evaluation board is configured to be driven from a single-ended 50 Ω source. Although the input of the ADL5390 is differential, it may be driven single-ended with no loss of performance. The low-pass corner frequency of the baseband I and Q channels can be reduced by installing capacitors in the C11 and C12 positions. The low-pass corner frequency for either channel is approximated by f 3 dB ≈ 45 kHz × 10 nF C external + 0.5 pF On this evaluation board, the I and Q baseband circuits are identical to each other, so the following description applies to each. The connections and circuit configuration for the I/Q baseband inputs are described in Table 4. The baseband input of the ADL5390 requires a differential voltage drive. The evaluation board is set up to allow such a drive by connecting the differential voltage source to QBBP and QBBM. The common-mode voltage should be maintained at approximately 0.5 V. For this configuration, Jumpers W1 to W4 should be removed. The baseband input of the evaluation board may also be driven with a single-ended voltage. In this case, a bias level is provided to the unused input from Potentiometer R10 by installing either W1 or W2. Setting SW1 in Position B disables the ADL5390 output amplifier. With SW1 set to Position A, the output amplifier is enabled. With SW1 set to Position A, an external voltage signal, such as a pulse, can be applied to the DSOP SMA connector to exercise the output amplifier enable/disable function. Rev. 0 | Page 19 of 24 ADL5390 Table 4. Evaluation Board Configuration Options Component R7, R9, R11, R14, R15, R19, R20, R21, C15, C19, W3, W4 Function I Channel Baseband Interface. Resistors R7 and R9 may be installed to accommodate a baseband source that requires a specific terminating impedance. Capacitors C15 and C19 are bypass capacitors. For single-ended baseband drive, the Potentiometer R11 can be used to provide a bias level to the unused input (install either W3 or W4). R1, R3, R10, R12, R13, R16, R17, R18, C16, C20, W1, W2 Q Channel Baseband Interface. See the I Channel Baseband Interface section. C11, C12 Baseband Low-Pass Filtering. By adding capacitor C11 between QFLP and QFLM, and capacitor C12 between IFLP and IFLM, the 3 dB low-pass corner frequency of the baseband interface can be reduced from 230 MHz (nominal) as given by the equation in the Evaluation Board section. Output Interface. The 1:1 balun transformer, T1, converts the 50 Ω differential output to 50 Ω single-ended. C17 and C18 are dc blocks. L3 and L4 provide dc bias for the output. I and Q Channel RF Input Interface. The single-ended impedance to the ADL5390 RF inputs is 200 Ω. Shunt terminations R2 and R22 of 66.5 Ω bring the impedances to 50 Ω. C2 and C5 are dc blocks. C1 and C6 are used to ac-couple the unused side of the differential inputs to common. T1, C17, C18, L3, L4 C2, C1, R2 C5, C6, R22 Default Conditions R7, R9 = not installed R11 = potentiometer, 2 kΩ, 10 turn (Bourns) R14 = 4 kΩ (size 0603) R15 = 44 kΩ (size 0603) R19, R20, R21 = 0 Ω (size 0603) C15, C19 = 0.1 µF (Size 0603) W3 = jumper (installed) W4 = jumper (open) R1, R3 = not installed R10 = potentiometer, 2 kΩ, 10 turn (Bourns) R12 = 4 kΩ (size 0603) R13 = 44 kΩ (size 0603) R16, R17, R18 = 0 Ω (size 0603) C16, C20 = 0.1 µF (size 0603) W1 = jumper (installed) W2 = jumper (open) C11, C12 = not installed C17, C18 = 10 nF (size 0603) T1 = ETC1-1-13 (M/A-COM) L3, L4 = 120 nH (size 0603) C2 = C1 = 10 nF (size 0603) R2 = 66.5 Ω 10 (size 0603) C5 = C6 = 10 nF (size 0603) R22 = 66.5 Ω 10 (size 0603) R4, R6, R5, C4, C7 C9, C3, C8, C10 Power Supply Decoupling. R4, R6, R5 = 0 Ω (size 0603) C4, C7 C9 = 0.1uF (size 0603) C3, C8, C10 = 100 pF (size 0603) R8, SW1 Output Disable Interface. The output stage of the ADL5390 is disabled by applying a high voltage to the DSOP pin by moving SW1 to Position B. The output stage is enabled moving SW1 to Position A. The output disable function can also be exercised by applying an external high or low voltage to the DSOP SMA connector with SW1 in Position A. R8 = 10 kΩ (size 0603) SW1 = SPDT (Position A, output enabled) Rev. 0 | Page 20 of 24 ADL5390 IBBP VP TEST POINT IBBM C19 R7 0.1µF (OPEN) R9 (OPEN) R21 0Ω GND TEST POINT R19 0Ω W3 W4 R20 0Ω C15 0.1µF VP R14 4kΩ VP C8 100pF R5 0Ω R15 44kΩ C12 (OPEN) B SW1 C1 10nF C6 10nF IBBM CMOP INMI RFOM RFOP INPQ CMOP CMRF VPRF QBBM C5 10nF IPMQ QBBP RFIN_Q C18 10nF L4 120nH 1 5 C17 L3 10nF 120nH 4 3 T1 ETC1-1-13 (M/A-COM) RFOP CMOP VPS2 R6 0Ω R4 0Ω C14 0.1µF VP VP C4 0.1µF DSOP ADL5390 L2 0Ω R22 66.5Ω A DSOP CMOP INPI QFLM C2 10nF QFLP R2 66.5Ω IBBP L1 0Ω RFIN_I IFLM VPRF CMRF IFLP R8 10kΩ C3 100pF C10 100pF C11 (OPEN) R12 4kΩ R10 2kΩ C9 0.1µF R13 44kΩ VP C16 0.1µF W2 R17 0Ω W1 R16 0Ω R1 (OPEN) R18 0Ω R3 C20 (OPEN) 0.1µF QBBP QBBM Figure 44. Evaluation Board Schematic Rev. 0 | Page 21 of 24 04954-040 C7 0.1µF R11 2kΩ 04954-042 04954-041 ADL5390 Figure 45. Component Side Layout Figure 46. Component Side Silkscreen Rev. 0 | Page 22 of 24 ADL5390 OUTLINE DIMENSIONS 0.60 MAX 4.00 BSC SQ PIN 1 INDICATOR 0.60 MAX TOP VIEW 0.50 BSC 3.75 BSC SQ 0.50 0.40 0.30 1.00 0.85 0.80 12° MAX PIN 1 INDICATOR 19 18 24 1 2.45 2.30 SQ* 2.15 EXPOSED PAD (BOTTOMVIEW) 13 12 7 0.80 MAX 0.65 TYP 6 0.23 MIN 2.50 REF 0.05 MAX 0.02 NOM 0.30 0.23 0.18 SEATING PLANE 0.20 REF COPLANARITY 0.08 *COMPLIANT TO JEDEC STANDARDS MO-220-VGGD-2 EXCEPT FOR EXPOSED PAD DIMENSION Figure 47. 24-Lead Lead Frame Chip Scale Package [LFCSP] 4 × 4 mm Body (CP-24-2) Dimensions shown in millimeters ORDERING GUIDE Models ADL5390ACPZ-WP1, 2 ADL5390ACPZ-REEL71 ADL5390-EVAL 1 2 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 24-Lead Lead Frame Chip Scale Package (LFCSP) 24-Lead Lead Frame Chip Scale Package (LFCSP) Evaluation Board Z = Pb-free part. WP = waffle pack. Rev. 0 | Page 23 of 24 Package Option CP-24-2 CP-24-2 Order Multiple 64 1,500 1 ADL5390 NOTES © 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D04954–0–10/04(0) Rev. 0 | Page 24 of 24