Low Cost DC to 150 MHz
Variable Gain Amplifier
AD8330
Fully differential signal path and also used
with single-sided signals
Inputs from 0.3 mV to 1 V rms, rail-to-rail outputs
Differential RIN = 1 kΩ; ROUT (each output) 75 Ω
Automatic offset compensation (optional)
Linear-in-dB and linear-in-magnitude gain modes
0 dB to 50 dB, for 0 V < VDBS < 1.5 V (30 mV/dB)
Inverted gain mode: 50 dB to 0 dB at −30 mV/dB
×0.03 to ×10 nominal gain for 15 mV < VMAG < 5 V
Constant bandwidth: 150 MHz at all gains
Low noise: 5 nV/√Hz typical at maximum gain
Low distortion: ≤−62 dBc typical
Low power: 20 mA typical at VS of 2.7 V to 6 V
Available in a space-saving, 3 mm × 3 mm LFCSP package
FUNCTIONAL BLOCK DIAGRAM
16
ENBL
Pre-ADC signal conditioning
75 Ω cable driving adjust
AGC amplifiers
GENERAL DESCRIPTION
The AD83301 is a wideband variable gain amplifier for applications
requiring a fully differential signal path, low noise, well-defined
gain, and moderately low distortion, from dc to 150 MHz. The
input pins can also be driven from a single-ended source. The
peak differential input is ±2 V, allowing sine wave operation at
1 V rms with generous headroom. The output pins can drive
single-sided loads essentially rail-to-rail. The differential output
resistance is 150 Ω. The output swing is a linear function of the
voltage applied to the VMAG pin that internally defaults to 0.5 V
providing a peak output of ±2 V. This can be raised to 10 V p-p,
limited by the supply voltage.
The basic gain function is linear-in-dB, controlled by the voltage
applied to Pin VDBS. The gain ranges from 0 dB to 50 dB for
control voltages between 0 V and 1.5 V—a slope of 30 mV dB.
The gain linearity is typically within ±0.1 dB. By changing the
logic level on Pin MODE, the gain decreases over the same range,
with an opposite slope. A second gain control port is provided at
the VMAG pin and allows the user to vary the numeric gain from
a factor of 0.03 to 10. All the parameters of the AD8330 have low
sensitivities to temperature and supply voltages.
1
14
4
OPLO
CMGN
COMM
6
10
OUTPUT CMOP 9
CONTROL
GAIN INTERFACE
VDBS
11
OUTPUT
STAGES
INLO
MODE
VPSO 12
OPHI
INHI
VGA CORE
3
CNTR
CM AND
OFFSET
CONTROL
BIAS AND VREF
2
13
VPOS
1 VPSI
5
APPLICATIONS
15
OFST
VMAG
7
8
03217-001
FEATURES
Figure 1.
Using VMAG, the basic 0 dB to 50 dB range can be repositioned
to any value from 20 dB higher (that is, 20 dB to 70 dB) to at least
30 dB lower (that is, –30 dB to +20 dB) to suit the application,
thereby providing an unprecedented gain range of over 100 dB.
A unique aspect of the AD8330 is that its bandwidth and pulse
response are essentially constant for all gains, over both the basic
50 dB linear-in-dB range, but also when using the linear-inmagnitude function. The exceptional stability of the HF response
over the gain range is of particular value in those VGA applications
where it is essential to maintain accurate gain law-conformance at
high frequencies.
An external capacitor at Pin OFST sets the high-pass corner of
an offset reduction loop, whose frequency can be as low as 5 Hz.
When this pin is grounded, the signal path becomes dc-coupled.
When used to drive an ADC, an external common-mode control
voltage at Pin CNTR can be driven to within 0.5 V of either ground
or VS to accommodate a wide variety of requirements. By default,
the two outputs are positioned at the midpoint of the supply, VS/2.
Other features, such as two levels of power-down (fully off and a
hibernate mode), further extend the practical value of this exceptionally versatile VGA.
The AD8330 is available in 16-lead LFCSP and 16-lead QSOP
packages and is specified for operation from −40°C to +85°C.
Protected by U.S. Patent No. 5,969,657; other patents pending.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD8330
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 14
Applications....................................................................................... 1
Circuit Description .................................................................... 14
General Description ......................................................................... 1
Using the AD8330 ...................................................................... 20
Functional Block Diagram .............................................................. 1
Applications..................................................................................... 25
Revision History ............................................................................... 2
ADC Driving............................................................................... 25
Specifications..................................................................................... 3
Simple AGC Amplifier .............................................................. 25
Absolute Maximum Ratings............................................................ 5
Wide Range True RMS Voltmeter............................................ 26
ESD Caution.................................................................................. 5
Outline Dimensions ....................................................................... 28
Pin Configurations and Function Descriptions ........................... 6
Ordering Guide .......................................................................... 29
Typical Performance Characteristics ............................................. 7
REVISION HISTORY
6/06—Rev. B to Rev. C
10/04—Rev. A to Rev. B
Updated Format..................................................................Universal
Changes to Figure 1.......................................................................... 1
Deleted Figure 2................................................................................ 1
Changes to Specifications Section.................................................. 3
Change to Absolute Maximum Ratings......................................... 5
Changes to Typical Performance Characteristics
Summary Statement ......................................................................... 7
Changes to Figure 14 and Figure 15............................................... 8
Changes to Figure 31 and Figure 32............................................. 11
Updated Outline Dimensions ....................................................... 28
Changes to Absolute Maximum Ratings........................................4
Changes to Ordering Guide .............................................................4
Change to TPC 14 .............................................................................8
Note added to CP-16 Package....................................................... 26
4/03—Rev. 0 to Rev. A
Updated Outline Dimensions....................................................... 26
Rev. C | Page 2 of 32
AD8330
SPECIFICATIONS
VS = 5 V, TA = 25°C, CL = 12 pF on OPHI and OPLO, RL = ∞, VDBS = 0.75 V, VMODE = high, VMAG = O/C (0.5 V), VOFST = 0 V, differential
operation, unless otherwise noted.
Table 1.
Parameter
INPUT INTERFACE
Full-Scale Input
Input Resistance
Input Capacitance
Voltage Noise Spectral Density
Common-Mode Voltage Level
Input Offset
Drift
Permissible CM Range 1
Common-Mode AC Rejection
OUTPUT INTERFACE
Small Signal –3 dB Bandwidth
Peak Slew Rate
Peak-to-Peak Output Swing
Common-Mode Voltage
Voltage Noise Spectral Density
Differential Output Impedance
HD2 2
HD32
OUTPUT OFFSET CONTROL
AC-Coupled Offset
High-Pass Corner Frequency
COMMON-MODE CONTROL
Usable Voltage Range
Input Resistance
DECIBEL GAIN CONTROL
Normal Voltage Range
Elevated Range
Gain Scaling
Gain Linearity Error
Absolute Gain Error
Bias Current
Incremental Resistance
Gain Settling Time to 0.5 dB Error
Mode Up/Down
Mode Up Logic Level
Mode Down Logic Level
LINEAR GAIN INTERFACE
Peak Output Scaling, Gain vs. VMAG
Gain Multiplication Factor vs. VMAG
Usable Input Range
Default Voltage
Incremental Resistance
Bandwidth
Conditions
Pin INHI, Pin INLO
VDBS = 0 V, differential drive
VDBS = 1.5 V
Pin-to-pin
Either pin to COMM
f = 1 MHz, VDBS = 1.5 V; inputs ac-shorted
Min
Typ
±1.4
±4.5
800
±2
±6.3
1k
4
5
3.0
1
2
Pin OFST connected to Pin COMM
VMAG ≥ 2 V (peaks are supply limited)
Pin CNTR O/C
f = 1 MHz, VDBS = 0
Pin-to-pin
VOUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ
VOUT = 1 V p-p, f = 10 MHz, RL = 1 kΩ
Pin OFST
CHPF on Pin OFST (0 V < VDBS < 1.5 V)
CHPF = 3.3 nF, from OFST to CNTR (scales as 1/CHPF)
Pin CNTR
±1.8
±4
2.4
120
−60
−55
150
1500
±2
±4.5
2.5
62
150
−62
−53
MHz
V/μs
V
V
V
nV/√Hz
Ω
dBc
dBc
VDBS stepped from 0.05 V to 1.45 V or 1.45 V to 0.05 V
Pin MODE
Gain increases with VDBS, MODE = O/C
Gain decreases with VDBS
Pin VMAG, Pin CMGN
See Circuit Description section
Gain is nominal when VMAG = 0.5 V
For VMAG ≥ 0.1 V
Rev. C | Page 3 of 32
±2.2
2.6
180
10
100
27
−0.35
−2
mV rms
kHz
4
4.5
V
kΩ
0 to 1.5
0.2 to 1.7
30
±0.1
±0.5
100
100
250
V
V
mV/dB
dB
dB
nA
MΩ
ns
33
+0.35
+2
1.5
3.8
0
0.48
VMAG O/C
1.2 k
VS
0.5
From Pin CNTR to VS/2
VDBS, CMGN, and MODE pins
CMGN connected to COMM
CMGN O/C (VCMGN rises to 0.2 V)
Mode high or low
0.3 V ≤ VDBS ≤ 1.2 V
VDBS = 0
Flows out of Pin VDBS
Unit
V
mV
Ω
pF
nV/√Hz
V
mV rms
μV/°C
V
dB
dB
0
f = 1 MHz, 0.1 V rms
f = 50 MHz
Pin OPHI, Pin OPLO
0 V < VDBS < 1.5 V
VDBS = 0
Max
4.0
×2
0.5
4
150
0.5
V
V
4.2
V/V
5
0.52
V
V
kΩ
MHz
AD8330
Parameter
CHIP ENABLE
Logic Voltage for Full Shutdown
Logic Voltage for Hibernate Mode
Logic Voltage for Full Operation
Current in Full Shutdown
Current in Hibernate Mode
Minimum Time Delay 3
POWER SUPPLY
Supply Voltage
Quiescent Current
Conditions
Pin ENBL
Min
Typ
Max
Unit
Output pins remain at CNTR
1.3
2.3
1.5
0.5
1.7
V
V
V
μA
mA
μs
20
1.5
1.7
100
VPSI, VPOS, VPSO, COMM, and CMOP pins
2.7
VDBS = 0.75 V
20
1
6
27
The use of an input common-mode voltage significantly different than the internally set value is not recommended due to its effect on noise performance.
See Figure 56.
2
See Typical Performance Characteristics for more detailed information on distortion in a variety of operating conditions.
3
For minimum sized coupling capacitors.
Rev. C | Page 4 of 32
V
mA
AD8330
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Supply Voltage
Power Dissipation
RQ Package1
CP Package
Input Voltage at Any Pin
Storage Temperature Range
θJA
RQ-16 Package
CP-16 Package
θJC
RQ-16 Package
Operating Temperature Range
Lead Temperature (Soldering 60 sec)
1
Rating
6V
0.62 W
1.67 W
VS + 200 mV
−65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
105.4°C/W
60°C/W
39°C/W
−40°C to +85°C
300°C
Four-Layer JEDEC Board (252P).
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. C | Page 5 of 32
AD8330
OFST
VPOS
CNTR
16
15
14
13
12 VPSO
1
OFST 1
16
ENBL 2
15
CNTR
14
VPSO
VPSI 3
AD8330
VPOS
2
AD8330
11 OPHI
INLO
3
TOP VIEW
(Not to Scale)
10 OPLO
INLO 5
MODE
4
CMOP
MODE 6
11
VDBS 7
10
VMAG
CMGN 8
9
COMM
7
8
INHI 4
TOP VIEW 13 OPHI
(Not to Scale)
12 OPLO
CMOP
03217-003
6
VMAG
VDBS
5
CMGN
9
COMM
INHI
03217-004
VSPI
ENBL
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 3. 16-Lead QSOP Pin Configuration
Figure 2. 16-Lead LFCSP Pin Configuration
Table 3. 16-Lead LFCSP Pin Function Descriptions
Table 4. 16-Lead QSOP Pin Function Descriptions
Pin
No.
1
2
Mnemonic
VPSI
INHI
3
INLO
4
MODE
Pin
No.
1
2
3
4
5
Mnemonic
OFST
ENBL
VPSI
INHI
INLO
5
VDBS
6
MODE
6
CMGN
7
VDBS
7
COMM
8
CMGN
8
9
VMAG
CMOP
9
COMM
10
OPLO
11
OPHI
10
11
12
VMAG
CMOP
OPLO
12
13
14
15
16
VPSO
CNTR
VPOS
OFST
ENBL
13
14
15
16
OPHI
VPSO
CNTR
VPOS
Description
Positive Supply for Input Stages.
Differential Signal Input, Positive Polarity.
Differential Signal Input, Negative
Polarity.
Logic Input: Selects Gain Slope. High =
gain up vs. VDBS.
Input for Linear-in-dB Gain Control
Voltage, VDBS.
Common Baseline for Gain Control
Interfaces.
Ground for Input and Gain Control Bias
Circuitry.
Input for Gain/Amplitude Control, VMAG.
Ground for Output Stages.
Differential Signal Output, Negative
Polarity.
Differential Signal Output, Positive
Polarity.
Positive Supply for Output Stages.
Common-Mode Output Voltage Control.
Positive Supply for Inner Stages.
Used in Offset Control Modes.
Power Enable, Active High.
Rev. C | Page 6 of 32
Description
Used in Offset Control Modes.
Power Enable, Active High.
Positive Supply for Input Stages.
Differential Signal Input, Positive Polarity.
Differential Signal Input, Negative
Polarity.
Logic Input: Selects Gain Slope. High =
gain up vs. VDBS.
Input for linear-in-dB Gain Control
Voltage, VDBS.
Common Baseline for Gain Control
Interfaces.
Ground for Input and Gain Control Bias
Circuitry.
Input for Gain/Amplitude Control, VMAG.
Ground for Output Stages.
Differential Signal Output, Negative
Polarity.
Differential Signal Output, Positive Polarity.
Positive Supply for Output Stages.
Common-Mode Output Voltage Control.
Positive Supply for Inner Stages.
AD8330
TYPICAL PERFORMANCE CHARACTERISTICS
VS = 5 V, TA = 25°C, CL = 12 pF, VDBS = 0.75 V, VMODE = high (or O/C) VMAG = O/C (0.5 V), RL = ∞, VOFST = 0, differential operation, unless
otherwise noted.
2.0
50
NORMALIZED @ VDBS = 0.75V
45
LO MODE
40
1.5
HI MODE
1.0
GAIN ERROR (dB)
GAIN (dB)
35
30
25
20
15
50MHz
100MHz
0.5
10MHz, 50MHz
0
–0.5
1MHz
1MHz
–1.0
10
5
0.25
0.75
VDBS (V)
0.50
1.00
1.25
1.50
–2.0
0
Figure 4. Gain vs. VDBS
20
9
1.0
0.8
VDBS (V)
1.2
1.4
1.6
2340 UNITS
MODE = LO
15
8
10
7
5
6
% OF UNITS
5
4
0
–30.6 –30.5 –30.4 –30.3 –30.2 –30.1 –30.0 –29.9 –29.8 –29.7 –29.6 –29.5 –29.4 –29.3 –29.2 –29.1 –29.0
20
MODE = HI
15
3
10
2
0
2
1
3
4
5
VMAG (V)
03217-006
0
0
29.1 29.2 29.3 29.4 29.5 29.6 29.7 29.8 29.9 30.0 30.1 30.2 30.3 30.4 30.5 30.6
GAIN SCALING (mV/dB)
Figure 5. Linear Gain Multiplication Factor vs. VMAG
Figure 8. Gain Slope Histogram
1.0
60
0.8
50
0.6
40
VDBS = 1.5V
1.2V
0.9V
30
0.4
0.6V
GAIN (dB)
20
0.2
T = –40°C
0
–0.2
–20
T = +25°C
–40
–1.0
0.4
0.6
0.8
1 .0
1.2
1.4
VDBS (V)
Figure 6. Gain Linearity Error Normalized at 25°C vs. VDBS,
at Three Temperatures, f = 1 MHz
1.6
03217-007
–30
–0.8
0.2
0V
0
–0.6
0
0.3V
10
–10
T = +85°C
–0.4
03217-009
5
1
–50
100k
1M
10M
FREQUENCY (Hz)
100M
500M
03217-010
GAIN MULTIPLICATION FACTOR
0.6
Figure 7. Gain Error vs. VDBS at Various Frequencies
10
GAIN ERROR (dB)
0.4
0.2
03217-008
0
03217-005
0
10MHz
100MHz
–1.5
Figure 9. Frequency Response in 10 dB Steps for Various Values of VDBS
Rev. C | Page 7 of 32
AD8330
50
40
1048 UNITS
ENABLE MODE
1.52V
20
30
0.48V
20
0.15V
10
0.048V
0
0.015V
% OF UNITS
GAIN (dB)
25
VMAG = 4.8V
15
10
–10
–20
5
1.0
03217-014
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0
0.1
–0.1
–0.2
–0.3
DIFFERENTIAL OFFSET (mV)
Figure 13. Differential Input Offset Histogram
Figure 10. Frequency Response for Various Values of VMAG,
VDBS = 0.75 V
10
10
VDBS = 0.1V
0
OUTPUT BALANCE ERROR (dB)
8
GROUP DELAY (ns)
–0.4
0
–0.5
500M
–0.6
100M
–0.7
10M
FREQUENCY (Hz)
–0.8
1M
03217-011
–40
100k
–0.9
–30
6
4
2
–10
–20
–30
–40
–50
–60
–70
10M
FREQUENCY (Hz)
100M
300M
03217-012
1M
–90
100k
Figure 11. Group Delay vs. Frequency
1M
10M
FREQUENCY (Hz)
100M
03217-015
–80
0
100k
Figure 14. Output Balance Error vs. Frequency for a Representative Part
0
200
190
–1
OUTPUT IMPEDANCE (Ω)
OFFSET VOLTAGE (mV)
180
–2
T = –40°C
–3
–4
T = +25°C
–5
170
160
150
140
130
120
–6
0
0.2
0.4
0.6
0.8
1.0
VDBS (V)
1.2
1.4
1.6
100
100k
03217-013
–7
Figure 12. Differential Output Offset vs. VDBS for Three Temperatures,
for a Representative Part
1M
10M
FREQUENCY (Hz)
100M
Figure 15. Output Impedance vs. Frequency
Rev. C | Page 8 of 32
300M
03217-016
110
T = +85°C
AD8330
90
6000
VDBS = 1.5V
VDBS = 1.5V
f = 1MHz
OFST: ENABLED
DISABLED
80
VDBS = 0.75V
70
5000
NOISE (nV/√Hz)
60
CMRR (dB)
50
VDBS = 0V
40
30
20
10
4000
3000
2000
1000
1M
10M
FREQUENCY (Hz)
100M
0
03217-017
–10
50k 100k
1 .0
1.5
2.0
2.5
VMAG (V)
Figure 16. CMRR vs. Frequency
Figure 19. Output Referred Noise vs. VMAG
80
1500
VMAG = 0.5V
f = 1MHz
T = +85°C
f = 1MHz
VMAG = 0.5V
0 .5
0
03217-020
0
70
T = +25°C
1200
60
NOISE (nV/√Hz)
NOISE (nV/√Hz)
T = +85°C
900
T = –40°C
600
50
40
T = +25°C
30
T = –40°C
20
300
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VDBS (V)
0
03217-018
0
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VDBS (V)
Figure 17. Output Referred Noise vs. VDBS for Three Temperatures
03217-021
10
Figure 20. Input Referred Noise vs. VDBS for Three Temperatures
700
180
f = 1MHz
f = 1MHz
160
600
140
NOISE (nV/√Hz)
400
300
200
VMAG = 0.125V
120
100
VMAG = 0.5V
80
60
40
0
20
0
0.5
1.0
1.5
2.0
VMAG (V)
2 .5
0
VMAG = 2V
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
VDBS (V)
Figure 18. Output Referred Noise vs. VMAG,
VDBS = 0.75 V
Figure 21. Input Referred Noise vs. VDBS for Three Values of VMAG
Rev. C | Page 9 of 32
03217-022
100
03217-019
NOISE (nV/√Hz)
500
AD8330
7
0
VDBS = 1.5V
f = 10MHz
–10
6
–20
DISTORTION (dBc)
4
3
2
–30
–40
HD3, RL = 1kΩ
–50
–60
1
HD2, RL = 1kΩ
–70
1M
10M
100M
FREQUENCY (Hz)
–80
03217-023
0
100k
0
0.6
0.9
VOUT (V p-p)
1.5
1.2
Figure 25. Harmonic Distortion vs. VOUT , VMAG = 0.5 V
Figure 22. Input Referred Noise vs. Frequency
0
0
VDBS = 0.75V
VOUT = 1V p-p
–10
RL = 1kΩ
–10
–20
–20
f = 10MHz
DISTORTION (dBc)
DISTORTION (dBc)
0.3
03217-026
NOISE (nV/√Hz)
5
–30
–40
HD3
–50
HD2
HD2 AND HD3, RL = 150Ω1
–30
–40
HD3, RL = 1kΩ
–50
–60
–60
–70
–70
–80
100k
–80
HD2, RL = 1kΩ
100M
10M
FREQUENCY (Hz)
0
0
5
4
0
VDBS = 0.75V
VOUT = 1V p-p
–10
RL = 1kΩ
f = 10MHz
VOUT = 1V p-p
–10 RL = 1kΩ
–20
–40
HD3
–50
–60
HD2
10
20
30
CLOAD (pF)
HD3
–40
–50
HD2
–60
–70
0
–30
40
50
Figure 24. Harmonic Distortion vs. CLOAD
–70
0
0.2
0.4
0.6
0.8
1.0
VDBS (V)
1.2
Figure 27. Harmonic Distortion vs. VDBS
Rev. C | Page 10 of 32
1.4
1.6
03217-028
DISTORTION (dBc)
–20
–30
03217-025
DISTORTION (dBc)
2
3
VOUT (V p-p)
Figure 26. Harmonic Distortion vs. VOUT , VMAG = 2.0 V
Figure 23. Harmonic Distortion vs. Frequency
–80
1
03217-027
1M
03217-024
1OUTPUT AMPLITUDE HARD LIMITED
AD8330
33
30
23
10
25
28
–10
3
20
23
–20
–7
–30
–17
–40
0.4
0.6
0.8
1.0
1.2
1.4
P1dB
10
13
–27
5
8
–37
1.6
0
VDBS (V)
0
0.2
0.4
13
–10
3
–20
–7
–30
–17
2
3
4
5
1.6
3
43
38
f = 10MHz
OIP3 (dBV rms)
0
1
1.4
35
P1dB
23
–27
6
VMAG (V)
30
33
25
28
20
23
f = 50MHz
15
18
10
13
5
8
0
03217-030
OUTPUT V1dB COMPRESSION (dBV rms)
f = 10MHz
0
1.2
40
33
10
–40
0.8
1.0
VDBS (V)
Figure 31. OIP3 vs. VDBS
Figure 28. Input Voltage 1 dBV vs. VDBS
20
0.6
0
0.2
Figure 29. Output Voltage 1 dB vs. VMAG
0.4
0.6
0.8
1.0
1.2
1.4
3
1.6
VMAG (V)
OIP3 (dBm)
0.2
18
03217-033
0
f = 50MHz
15
03217-029
INPUT VOLTAGE (dBV rms)
–50
OIP3 (dBV rms)
13
03217-032
f = 10MHz
0
OIP3 (dBm)
f = 10MHz
Figure 32. OIP3 vs. VMAG
1.5
0
VDBS = 0.75V
–10 VOUT = 1V p-p
1.0
–20
0.5
VOUT (V)
–40
–50
VDBS = 0V
0
–0.5
–60
–70
–1.0
–90
1M
10M
FREQUENCY (Hz)
100M
–1.5
–50
–25
0
25
TIME (ns)
50
75
Figure 33. Full-Scale Transient Response, VDBS = 0 V
Figure 30. IM3 Distortion vs. Frequency
Rev. C | Page 11 of 32
100
03217-034
–80
03217-031
IMD3 (dBc)
–30
AD8330
1.5
1V
1.0
VOUT (V)
0.5
VDBS = 0.75V
0
–0.5
–25
0
25
TIME (ns)
50
75
100
400ns
03217-035
1V
–1.5
–50
03217-038
–1.0
Figure 37. VDBS Interface Response, Top: VDBS, Bottom: VOUT
Figure 34. Full-Scale Transient Response, VDBS = 0.75 V,
f = 1 MHz, VOUT = 2 V p-p
1.5
2V
1.0
VOUT (V)
0.5
VDBS = 1.5V
0
–0.5
–25
0
25
TIME (ns)
50
75
100
400ns
03217-036
1mV
–1.5
–50
Figure 35. Full-Scale Transient Response, VDBS = 1.5 V,
f = 1 MHz, VOUT = 2 V p-p
03217-039
–1.0
Figure 38. VMAG Interface Response, Top: VMAG, Bottom: VOUT
500mV
1V
CL = 12pF
VMAG = 5V
VMAG = 0.5V
CL = 54pF
CL = 24pF
100mV
Figure 36. Transient Response vs. Various Load Capacitances, G = 25 dB
Rev. C | Page 12 of 32
12.5ns
Figure 39. Transient Response vs. VMAG
03217-040
12.5ns
03217-037
VMAG = 0.05V
AD8330
26
OUTPUT
24
INPUT
22
+85°C
20
+25°C
18
–40°C
50mV
03217-041
16
25ns
14
Figure 40. Overdrive Response, VDBS = 1.5 V, VMAG = 0.5 V, 18.5 dB Overdrive
0
0.2
0.4
0.6
0.8
1.0
VDBS (V)
1.2
1.4
1.6
Figure 43. Supply Current vs. VDBS at Three Temperatures
2V
3.125V
2.5V
1.875V
3.125V
1.875V
03217-042
1V
400ns
100ns
Figure 41. ENBL Interface Response. Top: VENBL; Bottom: VOUT, f = 10 MHz
–10
–20
VDBS = 0.75V
–30
PSRR (dB)
–40
VPSI
–50
–60
VPSO
VPOS
–70
–80
–90
–110
1M
10M
FREQUENCY (Hz)
100M
200M
03217-043
–100
Figure 42. PSRR vs. Frequency
Rev. C | Page 13 of 32
Figure 44. CNTR Transient Response, Top: Input to CNTR,
Bottom: VOUT Single-Ended
03217-045
2.5V
03217-044
SUPPLY CURRENT (mA)
4.00V
AD8330
INPUT IS xlD
THEORY OF OPERATION
OUTPUT IS xlN
G = IN/ID
LOOP
AMPLIFIER
(1–x) ID
2
Many monolithic variable gain amplifiers use techniques that
share common principles that are broadly classified as translinear. This term refers to circuit cells whose functions depend
directly on the very predictable properties of bipolar junction
transistors, notably the linear dependence of their transconductance on collector current. Since the discovery of these
cells in 1967, and their commercial exploitation in products
developed during the early 1970s, accurate wide bandwidth
analog multipliers, dividers, and variable gain amplifiers have
invariably employed translinear principles.
In practice, the realization of the full potential of this circuit
involves many other factors, but these three elementary ideas
remain essential.
By varying IN, the overall function is that of a two-quadrant
analog multiplier, exhibiting a linear relationship to both the
signal modulation factor (x) and this numerator current. On the
other hand, by varying ID, a two-quadrant analog divider is
realized, having a hyperbolic gain function with respect to the
input factor, x, controlled by this denominator current. The
AD8330 exploits both modes of operation. However, since a
hyperbolic gain function is generally of less value than one in
which the decibel gain is a linear function of a control input, a
special interface is included to provide either increasing or
decreasing exponential control of ID.
(1–x) IN
2
+
(1+x) IN
2
–
Q1
Q4
Q2
ID
Q3
DENOMINATOR
NUMERATOR
BIAS CURRENT BIAS CURRENT
IN
Figure 45. Basic Core
ENBL
Although these techniques are well understood, the realization
of a high performance variable gain amplifier (VGA) requires
special technologies and attention to many subtle details in
its design. The AD8330 is fabricated on a proprietary siliconon-insulator, complementary bipolar IC process and draws
on decades of experience in developing many leading edge
products using translinear principles to provide an unprecedented
level of versatility.
OFST
VPSI
BIAS AND
VREF
INHI
AD8330
VPOS
CNTR
CM MODE AND
OFFSET CONTROL
VPSO
OPHI
OUTPUT
STAGES
INLO
MODE
VGA CORE
GAIN INTERFACE
VDBS
CMGN
OPLO
OUTPUT
CONTROL CMOP
COMM
VMAG
03217-047
Figure 45 shows a basic representative cell comprising just four
transistors. This, or a very closely related form, is at the heart
of most translinear multipliers, dividers, and VGAs. The key
concepts are as follows: First, the ratio of the currents in the
left-hand and right-hand pairs of transistors is identical, represented by the modulation factor, x, with values between −1
and +1. Second, the input signal is arranged to modulate the
fixed tail current, ID, to cause the variable value of x, introduced
in the left-hand pair, to be replicated in the right-hand pair,
and, thus, generate the output by modulating its nominally
fixed tail current, IN. Third, the current gain of this cell is
exactly G = IN/ID over many decades of variable bias current.
(1–x) ID
2
03217-046
CIRCUIT DESCRIPTION
Figure 46. Block Schematic
Overall Structure
Figure 46 shows a block schematic of the AD8330 locating the
key sections. More detailed descriptions of its structure and
features are provided throughout the Theory of Operation
section; however, Figure 46 provides a general overview of its
capabilities.
The VGA core contains a more elaborate version of the cell
shown in Figure 45. The current, ID, is controlled exponentially
(linear-in-decibels) through the decibel gain interface at
Pin VDBS and its local common, Pin CMGN. The gain span
(that is, the decibel difference between maximum and
minimum values) provided by this control function is slightly
more than 50 dB. The absolute gain from input to output is a
function of source and load impedance, and also depends on
the voltage on a second gain control pin (VMAG), explained in
the Normal Operating Conditions section.
Normal Operating Conditions
To minimize confusion, normal operating conditions are
defined as follows:
•
The input pins are voltage driven (the source impedance is
assumed to be zero);
•
The output pins are open circuited (the load impedance is
assumed to be infinite);
Rev. C | Page 14 of 32
AD8330
Pin VMAG is unconnected setting up the output bias
current (IN in the four-transistor gain cell) to its nominal
value;
•
Pin CMGN is grounded; and
•
MODE is either tied to a logic high or left unconnected, to
set the up gain mode.
The effects of other operating conditions are considered
separately.
Throughout this data sheet, the end-to-end voltage gain for
the normal operating conditions are referred to as the basic
gain. Under these conditions, it runs from 0 dB when VDBS = 0
(where this voltage is more exactly measured with reference to
Pin CMGN, which is not necessarily tied to ground) up to
50 dB for VDBS = 1.5 V. The gain does not fold over when the
VDBS pin is driven below ground or above its nominal fullscale value.
The input is accepted at the Differential Port INHI/INLO.
These pins are internally biased to roughly the midpoint of the
supply, VS (it is actually ~2.75 V for VS = 5 V, VDBS = 0, and
1.5 V for VS = 3 V), but the AD8330 is able to accept a forced
common-mode value, from zero to VS, with certain limitations.
This interface provides good common-mode rejection up to
high frequencies (see Figure 16) and, thus, can be driven in
either a single-sided or differential manner. However, operation
using a differential drive is preferable, and this is assumed in the
specifications, unless otherwise stated.
The pin-to-pin input resistance is specified as 950 Ω ± 20%. The
driving-point impedance of the signal source can range from
zero up to values considerably in excess of this resistance, with a
corresponding variation in noise figure (see Figure 53). In most
cases, the input is coupled via two capacitors, chosen to provide
adequate low frequency transmission. This results in the
minimum input noise that increases when some other
common-mode voltage is forced onto these pins. The shortcircuit, input referred noise at maximum gain is approximately
5 nV/√Hz.
Output Pin OPHI and Output Pin OPLO operate at a commonmode voltage at the midpoint of the supply, VS/2, within a few
millivolts. This ensures that an analog-to-digital converter
(ADC) attached to these outputs operates within the often
narrow range permitted by their design. When a commonmode voltage other than VS/2 is required at this interface, it can
easily be forced by applying an externally provided voltage to
the output centering pin, CNTR. This voltage can run from zero
to the full supply, though the use of such extreme values leaves
only a small range for the differential output signal swing.
output interface, rather than an op amp style voltage-mode
output, is preferable in high speed applications because the
effects of complex reactive loads on the gain and phase can be
better controlled. The top end of the AD8330 ac response is
optimally flat for a 12 pF load on each pin, but this is not critical
and the system remains stable for any value of load capacitance
including zero.
Another useful feature of this VGA in connection with the
driving of an ADC is that the peak output magnitude can be
precisely controlled by the voltage on Pin VMAG. Usually, this
voltage is internally preset to 500 mV, and the peak differential,
unloaded output swing is ±2 V ± 3%. However, any voltage
from zero to at least 5 V can be applied to this pin to alter the
peak output in an exactly proportional way. Because either
output pin can swing rail-to-rail, which in practice means down
to at least 0.35 V and to within the same voltage below the
supply, the peak-to-peak output between these pins can be as
high as 10 V using VS = 6 V.
CM MODE
FEEDBACK
VPSI
VPSO
TRANSIMPEDANCE
OUTPUT STAGE
INHI 500Ω
OPHI
ΔV = 0
ROUT = 150Ω
ΔV = 0
OPLO
INLO 500Ω
O/P CM-MODE
NORMALLY
AT VP/2
CNTR
LINEAR-IN-dB
INTERFACE
MAGNITUDE
INTERFACE
MODE
100µA
VMAG
VDBS
VDBS
12.65µA–4mA OR
4mA–12.65µA
COMM
VMAG
5kΩ
COMM
Figure 47. Schematic of Key Components
Linear-in-dB Gain Control (VDBS)
All Analog Devices, Inc. VGAs featuring a linear-in-dB gain
law, such as the X-AMP® family, provide exact, constant gain
scaling over the fully specified gain range, and the deviation
from the ideal response is within a small fraction of a dB. For
the AD8330, the scaling of both of its gain interfaces is
substantially independent of process, supply voltage, or
temperature. The basic gain, GB, is simply
GB (dB ) =
VDBS
30 mV
(1)
where VDBS is in volts. Alternatively, this can be expressed as a
numerical gain magnitude
The differential impedance measured between OPHI and
OPLO is 150 Ω ± 20%. It follows that both the gain and the
full-scale voltage swing depend on the load impedance; both are
nominally halved when this is also 150 Ω. A fixed impedance
Rev. C | Page 15 of 32
VDBS
GBN = 10 0.6 V
(2)
03217-048
•
AD8330
The gain can be increased or decreased by changing the voltage,
VMAG, applied to the VMAG pin. The internally set default value
of 500 mV is derived from the same band gap reference that
determines the decibel scaling. The tolerance on this voltage,
and mismatches in certain on-chip resistors, cause small gain
errors (see the Specifications section). Though not all applications of VGAs demand accurate gain calibration, it is a
valuable asset in many situations, for example, in reducing
design tolerances.
Figure 47 shows the core circuit in more detail. The range and
scaling of VDBS is independent of the supply voltage, and the
Gain Control Pin VDBS presents a high incremental input resistance (~100 MΩ) with a low bias current (~100 nA), making
the AD8330 easy to drive from a variety of gain control sources.
Inversion of the Gain Slope
The AD8330 supports many features that further extend the
versatility of this VGA in wide bandwidth, gain control systems.
For example, the Logic Pin MODE allows the slope of the gain
function to be inverted, so that the basic gain starts at +50 dB
for a gain voltage, VDBS, of zero and runs down to 0 dB when
this voltage is at its maximum specified value of 1.5 V. The basic
forms of these two gain control modes are shown in Figure 48.
50
MODE PIN
LOW, GAIN
DECREASES
WITH VDBS
GAIN (dB)
40
GT = GBN
VMAG
0 .5 V
(3)
Using this to calculate the output voltage
VOUT = 2 × GIN × VIN × VMAG
(4)
from which it is apparent that the AD8330 implements a linear,
two-quadrant multiplier with a bipolar VIN and a unipolar VMAG.
Because the AD8330 is a dc-coupled system, it can be used in
many applications where a wideband two-quadrant multiplier
function is required, from dc up to about 100 MHz from either
input (VIN or VMAG).
As VMAG is varied, so also is the peak output magnitude, up to a
point where this is limited by the absolute output limit imposed
by the supply voltage. In the absence of the latter effect, the
peak output into an open circuited load is just
VOUT_PK = ±4 VMAG
(5)
whereas for a load resistance of RL directly across OPHI and
OPLO, it is
VOUT _ PK =
±2 VMAG RL
(6)
(RL + 150 )
These capabilities are illustrated in Figure 49, where VS = 6 V,
RL = O/C, VDBS = 0 V, VIN is swept from −2.5 V dc to +2.5 V dc, and
VMAG is set to 0.25 V, 0.5 V, 1 V, and 2 V. Except for the last value
of VMAG, the peak output follows Equation 5. This exceeds the
supply-limited value when VMAG = 2 V and the peak output is
±5.65 V, that is, ±6 V − 0.35 V. Figure 50 demonstrates the high
speed multiplication capability. The signal input is a 100 MHz,
0.1 V sine wave, VDBS is set to 0.6 V, and VMAG is a square wave at
5 MHz alternating from 0.25 V to 1 V. The output is ideally a
sine wave switching in amplitude between 0.5 V and 2 V.
MODE PIN
HIGH, GAIN
INCREASES
WITH VDBS
30
20
10
0
0.25
0.50
0.75
1.0
VDBS (V)
1.25
1.50
VMAG = 2V
6
1V
4
Figure 48. The Two Gain Directions of the AD8330
0.5V
Gain Magnitude Control (VMAG)
In addition to the basic linear-in-dB control, two more gain
control features are provided. The voltage applied to Pin VMAG
provides accurate linear-in-magnitude gain control with a very
rapid response. The bandwidth of this interface is >100 MHz.
When this pin is unconnected, VMAG assumes its default value of
500 mV (see Figure 47) to set up the basic 0 dB to 50 dB range.
However, any voltage from ~15 mV to 5 V can be applied to
either lower the gain by up to 30 dB or to raise it by 20 dB. The
combined gain span is thus 100 dB, that is, the 50 dB basic gain
span provided by VDBS plus a 60 dB linear-in-magnitude span
provided by VMAG. The latter modifies the basic numerical gain
GBN to generate a total gain, expressed here in magnitude terms
Rev. C | Page 16 of 32
VOUT (V)
2
0.25V
0
–2
–4
–6
–8
–3
–2
–1
0
VIN ( V)
1
2
Figure 49. Effect of VMAG on Gain and Peak Output
3
03217-050
0
03217-049
8
AD8330
VIN
0.10
Amplitude/Phase Response
0.05
The ac response of the AD8330 is remarkably consistent not
only over the full 50 dB of its basic gain range, but also with
changes of gain due to alteration of VMAG, as demonstrated in
Figure 51. This is an overlay of two sets of results: first with a
very low VMAG of 16 mV that reduces the overall gain by 30 dB
[20 × log10(500 mV/16 mV)]; second, with VMAG = 5 V that
increases the gain by 20 dB = 20 × log10(5 V/0.5 V).
0
–0.05
–0.10
VMAG
1.2
1.0
0.8
0.6
0.4
0.2
0
VOUT
90
–200
–100
0
100
200
TIME (ns)
300
50
30
10
–10
–30
–50
100k
0
Another gain related feature allows both gain control ranges
to be accurately raised by 200 mV. To enable this offset, open
circuit Pin 6 (CMGN) and add a 0.1 μF capacitor to ground.
In use, the nominal range for VDBS extends from 0.2 V to 1.7 V
and VMAG from 0.2 V to 5.2 V. These specifications apply for any
supply voltage. This allows the use of DACs whose output range
does not include ground as sources for the gain control function(s).
Note that the 200 mV that appears on this pin affects the
response to an externally applied VMAG, but when Pin VMAG is
unconnected, the internally set default value of 0.5 V still applies.
Furthermore, Pin CMGN can, if desired, be driven by a user
supplied voltage to reposition the baseline for VDBS (or for an
externally applied VMAG) to any other voltage up to 500 mV. In
all cases, the gain scaling, its law conformance, and temperature
stability are unaffected.
Two Classes of Variable Gain Amplifiers
Note that there are two broad classes of VGAs. The first type is
designed to cope with a very wide range of input amplitudes
and, by virtue of its gain control function, compress this range
down to an essentially constant output. This is the function
needed in an AGC system. Such a VGA is called an IVGA,
referring to a structure optimized to address a wide range of
input amplitudes. By contrast, an OVGA is optimized to deliver
a wide range of output values while operating with an essentially
constant input amplitude. This function might be needed, for
example, in providing a variable drive to a power amplifier.
It is apparent from the foregoing sections that the AD8330 is
both an IVGA and an OVGA in one package. This is an unusual
and possibly confusing degree of versatility for a VGA; therefore,
these two distinct control functions are described at separate
points throughout this data sheet to explain the operation and
applications of this product. It is, nevertheless, useful to briefly
describe the capabilities of these features when used together.
PHASE (Degrees)
Figure 50. Using VMAG in Modulation Mode
1M
10M
100M
300M
G = +70dB
–50
–100
–150
–200
–250
–300
–350
10k
G = –20dB
100k
1M
10M
FREQUENCY (Hz)
100M 300M
03217-052
–300
GAIN (dB)
70
03217-051
2.5
2.0
1.5
1.0
0.5
0
–0.5
–1.0
–1.5
–2.0
–400
Figure 51. AC Performance over a 100 dB Gain Range Obtained by
Using Two Values of VMAG
This 50 dB step change in gain produces two sets of gain curves,
having a total gain span of 100 dB. It is apparent that the amplitude and phase response are essentially independent of the gain
over this wide range, an aspect of the AD8330 performance
potential unprecedented in any prior VGA.
It is unusual for an application to require such a wide range of
gains, of course; and as a practical matter, the peak output
voltage for VMAG = 16 mV is reduced by the factor 16/500,
compared to its nominal value of ±2 V, to only ±64 mV. As
already noted, most applications of VGAs require that they
operate in a mode that is predominantly of either an IVGA or
OVGA style, rather than mixed modes.
With this limitation in mind, and simply in order to illustrate
the unusual possibilities afforded by the AD8330, it is noted
that with appropriate drive to VDBS and VMAG in tandem, the
gain span is a remarkable 120 dB, extending from −50 dB to
+70 dB, as shown in Figure 52 for operation at 1 MHz and
100 MHz. In this case, VDBS and VMAG are driven from a common
control voltage, VGAIN, that varies from 1.2 mV to 5 V, with 30%
(1.5/5) of VGAIN applied to VDBS, and 100% applied to VMAG.
The gain varies in a linear-in-dB manner with VDBS, although
the response from VMAG is linear-in-magnitude. Consequently, the
overall numerical gain as the product of these two functions is
GAIN = VGAIN / 0.5 V × 0.3 ×10
Rev. C | Page 17 of 32
VGAIN
0 .6 V
(7)
AD8330
In rare cases where such a wide gain range is of value, the
calibration is still accurate and the temperature is stable.
When a source of impedance (RS) is terminated using a resistor
of RS (a condition that is not to be confused with matching),
only one of these components is used, either the current (as in
the AD8330) or the voltage. Then, even if the amplifier is
perfect, the noise figure cannot be better than 3 dB. The 1 kΩ
internal termination resistance would result in a minimum
noise figure of 3 dB for an RS of 1 kΩ if the amplifier were
noise-free. However, this is not the case, and the minimum
noise figure occurs at a slightly different value of RS (for an
example, see Figure 53 and Using the AD8330 section).
80
40
20
0
–20
–40
10k
15
1k
14
100
13
10
12
0.1
1
VGAIN (V)
10
Figure 52. Gain Control Function and Input Referred Noise Spectral Density
over a 120 dB Range
11
10
9
Noise, Input Capacity, and Dynamic Range
8
The design of variable gain amplifiers invariably incurs some
compromises in noise performance. However, the structure of
the AD8330 is such that this penalty is minimal. Examination
of the simplified schematic (Figure 47) shows that the input
voltage is converted to current-mode form by the two 500 Ω
resistors at Pin INHI and Pin INLO, whose combined Johnson
noise contributes 4.08 nV/√Hz. The total input noise at full
gain, when driven from a low impedance source, is typically
5 nV/√Hz after accounting for the voltage and current noise
contributions of the loop amplifier. For a 200 kHz channel
bandwidth, this amounts to 2.24 μV rms. The peak input at full
gain is ±6.4 mV, or +4.5 mV rms for a sine wave signal. The
signal-to-noise ratio at full input, that is, the dynamic range, for
these conditions is, thus, 20 log10(4.5 mV/2.24 μV), or 66 dB.
The value of VMAG has essentially no effect on the input referred
noise, but it is assumed to be 0.5 V.
7
Below midgain (25 dB, VDBS = 0.75 V), noise in the output
section dominates, and the total input noise is 11 nV/√Hz, or
4.9 μV rms in a 200 kHz bandwidth, and the peak input is
78 mV rms. Thus, the dynamic range increases to 84 dB.
At minimum gain, the input noise is up to 120 nV/√Hz, or
53.7 mV rms in the assumed 200 kHz bandwidth, while the
input capacity is ±2 V, or +1.414 V rms (sine), a dynamic range
of 88.4 dB. In calculating the dynamic range for other channel
bandwidths, Δf, subtract 10 log10(Δf/200 kHz) from these
illustrative values. A system operating with a 2 MHz bandwidth,
for example, exhibits dynamic range values that are uniformly
10 dB lower; used in an audio application with a 20 kHz bandwidth, they are 10 dB higher.
Noise figure is a misleading metric for amplifiers that are not
impedance matched at their input, which is the special condition resulting only when both the voltage and current components
of a signal, that is, the signal power, are used at the input port.
6
5
10
100
RS (Ω)
1k
10k
03217-054
0.01
Figure 53. Noise Figure for Source Resistance of 50 Ω to 5 kΩ, at f = 10 MHz
(Lower) and 100 MHz (Simulation)
144
DYNAMIC RANGE (dB/√Hz)
140
CONSTANT 1V rms
OUTPUT, BOTH CASES
136
132
128
X-AMP WITH 40dB
OF GAIN AND AN
INPUT NSD
OF nV/√Hz
124
120
116
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 1.1 1.2 1.3 1.4 1.5
VDBS (V)
03217-055
1
0.001
03217-053
NOISE (nV/√Hz)
–60
100k
NOISE FIGURE
GAIN (dB)
60
Figure 54. Dynamic Range in dB/√Hz vs. VDBS (VMAG = 0.5 V, 1 V rms Output)
Compared with a Representative X-AMP (Simulation)
Dynamic Range
The ratio of peak output swing, expressed in rms terms, to the
output-referred noise spectral density provides a measure of
dynamic range, in dB/√Hz. For a certain class of variable gain
amplifiers, exemplified by the Analog Devices X-AMP family,
the dynamic range is essentially independent of the gain setting
because the peak output swing and noise are both constant. The
AD8330 provides a different dynamic range profile since there
is no longer a constant relationship between these two parameters.
Figure 54 compares the dynamic range of the AD8330 to a
representative X-AMP.
Rev. C | Page 18 of 32
AD8330
Input Common-Mode Range and Rejection Ratio
The scaling for VDBS = 0 is as follows:
Input Pin INHI and Pin INLO should be ac-coupled in most
applications to achieve the stated noise performance. When
direct coupling is used, care must be taken in setting the dc
voltage level at these inputs, in general, and particularly when
minimizing noise is critical. This objective is complicated by the
fact that the common-mode level varies with the basic gain
voltage, VDBS. Figure 55 shows this relationship for a supply
voltage of 5 V, for temperatures of −40°C, +25°C, and +85°C.
Figure 56 shows the input noise spectral density (RS = 0) vs. the
input common-mode voltage, for VDBS = 0.5 V, 0.6 V, 0.75 V, and
1.5 V. It is apparent that there is a broad range over which the
noise is unaffected by this dc level. The input CMRR is excellent
(see Figure 16).
DC VOLTAGE AT INHI, INLO (V)
3.2
T = +85°C
T = –40°C
2.9
VNOISE_OUT = (0.1 + 0.32 VMAG) μV/√Hz
0.2
0.4
0.6
0.8
VDBS (V)
1.0
1.2
1.4
1.6
03217-056
0
f HPF =
26
VDBS = 0.6V
16
14
10
8
SIMULATION
0
0.4
VDBS = 1.5V
0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
COMMON-MODE VOLTAGE AT INHI, INLO (V)
4.4
(11)
330 μ
C HP
(CHP in μF)
(12)
The offset compensation feature can be disabled simply by
grounding the OFST pin. This provides a dc-coupled signal
path, with no other effects on the overall ac response. Input
offsets must be externally nulled in this mode of operation, as
shown in Figure 58.
VDBS = 0.75V
12
4.8
03217-057
INPUT REFERRED NOISE (nV/√Hz)
20
18
(2π RINT CHP )
A small amount of peaking at this corner when using small
capacitor values can be avoided by adding a series resistor.
Useful combinations are CHP = 3 nF, RHP = 180 Ω , f = 100 kHz;
CHP = 33 nF, RHP = 10 Ω, f = 10 kHz; CHP = 0.33 μF, RHP = 0 Ω,
f = 1 kHz; CHP = 3.3 μF, RHP = 0 Ω, f = 100 Hz.
VDBS = 0.5V
22
1
where CHP is the external capacitance added from OFST to
CNTR, and RINT is an internal resistance of approximately
480 Ω, having a maximum uncertainty of about ±20%. This
evaluates to
Figure 55. Common-Mode Voltage at Input Pins vs. VDBS, for VS = 5 V,
T = −40°C, + 25°C, and + 85°C
24
(10)
for RS = 0 and VDBS = 1.5 V, assuming an input noise of 5 nV/√Hz.
The output noise for very small values of VMAG (at or below 15 mV)
is not precise, partly because the small input offset associated
with this interface has a large effect on the gain.
f HPF =
2.7
4
(9)
For example, using a reduced value of VMAG = 0.25 V that lowers
all gain values by 6 dB, the peak output swing is ±1 V (differ
entially) and the output noise spectral density evaluates to
102.5 nV/√Hz. The peak output swing is no different at full
gain, but the noise becomes
2.8
6
VNOISE_OUT = (85 + 70 VMAG) nV/√Hz
The AD8330 includes an offset compensation feature that is
operational in the default condition (no connection to Pin OFST).
This loop introduces a high-pass filter function into the signal
path, whose −3 dB corner frequency is at
3.0
2.6
(8)
Offset Compensation
T = +25°C
3.1
VOUT_PK = ±4 VMAG
Effects of Loading on Gain and AC Response
Figure 56. Input Noise vs. Common-Mode Input Voltage for
VDBS = 0.5 V, 0.6 V, 0.75 V, and 1.5 V
Output Noise and Peak Swing
The output noise of the AD8330 is the input noise multiplied by
the overall gain, including any optional change to the voltage,
VMAG, applied to Pin VMAG. The peak output swing is also
proportional to this voltage, which, at low gains and high values
of VMAG, affects the output noise.
The differential output impedance (RO) is 150 Ω, and the
frequency response of the output stage is optimized for
operation with a certain load capacitance on each output pin
(OPHI and OPLO) to ground, in combination with a load
resistance (RL) directly across these pins. In the absence of these
capacitances, there is a small amount of peaking at the top
extremity of the ac response. Suitable combinations are: RL = ∞,
CL = 12 pF; RL = 150 Ω, CL = 25 pF; RL = 75 Ω, CL = 40 pF;
RL = 50 Ω, CL = 50 pF.
Rev. C | Page 19 of 32
AD8330
The gain calibration is specified for an open-circuited load,
such as the high input resistance of an ADC. When resistively
loaded, all gain values are nominally lowered as follows:
G LOADED =
GUNLOADED RL
(150 Ω + RL )
(13)
Thus, when RL = 150 Ω, the gain is reduced by 6 dB; for
RL = 75 Ω, the reduction is 9.5 dB; and for RL = 50 Ω, it is 12 dB.
As in all high frequency circuits, careful observation of the
ground nodes associated with each function is important. Three
positive supply pins are provided: VPSI supports the input circuitry that often operates at a relatively high sensitivity; VPOS
supports general bias sources and needs no decoupling; and
VPSO biases the output stage where decoupling can be useful in
maintaining a glitch-free output. Figure 57 shows the general
case, where VPSI and VPSO are each provided with their own
decoupling network, but this is not needed in all cases.
Gain Errors Due to On-Chip Resistor Tolerances
VS 2.7V TO 6V
RD1
CHPF
ENBL
CD1
These variances need to be accounted for when calculating the
gain with input and output loading. This sensitivity can be avoided
by adjusting the source and load resistances to bear an inverse
relationship as follows:
VPSI
OFST
BIAS AND
V-REF
CD2
VPOS
INPUT,
0V TO ±2V MAX
The simplest case is when RS = 1 kΩ and RL = 150 Ω, therefore,
the gain is 12 dB lower than the basic value. The reduction of
peak swing at the load can be corrected by using VMAG = 1 V,
thereby restoring 6 dB of gain; using VMAG = 2 V restores the full
basic gain and doubles the peak available output swing.
Output (Input) Common-Mode Control
The output voltages are nominally positioned at the midpoint of
the supply, VS/2, over the range 2.7 V < VS < 6 V, and this voltage
appears at Pin CNTR, which is not normally expected to be
loaded (the source resistance is ~4 kΩ). However, some circumstances require a small change in this voltage, and a resistor
from CNTR to ground can lower this voltage, whereas a resistor
to the supply raises it. On the other hand, this pin can be driven
by an external voltage source to set the common-mode level to
satisfy, for example, the needs of a following ADC. Any value
from 0.5 V above ground to 0.5 V below the supply is permissible.
Of course, when using an extreme common-mode level, the
available output swing is limited, and it is recommended that
a value equal or close to the default of VCNTR = VS/2 be used.
There may be a few millivolts of offset between the applied
voltage and the actual common-mode level at the output pins.
The input common-mode voltage, VCMI, at Pin INHI and
Pin INLO is slaved to the output, but with a shifted value of
VCMI = 0.757 VCNTR + 1.12 V
(14)
for VDBS = 0.75 and T = 25°C. Thus, the default value for VCMI
when VS = 5 V is 3.01 V (see Figure 55).
USING THE AD8330
This section describes a few general aspects of using the
AD8330. Applying the AD8330 to a wide variety of circumstances requires very few precautions.
VGA CORE
MODE
VDBS
BASIC GAIN BIAS
VDBS: 0V TO 1.5V
CD3
VPSO
OPHI
OUTPUT,
±2V MAX
OUTPUT
STAGES
OPLO
INLO
NC
CNTR
CM MODE AND
OFFSET CONTROL
INHI
If RS = αRI, then make RL = RO/α; or,
if RL = αRO, then make RS = RI/α
RD2
GAIN INTERFACE
CMGN
OUTPUT
CONTROL CMOP
COMM
VMAG
NC
GROUND
03217-058
In all cases where external resistors are used, keep in mind that
all on-chip resistances, including the RO and the input resistance
(RI), are subject to variances of up to ±20%.
Figure 57. Power Supply Decoupling and Basic Connections
Because of the differential nature of the signal path, power
supply decoupling is, in general, much less critical than in a
single-sided amplifier; and where the minimization of boardlevel components is especially crucial, it is possible that these
pins need no decoupling at all. On the other hand, when the
signal source is single-sided, giving extra attention to the
decoupling on Pin VPSI is sometimes required. Likewise,
care is required in decoupling the VPSO pin if the output is
loaded on only one of its two output pins. The general common
(COMM) and the output stage common (CMOP) are usually
grounded as shown in the Figure 57; however, the Applications
section shows how a negative supply can optionally be used.
The AD8330 is enabled by taking the ENBL pin to a logical high
(or, in all cases, the supply). The UP gain mode is enabled either
by leaving the MODE pin unconnected or taking it to a logical
high. When the opposite gain direction is needed, the MODE
pin should be grounded or driven to a logical low. The low-pass
corner of the offset loop is determined by Capacitor CHPF; this
is preferably tied to the CNTR pin, that in turn, should be
decoupled to ground. The gain interface common pin (CMGN)
is grounded, and the output magnitude control pin (VMAG) is
left unconnected, or can optionally be connected to a 500 mV
source for basic gain calibration.
Rev. C | Page 20 of 32
AD8330
Connections to the input and output pins are not shown in
Figure 57 because of the many options that are available. When
the AD8330 is used to drive an ADC, connect the OPHI and
OPLO pins directly to the differential inputs of a suitable converter,
such as an AD9214. If an adjustment is needed to this commonmode level, it can be introduced by applying that voltage to the
CNTR pin, or, more simply, by using a resistor from this pin to
either ground or the supply (see the Applications section). The
CNTR pin can also supply the common-mode voltage to an
ADC that supports such a feature.
Occasionally, it is possible to avoid the use of coupling
capacitors when the dc level of the driving source is within a
certain range, as shown in Figure 56. This range extends from
3.5 V to 4.5 V when using a 5 V supply, and at high basic gains,
where the effect of an incorrect dc level degrades the noise level
due to internal aspects of the input stage. For example, suppose
the driver, IC, is an LNA having an output topology in which its
load resistors are taken to the supply, and the output is buffered
by emitter followers. This presents a source for the AD8330 that
can readily be directly coupled.
When the loads to be driven introduce a dc resistive path to
ground, coupling capacitors must be used. These should be of
sufficient value to pass the lowest frequency components of the
signal without excessive attenuation. Keep in mind that the
voltage swing on such loads alternate both above and below
ground, requiring that the subsequent component must be able
to cope with negative signal excursions.
DC-Coupled Signal Path
The output can also be coupled to a load via a transformer to
achieve a higher load power by impedance transformation. For
example, using a 2:1 turns ratio, a 50 Ω final load presents a
200 Ω load on the output. The gain loss (relative to the basic
value with no termination) is 20 log10{(200+150)/200} or
4.86 dB, which can be restored by raising the voltage on the
VMAG pin by a factor of 104.86/20 or × 1.75, from its basic value
of 0.5 V to 0.875 V. This also restores the peak swing at the 200 Ω
level to ±2 V, or ±1 V into the 50 Ω final load.
Whenever a stable supply voltage is available, additional voltage
swing can be provided by adding a resistor from the VMAG pin
to the supply. The calculation is based on knowing that the internal bias is delivered via a 5 kΩ source; because an additional
0.375 V is needed, the current in this external resistor must be
0.375 V/5 kΩ = 75 μA. Thus, using a 5 V supply, a resistor of
5 V − 0.875 V/75 μA = 55 kΩ is used. Based on this example,
the corrections for other load conditions are easy to calculate.
If the effects on gain and peak output swing due to supply
variations cannot be tolerated, VMAG must be driven by an
accurate voltage.
The dc common-mode voltage at the input pins varies with
the supply, the basic gain bias, and temperature (see Figure 55);
for this reason, many applications need to use coupling capacitors from the source that are large enough to support the lowest
frequencies to be transmitted. Using one capacitor at each input
pin, their minimum values can be readily found from the expression
C IN_CPL =
f HPF
VS 2.7V TO 6V
RD1
E NBL
CD1
VPSI
RS ASSUMED
50kΩ
TO BE 50Ω
ON EACH
SIDE
OFST
BIAS AND
V-REF
VPOS
CD3
VPSO
OPHI
OUTPUT,
±2V MAX
OUTPUT
STAGES
INLO
OPLO
75kΩ
MODE
(15)
BASIC GAIN BIAS
VDBS: 0V TO 1.5V
Rev. C | Page 21 of 32
CNTR
CM MODE AND
OFFSET CONTROL
VGA CORE
VDBS
where fHPF is the –3dB frequency expressed in hertz. Thus, for
an fHPF of 10 kHz, 33 nF capacitors are used.
RD2
CD2
INHI
Input Coupling
320 μF
Since the offset correction loop is placed after the front-end
variable gain sections of the AD8330, the most effective way
of dealing with such offsets is at the input pins, as shown in
Figure 58. For example, assume, for illustrative purposes, that
the resistances associated with each side of the source in a certain application are 50 Ω. If this source has a very low (op amp)
output impedance, the extra resistors should be inserted, with a
negligible noise penalty and an attenuation of only 0.83 dB. The
resistor values shown provide a trim range of about ±2 mV.
GAIN INTERFACE
CMGN
OUTPUT
CONTROL CMOP
COMM
VMAG
NC
GROUND
Figure 58. Input Offset Nulling in a DC-Coupled System
03217-059
Gain and Swing Adjustments When Loaded
In many cases, where the VGA is not required to provide its
lowest noise, the full common-mode input range of zero to VS
can be used without problems, avoiding the need for any ac
coupling means. However, such direct coupling at both the input
and output does not automatically result in a fully dc-coupled
signal path. The internal offset compensation loop must also be
disengaged by connecting the OFST pin to ground. Keep in
mind that at the maximum basic gain of 50 dB (×316), every
millivolt of offset at the input, arising from whatever source,
causes an output offset of 316 mV, which is an appreciable
fraction of the peak output swing.
AD8330
90
VDBS = 1.5V
80
common-mode control loop appear in both the magnitude and
phase response.
OFST: ENABLED
DISABLED
VDBS = 0.75V
70
Adding a dummy 75 Ω to OPLO results in Line 3: the gain is a
further 2.5 dB lower, at about 14 dB. The CM artifacts are no
longer present but a small amount of peaking occurs. If objectionable, this can be eliminated by raising both of the capacitors
on the output pins to 25 pF, as shown in Line 4 of Figure 60.
CMRR (dB)
60
50
40
VDBS = 0V
30
20
10
–10
50k 100k
1M
10M
FREQUENCY (Hz)
100M
03217-060
0
Figure 59. Input CMRR vs. Frequency for Various Values of VDBS
Using Single-Sided Sources and Loads
Where the source provides a single-sided output, either INHI or
INLO can be used for the input, with of course a polarity change
when using INLO. The unused pin must be connected either
through a capacitor to ground, or a dc bias point that corresponds
closely to the dc level on the active signal pin. The input CMRR
over the full frequency range is illustrated in Figure 59. In some
cases, an additional element such as a SAW filter (having a
single-sided balanced configuration) or a flux-coupled transformer can be interposed. Where this element must be terminated
in the correct impedance, other than 1 kΩ, it is necessary to add
either shunt or series resistors at this interface.
The gain reduction incurred both by using only one output and
by the additional effect of loading can be overcome by taking
advantage of the VMAG feature, provided primarily for just such
circumstances. Thus, to restore the basic gain in the first case
(Line 1), a 1 V source should be applied to this pin; to restore the
gain in the second case, this voltage should be raised by a factor
of ×1.5 to 1.5 V. In Case 3 and Case 4, a further factor of ×1.33
is needed to make up the 2.5 dB loss, that is, VMAG should be
raised to 2 V. With the restoration of gain, the peak output
swing at the load is, likewise restored to ±2 V.
Pulse Operation
When using the AD8330 in applications where its transient
response is of greater interest and the outputs are conveyed to
their loads via coaxial cables, the added capacitances can slightly
differ in value, and can be placed either at the sending or load
end of the cables, or divided between these nodes. Figure 61
shows an illustrative example where dual, 1 meter, 75 Ω cables
are driven through dc-blocking capacitors and are independently
terminated at ground level.
30
LINE 1
Because of the considerable variation between applications,
only general recommendations can be made with regard to
minimizing pulse overshoot and droop. The former can be
optimized by adding small load capacitances, if necessary;
the latter requires the use of sufficiently large capacitors (C1).
LINE 3
10
0
LINE 4
–10
LINE 2
–20
PHASE (Degrees)
–30
0
VS 2.7V–6V
LINE 2
–100
CD2
LINE 3
RD2
–200
LINE 4
–300
ENBL
–400
VPSI
–500
–600
1M
OFST
VPOS
CNTR
LINE 1
10M
FREQUENCY (Hz)
100M
500M
BIAS AND
V-REF
CM MODE AND
OFFSET CONTROL
CD3
VPSO
03217-061
GAIN (dB)
20
RL1
C1
INHI
OPHI
Figure 60. AC Gain and Phase for Various Loading Conditions
CL1
VGA CORE
C1
INLO
MODE
Rev. C | Page 22 of 32
VDBS
OPLO
GAIN INTERFACE
CMGN
CL2
RL2
OUTPUT
CONTROL CMOP
COMM
VMAG
NC
03217-062
When driving a single-sided load, either OPHI or OPLO can be
used. These outputs are very symmetric, so the only effect of
this choice is to select the desired polarity. However, when the
frequency range of interest extends to the upper limits of the
AD8330, a dummy resistor of the same value should be attached
to the unused output. Figure 60 illustrates the ac gain and phase
response for various loads and VDBS = 0.75 V. Line 1 shows the
unloaded (CL = 12 pF) case for reference; the gain is 6 dB lower
(20 dB) using only the single-sided output. Adding a 75 Ω load
from OPHI to an ac ground results in Line 2. The gain becomes
a factor of ×1.5 V or 3.54 dB lower, but artifacts of the output
OUTPUT
STAGES
Figure 61. Driving Dual Cables with Grounded Loads
AD8330
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
1.2
1.0
0.8
0.6
0.4
0.2
0
–0.2
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
–1.2
that is not dependent on sample-to-sample variations in on chip
resistances. Furthermore, this fixed and predictable loss can be
corrected by an adjustment to VMAG , as indicated in Table 5.
0
5ns
10ns
15ns
20ns
25ns
03217-063
Table 5. Preserving Absolute Gain
Figure 62. Typical Pulse Response for Figure 61
Figure 62 shows typical results for VDBS = 0.24 V, a square wave
input amplitude of 450 mV (the actual combination is not
important), a rise time of 2 ns, and VMAG raised to 2.0 V. In the
upper waveforms, the load capacitors are both zero, and a small
amount of overshoot is visible; with 40 pF the response is cleaner.
A shunt capacitance of 20 pF from OPHI to OPLO has a similar
effect. Coupling capacitors for this demonstration are sufficiently large to prevent any visible droop over this time scale.
The outputs at the load side eventually assume a mean value of
zero, with negative and positive excursions depending on the
duty cycle.
The bandwidth from Pin VMAG to these outputs is somewhat
higher than from the normal input pins. Thus, when this pin is
used to rapidly modulate the primary signal, some further
experimentation with response optimization may be required.
In general, the AD8330 is very tolerant of a wide range of
loading conditions.
Preserving Absolute Gain
Although the AD8330 is not laser trimmed, its absolute gain
calibration, based mainly on ratios, is very good. Full details are
found in the Specifications section and in the typical performance
curves (see the Typical Performance Characteristics section).
Nevertheless, having finite input and output impedances, the
gain is necessarily dependent on the source and load conditions.
The loss that is incurred when either of these is finite causes an
error in the absolute gain. The absolute gain can also be
uncertain due to the approximately ±20% tolerance in the
absolute value of the input and output impedances.
RS (Ω)
10
15
20
30
50
75
100
150
200
300
500
750
1k
1.5 k
2k
RL (Ω)
15 k
10 k
7.5 k
5.0 k
3.0 k
2.0 k
1.5 k
1.0 k
750
500
300
200
150
100
75
Uncorrected Loss
Factor
dB
0.980
0.17
0.971
0.26
0.961
0.34
0.943
0.51
0.907
0.85
0.865
1.26
0.826
1.66
0.756
2.43
0.694
3.17
0.592
4.56
0.444
7.04
0.327
9.72
0.250
12.0
0.160
15.9
0.111
19.1
VMAG Required to
Correct Loss
0.510
0.515
0.520
0.530
0.551
0.578
0.605
0.661
0.720
0.845
1.125
1.531
2.000
3.125
4.500
Calculation of Noise Figure
The AD8330 noise is a consequence of its intrinsic voltage noise
spectral density (ENSD) and the current noise spectral density
(INSD). Their combined effect generates a net input noise,
VNOISE_IN, that is a function of the input resistance of the device
(RI), nominally 1 kΩ, and the differential source resistance (RS)
as follows:
VNOISE _ IN =
{E NSD 2 + I NSD 2 (RI + RS )2 }
(16)
Note that we assume purely resistive source and input impedances
as a concession to simplicity. A more thorough treatment of
noise mechanisms, for the case where the source is reactive, is
beyond the scope of these brief notes. Also note that VNOISE_IN is
the voltage noise spectral density appearing across INHI and
INLO, the differential input pins. In preparing for the
calculation of the noise figure, VSIG is defined as the opencircuit signal voltage across the source, and VIN is defined as the
differential input to the AD8330. The relationship is simply
VIN =
VSIG R I
(17)
(RI + RS )
Often, such losses and uncertainties can be tolerated and
accommodated by a correction to the gain control bias. On the
other hand, the error in the loss can be essentially nulled by
using appropriate modifications to either the source impedance
(RS) or the load impedance (RL), or both (in some cases by
padding them with series or shunt components).
At maximum gain, ENSD is 4.1 nV/√Hz, and INSD is 3 pA/√Hz.
Thus, the short-circuit voltage noise is
The formulation for this correction technique was previously
described. However, to simplify its use, Table 5 shows spot
values for combinations of RS and RL resulting in an overall loss
Next, examine the net noise when RS = RI = 1 kΩ, often
incorrectly called the matching condition, rather than source
VNOISE _ IN =
{(4.1 n V/ Hz ) + (3 pA / Hz ) (1 kΩ + 0) } =
5.08 nV/√Hz
Rev. C | Page 23 of 32
2
2
2
(18)
AD8330
impedance termination, which is the actual situation in this
case. Repeating the procedure
VNOISE _ IN =
theory, yield extremely low distortion, a result of the fundamental linearization technique that is an inherent aspect of
these circuits.
(4.1n V/ Hz )2 + (3 pA/ Hz )2 (1 kΩ + 1 kΩ)2
= 7.3 nV/√Hz
(19)
The noise figure is the decibel representation of the noise factor,
NFAC, commonly defined as follows:
N FAC =
SNR at input
(20)
SNR at output
However, this is equivalent to
N FAC =
SNR at the source
SNR at the input pins
(21)
P1 dB and V1 dB
Let VNSD be the voltage noise spectral density √kTRS due to the
source resistance. Using Equation 17, gives
N FAC =
=
VSIG {RI /(RI + RS )}/ VNSD
VIN /{VNOISE _ IN RS /(RI + RS )}
RIVNOISE _ IN
(22)
RS VNSD
Then, using the result from Equation 19 for a source resistance
of 1 kΩ, having a noise-spectral density of 4.08 nV/√Hz,
produces
N FAC =
(1 kΩ)(7.3 nV /
(1 kΩ)(4.08 nV /
) = 1.79
Hz )
Hz
(23)
Finally, converting this to decibels using
NFIG = 10 log10(NFAC)
(24)
Thus, the resultant noise figure in this example is 5.06 dB,
which is somewhat lower than the value shown in Figure 53 for
this operating condition.
Noise as a Function of VDBS
The chief consequence of lowering the basic gain using VDBS is
that the current noise spectral density INSD increases with the
square root of the basic gain magnitude, GBN such that
INSD = (3 pA/√Hz)(√GBN)
In practice, however, the effect of device mismatches and
junction resistances in the core cell, and other mechanisms in
its supporting circuitry inevitably cause distortion, further
aggravated by other effects in the later output stages. Some of
these effects are very consistent from one sample to the next,
while those due to mismatches (causing predominantly evenorder distortion components) are quite variable. Where the
highest linearity (and also lowest noise) is demanded, consider
using one of the X-AMP products such as the AD603 (singlechannel), AD604 (dual-channel), or AD8332 (wideband dualchannel with ultralow noise LNAs).
(25)
Therefore, at the minimum basic gain of ×0, INSD rises to
53.3 pA/√Hz. However, the noise figure rises to 17.2 db if it
is recalculated using the procedures in Equation16 through
Equation 24.
Distortion Considerations
Continuously variable gain amplifiers invariably employ
nonlinear circuit elements; consequently, it is common for their
distortion to be higher than well-designed fixed gain amplifiers.
The translinear multiplier principles used in the AD8330, in
In addition to the nonlinearities that arise within the core of the
AD8330, at moderate output levels, another metric that is more
commonly stated for RF components that deliver appreciable
power to a load is the 1 dB compression point. This is defined
in a very specific manner: it is that point at which, with increasing
output level, the power delivered to the load eventually falls to a
value that is 1 dB lower than it would be for a perfectly linear
system. (Although this metric is sometimes called the 1 dB gain
compression point, it is important to note that this is not the
output level at which the incremental gain has fallen by 1 dB).
As was shown in Figure 49, the output of the AD8330 limits
quite abruptly, and the gain drops sharply above the clipping
level. The output power, on the other hand, using an external
resistive load, RL, continues to increase. In the most extreme
case, the waveform changes from the sinusoidal form of the test
signal, with an amplitude just below the clipping level, VCLIP, to
a squarewave of precisely the same amplitude. The change in
power over this range is from (VCLIP/√2)2/RL to (VCLIP)2/RL, that
is, a factor of 2, or 3 dB in power terms. It can be shown that for
an ideal limiting amplifier, the 1 dB compression point occurs
for an overdrive factor of 2 dB.
For example, if the AD8330 is driving a 150 Ω load and VMAG
has been set to 2 V, the peak output is nominally ±4 V (as
noted above, the actual value when loaded can differ because
of a mismatch between on chip and external resistors), or
2.83 V rms for a sine wave output that corresponds to a power
of 53.3 mW, that is, 17.3 dBm in 150 Ω. Thus, the P1dB level, at
2 dB above clipping, is 19.3 dBm.
Though not involving power transfer, it is sometimes useful to
state the V1dB, which is the output voltage (unloaded or
loaded) that is 2 dB above clipping for a sine waveform. In the
above example, this voltage is still 2.83 V rms that can be
expressed as 9.04 dBV (0 dBV corresponds to a 1 V sine wave).
Thus, the V1dB is at 11.04 dBV.
Rev. C | Page 24 of 32
AD8330
APPLICATIONS
The AD8330’s versatility, very constant ac response over a wide
range of gains, large signal dynamic range, output swing, single
supply operation, and low power consumption commend this
VGA to a diverse variety of applications. Only a few can be described here, including the most basic uses and some unusual ones.
from VMAG to ground. An overrange condition is signaled by
a high state on pin OR of the AD9214. DFS/GAIN is
unconnected in this example producing an offset-binary output.
To provide a twos complement output, it should be connected
to the REF pin.
ADC DRIVING
For ADCs running at sampling rates substantially below the
bandwidth of the AD8330, an intervening noise filter is
recommended to limit the noise bandwidth. A one-pole filter
can easily be created with a single differential capacitor between
OPHI and OPLO outputs. For a corner frequency of fC, the
capacitor should have a value of
The AD8330 is well-suited to drive a high speed converter.
There are many high speed converters available, but to illustrate the general features, the example in this data sheet uses
one of the least expensive, the AD9214. This is available in three
grades for operation at 65 MHz, 80 MHz, and 105 MHz; the
AD9214BRS-80 is a good complement to the general capabilities of this VGA.
CFILT = 1/942 fC
(26)
For example, a 10 MHz corner requires about 100 pF.
Figure 63 shows the connections to drive an ADC. A 3.3 V
supply is used for both parts. The ADC requires that its input
pins be positioned at one third of the supply, or 1.1 V. Given
that the default output level of the VGA is one half the supply
or 1.65 V, a small correction is introduced by the 8 kΩ resistor
from CNTR to ground. The ADC specifications require that the
common-mode input be within ±0.2 V of the nominal 1.1 V;
variations of up to ±20% in the AD8330 on chip resistors change
this voltage by only ±70 mV. With the connections shown, the
AD9214 is able to receive an input of 2 V p-p; the peak output
of the AD8330 can be reduced if desired by adding a resistor
SIMPLE AGC AMPLIFIER
Figure 64 illustrates the use of the inverted gain mode and the
offset gain range (0.2 V < VDBS < 1.7 V) in supporting a low cost
AGC loop. Q1 is used as a detector. When OPHI is sufficiently
higher than CNTR, due to the signal swing, it conducts and
charges C1. This raises VDBS and rapidly lowers the gain. Note
that MODE is grounded (see Figure 48). The minimum voltage
needed across R1 to set up the full gain is 0.2 V because CMGN
is dc open-circuited (this does not alter VMAG) and the
maximum voltage is 1.7 V.
VS, 3.3V
0.1µF
8kΩ
3.3Ω
0.1µF
OVERRANGE
3.3Ω
CHPF
VPSI
0.1µF
OFST
0.1µF
VPOS
CNTR
VPSO
CM MODE AND
OFFSET CONTROL
BIAS AND
V-REF
OR
DrVDD
D9
PWRDN
D8
DFS/GAIN
OPHI
INHI
INPUT,
±2V MAX
VGA CORE
MODE
VDBS
GAIN BIAS,
VDBS , 0V–1.5V
CMGN
D6
OUTPUT
CONTROL CMOP
COMM
D5
AD9214BRS-80
OPLO
GAIN INTERFACE
D7
AIN
OUTPUT
STAGES
INLO
NC
AVDD
D3
REFSENSE
D2
D1
REF
D0
AGND
VMAG
NC
D4
AIN
DATA OUTPUTS
ENBL
CLK
DGND
0.1µF
ANALOG GROUND
CLOCK
DIGITAL
GROUND
Figure 63. Driving an Analog-to-Digital Converter (Preliminary)
Rev. C | Page 25 of 32
03217-064
10Ω
AD8330
This simple detector exhibits a temperature variation in the
differential output amplitude of about 4 mV/°C. It provides a
fast attack time (an increase in the input is quickly leveled to the
nominal output, due to the high peak currents in Q1) and a
slow release time (a decrease in the input is not restored as
quickly). The voltage at the VDBS pin can be used as an RSSI
output, scaled 30 mV/dB. Note that the attack time can be
halved by adding a second transistor, labeled Q2 in Figure 64.
For operation at lower frequencies, the AGC hold capacitor
must be increased.
VS, 2.7V–6V
33nF
10Ω
ENBL
VPSI
OFST
VPOS
CNTR
CM MODE AND
OFFSET CONTROL
BIAS AND
V-REF
4.7Ω
VPSO
0.1µF
0.1µF
OPHI
INHI
INPUT,
5mV TO 1V rms
OUTPUT
STAGES
VGA CORE
INLO
MODE
SEE
TEXT
OUTPUT,
~1V rms
OPLO
GAIN INTERFACE
VDBS
CMGN
Q2
OUTPUT
CONTROL CMOP
COMM
WIDE RANGE TRUE RMS VOLTMETER
Q1
VMAG
0.1µF
03217-065
NC
R1
10kΩ
C1
0.1µF
0.1µF
The AD8362 is an rms responding detector providing a
dynamic range of 60 dB from low frequencies to 2.7 GHz.
This can increase to 110 dB using an AD8330 as a preconditioner, provided the noise bandwidth is limited by an interstage
low-pass or band-pass filter.
Figure 64. Simple AGC Amplifier (Preliminary)
When the loop is settled, the average current in Q1 is VDBS/R1,
which varies from 2 μA at maximum gain (VDBS = 0.2 V) to
17 μA at minimum gain (VDBS = 1.7 V). This change in the Q1
current causes an increase of ~0.25 dB over the full gain range
in the differential output of nominally 0.75 dBV at midrange
(3.08 V p-p), corresponding to a 200:1 compression ratio. This
is plotted in Figure 65 for a representative 100 kHz input.
1.0
The VGA also provides an input port that is easier to drive than
the 200 Ω input of the AD8362. Figure 67 shows the general
scheme.
Both the AD8330 and AD8362 provide linear-in-decibel control
interfaces. Thus, when the output of the AD8362 is used to
control the gain of the AD8330, the functional form is
unaffected. The overall scaling is 33 mV/dB. Figure 68 shows
the time domain response using a loop filter capacitor of 10 nF,
for inputs ranging from 10 μV to 1 V rms, that is, a 100 dB
measurement range.
1.75
1.50
VDBS
1.25
0.8
1.00
0.75
GAIN ERROR (dB)
0.7
0.6
–40
–30
–20
INPUT TO AD8330 (dBV)
–10
0
0.25
0
3
2
1
0
03217-066
0.5
–50
0.50
–1
–2
Figure 65. AGC Output vs. Input Amplitude (Simulation)
OUTPUT
–3
–4
The upper panel in Figure 66 shows time-domain output for
fourteen 3 dB steps in input amplitude from 5.4 mV to 1.7 V.
The waveforms in Figure 65 show the AGC voltage (VDBS).
Rev. C | Page 26 of 32
0
10
20
30
40
50
60
70
80
90
100 110 120 130 140 150
TIME (µs)
Figure 66. Time Domain Waveforms (Simulation)
03217-067
LEVELED OUTPUT (dBV)
0.9
AD8330
5V
3.3Ω
3.3Ω
0.1µF
AD8362
0.1µF
VPOS
VPS1
CNTR
VPSO
INHI
OPHI
CFLT
18nF
AD8330
INPUT
INLO
OPLO
MODE
CMOP
CMGN
COMM
VMAG
2
CHPF
VREF 15
3
DECL
VTGT 14
4
INHI
VPOS 13
5
INLO
VOUT 12
6
DECL
VSET 11
7
PWDN
ACOM 10
8
COMM
CLPF 9
0.1µF
3.6V
VOUT
0.1µF
10µF
6.04kΩ
4.02kΩ
Figure 67. Wide Range True RMS Voltmeter (Preliminary)
4
3
OUTPUT (V)
VDBS
ACOM 16
2
1
0
0
0 .4
0.8
1.2
1.6
2.0
2.4 2.8
TIME (ms)
3.2
3.6
4.0
4.4
4.8
Figure 68. Time Domain Response of RMS Voltmeter (Simulation)
Rev. C | Page 27 of 32
03217-068
OFST
COMM
10µF
3.6V
ENBL
1
03217-069
0.1µF
3.3Ω
AD8330
OUTLINE DIMENSIONS
0.60 MAX
3.00
BSC SQ
BOTTOM VIEW
0.45
PIN 1
INDICATOR
13
12
2.75
BSC SQ
TOP
VIEW
0.80 MAX
0.65 TYP
12° MAX
0.90
0.85
0.80
16
9
4
8
5
PIN 1
INDICATOR
*1.65
1.50 SQ
1.35
0.25 MIN
1.50 REF
THE EXPOSED PAD IS NOT CONNECTED
INTERNALLY. FOR INCREASED RELIABILITY
OF THE SOLDER JOINTS AND MAXIMUM
THERMAL CAPABILITY, IT IS RECOMMENDED
THAT THE PADDLE BE SOLDERED TO THE
GROUND PLANE.
0.05 MAX
0.02 NOM
0.30
0.23
0.18
1
EXPOSED
PAD
0.50
BSC
SEATING
PLANE
0.50
0.40
0.30
0.20 REF
*COMPLIANT TO JEDEC STANDARDS MO-220-VEED-2
EXCEPT FOR EXPOSED PAD DIMENSION.
Figure 69. 16-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
3 mm × 3 mm Body, Very Thin Quad
(CP-16-3)
Dimensions shown in millimeters
0.197
0.193
0.189
9
16
0.158
0.154
0.150
1
8
0.244
0.236
0.228
PIN 1
0.069
0.053
0.065
0.049
0.010
0.025
0.004
BSC
COPLANARITY
0.004
0.012
0.008
SEATING
PLANE
0.010
0.006
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-137-AB
Figure 70. 16-Lead Shrink Small Outline Package [QSOP]
(RQ-16)
Dimensions shown in inches
Rev. C | Page 28 of 32
0.050
0.016
AD8330
ORDERING GUIDE
Model
Temperature Range
Package Description
Package Option
Branding
AD8330ACP-R2
AD8330ACP-REEL
AD8330ACP-REEL7
AD8330ACPZ-R2 1
AD8330ACPZ-RL1
AD8330ACPZ-R71
AD8330ARQ
AD8330ARQ-REEL
AD8330ARQ-REEL7
AD8330ARQZ1
AD8330ARQZ-RL1
AD8330ARQZ-R71
AD8330-EVAL
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead LFCSP_VQ
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
16-Lead QSOP
Evaluation Board
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
CP-16-3
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
RQ-16
JFA
JFA
JFA
JFZ
JFZ
JFZ
1
Z = Pb-free part.
Rev. C | Page 29 of 32
AD8330
NOTES
Rev. C | Page 30 of 32
AD8330
NOTES
Rev. C | Page 31 of 32
AD8330
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C03217-0-6/06(C)
Rev. C | Page 32 of 32