HV9925 DATA SHEET (09/17/2008) DOWNLOAD

HV9925
Programmable-Current LED Lamp Driver IC
with PWM Dimming
Features
General Description
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The HV9925 is a pulse width modulated (PWM) high-efficiency
LED driver control IC with PWM dimming capabilities. It
allows efficient operation of high brightness LED strings from
voltage sources ranging up to 400VDC. The HV9925 includes
an internal high-voltage switching MOSFET controlled with a
fixed off-time (TOFF) of approximately 10.5µs. The LED string
is driven at constant current, thus providing constant light
output and enhanced reliability. Selecting a value of a current
sense resistor can externally program the output LED current
of the HV9925.
Programmable output current to 50mA
PWM dimming / enable
Universal 85 - 264VAC operation
Fixed off-time buck converter
Internal 475V power MOSFET
Over-temperature protection with hysteresis
Applications
► Decorative lighting
► Low power lighting fixtures
The peak current control scheme provides good regulation
of the output current throughout the universal AC line voltage
range of 85 to 264VAC or DC input voltage of 20 to 400V.
The HV9925 is designed with a built in thermal shutdown to
prevent excessive power dissipation in the IC.
Typical Application Circuit
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HV9925
Ordering Information
Package Option
Device
8-Lead SOIC (w/Heat Slug)
HV9925
4.90x3.90mm body
1.70mm height (max)
1.27mm pitch
HV9925SG-G
-G indicates package is RoHS compliant (‘Green’)
Absolute Maximum Ratings
Pin Configuration
Parameter
Value
Supply voltage, VDD
-0.3 to +10V
PWMD, RSENSE voltage
-0.3 to +10V
+5mA
Supply current, IDD
Operating ambient temperature range
-40°C to +85°C
Operating junction temperature range
-40°C to +125°C
Storage temperature range
-65°C to +150°C
Power dissipation @ 25°C
RSENSE
1
8
DRAIN
GND
2
7
DRAIN
PWMD
3
6
DRAIN
VDD
4
5
NC
Heat Slug
8-Lead SOIC (SG)
(top view)
Heat slug is at ground potential.
800mW**
All voltages referenced to GND pin.
Product Marking
**The power dissipation is given for the standard minimum pad without a heat
slug, and based on RθJA = 125°C/W. RθJA is the sum of the junction-to-case
and case-to-ambient thermal resistance, where the latter is determined by
the user’s board design. The junction-to-ambient thermal resistance is RθJA=
105°C/W when the part is mounted on a 0.04 in2 pad of 1 oz copper, and
RθJA= 60°C/W when mounted on a 1.0in2 pad of 1 oz copper.
Y = Year Sealed
WW = Week Sealed
L = Lot Number
= “Green” Packaging
YWW
H9925
LLLL
8-Lead SOIC (SG)
Electrical Characteristics (The specifications are at T = 25°C and V
A
Sym
VDD
Parameter
DRAIN
= 50V, unless otherwise noted.)
Min
Typ
Max
Units
Conditions
VDD regulator output
-
-
7.5
-
V
---
VDD undervoltage threshold
-
4.8
-
-
V
---
ΔVUVLO VDD undervoltage lockout hysteresis
-
-
200
-
mV
---
-
-
300
500
μA
VDD(EXT) = 8.5V
Breakdown voltage
*
475
-
-
V
---
VDRAIN supply voltage
-
20
-
-
V
---
On-resistance
-
-
100
200
Ω
IDRAIN = 50mA
Output capacitance
#
-
1.0
5.0
pF
VDRAIN = 400V
DRAIN saturation current
-
100
150
-
mA
---
VUVLO
IDD
Operating supply current
Output (DRAIN)
VBR
VDRAIN
RON
CDRAIN
ISAT
Notes:
* Denotes the specifications which apply over the full operating ambient temperature range of -40°C < TA < +85°C.
# Denotes guaranteed by design.
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2
HV9925
Electrical Characteristics (cont.) (The specifications are at T = 25°C and V
A
Sym
Parameter
Min
DRAIN
= 50V, unless otherwise noted.)
Typ
Max
Units
Conditions
0.470
0.525
V
---
Current Sense Comparator
VTH
Threshold voltage
- 0.435
Leading edge blanking delay
#
200
300
400
ns
---
-
-
-
650
ns
---
-
8.0
10.5
13
μs
---
VPWMD,HI PWMD input high voltage
-
2.0
-
-
V
---
VPWMD,LO PWMD input low voltage
-
-
-
0.8
V
---
-
100
200
300
kΩ
VPWMD = 5.0V
Over temperature trip limit
#
-
140
-
°C
---
Temperature hysteresis
#
-
60
-
°C
---
TBLANK
TON(MIN) Minimum on time
Off-Time Generator
TOFF
Off time
PWM Dimming
RPWMD
PWMD pull down resistance
Thermal Shutdown
TOT
THYST
Notes:
*
Denotes the specifications which apply over the full operating ambient temperature range of -40°C < TA < +85°C.
# Denotes guaranteed by design.
Functional Block Diagram
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3
HV9925
Typical Performance Characteristics (T
J
Threshold Voltage VTH vs Temperature TJ
0.485
ON Resistance RON vs Temperature TJ
200
180
0.480
ON Resistance, Ohm
Current Sense Threshold, V
= 25OC unless otherwise noted)
0.475
0.470
160
140
120
100
80
0.465
60
0.460
-40
-15
10
35
60
85
Junction Temperature, °C
40
110
-40
OFF Time TOFF vs Temperature TJ
13.0
-15
10
35
60
85
Junction Temperature, °C
110
Output Capacitance CDRAIN vs VDRAIN
1000
DRAIN Capacitance, pF
OFF Time, μs
12.5
12.0
11.5
11.0
10.5
10.0
100
10
9.5
1
9.0
-40
10
35
60
85
Junction Temperature, °C
0
110
DRAIN Breakdown Voltage BV vs TJ
570
160
560
140
540
530
520
510
30
40
TJ = 25OC
TJ = 125OC
120
100
80
60
40
20
500
490
-40
20
Output Characteristics IDRAIN vs VDRAIN
180
550
10
DRAIN Voltage, V
DRAIN Current, mA
DRAIN Breakdown Voltage, V
580
-15
0
-15
10
35
60
85
Junction Tem perature, °C
110
0
10
20
30
DRAIN Voltage, V
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4
40
HV9925
Functional Description
The HV9925 is a PWM peak current control IC for driving
a buck converter topology in continuous conduction mode
(CCM). The HV9925 controls the output current (rather than
output voltage) of the converter that can be programmed by
a single external resistor (RSENSE), for the purpose of driving a
string of light emitting diodes (LED). An external enable input
(PWMD) is provided that can be utilized for PWM dimming of
an LED string. The typical rising and falling edge transitions
of the LED current when using the PWM dimming feature of
the HV9925 are shown in Fig. 6 and Fig. 7.
When the input voltage of 20 to 400V appears at the DRAIN
pin, the internal linear regulator seeks to maintain a voltage
of 7.5VDC at the VDD pin. Until this voltage exceeds the
internally programmed under-voltage threshold, no output
switching occurs. When the threshold is exceeded, the
integrated high-voltage switch turns on, pulling the DRAIN
low. A 200mV hysteresis is incorporated with the undervoltage comparator to prevent oscillation.
When the voltage at RSENSE exceeds 0.47V, the switch turns
off and the DRAIN output becomes high impedance. At the
same time, a one-shot circuit is activated that determines
the off-time of the switch (10.5µs typ.).
A “blanking” delay of 300ns is provided upon the turn-on of
the switch that prevents false triggering of the current sense
comparator due to the leading edge spike caused by circuit
parasitics.
Application Information
Selecting L1 and D1
The required value of L1 is inversely proportional to the ripple
current ∆IO in it. Setting the relative peak-to-peak ripple to
20~30% is a good practice to ensure noise immunity of the
current sense comparator.
L1 = (VO • TOFF) / ΔIO
(1)
VO is the forward voltage of the LED string. TOFF is the offtime of the HV9925. The output current in the LED string (IO)
is calculated then as:
IO = (VTH / RSENSE) - 1/2ΔIO
(2)
where VTH is the current sense comparator threshold, and
RSENSE is the current sense resistor. The ripple current
introduces a peak-to-average error in the output current
setting that needs to be accounted for. Due to the constant
off-time control technique used in the HV9925, the ripple
current is nearly independent of the input AC or DC voltage
variation. Therefore, the output current will remain unaffected
by the varying input voltage.
Adding a filter capacitor across the LED string can reduce
the output current ripple even further, thus permitting a
reduced value of L1. However, one must keep in mind that
the peak-to-average current error is affected by the variation
of TOFF. Therefore, the initial output current accuracy might
be sacrificed at large ripple current in L1.
Another important aspect of designing an LED driver with
HV9925 is related to certain parasitic elements of the
circuit, including distributed coil capacitance of L1, junction
capacitance, and reverse recovery of the rectifier diode D1,
capacitance of the printed circuit board traces CPCB and output
capacitance CDRAIN of the controller itself. These parasitic
elements affect the efficiency of the switching converter and
could potentially cause false triggering of the current sense
comparator if not properly managed. Minimizing these
parasitics is essential for efficient and reliable operation of
HV9925.
Coil capacitance of inductors is typically provided in the
manufacturer’s data books either directly or in terms of the
self-resonant frequency (SRF).
SRF = 1 / (2π√(L • CL))
where L is the inductance value, and CL is the coil capacitance.
Charging and discharging this capacitance every switching
cycle causes high-current spikes in the LED string. Therefore,
connecting a small capacitor CO (~10nF) is recommended to
bypass these spikes.
Using an ultra-fast rectifier diode for D1 is recommended to
achieve high efficiency and reduce the risk of false triggering
of the current sense comparator. Using diodes with shorter
reverse recovery time trr, and lower junction capacitance CJ,
achieves better performance. The reverse voltage rating VR
of the diode must be greater than the maximum input voltage
of the LED lamp.
The total parasitic capacitance present at the DRAIN output
of the HV9925 can be calculated as:
CP = CDRAIN + CPCB + CL + CJ
(3)
When the switch turns on, the capacitance CP is discharged
into the DRAIN output of the IC. The discharge current is
limited to about 150mA typically. However, it may become
lower at increased junction temperature. The duration of the
leading edge current spike can be estimated as:
TSPIKE = ((VIN • CP) / ISAT) + trr
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5
(4)
HV9925
In order to avoid false triggering of the current sense
comparator, CP must be minimized in accordance with the
following expression:
(5)
where TBLANK(MIN) is the minimum blanking time of 200ns, and
VIN(MAX) is the maximum instantaneous input voltage.
The typical DRAIN and RSENSE voltage waveforms are shown
in Fig. 3 and Fig. 4.
When the LED driver is powered from the full-wave
rectified AC line input, the exact equation for calculating the
conduction loss is more cumbersome. However, it can be
estimated using the following equation:
PCOND = (KC • IO2 • RON) + (KD • IDD • VAC)
where VAC is the input AC line voltage. The coefficients KC
and Kd can be determined from the minimum duty ratio
Dm=0.71Vo/(VAC).
0.7
Estimating Power Loss
0.6
Discharging the parasitic capacitance CP into the DRAIN
output of the HV9925 is responsible for the bulk of the
switching power loss. It can be estimated using the following
equation:
(6)
where FS is the switching frequency and ISAT is the saturated
DRAIN current of the HV9925. The switching loss is the
greatest at the maximum input voltage.
Disregarding the voltage drop at HV9925 and D1, the
switching frequency is given by the following:
FS =
(10)
VIN - VO
(7)
VIN • TOFF
When the HV9925 LED driver is powered from the full-wave
rectified AC input, the switching power loss can be estimated
as:
(8)
0.5
KD ( DM )
K C ( DM )
0.4
0.3
0.2
0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
DM
Figure 1. Conduction Loss Coefficients KC and Kd
EMI Filter
As with all off-line converters, selecting an input filter is critical
to obtaining good EMI. A switching side capacitor, albeit of
small value, is necessary in order to ensure low impedance
to the high frequency switching currents of the converter. As
a rule of thumb, this capacitor should be approximately 0.10.2 µF/W of LED output power. A recommended input filter is
shown in Figure 2 for the following design example.
VAC is the input AC line voltage.
Design Example 1
The switching power loss associated with turn-off transitions
of the DRAIN output can be disregarded. Due to the large
amount of parasitic capacitance connected to this switching
node, the turn-off transition occurs essentially at zerovoltage.
Let us design an HV9925 LED lamp driver meeting the
following specifications:
When the HV9925 LED driver is powered from DC input
voltages, conduction power loss can be calculated as:
PCOND = (D • IO2 • RON) + IDD • VIN • (1 - D)
(9)
Input:
Universal AC, 85-264VAC
Output Current: 20mA
Load:
String of 10 LED (LW541C by OSRAM
VF = 4.1V max. each)
The schematic diagram of the LED driver is shown in
Figure 2.
where D = VO /VIN is the duty ratio, RON is the ON resistance,
IDD is the internal linear regulator current.
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6
HV9925
Step 1. Calculating L1.
Total power dissipation at VAC(max):
The output voltage VO = 10 · VF ≈ 41V (max.). Use equation
(1) assuming a 30% peak-to-peak ripple.
PTOTAL = 130mW + 50mW = 180mW
L1 = (41V • 10.5µs) / (0.3 • 20mA) = 72mH
Select L1 68mH, I=30mA. Typical SRF = 170KHz. Calculate
the coil capacitance.
68
Step 6. Selecting input capacitor CIN
Output Power = 41V • 20mA = 820mW
Select CIN ECQ-E4104KF by Panasonic (0.1µF, 400V,
Metalized Polyester Film).
Design Example 2
Let us now design a PWM-dimmable LED lamp driver using
the HV9925:
Step 2. Selecting D1
Usually, the reverse recovery characteristics of ultrafast rectifiers at IF = 20~50mA are not provided in the
manufacturer’s data books. The designer may want to
experiment with different diodes to achieve the best result.
Select D1 MUR160 with VR = 600V, trr ≈ 20ns (IF = 20mA, IRR
= 100mA) and CJ ≈ 8pF (VF>50V).
Step 3. Calculate total parasitic capacitance using (3):
CP = 5pF + 5pF +13pF + 8pF = 31pF
Step 4. Calculating the leading edge spike duration using
(4) and (5):
Step 5. Estimating power dissipation in HV9925 at 264VAC
using (8) and (10)
Switching power loss:
10.5µs
Input:
Universal AC, 85-135VAC
Output Current: 50mA
Load:
String of 12 LED (Power TOPLED® by
OSRAM, VF = 2.5V max. each)
The schematic diagram of the LED driver is shown in Fig.3.
We will use an aluminum electrolytic capacitor for CIN in order
to prevent interruptions of the LED current at zero crossings
of the input voltage. As a “rule of thumb”, 2~3μF per each
watt of the input power is required for CIN in this case.
Step 1. Calculating L1.
The output voltage VO = 12 · VF = 30V (max.). Use equation
(1) assuming a 30% peak-to-peak ripple.
L1 = (30V • 10.5µs) / (0.3 • 50mA) = 21mH
Select L1 22mH, I = 60mA. Typical SRF = 270KHz. Calculate
the coil capacitance.
Step 2. Selecting D1
PSWITCH ≈ 130mW
Select D1 ES1G with VR = 400V, trr ≈ 35ns and CJ < 8.0pF.
Minimum duty ratio:
Step 3. Calculating total parasitic capacitance using (3):
DM = (0.71 • 41V) / 264V ≈ 0.11
CP = 5pF + 5pF +15pF + 8pF = 33pF
Conduction power loss:
PCOND =
0.20 • (20mA)2 • 210Ω + 0.63 • 200µA • 264V ≈ 50mW
Step 4. Calculating the leading edge spike duration using
(4) and (5):
33pF
33ns 102ns
Step 5. Estimating power dissipation in HV9925 at 135VAC
using (6), (7) and (9)
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7
HV9925
Switching power loss:
10.5µs
Conduction power loss:
(
80kHz
PSWITCH =
(33pF • (135V)2 + 135V • √2 x 100mA • 35ns) • 80kHz
2
PSWITCH ≈ 78mW
PCOND = 170mW
Total power dissipation in HV9925:
PTOTAL = 78mW + 170mW = 248mW
Step 6. Selecting input capacitor CIN
Minimum duty ratio:
DM = 30V / (135V • √2) ≈ 0.16
Output Power = 30V • 50mA = 1.5W
Select CIN 3.3µF, 250V.
Figure 2. Universal 85-264VAC LED Lamp Driver
(IO = 20mA, VO = 50V) from Example 1
Figure 3. 85-135VAC LED Lamp Driver with PWM Dimming
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8
)
HV9925
Figure 4. Switching Waveforms. CH1: VRSENSE, CH2: VDRAIN
Figure 5. Switch-On Transition – Leading Edge Spike.
CH1: VRSENSE, CH2: VDRAIN
Figure 6. PWM Dimming – Rising Edge. CH4: 10×IOUT
Figure 7. PWM Dimming – Falling Edge. CH4: 10×IOUT
Pin Description
Pin # Function Description
1
RSENSE Source terminal of the output switching MOSFET provided for current sense resistor connection.
2
GND
3
PWMD
4
VDD
5
NC
Common connection for all circuits.
PWM Dimming input to the IC.
Power supply pin for internal control circuits. Bypass this pin with a 0.1uF low impedance capacitor.
No connection.
6
7
DRAIN
Drain terminal of the output switching MOSFET and a linear regulator input.
8
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9
HV9925
8-Lead SOIC (Narrow Body w/Heat Slug) Package Outline (SG)
4.90x3.90mm body, 1.70mm height (max), 1.27mm pitch
D1
D
8
8
Exposed
Thermal
Pad Zone
E2
E
E1
Note 1
(Index Area
D/2 x E1/2)
1
1
Top View
Bottom View
A
θ1
View B
h
h
A
A2
Note 1
Seating
Plane
e
A1
b
L1
A
Side View
View A - A
L
L2
Gauge
Plane
θ
Seating
Plane
View B
Notes:
1. This chamfer feature is optional. If it is not present, then a Pin 1 identifier must be located in the index area indicated. The Pin 1 Identifier can be:
a molded mark/identifier; an embedded metal marker; or a printed indicator.
Symbol
MIN
Dimension
NOM
(mm)
MAX
A
A1
A2
b
1.25*
0.00
1.25
0.31
-
-
-
-
1.70
0.15
1.55*
0.51
D
D1
4.80* 3.30
4.90
E
†
-
5.00* 3.81
E2
5.80* 3.80* 2.29
6.00
†
E1
3.90
e
†
-
6.20* 4.00* 2.79
†
1.27
BSC
h
L
0.25
0.40
-
-
0.50
1.27
L1
1.04
REF
L2
0.25
BSC
θ
θ1
0
5O
O
-
-
8
15O
O
JEDEC Registration MS-012, Variation BA, Issue E, Sept. 2005.
* This dimension is not specified in the original JEDEC drawing. The value listed is for reference only.
† This dimension is a non-JEDEC dimension.
Drawings not to scale.
Supertex Doc. #: DSPD-8SOSG, Version C090408.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline
information go to http://www.supertex.com/packaging.html.)
Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an
adequate “product liability indemnification insurance agreement.” Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the
replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications
are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http//www.supertex.com.
©2008
Doc.# DSFP-HV9925
A091708
All rights reserved. Unauthorized use or reproduction is prohibited.
10
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Tel: 408-222-8888
www.supertex.com