VIPer0P Zero-power off-line high voltage converter Datasheet - production data Figure 1: Basic application schematic Embedded E/A with 1.2 V reference and separate ground for easy negative voltage setting Protections with automatic restart: overload/short circuit (OLP), max. duty cycle counter, VCC clamp Pulse-skip protection to prevent fluxrunaway Embedded thermal shutdown Built in soft start for improved system reliability Applications Description Features Smart stand-by architecture using the zero-power mode (ZPM) ZPM management by MCU easily realizable 800 V avalanche-rugged power MOSFET allowing ultra wide VAC input range to be covered Embedded HV startup and sense-FET Current mode PWM controller Drain current limit protection (OCP) Wide supply voltage range: 4.5 V to 30 V Self-supply option allows to remove the auxiliary winding or bias components Minimized system input power consumption: Less than 4 mW @ 230 VAC in ZPM Less than 10 mW @ 230 VAC in no-load condition Less than 400 mW @ 230 VAC with 250 mW load Jittered switching frequency reduces the EMI filter cost 60 kHz ±7% (type L) 120 kHz ±7% (type H) April 2016 SMPS for home appliances, home automation, industrial, lighting and consumers The device is a high-voltage converter that smartly integrates an 800 V avalanche rugged power MOSFET with PWM current-mode control. The power MOSFET with 800 V breakdown voltage allows extended input voltage range to be applied, as well as to reduce the size of the DRAIN snubber circuit. This IC is capable of meeting the most stringent energy-saving standards as it has very low consumption and operates in pulse frequency modulation under light load. The zero-power mode (ZPM) feature enables the IC to work in an idle state, where the system is totally shutdown. An MCU can be easily connected to the IC for smart ZPM management and it can be supplied by the IC itself during the idle state. The design of flyback, buck and buck boost converters is supported. The integrated HV startup, sense FET, error amplifier and oscillator with jitter allow a complete application to be designed with a minimum component count. In flyback non isolated topology, a negative output voltage is easily set thanks to the integrated error amplifier with separate ground. DocID028423 Rev 2 This is information on a product in full production. 1/36 www.st.com Contents VIPer0P Contents 1 Pin setting ........................................................................................ 5 2 Electrical and thermal ratings ........................................................ 7 2.1 Electrical characteristics .................................................................... 8 3 Typical electrical characteristics.................................................. 12 4 General description ....................................................................... 16 5 6 4.1 Block diagram ................................................................................. 16 4.2 Typical power capability .................................................................. 16 4.3 Primary MOSFET ............................................................................ 16 4.4 High voltage startup ........................................................................ 17 4.5 Soft startup ...................................................................................... 18 4.6 Oscillator ......................................................................................... 19 4.7 Pulse skipping ................................................................................. 19 4.8 Direct feedback ............................................................................... 20 4.9 Secondary feedback ....................................................................... 21 4.10 Pulse frequency modulation ............................................................ 21 4.11 Zero-power mode ............................................................................ 21 4.12 Overload protection (OLP) .............................................................. 23 4.13 Max. duty cycle counter protection .................................................. 23 4.14 VCC clamp protection ..................................................................... 24 4.15 Thermal shutdown ........................................................................... 24 Application information ................................................................ 25 5.1 Typical schematics .......................................................................... 25 5.2 Example of ZPM management using MCU ..................................... 28 5.3 Energy saving performances........................................................... 28 5.4 Layout guidelines and design recommendations ............................ 29 Package information ..................................................................... 32 6.1 SO16N package information ........................................................... 32 7 Ordering information..................................................................... 34 8 Revision history ............................................................................ 35 2/36 DocID028423 Rev 2 VIPer0P List of tables List of tables Table 1: Pin description .............................................................................................................................. 5 Table 2: Absolute maximum ratings ........................................................................................................... 7 Table 3: Thermal data ................................................................................................................................. 7 Table 4: Avalanche characteristics ............................................................................................................. 8 Table 5: Power section ............................................................................................................................... 8 Table 6: Supply section............................................................................................................................... 8 Table 7: Controller section ........................................................................................................................ 10 Table 8: Typical power .............................................................................................................................. 16 Table 9: Power supply efficiency, VOUT = 12 V ......................................................................................... 28 Table 10: Input power consumption .......................................................................................................... 29 Table 11: SO16N mechanical data ........................................................................................................... 33 Table 12: Order codes .............................................................................................................................. 34 Table 13: Document revision history ........................................................................................................ 35 DocID028423 Rev 2 3/36 List of figures VIPer0P List of figures Figure 1: Basic application schematic ........................................................................................................ 1 Figure 2: Connection diagram .................................................................................................................... 5 Figure 3: IDLIM vs TJ ................................................................................................................................... 12 Figure 4: ION vs VON ................................................................................................................................... 12 Figure 5: FOSC vs TJ................................................................................................................................... 12 Figure 6: VHV_START vs TJ ........................................................................................................................... 12 Figure 7: VFB_REF vs TJ ............................................................................................................................... 12 Figure 8: Quiescent current Iq vs TJ .......................................................................................................... 12 Figure 9: Operating current ICC vs TJ ........................................................................................................ 13 Figure 10: ICOMP vs TJ ................................................................................................................................ 13 Figure 11: ICH1 vs TJ .................................................................................................................................. 13 Figure 12: ICH1 vs VDRAIN ............................................................................................................................ 13 Figure 13: ICH2 vs TJ .................................................................................................................................. 13 Figure 14: ICH2 vs VDRAIN ............................................................................................................................ 13 Figure 15: ICH3 vs TJ .................................................................................................................................. 14 Figure 16: ICH3 vs VDRAIN ............................................................................................................................ 14 Figure 17: GM vs TJ ................................................................................................................................... 14 Figure 18: RDS(on) vs TJ .............................................................................................................................. 14 Figure 19: Static drain source on resistance ............................................................................................ 14 Figure 20: Output characteristic ................................................................................................................ 14 Figure 21: VBVDSS vs TJ ............................................................................................................................. 15 Figure 22: Max avalache energy vs T J ..................................................................................................... 15 Figure 23: SOA SO16N package .............................................................................................................. 15 Figure 24: Block diagram .......................................................................................................................... 16 Figure 25: IC supply modes: self-supply and external supply .................................................................. 17 Figure 26: Power-ON and power-OFF...................................................................................................... 18 Figure 27: Soft startup .............................................................................................................................. 19 Figure 28: Pulse skipping during start-up for FOSC = 60 kHz .................................................................... 20 Figure 29: ZPM managed in mixed mode................................................................................................. 22 Figure 30: ZPM fully managed by MCU .................................................................................................... 22 Figure 31: Overload condition ................................................................................................................... 23 Figure 32: Thermal shutdown timing diagram .......................................................................................... 24 Figure 33: Flyback converter (non-isolated) ............................................................................................. 25 Figure 34: Negative output flyback converter (non-isolated) .................................................................... 25 Figure 35: Isolated flyback converter with secondary feedback ............................................................... 26 Figure 36: Primary side regulation isolated flyback converter .................................................................. 26 Figure 37: Buck converter (positive output) .............................................................................................. 27 Figure 38: Buck-boost converter (negative output) .................................................................................. 27 Figure 39: Example of interfacing the VIPer0P to a MCU supplied from a negative rail .......................... 28 Figure 40: PIN versus VIN in ZPM and no load .......................................................................................... 29 Figure 41: PIN versus VIN in light load ....................................................................................................... 29 Figure 42: Recommended routing for flyback converter ........................................................................... 31 Figure 43: Recommended routing for buck converter .............................................................................. 31 Figure 44: SO16N package outline ........................................................................................................... 32 4/36 DocID028423 Rev 2 VIPer0P 1 Pin setting Pin setting Figure 2: Connection diagram DRAIN PGND EAGND VIPer0P DRAIN VCC DRAIN SGND DRAIN FB N.C. COMP N.C. ON N.C. OFF N.C. GIPD210420151108MT The PCB copper area for heat dissipation has to be provided under the DRAIN pins. Table 1: Pin description SO16N Name Function 1 PGND Power ground and MOSFET source. The pulsed current flowing through the Power MOSFET must be closed on this pin. The pin must be connected to the same ground plan of SGND with the shortest track. EAGND Error amplifier ground reference. In case of non-isolated flyback converter with negative output voltage, this pin can be connected directly to the negative rail. Otherwise, in case of positive output voltage, the pin must be shorted to SGND. 2 3 VCC 4 SGND 5 6 FB COMP Controller supply. An external storage capacitor has to be connected across this pin and SGND. The pin, internally connected to the high-voltage current source, provides the VCC capacitor charging current at startup and, if selfsupply mode is selected, also during steady-state operation. A small bypass capacitor (0.1 μF typ.) in parallel, placed as close as possible to the IC, is also recommended, for noise filtering purpose. Signal ground. All of the groundings of bias components must be tied to a trace going to this pin and kept separate from the pulsed current return. Direct feedback. It is the inverting input of the internal transconductance E/A, which is internally referenced to 1.2 V with respect to EAGND. In case of nonisolated converter, the output voltage information is directly fed into the pin through a voltage divider. In case of primary regulation, the FB voltage divider is connected to the VCC. The E/A is disabled soldering FB to EAGND. Compensation. It is the output of the internal E/A. A compensation network is placed between this pin and SGND to achieve stability and good dynamic performance of the control loop. In case of secondary feedback, the internal E/A must be disabled and the COMP directly driven by the optocoupler to control the DRAIN peak current setpoint. DocID028423 Rev 2 5/36 Pin setting VIPer0P SO16N Name Function 7 ON ZPM exit. When the device is in ZPM, the IC is reactivated by forcing this pin to SGND for a debounce time, tDEB_ON. Due to the extremely low level of energy available while in ZPM, the pin can be noise sensitive. A film-type bypass capacitor from the pin to SGND is therefore recommended in a noisy environment to prevent improper startup of the device. An internal pull-up resistor keeps the pin voltage at VON level during normal operation. 8 OFF ZPM enter. To enter ZPM this pin has to be forced to SGND, for a debounce time tDEB_OFF. An internal pull-up resistor keeps the pin voltage at VOFF level during normal operation. 9 to 12 N.C. These pins are not internally connected and must be left floating in order to get a safe clearance distance. 13 to 16 6/36 DRAIN MOSFET drain. The internal high-voltage current source sinks current from this pin to charge the VCC capacitor at startup and during steady-state operation. These pins are mechanically connected to the internal metal PAD of the MOSFET in order to facilitate heat dissipation. On the PCB, some copper area must be placed under these pins in order to decrease the total junctionto-ambient thermal resistance thus facilitating the power dissipation. DocID028423 Rev 2 VIPer0P 2 Electrical and thermal ratings Electrical and thermal ratings Table 2: Absolute maximum ratings Parameter (1)(2) Symbol Pin VDS 13 to 16 Drain-to-source (ground) voltage IDRAIN 13 to 16 Pulsed drain current (pulse-width limited by SOA) VEAGND 2 VCC 3 ICC 3 VFB 5 VCOMP 6 VON 7 VOFF 8 PTOT Min. Max. Unit -0.3 800 V 2 A 0.3 V 0.3 V -35 EAGND voltage (referred to VCC) (3) EAGND voltage (referred to SGND) VCC voltage (referred to EAGND) -0.3 VCC voltage (referred to SGND) -0.3 35 VCC internal Zener current FB voltage (referred to EAGND) Tj V 35 V 30 mA 5 -0.3 (3) V FB voltage (referred to VCC) -35 0.3 V COMP voltage (referred to SGND) -0.3 5 (3) V COMP voltage (referred to VCC) -35 0.3 V ON voltage (referred to SGND) -0.3 5.5 V ON voltage (referred to VCC) -35 0.3 V OFF voltage (referred to SGND) -0.3 5.5 V OFF voltage (referred to VCC) -35 0.3 V 1 W Power dissipation @ Tamb < 50 °C TSTG (3) Junction temperature operating range -40 150 °C Storage temperature -55 150 °C Notes: (1)Stresses beyond those listed absolute maximum ratings may cause permanent damage to the device. (2)Exposure (3)Voltage to absolute-maximum-rated conditions for extended periods may affect the device reliability. is internally limited. Table 3: Thermal data Max. value Symbol Parameter Unit SO16N RthJP Thermal resistance junction-pin (dissipated power 1 W) RthJA (1) 35 Thermal resistance junction-ambient (dissipated power 1 W) Thermal resistance junction-ambient (dissipated power 1 W) 110 (2) °C/W 80 Notes: (1)Derived (2)When by characterization. mounted on a standard single side FR4 board with 100 mm² (0.1552 inch) of Cu (35 µm thick). DocID028423 Rev 2 7/36 Electrical and thermal ratings VIPer0P Table 4: Avalanche characteristics Symbol Conditions Parameter Min. Typ. Max. Unit IAR Avalanche current Repetitive and non-repetitive. Pulse-width limited by TJmax 0.8 A EAS Single pulse avalanche energy (1) IAS = IAR; VDS = 100 V; Starting TJ = 25 °C 0.5 mJ Max. Unit Notes: (1)Parameter 2.1 derived by characterization. Electrical characteristics Tj = -40 to 125 °C, VCC = 9 V (unless otherwise specified). Table 5: Power section Symbol Parameter Test conditions Min. Typ. Breakdown voltage IDRAIN = 1 mA, VCOMP = SGND, TJ = 25 °C Drain-Source leakage current VDS = 400 V, VCOMP = SGND, TJ = 25 °C 1 RDS(on) Static drain-source ON-resistance IDRAIN = 200 mA, TJ = 25 °C 20 IDRAIN = 200 mA, TJ = 125 °C 40 COSS EQ Equivalent output capacitance VGS = 0; VDS = 0 to 640 V, TJ = 25 °C VBVDSS IDSS 800 V 10 µA Ω pF Table 6: Supply section Symbol Parameter Test conditions Min. Typ. Max. Unit High voltage startup current source VBVDSS_SU Breakdown voltage of startup MOSFET 800 VHV_START Drain-Source start up voltage 40 80 V MΩ RG Startup resistor VFB > VFB_REF, VDRAIN = 400 V, VDRAIN = 600 V 28 34 40 ICH1 VCC charging current at startup VFB > VFB_REF, VDRAIN = 100 V, VCC = 0 V, TJ = 25 °C 0.7 1 1.3 ICH2 VCC charging current at startup VFB > VFB_REF, VDRAIN = 100 V, VCC = 1 V, TJ = 25 °C 2.3 3.2 4.1 Max. VCC charging current in self-supply VFB > VFB_REF, VDRAIN = 100 V, VCC = 6 V, TJ = 25 °C 6.4 7.8 9.2 ICH3 8/36 V (1) DocID028423 Rev 2 mA VIPer0P Electrical and thermal ratings Symbol Parameter Test conditions Min. Typ. Max. Unit 30 V IC supply and consumptions referred to SGND, VEAGND = 0 VCC Operating voltage range referred to EAGND, VEAGND < 0 4.5 VCCclamp Clamp voltage ICC = Iclamp_max 30 32.5 35 V Iclamp max Clamp shutdown current VCC > VCCclamp 29 35 41 mA tclamp max Clamp time before shutdown 5 VCCon VCC startup threshold VFB = 1.2 V,VDRAIN = 400 V VCSon HV current source turn-on threshold VCC falling VCCoff UVLO VFB = 1.2 V, VDRAIN = 400 V Quiescent current Not switching, VFB > VFB_REF Quiescent current in ZPM Not switching, VFB > VFB_REF, VDRAIN = 325 V Iq Iq_ZPM ICC Operating supply current, switching ms 7.5 8 8.5 V 4 4.25 4.5 V 3.75 4 4.25 V 0.25 0.35 mA 20 µA FOSC = 60 kHz, VDS = 150 V, VCOMP =1.2 V 0.6 0.9 1.2 FOSC = 120 kHz, VDS = 150 V, VCOMP =1.2 V 0.9 1.2 1.5 mA Notes: (1)Current supplied only during the main MOSFET OFF time. DocID028423 Rev 2 9/36 Electrical and thermal ratings VIPer0P Table 7: Controller section Symbol Parameter Test conditions Min. Typ. Max. Unit 0 V E/A VEAGND E/A ground reference voltage Referred to SGND VFB_REF E/A reference voltage Referred to EAGND 1.175 1.2 1.225 V VFB_DIS E/A disable voltage Referred to EAGND 150 250 350 mV 0.5 1 1.5 µA IFB PULL UP Pull-up current -20 GM Trans conductance VCOMP = 1.5 V, VFB > VFB_REF 300 550 700 µA/V ICOMP1 Max. source current VFB = 0.5 V, VCOMP = 1.5 V 75 100 125 µA ICOMP2 Max. sink current VFB = 2 V, VCOMP = 1.5 V 75 100 125 µA Dynamic resistance VCOMP = 2.7 V, VFB = EAGND 55 65 75 kΩ VCOMPH Current limitation threshold Referred to SGND 2.65 3.2 3.75 V VCOMPL PFM threshold Referred to SGND 0.7 0.9 1.1 V TJ = 25 °C 380 400 420 mA +10% A2·kHz RCOMP(DYN) OLP and timing IDLIM I2 f IDLIM_PFM tOVL tOVL_MAX tSS Drain current limitation VIPER0PL Power coefficient VIPER0PH -10% 9.6 19.2 Drain current limitation at light load TJ = 25 °C VCOMP = VCOMPL (1) 60 95 130 mA Overload delay time FOSC = 60 kHz (VIPER0PL) FOSC = 120 kHz (VIPER0PH) 45 50 55 ms VIPER0PL FOSC = FOSC_MIN 180 200 220 VIPER0PH FOSC = FOSC_MIN 360 Max. overload delay time ms Soft-start time 400 440 8 tON_MIN Minimum turn-on time tRESTART Restart time after fault VCC = 9 V, VCOMP = 1 V, VFB = VFB_REF 230 ms 350 1 ns s ZPM VOFFth ZPM entering threshold During normal operation VCC = 7 V 0.75 VOFF Operating voltage level Pin floating 4.1 ROFF Pull-up resistor on OFF pin tDEB_OFF 10/36 OFF debounce time DocID028423 Rev 2 32 1 1.25 V 4.6 V 41 50 kΩ 10 16 ms VIPer0P Electrical and thermal ratings Symbol Parameter Test conditions Min. Typ. Max. Unit 1 1.25 V 4.6 V 41 50 kΩ 20 35 µs VONth ZPM exiting threshold During ZPM 0.75 VON Operating voltage level Pin floating 4.1 RON Pull-up resistor on ON pin tDEB_ON (3) ON debounce time 32 Oscillator FOSC Switching frequency FOSC_MIN Minimum switching frequency VIPER0PL 54 60 66 VIPER0PH 108 120 132 (2) 13.5 15 16.5 kHz kHz FD Modulation depht ±7% FOSC kHz FM Modulation frequency 260 Hz DMAX Max. duty cycle 70 80 % Thermal shutdown TSD Thermal shutdown temperature (3) 150 160 °C Notes: (1)See Section 5.10: "Pulse frequency modulation". (2)See Section 5.7: "Pulse skipping " . (3)Parameter assured by design, characterization, and statistical correlation. DocID028423 Rev 2 11/36 Typical electrical characteristics 3 VIPer0P Typical electrical characteristics Figure 4: ION vs VON Figure 3: IDLIM vs TJ ION (µA) IDLIM/(IDLIM@25°C) 30 1.1 25 20 15 1 10 5 0.9 0 -50 0 50 Tj(°C) 100 150 2.75 3.25 3.75 VON (V) GIPD160720151000MT 4.25 GIPD160720151001MT Figure 6: VHV_START vs TJ VHV_START/(VHV_START@25°C) Figure 5: FOSC vs TJ FOSC /(FOSC @25°C) 1.05 1.5 1.25 1 1 0.75 0.95 0.5 -50 0 50 Tj(°C) 100 150 -50 0 50 Tj(°C) GIPD160720151002MT Figure 7: VFB_REF vs TJ 100 150 GIPD160720151004MT Figure 8: Quiescent current Iq vs TJ Iq /(Iq @25°C) VFB_REF / (VFB_REF@ 25°C) 1.2 1.05 1.1 1 1 0.9 0.95 0.8 -50 0 50 Tj(°C) 12/36 100 150 -50 GIPD160720151005MT DocID028423 Rev 2 0 50 Tj(°C) 100 150 GIPD160720151006MT VIPer0P Typical electrical characteristics Figure 9: Operating current ICC vs TJ ICC/(ICC@25°C) Figure 10: ICOMP vs TJ ICOMP/(ICOMP@25°C) 1.1 1.1 1 1 0.9 0.9 -50 0 50 Tj(°C) 100 -50 150 50 GIPD160720151007MT ICH1/(ICH1@25°C) 100 Tj(°C) Figure 11: ICH1 vs TJ 1.5 0 1.2 1.25 1.1 1 1 0.75 0.9 150 GIPD160720151015MT Figure 12: ICH1 vs VDRAIN ICH1/(ICH1@VDRAIN=100V) 0.8 0.5 -50 0 50 Tj(°C) 100 50 150 100 150 200 250 VDRAIN [V] GIPD160720151008MT 300 350 400 GIPD160720151009MT Figure 14: ICH2 vs VDRAIN Figure 13: ICH2 vs TJ ICH2/(ICH2@25°C) 1.2 1.2 ICH2/(ICH2@VDRAIN=100V) 1.1 1 1 0.9 0.8 0.8 -50 0 50 Tj(°C) 100 150 50 GIPD160720151010MT DocID028423 Rev 2 100 150 200 250 VDRAIN [V] 300 350 400 GIPD160720151011MT 13/36 Typical electrical characteristics VIPer0P Figure 15: ICH3 vs TJ ICH3/(ICH3@25°C) Figure 16: ICH3 vs VDRAIN ICH3/(ICH3@VDRAIN=100V) 1.2 1.2 1.1 1 1 0.9 0.8 0.8 -50 0 50 100 Tj(°C) 50 150 150 200 250 VDRAIN [V] GIPD160720151012MT Figure 17: GM vs TJ 300 350 400 GIPD160720151013MT Figure 18: RDS(on) vs TJ RDS(on)/(RDS(on)@25°C) GM/(GM@25°C) 1.2 100 2.5 1 1.5 0.8 0.5 -50 0 50 100 Tj(°C) 150 -50 GIPD160720151014MT Figure 19: Static drain source on resistance 1.2 R DS(on) /(R DS(on) @ I DR AIN =20 0m A) 1.1 1 T= 25°C 0.9 0.8 0 100 200 300 IDRAIN [m A] 14/36 400 500 GIPD160720151017MT DocID028423 Rev 2 0 50 Tj(°C) 100 150 GIPD160720151016MT Figure 20: Output characteristic VIPer0P Typical electrical characteristics Figure 21: VBVDSS vs TJ VBVDSS/(VBVDSS@25°C) Figure 22: Max avalache energy vs TJ 1.2 1.1 EAS/(EAS@ 25°C) 1 0.8 1 0.6 0.4 0.2 0.9 0 -50 0 50 100 Tj(°C) 150 0 15 30 45 60 75 Tj (°C) GIPD160720151019MT 90 105 120 150 135 GIPD200820151330MT Figure 23: SOA SO16N package IDRAIN [A] 1.0E+01 1.0E+00 10µs a is are this ) n i (on n ax R DS ratio Ope d by M te limi 1.0E-01 100µs 1ms 10ms 1.0E-02 1.0E-03 Tj=150°C Tc=25°C Single pulse 1.0E-04 1.0E-05 0 1 10 100 1,000 VD-S [V] GIPD160720151020MT DocID028423 Rev 2 15/36 General description VIPer0P 4 General description 4.1 Block diagram Figure 24: Block diagram 4.2 Typical power capability Table 8: Typical power Vin: 230 VAC Adapter (1) Vin: 85-265 VAC Open frame 10 W (2) 12 W Adapter (1) Open frame (2) 6W 7W Notes: (1)Typical continuous power in non-ventilated enclosed adapter measured at 50 °C ambient. (2)Maximum 4.3 practical continuous power in an open frame design at 50 °C ambient, with adequate heatsinking. Primary MOSFET The primary switch is implemented with an avalanche rugged N-channel MOSFET with minimum breakdown voltage 800 V, VBVDSS, and maximum on-resistance of 20 Ω, RDS(on). The sense-FET is embedded and it allows a virtually lossless current sensing. The startupMOSFET is embedded and it allows the HV voltage startup operation. The MOSFET gate driver controls the gate current during both turn-on and turn-off in order to minimize EMI. 16/36 DocID028423 Rev 2 VIPer0P 4.4 General description High voltage startup The embedded high voltage startup includes both the 800 V startup FET, whose gate is biased through the resistor RG, and the switchable HV current source, delivering the current IHV. The major portion of IHV, (ICH), charges the capacitor connected to VCC. A minor portion is sunk by the controller block. At start up, as the voltage across the DRAIN pin exceeds the VHV_START threshold, the HV current source is turned on, charging linearly the Cs capacitor. At the very beginning of the start-up, when Cs is fully discharged, the charging current is low (I CH1 = 1 mA typ.) in order to avoid IC damaging in case VCC is accidentally shorted to SGND. As VCC exceeds 1 V, ICH is increased to ICH2 (3.2 mA, typ.) in order to speed up the charging of CS. As VCC reaches the startup threshold VCCon (8 V typ.) the chip starts operating, the primary MOSFET is enabled to switch, the HV current source is disabled and the device is powered by the energy stored in the CS capacitor. In steady-state the IC supports two different kind of supplies: self-supply and external supply, as shown in Figure 25: "IC supply modes: self-supply and external supply". Figure 25: IC supply modes: self-supply and external supply External supply Self -supply VAux V OUT VCC ICH VCC ICH VCC ICH CS CS from the output CS from auxiliary winding GIPD160720151024MT In self-supply only a capacitor CS is connected to the VCC and the device is supplied by the energy stored in CS. After the IC startup, due to its internal consumption, the V CC decays to VCSon (4.25 V, typ.) and the HV current source is turned on delivering the current ICH3 (7.8 mA typ.) until VCC is recharged to VCCon. The HV current source is reactivated when VCC decays to VCSon again. The ICH3 is supplied during the switching OFF time only. In external supply the HV current source is always kept off by maintaining the V CC above VCSon. This can be obtained through a transformer auxiliary winding or a connection from the output, the latter only in case of non-isolated topology. In this case the residual consumption is given by the power dissipated on RG, calculated as follows: Pd 2 VINDC RG DocID028423 Rev 2 17/36 General description VIPer0P At the nominal input voltage, 230 VAC, the typical consumption (RG = 34 MΩ) is 3.2 mW and the worst-case consumption (RG = 28 MΩ) is 3.9 mW. When the IC is disconnected from the mains, or there is a mains interruption, for some time the converter will keep on working, powered by the energy stored in the input bulk capacitor. When this is discharged below a critical value, the converter is no longer able to keep the output voltage regulated. During the power down, when the DRAIN voltage becomes too low, the HV current source (IHV) remains off and the IC is stopped as soon as the VCC drops below the UVLO threshold, VCCoff. Figure 26: Power-ON and power-OFF 4.5 Soft startup The internal soft-start function of VIPer0P progressively increases the cycle-by-cycle current limitation set point from zero up to IDLIM in 8 steps of 50 mA each. The soft-start time, tSS, is internally set at 8 ms. This function is activated at any attempt of converter start-up and at any restart after a fault event. The feature protects the system at the startup when the output load presents itself like a short-circuit and the converter would work at its maximum drain current limitation. 18/36 DocID028423 Rev 2 VIPer0P General description Figure 27: Soft startup 4.6 Oscillator The IC embeds a fixed frequency oscillator with jittering feature. The switching frequency is modulated by approximately ±7% kHz FOSC at 260 Hz rate. The purpose of the jittering is to get a spread-spectrum action that distributes the energy of each harmonic of the switching frequency over a number of frequency bands, having the same energy on the whole but smaller amplitudes. This helps to reduce the conducted emissions, especially when measured with the average detection method or, which is the same, to pass the EMI tests with an input filter of smaller size with respect to the one that should be needed in absence of jittering feature. Two options with different switching frequencies, F OSC, are available: 60 kHz (L type) and 120 kHz (H type). 4.7 Pulse skipping The IC embeds a pulse skip circuit that operates in the following way: each time the DRAIN peak current exceeds IDLIM level within tON_MIN, the switching cycle is skipped. The cycles can be skipped until the minimum switching frequency is reached, FOSC_MIN (15 kHz, typ.). each time the DRAIN peak current does not exceed I DLIM within tON_MIN, a switching cycle is restored. The cycles can be restored until the nominal switching frequency is reached, FOSC (60 or 120 kHz, typ.) If the converter is indefinitely operated at FOSC_MIN, the IC is turned off after the time tOVL_MAX (200 ms or 400 ms typ., depending on FOSC) and then automatically restarted with soft start phase, after the time tRESTART (1 sec, typ.). The protection is intended in order to avoid the so called "flux runaway" condition often present at converter startup or in case of a dead-short at converter output and due to the fact that the primary MOSFET, which is turned on by the internal oscillator, cannot be turned off before the minimum on-time. DocID028423 Rev 2 19/36 General description VIPer0P During the on-time, the inductor is charged through the input voltage and if it cannot be discharged by the same amount during the off-time, in every switching cycle there is a net increase of the average inductor current, that can reach dangerously high values until the output capacitor is not charged enough to ensure the inductor discharge rate needed for the volt-second balance. This condition is common at converter startup, because of the low output voltage. In the following Figure 28: "Pulse skipping during start-up for FOSC = 60 kHz" the effect of pulse skipping feature on the DRAIN peak current shape is shown (solid line), compared with the DRAIN peak current shape when pulse skipping feature is not implemented (dashed line). Providing more time for cycle-by-cycle inductor discharge when needed, this feature is effective in keeping low the maximum DRAIN peak current avoiding the flux runaway condition. Figure 28: Pulse skipping during start-up for FOSC = 60 kHz 4.8 Direct feedback The IC embeds a transconductance type error amplifier (E/A) whose inverting input, ground reference and output are FB, EAGND and COMP, respectively. The internal reference voltage of the E/A is VFB_REF (1.2 V typical value referred to EAGND). In non-isolated topologies this makes it possible to tightly regulate positive output voltages through a simple voltage divider applied among the output voltage terminal, FB and EAGND, and soldering SGND to EAGND. Since EAGND can float down to -12.5 V with respect to the ground of the IC (SGND), negative output voltages can be regulated as well, connecting EAGND to the negative rail, and the voltage divider among FB, EAGND and SGND, as shown in Figure 34: "Negative output flyback converter (non-isolated)". The E/A output is scaled down and fed into the PWM comparator, where it is compared to the voltage across the sense resistor in series to the sense-FET, thus setting the cycle-bycycle drain current limitation. An R-C network connected on the output of the E/A (COMP) is usually used to stabilize the overall control loop. 20/36 DocID028423 Rev 2 VIPer0P General description The FB is provided with an internal pull-up to prevent a wrong IC behavior when the pin is accidentally left floating. 4.9 Secondary feedback When a secondary feedback is required, the internal E/A has to be disabled shorting FB to EAGND (VFB < VFB_DIS). With this setting COMP is internally connected to a pre-regulated voltage through the pull-up resistor RCOMP(DYN), (65 kΩ, typ.) and the voltage across COMP is set by the current sunk. This allows the output voltage value to be set through an external error amplifier (TL431 or similar) placed on the secondary side, whose error signal is used to set the DRAIN peak current setpoint corresponding to the output power demand. If isolation is required, the error signal must be transferred through an optocoupler, with the phototransistor collector connected across COMP and SGND. 4.10 Pulse frequency modulation If the output load is decreased, the feedback loop reacts lowering the V COMP voltage, which reduces the DRAIN peak current setpoint, down to the minimum value of IDLIM_PFM when the VCOMPL threshold is reached. If the load is further decreased, the DRAIN peak current value is maintained at I DLIM_PFM and some PWM cycles are skipped. This mode of operation is referred to as “pulse frequency modulation” (PFM), the number of the skipped cycles depends on the balance between the output power demand and the power transferred from the input. The result is an equivalent switching frequency which can go down to some hundreds Hz, thus reducing all the frequency-related losses. This kind of operation, together with the extremely low IC quiescent current, allows very low input power consumption in no load and light load, while the low DRAIN peak current value, IDLIM_PFM, prevents any audible noise which could arise from low switching frequency values. When the load is increased, VCOMP increases and PFM is exited. VCOMP reaches its maximum at VCOMPH and corresponding to that value, the DRAIN current limitation (I DLIM) is reached. 4.11 Zero-power mode The zero-power mode (ZPM) is a special idle state of VIPer0P, characterized by the following features: there is no switching activity, then neither voltage nor power, available at the output the HV current source charges VCC at 13 V and does not perform its usual functions all IC circuits, except the ones needed to exit ZPM, are turned off, reducing the controller consumption to very low values The IC enters ZPM if OFF is forced to SGND for more than tDEB_OFF (10 ms, typ.), the IC exits ZPM if ON is forced to SGND for a more than tDEB_ON (20 μs, typ.). The ZPM can be managed manually or by a microcontroller (MCU) or in mixed mode. In case of mixed ZPM management (see Figure 29: "ZPM managed in mixed mode") the MCU supervising the operation of the appliance shuts down the SMPS by pulling low OFF through one of its GPIOs, cutting also its own supply voltage. The restart is commanded by a pushbutton or a tactile switch pressed by the user that directly operates pin ON. For safety reasons, this switch should operate at low voltage (SELV level). The MCU wakes up after the SMPS is again up and running. This arrangement provides the minimum consumption from the power line. DocID028423 Rev 2 21/36 General description VIPer0P In case of ZPM management by MCU only (see Figure 30: "ZPM fully managed by MCU") the MCU shuts down the SMPS by pulling low OFF and wakes it up as well by pulling low ON. Two of its GPIOs are used. The MCU is powered also during ZPM using the resistive pull-up available at ON (RON, 45 kΩ typical), provided that it is rated for 3.3 V supply voltage, and equipped with an ultra-low consumption Standby Mode. Since in ZPM the device is supplied with extremely low current, it is naturally prone to pick up noise. If the device is required to work in a noisy environment, it is recommended to connect a film capacitor (tens to some hundreds pF) across ON and OFF versus SGND. If the device is disconnected from the mains or there is a mains interruption while in ZPM, the information in the logic is lost. When the input source is applied again, the IC will be restarted in normal mode. The ultimate aim of ZPM function is to enable the realization of PSUs able to comply with the European regulation 1275/2008 as far as the standby and off-mode power consumption of appliances is concerned. To meet this target a careful system-level design is required. The total input consumption is therefore reduced to the residual consumption lower than 4 mW at 230 VAC that can be rounded to zero based on the IEC62301 that sets to 10 mW the minimum accuracy of the standby power measurements. Figure 29: ZPM managed in mixed mode VAUX GPIO Active low output MCU CB OFF ON VIPer0P Power-ON GIPD280420151131MT Figure 30: ZPM fully managed by MCU 4V VAUX ON 45 kW VIPer0P CB OFF MCU GPIO Active low outputs GPIO Power-ON/OFF GIPD250820151513FSR 22/36 DocID028423 Rev 2 VIPer0P 4.12 General description Overload protection (OLP) In order to manage the overload condition the IC embeds the following main blocks: the OCP comparator to turn off the power MOSFET when the drain current reaches its limit (IDLIM), the up and down OCP counter to define the turn off delay time in case of continuous overload (tOVL = 50 ms typ.) and the timer to define the restart time after protection tripping (tRESTART = 1 sec, typ.). In case of short-circuit or overload, the control level on the inverting input of the PWM comparator is greater than the reference level fed into the inverting input of the OCP comparator. As a result, the cycle-by-cycle turn off of the power switch will be triggered by the OCP comparator instead of by the PWM comparator. Every cycle this condition is met, the OCP counter is incremented and if the fault condition persists for a time greater than tOVL (corresponding to the counter end-of-count), the protection is tripped, the PWM is disabled for tRESTART, then it resumes switching with soft-start and, if the fault is still present, it is disabled again after tOVL. The OLP management prevents that the IC could be indefinitely operated at IDLIM and the low repetition rate of the restart attempts of the converter avoids overheating the IC in case of repeated fault events. After the fault removal, the IC resumes working normally. If the fault is removed before the protection tripping (before tOVL), the tOVL-counter is decremented on a cycle-by-cycle basis down to zero and the protection is not tripped. If the fault is removed during tRESTART, the IC waits for that the tRESTART period has elapsed before resuming switching. In fault condition the VCC ranges between VCSon and VCCon levels, due to the periodical activation of the HV current source recharging the VCC capacitor. Figure 31: Overload condition 4.13 Max. duty cycle counter protection The IC embeds a max duty-cycle counter, which disables the PWM if the MOSFET is turned off by max duty cycle (70% min, 80% max) for ten consecutive switching cycles. After protection tripping, the PWM is stopped for tRESTART and then activated again with softstart phase until the fault condition is removed. In some cases (i.e. breaking of the loop) even if VCOMP is saturated high, the OLP cannot be triggered because at every switching cycle the PWM is turned off by maximum duty cycle before the DRAIN peak current can reach the IDLIM setpoint. As a result, the output voltage DocID028423 Rev 2 23/36 General description VIPer0P VOUT could increases out of control and be maintained indefinitely at much higher value than nominal one with risk for the output capacitor, the output diode and the IC itself. The max duty cycle counter protection prevents this kind of failures. 4.14 VCC clamp protection This protection can be invoked when the IC is supplied by auxiliary winding or diode from the output voltage, when an output over-voltage produces an increase of VCC. If VCC reaches the clamp level VCCclamp (30 V, min. referred to EAGND) the current injected into the pin is monitored and if it exceeds the internal threshold Iclamp_max (30 mA, typ.) for more than tclamp_max (5 ms, typ.), the PWM is disabled for tRESTART (1 sec, typ.) and then activated again with soft-start phase. The protection is disabled during the soft-start time. 4.15 Thermal shutdown If the junction temperature becomes higher than the internal threshold T SD (160 °C, typ.), the PWM is disabled. After tRESTART time, a single switching cycle is performed, during which the temperature sensor embedded in the Power MOSFET section is checked. If a junction temperature above TSD is still measured, the PWM is maintained disabled for tRESTART time, otherwise it resumes switching with soft-start phase. During tRESTART VCC is maintained between VCSon and VCCon levels by the HV current source periodical activation. Such a behavior is summarized in Figure 32: "Thermal shutdown timing diagram". Figure 32: Thermal shutdown timing diagram VCC TJ > TSD TJ < TSD VCC on VCS on IDRAIN time IDLIM IPEA K tRES TART time tRESTART tSS GIPD270420151404MT 24/36 DocID028423 Rev 2 VIPer0P Application information 5 Application information 5.1 Typical schematics Figure 33: Flyback converter (non-isolated) Figure 34: Negative output flyback converter (non-isolated) DocID028423 Rev 2 25/36 Application information VIPer0P Figure 35: Isolated flyback converter with secondary feedback Figure 36: Primary side regulation isolated flyback converter 26/36 DocID028423 Rev 2 VIPer0P Application information Figure 37: Buck converter (positive output) Figure 38: Buck-boost converter (negative output) DocID028423 Rev 2 27/36 Application information 5.2 VIPer0P Example of ZPM management using MCU Sometimes the SMPS provides a -5 V bus for instance to enable triac driving to control the motor of a washing machine. In this case, not to generate an additional +5 V bus, the ground of the MCU can be connected to the -5 V bus and its positive supply voltage to the ground of SMPS and VIPer0P. This connection requires an interface circuit realizing a level shifting to properly drive ON and OFF, like the one shown in the Figure 39: "Example of interfacing the VIPer0P to a MCU supplied from a negative rail ". During ZPM the MCU is supplied through ON, but a linear regulator is needed in between, in order to avoid that during normal operation the AMR of the MCU is exceeded. Figure 39: Example of interfacing the VIPer0P to a MCU supplied from a negative rail EAGND GND VIPer0P OFF ON 220 pF 220 pF 0V 56 kW 56 kW LDO VCC GPIO GPIO MCU GND -5 V GIPD250820151541FSR 5.3 Energy saving performances VIPer0P allows designing applications compliant with the most stringent energy saving regulations. In order to show the typical performances achievable, the active mode average efficiency and the efficiency at 10% of the rated output power of a single output flyback converter using VIPer0P have been measured and are reported in Table 9. In addition, ZPM, no-load and light load consumptions are shown in the below tables and Figure 40: "PIN versus VIN in ZPM and no load" and Figure 41: "PIN versus VIN in light load". Table 9: Power supply efficiency, VOUT = 12 V 28/36 VIN 10% output load efficiency [%] Active mode average efficiency [%] 115 VAC 78.0 80.9 230 VAC 71.1 81.0 DocID028423 Rev 2 VIPer0P Application information Table 10: Input power consumption VIN PIN in ZPM [mW] PIN @ no-load [mW] 115 VAC 0.8 6.5 230 VAC 3.3 9.0 Figure 40: PIN versus VIN in ZPM and no load P IN [ mW] 14 no load 12 ZPM 10 8 6 4 2 0 90 115 150 180 230 265 V IN [V AC ] GIPD160720151022MT Figure 41: PIN versus VIN in light load P IN [ mW] 400 350 POUT = 250 mW 300 250 200 150 POUT = 50 mW 100 50 POUT = 25 mW 0 90 115 150 180 V IN [V AC ] 230 265 GIPD160720151023MT 5.4 Layout guidelines and design recommendations A proper printed circuit board layout is essential for correct operation of any switch-mode converter and this is true for the VIPer0P as well. The main reasons to have a proper PCB layout are: Provide clean signals to the IC, ensuring good immunity against external noises and switching noises Reduce the electromagnetic interferences, both radiated and conducted, to pass more easily the EMC When designing a SMPS using VIPer0P, the following basic rules should be considered: Separating signal from power tracks: generally, traces carrying signal currents should run far from others carrying pulsed currents or with quickly swinging voltages. Signal ground traces should be connected to the IC signal ground, SGND, using a DocID028423 Rev 2 29/36 Application information VIPer0P single "star point", placed close to the IC. Power ground traces should be connected to the IC power ground, PGND. SGND and PGND are then to be connected to each other with the shortest track as possible. The compensation network should be connected to the COMP, maintaining the trace to SGND as short as possible. In case of two layer PCB, it is a good practice to route signal traces on one PCB side and power traces on the other side. Filtering sensitive pins: some crucial points of the circuit need or may need filtering. A small high-frequency bypass capacitor to SGND might be useful to get a clean bias voltage for the signal part of the IC and protect the IC itself during EFT/ESD tests. A low ESL ceramic capacitor (a few hundreds pF up to 0.1 μF) should be connected across VCC and SGND, placed as close as possible to the IC. With flyback topologies, when the auxiliary winding is used, it is suggested to connect the VCC capacitor on the auxiliary return and then to the main GND using a single track. In case of nosy environment, it is strongly recommended to filter ON and OFF with small ceramic capacitors (tens to hundreds pF) connected to SGND, in order to improve the system noise immunity. Keep power loops as confined as possible: minimize the area circumscribed by current loops where high pulsed currents flow, in order to reduce its parasitic selfinductance and the radiated electromagnetic field: this will greatly reduce the electromagnetic interferences produced by the power supply during the switching. In a flyback converter the most critical loops are: the one including the input bulk capacitor, the power switch, the power transformer, the one including the snubber, the one including the secondary winding, the output rectifier and the output capacitor. In a buck converter the most critical loop is the one including the input bulk capacitor, the power switch, the power inductor, the output capacitor and the free-wheeling diode. Reduce line lengths: any wire will act as an antenna. With the very short rise times exhibited by EFT pulses, any antenna has the capability of receiving high voltage spikes. By reducing line lengths, the level of radiated energy that is received will be reduced, and the resulting spikes from electrostatic discharges will be lower. This will also keep both resistive and inductive effects to a minimum. In particular, all of traces carrying high currents, especially if pulsed (tracks of the power loops) should be as short and fat as possible. Optimize track routing: as levels of pickup from static discharges are likely to be greater closer to the extremities of the board, it is wise to keep any sensitive lines away from these areas. Input and output lines will often need to reach the PCB edge at some stage, but they can be routed away from the edge as soon as possible where applicable. Since vias are to be considered inductive elements, it is recommended to minimize their number in the signal path and avoid them when designing the power path. Improve thermal dissipation: an adequate copper area has to be provided under the DRAIN pins as heat sink, while it is not recommended to place large copper areas on the SGND and PGND. 30/36 DocID028423 Rev 2 VIPer0P Application information Figure 42: Recommended routing for flyback converter T ~ AC Rin Din Dout Cin Vout Ccl Cout Rcl Daux GND Cs OPTO R1 VIPER0P VCC DRAIN ON CONTROL OFF COMP FB EAGND SGND PGND OPTO C1 R2 GIPD030920151537MT Figure 43: Recommended routing for buck converter ~ AC Din Rin1 Cin Daux VIPER0P VCC DRAIN R1 ON Cs D CONTROL C2 OFF COMP FB EAGND SGND R2 PGND C1 Lout Dout Vout Cout GIPD030920151538MT DocID028423 Rev 2 31/36 Package information 6 VIPer0P Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 6.1 SO16N package information Figure 44: SO16N package outline 32/36 DocID028423 Rev 2 VIPer0P Package information Table 11: SO16N mechanical data mm Dim. Min. Typ. A Max. 1.75 A1 0.1 A2 1.25 b 0.31 0.51 c 0.17 0.25 D 9.8 9.9 10 E 5.8 6 6.2 E1 3.8 3.9 4 e 0.25 1.27 h 0.25 0.5 L 0.4 1.27 k 0 8 ccc 0.1 DocID028423 Rev 2 33/36 Ordering information 7 VIPer0P Ordering information Table 12: Order codes Order code Package Packing 60 kHz ±7% VIPER0PLD Tube VIPER0PHD SO16N Tape and reel VIPER0PHDTR DocID028423 Rev 2 120 kHz ±7% 60 kHz ±7% VIPER0PLDTR 34/36 FOSC ± jitter 120 kHz ±7% VIPer0P 8 Revision history Revision history Table 13: Document revision history Date Revision Changes 18-Aug-2015 1 Initial release 12-Apr-2016 2 Updated Table 4: "Avalanche characteristics", Table 6: "Supply section" and Table 7: "Controller section". Minor text changes. DocID028423 Rev 2 35/36 VIPer0P IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved 36/36 DocID028423 Rev 2