7B991 Programmable Skew Clock Buffer (PSCB) FEATURES: DESCRIPTION: • • • • • • • Maxwell Technologies’ 7B991 Programmable Skew Clock Buffers (PSCB) offer user-selectable control over system clock functions. These multiple-output clock drivers provide the system integrator with functions necessary to optimize timing of high-performance computer systems. Eight individual drivers, arranged as four pairs of user-controllable outputs, can each drive terminated transmission lines with impedances as low as 50Ω while delivering minimal and specified output skews and full-swing logic levels. • • • • • • • • • All output pair skew < 100 ps typical (250 max.) 3.75 to 80 MHz output operation User-selectable output functions Selectable skew to 18 ns Inverted and non-inverted Operation at ½ and ¼ input frequency Operation at 2x and 4x input frequency (input as low as 3.75 MHz) Zero input to output delay 50% duty-cycle outputs Outputs drive 50Ω terminated lines Low operating current Package: 32-pin RAD-PAK® flat package Jitter < 200 ps peak-to-peak (< 25 ps RMS) Compatible with Pentium™-based processor Total dose hardness: - >100 krads (Si), depending upon space mission Excellent Single Event Effects: - SEL > 116MeV/mg/cm2 - SEUTH -3 MeV/mg/cm2 - SEU sat cross section: 1E-3/device Each output can be hardwired to one of nine delay or function configurations. Delay increments of 0.7 to 1.5 ns are determined by the operating frequency with outputs able to skew up to ± 6 time units from their nominal “zero” skew position. The completely integrated PLL allows external load and transmission line delay effects to be canceled. When this “zero delay” capability of the PSCB is combined with the selectable output skew functions, the user can create output-to-output delays of up to ±12 time units. Maxwell Technologies' patented RAD-PAK® packaging technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, RAD-PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. 2.10.03 REV 5 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com All data sheets are subject to change without notice 1 ©2003 Maxwell Technologies. All rights reserved. Memory Logic Diagram 7B991 Programmable Skew Clock Buffer (PSCB) TABLE 1. 7B991 PINOUT DESCRIPTIONS SYMBOL I/O DESCRIPTION 1 REF I Reference frequency input supplies the frequency and timing against which all functional variation is measured. 17 FB I PLL feedback (typically connected to one of the eight outputs) 3 FS I Three-level frequency range select. See Table 9 . 26, 27 1F0, 1F1 I Three-level function select inputs for output pair 1 (1Q0, 1Q1). See Table 9. 29, 30 2F0, 2F1 I Three-level function select inputs for output pair 2 (2Q0, 2Q1). See Table 9. 4, 5 3F0, 3F1 I Three-level function select inputs for output pair 3 (3Q0, 3Q1). See Table 9. 6, 7 4F0, 4F1 I Three-level function select inputs for output pair 4 (4Q0, 4Q1). See Table 9. 31 TEST I Three-level select. See test mode section under the block diagram descriptions. 23, 24 1Q1, 1Q0 O Output pair 1. See Table 9. 21, 22 2Q1, 2Q0 O Output pair 2. See Table 9. 14, 15 3Q1, 3Q0 O Output pair 3. See Table 9. 10, 11 4Q1, 4Q0 O Output pair 4. See Table 9. 9, 16, 18, 25 VCCN PWR Power supply for output drivers 2 VCCQ PWR Power supply for internal circuitry 12, 13, 21, 22, 28, 32 GND PWR Ground. Memory PIN TABLE 2. 7B991 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL MIN MAX UNIT Storage Temperature TS -65 150 °C Operating Temperature Range TA -40 85 °C Supply Voltage to Ground Potential VS -0.5 7.0 V DC Input Voltage VI -0.5 7.0 V Output Current into Outputs (LOW) IOUT -- 64 mA Static Discharge Voltage (per MIL-STD-882, Method 3015) VSD >2001 -- V Latchup Current ILU >200 -- mA 2.10.03 REV 5 All data sheets are subject to change without notice 2 ©2003 Maxwell Technologies. All rights reserved. 7B991 Programmable Skew Clock Buffer (PSCB) TABLE 3. DELTA LIMITS PARAMETER VARIATION ICC ±10% of specified value in Table 5 TABLE 4. 7B991 RECOMMENDED OPERATING CONDITIONS PARAMETER MIN MAX UNIT Supply Voltage VCC -0.5 +7.0 V Input HIGH Voltage (REF and FB inputs only) VIH 2.0 VCC V Input LOW Voltage (REF and FB inputs only) VIL -0.5 0.8 V Three-Level Input HIGH Voltage (Test, FS, xFn) 1 VIHH VCC-0.85 VCC V Thermal Impedance ΘJC -- 3.43 °C/W 1. These inputs are normally wired to VCC,GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved. TABLE 5. 7B991 DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±10%, TA = -40 TO 85°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL TEST CONDITIONS SUBGROUPS MIN MAX UNIT Output HIGH Voltage VOH VCC = Min, IOH = -16 mA 1, 2, 3 2.4 -- V Output LOW Voltage VOL VCC = Min, IOL = 46 mA 1, 2, 3 -- 0.45 V Input HIGH Voltage (REF and FB inputs only) VIH 1, 2, 3 2.0 -- V Input LOW Voltage (REF and FB inputs only) VIL 1, 2, 3 -- 0.8 V Three-Level Input HIGH Voltage (Test, FS, xFn) 1 VIHH Min < VCC < Max 1, 2, 3 VCC-0.85 -- V Three-Level Input MID Voltage (Test, FS, xFn) 1 VIMM Min < VCC < Max 1, 2, 3 VCC/2 500 mV VCC/2 + 500 mV V Three-Level Input LOW Voltage (Test, FS, xFn) 1 VILL Min < VCC < Max 1, 2, 3 0.0 0.8 V Input HIGH Leakage Current (REF and FB inputs only) IIH VCC = Max, VIN = 5.0V 1, 2, 3 -- 10 µA Input LOW Leakage Current (REF and FB inputs only) IIL VCC = Max, VIN = 0.0V 1, 2, 3 -500 -- µA Input HIGH Current (Test, FS, xFn) IIH VIN = 5.0V 1, 2, 3 -- 200 µA 2.10.03 REV 5 All data sheets are subject to change without notice 3 ©2003 Maxwell Technologies. All rights reserved. Memory SYMBOL 7B991 Programmable Skew Clock Buffer (PSCB) TABLE 5. 7B991 DC ELECTRICAL CHARACTERISTICS (VCC = 5V ±10%, TA = -40 TO 85°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL TEST CONDITIONS SUBGROUPS MIN MAX UNIT Input MID Current (Test, FS, xFn) IIMM VIN = 2.75V 1, 2, 3 -200 200 µA Input LOW Current (Test, FS, xFn) IIL VIN = 0.0V 1, 2, 3 -- -200 µA Output Short Circuit (Test, FS, xFn) IOS VCC = Max., VOUT = GND (25 ° C only) 1 -- -200 mA Operating Current used by Internal Circuitry3 ICC VCCN = VCCQ = Max, all input selects open 1, 2, 3 -- 166 mA Power Dissipation per Output Pair 4 PD VCCN = VCCQ = Max, IOUT = 0 mA Input selects open, fMAX 1, 2, 3 -- 78 mW 2 1. These inputs are normally wired to VCC,GND, or left unconnected (actual threshold voltages vary as a percentage of VCC). Internal termination resistors hold unconnected inputs at VCC/2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional tLOCK time before all datasheet limits are achieved. 3. Total power dissipation per output pair can be approximated by the following expression that includes device current plus load current: ICCN = [(4 + 0.11F) + [(835-3F)/Z) + ( 0.0022FC)]N] * 1.1 Where: f = frequency in MHz C = capacitive load in pF Z = line impedance in ohms N = number of loaded outputs; 0, 1, 2 FC = F * C 4. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation due to the load circuit PD = [(22 + 0.61F) + [((1550-2.7F)/Z) + (.0125FC)]N] x 1.1 TABLE 6. 7B991 CAPACITANCE1 PARAMETER Input Capacitance 1. Guaranteed by design. SYMBOL CIN TEST CONDITIONS TA = 25 ° C, f = 1 MHz, VCC = 5.0V 2.10.03 REV 5 MAX UNIT 10 pF All data sheets are subject to change without notice 4 ©2003 Maxwell Technologies. All rights reserved. Memory 2. This device should be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. 7B991 Programmable Skew Clock Buffer (PSCB) FIGURE 1. TTL AC TEST LOAD FIGURE 2. TTL INPUT TEST WAVEFORM Memory TABLE 7. AC ELECTRICAL CHARACTERISTICS 1,2,3 (VCC = 5V ±10%, TA = -40 TO 85°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNIT fNOM 9, 10, 11 15 -- 30 MHz FS = MID 1,4 25 -- 50 FS = HIGH 40 -- 803 Operating Clock Frequency in MHz FS = LOW 1,4 1,4,5 REF Pulse Width HIGH12 tRPWH 9, 10, 11 5.0 -- -- ns LOW12 tRPWL 9, 10, 11 5.0 -- -- ns tU 9, 10, 11 tSKEWPR 9, 10, 11 -- 0.1 0.50 ns tSKEW0 9, 10, 11 -- 0.3 0.75 ns Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs) 6,10 tSKEW1 9, 10, 11 -- 0.6 1.0 ns Output Skew (Rise-Fall, Nominal-Inverted, DividedDivided) 6,10 tSKEW2 9, 10, 11 -- 1.0 1.5 ns Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs) 6,10 tSKEW3 9, 10, 11 -- 0.7 1.2 ns Output Skew (Rise-Fall, Nominal-Divided, DividedInverted) 6,10 tSKEW4 9, 10, 11 -- 1.2 1.7 ns Device-to-Device Skew 1,11,12 tDEV 9, 10, 11 -- -- 1.65 ns Propagation Delay, REF Rise to FB Rise tPD 9, 10, 11 -1 0.0 1 ns tODCV 9, 10, 11 -1.2 0.0 1.2 ns REF Pulse Width Programmable Skew Unit Zero Output Matched-Pair Skew (XQ0, XQ1) Zero Output Skew (All Outputs) Output Duty Cycle Variation 13 6,7 6,8,9 2.10.03 REV 5 See Table 2 All data sheets are subject to change without notice 5 ©2003 Maxwell Technologies. All rights reserved. 7B991 Programmable Skew Clock Buffer (PSCB) TABLE 7. AC ELECTRICAL CHARACTERISTICS 1,2,3 (VCC = 5V ±10%, TA = -40 TO 85°C, UNLESS OTHERWISE SPECIFIED) PARAMETER SYMBOL SUBGROUPS MIN TYP MAX UNIT Output HIGH Time Deviation from 50% 14,15 tPWH 9, 10, 11 -- -- 3 ns Output LOW Time Deviation from 50% 14,15 tPWL 9, 10, 11 -- -- 3.5 ns Output Rise Time 14,16 tORISE 9, 10, 11 -- 1.5 2.5 ns Output Fall Time 14,16 tOFALL 9, 10, 11 -- 1.5 2.5 ns PLL Lock Time 12,17 tLOCK 9, 10, 11 -- -- 0.5 ms tJR 9, 10, 11 -- -- 200 ps Cycle-to-Cycle Output Jitter Peak-toPeak 3 1. The level to be set of FS in determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (See Table 9). The frequency appearing at the REF and FB inputs will be fNOM when the output connected to FB is undivided. The frequency of the REF and FB inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. Guaranteed by statistical correlation. Tested initially and after any design or process changes that may affect these parameters. 4. For all three state inputs. HIGH indicates a connection to VCC, LOW indicates a connection to GND, and MID indicates an open connections. Internal termination circuitry holds an unconnected input to VCC/2. 5. When the FS pin is selected HIGH, the REF input must not transition upon power-up until VCC has reached 4.3V. 6. SKEW is defined as the time between the earliest and the latest output transition among all outputs for which the same tU delay has been selected when all are loaded with 50 pF and terminated with 50Ω to 2.06V. 7. tSKEWPR is defined as the skew between a pair of outputs (XQ0 and XQ1) when all eight outputs are selected for 0tU. 8. tSKEW0 is defined as the skew between outputs when they are selected for 0tU. Other outputs are divided or inverted but not shifted. 9. CL = 0 pF. For CL = 30 pF, tSKEW0 = 0.35 ns. 10.There are three classes of outputs: Nominal (multiple of tU delay), Inverted (4Q0 and 4Q1 only with 4F0 = 4F1 = HIGH), and divided (3Qx and 4Qx only in Divide-by-2 or Divide-by-4 mode). 11. tDEV is the output-to-output skew between any two devices operating under the same conditions (VCC ambient temperature, air flow, etc.) 12.Guaranteed by design. 13.tODCV is the deviation of the output from a 50% duty cycle. Output pulse width variations are included in tSKEW2 and tSKEW4 specifications. 14.Specified with outputs loaded 30 pF for the 7B99 devices. Devices are terminated through 50Ω to 2.05V. 15.tPWH is measured at 2.0V. tPWL is measured at 0.8V. 16.tORISE and tOFALL measured between 0.8V and 2.0V. 17.tLOCK is the time that is required before synchronization is achieved. This specification is valid only after VCC is stable and within normal operating limits. This parameter is measured from the application of a new signal or frequency at REF or FB until tPD is within specified limits. 2.10.03 REV 5 All data sheets are subject to change without notice 6 ©2003 Maxwell Technologies. All rights reserved. Memory 2. Test measurement levels for the 7B991 are TTL levels (1.5V to 1.5V). Test conditions assume signal transition times of 2 ns or less and output loading as shown in the AC Test Loads and Waveforms unless otherwise specified. Programmable Skew Clock Buffer (PSCB) 7B991 FIGURE 3. AC TIMING DIAGRAMS Memory 2.10.03 REV 5 All data sheets are subject to change without notice 7 ©2003 Maxwell Technologies. All rights reserved. 7B991 Programmable Skew Clock Buffer (PSCB) BLOCK DIAGRAM DESCRIPTION Phase Frequency Detector and Filter These two blocks accept inputs from the reference frequency (REF) input and the feedback (FB) input and generate correction information to control the frequency of the Voltage-Controlled Oscillator (VCO). These blocks, along with the VCO, form a Phase-Locked Loop (PLL) that tracks the incoming REF signal. VCO and Time Unit Generator The VCO accepts analog control inputs from the PLL filter block and generates a frequency that is used by the time unit generator to create discrete time units that are selected in the skew select matrix. The operational range of the VCO is determined by the FS control pin. The time unit (tU) is determined by the operating frequency of the device and the level of the FS pin as shown in Table 1. TABLE 8. 7B991 FREQUENCY RANGE SELECT AND tU CALCULATION1 FS fNOM (MHZ) 2,3 APPROXIMATE FREQUENCY (MHZ) AT WHICH tU = 1.0 ns MIN MAX LOW 15 30 44 22.7 MID 25 50 26 38.5 Memory tU = 1/fNOM X N WHERE N = HIGH 40 80 16 62.5 1. For all three state inputs. HIGH indicates a connection to VCC. LOW indicates a connection to GND, and MID indicates an open connection. Internal termination circuitry holds an unconnected input to VCC/2. 2. The level to be set of FS is determined by the “normal” operating frequency (fNOM) of the VCO and Time Unit Generator (see Logic Block Diagram). Nominal frequency (fNOM) always appears at 1Q0 and the other outputs when they are operated in their undivided modes (See Table 9). The frequency appearing at the REF and FB inputs will be fNOM when the output connected to FB is undivided. The frequency appearing at the REF and FB inputs will be fNOM/2 or fNOM/4 when the part is configured for a frequency multiplication by using a divided output as the FB input. 3. When the FS pin is selected HIGH, the REF input must not transition upon power-up until VCC has reached 4.3V. Skew Select Matrix The skew select matrix is comprised of four independent sections. Each section has two low-skew, high-fanout drivers(xQ0, xQ1), and two corresponding three-level function select (xF0, xF1) inputs. Table 9 below shows the nine possible output functions for each section as determined by the function select inputs. All times are measured with respect to the REF input assuming that the output connected to the FB input has 0tU selected. 2.10.03 REV 5 All data sheets are subject to change without notice 8 ©2003 Maxwell Technologies. All rights reserved. 7B991 Programmable Skew Clock Buffer (PSCB) TABLE 9. 7B991 PROGRAMMABLE SKEW CONFIGURATIONS 1 FUNCTION SELECTS OUTPUT FUNCTIONS 1F1, 2F1, 3F1, 4F1 1F0, 2F0, 3F0, 4F0 1Q0, 1Q1, 2Q0, 2Q1 3Q0, 3Q1 4Q0, 4Q1 LOW LOW -4tU Divide by 2 Divide by 2 LOW MID -3tU -6tU -6tU LOW HIGH -2tU -4tU -4tU MID LOW -1tU -2tU -2tU MID MID 0tU 0tU 0tU MID HIGH +1tU +2tU +2tU HIGH LOW +2tU +4tU +4tU HIGH MID +3tU +6tU +6tU HIGH HIGH +4tU Divide by 4 Inverted FIGURE 4. TYPICAL OUTPUTS WITH FB CONNECTED TO A ZERO-SKEW OUTPUT1 1. FB connected to an output selected for “zero” skew (i.e. xF1 = xF0 = MID) 2.10.03 REV 5 All data sheets are subject to change without notice 9 ©2003 Maxwell Technologies. All rights reserved. Memory 1. For all three state inputs. HIGH indicates a connection to VCC. LOW indicates a connection to GND, and MID indicates an open connections. Internal termination circuitry holds an inconnected input to VCC/2. Programmable Skew Clock Buffer (PSCB) 7B991 Test Mode The TEST input is a three-level input. In normal system operation, this pin is connected to ground, allowing the 7B991RP to operate as explained briefly above (for testing purposes, any of the three-level inputs can have a removable jumper to ground, or be tied LOW through a 100Ω resistor. This will allow an external tester to change the state of these pins.) If the TEST input is forced to its MID or HIGH state, the device will operate with its internal phase locked loop disconnected, and input levels supplied to REF will directly control all outputs. Relative output to output functions are the same as in normal mode. In contrast with normal operation (TEST tied LOW). All outputs will function based only on the connection of their own function select inputs (xF0 and xF1) and the waveform characteristics of the REF input. Memory 2.10.03 REV 5 All data sheets are subject to change without notice 10 ©2003 Maxwell Technologies. All rights reserved. Programmable Skew Clock Buffer (PSCB) 7B991 OPERATIONAL MODE DESCRIPTIONS FIGURE 5. ZERO-SKEW AND/OR ZERO-DELAY CLOCK DRIVER FIGURE 6. PROGRAMMABLE-SKEW CLOCK DRIVE Figure 6 shows a configuration to equalize skew between metal traces of different lengths. In addition to low skew between outputs, the PSCB can be programmed to stagger the timing of its outputs. The four groups of output pairs can each be programmed to different output timing. Skew timing can be adjusted over a wide range in small increments with the appropriate strapping of the function select pins. In this configuration, the 4Q0 output is fed back to FB and configured for zero skew. The other three pairs of outputs are programmed to yield different skews relative to the feedback. By advancing the clock signal on the longer traces or retarding the clock signal on shorter traces, all loads can receive the clock pulse at the same time. In this illustration, the FB input is connected to an output with 0-ns skew (xF1, xF0 = MID) selected. The internal PLL synchronizes the FB and REF inputs and aligns their rising edges to insure that all outputs have precise phase alignment. 2.10.03 REV 5 All data sheets are subject to change without notice 11 ©2003 Maxwell Technologies. All rights reserved. Memory Figure 5 shows the PSCB configured as a zero-skew clock buffer. In this mode, the 7B991 can be used as the basis for a low-skew clock distribution tree. When all of the function select inputs (xF0, xF1) are left open, the outputs are aligned and may each drive a terminated transmission line to an independent load. The FB input can be tied to any output in this configuration and the operating frequency range is selected with the FS pin. The low-skew specification, coupled with the ability to drive terminated transmission lines (with impedances as low as 50 Ω), allow efficient printed circuit board design. Programmable Skew Clock Buffer (PSCB) 7B991 Clock skews can be advanced by ± 6 time units (tU) when using an output selected for zero skew as the feedback. A wider range of delays is possible if the output connected to FB is also skewed. Since “Zero Skew”, +tU and -tU are defined relative to output groups, and since the PLL aligns the rising edges of REF and FB, it is possible to create wider output skews by proper selection of the xFn inputs. For example, a +10 tU between REG and 3Qx can be achieved by connecting 1Q0 to FB and setting 1F0 = 1F1 = GND, 3F0 = MID, and 3F1 = HIGH (Since FB aligns at -4 tU and 3Qx skews to +6 tU, a total of +10 tU skew is realized.). Many other configurations can be realized by skewing both the output used as the FB input and skewing the other outputs. FIGURE 7. INVERTED OUTPUT CONNECTIONS FIGURE 8. FREQUENCY MULTIPLIER WITH SKEW CONNECTIONS Figure illustrates the PSCB configured as a clock multiplier. The 3Q0 output is programmed to divide by four and is fed back to FB. This causes the PLL to increase its frequency until the 3Q0 and 3Q1 outputs are locked at 20 MHz while the 1Qx and 2Qx outputs run at 80 MHz. The 4Q0 and 4Q1 outputs are programmed to divide by two, which 2.10.03 REV 5 All data sheets are subject to change without notice 12 ©2003 Maxwell Technologies. All rights reserved. Memory Figure shows an example of the invert function of the PSCB. In this example the 4Q0 output used as the FB input is programmed for invert (4F0 = 4F1 = HIGH) while the other three pairs of outputs are programmed for zero skew. When 4F0 and 4F1 are tied high, 4Q0 and 4Q1 become inverted zero phase outputs. The PLL aligns the rising edge of the FB input with the rising edge of the REF. This causes the 1Q, 2Q, and 3Q outputs to become the “inverted” outputs with respect to the REF input. By selecting which output connects to FB, it is possible to have 2 inverted and 6 non-inverted output or 6 inverted and 2 non-inverted outputs. The correct configuration would be determined by the need for more (or fewer) inverted outputs. 1Q, 2Q, and 3Q outputs can also be skewed to compensate for varying trace delays independent of inversion on 4Q. Programmable Skew Clock Buffer (PSCB) 7B991 results in a 40 MHz waveform at these outputs. Note that the 20 and 40 MHz clocks fall simultaneously and are out of phase on their rising edge. This will allow the designer to use the rising edges of the ½ frequency and ¼ frequency outputs without concern for rising-edge skew. The 2Q0, 2Q1, 1Q0, and 1Q1 outputs run at 80 MHz and are skewed by programming their select inputs accordingly. Note that the FS pin is wired for 80 MHz operation because that is the frequency of the fastest output. FIGURE 9. FREQUENCY DIVIDER CONNECTIONS FIGURE 10. MULTI-FUNCTION CLOCK DRIVER Figure shows some of the functions that are selectable on the 3Qx and 4Qx outputs. These include inverted outputs and outputs that offer divide-by-2 and divide-by-4 timing. An inverted output allows the system designer to clock different sub-systems on opposite edges, without suffering from the pulse asymmetry typical of non-ideal loading. This function allows the two subsystems to each be clocked 180 degrees out of phase, but still to be aligned within the skew specification. The divided outputs offer a zero-delay divider for portions of the system that need the clock to be divided by either two or four, and still remain within a narrow skew of the “1X” clock. Without this feature, an external divider would need to be added, and the propagation delay of the divider would add to the skew between the different clock signals. 2.10.03 REV 5 All data sheets are subject to change without notice 13 ©2003 Maxwell Technologies. All rights reserved. Memory Figure demonstrates the PSCB in a clock divider application. 2Q0 is fed back to the FB input and programmed for zero skew. 3Qx is programmed to divide by four. 4Qx is programmed to divide by two. Note that the falling edges of the 4Qx and 3Qx outputs are aligned. This allows use of the rising edges of the ½ frequency and ¼ frequency without concern for skew mismatch. The 1Qx outputs are programmed to zero skew and are aligned with the 2Qx outputs. In this example, the FS input is grounded to configure the device in the 15 to 30 MHz range since the highest frequency output is running at 20 MHz. Programmable Skew Clock Buffer (PSCB) 7B991 These divided outputs, coupled with the Phase Locked Loop, allow the PSCB to multiply the clock rate at the REF input by either two or four. This mode will enable the designer to distribute a low-frequency clock between various portions of the system, and then locally multiply the clock rate to a more suitable frequency, while still maintaining the lowskew characteristics described above at the same time. It can multiply by two and four or divide by two (and four) at the same time that it is shifting its outputs over a wide range or maintaining zero skew between selected outputs. FIGURE 11. BOARD-TO-BOARD CLOCK DISTRIBUTION Memory Figure shows the 7B991 connected in series to construct a zero-skew clock distribution tree between boards. Delays of the downstream clock buffers can be programmed to compensate for the wire length (i.e. select negative skew equal to the wire delay) necessary to connect them to the master clock source, approximating a zerp-delay clock tree. Cascaded clock buffers will accumulate low-frequency jitter because of the non-ideal filtering characteristics of the PLL filter. It is recommended that not more than two clock buffers be connected in series. 2.10.03 REV 5 All data sheets are subject to change without notice 14 ©2003 Maxwell Technologies. All rights reserved. Programmable Skew Clock Buffer (PSCB) 7B991 Memory 32 PIN RAD-PAK® FLAT PACKAGE SYMBOL DIMENSION MIN NOM MAX A 0.117 0.130 0.163 b 0.015 0.017 0.022 c 0.004 0.005 0.009 D -- 0.820 0.830 E 0.404 0.410 0.416 E1 -- -- 0.440 E2 0.234 0.240 -- E3 0.030 0.085 -- e 0.050 BSC L 0.350 0.370 0.390 Q 0.020 0.033 0.036 S1 0.005 0.027 -- N 32 F32-01 Note: All dimensions in inches 2.10.03 REV 5 All data sheets are subject to change without notice 15 ©2003 Maxwell Technologies. All rights reserved. Programmable Skew Clock Buffer (PSCB) 7B991 Important Notice: These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts. Memory 2.10.03 REV 5 All data sheets are subject to change without notice 16 ©2003 Maxwell Technologies. All rights reserved. 7B991 Programmable Skew Clock Buffer (PSCB) Product Ordering Options Model Number 7B991 XX F X Option Details Feature Monolithic S = Maxwell Class S B = Maxwell Class B I = Industrial (testing @ -40°C, +25°C, +85°C) E = Engineering (testing @ +25°C) Package F = Flat Pack Radiation Feature RP = RAD-PAK® package Base Product Nomenclature Programmable Skew Clock Buffer (PSCB) 2.10.03 REV 5 All data sheets are subject to change without notice Memory Screening Flow 17 ©2003 Maxwell Technologies. All rights reserved.