69F64G16 69F128G16 69F256G16 Preliminary 64 Gb, 128 Gb, 256 Gb x16 NAND Flash Module FEATURES: NAND Flash Interface Single Level Cell (SLC) Technology ONFI 2.2 Compliant Operating Voltage VCC 3.0 - 3.6V VCCQ 1.7 - 1.95V or 3.0-3.6V High density 32Gbit per FLASH NAND die Supports higher speed designs with less capacitance/fewer I/O's to drive Page Size 8640 bytes (8192 + 448 spare bytes) Supports external BCH correction algorithms (16 bit correction per 540 bytes) Features High reliability data storage for demanding space applications Ceramic hermetic package with built-in TID shielding Two separate isolated FLASH memory banks (isolated control, data and power) Can be used separately or tied together on customer board Class E, I, H or K 64G16, 128G16 and 256G16 densities with same footprint/pinout functionality Speed Can be used in asynch or synch mode Asynch: Up to asynch timing mode 5 (50MT/sec) Synch: Up to synchronous timing mode 5 (200MT/sec) Temperature Range -55⁰C to 125⁰C Endurance 60,000 cycles 10.08.15 Rev 2 (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com All data sheets are subject to change without notice ©2015 Maxwell Technologies All rights reserved NAND Flash 64 Gb, 128 Gb, 256 Gb X16 Supported Features ONFI 1.0, 2.0, 2.1, 2.2 Interleaved (multi-plane) operations Multiple LUN operations Small Data Move Interleaved Address restrictions for cache operations No interleaved block address restrictions Overlapped/concurrent interleaving supported Supports timing modes: 0 thru 5 Supports driver strength settings: underdrive, overdrive 1 and 2 Supported Commands: Reset Synchronous Reset Reset LUN Get Features Set Features Read Status Read Status Enchanced Change Row Address Read Mode Read Page Interleaved Read Page Cache Sequential Read Page Cache Random Read Page Cache Last Program Page Program Page Interleaved Program Page Cache Erase Block Erase Block Interleaved Copyback Read Copyback Program Copyback Program Interleaved Read Unique ID Read Parameter Page Read ID Not Supported Non-sequential page programming 16 bit data bus width per Target/LUN Extended ECC 10.08.15 Rev 2 All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 2 ©2015 Maxwell Technologies All rights reserved NAND Flash 64 Gb, 128 Gb, 256 Gb X16 Array Organization Cycle First Second Third Fourth Fifth DQ7 CA7 L BA7 BA15 L DQ6 CA6 L PA6 BA14 L DQ5 CA5 CA13 PA5 BA13 L DQ4 CA4 CA12 PA4 BA12 L DQ3 CA3 CA11 PA3 BA11 LUN DQ2 CA2 CA10 PA2 BA10 BA18 DQ1 CA1 CA9 PA1 BA9 BA17 DQ0 CA0 CA8 PA0 BA8 BA16 CA[n] = Column Address PA[n] = Page Address BA[n] = Bank Address LUN = Logical Unit Address Row Address = LUN, Bank, Page Address BA[7] = Plane select Column Addresses above 8639 are invalid (page size = 8192 + 448) Memory Organizatoin Bytes per page: 8192 Spare ECC bytes per page: 448 Pages per block: 128 Blocks per LUN: 4096 LUNs per chip enable: 2; 64G16 is 1 LUN per chip enable Column address cycles: 2 Row address cycles: 3 Bits per cell: 1 Bad blocks maximum per LUN: 80 Block endurance: 60,000 Programs per page: 4 Number of interleave address bits: 1 10.08.15 Rev 2 All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 3 ©2015 Maxwell Technologies All rights reserved NAND Flash 64 Gb, 128 Gb, 256 Gb X16 Package Organization 69F256G16 Sync Async CE#-1 CLE-1 ALE-1 CLK-1 W/R#-1 DQ[7-0]-1 DQS-1 WP#-1 CE#-1 CLE-1 ALE-1 WE#-1 RE#-1 DQ[7-0]-1 N/A WP#-1 Target-1 CE#-2 CLE-2 ALE-2 CLK-2 W/R#-2 DQ[7-0]-2 DQS-2 WP#-2 CE#-2 CLE-2 ALE-2 WE#-2 RE#-2 DQ[7-0]-2 N/A WP#-2 Target-2 CE#-3 CLE-1 ALE-1 CLK-1 W/R#-1 DQ[7-0]-1 DQS-1 WP#-1 CE#-3 CLE-1 ALE-1 WE#-1 RE#-1 DQ[7-0]-1 N/A WP#-1 Target-3 CE#-4 CLE-2 ALE-2 CLK-2 W/R#-2 DQ[7-0]-2 DQS-2 WP#-2 CE#-4 CLE-2 ALE-2 WE#-2 RE#-2 DQ[7-0]-2 N/A WP#-2 Target-4 Package LUN 1 LUN 2 R/B#-1 LUN 1 LUN 2 R/B#-2 LUN 1 LUN 2 R/B#-1 Architecture Independent 8 bit buses per package: 2 Targets per 8 bit bus: 2 LUNS per Target: 2 (4 die per 8 bit bus) (8 die per package) LUN 1 LUN 2 R/B#-2 DQ[7-0]-1 CE-1#, CE-3# RB-1# RE-1#, WR-1# CLE-1, ALE-1 WE-1#/CLK-1 WP-1#, DQS-1 DQ[7-0]-2 CE-2#, CE-4# RB-2# RE-2#, WR-2# WE-2#/CLK-2 WP-2#, DQS-2 10.08.15 Rev 2 All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 4 ©2015 Maxwell Technologies All rights reserved NAND Flash 64 Gb, 128 Gb, 256 Gb X16 Package Organization 69F128G16 Sync Async CE#-1 CLE-1 ALE-1 CLK-1 W/R#-1 DQ[7-0]-1 DQS-1 WP#-1 CE#-1 CLE-1 ALE-1 WE#-1 RE#-1 DQ[7-0]-1 N/A WP#-1 Target-1 CE#-2 CLE-2 ALE-2 CLK-2 W/R#-2 DQ[7-0]-2 DQS-2 WP#-2 CE#-2 CLE-2 ALE-2 WE#-2 RE#-2 DQ[7-0]-2 N/A WP#-2 Target-2 Package LUN 1 LUN 2 R/B#-1 Architecture Independent 8 bit buses per package: 2 Targets per 8 bit bus: 1 LUNS per Target: 2 (2 die per 8 bit bus) (4 die per package) LUN 1 LUN 2 R/B#-2 DQ[7-0]-1 CE-1# RB-1# RE-1#, WR-1# CLE-1, ALE-1 WE-1#/CLK-1 WP-1#, DQS-1 DQ[7-0]-2 CE-2# RB-2# RE-2#, WR-2# WE-2#/CLK-2 WP-2#, DQS-2 10.08.15 Rev 2 All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 5 ©2015 Maxwell Technologies All rights reserved NAND Flash 64 Gb, 128 Gb, 256 Gb X16 Package Organization 69F64G16 Sync Async CE#-1 CLE-1 ALE-1 CLK-1 W/R#-1 DQ[7-0]-1 DQS-1 WP#-1 CE#-1 CLE-1 ALE-1 WE#-1 RE#-1 DQ[7-0]-1 N/A WP#-1 Target-1 CE#-2 CLE-2 ALE-2 CLK-2 W/R#-2 DQ[7-0]-2 DQS-2 WP#-2 CE#-2 CLE-2 ALE-2 WE#-2 RE#-2 DQ[7-0]-2 N/A WP#-2 Target-2 Package LUN 1 R/B#-1 Architecture Independent 8 bit buses per package: 2 Targets per 8 bit bus: 1 LUNS per Target: 1 (1 die per 8 bit bus) (2 die per package) LUN 1 R/B#-2 DQ[7-0]-1 CE-1# RB-1# RE-1#, WR-1# CLE-1, ALE-1 WE-1#/CLK-1 WP-1#, DQS-1 DQ[7-0]-2 CE-2# RB-2# RE-2#, WR-2# WE-2#/CLK-2 WP-2#, DQS-2 10.08.15 Rev 2 All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 6 ©2015 Maxwell Technologies All rights reserved NAND Flash 10.08.15 Rev 2 64 Gb, 128 Gb, 256 Gb X16 All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 7 ©2015 Maxwell Technologies All rights reserved NAND Flash Pinout 64 Gb, 128 Gb, 256 Gb X16 1 64G16 & 128G16 Pin Description same same same same same same NC2 same same same same same same same same same same same same same same same same same same same same same same same same same same same 256G16 Pin Description VSS VCC-1 WP#-1 WE#/CLK-1 ALE-1 CLE-1 CE#3 CE#1 RE#/WR#-1 RB#-1 VSS VCC-1 VSS VSSQ VCCQ-1 DQ7-1 DQ6-1 DQ5-1 DQ4-1 VSSQ VCCQ-1 VCC-1 VSS DQS-1 VCCQ-1 VSSQ DQ3-1 DQ2-1 DQ1-1 DQ0-1 VCCQ-1 VSSQ VSS VCC-1 Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pin # 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 256G16 Pin Description VCC-2 WP#-2 WE#/CLK-2 ALE-2 CLE-2 CE#4 CE#2 RE#/WR#-2 RB#-2 VSS VCC-2 VSS VSSQ VCCQ-2 DQ7-2 DQ6-2 DQ5-2 DQ4-2 VSSQ VCCQ-2 VCC-2 VSS DQS-2 VCCQ-2 VSSQ DQ3-2 DQ2-2 DQ1-2 DQ0-2 VCCQ-2 VSSQ VSS VCC-2 64G16 & 128G16 Pin Description same same same same same same NC2 same same same same same same same same same same same same same same same same same same same same same same same same same same same 1. Two independent 8 bit buses; Bus-1 and Bus-2 completely isolated (DQ, control, Power) 2. NC = Not internally connected 10.08.15 Rev 2 All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 8 ©2015 Maxwell Technologies All rights reserved NAND Flash 64 Gb, 128 Gb, 256 Gb X16 Product Ordering Options 69F XXX G 16 XX F X Screening Flow K = Maxwell Class K H = Maxwell Class H I = Industrial (testing @ -55⁰C, +25⁰C +125⁰C ) E = Engineering (testing at +25⁰C ) Package F = Flat Pack Radiation Feature RP = RAD -PAK® Package Shielding Data Width 16 = 16bits wide Total Gbits 64 = 64Gb 128 = 128Gb 256 = 256Gb Base Product 3.3V by 16 NAND FLASH SLC Nomenclature 10.08.15 Rev 2 All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com 9 ©2015 Maxwell Technologies All rights reserved