LTC3225/LTC3225-1 - 150mA Supercapacitor Charger

LTC3225/LTC3225-1
150mA Supercapacitor
Charger
FEATURES
DESCRIPTION
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The LTC®3225/LTC3225-1 are programmable supercapacitor chargers designed to charge two supercapacitors in
series to a selectable fixed output voltage (4.8V/5.3V for
the LTC3225 and 4V/4.5V for the LTC3225-1) from input
supplies as low as 2.8V to 5.5V. Automatic cell balancing
prevents overvoltage damage to either supercapacitor. No
balancing resistors are required.
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Low Noise Constant Frequency Charging of Two
Series Supercapacitors
Automatic Cell Balancing Prevents Capacitor
Overvoltage During Charging
Programmable Charge Current (Up to 150mA)
Selectable 2.4V or 2.65V Regulation per Cell
(LTC3225)
Selectable 2V or 2.25V Regulation per Cell
(LTC3225-1)
Automatic Recharge
IVIN = 20μA in Standby Mode
ICOUT < 1μA When Input Supply is Removed
No Inductors
Tiny Application Circuit (2mm × 3mm DFN Package,
All Components <1mm High)
APPLICATIONS
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Current Limited Applications with High Peak Power
Loads (LED Flash, PCMCIA Tx Bursts, HDD Bursts,
GPRS/GSM Transmitter)
Backup Supplies
Low input noise, low quiescent current and low external
parts count (one flying capacitor, one bypass capacitor at
VIN and one programming resistor) make the LTC3225/
LTC3225-1 ideally suited for small battery-powered
applications.
Charge current level is programmed with an external
resistor. When the input supply is removed, the LTC3225/
LTC3225-1 automatically enter a low current state, drawing
less than 1μA from the supercapacitors.
The LTC3225/LTC3225-1 are available in a 10-lead 2mm
× 3mm DFN package.
L, LT, LTC and LTM are registered trademarks and ThinSOT is a trademark of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
TYPICAL APPLICATION
Charging Profile with 30% Mismatch
in Output Capacitance, CTOP < CBOT
VIN
2.8V/3V TO 5.5V
VIN
COUT
0.6F
2.2μF
1μF
ON/OFF
OUTPUT
PROGRAMMING
C+ LTC3225 CX
LTC3225-1
C–
GND
SHDN
VOUT
4.8V/5.3V (LTC3225)
4V/4.5V (LTC3225-1)
SHDN
5V/DIV
IVIN
300mA/DIV
0.6F
100k
VCOUT
2V/DIV
PGOOD
VSEL
PROG
12k
3225 TA01a
VTOP-VBOT
200mV/DIV
5 SEC/DIV
LTC3225
VSEL = VIN
RPROG = 12k
CTOP = 1.1F
CBOT = 1.43F
CTOP INITIAL VOLTAGE = 0V
CBOT INITIAL VOLTAGE = 0V
3225 TA01b
3225fb
1
LTC3225/LTC3225-1
ABSOLUTE MAXIMUM RATINGS
(Note 1)
PIN CONFIGURATION
VIN, COUT to GND ......................................... –0.3V to 6V
SHDN, VSEL ...................................... –0.3V to VIN + 0.3V
COUT Short-Circuit Duration ............................. Indefinite
IVIN Continuous (Note 2) ......................................350mA
IOUT Continuous (Note 2) .....................................175mA
Operating Temperature Range (Note 3).... –40°C to 85°C
Storage Temperature Range................... –65°C to 125°C
TOP VIEW
C+ 1
10 COUT
C– 2
9
VIN
8
GND
SHDN 4
7
PROG
PGOOD 5
6
VSEL
CX 3
11
DDB PACKAGE
10-LEAD (3mm s 2mm) PLASTIC DFN
TJMAX = 125°C, θJA = 76°C/W
EXPOSED PAD (PIN 11) MUST BE SOLDERED TO
LOW IMPEDANCE GND PLANE (PIN 8) ON PCB
ORDER INFORMATION
Lead Free Finish
TAPE AND REEL (MINI)
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3225EDDB#TRMPBF
LTC3225EDDB-1#TRMPBF
TRM = 500 pieces.
LTC3225EDDB#TRPBF
LTC3225EDDB-1#TRPBF
LCYR
LFFS
10-Lead (3mm × 2mm) Plastic DFN
10-Lead (3mm × 2mm) Plastic DFN
–40°C to 85°C
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, CIN = 2.2μF, CFLY = 1μF, unless otherwise specified (Note 3).
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VIN-UVLO
Input Supply Undervoltage Lockout
High-to-Low Threshold
VSEL = VIN
VSEL = 0
2.65
2.4
2.75
2.5
2.85
2.6
V
V
VIN-UVLO-HYS
Input Supply Undervoltage Lockout
Hysteresis
VSEL = VIN
VSEL = 0
VIN
Input Voltage Range
VSEL = VIN
VSEL = 0V
l
l
3
2.8
VCOUT
Charge Termination Voltage
Sleep Mode Threshold (Rising Edge)
VSEL = VIN
VSEL = 0V
l
l
5.2
4.7
VCOUT-HYS
Output Comparator Hysteresis
VTOP/BOT
Maximum Voltage Across Each of the
Supercapacitors After Charging
VSEL = VIN
VSEL = 0V
l
l
VIN-UVLO
Input Supply Undervoltage Lockout
High-to-Low Threshold
VSEL = VIN
VSEL = 0
l
l
VIN-UVLO-HYS
Input Supply Undervoltage Lockout
Hysteresis
VSEL = VIN
VSEL = 0
LTC3225
l
l
150
140
5.3
4.8
mV
mV
5.5
5.5
V
V
5.4
4.9
V
V
100
mV
2.75
2.5
V
V
2.45
2.2
V
V
LTC3225-1
2.25
2.0
2.35
2.1
150
140
mV
mV
3225fb
2
LTC3225/LTC3225-1
ELECTRICAL CHARACTERISTICS
The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.6V, CIN = 2.2μF, CFLY = 1μF, unless otherwise specified (Note 3).
SYMBOL
PARAMETER
CONDITIONS
MIN
VIN
Input Voltage Range
VSEL = VIN
VSEL = 0
l
l
2.8
2.8
VCOUT
Charge Termination Voltage
Sleep Mode Threshold (Rising Edge)
VSEL = VIN
VSEL = 0
l
l
4.4
3.9
VCOUT-HYS
Output Comparator Hysteresis
VTOP/BOT
Maximum Voltage Across Each of the
Supercapacitors After Charging
TYP
4.5
4.0
MAX
5.5
5.5
V
V
4.6
4.1
V
V
100
VSEL = VIN
VSEL = 0
l
l
UNITS
mV
2.35
2.1
V
V
LTC3225/LTC3225-1
IQ-VIN
No Load Operating Current at VIN
IOUT = 0mA
l
20
40
μA
ISHDN-VIN
Shutdown Current
SHDN = 0V, VOUT = 0V
l
0.1
1
μA
ICOUT
COUT Leakage Current
VOUT = 5.6V, SHDN = 0V
VOUT = 5.6V, Charge Pump in Sleep Mode
VOUT = 5.6V, SHDN Connected to VIN with
Input Supply Removed
l
l
1
2
3
4
1
μA
μA
μA
IVIN
Input Charge Current
IOUT
Output Charge Current
VIN = 3.6V, RPROG = 12k, CTOP = CBOT
306
mA
VIN = 3.6V, RPROG = 60k, CTOP = CBOT
55
mA
VIN = 3.6V, RPROG = 12k, CTOP = CBOT,
VOUT = 4.5V (LTC3225),
VOUT = 3.7V (LTC3225-1)
125
VIN = 3.6V, RPROG = 60k, CTOP = CBOT,
VOUT = 4.5V (LTC3225),
VOUT = 3.7V (LTC3225-1)
150
175
26
mA
mA
VPGOOD
PGOOD Low Output Voltage
IPGOOD = –1.6mA
l
0.4
V
IPGOOD-LEAK
PGOOD High Impedance Leakage Current
VPGOOD = 5V
l
10
μA
VPG
PGOOD Low-to-High Threshold
Relative to Output Voltage Threshold
l
92
94
96
%
VPG-HYS
PGOOD Threshold Hysteresis
Relative to Output Voltage Threshold
l
0.25
1.2
2.5
%
ROL
Effective Open-Loop Output Impedance
(Note 4)
VIN = 3.6V, VOUT = 4.5V (LTC3225)
VIN = 3.6V, VOUT = 3.7V (LTC3225-1)
fOSC
CLK Frequency
l
0.6
VIH
Input High Voltage
l
1.3
VIL
Input Low Voltage
l
IIH
Input High Current
l
Input Low Current
l
Ω
8
9
0.9
1.5
MHz
VSEL, SHDN
IIL
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: Based on long-term current density limitations.
V
0.4
V
–1
1
μA
–1
1
μA
Note 3: The LTC3225/LTC3225-1 are tested under pulsed load conditions
such that TJ ≈ TA. The LTC3225/LTC3225-1 are guaranteed to meet
performance specifications from 0°C to 85°C. Specifications over the
–40°C to 85°C operating temperature range are assured by design,
characterization and correlation with statistical process controls.
Note 4: Output not in regulation;
ROL ≡ (2 • VIN – VOUT)/IOUT
3225fb
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LTC3225/LTC3225-1
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, CFLY = 1μF, CIN = 2.2μF, CTOP = CBOT , unless otherwise specified)
IOUT vs RPROG
IOUT vs VOUT (RPROG = 12k)
160
VIN = 3.6V
VOUT = 4.5V (LTC3225)
140
100
160
90
80
140
120
70
80
60
EFFICIENCY (%)
120
100
IOUT (mA)
IOUT (mA)
Efficiency vs VIN
180
100
80
60
40
20
20
0
0
20
10
30
50
40
RPROG (kΩ)
60
0.5
1
1.5
2 2.5 3
VOUT (V)
3.5
4
4.5
3225 G01
0
VOUT = 4.5V
VOUT = 3.7V
25
TA = 85°C
20
TA = 25°C
VOUT = 3.7V
(LTC3225-1)
8.5
TA = –40°C
15
VOUT = 4.5V
(LTC3225)
8.0
7.5
5
2
120
140
160
0
6.5
2.5
3
3.5
4
VIN (V)
4.5
5
5.5
6.0
–40
–15
10
35
TEMPERATURE (°C)
3225 G05
3225 G04
Oscillator Frequency vs
Supply Voltage
60
85
3225 G06
Charging Profile with Unequal
Initial Output Capacitor Voltage
(Initial VTOP = 1.3V, VBOT = 1V)
Input Ripple and Input Current
0.94
SHDN
5V/DIV
VIN
20mV/DIV
0.93
FREQUENCY (MHz)
5.5
5
7.0
VOUT = 4.2V
80 100
IOUT (mA)
4.5
VIN = 3.6V
9.0
10
60
4
VIN (V)
9.5
4
40
3.5
3525 G03
ROL (Ω)
IIN (μA)
5
3
Charge Pump Open-Loop Output
Resistance vs Temperature
(2VIN – VCOUT)/IOUT
10.0
VOUT = 5V
20
2.5
5
30
6
EXTRA IIN (mA)
10
No-Load Input Current vs
Supply Voltage
VIN = 3.6V
CHARGE PUMP IS ON
3
ILOAD = 100mA
CTOP = CBOT
VSEL = VIN
VSEL = 0
3225 G02
Extra Input Current vs Output
Current (IVIN – 2 • IOUT)
7
LTC3225-1
40
20
VIN = 2.8V
VIN = 3.6V
VIN = 5.5V
0
50
30
CTOP = CBOT
40
LTC3225
60
IVIN
300mA/DIV
TA = 25°C
0.92
IVIN
200mA/DIV
TA = –40°C
VCOUT
2V/DIV
0mA
0.91
VTOP-VBOT
500mV/DIV
TA = 85°C
0.90
RPROG = 12k
0.89
0.88
2.5
3
3.5
4
VIN (V)
4.5
5
5.5
200ns/DIV
3225 G08
2 SEC/DIV
LTC3225
VSEL = VIN
RPROG = 12k
CTOP = CBOT = 1.1F
CTOP INITIAL VOLTAGE = 1.3V
CBOT INITIAL VOLTAGE = 1V
3225 G09
3225 G07
3225fb
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LTC3225/LTC3225-1
TYPICAL PERFORMANCE CHARACTERISTICS
(TA = 25°C, CFLY = 1μF, CIN = 2.2μF, CTOP = CBOT , unless otherwise specified)
Charging Profile with Unequal
Initial Output Capacitor Voltage
(Initial VTOP = 1V, VBOT = 1.3V)
Charging Profile with 30%
Mismatch in Output Capacitance
(CTOP > CBOT)
Charging Profile with 30%
Mismatch in Output Capacitance
(CTOP < CBOT)
SHDN
5V/DIV
SHDN
5V/DIV
SHDN
5V/DIV
IVIN
300mA/DIV
IVIN
300mA/DIV
IVIN
300mA/DIV
VCOUT
2V/DIV
VCOUT
2V/DIV
VCOUT
2V/DIV
VTOP-VBOT
200mV/DIV
VTOP-VBOT
200mV/DIV
VTOP-VBOT
500mV/DIV
2 SEC/DIV
LTC3225
VSEL = VIN
RPROG = 12k
CTOP = CBOT = 1.1F
CTOP INITIAL VOLTAGE = 1V
CBOT INITIAL VOLTAGE = 1.3V
3225 G10
5 SEC/DIV
LTC3225
VSEL = VIN
RPROG = 12k
CTOP = 1.43F
CBOT = 1.1F
CTOP INITIAL VOLTAGE = 0V
CBOT INITIAL VOLTAGE = 0V
3225 G11
5 SEC/DIV
LTC3225
VSEL = VIN
RPROG = 12k
CTOP = 1.1F
CBOT = 1.43F
CTOP INITIAL VOLTAGE = 0V
CBOT INITIAL VOLTAGE = 0V
3225 G12
PIN FUNCTIONS
C+ (Pin 1): Flying Capacitor Positive Terminal. A 1μF X5R
or X7R ceramic capacitor should be connected from C+
to C–.
C– (Pin 2): Flying Capacitor Negative Terminal.
CX (Pin 3): Midpoint of Two Series Supercapacitors. This
pin voltage is monitored and forced to track COUT (CX =
COUT/2) during charging to achieve voltage balancing of
the top and bottom supercapacitors.
SHDN (Pin 4): Active Low Shutdown Input. A low on SHDN
puts the LTC3225/LTC3225-1 in low current shutdown
mode. Do not float the SHDN pin.
PGOOD (Pin 5): Open-Drain Output Status Indicator. Upon
start-up, this open-drain pin remains low until the output
voltage, VOUT, is within 6% (typical) of its final value. Once
VOUT is valid, PGOOD becomes Hi-Z. If VOUT falls 7.2%
(typical) below its correct regulation level, PGOOD is
pulled low. PGOOD may be pulled up through an external
resistor to an appropriate reference level. This pin is Hi-Z
in shutdown mode.
VSEL (Pin 6): Output Voltage Selection Input. A logic
low at VSEL sets the regulated COUT to 4.8V (LTC3225)
or 4V (LTC3225-1); a logic high sets the regulated COUT
to 5.3V (LTC3225) or 4.5V (LTC3225-1). Do not float the
VSEL pin.
PROG (Pin 7): Charge Current Programming Pin. A resistor connected between this pin and GND sets the charge
current. (See Applications Information section).
GND (Pin 8, Exposed Pad Pin 11): Charge Pump Ground.
These pins must be soldered directly to PCB ground. The
exposed pad must be soldered to a low impedance PCB
ground for rated thermal performance.
VIN (Pin 9): Power Supply for the LTC3225/LTC3225-1.
VIN should be bypassed to GND with a low ESR ceramic
capacitor of more than 2.2μF.
COUT (Pin 10): Charge Pump Output Pin. Connect COUT to
the top plate of the top supercapacitor. COUT provides charge
current to the supercapacitors and regulates the final voltage to 4.8V/5.3V (LTC3225) or 4V/4.5V (LTC3225-1).
3225fb
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LTC3225/LTC3225-1
SIMPLIFIED BLOCK DIAGRAM
CFLY
9
1
2
C+
VIN
4
C–
VIN
SHDN
SOFT-START AND
SHUTDOWN CONTROL
UVLO
THERMAL
PROTECTION
3000i
POR
1.2V
COUT
CX
CHARGE
PUMP
RUN
CTOP
3
CBOT
GND
8
i
7
10
PROG
CLK
RPROG
RUN/STOP
R1
OSCILLATOR
–
C1
R2
+
VREF – 2%
1.2V
PGOOD
VREF
+
1.088V (LTC3225)
1.067V (LTC3225-1)
6
POR
VREF – 6%
VSEL
VREF – 7.2%
5
C2
–
3225 F01
Figure 1
OPERATION
The LTC3225/LTC3225-1 are dual cell supercapacitor chargers. Their unique topology maintains a constant output
voltage with programmable charge current. Their ability
to maintain equal voltages on both cells while charging
protects the supercapacitors from damage that is possible
with other charging methods, without the use of external
balancing resistors. The LTC3225/LTC3225-1 include an
internal switched capacitor charge pump to boost VIN to a
regulated output voltage. A unique architecture maintains
relatively constant input current for the lowest possible
input noise. The basic charger circuit requires only three
external components.
Normal Charge Cycle
Operation begins when the SHDN pin is pulled above 1.3V.
The COUT pin voltage is sensed and compared with a preset
voltage threshold using an internal resistor divider and
a comparator. The preset voltage threshold is selectable
with the VSEL pin. If the voltage at the COUT pin is lower
than the preset voltage threshold, the oscillator is enabled.
The oscillator operates at a typical frequency of 0.9MHz.
When the oscillator is enabled, the charge pump operates
charging up COUT. Each time the charge pump starts up
from shutdown, the input current drawn by the internal
charge pump ramps up at approximately 20mA/μs until it
reaches a level which is determined by RPROG.
3225fb
6
LTC3225/LTC3225-1
OPERATION
Once the output voltage is charged to the preset voltage threshold, the part shuts down the internal charge
pump and enters into a low current state. In this state,
the LTC3225/LTC3225-1 consume only about 20μA
from the input supply. The current drawn from COUT is
approximately 2μA.
Automatic Cell Balancing
Due to manufacturing tolerances, capacitance and leakage
current can vary from supercapacitor to supercapacitor.
Without the automatic cell balancing scheme used in the
LTC3225/LTC3225-1, the voltages across the supercapacitors could differ from each other and potentially overvoltage
a cell. This can affect the performance and lifetime of a
supercapacitor.
The LTC3225/LTC3225-1 constantly monitor the voltage across both supercapacitors while charging. When
the voltage across the supercapacitors is equal, both
capacitors are charged with equal currents. If the voltage
across one supercapacitor is lower than the other, the
lower supercapacitor’s charge current is increased and
the higher supercapacitor’s charge current is decreased.
The greater the difference between the supercapacitor
voltages, the greater the difference in charge current per
capacitor. The charge currents can increase or decrease
as much as 50% to balance the voltage across the supercapacitors. When the cell voltages are balanced, the
supercapacitors are charged at a rate of approximately:
1
ICOUT = •IVIN
2
If the leakage currents or capacitances of the two supercapacitors are mismatched enough that varying the charge
current is not sufficient to balance their voltages, the
LTC3225/LTC3225-1 stop charging the capacitor with the
higher voltage until they are again balanced. This feature
protects either capacitor from experiencing an overvoltage
condition. Attempting to equalize the voltages using parallel
resistors wastes power, discharges the supercapacitors,
and takes time to equalize the voltages. A 30% capacitance
mismatch leads to a 30% initial voltage difference after
charging. It takes hours to equalize the voltages across
1F supercapacitors using 10k resistors.
Shutdown Mode
Asserting SHDN low causes the LTC3225/LTC3225-1 to
enter shutdown mode. With the SHDN pin connected to
VIN and the input supply removed or grounded, less than
1μA is consumed from the output, allowing the supercapacitors to remain charged.
If the input supply is present at VIN and the SHDN pin is
grounded, the LTC3225/LTC3225-1 draw approximately
1μA of supply current. With the voltage at the COUT pin
discharged to 0V, this current drops to less than 1μA. Since
the SHDN pin is a high impedance CMOS input, it should
never be allowed to float.
Output Voltage Programming
The LTC3225/LTC3225-1 have a VSEL input pin that allows
the user to set the output threshold voltage to either 4.8V
or 5.3V for the LTC3225 and 4V or 4.5V for the LTC3225-1
by forcing a low or high at the VSEL pin respectively.
Output Status Indicator (PGOOD)
During shutdown, the PGOOD pin is high impedance. When
the charge cycle starts, an internal N-channel MOSFET
pulls the PGOOD pin to ground. When the output voltage,
VOUT, is within 6% (typical) of its final value, the PGOOD
pin becomes high impedance, but charge current continues
to flow until VOUT crosses the charge termination voltage.
When VOUT drops 7% below the charge termination voltage, the PGOOD pin again pulls low.
Current Limit/Thermal Protection
The LTC3225/LTC3225-1 have built-in current limit as well
as overtemperature protection. If the PROG pin is shorted
to ground, a protection circuit automatically shuts off the
internal charge pump. At higher temperatures, or if the
input voltage is high enough to cause excessive self-heating of the part, the thermal shutdown circuitry shuts down
the charge pump once the junction temperature exceeds
approximately 150°C. It will enable the charge pump once
the junction temperature drops back to approximately
135°C. The LTC3225/LTC3225-1 are able to cycle in and
out of thermal shutdown indefinitely without latch-up or
damage until the overcurrent condition is removed.
3225fb
7
LTC3225/LTC3225-1
APPLICATIONS INFORMATION
Programming Charge Current
Charging Time Estimation
The charge current is programmed with a single resistor
connecting the PROG pin to ground. The program resistor
and the input/output charge currents are calculated using
the following equations:
The estimated charging time with equal initial voltages
across the two supercapacitors is given by the equation:
IVIN =
3600V
RPROG
IOUT =
IVIN
(with matched output capacitors)
2
An RPROG resistor value of 2k or less (i.e., short circuit)
causes the LTC3225/LTC3225-1 to enter overcurrent
shutdown mode. This mode prevents damage to the part
by shutting down the internal charge pump.
Power Efficiency
The power efficiency (η) of the LTC3225/LTC3225-1 is
similar to that of a linear regulator with an effective input
voltage of twice the actual input voltage. In an ideal regulating voltage doubler the power efficiency is given by:
η2xIDEAL =
POUT VOUT •IOUT VOUT
=
=
PIN
VIN • 2IOUT 2VIN
At moderate to high output power the switching losses
and quiescent current of the LTC3225/LTC3225-1 are
negligible and the above expression is valid. For example,
with VIN = 3.6V, IOUT = 100mA and VOUT regulated to 5.3V,
the measured efficiency is 71.2% which is in close agreement with the theoretical 73.6% calculation.
Effective Open-Loop Output Resistance (ROL)
The effective open-loop output resistance (ROL) of a charge
pump is an important parameter that describes the strength
of the charge pump. The value of this parameter depends
on many factors including the oscillator frequency (fOSC),
value of the flying capacitor (CFLY), the non-overlap time,
the internal switch resistances (RS) and the ESR of the
external capacitors.
t CHRG =
COUT • ( VCOUT – VINI)
IOUT
where COUT is the series output capacitance, VCOUT is the
voltage threshold set by the VSEL pin, VINI is the initial
voltage at the COUT pin and IOUT is the output charge
current given by:
IOUT =
1800V
RPROG
When the charging process starts with unequal initial voltages across the supercapacitors, only the capacitor with
the lower voltage level is charged; the other capacitor is
not charged until the voltages equalize. This extends the
charging time slightly. Under the worst-case condition,
whereby one capacitor is fully depleted while the other
remains fully charged due to significant leakage current
mismatch, the charging time is about 1.5 times longer
than normal.
Thermal Management
For higher input voltages and maximum output current,
there can be substantial power dissipation in the LTC3225/
LTC3225-1. If the junction temperature increases above
approximately 150°C, the thermal shutdown circuitry automatically deactivates the output. To reduce the maximum
junction temperature, a good thermal connection to the PC
board is recommended. Connecting the GND pin (Pin 8)
and the Exposed Pad (Pin 11) of the DFN package to a
ground plane under the device on two layers of the PC
board can reduce the thermal resistance of the package
and PC board considerably.
3225fb
8
LTC3225/LTC3225-1
APPLICATIONS INFORMATION
VIN Capacitor Selection
The type and value of CIN controls the amount of ripple
present at the input pin (VIN). To reduce noise and ripple,
it is recommended that low equivalent series resistance
(ESR) multilayer ceramic chip capacitors (MLCCs) be
used for CIN. Tantalum and aluminum capacitors are not
recommended because of their high ESR.
The input current to the LTC3225/LTC3225-1 is relatively
constant during both the input charging phase and the
output charging phase but drops to zero during the clock
non-overlap times. Since the non-overlap time is small
(~40ns) these missing “notches” result in only a small
perturbation on the input power supply line. Note that a
higher ESR capacitor, such as a tantalum, results in higher
input noise. Therefore, ceramic capacitors are recommended for their exceptional ESR performance. Further
input noise reduction can be achieved by powering the
LTC3225/LTC3225-1 through a very small series inductor
as shown in Figure 2.
A 10nH inductor will reject the fast current notches,
thereby presenting a nearly constant current load to the
input power supply. For economy, the 10nH inductor can
be fabricated on the PC board with about 1cm (0.4") of
PC board trace.
Flying Capacitor Selection
Warning: Polarized capacitors such as tantalum or aluminum should never be used for the flying capacitor since
its voltage can reverse upon start-up of the LTC3225/
LTC3225-1. Low ESR ceramic capacitors should always
be used for the flying capacitor.
The flying capacitor controls the strength of the charge
pump. In order to achieve the rated output current, it is
necessary to use at least 0.6μF of capacitance for the
flying capacitor.
The effective capacitance of a ceramic capacitor varies with
temperature and voltage in a manner primarily determined
by its formulation. For example, a capacitor made of X5R
or X7R material retains most of its capacitance from
–40°C to 85°C whereas a Z5U or Y5V type capacitor loses
considerable capacitance over that range. X5R, Z5U and
Y5V capacitors may also have a poor voltage coefficient
causing them to lose 60% or more of their capacitance
when the rated voltage is applied. Therefore, when comparing different capacitors, it is often more appropriate to
compare the amount of achievable capacitance for a given
case size rather than comparing the specified capacitance
value. For example, over rated voltage and temperature
conditions, a 4.7μF 10V Y5V ceramic capacitor in a 0805
case may not provide any more capacitance than a 1μF 10V
X5R or X7R capacitor available in the same 0805 case. In
fact, over bias and temperature range, the 1μF 10V X5R
or X7R provides more capacitance than the 4.7μF 10V
Y5V capacitor. The capacitor manufacturer’s data sheet
should be consulted to determine what value of capacitor
is needed to ensure minimum capacitance values are met
over operating temperature and bias voltage.
10nH
9
VIN
0.1μF
2.2μF
8, 11
VIN
LTC3225
LTC3225-1
GND
3225 F02
Figure 2. 10nH Inductor Used for Input Noise Reduction
3225fb
9
LTC3225/LTC3225-1
APPLICATIONS INFORMATION
Table 1 contains a list of ceramic capacitor manufacturers
and how to contact them.
Table 1. Capacitor Manufacturers
also be generated if the flying capacitors are far from the
part (i.e. the loop area is large). To prevent capacitive
energy transfer, a Faraday shield may be used. This is a
grounded PC trace between the sensitive node and the
LTC3225/LTC3225-1 pins. For a high quality AC ground it
should be returned to a solid ground plane that extends
all the way to the LTC3225/LTC3225-1.
AVX
www.avx.com
Kemet
www.kemet.com
Murata
www.murata.com
Taiyo Yuden
www.t-yuden.com
Vishay
www.vishay.com
Table 2. Supercapacitor Manufacturers
TDK
www.component.tdk.com
CAP-XX
www.cap-xx.com
NESS CAP
www.nesscap.com
Layout Considerations
Maxwell
www.maxwell.com
Due to the high switching frequency and high transient
currents produced by the LTC3225/LTC3225-1, careful
board layout is necessary for optimum performance. An
unbroken ground plane and short connections to all the
external capacitors improves performance and ensures
proper regulation under all conditions.
Bussmann
www.cooperbussmann.com
AVX
www.avx.com
Illinois Capacitor
www.illcap.com
Tecate Group
www.tecategroup.com
The voltages on the flying capacitor pins C+ and C– have
very fast rise and fall times. The high dV/dt values on
these pins can cause energy to capacitively couple to
adjacent printed circuit board traces. Magnetic fields can
The LTC3225/LTC3225-1 can also be used to charge a
single supercapacitor by connecting two series-connected
matched ceramic capacitors with a minimum capacitance
of 100μF in parallel with the supercapacitor as shown in
Figure 3.
LTC3225
LTC3225-1
10
COUT
CX
GND
Charging a Single Supercapacitor
3
C1
8, 11
C2
VOUT
CSUP
3225 F03
C1 = C2 ≥ 100μF
Figure 3. Charging a Single Supercapacitor
3225fb
10
LTC3225/LTC3225-1
TYPICAL APPLICATION
5V Supercapacitor Back-Up Supply
Q2
Si4421DY
LTM4616
VIN1 VOUT1
VIN
5V
VIN2
C6
100μF
FB1
R3
4.78k
C5
22μF
Q1
Si4421DY
1.8V
GND ITHM1
1.2V
VOUT2
C7
100μF
FB2
VIN
COUT
C+
C1
1μF
C4
2.2μF
CX
LTC3225
LTC3225-1
GND
C–
R2
10k
C2
10F
LTC4412
VIN SENSE
C3
10F
GND GATE
CTL
C8
100μF
3225 TA02
ITHM2
GND
R2
470k
STAT
SHDN
VSEL
PROG
R1
12k
3225fb
11
LTC3225/LTC3225-1
PACKAGE DESCRIPTION
DDB Package
10-Lead Plastic DFN (3mm × 2mm)
(Reference LTC DWG # 05-08-1722 Rev Ø)
0.64 p0.05
(2 SIDES)
3.00 p0.10
(2 SIDES)
R = 0.05
TYP
0.70 p0.05
2.55 p0.05
1.15 p0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
2.39 p0.05
(2 SIDES)
PIN 1 BAR
TOP MARK
(SEE NOTE 6)
0.200 REF
RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS
R = 0.115
TYP
6
0.40 p 0.10
10
2.00 p0.10
(2 SIDES)
0.75 p0.05
0.64 p 0.05
(2 SIDES)
5
0.25 p 0.05
0 – 0.05
PIN 1
R = 0.20 OR
0.25 s 45o
CHAMFER
1
(DDB10) DFN 0905 REV Ø
0.50 BSC
2.39 p0.05
(2 SIDES)
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO VERSION (WECD-1) IN JEDEC PACKAGE OUTLINE M0-229
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
3225fb
12
LTC3225/LTC3225-1
REVISION HISTORY
(Revision history begins at Rev B)
REV
DATE
DESCRIPTION
PAGE NUMBER
B
6/10
Updated Note 3 in Electrical Characteristics section.
2, 3
Updates to Pins 8 and 11 in Pin Functions.
5
Update to text in Layout Considerations section.
10
Updated Typical Application and Related Parts.
14
3225fb
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
13
LTC3225/LTC3225-1
TYPICAL APPLICATION
12V Supercapacitor Back-Up Supply
LT3740
HIGH EFFICIENCY
DOWN CONVERTER
D1
CSHD6-40C
DPAK
VIN
12V
VIN+
+
GND
C1
47μF
25V
DCAP
VOUT
LT3740
GND
VOUT
1.8V
10A
GND
GND
*
CHARGER 3
C2
1μF
10V
VIN
COUT
LTC3225/
LTC3225-1
C+
CX
C–
GND
10A
D2
CMSH3-20
VBIAS
3.3V
C5
10μF
GND
1
M4
Si4410DY
D3
CMSH3-20
CHARGER 2
D4
CMSH3-20
VIN
COUT
LTC3225/
LTC3225-1
C+
CX
C3
1μF
10V
8
VM
VCC
LTC2915
7
2
SEL1 SEL2
6
3
TOL/MR RT
5
4
GND
RST
R7
10k
R1
2k
C6
0.1μF
R6
1k
R2
100k
8
PGND OUT
LTC4441-1
7
2
SGND DRVCC
6
3
IN
VIN
5
4
EN/SHDN FB
C–
1
M3
Si4410DY
R3
332k
R4
84.5k
M2
IRF7424
*
GND
R5
1k
M1
IRF7424
CHARGER 1
C7
10μF
C4
1μF
10V
VIN
COUT
LTC3225/
LTC3225-1
C+
CX
C–
GND
3225 TA03
* REQUIRES PIN 8 (GND) AND EXPOSED PAD TO BE CONNECTED TO A
THERMAL PAD ISOLATED FROM THE SYSTEM GROUND.
RELATED PARTS
PART NUMBER
LTC1751-3.3/LTC1751-5
LTC3200
LTC3203/LTC3203B/
LTC3203B-1/LTC3203-1
LTC3204/LTC3204B-3.3/
LTC3204-5
LTC3221/LTC3221-3.3/
LTC3221-5
LTC3240-3.3/LTC3240-2.5
LT®3420/LT3420-1
LT3468/LT3468-1/
LT3468-2
LTC3484-0/LTC3484-1/
LTC3484-2
LT3485-0/LT3485-1/
LT3485-2/LT3485-3
LT3750
LT3751
DESCRIPTION
Micropower 5V/3.3V Doubler Charge Pumps
Constant Frequency Doubler Charge Pump
500mA Low Noise High Efficiency Dual Mode
Step-Up Charge Pumps
Low Noise Regulating Charge Pumps
COMMENTS
IQ = 20μA, Up to 100mA Output, MS-8 Package
Low Noise, 5V Output or Adjustable
Micropower Regulated Charge Pump
Up to 60mA Output
Step-Up/Step-Down Regulated Charge Pumps
1.4A/1A Photoflash Capacitor Charger with
Automatic Top-Off
1.4A/1A/0.7A, Photoflash Capacitor Charger
Up to 150mA Output
Charges 220μF to 320V in 3.7 Seconds from 5V, VIN: 2.2V to 16V,
ISD < 1μA, 10-Lead MS Package
VIN: 2.5V to 16V, Charge Time = 4.6 Seconds for the LT3468 (0V to 320V,
100μF, VIN = 3.6V), ISD < 1μA, ThinSOT™ Package
VIN: 1.8V to 16V, Charge Time = 4.6 Seconds for the LT3484-0 (0V to 320V,
100μF, VIN = 3.6V), ISD < 1μA, 2mm × 3mm 6-Lead DFN Package
VIN: 1.8V to 10V, Charge Time = 3.7 Seconds for the LT3485-0 (0V to 320V,
100μF, VIN = 3.6V), ISD < 1μA, 3mm × 3mm 10-Lead DFN Driver
1.4A/0.7A/1A, Photoflash Capacitor Charger
1.4A/0.7A/1A/2A Photoflash Capacitor Charger
with Output Voltage Monitor and Integrated
IGBT
Capacitor Charger Controller
Capacitor Controller with Regulation
VIN: 2.7V to 5.5V, 3mm × 3mm 10-Lead DFN Package
Up to 150mA (LTC3204-5), Up to 50mA (LTC3204-3.3)
Charges Any Size Capacitor, 10-Lead MS Package
Charges Any Size Capacitor, 4mm × 5mm QFN-20 Package
3225fb
14 Linear Technology Corporation
LT 0610 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2008