ESDALC5-4BN4 4-line bidirectional Transil™, transient voltage surge suppressor for ESD protection Datasheet production data Features ■ 4 bidirectional Transil diodes ■ Breakdown voltage VBR = 5.5 V min. ■ Low leakage current < 60 nA ■ Very small PCB area: 0.8 mm² ■ 400 µm pitch micro-package ■ Lead-free and RoHS package µQFN-4L Complies with the following standards ■ Figure 1. Functional diagram (top view) IEC 61000-4-2 level 4 – 15 kV (air discharge) – 8 kV (contact discharge) I/O4 I/O1 Applications GND Where transient overvoltage protection in ESD sensitive equipment is required, such as: I/O2 ■ Mobile phones ■ Portable multimedia devices and accessories ■ Computers, tablets and peripherals ■ Set top boxes ■ Audio equipment I/O3 Description The ESDALC5-4BN4 is a monolithic array designed to protect up to 4 bidirectional lines against ESD transients. The device is ideal for applications where both reduced printed circuit board space and high ESD protection levels are required. January 2013 This is information on a product in full production. Doc ID 023686 Rev 1 1/10 www.st.com 10 Characteristics 1 ESDALC5-4BN4 Characteristics Absolute maximum ratings (Tamb = 25 °C) Table 1. Symbol Parameter Value Unit VPP Peak pulse voltage, IEC 61000-4-2, level 4: Contact discharge Air discharge 30 30 kV Ipp Peak pulse current (8/20 µs) 4 A PPP Peak pulse power dissipation (8/20 µs)(1) 60 W Operating junction temperature range -40 to 125 °C Storage temperature range -65 + 150 °C 260 °C Tj Tstg TL GND to I/O Maximum lead temperature for soldering during 10 s 1. For a surge greater than the maximum values, the diode will fail in short-circuit. Figure 2. Electrical characteristics (definitions) Symbol VBR VCL IRM VRM IPP Table 2. = = = = = Electrical characteristics (values, Tamb = 25 °C) Symbol VBR IRM VCL CLINE 2/10 Parameter Breakdown voltage Clamping voltage Leakage current @ VRM Stand-off voltage Peak pulse current Test conditions Min. Typ. IR = 1 mA, I/O to GND 11 13 IR = 1 mA, GND to I/O 5.5 8 VRM = 5 V Max. V 1 60 Ipp = 1 A, 8/20 µs, I/O to GND 18 Ipp = 1 A, 8/20 µs, GND to I/O 14.5 VR = 0 V, F = 1 MHz, Vosc = 30 mV Doc ID 023686 Rev 1 Unit nA V 13 15 pF ESDALC5-4BN4 Figure 3. 100 Characteristics Leakage current versus junction temperature (typical values) Figure 4. IR (nA) 15 Junction capacitance versus reverse voltage applied (typical values) C (PF) 14 Vr=5V IO/GND GND/IO 13 TJ=25°C IO/GND IO/IO 12 10 11 10 9 8 1 7 6 5 4 0,1 3 2 T j (°C) VR(V) 1 0 0,01 25 50 Figure 5. 75 100 125 0 150 ESD response to IEC 61000-4-2 (+8 kV contact discharge) 1 2 Figure 6. 3 4 5 6 ESD response to IEC 61000-4-2 (-8 kV contact discharge) 10 V/div 10 V/div 41 V -8 V -11 V -12 V 18 V 17 V 14 V -36 V 20 ns/div 30 nS Figure 7. 0 60 nS 20 ns/div 30 nS 100 nS S21 attenuation measurements Figure 8. S21 (dB) 0 -3 -10 -6 -20 -9 -30 -12 -40 -15 -18 -21 -24 -27 Pass band attenuation 0.05 dB 3-dB point 484 MHz -60 Analog crosstalk measurements between channels Average Performance (50 Ω System) Attenuation @ 1MHz 100 dB Attenuation @ 100MHz 66 dB Min Attenuation 33 dB @ 6 GHz @ Hz -70 -80 -90 >6 dB Attenuation 7 dB @ 900 MHz (0.8– 4GHz) 15 dB @ 1.8 GHz -30 100 nS dB -50 Average Performance (50 Ω System) 60 nS -100 -110 -33 F/Hz -36 100k 1M 10M 100M 1G -120 100k 10G Doc ID 023686 Rev 1 F/Hz 1M 10M 100M 1G 10G 3/10 Ordering information scheme 2 ESDALC5-4BN4 Ordering information scheme Figure 9. Ordering information scheme ESDA LC 5 4 B N4 ESD array Low capacitance Breakdown voltage 5 = 5.5 Volts min Number of lines 4 = 4 lines Direction B = Bidirectional Package N4 = µQFN-4L 4/10 Doc ID 023686 Rev 1 ESDALC5-4BN4 3 Package information Package information ● Epoxy meets UL94, V0 ● Lead-free package In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. µQFN-4L dimensions Table 3. Dimensions Ref. D D2 e 2 Index area 1 E2 E L 3 4 L1 b Millimeters Inches Min. Typ. Max. Min. Typ. Max. A 0.31 0.38 0.40 0.012 0.015 0.016 A1 0.00 0.02 0.05 0.00 b 0.10 0.15 0.20 0.004 0.006 0.008 D 0.70 0.80 0.90 0.028 0.031 0.035 D2 0.50 0.58 0.65 0.020 0.023 0.026 e 0.35 0.40 0.45 0.014 0.016 0.018 E 0.90 1.00 1.10 0.035 0.039 0.043 E2 0.15 0.20 0.25 0.006 0.008 0.010 L 0.18 0.23 0.28 0.007 0.009 0.011 L1 0.00 - 0.05 0.00 0.0008 0.002 A A1 - 0.002 Figure 10. Footprint dimensions (in mm) Figure 11. Marking 0.4 0.43 0.2 0.58 L 0.17 1.4 0.18 0.58 Note: Product marking may be rotated by multiples of 90° for assembly plant differentiation. In no case should this product marking be used to orient the component for its placement on a PCB. Only pin 1 mark is to be used for this purpose. Doc ID 023686 Rev 1 5/10 Package information ESDALC5-4BN4 Figure 12. Tape and reel specifications Dot identifying Pin A1 location 2.0 Ø 1.55 4.0 3.5 2.0 0.63 All dimensions are typical values in mm 6/10 User direction of unreeling Doc ID 023686 Rev 1 L L L 0.89 L L L L 8.0 1.07 1.75 0.22 ESDALC5-4BN4 Recommendation on PCB assembly 4 Recommendation on PCB assembly 4.1 Stencil opening design Reference design ● Stencil opening thickness: 100 µm ● Stencil opening for leads: Opening to footprint ratio is 100%. Figure 13. Recommended stencil window position 430 µm T=100 µm and opening ratio is 100% 180 µm 580 µm 200 µm Footprint Stencil window Footprint 4.2 4.3 Solder paste 1. Halide-free flux qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste is recommended. 3. Offers a high tack force to resist component movement during high speed. 4. Solder paste with fine particles: powder particle size is 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. Doc ID 023686 Rev 1 7/10 Recommendation on PCB assembly 4.4 4.5 ESDALC5-4BN4 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. PCB design preference 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Reflow profile Figure 14. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 8/10 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Doc ID 023686 Rev 1 ESDALC5-4BN4 5 Ordering information Ordering information Table 4. Ordering information Order code Marking Package Weight Base qty Delivery mode ESDALC5-4BN4 L(1) µQFN-4L 0.77 mg 10 000 Tape and reel 1. The marking can be rotated by multiples of 90° to differentiate assembly location 6 Revision history Table 5. Document revision history Date Revision 18-Jan-2013 1 Changes Initial release. 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