ADuCM302x Mixed-Signal Control Processor Hardware Reference (Rev. 0.3) PDF

ADuCM302x Mixed-Signal Control
Processor Hardware Reference
Revision 0.3, November 2015
Part Number
82-100125-01
Analog Devices, Inc.
One Technology Way
Norwood, MA 02062-9106
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without prior, express written consent from Analog Devices, Inc.
Printed in the USA.
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
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Contents
Introduction
ADuCM302x Mixed Control Processor Features ........................................................................................... 1–1
ADuCM302x Functional Description............................................................................................................ 1–2
ADuCM302x Block Diagram ..................................................................................................................... 1–2
Memory Architecture.................................................................................................................................. 1–2
SRAM Region ............................................................................................................................................ 1–2
System Region ............................................................................................................................................ 1–4
Flash Controller.......................................................................................................................................... 1–4
Cache Controller ........................................................................................................................................ 1–4
ARM Cortex-M3 Memory Subsystem ........................................................................................................ 1–4
Booting ...................................................................................................................................................... 1–5
Security Features......................................................................................................................................... 1–5
Processor Safety Features ............................................................................................................................ 1–5
Multi Parity Bit Protected L1 Memories..................................................................................................... 1–5
Programmable GPIOs ................................................................................................................................ 1–6
Timers ........................................................................................................................................................ 1–6
Power Management .................................................................................................................................... 1–6
Clocking ..................................................................................................................................................... 1–7
Real Time Clock......................................................................................................................................... 1–7
System Debug ............................................................................................................................................ 1–8
Beeper Driver ............................................................................................................................................. 1–8
Crypto Accelerator...................................................................................................................................... 1–8
CRC Accelerator......................................................................................................................................... 1–9
Random Number Generator....................................................................................................................... 1–9
Serial Ports ................................................................................................................................................. 1–9
SPI Ports .................................................................................................................................................... 1–9
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UART Ports.............................................................................................................................................. 1–10
Signal Chains............................................................................................................................................ 1–10
Development Tools................................................................................................................................... 1–10
ADuCM302x Registers List......................................................................................................................... 1–11
General-Purpose I/O (GPIO)
GPIO Features............................................................................................................................................... 2–1
GPIO Functional Description........................................................................................................................ 2–1
ADuCM302x GPIO Register List .............................................................................................................. 2–1
ADuCM302x GP I/O Multiplexing ........................................................................................................... 2–2
GPIO Block Diagram................................................................................................................................. 2–4
GPIO Operating Modes ................................................................................................................................ 2–5
IO Pull-Up or Pull-Down Enable ............................................................................................................... 2–5
IO Data In ................................................................................................................................................. 2–5
IO Data Out............................................................................................................................................... 2–5
Bit Set......................................................................................................................................................... 2–5
Bit Clear ..................................................................................................................................................... 2–5
Bit Toggle ................................................................................................................................................... 2–5
IO Data Output Enable.............................................................................................................................. 2–5
Interrupts ................................................................................................................................................... 2–5
Interrupt Polarity........................................................................................................................................ 2–6
Interrupt A Enable...................................................................................................................................... 2–6
Interrupt B Enable...................................................................................................................................... 2–6
Interrupt Status .......................................................................................................................................... 2–6
GPIO Programming Model ........................................................................................................................... 2–7
ADuCM302x GPIO Register Descriptions ................................................................................................... 2–7
Port Configuration .................................................................................................................................... 2–8
Port data out clear ................................................................................................................................... 2–10
Port drive strength select .......................................................................................................................... 2–11
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Port Input Path Enable ............................................................................................................................ 2–12
Port interrupt A enable ............................................................................................................................ 2–13
Port interrupt B enable ............................................................................................................................ 2–14
Port registered data input ........................................................................................................................ 2–15
Port interrupt Status ................................................................................................................................ 2–16
Port output enable ................................................................................................................................... 2–17
Port data output ...................................................................................................................................... 2–18
Port output pullup/pulldown enable ........................................................................................................ 2–19
Port interrupt polarity ............................................................................................................................. 2–20
Port data out set ...................................................................................................................................... 2–21
Port pin toggle ......................................................................................................................................... 2–22
Events (Interrupts and Exceptions)
Events Features .............................................................................................................................................. 3–1
ADuCM302x XINT Register List .............................................................................................................. 3–1
Events Interrupts and Exceptions................................................................................................................... 3–1
Cortex Exceptions....................................................................................................................................... 3–1
Nested Vectored Interrupt Controller ......................................................................................................... 3–2
Handling Interrupt Registers...................................................................................................................... 3–4
External Interrupt Configuration................................................................................................................ 3–5
ADuCM302x XINT Register Descriptions ................................................................................................... 3–5
External Interrupt configuration ................................................................................................................ 3–6
External Interrupt clear ............................................................................................................................. 3–9
External Wakeup Interrupt Status register ............................................................................................... 3–10
Non-maskable interrupt clear .................................................................................................................. 3–12
Power Management (PMG)
PWR Features................................................................................................................................................ 4–1
PWR Functional Description......................................................................................................................... 4–1
ADuCM302x PMG Register List ............................................................................................................... 4–1
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ADuCM302x PMG_TST Register List ...................................................................................................... 4–2
Power-up Sequence..................................................................................................................................... 4–2
PWR Operating Modes ................................................................................................................................. 4–2
Active Mode ............................................................................................................................................... 4–3
Flexi Mode.................................................................................................................................................. 4–3
Hibernate Mode ......................................................................................................................................... 4–3
Memory Configuration .............................................................................................................................. 4–4
Shutdown Mode ......................................................................................................................................... 4–4
Programming Sequence ................................................................................................................................. 4–5
Configuring Hibernate Mode ..................................................................................................................... 4–5
Configuring Shutdown Mode..................................................................................................................... 4–6
Wake-up Sequence ......................................................................................................................................... 4–6
Monitor Voltage Control ............................................................................................................................... 4–7
ADuCM302x PMG Register Descriptions .................................................................................................... 4–8
HPBUCK control .................................................................................................................................... 4–10
Power Supply Monitor Interrupt Enable .................................................................................................. 4–11
Power supply monitor status .................................................................................................................... 4–13
Key protection for PWRMOD and SRAMRET ...................................................................................... 4–15
Power Mode Register ............................................................................................................................... 4–16
Reset status .............................................................................................................................................. 4–17
SHUTDOWN Status Register ................................................................................................................ 4–18
Control for Retention SRAM during HIBERNATE Mode ...................................................................... 4–19
ADuCM302x PMG_TST Register Descriptions ........................................................................................ 4–19
CLEAR GPIO AFTER SHUTDOWN MODE ...................................................................................... 4–20
SCRATCH PAD SAVED IN BATTERY DOMAIN ............................................................................... 4–21
SCRATCH PAD IMAGE ........................................................................................................................ 4–22
Control for SRAM parity and instruction SRAM .................................................................................... 4–23
Initialization Status Register .................................................................................................................... 4–25
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System Clocks (SCLK)
System Clock Features ................................................................................................................................... 5–1
System Clock Functional Description ............................................................................................................ 5–2
ADuCM302x CLKG_OSC Register List.................................................................................................... 5–2
ADuCM302x CLKG_CLK Register List .................................................................................................... 5–2
System Clock Block Diagram ..................................................................................................................... 5–2
Clock Muxes............................................................................................................................................... 5–3
Clock Dividers............................................................................................................................................ 5–4
Clock Gating .............................................................................................................................................. 5–5
PLL Settings .................................................................................................................................................. 5–5
PLL Interrupts............................................................................................................................................ 5–6
PLL Programming Sequence ...................................................................................................................... 5–6
System Clock Interrupts and Exceptions........................................................................................................ 5–7
System Clock Programming Model................................................................................................................ 5–7
Oscillators .................................................................................................................................................. 5–7
Crystal Programming ................................................................................................................................. 5–8
Oscillator Programming ............................................................................................................................. 5–9
Setting the System Clocks.............................................................................................................................. 5–9
Set System Clock to PLL Input Source ....................................................................................................... 5–9
Set System Clock to XTAL ....................................................................................................................... 5–12
Changing System Clock Source ................................................................................................................ 5–14
ADuCM302x CLKG_OSC Register Descriptions ...................................................................................... 5–15
Oscillator Control ................................................................................................................................... 5–16
Key Protection for OSCCTRL ................................................................................................................ 5–19
ADuCM302x CLKG_CLK Register Descriptions ...................................................................................... 5–19
Misc clock settings ................................................................................................................................... 5–20
Clock dividers .......................................................................................................................................... 5–22
System PLL ............................................................................................................................................. 5–24
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User clock gating control ......................................................................................................................... 5–26
Clocking status ........................................................................................................................................ 5–28
Direct Memory Access (DMA)
DMA Features ............................................................................................................................................... 6–1
DMA Functional Description ........................................................................................................................ 6–2
ADuCM302x DMA Register List............................................................................................................... 6–2
DMA Architectural Concepts ..................................................................................................................... 6–3
DMA Operating Modes................................................................................................................................. 6–4
Channel Control Data Structure................................................................................................................. 6–4
Source Data End Pointer ............................................................................................................................ 6–6
Destination Data End Pointer .................................................................................................................... 6–6
Control Data Configuration ....................................................................................................................... 6–6
DMA Priority ............................................................................................................................................. 6–9
Address Calculation .................................................................................................................................... 6–9
Address Decrement..................................................................................................................................... 6–9
Endian Operation..................................................................................................................................... 6–10
Channel Enable/Disable ........................................................................................................................... 6–11
Master Enable........................................................................................................................................... 6–12
Power-down Considerations ..................................................................................................................... 6–12
DMA Transfer Types ................................................................................................................................... 6–13
Invalid ...................................................................................................................................................... 6–13
Basic ......................................................................................................................................................... 6–13
Auto-Request............................................................................................................................................ 6–14
Ping-Pong................................................................................................................................................. 6–14
DMA Interrupts and Exceptions.................................................................................................................. 6–16
Memory Scatter-Gather............................................................................................................................ 6–16
Peripheral Scatter-Gather ......................................................................................................................... 6–18
Error Management ................................................................................................................................... 6–20
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DMA Programming Model.......................................................................................................................... 6–20
Programming Guidelines.......................................................................................................................... 6–21
ADuCM302x DMA Register Descriptions ................................................................................................. 6–21
DMA channel alternate control data base pointer .................................................................................... 6–23
DMA channel primary-alternate clear ..................................................................................................... 6–24
DMA channel primary-alternate set ........................................................................................................ 6–25
DMA channel bytes swap enable clear ..................................................................................................... 6–26
DMA channel bytes swap enable set ........................................................................................................ 6–27
DMA Configuration ................................................................................................................................ 6–28
DMA channel destination address decrement enable clear ....................................................................... 6–29
DMA channel destination address decrement enable set .......................................................................... 6–30
DMA channel enable clear ....................................................................................................................... 6–31
DMA channel enable set .......................................................................................................................... 6–32
DMA Per Channel Error Clear ................................................................................................................ 6–33
DMA bus error clear ................................................................................................................................ 6–34
DMA Per Channel Invalid Descriptor Clear ............................................................................................ 6–35
DMA channel primary control data base pointer ..................................................................................... 6–36
DMA channel priority clear ..................................................................................................................... 6–37
DMA channel priority set ........................................................................................................................ 6–38
DMA Controller Revision ID .................................................................................................................. 6–39
DMA channel request mask clear ............................................................................................................ 6–40
DMA channel request mask set ............................................................................................................... 6–41
DMA channel source address decrement enable clear .............................................................................. 6–42
DMA channel source address decrement enable set ................................................................................. 6–43
DMA Status ............................................................................................................................................ 6–44
DMA channel software request ................................................................................................................ 6–45
Reset (RST)
ADuCM302x Reset Register Description ...................................................................................................... 7–2
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Debug (DBG)
DBG Features ................................................................................................................................................ 8–1
DBG Functional Description......................................................................................................................... 8–1
ADuCM302x SYS Register List.................................................................................................................. 8–1
Serial Wire Interface ................................................................................................................................... 8–2
DBG Operating Modes ................................................................................................................................. 8–3
Serial Wire Protocol.................................................................................................................................... 8–3
Debug Access Port (DAP).............................................................................................................................. 8–4
Debug Port .................................................................................................................................................... 8–5
ADuCM302x SYS Register Descriptions ...................................................................................................... 8–5
ADI Identification ..................................................................................................................................... 8–6
Chip Identifier ........................................................................................................................................... 8–7
Serial Wire Debug Enable .......................................................................................................................... 8–8
CRYPTO
Crypto Features ............................................................................................................................................. 9–1
Crypto Functional Description ...................................................................................................................... 9–2
ADuCM302x CRYPT Register List............................................................................................................ 9–2
Crypto Block Diagram ............................................................................................................................... 9–3
Crypto Operating Modes............................................................................................................................... 9–4
DMA Capability......................................................................................................................................... 9–5
Core Transfer.............................................................................................................................................. 9–5
Endianness ................................................................................................................................................. 9–5
INPUT_READY_INT ............................................................................................................................... 9–6
OUTPUT_READY_INT........................................................................................................................... 9–6
SHA_DONE .............................................................................................................................................. 9–6
IN_OVF_INT............................................................................................................................................ 9–6
OUT_UDF_INT ....................................................................................................................................... 9–6
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Crypto Error Conditions ............................................................................................................................... 9–6
Crypto Data Transfer..................................................................................................................................... 9–7
Crypto Data Rate .......................................................................................................................................... 9–7
Crypto Status Bits.......................................................................................................................................... 9–8
IN_DATA_CNT/OUT_DATA_CNT........................................................................................................ 9–8
HASH_READY.......................................................................................................................................... 9–8
HASH_BUSY............................................................................................................................................. 9–8
IN_OVF_INT/OUT_UDF_INT............................................................................................................... 9–8
Crypto Keys................................................................................................................................................... 9–8
Key Length ................................................................................................................................................. 9–8
Key Programming ...................................................................................................................................... 9–8
Crypto Power Saver Mode ............................................................................................................................. 9–9
DATALENGTH......................................................................................................................................... 9–9
PREFIXLENGTH...................................................................................................................................... 9–9
CRYPT_NONCEx..................................................................................................................................... 9–9
CRYPT_CTRINT.................................................................................................................................... 9–10
Crypto Programming Model........................................................................................................................ 9–10
Enabling CRYPTO................................................................................................................................... 9–11
Key Programming .................................................................................................................................... 9–11
Data Transfer............................................................................................................................................ 9–11
Block Mode of Operation ......................................................................................................................... 9–11
Mode Specific Parameters ......................................................................................................................... 9–11
Payload and Associated Data Formatting.................................................................................................. 9–12
Programming Flow Description for SHA Operation ................................................................................ 9–12
Software Operation in CCM Mode .......................................................................................................... 9–13
Simultaneous SHA+Block Mode of Operation ......................................................................................... 9–15
ADuCM302x CRYPT Register Descriptions .............................................................................................. 9–16
Key Bits[ 31:0 ] ....................................................................................................................................... 9–18
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Key Bits [ 63:32 ] .................................................................................................................................... 9–19
Key Bits [ 95:64 ] .................................................................................................................................... 9–20
Key Bits [ 127:96 ] .................................................................................................................................. 9–21
Key Bits [ 159:128 ] ................................................................................................................................ 9–22
Key Bits [ 191:160 ] ................................................................................................................................ 9–23
Key Bits [ 223:192 ] ................................................................................................................................ 9–24
Key Bits [ 255:224 ] ................................................................................................................................ 9–25
NUM_VALID_BYTES ........................................................................................................................... 9–26
Configuration Register ............................................................................................................................ 9–27
Counter Initialization Vector ................................................................................................................... 9–30
Payload Data Length ............................................................................................................................... 9–31
Input Buffer ............................................................................................................................................ 9–32
Interrupt Enable Register ........................................................................................................................ 9–33
Nonce Bits [31:0] .................................................................................................................................... 9–34
Nonce Bits [63:32] .................................................................................................................................. 9–35
Nonce Bits [95:64] .................................................................................................................................. 9–36
Nonce Bits [127:96] ................................................................................................................................ 9–37
Output Buffer .......................................................................................................................................... 9–38
Authentication Data Length .................................................................................................................... 9–39
SHA Bits [ 31:0 ] ..................................................................................................................................... 9–40
SHA Bits [ 63:32 ] ................................................................................................................................... 9–41
SHA Bits [ 95:64 ] ................................................................................................................................... 9–42
SHA Bits [ 127:96 ] ................................................................................................................................. 9–43
SHA Bits [ 159:128 ] ............................................................................................................................... 9–44
SHA Bits [ 191:160 ] ............................................................................................................................... 9–45
SHA Bits [ 223:192] ................................................................................................................................ 9–46
SHA Bits [ 255:224 ] ............................................................................................................................... 9–47
SHA Last Word and Valid Bits Information ............................................................................................. 9–48
Status Register ......................................................................................................................................... 9–49
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Serial Peripheral Interface (SPI)
SPI Features................................................................................................................................................. 10–1
SPI Functional Description.......................................................................................................................... 10–2
ADuCM302x SPI Register List ................................................................................................................ 10–2
MISO (Master In, Slave Out) Pin............................................................................................................. 10–3
MOSI (Master Out, Slave In) Pin............................................................................................................. 10–3
SCLK (Serial Clock I/O) Pin .................................................................................................................... 10–3
Chip Select (CS I/O) Pin.......................................................................................................................... 10–3
SPI Block Diagram................................................................................................................................... 10–4
SPI Operating Modes .................................................................................................................................. 10–4
Wired-OR Mode (WOM) ........................................................................................................................ 10–4
General Instructions.............................................................................................................................. 10–4
SPI and Power-down Mode ...................................................................................................................... 10–5
SPIH vs SPI0/SPI1................................................................................................................................... 10–5
Interfacing with SPI Slaves on Converters/Flash....................................................................................... 10–5
Flow Control ............................................................................................................................................ 10–7
Three Pin Mode ....................................................................................................................................... 10–8
SPI Data Transfer ........................................................................................................................................ 10–9
Tx Initiated Transfer................................................................................................................................. 10–9
Rx Initiated Transfer................................................................................................................................. 10–9
Transfers in Slave Mode.......................................................................................................................... 10–10
SPI Data Underflow and Overflow......................................................................................................... 10–11
SPI Interrupts and Exceptions ................................................................................................................... 10–12
Tx Interrupt ........................................................................................................................................... 10–12
Rx Interrupt ........................................................................................................................................... 10–12
Underflow/Overflow Interrupts.............................................................................................................. 10–13
SPI Programming Model ........................................................................................................................... 10–13
SPI DMA ............................................................................................................................................... 10–13
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ADuCM302x SPI Register Descriptions ................................................................................................... 10–15
Transfer byte count ................................................................................................................................ 10–16
Chip-Select control for multi-slave connections ..................................................................................... 10–17
Chip-Select Override ............................................................................................................................. 10–18
SPI configuration 1 ............................................................................................................................... 10–19
SPI baud rate selection .......................................................................................................................... 10–22
SPI DMA enable ................................................................................................................................... 10–23
FIFO Status ........................................................................................................................................... 10–24
Flow Control ......................................................................................................................................... 10–25
SPI configuration 2 ............................................................................................................................... 10–26
Read Control ......................................................................................................................................... 10–29
Receive .................................................................................................................................................. 10–31
Status ..................................................................................................................................................... 10–32
Transmit ................................................................................................................................................ 10–35
Wait timer for flow control .................................................................................................................... 10–36
Serial Port (SPORT)
SPORT Features .......................................................................................................................................... 11–1
Signal Description ....................................................................................................................................... 11–2
SPORT Functional Description................................................................................................................... 11–3
ADuCM302x SPORT Register List.......................................................................................................... 11–3
SPORT Block Diagram ............................................................................................................................ 11–3
Multiplexer Logic ..................................................................................................................................... 11–4
Serial Clock .............................................................................................................................................. 11–7
Frame Sync ............................................................................................................................................... 11–8
Frame Sync Options .............................................................................................................................. 11–9
Sampling Edge........................................................................................................................................ 11–11
Premature Frame Sync Error Detection .................................................................................................. 11–12
Serial Word Length................................................................................................................................. 11–13
Number of Transfers............................................................................................................................... 11–13
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SPORT Transfer..................................................................................................................................... 11–14
SPORT Power Management................................................................................................................... 11–15
SPORT Operating Modes ......................................................................................................................... 11–15
Mode selection ....................................................................................................................................... 11–16
SPORT Data Transfer ............................................................................................................................... 11–17
Single Word (Core) Transfers.................................................................................................................. 11–17
DMA Transfers....................................................................................................................................... 11–18
SPORT Data Buffers ................................................................................................................................. 11–18
Data Buffer Status .................................................................................................................................. 11–18
Data Buffer Packing ............................................................................................................................... 11–19
SPORT Interrupts and Exceptions............................................................................................................. 11–19
Error Detection ...................................................................................................................................... 11–20
System Transfer Interrupts ..................................................................................................................... 11–20
Transfer Finish Interrupt (TFI)............................................................................................................... 11–21
SPORT Programming Model .................................................................................................................... 11–21
ADuCM302x SPORT Register Descriptions ............................................................................................ 11–21
Half SPORT 'A' Control Register ......................................................................................................... 11–23
Half SPORT 'B' Control Register ......................................................................................................... 11–28
Half SPORT 'A' Divisor Register .......................................................................................................... 11–32
Half SPORT 'B' Divisor Register .......................................................................................................... 11–33
Half SPORT A's Interrupt Enable register ............................................................................................ 11–34
Half SPORT B's Interrupt Enable register ............................................................................................ 11–36
Half SPORT A Number of transfers register ......................................................................................... 11–38
Half SPORT B Number of transfers register ......................................................................................... 11–39
Half SPORT 'A' Rx Buffer Register ....................................................................................................... 11–40
Half SPORT 'B' Rx Buffer Register ....................................................................................................... 11–41
Half SPORT 'A' Status register ............................................................................................................. 11–42
Half SPORT 'B' Status register ............................................................................................................. 11–44
Half SPORT 'A' CONVT width ........................................................................................................... 11–46
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Half SPORT 'B' CONVT width register ............................................................................................... 11–47
Half SPORT 'A' Tx Buffer Register ...................................................................................................... 11–48
Half SPORT 'B' Tx Buffer Register ...................................................................................................... 11–49
ADC Subsystem
ADC Features .............................................................................................................................................. 12–1
ADC Functional Description ....................................................................................................................... 12–1
ADuCM302x ADC Register List.............................................................................................................. 12–2
ADC Subsystem Components .................................................................................................................. 12–3
ADC Voltage Reference Selection ............................................................................................................. 12–4
Digital Offset Calibration......................................................................................................................... 12–5
Powering the ADC ................................................................................................................................... 12–5
Hibernate ................................................................................................................................................. 12–6
Sampling and Conversion Time ............................................................................................................... 12–7
Operation ................................................................................................................................................. 12–8
Programming Flow................................................................................................................................. 12–10
Temperature Sensor ................................................................................................................................ 12–12
Battery Monitoring................................................................................................................................. 12–15
Over Sampling........................................................................................................................................ 12–15
Averaging Function................................................................................................................................. 12–15
ADC Digital Comparator....................................................................................................................... 12–17
ADuCM302x ADC Register Descriptions ................................................................................................ 12–19
Alert Indication ..................................................................................................................................... 12–22
Averaging Configuration ....................................................................................................................... 12–23
Battery Monitoring Result ..................................................................................................................... 12–24
Calibration Word ................................................................................................................................... 12–25
ADC Configuration ............................................................................................................................... 12–26
Reference Buffer Low Power Mode ........................................................................................................ 12–28
Conversion Result Channel 0 ................................................................................................................ 12–29
Conversion Result Channel 1 ................................................................................................................ 12–30
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Conversion Result Channel 2 ................................................................................................................ 12–31
Conversion Result Channel 3 ................................................................................................................ 12–32
Conversion Result Channel 4 ................................................................................................................ 12–33
Conversion Result Channel 5 ................................................................................................................ 12–34
Conversion Result Channel 6 ................................................................................................................ 12–35
Conversion Result Channel 7 ................................................................................................................ 12–36
ADC Conversion Configuration ............................................................................................................ 12–37
ADC Conversion Time .......................................................................................................................... 12–38
DMA Output Register ........................................................................................................................... 12–39
Channel 0 Hysteresis ............................................................................................................................. 12–40
Channel 1 Hysteresis ............................................................................................................................. 12–41
Channel 2 Hysteresis ............................................................................................................................. 12–42
Channel 3 Hysteresis ............................................................................................................................. 12–43
Interrupt Enable .................................................................................................................................... 12–44
Channel 0 High Limit ........................................................................................................................... 12–45
Channel 0 Low Limit ............................................................................................................................ 12–46
Channel 1 High Limit ........................................................................................................................... 12–47
Channel 1 Low Limit ............................................................................................................................ 12–48
Channel 2 High Limit ........................................................................................................................... 12–49
Channel 2 Low Limit ............................................................................................................................ 12–50
Channel 3 High Limit ........................................................................................................................... 12–51
Channel 3 Low Limit ............................................................................................................................ 12–52
Overflow of Output Registers ................................................................................................................ 12–53
ADC Power-up Time ............................................................................................................................. 12–55
ADC Status ........................................................................................................................................... 12–56
Value of R1p25 ...................................................................................................................................... 12–58
Value of R2p5 ........................................................................................................................................ 12–59
Value of R_virtual .................................................................................................................................. 12–60
Temperature Result 2 ............................................................................................................................ 12–61
Temperature Result ............................................................................................................................... 12–62
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Sampling Time for Temperature Sensor ................................................................................................ 12–63
Flash Controller (FLASH)
Flash Features .............................................................................................................................................. 13–1
ADuCM302x FLCC Register List ............................................................................................................ 13–1
Supported Features ................................................................................................................................... 13–2
Supported Commands.............................................................................................................................. 13–2
Protection and Integrity Features.............................................................................................................. 13–2
Flash Functional Description ....................................................................................................................... 13–3
Organization ............................................................................................................................................ 13–3
Flash Access .............................................................................................................................................. 13–5
Reading Flash ........................................................................................................................................ 13–6
Erasing Flash ......................................................................................................................................... 13–6
Writing Flash......................................................................................................................................... 13–6
Protection and Integrity.......................................................................................................................... 13–10
Integrity of Info Space......................................................................................................................... 13–10
User Space Protection.......................................................................................................................... 13–11
Runtime Configuration ....................................................................................................................... 13–11
Meta Data Configuration .................................................................................................................... 13–12
Signatures............................................................................................................................................ 13–13
Key Register ........................................................................................................................................ 13–14
ECC .................................................................................................................................................... 13–14
Clock and Timings ................................................................................................................................. 13–16
Flash Operating Modes.............................................................................................................................. 13–16
Sleep Mode............................................................................................................................................. 13–16
Power-down Mode Support.................................................................................................................... 13–16
Clock Gating .......................................................................................................................................... 13–17
Flash Interrupts and Exceptions................................................................................................................. 13–17
Flash Programming Model......................................................................................................................... 13–17
Programming Guidelines........................................................................................................................ 13–17
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ADuCM302x FLCC Register Descriptions ............................................................................................... 13–18
IRQ Abort Enable (upper bits) .............................................................................................................. 13–19
IRQ Abort Enable (lower bits) ............................................................................................................... 13–20
Command ............................................................................................................................................. 13–21
ECC Status (Address) ............................................................................................................................ 13–24
ECC Config ........................................................................................................................................... 13–25
Interrupt Enable .................................................................................................................................... 13–26
Key ........................................................................................................................................................ 13–27
WRITE Address .................................................................................................................................... 13–28
WRITE Lower Data .............................................................................................................................. 13–29
WRITE Upper Data .............................................................................................................................. 13–30
Lower Page Address ............................................................................................................................... 13–31
Upper Page Address ............................................................................................................................... 13–32
Signature ............................................................................................................................................... 13–33
Status ..................................................................................................................................................... 13–34
Time Parameter 0 .................................................................................................................................. 13–40
Time parameter 1 .................................................................................................................................. 13–42
User Configuration ................................................................................................................................ 13–43
Write Protection .................................................................................................................................... 13–44
Write Abort Address .............................................................................................................................. 13–46
Static Random Access Memory (SRAM)
SRAM Features ............................................................................................................................................ 14–1
SRAM Configuration .................................................................................................................................. 14–1
Instruction vs Data SRAM ....................................................................................................................... 14–2
SRAM Retention in Hibernate Mode ....................................................................................................... 14–2
SRAM Programming Model ........................................................................................................................ 14–2
Stack......................................................................................................................................................... 14–2
SRAM Parity ............................................................................................................................................... 14–3
xviii
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SRAM Initialization..................................................................................................................................... 14–3
Initialization in Cache and Instruction SRAM.......................................................................................... 14–4
ADuCM302x SRAM Register Description .................................................................................................. 14–4
Cyclic Redundancy Check (CRC)
CRC Features............................................................................................................................................... 15–1
CRC Functional Description ....................................................................................................................... 15–1
ADuCM302x CRC Register List .............................................................................................................. 15–1
CRC Block Diagram................................................................................................................................. 15–2
CRC Architectural Concepts .................................................................................................................... 15–2
CRC Operating Modes ................................................................................................................................ 15–2
Polynomial ............................................................................................................................................... 15–3
Reset and Hibernate Modes...................................................................................................................... 15–5
CRC Data Transfer ...................................................................................................................................... 15–5
CRC Interrupts and Exceptions ................................................................................................................... 15–5
CRC Programming Model........................................................................................................................... 15–5
CORE Access ........................................................................................................................................... 15–5
DMA Access ............................................................................................................................................. 15–6
Mirroring Options.................................................................................................................................... 15–7
ADuCM302x CRC Register Descriptions ................................................................................................... 15–7
CRC Control Register ............................................................................................................................. 15–9
Input Data Word Register ..................................................................................................................... 15–11
Programmable CRC Polynomial ............................................................................................................ 15–12
CRC Result Register .............................................................................................................................. 15–13
True Random Number Generator (TRNG)
TRNG Features ........................................................................................................................................... 16–1
TRNG Functional Description .................................................................................................................... 16–1
ADuCM302x RNG Register List ............................................................................................................. 16–1
ADuCM302x Mixed-Signal Control Processor Hardware Reference
xix
TRNG Block Diagram ............................................................................................................................. 16–1
TRNG Oscillator Counter ....................................................................................................................... 16–2
RNG Entropy and Surprisal ..................................................................................................................... 16–4
Oscillator Count Difference ..................................................................................................................... 16–5
TRNG Interrupts and Exceptions................................................................................................................ 16–5
ADuCM302x RNG Register Descriptions .................................................................................................. 16–5
RNG Control Register ............................................................................................................................. 16–7
RNG Data Register ................................................................................................................................. 16–8
RNG Sample Length Register .................................................................................................................. 16–9
Oscillator Count .................................................................................................................................... 16–10
Oscillator Difference .............................................................................................................................. 16–11
RNG Status Register ............................................................................................................................. 16–12
Beeper Driver (BEEP)
Beep Features............................................................................................................................................... 17–1
Beep Functional Description........................................................................................................................ 17–1
ADuCM302x BEEP Register List............................................................................................................. 17–1
Beep Block Diagram................................................................................................................................. 17–2
Beep Operating Modes ................................................................................................................................ 17–2
Pulse Mode............................................................................................................................................... 17–3
Sequence Mode......................................................................................................................................... 17–3
Tones........................................................................................................................................................ 17–4
Clocking and Power.................................................................................................................................. 17–4
Power-down Considerations ..................................................................................................................... 17–5
Beep Interrupts and Events .......................................................................................................................... 17–5
Beep Programming Model ........................................................................................................................... 17–5
Timing Diagram....................................................................................................................................... 17–5
Programming Guidelines.......................................................................................................................... 17–6
ADuCM302x BEEP Register Descriptions ................................................................................................. 17–7
xx
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Beeper configuration ............................................................................................................................... 17–8
Beeper status ......................................................................................................................................... 17–10
Tone A Data .......................................................................................................................................... 17–12
Tone B Data .......................................................................................................................................... 17–13
Timer (TMR)
TMR Features.............................................................................................................................................. 18–1
TMR Functional Description ...................................................................................................................... 18–2
ADuCM302x TMR Register List ............................................................................................................. 18–2
TMR Block Diagram................................................................................................................................ 18–3
TMR Operating Modes ............................................................................................................................... 18–3
Free Running Mode.................................................................................................................................. 18–3
Periodic Mode .......................................................................................................................................... 18–3
Toggle Mode............................................................................................................................................. 18–4
Match Mode............................................................................................................................................. 18–4
PWM Demodulation................................................................................................................................... 18–5
Clock Select ................................................................................................................................................. 18–5
Capture Event Function............................................................................................................................... 18–6
TMR Interrupts and Exceptions .................................................................................................................. 18–6
ADuCM302x TMR Register Descriptions .................................................................................................. 18–7
16-bit load value, asynchronous ............................................................................................................... 18–8
16-bit timer value, asynchronous ............................................................................................................. 18–9
Capture ................................................................................................................................................. 18–10
Clear Interrupt ...................................................................................................................................... 18–11
Control .................................................................................................................................................. 18–12
16-bit load value .................................................................................................................................... 18–15
PWM Control Register ......................................................................................................................... 18–16
PWM Match Value ................................................................................................................................ 18–17
Status ..................................................................................................................................................... 18–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
xxi
16-bit timer value .................................................................................................................................. 18–20
I2C Serial Interface (I2C)
I2C Features ................................................................................................................................................ 19–1
I2C Functional Description ......................................................................................................................... 19–1
ADuCM302x I2C Register List................................................................................................................ 19–2
I2C Operating Modes.................................................................................................................................. 19–2
Master Transfer Initiation......................................................................................................................... 19–3
Slave Transfer Initiation............................................................................................................................ 19–3
Rx/Tx Data FIFOs ................................................................................................................................... 19–3
Master NOACK ....................................................................................................................................... 19–5
No Acknowledge from Slave ..................................................................................................................... 19–5
General Call ............................................................................................................................................. 19–6
Generation of Repeated Starts by Master.................................................................................................. 19–6
DMA Requests ......................................................................................................................................... 19–6
I2C Reset Mode ....................................................................................................................................... 19–6
I2C Test Modes ........................................................................................................................................ 19–7
I2C Low Power Mode .............................................................................................................................. 19–7
I2C Bus Clear Operation.......................................................................................................................... 19–7
Power-down Considerations ..................................................................................................................... 19–7
I2C Data Transfer........................................................................................................................................ 19–8
I2C Interrupts and Exceptions..................................................................................................................... 19–8
ADuCM302x I2C Register Descriptions .................................................................................................... 19–8
1st master address byte .......................................................................................................................... 19–10
2nd master address byte ......................................................................................................................... 19–11
Hardware general call ID ....................................................................................................................... 19–12
Automatic stretch SCL register .............................................................................................................. 19–13
Start byte ............................................................................................................................................... 19–15
Serial clock period divisor ...................................................................................................................... 19–16
xxii
ADuCM302x Mixed-Signal Control Processor Hardware Reference
1st slave address device ID ..................................................................................................................... 19–17
2nd slave address device ID ................................................................................................................... 19–18
3rd slave address device ID .................................................................................................................... 19–19
4th slave address device ID .................................................................................................................... 19–20
Master control ....................................................................................................................................... 19–21
Master current receive data count .......................................................................................................... 19–23
Master receive data ................................................................................................................................ 19–24
Master receive data count ...................................................................................................................... 19–25
Master status ......................................................................................................................................... 19–26
Master transmit data ............................................................................................................................. 19–29
Slave control .......................................................................................................................................... 19–30
Shared control ....................................................................................................................................... 19–32
Slave receive ........................................................................................................................................... 19–33
Slave I2C Status/Error/IRQ ................................................................................................................... 19–34
Master and slave FIFO status ................................................................................................................. 19–37
Slave transmit ........................................................................................................................................ 19–39
Timing Control Register ....................................................................................................................... 19–40
Real Time Clock (RTC)
RTC Features............................................................................................................................................... 20–1
RTC Functional Description........................................................................................................................ 20–2
ADuCM302x RTC Register List.................................................................................................................. 20–2
RTC Block Diagram .................................................................................................................................... 20–3
RTC Architectural Concepts........................................................................................................................ 20–4
RTC Operating Modes ................................................................................................................................ 20–4
Initial RTC Power-Up .............................................................................................................................. 20–4
Persistent, Sticky RTC Wake-Up Events ................................................................................................... 20–4
RTC Capacity to Accommodate Posted Writes by CPU ........................................................................... 20–5
Realignment of RTC Count to Packet-Defined Time Reference............................................................... 20–5
ADuCM302x Mixed-Signal Control Processor Hardware Reference
xxiii
RTC Recommendations : Clocks and Power................................................................................................ 20–5
Stopping PCLK ........................................................................................................................................ 20–5
Ensuring No Communication across RTC Power Boundary when Powering Down ................................. 20–5
RTC Interrupts and Exceptions ................................................................................................................... 20–6
RTC Programming Model ........................................................................................................................... 20–6
Programming Guidelines.......................................................................................................................... 20–6
RTC Output Compare................................................................................................................................. 20–6
RTC Input Capture ..................................................................................................................................... 20–7
ADuCM302x RTC Register Descriptions ................................................................................................... 20–9
RTC Alarm 0 ......................................................................................................................................... 20–11
RTC Alarm 1 ......................................................................................................................................... 20–12
RTC Alarm 2 ......................................................................................................................................... 20–13
RTC Count 0 ........................................................................................................................................ 20–15
RTC Count 1 ........................................................................................................................................ 20–16
RTC Count 2 ........................................................................................................................................ 20–17
RTC Control 0 ...................................................................................................................................... 20–18
RTC Control 1 ...................................................................................................................................... 20–25
RTC Control 2 for Configuring Input Capture Channels ...................................................................... 20–28
RTC Control 3 for Configuring Output Compare Channel .................................................................. 20–33
RTC Control 4 for Configuring Output Compare Channel .................................................................. 20–34
RTC Freeze Count ................................................................................................................................. 20–36
RTC Gateway ........................................................................................................................................ 20–37
RTC Input Capture Channel 2 .............................................................................................................. 20–38
RTC Input Capture Channel 3 .............................................................................................................. 20–39
RTC Input Capture Channel 4 .............................................................................................................. 20–40
RTC Modulo ......................................................................................................................................... 20–41
RTC Output Compare Channel 1 ......................................................................................................... 20–43
RTC Auto-Reload for Output Compare Channel 1 ............................................................................... 20–45
RTC Output Compare Channel 1 Target .............................................................................................. 20–46
xxiv
ADuCM302x Mixed-Signal Control Processor Hardware Reference
RTC Masks for Output Compare Channel ............................................................................................ 20–48
RTC Snapshot 0 .................................................................................................................................... 20–49
RTC Snapshot 1 .................................................................................................................................... 20–51
RTC Snapshot 2 .................................................................................................................................... 20–53
RTC Status 0 ......................................................................................................................................... 20–55
RTC Status 1 ......................................................................................................................................... 20–65
RTC Status 2 ......................................................................................................................................... 20–69
RTC Status 3 ......................................................................................................................................... 20–75
RTC Status 4 ......................................................................................................................................... 20–78
RTC Status 5 ......................................................................................................................................... 20–83
RTC Status 6 ......................................................................................................................................... 20–88
RTC Trim .............................................................................................................................................. 20–94
Universal Asynchronous Receiver/Transmitter (UART)
UART Features ............................................................................................................................................ 21–1
UART Functional Description ..................................................................................................................... 21–2
ADuCM302x UART Register List ............................................................................................................... 21–2
UART Operations........................................................................................................................................ 21–2
Serial Communications ............................................................................................................................ 21–2
UART Operating Modes.............................................................................................................................. 21–4
IO Mode .................................................................................................................................................. 21–4
DMA Mode.............................................................................................................................................. 21–5
UART Interrupts ......................................................................................................................................... 21–5
FIFO Mode (16550) .................................................................................................................................... 21–5
Auto Baud-rate Detection ............................................................................................................................ 21–6
RS485 Half-Duplex Mode ........................................................................................................................... 21–6
Receive Line Inversion ................................................................................................................................. 21–7
Clock Gating ............................................................................................................................................... 21–7
ADuCM302x Mixed-Signal Control Processor Hardware Reference
xxv
UART and Power-Down Modes .................................................................................................................. 21–7
ADuCM302x UART Register Descriptions ................................................................................................ 21–8
Auto Baud Control .................................................................................................................................. 21–9
Auto Baud Status (High) ....................................................................................................................... 21–11
Auto Baud Status (Low) ......................................................................................................................... 21–12
UART control register ........................................................................................................................... 21–13
Baudrate divider .................................................................................................................................... 21–14
Fractional Baud Rate ............................................................................................................................. 21–15
FIFO Control ........................................................................................................................................ 21–16
Interrupt Enable .................................................................................................................................... 21–17
Interrupt ID .......................................................................................................................................... 21–18
Line Control .......................................................................................................................................... 21–19
second Line Control .............................................................................................................................. 21–21
Line Status ............................................................................................................................................. 21–22
Modem Control ..................................................................................................................................... 21–24
Modem Status ....................................................................................................................................... 21–25
RX FIFO byte count .............................................................................................................................. 21–27
RS485 half-duplex Control .................................................................................................................... 21–28
Receive Buffer Register .......................................................................................................................... 21–29
Scratch buffer ........................................................................................................................................ 21–30
TX FIFO byte count .............................................................................................................................. 21–31
Transmit Holding Register .................................................................................................................... 21–32
Watchdog Timer (WDT)
WDT Features ............................................................................................................................................. 22–1
WDT Functional Description...................................................................................................................... 22–1
ADuCM302x WDT Register List ............................................................................................................ 22–1
WDT Block Diagram ............................................................................................................................... 22–1
WDT Operating Modes .............................................................................................................................. 22–2
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
Watchdog Synchronization ....................................................................................................................... 22–3
Watchdog Power Modes behavior ............................................................................................................. 22–3
ADuCM302x WDT Register Descriptions ................................................................................................. 22–3
Current count value ................................................................................................................................. 22–4
Control .................................................................................................................................................... 22–5
Load value ............................................................................................................................................... 22–6
Clear interrupt ......................................................................................................................................... 22–7
Status ....................................................................................................................................................... 22–8
Cache
ADuCM302x FLCC_CACHE Register List ................................................................................................ 23–1
Cache Programming Model ......................................................................................................................... 23–1
Programming Guidelines.......................................................................................................................... 23–1
ADuCM302x FLCC_CACHE Register Descriptions ................................................................................. 23–1
Cache Key register ................................................................................................................................... 23–3
Cache Setup register ................................................................................................................................ 23–4
Cache Status register ................................................................................................................................ 23–5
ADuCM302x Mixed-Signal Control Processor Hardware Reference
xxvii
Preface
Thank you for purchasing and developing systems using an ADuCM302x processor from Analog Devices, Inc.
Purpose of This Manual
The ADuCM302x Mixed-Signal Control Processor with ARM® Cortex®-M3 Hardware Reference provides architectural
information about the ADuCM302x processors. This hardware reference provides the main architectural information about these processors. This includes power management, clocking, memories, peripherals, and the AFE.
For programming information, visit the ARM Information Center at: http://infocenter.arm.com/help/
The applicable documentation for programming the ARM Cortex-M3 processor include:
• ARM Cortex-M3 Devices Generic User Guide
• ARM Cortex-M3 Technical Reference Manual
For timing, electrical, and package specifications, see the ADuCM302x Processor Data Sheet.
Intended Audience
The primary audience for this manual is a programmer who is familiar with the Analog Devices processors. The
manual assumes that the audience has a working knowledge of the appropriate processor architecture and instruction set. Programmers who are unfamiliar with Analog Devices processors can use this manual, but should supplement it with other texts, such as programming reference books and data sheets, that describe their target architecture.
Whats New in This Manual?
This is the third preliminary revision (0.3) of the ADuCM302x Mixed-Signal Control Processor with ARM Cortex-M3
Hardware Reference.
This revision adds the ADC Subsystem chapter. Also, the UART and RTC chapters are updated.
Technical or Customer Support
You can reach customer and technical support for processors from Analog Devices in the following ways:
• Post your questions in the processors and DSP support community at EngineerZone:
http://ez.analog.com/community/dsp
• Submit your questions to technical support at Connect with ADI Specialists:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
xxviii
http://www.analog.com/support
• E-mail your questions about software/hardware development tools to:
[email protected]
• E-mail your questions about processors and DSPs to:
[email protected] (world wide support)
[email protected] (China support)
• Phone questions to 1-800-ANALOGD (USA only)
• Contact your Analog Devices sales office or authorized distributor. Locate one at:
http://www.analog.com/adi-sales
• Send questions by mail to:
Analog Devices, Inc.
Three Technology Way
P.O. Box 9106
Norwood, MA 02062-9106 USA
Product Information
Product information can be obtained from the Analog Devices Web site and the online help system.
Analog Devices Web Site
The Analog Devices Web site, http://www.analog.com, provides information about a broad range of products—analog integrated circuits, amplifiers, converters, and digital signal processors.
To access a complete technical library for each processor family, go to: http://www.analog.com/processors/technical_library The manuals selection opens a list of current manuals related to the product as well as a link to the previous revisions of the manuals. When locating your manual title, note a possible errata check mark next to the title
that leads to the current correction report against the manual.
Also note, MyAnalog.com is a free feature of the Analog Devices Web site that allows customization of a Web page
to display only the latest information about products you are interested in. You can choose to receive weekly e-mail
notifications containing updates to the Web pages that meet your interests, including documentation errata against
all manuals. MyAnalog.com provides access to books, application notes, data sheets, code examples, and more.
Visit MyAnalog.com to sign up. If you are a registered user, just log on. Your user name is your e-mail address.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
xxix
EngineerZone
EngineerZone is a technical support forum from Analog Devices. It allows you direct access to ADI technical support engineers. You can search FAQs and technical information to get quick answers to your embedded processing
and DSP design questions.
Use EngineerZone to connect with other DSP developers who face similar design challenges. You can also use this
open forum to share knowledge and collaborate with the ADI support team and your peers. Visit http://
ez.analog.com to sign up.
Notation Conventions
Text conventions used in this manual are identified and described as follows. Additional conventions, which apply
only to specific chapters, may appear throughout this document.
Example
Description
File > Close
Titles in reference sections indicate the location of an item within the CrossCore
Embedded Studio IDE's menu system (for example, the Close command appears
on the File menu).
{this | that}
Alternative required items in syntax descriptions appear within curly brackets and
separated by vertical bars; read the example as this or that. One or the other is
required.
[this | that]
Optional items in syntax descriptions appear within brackets and separated by
vertical bars; read the example as an optional this or that.
[this, …]
Optional item lists in syntax descriptions appear within brackets delimited by
commas and terminated with an ellipse; read the example as an optional commaseparated list of this.
.SECTION
Commands, directives, keywords, and feature names are in text with Letter
Gothic font.
filename
Non-keyword placeholders appear in text with italic style format.
NOTE:
NOTE: For correct operation, ...
A note provides supplementary information on a related topic. In the online version of this book, the word NOTE: appears instead of this symbol.
CAUTION:
CAUTION: Incorrect device operation may result if ...
CAUTION: Device damage may result if ...
A caution identifies conditions or inappropriate usage of the product that could
lead to undesirable results or product damage. In the online version of this book,
the word CAUTION: appears instead of this symbol.
ATTENTION:
ATTENTION: Injury to device users may result if ...
A warning identifies conditions or inappropriate usage of the product that could
lead to conditions that are potentially hazardous for devices users. In the online
version of this book, the word ATTENTION: appears instead of this symbol.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
xxx
Register Diagram Conventions
Register diagrams use the following conventions:
• The descriptive name of the register appears at the top, followed by the short form of the name in parentheses.
• If the register is read-only (RO), write-1-to-set (W1S), or write-1-to-clear (W1C), this information appears under the name. Read/write is the default and is not noted. Additional descriptive text may follow.
• If any bits in the register do not follow the overall read/write convention, this is noted in the bit description
after the bit name.
• If a bit has a short name, the short name appears first in the bit description, followed by the long name in
parentheses.
• The reset value appears in binary in the individual bits and in hexadecimal to the right of the register.
• Bits marked X have an unknown reset value. Consequently, the reset value of registers that contain such bits is
undefined or dependent on pin values at reset.
• Shaded bits are reserved.
Note: To ensure upward compatibility with future implementations, write back the value that is read for reserved bits
in a register, unless otherwise specified.
Register description tables use the following conventions:
• Each bit's or bit field's access type appears beneath the bit number in the table in the form (read-access/writeaccess). The access types include:
• R = read, RC = read clear, RS = read set, R0 = read zero, R1 = read one, Rx = read undefined
• W = write, NW = no write, W1C = write one to clear, W1S = write one to set, W0C = write zero to clear, W0S
= write zero to set, WS = write to set, WC = write to clear, W1A = write one action.
• Many bit and bit field descriptions include enumerations, identifying bit values and related functionality. Unless otherwise indicated (with a prefix), these enumerations are decimal values.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
xxxi
Introduction
1 Introduction
The ADuCM302x processor is an ultra-low power, integrated mixed-signal micro-controller system used for processing, control, and connectivity. The MCU subsystem is based on the ARM® Cortex®-M3 processor, a collection
of digital peripherals, cache embedded SRAM and flash memory, and an analog subsystem which provides clocking,
reset and power management capabilities along with ADC.
The ADuCM302x processor provides a collection of power modes and features such as dynamic and software controlled clock gating and power gating to support extremely low dynamic and hibernate power management.
ADuCM302x Mixed Control Processor Features
The ADuCM302x processor supports the following features:
• A 26 MHz ARM Cortex-M3 processor
• 256 KB of embedded flash memory with ECC
• 32 KB system SRAM with parity
• 32 KB user configurable instruction/data SRAM with parity
4 KB of SRAM may be used as cache memory to reduce active power consumption by reducing access to flash
memory
• A power management unit (PMU)
• A power-on reset (POR) and power supply monitor (PSM)
• A buck converter for improved efficiency during active state
• A multilayer AMBA bus matrix
• A central DMA controller
• I2C and UART peripheral interfaces
• Three SPI interfaces capable of interfacing gluelessly with a range of sensors and converters
• A serial port (SPORT) capable of interfacing with a wide range of radios and converters
Two single direction half SPORT or one bi-directional full SPORT
ADuCM302x Mixed-Signal Control Processor Hardware Reference
1–1
ADuCM302x Functional Description
• A beeper driver to produce single and multi-tone playback options
• A real-time clock (RTC) capable of maintaining accurate wall clock time
• A flexible real-time clock (FLEXI RTC) that supports a wide range of wakeup times
• Three general-purpose and one watchdog timer
• Programmable GPIOs
ADuCM302x Functional Description
This section provides information on the function of the ADuCM302x processor.
ADuCM302x Block Diagram
ARM Cortex-M3 core is a 32-bit reduced instruction set computer (RISC) offering up to 33 MIPS of peak performance at 26 MHz. A central DMA controller is used to efficiently move data between peripherals and memory.
26 MHz CORE RATE
PLL
HF XTAL
LF XTAL
SERIAL-WIRE
ARM
CORTEX-M3
HF RC OSC
LF RC OSC
NVIC
WIC
INSTRUCTION
RAM/CACHE
(32kB)
MULTILAYER
AMBA
BUS
MATRIX
FLASH
256kB
PWR MGMT.
BUCK
SRAM0
(16kB)
REF BUFFER
TEMP
SENSOR
ADC
SRAM1
(16kB)
DMA
CRYPTO
(AES 128/256,
SHA256)
SPORT
UART
TMR0
TMR1
RTC0
RTC1
TMR2
WDT
Beeper
GPIO
TRNG
AHB-APB
BRIDGE
PROGRAMMABLE
CRC POLY
SPI
SPI
SPI
I2C
Figure 1-1: ADuCM302x Block Diagram
Memory Architecture
The ADuCM302x processor incorporates up to 256 KB of embedded flash memory for program code and nonvolatile data storage, 32 KB of data SRAM, and 32 KB of SRAM (configurable between instruction and data space). For
added robustness and reliability, ECC can be enabled for the flash memory and multi-bit parity can be used to detect random soft errors in SRAM.
SRAM Region
This memory space contains the application instructions and literal (constant) data which must be executed real
time. It supports read/write access by the M3 core and read/write DMA access by system peripherals. SRAM is divided into Data SRAM of 32 KB and Instruction SRAM of 32 KB. If instruction SRAM is not enabled, then the
associated 32 KB can be mapped as data SRAM, resulting in a 64 KB Data SRAM.
1–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x Functional Description
The ARM Cortex-M3 processor accesses the SRAM region on its SYS interface. The SRAM region of the core can
otherwise act as a data region for an application.
Internal SRAM Data Region: This space can contain read/write data. Internal SRAM can be partitioned between
CODE and DATA (SRAM region in M3 space) in 32 KB blocks. Access to this region occurs at core clock speed,
with no wait states. It supports read/write access by the M3 core and read/write DMA access by system devices. It
supports exclusive memory access through the global exclusive access monitor within the Analog Devices Cortex-M3
platform.
The figure shows the address map of the SRAM for various user selectable configurations. For information about the
configuration, refer to Static Random Access Memory (SRAM).
END ADDR
MODE0
Cache OFF
32kB ISRAM
32KB DSRAM
MODE1
4kB Cache
28kB ISRAM
32kB DSRAM
MODE2
Cache OFF
0kB ISRAM
64kB DSRAM
MODE3
4kB CACHE
0kB ISRAM
60kB DSRAM
0x0000_0000
0x0003_FFFF
256kB FLASH
256kB FLASH
256kB FLASH
256kB FLASH
0x1000_0000
0x1000_0FFF
16kB ISRAM
16kB ISRAM
0x1000_1000
0x1000_1FFF
0x1000_2000
0x1000_2FFF
0x1000_3000
0x1000_3FFF
0x1000_4000
0x1000_4FFF
12kB ISRAM
12kB ISRAM
0x1000_5000
0x1000_5FFF
0x1000_6000
0x1000_6FFF
0x1000_7000
0x1000_7FFF
12kB ISRAM
0x2000_0000
0x2000_0FFF
12kB DSRAM
8kB DSRAM
8kB DSRAM
8kB DSRAM
0x2000_1000
0x2000_1FFF
0x2000_2000
0x2000_2FFF
8kB DSRAM
8kB DSRAM
8kB DSRAM
8kB DSRAM
0x2000_3000
0x2000_3FFF
0x2000_4000
0x2000_4FFF
16kB DSRAM
16kB DSRAM
0x2000_5000
0x2000_5FFF
0x2000_6000
0x2000_6FFF
0x2000_7000
0x2000_7FFF
0x2004_0000
0x2004_0FFF
0x2004_1000
0x2004_1FFF
16kB DSRAM
16kB DSRAM
0x2004_2000
0x2004_2FFF
0x2004_3000
0x2004_3FFF
0x2004_4000
0x2004_4FFF
12kB DSRAM
12kB DSRAM
0x2004_5000
0x2004_5FFF
0x2004_6000
0x2004_6FFF
0x2004_7000
0x2004_7FFF
INI ADDR
16kB DSRAM
16kB DSRAM
4kB DSRAM
Not mapped
Always retained
Not retained
Retained during Hibernate if programmed by user
Retained during Hibernate if programmed by user
Figure 1-2: Selectable Configuration
ADuCM302x Mixed-Signal Control Processor Hardware Reference
1–3
ADuCM302x Functional Description
System Region
The ARM Cortex-M3 processor accesses the system region on its SYS interface and is handled within the Analog
Devices Cortex-M3 platform.
CoreSight ROM: The ROM table entries point to the debug components of the processor.
ARM PPB Peripherals: This space is defined by ARM and occupies the bottom 256 KB of the SYS region. The
space supports read/write access by the M3 core to the ARM cores internal peripherals (SCS, NVIC, and WIC) and
the CoreSight ROM. It is not accessible by the system DMA.
Platform Control Registers: This space has registers within the Analog Devices Cortex-M3 platform component
that control the ARM core, its memory, and the code cache. It is accessible by the M3 core through its SYS port
(but is not accessible by the system DMA).
Flash Controller
The ADuCM302x includes 256 KB of embedded flash memory, accessed using the flash controller. The Flash Controller is coupled with a Cache Controller module which provides two AHB ports: one port for reading Data
(DCode), the other for reading Instructions (ICode). A pre-fetch mechanism is implemented in the Flash Controller
to optimize ICode read performance. Flash writes are supported by a keyhole mechanism from APB writes to memory mapped registers. The Flash Controller provides support for DMA-based key-hole writes.
The Controller supports:
• A fixed user key required for running protected commands including mass erase and page erase.
• An optional and user definable user failure analysis key (FAA Key); if set, this key may be required by Analog
Devices personnel when performing failure analysis.
• An optional and user definable write protection for user accessible memory.
• An optional 8-bit error correction code (ECC); this code may be enabled by user code (off by default).
Cache Controller
The ADuCM302x family has an optional 4 KB instruction cache. This is a two-way, set associative cache with line
size of 256 bits. When the cache controller is enabled, 4 KB of instruction SRAM is reserved for cache data. In
Hibernate mode, the cache memory is not retained.
ARM Cortex-M3 Memory Subsystem
The memory map of the ADuCM302x family is based on the ARM Cortex-M3 model. By retaining the standardized memory mapping, it becomes easier to port applications across M3 platforms. The ADuCM302x application
development is typically based on memory blocks across CODE/SRAM regions. Sufficient internal memory is available from internal SRAM and internal flash.
1–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x Functional Description
Booting
The processor supports the following boot modes:
• Booting from internal flash
• Upgrading software through UART download
Table 1-1:
Boot Modes
Boot Mode
Description
0
UART Download mode.
1
Flash Boot. Boot from integrated Flash memory.
Security Features
The ADuCM302x processor provides a combination of hardware and software protection mechanisms that lock out
access to the part in secure mode, but grant access in open mode. These mechanisms include password-protected
slave boot modes (UART), as well as password-protected SWD debug interfaces. During boot, the system is clocked
from an internal on-chip oscillator. Reset will compute a hardware checksum of the information area and then permit the CPU to execute the Analog Devices boot loader in the Flash information area if the checksum passes. The
Analog Devices boot loader inspects a GPIO boot pin which determines whether user code or a UART download is
executed.
There is a mechanism to protect the device contents (Flash, SRAM, CPU registers, and peripheral registers) from
being read through an external interface by an unauthorized user. This is referred to as read-protection.
It is possible to protect the device from being reprogrammed in-circuit with unauthorized code. This is referred to as
in-circuit write-protection. The device can be configured with no protection, read protection, or read and in-circuit
write protection. It is not necessary to provide in-circuit write protection without read protection.
The device can be configured with no protection, read protection, or read and in-circuit write protection. It is not
necessary to provide in-circuit write protection without read protection.
Processor Safety Features
The ADuCM302x processor provides a number of features that help achieve certain levels of system safety and reliability. While the level of safety is mainly dominated by system considerations, the following features are provided to
enhance robustness:
Multi Parity Bit Protected L1 Memories
In the processors SRAM and cache L1 memory space, each word is protected by multiple parity bits to detect the
single event upsets that occur in all RAMs.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
1–5
ADuCM302x Functional Description
Programmable GPIOs
The ADuCM302x processor has 44 GPIO pins, most of which have multiple, configurable functions defined by
user code. They can be configured as an input/output and have programmable pull-up resistors. All I/O pins are
functional over the full supply range. In power-saving mode, GPIO pins retain state; they tristate on reset to prevent
any bus irritation.
Timers
The ADuCM302x processor contains general-purpose timers and a watchdog timer.
General-Purpose Timers
The ADuCM302x has three identical general-purpose timers, each with a 16-bit count-up/count-down counter.
The count-up/count-down counter can be clocked from one of four user selectable clock sources. Any selected clock
source can be scaled down using a prescaler of 1, 16, 64, or 256.
Watchdog Timer (WDT)
The watchdog timer is a 16-bit count-down timer with a programmable prescaler. The prescaler source is selectable
and can be scaled by a factor of 1, 16, or 256. The watchdog timer is clocked by the 32 kHz on-chip oscillator
(LFOSC).The watchdog timer (WDT) is used to recover from an illegal software state. The WDT requires periodic
servicing to prevent it from forcing a reset or interrupt of the processor.
Power Management
The ADuCM302x processor includes power management and clocking features.
Power Modes
The PMU provides control of the ADuCM302x power modes, and allows the ARM Cortex-M3 to control the
clocks and power gating to reduce the dynamic power and hibernate power. The power modes are:
Active Mode
All peripherals can be enabled. Active power is managed by optimized clock management.
Flexi Mode
The core is clock gated, but the remainder of the system is active. No instructions can be executed in this mode, but
DMA transfers can continue between peripherals and memory.
Hibernate Mode
This mode provides configurable SRAM and port pin retention, a limited number of wake-up interrupts, and (optionally) an active RTC.
1–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x Functional Description
Shutdown Mode
This mode is the deepest sleep mode, in which all the digital and analog circuits are powered down with an option
to wake from four possible wake-up sources. In hibernate mode, the registers of the Cortex micro and control registers of all peripherals are retained to ensure that the user need not re-program these registers after waking up. However, any volatile registers such as status registers, internal state machines, FIFOs and so on are not retained. The
exact registers retained in hibernate mode are captured in the chapters for each peripheral.
If a peripheral is active prior to the part going into hibernate, on wakeup from hibernate, the peripheral is disabled
and will not continue from where it left off prior to going into hibernate. The user must ensure that all peripheral
and DMA activity has completed before going into hibernate.
Clocking
Two on-chip oscillators and driver circuitry for two external crystals are available on the ADuCM302x:
1. LFOSC is a 32 kHz internal oscillator
2. HFOSC is a 26 MHz internal oscillator
3. LFXTAL is a 32 kHz external crystal oscillator
4. HFXTAL is a 26 MHz external crystal oscillator
Real Time Clock
The ADuCM302x processor has two real-time blocks, RTC0 and RTC1 (also called as FLEX_RTC). The clock
blocks share a low power crystal oscillation circuit that operates in conjunction with a 32,768 Hz external crystal. It
achieves 25 ppm performance in keeping time at 25°C when used with a 10 ppm crystal class load capacitors. The
real time clock is an APB slave in the system that keeps track of wall clock time using an externally attached 32,768
Hz crystal. The RTC maintains a count of elapsed time from a point when it programmed. It is important to note
that the core still needs to interpret the count values provided by the RTC due to the fact that the units involved are
not seconds but units dependent on the pre-scaling used.
The RTC is divided into two sections which are on different power domains. One is a power gated module which
interfaces with the core and the other is an always on module which can be left on whilst the core is turned off. The
RTC also has an alarm that interrupts the core when a programmed alarm value matches the RTC count. The software enables and configures the RTC and interprets its count to the time of day.
Table 1-2:
RTC Features
Features
RTC0
RTC1 (FLEX_RTC)
Resolution of time base
RTC0 counts time at 1Hz in units of seconds
only. Operationally, when used by the customer, RTC0 will always prescale to 1 Hz (that is,
divide by 32,768) and will always count real
time in units of seconds.
RTC1 (FLEX_RTC) can prescale the clock by any power of
two from 0 to 15. It can count time in units of any of these
16 possible prescale settings. For example, the clock can be
prescaled by 1, 2, 4, 8, , 16384, or 32768.
(prescaling)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
1–7
ADuCM302x Functional Description
Table 1-2:
RTC Features (Continued)
Features
RTC0
RTC1 (FLEX_RTC)
Wake-up timer
Wake-up time is specified in units of seconds.
Wake-up time can be specified in units of any power of two
multiple of 30.7μs up to 1 second. In practice, RTC1 supports alarm times down to a resolution of 30.7μs, that is,
where the time is specified down to a specific 32 kHz clock
cycle.
Number of Alarms
One alarm only. Uses an absolute, non-repeating alarm time, specified in units of one second.
Two alarms. One absolute alarm time and one periodic
alarm, repeating every 60 prescaled time units.
System Debug
The ADuMC320x processor supports serial wire debug.
Beeper Driver
The ADuCM302x processor has an integrated audio driver for a beeper. The beeper driver module in the
ADuCM302x generates a differential square wave of programmable frequency. It drives an external piezoelectric
sound component whose two terminals connect to the differential square wave output. The beeper driver consists of
a module that can deliver frequencies from 8 kHz to ~0.25 kHz. It operates on a fixed independent 32 kHz (32,768
Hz) clock source that is unaffected by changes in system clocks.
A timer allows for programmable tone durations from 4 ms to 1.02 sec in 4 ms increments. Single-tone (pulse) and
multi-tone (sequence) modes provide versatile playback options. In sequence mode, the beeper can be programmed
to play any number of tone pairs from 1 to 254 (2 to 508 tones) or be programmed to play forever (until stopped by
the user). Interrupts are available to indicate the start or end of any beep, the end of a sequence, or that the sequence
is nearing completion.
Crypto Accelerator
Crypto is a 32-bit APB DMA-capable peripheral. There are two buffers provided for data I/O operations. These
buffers are 32- bit wide and will read in or read out 128 bits in 4 data accesses. Big Endian and Little Endian data
formats are supported. The modes supported are:
• ECB Mode - AES mode
• CTR Mode - Counter mode
• CBC Mode - Cipher Block Chaining mode
• MAC Mode - Message Authentication Code mode
• CCM/CCM* Mode -Cipher Block Chaining-Message Authentication Code Mode
• SHA-256 Mode
1–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x Functional Description
CRC Accelerator
The CRC accelerator can be used to compute the CRC for a block of memory locations. The exact memory location
can be in the SRAM, flash, or any combination of memory mapped registers. The CRC accelerator generates a
checksum that can be used to compare it with an expected signature. The main features of the CRC include:
• Generate a CRC signature for a block of data
• Supports programmable polynomial length of up to 32 bits
• Operates on 32 bit of data at a time
• Supports MSB first as well as LSB first implementations of CRC
• Various data mirroring capabilities
• Initial seed to be programmed by user
• DMA controller (memory to memory transfer) can be used for data transfer to offload the processor
Random Number Generator
The random number generator is used during operations where nondeterministic values are required. This may include generating challenges for secure communication or keys used for an encrypted communication channel. The
generator can be run multiple times to generate a sufficient number of bits for the strength of the intended operation. The true random number generator can be used to seed a deterministic random bit generator.
Serial Ports
The synchronous serial ports provide an inexpensive interface to a wide variety of digital and mixed-signal peripheral
devices such as Analog Devices audio codecs, ADCs, and DACs. The serial port consist of two half SPORTs, each
identical and made up of one bidirectional data line, a clock, frame sync and SPT_CONVT. The data line can be
programmed to either transmit or receive and each data line has a dedicated DMA channel. The serial port data can
be automatically transferred to and from on-chip memory/external memory through dedicated DMA channels. It is
possible that one half SPORT provides a transmit signal while the other half SPORT provides the receive signal.
The frame sync and clock between two half SPORTS can also be shared. Some of the ADCs/DACs require two
control signals for their conversion process. In order to interface with such devices, an extra signal called
SPT_CONVT signal is provided. The timer enable mode should be enabled in order to use this signal. The serial
ports can operate in Standard DSP serial and Timer Enable modes.
SPI Ports
SPI is an industry standard, synchronous serial interface that allows eight bits of data to be synchronously transmitted and simultaneously received, that is, full duplex. The SPI incorporates two DMA channels that interface with
the DMA controller. One DMA channel is used to transmit and the other is used to receive. The SPI on the processor eases interfacing to external serial flash devices. The SPI features available include the following:
• Serial clock phase mode and serial clock polarity mode
ADuCM302x Mixed-Signal Control Processor Hardware Reference
1–9
ADuCM302x Functional Description
• Loopback mode
• Continuous transfer mode
• Wired-OR output mode
• Read-command mode for half-duplex operation
• Flow control support
• Multiple CS line support
• CS software override support
• Support for 3-pin SPI
• Master or Slave mode
• LSB first transfer option
• Interrupt mode: interrupt after 1, 2, 3, 4, 5, 6, 7, or 8 bytes
UART Ports
The ADuCM302x processor provides full-duplex universal asynchronous receiver/transmitter (UART) ports, which
are fully compatible with PC-standard UARTs. Each UART port provides a simplified UART interface to other peripherals or hosts, supporting full-duplex, DMA-supported, asynchronous transfers of serial data. A UART port includes support for five to eight data bits, and none, even, or odd parity. A frame is terminated by one, one and a
half, or two stop bits.
Signal Chains
A signal chain is a series of signal-conditioning electronic components that receive input (data acquired from sampling either real-time phenomena or from stored data) in tandem, with the output of one portion of the chain supplying input to the next. Signal chains are often used in signal processing applications to gather and process data or
to apply system controls based on analysis of real-time phenomena. Analog Devices eases signal processing system
development by providing signal processing components that are designed to work together well. Refer to the Application Signal Chains page on http:\\www.analog.com\circuits that provides information on:
• Graphical circuit block diagram presentation of signal chains for a variety of circuit types and applications.
• Drill down links for components in each chain to selection guides and application information.
• Reference designs applying best practice design techniques.
Development Tools
In addition to this Hardware Reference document, the development support for the ADuCM302x processor includes evaluation hardware and development software tools.
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x Registers List
Hardware
The ADZS-ADUCM3025EZLITE evaluation kit is available to prototype a user's sensor configuration with theADuCM302x. A selection of daughter cards are available to interrogate peripheral performance.
Software
The EVAL-ADuCM302xEBZ includes a complete development and debug environment for the ADuCM302x. The
software development kit (SDK) for the ADuCM302x uses the IAR Embedded Workbench for ARM as its development environment. The SDK also includes operating system (OS) aware drivers and example code for all the peripherals on the device, including SPI and I2C.
ADuCM302x Registers List
Table 1-3:
Instance Summary
Name
Module
Address
TMR0
General-Purpose Timer
0x40000000
TMR1
General-Purpose Timer
0x40000400
TMR2
General-Purpose Timer
0x40000800
RTC0
Real-Time Clock
0x40001000
RTC1
Real-Time Clock
0x40001400
SYS
System
0x40002000
WDT0
Watchdog Timer
0x40002C00
I2C0
I2C Interface
0x40003000
SPI0
SPI
0x40004000
SPI1
SPI
0x40004400
UART0
UART
0x40005000
BEEP0
BEEPER
0x40005C00
DMA0
DMA
0x40010000
FLCC0
Flash/Cache Controller
0x40018000
GPIO0
GPIO
0x40020000
GPIO1
GPIO
0x40020040
GPIO2
GPIO
0x40020080
SPI2
SPI
0x40024000
SPORT0
SPORT
0x40038000
CRC0
CRC Accelerator
0x40040000
RNG0
Random Number Generator
0x40040400
ADuCM302x Mixed-Signal Control Processor Hardware Reference
1–11
ADuCM302x Registers List
Table 1-3:
Instance Summary (Continued)
Name
Module
Address
CRYPT0
Cryptographic Module
0x40044000
PMG0
PMG
0x4004C000
XINT0
External Interrupt Module
0x4004C080
CLKG0
Clocking Subsystem
0x4004C100
1–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
General-Purpose I/O (GPIO)
2 General-Purpose I/O (GPIO)
This section describes the general-purpose input/output (GPIO) functionality.
GPIO Features
The GPIO ports include the following features:
• Input and output modes of GPIO operation.
• Port multiplexing controlled by individual pin-per-pin base.
• All port pins provide interrupt functionality.
GPIO Functional Description
The ADuCM302x processor controls the GPIO pins through a set of MMR registers. These MMRs are implemented as part of an APB32 peripheral. Multiple functions are mapped on most of the GPIO pins. These functions can
be selected by appropriately configuring the corresponding ports of the GPIO_CFG control registers.
ADuCM302x GPIO Register List
Table 2-1:
ADuCM302x GPIO Register List
Name
Description
GPIO_CFG
Port Configuration
GPIO_CLR
Port data out clear
GPIO_DS
Port drive strength select
GPIO_IEN
Port Input Path Enable
GPIO_IENA
Port interrupt A enable
GPIO_IENB
Port interrupt B enable
GPIO_IN
Port registered data input
GPIO_INT
Port interrupt Status
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–1
GPIO Functional Description
Table 2-1:
ADuCM302x GPIO Register List (Continued)
Name
Description
GPIO_OEN
Port output enable
GPIO_OUT
Port data output
GPIO_PE
Port output pullup/pulldown enable
GPIO_POL
Port interrupt polarity
GPIO_SET
Port data out set
GPIO_TGL
Port pin toggle
ADuCM302x GP I/O Multiplexing
The table identifies the pin functions that are multiplexed on the general-purpose I/O pins of the package
Table 2-2:
Signal Muxing Table Port 0
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
P0_00
P0_00
SPI0_CLK
SPT0_BCLK
P0_01
P0_01
SPI0_MOSI
SPT0_BFS
P0_02
P0_02
SPI0_MISO
SPT0_BD0
P0_03
P0_03
SPI0_CS0
SPT0_BCNV
P0_04
P0_04
I2C0_SCL
P0_05
P0_05
I2C0_SDA
P0_06
SWD0_CLK
P0_06
P0_07
SWD0_DATA
P0_07
P0_08
P0_08
BEEP0_TONE
P0_09
P0_09
BEEP0_TONE
P0_10
P0_10
UART0_TX
P0_11
P0_11
UART0_RX
P0_12
P0_12
SPT0_AD0
P0_13
P0_13
P0_14
P0_14
P0_15
P0_15
2–2
TMR0_OUT
Multiplexed
Function 3
SPI2_RDY
SPI2_CSn
SPI1_RDY
ADuCM302x Mixed-Signal Control Processor Hardware Reference
GPIO Functional Description
Table 2-3:
Signal Muxing Table Port 1
Signal Name
Multiplexed
Function 0
P1_00
P1_00
P1_01
SYS_BMODE0 P1_01
P1_02
P1_02
SPI2_CLK
P1_03
P1_03
SPI2_MOSI
P1_04
P1_04
SPI2_MISO
P1_05
P1_05
SPI2_CSn
P1_06
P1_06
SPI1_CLK
P1_07
P1_07
SPI1_MOSI
P1_08
P1_08
SPI1_MISO
P1_09
P1_09
SPI1_CS0
P1_10
P1_10
SPI0_CS1
P1_11
P1_11
P1_12
P1_12
P1_13
P1_13
P1_14
P1_14
P1_15
P1_15
Table 2-4:
Multiplexed
Function 1
Multiplexed
Function 2
Multiplexed
Function 3
SPI1_CS3
TMR1_OUT
SPI0_RDY
SPT0_ACLK
Signal Muxing Table Port 2
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
Multiplexed
Function 2
P2_00
P2_00
SPT0_AFS
P2_01
P2_01
P2_02
P2_02
P2_03
P2_03
P2_04
P2_04
P2_05
P2_05
P2_06
P2_06
P2_07
P2_07
SPI2_CSn
P2_08
P2_08
SPI0_CS2
P2_09
P2_09
SPI0_CS3
P2_10
P2_10
SPI2_CSn
Multiplexed
Function 3
TMR2_OUT
SPT0_ACNV
SPI1_CS2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–3
GPIO Functional Description
Table 2-4:
Signal Muxing Table Port 2 (Continued)
Signal Name
Multiplexed
Function 0
Multiplexed
Function 1
P2_11
P2_11
SPI1_CS1
Multiplexed
Function 2
Multiplexed
Function 3
GPIO Block Diagram
The figures show the block diagrams of the GPIO Pins with Pull-up and Pull-down resistors.
Output Enable
IOVDO
Pull-up Enable
GPxPE
GPxOEN
Output Data
GPxOUT, GPxSET,
GPxCLR, GPxTGL
GPIO
Input Data
GPxIEN
Input Data
GPxIN
Figure 2-1: GPIO Pins with Pull-up Resistor
Output Enable
GPxOEN
Output Data
GPIO
GPxOUT, GPxSET,
GPxCLR, GPxTGL
Pull-down Enable
GPxPE
Input Data
GPxIEN
Input Data
IDGND
GPxIN
Figure 2-2: GPIO Pins with Pull-down Resistor
2–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
GPIO Operating Modes
GPIO Operating Modes
IO Pull-Up or Pull-Down Enable
All GPIO pins can be grouped into two categories: GPIO pins with a pull-up resistor and GPIO pins with a pulldown resistor. Each GPIO port has a corresponding GPIO_PE register. Using the GPIO_PE registers, it is possible to
enable/disable pull-up/pull-down registers on the pins when they are configured as inputs.
IO Data In
When configured as an input using the GPIO_IEN register, the GPIO input levels are available in the GPIO_IN
register.
IO Data Out
When the GPIOs are configured as outputs using the GPIO_OEN register, the values in the GPIO_OUT register are
reflected on the GPIOs.
Bit Set
Each GPIO port has a corresponding bit set register, GPIO_SET. Use the bit set register to set one or more GPIO
data outs without affecting others within the port. Only the GPIO corresponding with the write data bit equal to
one is set, the remaining GPIOs are unaffected.
Bit Clear
Each GPIO port has a corresponding bit clear register, GPIO_CLR. Use the bit clear register to clear one or more
GPIO data outs without affecting others within the port. Only the GPIO corresponding with the write data bit
equal to one is cleared, the remaining GPIOs are unaffected.
Bit Toggle
Each GPIO port has a corresponding bit toggle register, GPIO_TGL. Using the bit toggle register, it is possible to
invert one or more GPIO data outs without affecting others within the port. Only the GPIO corresponding with
the write data bit equal to one is toggled, the remaining GPIOs are unaffected.
IO Data Output Enable
Each GPIO port has a data output enable (GPIO_IEN) register, by which the data output path is enabled. When the
data output enable register bits are set, the values in GPIO_OUT are reflected on the corresponding GPIO pins.
Interrupts
Each GPIO pin can be associated with an interrupt. Interrupts can be independently enabled for each GPIO pin
and are always edge detect; only one interrupt will be generated with each GPIO pin transition. The polarity of the
detected edge can be positive (low-to-high) or negative (high-to-low). Each GPIO interrupt event can be mapped to
one of two interrupts (INTA or INTB). This allows the system more flexibility in terms of how GPIO interrupts are
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–5
GPIO Operating Modes
grouped for servicing, and how interrupt priorities are set. The interrupt status of each GPIO pin can be determined
and cleared by accessing the associated status registers.
Interrupt Polarity
The polarity of the interrupt determines if the interrupt is accepted on the rising or the falling edge. Each GPIO
port has a corresponding interrupt register (GPIO_POL) by which the interrupt polarity of each pin is configured.
When set to 0, an interrupt event will be latched on a high-to-low transition on the corresponding pin. When set to
1, an interrupt event will be latched on a low-to-high transition on the corresponding pin.
Interrupt A Enable
Each GPIO port has an Interrupt Enable A register (GPIO_IENA) that is enabled or masked for each pin in the
port. These register bits determine if a latched edge event should be allowed to interrupt the core (Interrupt A) or be
masked. In either case, the occurrence of the event will be captured in the corresponding bit of the GPIO_INT status
register. When set to 0, Interrupt A is not enabled (masked). No interrupts to the core will be generated by this
GPIO pin. When set to 1, Interrupt A is enabled. On a valid detected edge, an interrupt source to the core will be
generated.
Interrupt B Enable
Each GPIO port has a corresponding Interrupt Enable B (GPIO_IENB) register that is enabled or masked for each
pin in the port. These register bits determine if a latched edge event should be allowed to interrupt the core (Interrupt B) or be masked. In either case, the occurrence of the event will be captured in the corresponding bit of the
GPIO_INT status register. When set to 0, Interrupt B is not enabled (masked). No interrupts to the core will be
generated by this GPIO pin. When set to 1, Interrupt B is enabled. On a valid detected edge, an interrupt source to
the core will be generated.
Interrupt Status
Each GPIO port has an interrupt status register (GPIO_INT) that captures the interrupts occurring on its pins.
These register bits indicate that the appropriately configured rising or falling edge has been detected on the corresponding GPIO pin.
Once an event is detected, GPIO_INT will remain set until cleared; this is true even if the GPIO pin transitions back
to a nonactive state. Out of reset, pull ups combined with falling edge detect can result in the GPIO_INT status
being cleared; however, this may not be the case based on pin activity. It is therefore recommended that the status of
GPIO_INT be checked before enabling interrupts (GPIO_IENA and GPIO_IENB) initially as well as anytime GPIO
pins are configured.
Interrupt bits are cleared by writing a 1 to the appropriate bit location. Writing a 0 has no effect. If interrupts are
enabled to the core (GPIO_IENA, GPIO_IENB), an interrupt (GPIO_INT) value of 1 will result in an interrupt to
the core. This bit should be cleared during servicing of the interrupt. When read as 0, a rising or falling edge was not
detected on the corresponding GPIO pin because this bit was last cleared. When read as 1, a rising or falling edge
(GPIO_POL selectable) was detected on the corresponding GPIO pin. This bit can be software cleared by writing a 1
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
GPIO Programming Model
to this bit location. This bit can only be subsequently set again after the pin returns to its nonasserted state and then
returns to an asserted state.
GPIO Programming Model
Programming Sequence for output functionality:
1. Program the GPIO_OEN register for the appropriate GPIO pins.
2. The data on the selected pin is driven high or low by writing to the GPIO_SET/GPIO_CLR/GPIO_TGL registers.
Programming Sequence for input functionality:
1. Program the GPIO_IEN register for the appropriate port pins.
2. The data latched by the input port pin is registered in the GPIO_IN register.
ADuCM302x GPIO Register Descriptions
(GPIO) contains the following registers.
Table 2-5:
ADuCM302x GPIO Register List
Name
Description
GPIO_CFG
Port Configuration
GPIO_CLR
Port data out clear
GPIO_DS
Port drive strength select
GPIO_IEN
Port Input Path Enable
GPIO_IENA
Port interrupt A enable
GPIO_IENB
Port interrupt B enable
GPIO_IN
Port registered data input
GPIO_INT
Port interrupt Status
GPIO_OEN
Port output enable
GPIO_OUT
Port data output
GPIO_PE
Port output pullup/pulldown enable
GPIO_POL
Port interrupt polarity
GPIO_SET
Port data out set
GPIO_TGL
Port pin toggle
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–7
ADuCM302x GPIO Register Descriptions
Port Configuration
The GPIO_CFG register is reserved for top-level pin muxing for the GPIO block.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PIN07 (R/W)
Pin 7 configuration bits
PIN00 (R/W)
Pin 0 configuration bits
PIN06 (R/W)
Pin 6 configuration bits
PIN01 (R/W)
Pin 1 configuration bits
PIN05 (R/W)
Pin 5 configuration bits
PIN02 (R/W)
Pin 2 configuration bits
PIN04 (R/W)
Pin 4 configuration bits
PIN03 (R/W)
Pin 3 configuration bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PIN15 (R/W)
Pin 15 configuration bits
PIN08 (R/W)
Pin 8 configuration bits
PIN14 (R/W)
Pin 14 configuration bits
PIN09 (R/W)
Pin 9 configuration bits
PIN13 (R/W)
Pin 13 configuration bits
PIN10 (R/W)
Pin 10 configuration bits
PIN12 (R/W)
Pin 12 configuration bits
PIN11 (R/W)
Pin 11 configuration bits
Figure 2-3: GPIO_CFG Register Diagram
Table 2-6:
GPIO_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:30 PIN15
Pin 15 configuration bits.
(R/W)
29:28 PIN14
Pin 14 configuration bits.
(R/W)
27:26 PIN13
Pin 13 configuration bits.
(R/W)
25:24 PIN12
Pin 12 configuration bits.
(R/W)
23:22 PIN11
Pin 11 configuration bits.
(R/W)
21:20 PIN10
2–8
Pin 10 configuration bits.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x GPIO Register Descriptions
Table 2-6:
GPIO_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
(R/W)
19:18 PIN09
Pin 9 configuration bits.
(R/W)
17:16 PIN08
Pin 8 configuration bits.
(R/W)
15:14 PIN07
Pin 7 configuration bits.
(R/W)
13:12 PIN06
Pin 6 configuration bits.
(R/W)
11:10 PIN05
Pin 5 configuration bits.
(R/W)
9:8 PIN04
Pin 4 configuration bits.
(R/W)
7:6 PIN03
Pin 3 configuration bits.
(R/W)
5:4 PIN02
Pin 2 configuration bits.
(R/W)
3:2 PIN01
Pin 1 configuration bits.
(R/W)
1:0 PIN00
Pin 0 configuration bits.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–9
ADuCM302x GPIO Register Descriptions
Port data out clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Set the output low for the port pin
Figure 2-4: GPIO_CLR Register Diagram
Table 2-7:
GPIO_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
2–10
Set the output low for the port pin.
Each bit is set to drive the corresponding GPIO pin low. Clearing this bit has no effect.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x GPIO Register Descriptions
Port drive strength select
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Drive strength select
Figure 2-5: GPIO_DS Register Diagram
Table 2-8:
GPIO_DS Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Drive strength select.
Each bit is configured to set the Drive strength of the corresponding GPIO Pin.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–11
ADuCM302x GPIO Register Descriptions
Port Input Path Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Input path enable
Figure 2-6: GPIO_IEN Register Diagram
Table 2-9:
GPIO_IEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
2–12
Input path enable.
Each bit is set to enable the input path and cleared to disable the input path for the
GPIO pin.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x GPIO Register Descriptions
Port interrupt A enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Interrupt A enable.
Figure 2-7: GPIO_IENA Register Diagram
Table 2-10:
GPIO_IENA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Interrupt A enable..
Determines if a latched edge event should be allowed to interrupt the core (INTERRUPT A) or be masked. In either case the occurrence of the event will be captured in
the GPIO_INT status register. when cleared Interrupt A is not enabled (masked).
When set Interrupt A is enabled.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–13
ADuCM302x GPIO Register Descriptions
Port interrupt B enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Interrupt B enable.
Figure 2-8: GPIO_IENB Register Diagram
Table 2-11:
GPIO_IENB Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
2–14
Interrupt B enable..
Determines if a latched edge event should be allowed to interrupt the core (INTERRUPT B) or be masked. In either case the occurrence of the event will be captured in
the GPIO_INT status register. when set to 0 Interrupt B is not enabled (masked).
When set 1 Interrupt A is enabled.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x GPIO Register Descriptions
Port registered data input
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
X X X X X X X X X X X X X X X X
VALUE (R)
Registered data input
Figure 2-9: GPIO_IN Register Diagram
Table 2-12:
GPIO_IN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/NW)
Registered data input.
Each bit reflects the state of the GPIO pin if the corresponding input buffer is enabled.
If the pin input buffer is disabled the value seen is zero.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–15
ADuCM302x GPIO Register Descriptions
Port interrupt Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W1C)
Interrupt Status
Figure 2-10: GPIO_INT Register Diagram
Table 2-13:
GPIO_INT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W1C)
2–16
Interrupt Status.
Indicates that the appropriately configured rising or falling edge has been detected on
the corresponding GPIO pin. Once an event is detected GPIO_INT.VALUE bit will
remain set until cleared, this is true even if the GPIO pin transitions back to a non
active state. GPIO_INT.VALUE bits are cleared by writing 1 to the appropriate bit location. Writing 0 has no effect
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x GPIO Register Descriptions
Port output enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Pin Output Drive enable
Figure 2-11: GPIO_OEN Register Diagram
Table 2-14:
GPIO_OEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Pin Output Drive enable.
Each bit is set to enable the output for that particular pin. It is cleared to disable the
output for each pin.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–17
ADuCM302x GPIO Register Descriptions
Port data output
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Data out
Figure 2-12: GPIO_OUT Register Diagram
Table 2-15:
GPIO_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
2–18
Data out.
Set by user code to drive the corresponding GPIO high. Cleared by user to drive the
corresponding GPIO low.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x GPIO Register Descriptions
Port output pullup/pulldown enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
1
1
0
0
0
0
0
0
VALUE (R/W)
Pin Pull enable
Figure 2-13: GPIO_PE Register Diagram
Table 2-16:
GPIO_PE Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Pin Pull enable.
Each bit is set to enable the pullup/pulldown for that particular pin. It is cleared to
disable the pullup/pulldown for each pin.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–19
ADuCM302x GPIO Register Descriptions
Port interrupt polarity
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Interrupt polarity.
Figure 2-14: GPIO_POL Register Diagram
Table 2-17:
GPIO_POL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
2–20
Interrupt polarity..
Determines whether interrupts are generated on the rising or falling edge of the corresponding GPIO pin. When cleared , an interrupt event will be latched on a high-tolow transition. When set an interrupt event will be latched on a low-to-high transition.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x GPIO Register Descriptions
Port data out set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Set the output HIGH for the pin
Figure 2-15: GPIO_SET Register Diagram
Table 2-18:
GPIO_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
Set the output HIGH for the pin.
Set by user code to drive the corresponding GPIO high. Clearing this bit has no effect.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
2–21
ADuCM302x GPIO Register Descriptions
Port pin toggle
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Toggle the output of the port pin
Figure 2-16: GPIO_TGL Register Diagram
Table 2-19:
GPIO_TGL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
2–22
Toggle the output of the port pin.
Each bit is set to invert the corresponding GPIO pin. Clearing this bit has not effect.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Events (Interrupts and Exceptions)
3 Events (Interrupts and Exceptions)
The ADuCM302x processor supports a number of system exceptions and peripheral interrupts.
Events Features
The ADuCM302x Events have the following features:
• 16 system exceptions with highest priority.
• 79 system interrupts with programmable priority.
• Four external interrupts which can be configured separately to wake up the core from low power modes.
ADuCM302x XINT Register List
Table 3-1:
ADuCM302x XINT Register List
Name
Description
XINT_CFG0
External Interrupt configuration
XINT_CLR
External Interrupt clear
XINT_EXT_STAT
External Wakeup Interrupt Status register
XINT_NMICLR
Non-maskable interrupt clear
Events Interrupts and Exceptions
Cortex Exceptions
Exceptions 1 to 15 are system exceptions and are described in the table below:
Table 3-2:
List of System Exceptions
Exception
Number
IRQ
Number
Exception Type
Priority
Description
1
-
Reset
−3 (highest)
Any reset
ADuCM302x Mixed-Signal Control Processor Hardware Reference
3–1
Events Interrupts and Exceptions
Table 3-2:
List of System Exceptions (Continued)
Exception
Number
IRQ
Number
Exception Type
Priority
Description
2
-14
NMI
−2
Nonmaskable interrupt connected to a combination of (logical OR) of VREG under or VBAT (under 1.8 V)
3
-13
Hard fault
−1
All fault conditions, if the corresponding fault handler is not
enabled
4
-12
MemManagement fault
Programmable
Memory management fault; access to illegal locations
5
-11
Bus fault
Programmable
Pre-fetch fault, memory access fault, and other address/
memory related faults
6
-10
Usage fault
Programmable
Exceptions such as undefined instruction executed or illegal
state transition attempt
7 to 10
-
Reserved
Not applicable
11
-5
SVCALL
Programmable
System service call with SVC instruction
12
-4
Debug monitor
Programmable
Debug monitor (breakpoint, watchpoint, or external debug
requests)
13
-
Reserved
Not applicable
14
-2
PENDSV
Programmable
Pendable request for system service
15
-1
SYSTICK
Programmable
System tick timer
Nested Vectored Interrupt Controller
Interrupts are controlled by the Nested Vectored Interrupt Controller (NVIC), and eight levels of priority are available. Only a limited number of interrupts can wake up the device from the Hibernate mode. When the device is
woken up from the Flexi, Hibernate, or Shutdown modes, it always returns to the Active mode.
Table 3-3:
Interrupt Sources
Exception
Number
IRQ
Number
Vector
16
0
17
Wake-up From
HIBERNATE
SHUTDOWN
Real Time Clock 1/Wakeup Timer/Hibernate RTC Yes
Yes
No
1
External Interrupt 0
Yes
Yes
Yes
18
2
External Interrupt 1
Yes
Yes
Yes
19
3
External Interrupt 2
Yes
Yes
Yes
20
4
External Interrupt 3
Yes
Yes
No
21
5
Watchdog Timer
Yes
No
No
22
6
VREG Over
Yes
No
No
23
7
Battery Voltage Range
Yes
Yes
No
3–2
FLEXI
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Events Interrupts and Exceptions
Table 3-3:
Interrupt Sources (Continued)
Exception
Number
IRQ
Number
Vector
24
8
Real Time Clock 0/
Wake-up From
FLEXI
HIBERNATE
SHUTDOWN
Yes
Yes
Yes
Shutdown RTC
25
9
GPIO IntA
Yes
No
No
26
10
GPIO IntB
Yes
No
No
27
11
GP Timer 0
Yes
No
No
28
12
GP Timer 1
Yes
No
No
29
13
Flash Controller
Yes
No
No
30
14
UART0
Yes
No
No
31
15
SPI0
Yes*
No
No
32
16
SPI-H
Yes*
No
No
33
17
I2C0 Slave
Yes*
No
No
34
18
I2C0 Master
Yes*
No
No
35
19
DMA Error
Yes
No
No
36
20
DMA Channel 0 Done
Yes
No
No
37
21
DMA Channel 1 Done
Yes
No
No
38
22
DMA Channel 2 Done
Yes
No
No
39
23
DMA Channel 3 Done
Yes
No
No
40
24
DMA Channel 4 Done
Yes
No
No
41
25
DMA Channel 5 Done
Yes
No
No
42
26
DMA Channel 6 Done
Yes
No
No
43
27
DMA Channel 7 Done
Yes
No
No
44
28
DMA Channel 8 Done
Yes
No
No
45
29
DMA Channel 9 Done
Yes
No
No
46
30
DMA Channel 10 Done
Yes
No
No
47
31
DMA Channel 11 Done
Yes
No
No
48
32
DMA Channel 12 Done
Yes
No
No
49
33
DMA Channel 13 Done
Yes
No
No
50
34
DMA Channel 14 Done
Yes
No
No
51
35
DMA Channel 15 Done
Yes
No
No
52
36
SPORT0A
Yes
No
No
ADuCM302x Mixed-Signal Control Processor Hardware Reference
3–3
Events Interrupts and Exceptions
Table 3-3:
Interrupt Sources (Continued)
Exception
Number
IRQ
Number
Vector
53
37
54
Wake-up From
FLEXI
HIBERNATE
SHUTDOWN
SPORT0B
Yes
No
No
38
Crypto
Yes
No
No
55
39
Reserved
-
-
-
56
40
GP Timer 2
Yes
No
No
57
41
Crystal Oscillator
Yes
No
No
58
42
SPI1
Yes
No
No
59
43
PLL
Yes
No
No
60
44
Random Number Generator
Yes
No
No
61
45
Beeper
Yes
No
No
62
46-55
Reserved
-
-
-
72
56
DMA Channel 16 Done
Yes
No
No
73
57
DMA Channel 17 Done
Yes
No
No
74
58
DMA Channel 18 Done
Yes
No
No
75
59
DMA Channel 19 Done
Yes
No
No
76
60
DMA Channel 20 Done
Yes
No
No
77
61
DMA Channel 21 Done
Yes
No
No
78
62
DMA Channel 22 Done
Yes
No
No
79
63
DMA Channel 23 Done
Yes
No
No
* Corresponding PCLK is required to generate the interrupt.
Internally, the highest user-programmable priority (0) is treated as the fourth priority, after a reset, NMI, and a hard
fault. Note that 0 is the default priority for all programmable priorities.
If the same priority level is assigned to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. For example, if both SPI0 and SPI1 are Priority
Level 1, SPI0 has higher priority.
For more information on the exceptions and interrupts, refer to Chapter 5 (Exceptions) and Chapter 8 (Nested Vectored Interrupt Controller) in the ARM Cortex-M3 Technical Reference Manual.
Handling Interrupt Registers
In the Interrupt Service Routine (ISR) for any interrupt source, the first action usually taken is clearing of the interrupt source. In case of write-1-to-clear interrupts, the interrupt status register should be written to clear the interrupt
source. Due to internal delays in the bus-matrix, this write may be delayed before it reaches the destination. Meanwhile, the ISR execution might have been completed and there is a possibility of mistaking the previous interrupt for
3–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Events Interrupts and Exceptions
a second one. Therefore, it is always recommended to ensure that the interrupt source has been cleared before exiting the ISR. This can be done by reading the interrupt status again at the end of the ISR.
External Interrupt Configuration
Four external interrupts are implemented. These external interrupts can be separately configured to detect any combination of the following types of events:
• Rising edge: The logic detects a transition from low to high and generates a pulse. Only one pulse is sent to the
Cortex-M3 per rising edge.
• Falling edge: The logic detects a transition from high to low and generates a pulse. Only one pulse is sent to the
Cortex-M3 per falling edge.
• Rising or falling edge: The logic detects a transition from low to high or high to low and generates a pulse.
Only one pulse is sent to the Cortex-M3 per edge.
• High level: The logic detects a high level. The appropriate interrupt is asserted and sent to the Cortex-M3. The
interrupt line is held asserted until the external source deasserts. The high level needs to be maintained for one
core clock cycle minimum to be detected.
• Low level: The logic detects a low level. The appropriate interrupt is asserted and sent to the Cortex-M3. The
interrupt line is held asserted until the external source deasserts. The low level needs to be maintained a minimum of one core clock cycle to be detected.
The external interrupt detection unit block is always on and allows external interrupt to wake up the device when in
hibernate mode.
NOTE: For the use of the external interrupt on the corresponding pads, the pads must be configured as GPIOs and
the corresponding GPIO input enable should be set high. For example, when using the pad p0_15 as external interrupt, set the GP0CON [31:30] as 2'b00 and the GP0IE [15] as 1'b1.
ADuCM302x XINT Register Descriptions
External interrupt configuration (XINT) contains the following registers.
Table 3-4:
ADuCM302x XINT Register List
Name
Description
XINT_CFG0
External Interrupt configuration
XINT_CLR
External Interrupt clear
XINT_EXT_STAT
External Wakeup Interrupt Status register
XINT_NMICLR
Non-maskable interrupt clear
ADuCM302x Mixed-Signal Control Processor Hardware Reference
3–5
ADuCM302x XINT Register Descriptions
External Interrupt configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
IRQ3EN (R/W)
External Interrupt 3 enable bit
IRQ0MDE (R/W)
External Interrupt 0 Mode registers
IRQ3MDE (R/W)
External Interrupt 3 Mode registers
IRQ0EN (R/W)
External Interrupt 0 Enable bit
IRQ2EN (R/W)
External Interrupt 2 Enable bit
IRQ1MDE (R/W)
External Interrupt 1 Mode registers
IRQ2MDE (R/W)
External Interrupt 2 Mode registers
IRQ1EN (R/W)
External Interrupt 1 Enable bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
UART_RX_MDE (R/W)
External Interrupt using UART_RX wakeup
Mode registers
UART_RX_EN (R/W)
External Interrupt enable bit
Figure 3-1: XINT_CFG0 Register Diagram
Table 3-5:
XINT_CFG0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:21 UART_RX_MDE
(R/W)
External Interrupt using UART_RX wakeup Mode registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
20 UART_RX_EN
(R/W)
External Interrupt enable bit.
This bit enables 'UART_RX' pin to generate interrupt on Interrupt no. 4 (refer to the
table SYSTEM Interrupt and Exceptions chapter).
0 UART_RX wakeup interrupt is disabled
1 UART_RX wakeup interrupt is enabled
3–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x XINT Register Descriptions
Table 3-5:
XINT_CFG0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
15 IRQ3EN
External Interrupt 3 enable bit.
(R/W)
0 External Interrupt 3 disabled
1 External Interrupt 3 enabled
14:12 IRQ3MDE
External Interrupt 3 Mode registers.
(R/W)
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
11 IRQ2EN
External Interrupt 2 Enable bit.
(R/W)
0 External Interrupt 2 disabled
1 External Interrupt 2 enabled
10:8 IRQ2MDE
External Interrupt 2 Mode registers.
(R/W)
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
7 IRQ1EN
External Interrupt 1 Enable bit.
(R/W)
0 External Interrupt 0 disabled
1 External Interrupt 0 enabled
6:4 IRQ1MDE
External Interrupt 1 Mode registers.
(R/W)
0 Rising edge
1 Falling edge
ADuCM302x Mixed-Signal Control Processor Hardware Reference
3–7
ADuCM302x XINT Register Descriptions
Table 3-5:
XINT_CFG0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
3 IRQ0EN
(R/W)
External Interrupt 0 Enable bit.
0 External Interrupt 0 disabled
1 External Interrupt 0 enabled
2:0 IRQ0MDE
(R/W)
External Interrupt 0 Mode registers.
0 Rising edge
1 Falling edge
2 Rising or falling edge
3 High level
4 Low level
5 Falling edge (same as 001)
6 Rising or falling edge (same as 010)
7 High level (same as 011)
3–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x XINT Register Descriptions
External Interrupt clear
This register has W1C bits that are used to clear the corresponding EXT_STAT bits
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
UART_RX_CLR (R/W)
External interrupt Clear for UART_RX
WAKEUP interrupt
IRQ0 (R/W)
External interrupt 0
IRQ1 (R/W)
External interrupt 1
IRQ3 (R/W)
External interrupt 3
IRQ2 (R/W)
External interrupt 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-2: XINT_CLR Register Diagram
Table 3-6:
XINT_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5 UART_RX_CLR
(R/W)
3 IRQ3
(R/W)
2 IRQ2
(R/W)
1 IRQ1
(R/W)
0 IRQ0
(R/W)
External interrupt Clear for UART_RX WAKEUP interrupt.
Set to 1 to clear an interrupt STATUS flag. Cleared automatically by hardware.
External interrupt 3.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
External interrupt 2.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
External interrupt 1.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
External interrupt 0.
Set to 1 to clear interrupt status flag. Cleared automatically by hardware.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
3–9
ADuCM302x XINT Register Descriptions
External Wakeup Interrupt Status register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
STAT_UART_RXWKUP (R)
Interrupt status bit for UART RX WAKEUP
interrupt
STAT_EXTINT0 (R)
Interrupt status bit for External Interrupt 0
STAT_EXTINT1 (R)
Interrupt status bit for External Interrupt 1
STAT_EXTINT3 (R)
Interrupt status bit for External Interrupt 3
STAT_EXTINT2 (R)
Interrupt status bit for External Interrupt 2
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-3: XINT_EXT_STAT Register Diagram
Table 3-7:
XINT_EXT_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5 STAT_UART_RXWKUP
(R/NW)
3 STAT_EXTINT3
(R/NW)
2 STAT_EXTINT2
(R/NW)
1 STAT_EXTINT1
(R/NW)
0 STAT_EXTINT0
Interrupt status bit for UART RX WAKEUP interrupt.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 4 as mentioned
in System Interrupts and exceptions chapter 0 - UART_RX Wakeup did not generate
the interrupt 1 - UART_RX Wakeup generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.UART_RX_CLR bit Note : Interrupt No. 4 is shared with External Interrupt 3, UART RX Wakeup.
Interrupt status bit for External Interrupt 3.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 4 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 3 did not generate
the interrupt 1 - External interrupt 3 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ3 bit
Interrupt status bit for External Interrupt 2.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 3 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 2 did not generate
the interrupt 1 - External interrupt 2 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ2 bit
Interrupt status bit for External Interrupt 1.
This bit is valid if there is an interrupt asserted on INTERRUPT no. 2 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 1 did not generate
the interrupt 1 - External interrupt 1 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ1 bit
Interrupt status bit for External Interrupt 0.
(R/NW)
3–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x XINT Register Descriptions
Table 3-7:
XINT_EXT_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
This bit is valid if there is an interrupt asserted on INTERRUPT no. 1 as mentioned
in System Interrupts and exceptions chapter 0 - External interrupt 0 did not generate
the interrupt 1 - External interrupt 0 generated the interrupt This is a read only register bit. This can be cleared by writing 1 to EICLR.IRQ0 bit
ADuCM302x Mixed-Signal Control Processor Hardware Reference
3–11
ADuCM302x XINT Register Descriptions
Non-maskable interrupt clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CLR (R/W)
NMI clear
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 3-4: XINT_NMICLR Register Diagram
Table 3-8:
XINT_NMICLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 CLR
(R/W)
3–12
NMI clear.
Set to 1 to clear an interrupt status flag when the NMI interrupt is set. Cleared automatically by hardware.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Power Management (PMG)
4 Power Management (PMG)
This chapter provides an overview of the functional architecture and implementation of the Power Management and
power modes used in the ADuCM302x processor.
PWR Features
The features include:
• High efficiency Buck Converters to reduce power.
• Buck Converter for active mode. Needs external flying capacitors.
• Customized clock gating for active modes.
• Power Gating to reduce leakage in sleep modes.
• Voltage monitoring.
• Flexible sleep modes with smart peripherals.
• Deep sleep modes with no retention.
PWR Functional Description
This section provides information on the power management function of the ADuCM302x processor.
The system has two voltage domains:
• VBAT: Input Voltage with a range from 1.8 V - 3.6 V.
• VREG: Internally generated voltage with a range of 1.2 V +/- 10%.
ADuCM302x PMG Register List
Table 4-1:
ADuCM302x PMG Register List
Name
Description
PMG_CTL1
HPBUCK control
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–1
PWR Functional Description
Table 4-1:
ADuCM302x PMG Register List (Continued)
Name
Description
PMG_IEN
Power Supply Monitor Interrupt Enable
PMG_PSM_STAT
Power supply monitor status
PMG_PWRKEY
Key protection for PWRMOD and SRAMRET
PMG_PWRMOD
Power Mode Register
PMG_RST_STAT
Reset status
PMG_SHDN_STAT
SHUTDOWN Status Register
PMG_SRAMRET
Control for Retention SRAM during HIBERNATE Mode
ADuCM302x PMG_TST Register List
Table 4-2:
ADuCM302x PMG_TST Register List
Name
Description
PMG_TST_CLR_LATCH_GPIOS
CLEAR GPIO AFTER SHUTDOWN MODE
PMG_TST_SCRPAD_3V_RD
SCRATCH PAD SAVED IN BATTERY DOMAIN
PMG_TST_SCRPAD_IMG
SCRATCH PAD IMAGE
PMG_TST_SRAM_CTL
Control for SRAM parity and instruction SRAM
PMG_TST_SRAM_INITSTAT
Initialization Status Register
Power-up Sequence
The systems powers up when the battery is above 1.6 V. The Buck Converter is disabled during the power up sequence, so the system starts in LDO mode. The user can switch to Buck mode if required. The Buck provides lowest
dynamic power at the expense of five extra pins, so the user can tradeoff between external components and active
power. The Buck can be enabled by writing to the PMG_CTL1 register.
PWR Operating Modes
The ADuCM302x processor supports the following power modes:
• Active Mode: Cortex-M3 is executing from Flash/SRAM.
• Flexi Mode: Cortex-M3 is disabled. User selects the peripherals to be enabled: DMA/SPI, DMA/I2C and so
on.
• Hibernate Mode: System power gated. 8 KB of SRAM is always retained. Up to an addition of 24 KB SRAM
can be selected to be retained. The registers in each of the peripherals that are retained in this mode are enumerated in each chapter.
• Shutdown Mode: Non-Retain State; pins retain values.
4–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
PWR Operating Modes
Active Mode
In this mode, the part is up and running. The Cortex-M3 executes instructions from Flash and/or SRAM.
The system is not only clock gated using automatic clock gating techniques, but also clock gates can be selected
using the CLKG_CLK_CTL5 register. Most of the peripherals are automatically clock gated when disabled. The clock
runs only when the peripheral is enabled. An exception to this is I2C, UART, and GPTMR. Those blocks must be
manually clock gated using the CLKG_CLK_CTL5 register.
Writing 1 to the bit in the CLKG_CLK_CTL5 register stops the corresponding clock to the peripheral. After the clock
stops, if the user/software accesses any register in that peripheral, the clock is auto-enabled . Also, writing 0 to the bit
in the CLKG_CLK_CTL5 register enables the corresponding clock to the peripheral.
The CLKG_CLK_CTL5.PERCLKOFF bit can be used to disable all peripherals. This is useful when the Cortex-M3
processor is executing exclusively from SRAM or Flash, and no other peripherals are required.
When the CLKG_CLK_CTL5.PERCLKOFF bit is 1, the clock is gated. The clock is re-enabled if the processor or
DMA is accessing the register of any gated peripherals.
The chips power-up with the LDO. Buck can be enabled to save power consumption, by writing to the PMG_CTL1
register.
Flexi Mode
In this mode, the Cortex-M3 is always disabled. This mode is entered by the PM Mode set to 0 and executing WFI.
Writing 1 to the bit in the CLKG_CLK_CTL5 register stops the corresponding clock to the peripheral.
After the clock stops, if the user/software accesses any register in that peripheral , the clock is auto-enabled . Also,
writing 0 to the bit in CLKG_CLK_CTL5 register enables the corresponding clock to the peripheral.
The clock for all other blocks in the system runs if the peripheral is enabled.
This mode adds flexibility to the user to determine the blocks that are enabled while the Cortex is sleeping. For
example, the user can perform DMA transactions through SPI or I2C, or ADC conversions to DMA without processor interaction. This mode can be used to substantially reduce active power when a very low speed activity is
expected to complete (for example, reading a certain number of bytes from a sensor, and so on) before the processor
can be woken up for processing the data.
Hibernate Mode
In this mode, the Cortex-M3 and all digital peripherals are OFF. The SRAM does not retain the entire 64 KB, but
only the lower 32 KB, 24 KB, 16 KB or 8 KB. Important information must be kept on the lower SRAM before
moving to the Hibernate mode.
As a user, you can select:
1. The amount of SRAM to retain 16 KB or 8 KB or both. This is in addition to the 8 KB of SRAM always
retained in the Hibernate mode. This selection is controlled using the PMG_TST_SRAM_CTL register.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–3
PWR Operating Modes
2. The RTC/WakeUp Timer with a 32 kHz crystal or with the internal 32 kHz oscillator. The crystal provides a
higher accuracy clock at the expense of extra power consumption.
3. Control battery monitoring during the Hibernate mode. The regulated 1.2 V supply is always monitored to
guarantee data is never corrupted by the supply going below the minimum retention voltage. If the regulated
supply falls below 1 V, the chip resets before any data is corrupted. Though the regulated supply is always
monitored, there is an option to also monitor the battery in the Hibernate mode. This is done using the
PMG_PWRMOD register.
NOTE: Switch to HFOSC before going to the Hibernate mode if running from PLL, external clock, or HF XTAL.
For more information, refer to Configuring Hibernate Mode.
Memory Configuration
When entering the Hibernate mode, you are presented with the option to retain only lower 8 KB, lower 16 KB, or
lower 32 KB of a total of 64 KB. This selection option is the controller with the PMG_TST_SRAM_CTL register.
There is no option to retain the higher 32 KB of SRAM during Hibernate mode. The lowest 8 KB is always retained
during the Hibernate mode, irrespective of the configuration set in the PMG_TST_SRAM_CTL register.
For more information, refer to SRAM Region.
Shutdown Mode
The Shutdown mode is the deepest sleep mode where all the digital and analog circuits are powered down except for
a wake up controller and a failsafe. These circuits are powered from the battery voltage. The LDOs are OFF, so the
1.2 V region is shutdown.
The state of the digital core will not be retained and the SRAM memory content will not be preserved. When the
part wakes up from Shutdown mode, it follows the POR sequence and the code execution starts from the beginning.
The user can read the PMG_SHDN_STAT register to see the wake up source from this mode. There are four possible
wake up sources:
• External interrupts, limited to three external interrupts to save power.
• External reset.
• Battery falling below 1.6 V.
• RTC Timer (if this option has been enabled by the customer). Only available with the crystal oscillator. The LF
Oscillator is OFF during Shutdown mode.
During this mode, the state of the pads and the wakeup interrupt configuration are preserved.
The configuration of the pads is preserved, but it is also locked after waking up from Shutdown mode. The user
needs to unlock the state of the PADS by writing the value 0x58FA to register PMG_TST_CLR_LATCH_GPIOS. It is
recommended to perform the write inside the ISR routine.
4–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Programming Sequence
The user can only go to Shutdown with the HFOSC. It will not go to Shutdown mode if running from PLL, external clock or HF XTAL. The user needs to switch to HFOSC before going to Shutdown mode.
There is also a scratch pad available for the user during Shutdown mode. The scratch pad consists of a 32bit register.
The intention of the scratch pad is for the user to save some data on 3V before all the information is lost in Shutdown mode.
The user can write to the PMG_TST_SCRPAD_IMG at any time. This is a write-read register. The information saved
in this register will be copied to an area in VBAT before going to the Shutdown mode. This information in VBAT
can be accessed through PMG_TST_SCRPAD_3V_RD, which is a read-only register.
NOTE: You need to switch to HFOSC before going to Shutdown mode if running from PLL, external clock, or HF
XTAL.
For more information, refer to Configuring Shutdown Mode.
Programming Sequence
The power mode sequence has two modes:
• Hibernate mode
• Shutdown mode
Configuring Hibernate Mode
The Hibernate mode, also called PD2, is the lowest power-down mode with state retention. Digital information and
SRAM 0 is always retained, but retaining SRAM 1 and SRAM2 is optional. Refer to SRAM Region.
It is also optional to monitor the battery while in the Hibernate mode. The PMG_CTL1 register provides information
about the battery state. These bits also generate interrupts. Therefore, the battery is within safe margin voltages 3.6
V and 2.75 V. The battery voltage between 2.75 V and 2.3 V in the BG1 region can also be considered a safe region,
but is an indication that the battery is decaying. In the BG2 region, the battery voltage below 2.3 V is an indication
that the battery is dying.
NOTE: It is advisable to enter the Hibernate mode and stop monitoring the battery when the chip is in Safe or BG1
region.
1. Select PD2.
2. Select SLEEPDEEP bit in the Cortex-M3.
3. Enable wake-up interrupt.
4. If a wake-up from RTC1 is required, select LF OSC or crystal as the wake-up source.
5. If battery monitor is required, select the PMG_PWRMOD register.
6. Execute the WFI/WFE instruction.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–5
Programming Sequence
The chip is in the Sleep mode.
When a wake-up interrupt arrives, the part exits Hibernate mode and serves the interrupt routine.
NOTE: Switch to HFOSC before going to Hibernate mode if running from PLL, external clock, or HF XTAL.
Configuring Shutdown Mode
The Shutdown mode, also called PD3, is the deepest power-down mode. No state information is retained during
this mode and the chip will restart from reset after waking up.
The wake-up sources available are external reset, external interrupts limited only to three and RTC0 with the crystal
oscillator if the application needs periodic wake ups. The internal low frequency oscillator is disabled during this
mode. The only clock available in this mode is the crystal and is optional.
The following steps describe the sequence to enter this mode:
1. Select PD3.
2. Set the SLEEPDEEP bit in Cortex-M3.
3. Enable wake up interrupt.
4. If a wake up from RTC0 is required, select crystal as the clock source.
5. Execute the WFI instruction.
The chip is in sleep mode.
NOTE: Switch to HFOSC before going to Shutdown mode if running from PLL, external clock, or HF XTAL.
When a wake-up interrupt arrives, the part exits Shutdown mode and the chip wakes up to a POR scenario.
The sequence is as follows:
1. Read the Shutdown STATUS register.
2. Enable the interrupt routine that caused the wake-up event.
3. The chip jumps to the enabled ISR and served the interrupt routine.
NOTE: It is advisable to write PMG_PWRMOD back to 0 in the ISR after waking up from the Shutdown mode.
Wake-up Sequence
This section describes the wake-up mechanism for different power-down modes. The wake-up is triggered by an
interrupt or a reset. The sequence for the wake-up is different depending on the power mode.
If the wake-up is triggered by a coming interrupt, then the system first executes the interrupt routine.
The wake-up sequence is different for Shutdown mode. The information is not retained, and therefore the system
will always start from reset state after waking up. The interrupt triggering the wake-up sequence remains pending in
4–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Monitor Voltage Control
the Cortex-M3 until interrupt routine is enabled at the restart of the code. The status register can be read after waking up from Shutdown mode and the interrupt routine can be enabled.
Refer to the table titled Interrupt Sources in the Events Overview chapter that summarizes the interrupts and wake
up sources for power modes.
Monitor Voltage Control
Voltage Supervisory circuits are enabled at all times to guarantee that the battery and the regulated supply are always
within operating levels. The circuit monitoring these supplies is called PMG.
The main features for the PMG during active mode are:
• Monitor battery voltage
• Generates an alarm to the processor if battery supply is below 1.83 V
• Generates a reset to the chip if battery supply is below 1.6 V
• Monitors the state of the battery. Generate interrupts
Battery between: 3.6 V - 2.75 V
Battery between: 2.75 V - 2.3 V Generates interrupt BR1
Battery between: 2.3 V - 1.6 V Generates interrupt BR 2
• Monitors regulated supply
• Generates an interrupt if the regulated supply is above 1.32 V (overvoltage)
• Generates an interrupt if the regulated supply is below 1.1 V (undervoltage)
• Generates a reset if the regulated supply is below 1.08 V
The main features for the PMG during hibernate mode are:
• Monitor battery voltage
• Generates an alarm to the processor if supply is below 1.83 V - Optional
• Generates a reset to the chip if supply is below 1.6 V - Optional
• Monitors the state of the battery. Optional
Battery between: 3.6 V - 2.75 V
Battery between: 2.75 V - 2.3 V Generates interrupt BR1
Battery between: 2.3 V - 1.6 V Generates interrupt BR2
• Monitors regulated supply
• Generates a reset if the regulated supply is below 1.08 V
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–7
ADuCM302x PMG Register Descriptions
There is also the possibility to have an interrupt when the voltage is between 3.6 V - 2.7 V. The battery and VREG
supply monitors are shown below.
Figure 4-1: Battery Supply Monitor
VREG
1V
0V
1.1V
1.0V
1.0V 1.1V
VREG INT
VBAT RESET
Figure 4-2: VREG Supply Monitor
ADuCM302x PMG Register Descriptions
Power Management Registers (PMG) contains the following registers.
Table 4-3:
ADuCM302x PMG Register List
Name
Description
PMG_CTL1
HPBUCK control
PMG_IEN
Power Supply Monitor Interrupt Enable
4–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x PMG Register Descriptions
Table 4-3:
ADuCM302x PMG Register List (Continued)
Name
Description
PMG_PSM_STAT
Power supply monitor status
PMG_PWRKEY
Key protection for PWRMOD and SRAMRET
PMG_PWRMOD
Power Mode Register
PMG_RST_STAT
Reset status
PMG_SHDN_STAT
SHUTDOWN Status Register
PMG_SRAMRET
Control for Retention SRAM during HIBERNATE Mode
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–9
ADuCM302x PMG Register Descriptions
HPBUCK control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
HPBUCKEN (R/W)
Enable HP Buck
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-3: PMG_CTL1 Register Diagram
Table 4-4:
PMG_CTL1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 HPBUCKEN
Enable HP Buck.
(R/W)
4–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x PMG Register Descriptions
Power Supply Monitor Interrupt Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
IENBAT (R/W)
Interrupt enable for VBAT range
VBAT (R/W)
Enable Interrupt for VBAT
RANGEBAT (R/W)
Battery Monitor Range
VREGUNDR (R/W)
Enable Interrupt when VREG under-voltage:
below 1V
VREGOVR (R/W)
Enable Interrupt when VREG over-voltage:
over- 1.32V
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-4: PMG_IEN Register Diagram
Table 4-5:
PMG_IEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
10 IENBAT
(R/W)
9:8 RANGEBAT
(R/W)
Interrupt enable for VBAT range.
Set this bit if interrupt needs to be generated for appropriate PMG_IEN.RANGEBAT.
Configure the appropriate PMG_IEN.RANGEBAT for which interrupt to be generated
and then set this bit. Interrupt will be generated if VBAT falls in the
PMG_IEN.RANGEBAT. e.g. if battery is GOOD, and user would like to monitor the
battery, user has to configure in PMG_PSM_STAT.RANGE2 or
PMG_PSM_STAT.RANGE3, user has to clear all PMG_PSM_STAT flags and then enable
this interrupt. Otherwise PMG_PSM_STAT.RANGE1 of battery will keep firing the interrupt.
Battery Monitor Range.
Configure appropriate PMG_IEN.RANGEBAT for which interrupt has to be generated
0 Configure to generate interrupt if VBAT > 2.75V
1 Configure to generate interrupt if VBAT between 2.75V
- 1.6V
2 Configure to generate interrupt if VBAT between 2.3V
- 1.6V
3 N/A
2 VREGOVR
Enable Interrupt when VREG over-voltage: over- 1.32V.
(R/W)
1 VREGUNDR
(R/W)
0 VBAT
Enable Interrupt when VREG under-voltage: below 1V.
If enabled, the irq connects to NMI (non-maskable interrupt)
Enable Interrupt for VBAT.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–11
ADuCM302x PMG Register Descriptions
Table 4-5:
PMG_IEN Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
(R/W)
4–12
If enabled, the irq connects to NMI (non-maskable interrupt) if enabled, it generates
an interrupt if VBAT < 1.83v
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x PMG Register Descriptions
Power supply monitor status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RORANGE3 (R)
VBAT range3 (2.3v - 1.6v)
VBATUNDR (R/W1C)
Status bit indicating an Alarm that battery
is below 1.8V.
RORANGE2 (R)
VBAT range2 (2.75v - 2.3v)
VREGUNDR (R/W1C)
Status bit for Alarm indicating VREG
is below 1V.
RORANGE1 (R)
VBAT range1 (> 2.75v)
RANGE3 (R/W1C)
VBAT range3 (2.3v - 1.6v)
VREGOVR (R/W1C)
Status bit for alarm indicating Overvoltage
for VREG
RANGE2 (R/W1C)
VBAT range2 (2.75v - 2.3v)
WICENACK (R)
WIC Enable Acknowledge from Cortex
RANGE1 (R/W1C)
VBAT range1 (> 2.75v)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-5: PMG_PSM_STAT Register Diagram
Table 4-6:
PMG_PSM_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 RORANGE3
(R/NW)
VBAT range3 (2.3v - 1.6v).
read-only status bit
0 VBAT NOT in the range specified
1 VBAT in the range specified
14 RORANGE2
(R/NW)
VBAT range2 (2.75v - 2.3v).
read-only status bit
0 VBAT NOT in the range specified
1 VBAT in the range specified
13 RORANGE1
(R/NW)
VBAT range1 (> 2.75v).
Read-only status bit.
0 VBAT NOT in the range specified
1 VBAT in the range specified
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–13
ADuCM302x PMG Register Descriptions
Table 4-6:
PMG_PSM_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 RANGE3
(R/W1C)
VBAT range3 (2.3v - 1.6v).
This is a write-one-to-clear status bit indicating the relevant VBAT range. Generates
VBAT range interrupt if PMG_IEN.IENBAT is set. Note : The status bit will be set
again even after '1' is written (to clear the flag) to the flag, if VBAT falls in the range
specified.
0 VBAT NOT in the range specified
1 VBAT in the range specified
9 RANGE2
(R/W1C)
VBAT range2 (2.75v - 2.3v).
This is a write-one-to-clear status bit indicating the relevant VBAT range. Generates
VBAT range interrupt if PMG_IEN.IENBAT is set. Note : The status bit will be set
again even after '1' is written(to clear the flag) to the flag, if VBAT falls in the range
specified.
0 VBAT NOT in the range specified
1 VBAT in the range specified
8 RANGE1
(R/W1C)
VBAT range1 (> 2.75v).
This is a write-one-to-clear status bit indicating the relevant VBAT range. Generates
VBAT range interrupt if PMG_IEN.IENBAT is set. Note : The status bit will be set
again even after '1' is written (to clear the flag) to the flag, if VBAT falls in the range
specified.
0 VBAT NOT in the range specified
1 VBAT in the range specified
7 WICENACK
WIC Enable Acknowledge from Cortex.
(R/NW)
2 VREGOVR
(R/W1C)
1 VREGUNDR
(R/W1C)
0 VBATUNDR
(R/W1C)
4–14
Status bit for alarm indicating Overvoltage for VREG.
Bit set if VREG (LDO out) > 1.32v Generates an interrupt if PMG_IEN.VREGOVR is
set. This is write-1-to-clear bit Note : The status bit will be set again even after '1' is
written (to clear the flag) to the flag, if VREG is > 1.32v
Status bit for Alarm indicating VREG is below 1V..
Generates an interrupt if PMG_IEN.VREGUNDR is set. This bit will be set if VREG <
1v This is a write-one-to-clear bit. Note : The status bit will be set again even after '1'
is written (to clear the flag) to the flag, if VREG is < 1v
Status bit indicating an Alarm that battery is below 1.8V..
Generates an interrupt if PMG_IEN.VBAT is set. This bit will be set if VBAT < 1.83v
This is a write-one-to-clear bit. Note : The status bit will be set again even after '1' is
written (to clear the flag) to the flag, if VBAT is < 1.83v
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x PMG Register Descriptions
Key protection for PWRMOD and SRAMRET
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Power control key register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-6: PMG_PWRKEY Register Diagram
Table 4-7:
PMG_PWRKEY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
Power control key register.
The PMG_PWRMOD and PMG_SRAMRET registers is key-protected. One write to the key
is necessary to change the value in the PMG_PWRMOD and PMG_SRAMRET registers and
Key to be written is 0x4859. The PMG_PWRMOD and PMG_SRAMRET registers should
then be written. A write to any other register on the APB bus before writing to
PMG_PWRMOD or PMG_SRAMRET will return the protection to the lock state.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–15
ADuCM302x PMG Register Descriptions
Power Mode Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MONVBATN (R/W)
Monitor VBAT during HIBERNATE Mode.
Monitors VBAT by default
MODE (R/W)
Power Mode Bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-7: PMG_PWRMOD Register Diagram
Table 4-8:
PMG_PWRMOD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3 MONVBATN
(R/W)
1:0 MODE
(R/W)
Monitor VBAT during HIBERNATE Mode. Monitors VBAT by default.
0 VBAT monitor enabled in PMG block 1 VBAT monitor disabled in PMG block default = 0 VDD Monitoring cannot be disabled
Power Mode Bits.
0 FLEXI Mode
1 Reserved
2 HIBERNATE Mode
3 SHUTDOWN Mode
4–16
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x PMG Register Descriptions
Reset status
This register is recommended to be read at the beginning of the user-code to determine the cause of the reset. Default values of this register is 'unspecified' because the cause of reset can be any source.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
0
0
0
X X X X X X
4
3
2
1
0
PORSRC (R)
Power on reset Source (pmg_rst_src)
POR (R/W)
Power-on reset
SWRST (R/W)
Software reset
EXTRST (R/W)
External reset
WDRST (R/W)
Watchdog timeout
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-8: PMG_RST_STAT Register Diagram
Table 4-9:
PMG_RST_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5:4 PORSRC
(R/NW)
Power on reset Source (pmg_rst_src).
This bit contains additional details after a power-on-reset occurs.
0 POR triggered because VBAT drops below Fail Safe
1 POR trigger because VBAT supply (VBAT<1.7v)
2 POR triggered because VDD supply (VDD < 1.08v)
3 POR triggered because VREG drops below Fail Safe
3 SWRST
(R/W)
2 WDRST
(R/W)
1 EXTRST
(R/W)
0 POR
(R/W)
Software reset.
Software reset. Set automatically to 1 when the Cortex system reset is generated.
Cleared by writing 1 to the bit. This bit is also cleared when power-on-reset is triggered
Watchdog timeout.
Set automatically to 1 when a watchdog timeout occurs. Cleared by writing 1 to the
bit. This bit is also cleared when power-on-reset is triggered
External reset.
Set automatically to 1 when an external reset occurs. Cleared by writing 1 to the bit.
This bit is also cleared when power-on-reset is triggered
Power-on reset.
Set automatically when a power-on reset occurs. Cleared by writing one to the bit.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–17
ADuCM302x PMG Register Descriptions
SHUTDOWN Status Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTC (R)
Interrupt from RTC
EXTINT0 (R)
Interrupt from External Interrupt 0
EXTINT2 (R)
Interrupt from External Interrupt 2
EXTINT1 (R)
Interrupt from External Interrupt 1
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-9: PMG_SHDN_STAT Register Diagram
Table 4-10:
PMG_SHDN_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3 RTC
Interrupt from RTC.
(R/NW)
2 EXTINT2
Interrupt from External Interrupt 2.
(R/NW)
1 EXTINT1
Interrupt from External Interrupt 1.
(R/NW)
0 EXTINT0
Interrupt from External Interrupt 0.
(R/NW)
4–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x PMG Register Descriptions
Control for Retention SRAM during HIBERNATE Mode
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BNK2EN (R/W)
Enable retention bank 2 (16kB)
BNK1EN (R/W)
Enable retention bank 1 (8kB)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-10: PMG_SRAMRET Register Diagram
Table 4-11:
PMG_SRAMRET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1 BNK2EN
Enable retention bank 2 (16kB).
(R/W)
0 BNK1EN
Enable retention bank 1 (8kB).
(R/W)
ADuCM302x PMG_TST Register Descriptions
Power Management Registers (PMG_TST) contains the following registers.
Table 4-12:
ADuCM302x PMG_TST Register List
Name
Description
PMG_TST_CLR_LATCH_GPIOS
CLEAR GPIO AFTER SHUTDOWN MODE
PMG_TST_SCRPAD_3V_RD
SCRATCH PAD SAVED IN BATTERY DOMAIN
PMG_TST_SCRPAD_IMG
SCRATCH PAD IMAGE
PMG_TST_SRAM_CTL
Control for SRAM parity and instruction SRAM
PMG_TST_SRAM_INITSTAT
Initialization Status Register
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–19
ADuCM302x PMG_TST Register Descriptions
CLEAR GPIO AFTER SHUTDOWN MODE
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Writing 0x58FA creates a pulse to clear
the latches for the GPIOs
Figure 4-11: PMG_TST_CLR_LATCH_GPIOS Register Diagram
Table 4-13:
PMG_TST_CLR_LATCH_GPIOS Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
Writing 0x58FA creates a pulse to clear the latches for the GPIOs.
(RX/W)
4–20
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x PMG_TST Register Descriptions
SCRATCH PAD SAVED IN BATTERY DOMAIN
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DATA[15:0] (R)
Read Only register. Reading the scratch
pad stored in shutdown mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DATA[31:16] (R)
Read Only register. Reading the scratch
pad stored in shutdown mode
Figure 4-12: PMG_TST_SCRPAD_3V_RD Register Diagram
Table 4-14:
PMG_TST_SCRPAD_3V_RD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 DATA
Read Only register. Reading the scratch pad stored in shutdown mode.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–21
ADuCM302x PMG_TST Register Descriptions
SCRATCH PAD IMAGE
This register is useful in Shutdown mode. The GPIO configuration, OUT registers lose its contents when in shutdown mode. 32-bit Scratch register can be used to store the GPIO configuration. Note that the bits are not wide
enough to store all GPIO related configuration and output values. It is envisaged that the user might have only few
combination of shutdown port configurations. Hence these combination can be remembered by storing an equivalent encoded data in the scratch 32-bit registers. The USER after reading back the SCRATCHPAD_3V_READ register (wakeup from shutdown) can determine the GPIO configuration. Note that the scratch register content will be
lost in shutdown mode if VBAT < 1.54v
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DATA[15:0] (R/W)
Anything written to this register will
be saved in 3V when going to shutdown
mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DATA[31:16] (R/W)
Anything written to this register will
be saved in 3V when going to shutdown
mode
Figure 4-13: PMG_TST_SCRPAD_IMG Register Diagram
Table 4-15:
PMG_TST_SCRPAD_IMG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 DATA
(R/W)
4–22
Anything written to this register will be saved in 3V when going to shutdown mode.
Anything written to this register will be saved in 3V when going to shutdown mode
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x PMG_TST Register Descriptions
Control for SRAM parity and instruction SRAM
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ABTINIT (R/W)
Abort current initialization. Self-cleared
BNK0EN (R/W)
Enable initialization
AUTOINIT (R/W)
Automatic initialization on wake up from
Hibernate mode
BNK1EN (R/W)
Enable initialization
BNK2EN (R/W)
Enable initialization
STARTINIT (R/W)
Write one to trigger initialization. Self-cleared
BNK3EN (R/W)
Enable initialization
BNK5EN (R/W)
Enable initialization
BNK4EN (R/W)
Enable initialization
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
INSTREN (R/W)
Enables instruction SRAM
PENBNK0 (R/W)
Enable parity check
PENBNK5 (R/W)
Enable parity check
PENBNK1 (R/W)
Enable parity check
PENBNK4 (R/W)
Enable parity check
PENBNK2 (R/W)
Enable parity check
PENBNK3 (R/W)
Enable parity check
Figure 4-14: PMG_TST_SRAM_CTL Register Diagram
Table 4-16:
PMG_TST_SRAM_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31 INSTREN
Enables instruction SRAM.
(R/W)
21 PENBNK5
Enable parity check.
(R/W)
20 PENBNK4
Enable parity check.
(R/W)
19 PENBNK3
Enable parity check.
(R/W)
18 PENBNK2
Enable parity check.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–23
ADuCM302x PMG_TST Register Descriptions
Table 4-16:
PMG_TST_SRAM_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
17 PENBNK1
Enable parity check.
(R/W)
16 PENBNK0
Enable parity check.
(R/W)
15 ABTINIT
Abort current initialization. Self-cleared.
(R/W)
14 AUTOINIT
Automatic initialization on wake up from Hibernate mode.
(R/W)
13 STARTINIT
Write one to trigger initialization. Self-cleared.
(R/W)
5 BNK5EN
Enable initialization.
(R/W)
4 BNK4EN
Enable initialization.
(R/W)
3 BNK3EN
Enable initialization.
(R/W)
2 BNK2EN
Enable initialization.
(R/W)
1 BNK1EN
Enable initialization.
(R/W)
0 BNK0EN
Enable initialization.
(R/W)
4–24
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x PMG_TST Register Descriptions
Initialization Status Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BNK5 (R)
0:Not initialized; 1:Initialization completed
BNK0 (R)
0:Not initialized; 1:Initialization completed
BNK4 (R)
0:Not initialized; 1:Initialization completed
BNK1 (R)
0:Not initialized; 1:Initialization completed
BNK3 (R)
0:Not initialized; 1:Initialization completed
BNK2 (R)
0:Not initialized; 1:Initialization completed
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-15: PMG_TST_SRAM_INITSTAT Register Diagram
Table 4-17:
PMG_TST_SRAM_INITSTAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5 BNK5
0:Not initialized; 1:Initialization completed.
(R/NW)
4 BNK4
0:Not initialized; 1:Initialization completed.
(R/NW)
3 BNK3
0:Not initialized; 1:Initialization completed.
(R/NW)
2 BNK2
0:Not initialized; 1:Initialization completed.
(R/NW)
1 BNK1
0:Not initialized; 1:Initialization completed.
(R/NW)
0 BNK0
0:Not initialized; 1:Initialization completed.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
4–25
System Clocks (SCLK)
5 System Clocks (SCLK)
The ADuCM302x processor is integrated with two on-chip oscillators and the circuitry for two external crystals.
System Clock Features
The features include the following:
• LFOSC is a 32 kHz internal oscillator
• HFOSC is a 26 MHz internal oscillator
• LFXTAL is a 32 kHz external crystal oscillator
• HFXTAL is a 16 MHz or 26 MHz external crystal oscillator
• External clock input through GPIO_CLKIN
• One on-chip phase-locked loop (PLL) is available: the system PLL (SPLL). PLL can use either the HFOSC or
the HFXTAL as an input clock.
• The high frequency oscillators (HFOSC and HFXTAL), along with the output of the SPLL and
GPIO_CLKIN, can be used to generate the root clock.
• The 32 kHz clock (LF_CLK) is generated from either LFXTAL or LFOSC to drive certain blocks, including
the beeper. The general-purpose timers have their own multiplexers to select their clock source.
• The RTC1 works from LFXTAL or LFOSC in Hibernate mode and active mode. The RTC0 always works
from LFXTAL in Shutdown/Hibernate/Active modes.
• Watchdog Timer always works on LFOSC Oscillator. It cannot be run using LFXTAL to avoid reliability issues. It does not work in the Hibernate or Shutdown mode.
• The root clock is divided into several internal clocks.
• RCLK clocks the reference timer (counter) in flash controller. This is used to time flash erase, write operations.
By default, it is always connected to 13 MHz clock source. This is generated by ½ divider connected to
HFOSC (26 MHz). So, the default values of flash timer registers correspond to 13 MHz clock. If
RCLKMUX[1:0] = 11(HFXTAL = 16 MHz), the ½ DIV (divider) is automatically bypassed and 16 MHz
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–1
System Clock Functional Description
HFXTAL is directly connected to the RCLK. Therefore, if HFXTAL 16 MHz is used, flash timer registers need
to be programmed to 16 MHz before any flash erase/write operations.
• HP_BUCK_CLK clocks the HP Buck module. When HPBUCK is enabled, this clock is always 200 kHz.
System Clock Functional Description
This section provides information on the clocks and the clock gates required for power management.
ADuCM302x CLKG_OSC Register List
Table 5-1:
ADuCM302x CLKG_OSC Register List
Name
Description
CLKG_OSC_CTL
Oscillator Control
CLKG_OSC_KEY
Key Protection for OSCCTRL
ADuCM302x CLKG_CLK Register List
Table 5-2:
ADuCM302x CLKG_CLK Register List
Name
Description
CLKG_CLK_CTL0
Misc clock settings
CLKG_CLK_CTL1
Clock dividers
CLKG_CLK_CTL3
System PLL
CLKG_CLK_CTL5
User clock gating control
CLKG_CLK_STAT0
Clocking status
System Clock Block Diagram
The clocking diagram is shown below.
5–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
System Clock Functional Description
PLL
HF
External
XTAL16/
26MHz
26 MHz
SPLL
SPLL_MUX
PCLK
ROOT_CLK
HF Internal
OSC
HF_OSC_CLK
26 MHz
CG
PDIV
PERCLKOFF
ROOT_CLK_MUX
SYS_CLKIN
PCLK Self Gated
Peripherals
CG
PCLK_I2C
I2C-OFF
RTC0
LF External
XTAL32KHz
HDIV
AHB Sub System
Clock
LF_CLK
Beeper
LF Internal
OSC32KHz
RTC1
LFCLK_MUX
DIV/2
or/1
HF XTAL
16/26 MHz
WDT
LFXTAL
LFOSC
RCLK_MUX
200KHz
clock
GPT[0/1/2]_CLK
CG
PCLK
RCLK (Flash)
HP_BUCK_CLK
HFOSC_CLK
GPT_CLK MUX
CG - Clock - Gate
Figure 5-1: Clocking Diagram
Clock Muxes
As shown in the Clocking Diagram, there are four clock source multiplexers:
• Root Clock selection Mux (Root Clock Mux)
• Low frequency clock Mux (LFCLK Mux)
• SPLL input Mux (SPLL Mux)
• RCLK Mux controlled using MMRs
The multiplexer for general-purpose timers are controlled through registers within the Timer block.
NOTE: Ensure that the desired clock input is available and stable for the clock selection made for the clock mux.
Otherwise, situations where the system can be locked out of a stable clock can arise.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–3
System Clock Functional Description
Table 5-3:
Clock Muxes
Clocks
Registers
Selection
Root Clock Mux
CLKCON0[1:0]
00: HFOSC
01: HFXTAL
10: SPLL
11: External clock through SYS_CLKIN
SPLL Mux
CLKCON0[11]
0: HFOSC
1: HFXTAL
LFCLK Mux
OSCCTRL[0]
0: LFOSC
1: LFXTAL
RCLK Mux
CLKCON0[9:8]
00: HF Osc
01: Reserved
10: HF XTAL 26 MHz
11: Reserved
GPTX_CLK Mux
GPTXCON[6:5]
Controlled by the General-Purpose Timer 0/ General-Purpose Timer 1/
General-Purpose Timer 2. For more information, please refer to the registry description in the Timer chapter.
Clock Dividers
Three programmable clock dividers are available to generate the clocks in the system. A clock divider integer divides
the input clock down to a new clock. The division range is from 1 to 32. Division selection can be made on the fly.
The output remains glitch free and stretches the high time, never creating a high time shorter than the pre or post
value of the clock period.
Two clock dividers use the root clock as an input and generate the core and peripheral synchronized clocks. The
clock dividers are cascaded in such a way that each stage initially releases its divided clock in a sequence. The last
stage informs all other stages that its divided clock is ready to be output. The effect of this cascading is that divided
clocks are released synchronously when new divider values are programmed. Initial edges of each clock are mutually
aligned.
The Clock Dividers table summarizes the inputs and outputs of each clock divider along with the register bits to
program them.
Table 5-4:
Clock Dividers
Divider
Input Clock
Output Clocks
Register, Bits
0
Root clock
HCLK_CORE, HCLK_BUS
CLKG_CLK_CTL1.HCLKDIVCNT
1
Root clock
PCLK, all peripheral CLKs
CLKG_CLK_CTL1.PCLKDIVCNT
Only certain divider ratios are legal between PCLK and HCLK. Specifically, the following rules must be respected:
• The frequency of PCLK must always be smaller or equal to the frequency of HCLK.
5–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
System Clock Functional Description
• The ratio of the dividers must be an integer.
In general, clock division can be changed on the fly during normal operation.
Clock Gating
In the case of certain clocks, clocks can be individually gated depending on the power mode or register settings. For
more information about clock gating and power modes, refer to the Power Management chapter.
The clock gates of the peripheral clocks are user controllable in certain power modes. Register CLKG_CLK_CTL5 can
be programmed to turn off certain clocks, depending on user application. Set the respective bits to a 1 in
CLKG_CLK_CTL5 to disable clock.
PLL Settings
The PLL Diagram shows the abstract PLL structure for SPLL. It has the multiplier coefficient N and divider coefficient M to decide the output clock ratio of N/M. There is an optional DIV2 built in the PLL to either divide down
the PLL output clock by 2 or directly output it. This is also an optional MUL2 built-in to PLL to multiply the clock
out of PLL by 2 to increase the range of the PLL.
The PLL should always switch away from ROOT_CLK when changing any coefficients or clock sources.
When the reference clock for the phase frequency detector (PFD) has a 2 MHz input, the PLL has its best phase
margin. Therefore, it is recommended that for a 26 MHz crystal clock input, configure M as 13, and for a 16 MHz
crystal clock input, configure M as 8.
Clock in
1/M
PFD
VCO
1/N
DIV2
1/MUL2
Figure 5-2: PLL Diagram
PLL output frequency=Clock in * (MUL2*N)/ (DIV2*M)
The PLL Settings table shows the recommend PLL settings for a variety of input and output clocks. The PLL settings can be programmed using the CLKG_CLK_CTL3 register.
To enable the SPLL, the CLKG_CLK_CTL3.SPLLEN bit must be set. The SPLL N multiplier can be set using the
CLKG_CLK_CTL3.SPLLNSEL bits.
The M divider can also be set using the CLKG_CLK_CTL3.SPLLMSEL bits. SPLL MUL2 is controlled by
CLKG_CLK_CTL3.SPLLMUL2 bit. DIV2 is controlled by CLKG_CLK_CTL3.SPLLDIV2 bit.
Note that MUL2 = CLKG_CLK_CTL3.SPLLMUL2+1, DIV2 = CLKG_CLK_CTL3.SPLLDIV2 + 1.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–5
PLL Settings
Table 5-5:
PLL Settings
PLL
Input Clock (MHz)
M
MUL2
N
DIV2
Output Clock (MHz)
SPLL
26
13
1
26
2
26
SPLL
16
8
1
26
2
26
The recommended VCO output range is 32 MHz to 60 MHz and the PLL output range is 16 MHz to 60 MHz.
The minimum value of N is 8 (if MUL2=2) and maximum is 31. The recommended output frequency from 1/M
divider is 2 MHz and the minimum value of M = 2.
PLL output frequency=
Clock in* ((CLKG_CLK_CTL3.SPLLMUL2+1)*CLKG_CLK_CTL3.SPLLNSEL)/
((CLKG_CLK_CTL3.SPLLDIV2+1)*CLKG_CLK_CTL3.SPLLMSEL)
PLL Interrupts
Either PLL can interrupt the core when it locks or when it loses its lock. To enable the SPLL interrupts, the
CLKG_CLK_CTL3.SPLLIE bit must be set. The CLKG_CLK_STAT0.SPLLUNLK bit in the CLKG_CLK_STAT0 register indicates that the SPLL unlock event has happened.
The CLKG_CLK_STAT0.SPLLLK bit in the CLKG_CLK_STAT0 register indicates that a SPLL lock event has happened. Both the bits are used to interrupt the core when PLL interrupts are enabled. Both bits are sticky and must
write a 1 to be cleared. These bits are different from the CLKG_CLK_STAT0.SPLL bit in CLKG_CLK_STAT0, which
simply mirrors the value of the SPLL lock signal (1 = locked, 0 = unlocked).
PLL Programming Sequence
To start using the system PLL, the following sequence of events is suggested as an example. The example multiplies a
26 MHz crystal input to 26 MHz through the SPLL and uses it as the root clock. The HCLK is set to 26 MHz and
the PCLK to 6.25 MHz.
1. Enable PLL interrupts. CLKG_CLK_CTL3.SPLLIE = 0x1.
2. Set the PLL input to the external crystal (HFXTAL oscillator). CLKG_CLK_CTL0.CLKMUX = 0x1.
3. Enable the external crystal (HFXTAL oscillator). CLKG_OSC_CTL.HFXTALEN = 0x1.
4. Set the clock dividers consistent with the intended system clock rates. For example, assuming a PLL output of
26 MHz sets the HCLK to 26 MHz and the PCLK to 6.25 MHz. CLKG_CLK_CTL1.PCLKDIVCNT= 0x08
and CLKG_CLK_CTL1.HCLKDIVCNT = 0x01.
5. Set up the PLL M and N values and enable the PLL. CLKG_CLK_CTL3.SPLLEN= 0x1,
CLKG_CLK_CTL3.SPLLMSEL = 0xD, and CLKG_CLK_CTL3.SPLLNSEL = 0x1A.
6. Wait for the PLL interrupt indicating that the PLL has locked. Optionally, also check that the crystal is stable
at this stage, even though the PLL should not lock if the crystal is not stable.
5–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
System Clock Interrupts and Exceptions
7. Clear the PLL interrupt and select PLL as the system clock source. CLKG_CLK_STAT0.SPLLLK = 0x1,
CLKG_CLK_CTL0.CLKMUX = 0x2.
To change PLL clock out frequency from 26 MHz to 16 MHz, assume that CLKG_CLK_CTL1.HCLKDIVCNT and
CLKG_CLK_CTL1.PCLKDIVCNT are programmed to divide by one. Assume that PLL input source is HF XTAL (26
MHz).
1. Enable PLL interrupts. CLKG_CLK_CTL3.SPLLIE = 0x1.
2. Select HF OSC (26 MHz) as the root clock instead of the PLL clock. CLKG_CLK_CTL0.CLKMUX = 0x00
3. Disable PLL, CLKG_CLK_CTL3.SPLLEN = 0x0
4. Program appropriate MSEL, NSEL to get PLL clock out as 16 MHz. CLKG_CLK_CTL3.SPLLMSEL = 0xD,
and CLKG_CLK_CTL3.SPLLNSEL = 0x10
5. Enable PLL, CLKG_CLK_CTL3.SPLLEN = 0x1
6. Wait for the PLL interrupt indicating that the PLL has locked. Optionally, also check that the crystal is stable
at this stage, even though the PLL should not lock if the crystal is not stable.
7. Clear the PLL interrupt and select PLL as the system clock source. CLKG_CLK_STAT0.SPLLLK = 0x1,
CLKG_CLK_CTL0.CLKMUX = 0x2.
System Clock Interrupts and Exceptions
Refer to Events (Interrupts and Exceptions), for more information.
System Clock Programming Model
The following sections provide general programming models.
Oscillators
There are four types of oscillators:
• HF Oscillator:
The 26 MHz high frequency oscillator is enabled by the CLKG_OSC_CTL.HFOSCEN bit. The oscillator accuracy is ±3%.
• LF Oscillator:
The 32.768 kHz low frequency oscillator is enabled always, it cannot be disabled, and it is disabled automatically in the shut-down mode. The oscillator accuracy is ±5%.
• HF XTAL Oscillator:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–7
System Clock Programming Model
The 26 MHz high frequency oscillator is enabled by the CLKG_OSC_CTL.HFXTALEN bit. Lock time is the
time the XTAL takes to give stable clock out after it is enabled. The locking of the oscillator to the correct
frequency is signified by the setting of CLKG_CLK_STAT0.HFXTALOK status bit.
• LF XTAL Oscillator:
The LF XTAL oscillator is the clock source for the RTC. It is used to keep the time of the system. It provides a
32.768 kHz output clock. This is enabled by setting the CLKG_OSC_CTL.HFXTALEN bit.
Once the oscillator is enabled, it remains always on, even in Hibernate, Shutdown mode.
Crystal Programming
The crystals are disabled by default and can be programmed using the CLKG_OSC_CTL register. The crystals can be
enabled by setting the CLKG_OSC_CTL.HFXTALEN or CLKG_OSC_CTL.LFXTALEN bits. The stable signal status
bits are also mirrored in this register.
NOTE: The CLKG_OSC_CTL.HFOSCEN must be set before issuing a SYSRESETREQ and allowing the Cortex-M3
to assert a reset request signal to the systems reset generator. This will ensure that all system components will be reset
properly. This is independent of the Root Clock Mux and the SPLL Clock Mux settings.
Interrupts
Each crystal can interrupt the core when its output clock becomes stable. The interrupts are enabled by setting the
CLKG_CLK_CTL0.HFXTALIE and CLKG_CLK_CTL0.LFXTALIE bits in the CLKG_CLK_CTL0 register. Register
CLKG_CLK_STAT0 contains the stable information pertaining to both crystals.
The CLKG_CLK_STAT0.HFXTAL and CLKG_CLK_STAT0.LFXTAL bits in the CLKG_CLK_STAT0 register contain
the current state of the stable signals of the crystals. The CLKG_CLK_STAT0.HFXTALOK or
CLKG_CLK_STAT0.LFXTALOK bits in the CLKG_CLK_STAT0 register are set when an event is detected on the stable signals of the crystals.
The CLKG_CLK_STAT0.HFXTALOK/ CLKG_CLK_STAT0.HFXTALNOK and CLKG_CLK_STAT0.LFXTALOK/
CLKG_CLK_STAT0.LFXTALNOK bits are sticky and must be cleared by writing a 1 to them.
NOTE: CLKG_CLK_STAT0.HFXTALNOK and CLKG_CLK_STAT0.LFXTALNOK bits are not continuous XTAL
monitors and are only set as a confirmation that the corresponding XTAL has been properly disabled.
PLL Clock Protection
In the event the clock source to the PLL is lost, the PLL will maintain operation at a reduced VCO output frequency of approximately 20 MHz, for approximately 3 to 5 ms, this clock will be active/running until PLL is disabled.
This behavior allows PLL interrupt sources such as CLKG_CLK_STAT0.SPLLUNLK (CLKG_CLK_STAT0 bit 6) to be
serviced and enables the appropriate action to be taken by the core. This feature protects the core from an indefinite
stall due to broken or shorted leads of the XTAL circuit.
5–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
System Clock Programming Model
Oscillator Programming
Both the internal oscillators are enabled by default.
Before issuing a SYSRESETREQ and allowing the Cortex-M3 to assert a reset request signal to the systems reset generator, the CLKG_OSC_CTL.HFOSCEN (CLKG_OSC_CTL bit 1) must be set. This will ensure that all system components are reset properly. This is independent of Root Clock Mux and SPLL Clock Mux settings.
Enabling the HFOSC is done using the CLKG_OSC_CTL.HFOSCEN bit in the CLKG_OSC_CTL register.
NOTE: Before stopping the HFOSC internal oscillator, the HFXTAL should be running the system. Otherwise, the
part locks because its clock has been stopped by the user without possibility of recovery. Peripherals driven with a 32
kHz clock should be switched over to the LFXTAL external crystal oscillator only after ensuring that LFXTAL is
stable and running. LFOSC internal oscillator cannot be disabled.
Setting the System Clocks
Set System Clock to PLL Input Source
The three timing diagrams shown below describe the sequence of events to change system clock from internal oscillator to PLL input source based. In the following figures, Xtal refers to HF XTAL (26 MHz or 16 MHz crystal
oscillator). Timers (GPT) used in the following figures are recommended to have following expiry periods. Beyond
the expiry period if the oscillators are not locked, this denotes that there are issues in the XTAL.
HF XTAL lock timer expiry: 20 ms
LF XTAL lock timer expiry: 1.5 s
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–9
Setting the System Clocks
1. Set System Clock to
oscillator (default)
PLL input
source?
XTAL
2. Turn On XTAL
3. Setup Timer
4. Poll XTAL lock bit
No
OSC
5. Xtal Locked?
Timer ISR: Error, the
XTAL has not locked
6. Disable Timer
7. Select Xtal as PLL
source
8. Setup Timer
9. Program PLL
10. Poll PLL lock bit
No
Timer ISR: Error, the
PLL has not locked
11. PLL Locked?
12. Disable Timer
13. Change System
Clock to PLL
Figure 5-3: Change System Clock To PLL (POLL)
5–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Setting the System Clocks
1. Set System Clock to
oscillator (default)
PLL input source?
XTAL
2. Select XTAL as PLL
source
3. Turn On XTAL
osc
4. Program PLL
5. Setup Timer
6. Pall XTAL lack bit
No
XTAL Locked?
Timer ISR: Error, the
XTAL has not locked
7. Pall PLL lack bit
No
PLL Locked?
Timer ISR: Error, the
PLL has not locked
8. Disable Timer
9. Change System
Clock to PLL
Figure 5-4: Change System Clock To PLL (POLL Alternative)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–11
Setting the System Clocks
1. Set System Clock
to oscillator
(default)
PLL input
source?
XTAL
2. Select XTAL
as PLL source
3. Turn On XTAL
osc
4. Program PLL
w/irq
5. Setup Timer
6. Go to Sleep
GPT ISR: The PLL
has not locked
7. PLL ISR.
The PLL has locked.
Clear interrupt
XTAL
PLL input
source?
8. XTAL Locked?
(sanity check)
osc
Error, PLL is locked
but XTAL is not
(unlikely)
Yes
9. Change System
Clock to PLL
Figure 5-5: Change System Clock To PLL (IRQ Method)
Set System Clock to XTAL
The following figures show the sequence of events to change system clock from internal oscillator based to XTAL
based source.
5–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Setting the System Clocks
1. Set System Clock
to oscillator
(default)
2. Turn On XTAL
3. Setup Timer
4. Poll XTAL lock bit
No
5. XTAL Locked?
Timer ISR: Error, the
XTAL has not locked
6. Disable Timer
7. Change System
Clock to XTAL source
Figure 5-6: Change System Clock To XTAL (Poll Method)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–13
Setting the System Clocks
1. Set System Clock
to oscillator
(default)
2. Turn On XTAL with
IRQ
3. Setup Timer
4. Go to Sleep
GPT ISR: The XTAL
has not locked
XTAL ISR. The XTAL
has locked
5. Change System
Clock to XTAL source
Figure 5-7: Change System Clock to XTAL (IRQ Method)
Changing System Clock Source
The figure shows the sequence to change the system clock source from oscillator to either XTAL input or PLL based
input source.
5–14
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CLKG_OSC Register Descriptions
1. Set System Clock
to oscillator
(default)
14. Turn On XTAL
XTAL
15. Setup Timer
16. Poll XTAL lock bit
Switch HF Clock?
PLL
PLL input
source?
XTAL
2. Turn On XTAL
3. Setup Timer
GPIO
13. Enable GPIO
clock input
4. Poll XTAL lock bit
No
No
OSC
5. XTAL Locked?
17. XTAL Locked?
Timer ISR: Error, the
XTAL has not locked
Timer ISR: Error, the
XTAL has not locked
6. Disable Timer
18. Disable Timer
7. Select XTAL as
PLL source
8. Program PLL
9. Setup Timer
10. Poll PLL lock bit
No
Timer ISR: Error, the
PLL has not locked
11. PLL Locked?
12. Disable Timer
19. Change System
Clock Source
Figure 5-8: Changing System Clock
ADuCM302x CLKG_OSC Register Descriptions
Clocking registers (CLKG_OSC) contains the following registers.
Table 5-6:
ADuCM302x CLKG_OSC Register List
Name
Description
CLKG_OSC_CTL
Oscillator Control
CLKG_OSC_KEY
Key Protection for OSCCTRL
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–15
ADuCM302x CLKG_OSC Register Descriptions
Oscillator Control
The CLKG_OSC_CTL register is key-protected. To unlock this protection 0xCB14 should be written to
CLKG_OSC_KEY before writing to CLKG_OSC_CTL A write to any other register on the APB bus before writing to
CLKG_OSC_CTL will return the protection to the lock state.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
HFXTALOK (R)
Status of HFXTAL oscillator
LFCLKMUX (R/W)
32 KHz clock select mux
LFXTALOK (R)
Status of LFXTAL oscillator
HFOSCEN (R/W)
High frequency internal oscillator enable
HFOSCOK (R)
Status of HFOSC oscillator
LFXTALEN (R/W)
Low frequency crystal oscillator enable
LFOSCOK (R)
Status of LFOSC oscillator
HFXTALEN (R/W)
High frequency crystal oscillator enable
LFXTAL_MON_EN (R/W)
LFXTAL clock monitor and Clock FAIL
interrupt enable
LFXTAL_BYPASS (R/W)
Low frequency crystal oscillator Bypass
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LFXTAL_MON_FAIL_STAT (R/W)
LF XTAL (crystal clock) Not Stable
Figure 5-9: CLKG_OSC_CTL Register Diagram
Table 5-7:
CLKG_OSC_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31 LFXTAL_MON_FAIL_ST
(R/W) AT
11 HFXTALOK
(R/NW)
LF XTAL (crystal clock) Not Stable.
This is a sticky bit. If set, it generates interrupt on the RTC1 IRQ line. It can generate
interrupt during Hibernate or Active modes. If the flag is set in Hibernate mode, the
part will wakeup from Hibernate mode by asserting interrupt on RTC1 IRQ line. The
interrupt and this bit can be cleared by writing 1 to this bit 1 - LFXTAL (low frequency XTAL clock) is not running. The Crystal connection in the board to the chip has
possible snapped. Or the External clock driver has stopped giving out clock. 0 LFXTAL is running fine.
Status of HFXTAL oscillator.
This bit indicates when the crystal is stable after it is enabled. This bit is not a monitor
and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use
5–16
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CLKG_OSC Register Descriptions
Table 5-7:
CLKG_OSC_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 LFXTALOK
(R/NW)
Status of LFXTAL oscillator.
This bit indicates when the crystal is stable after it is enabled. This bit is not a monitor
and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use
9 HFOSCOK
(R/NW)
Status of HFOSC oscillator.
This bit indicates when the oscillator is stable after it is enabled. This bit is not a monitor and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use
8 LFOSCOK
(R/NW)
Status of LFOSC oscillator.
This bit indicates when the oscillator is stable after it is enabled. This bit is not a monitor and will not indicate a subsequent loss of stability.
0 Oscillator is not yet stable or is disabled
1 Oscillator is enabled and is stable and ready for use
5 LFXTAL_MON_EN
(R/W)
LFXTAL clock monitor and Clock FAIL interrupt enable.
If set the LFXTAL clock will be monitored using the on chip 32khz low frequency
OSCILLATOR. This clock will be monitored in both Hibernate and Active/Flexi
modes. If the LFXTAL clock stops toggling for 2ms the LFXTAL_MON_FAIL flag is
set and interrupt is generated on the RTC1 IRQ line. If cleared The Monitor circuit is
reset and the LFXTAL clock FAIL interrupt is not generated.
0 LFXTAL Clock Monitor and clock FAIL interrupt disabled
1 LFXTAL Clock Monitor and clock FAIL interrupt enabled
4 LFXTAL_BYPASS
(R/W)
Low frequency crystal oscillator Bypass.
This bit is used to bypass the low frequency crystal oscillator, and if a clock is supplied
externally on one of the LF XTAL pin. The oscillator must be disabled before setting
this bit. Disabling of LFXTAL could take a while, hence ensure that the oscillator is
disabled by reading the LFXTALEN bit and it reads 0.
0 The LFXTAL oscillator is disabled and placed in a low
power state
1 The LFXTAL oscillator is enabled
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–17
ADuCM302x CLKG_OSC Register Descriptions
Table 5-7:
CLKG_OSC_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 HFXTALEN
(R/W)
High frequency crystal oscillator enable.
This bit is used to enable/disable the oscillator. The oscillator must be stable before
use.
0 The HFXTAL oscillator is disabled and placed in a low
power state
1 The HFXTAL oscillator is enabled
2 LFXTALEN
(R/W)
Low frequency crystal oscillator enable.
This bit is used to enable/disable the oscillator. The oscillator must be stable before
use.
0 The LFXTAL oscillator is disabled and placed in a low
power state
1 The LFXTAL oscillator is enabled
1 HFOSCEN
(R/W)
High frequency internal oscillator enable.
This bit is used to enable/disable the oscillator. The oscillator must be stable before
use. This bit must be set before the SYSRESETREQ system reset can be initiated.
0 The HFOSC oscillator is disabled and placed in a low
power state
1 The HFOSC oscillator is enabled
0 LFCLKMUX
(R/W)
32 KHz clock select mux.
This clock connects to beeper, RTC Note : This bit is not RESET to default value
when SOFT RESET is asserted. While all other bits will be reset. This bit will be reset
during other reset such as Power-Up, external reset. User needs to specifically take care
to program appropriate value when the software executes after a SOFT-RESET. Soft
reset is generated by setting the bit in CORTEXM3 register AIRCR.SYSRESETREQ.
0 Internal 32 KHz oscillator is selected.
1 External 32 KHz crystal is selected.
5–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CLKG_OSC Register Descriptions
Key Protection for OSCCTRL
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (W)
Oscillator key
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-10: CLKG_OSC_KEY Register Diagram
Table 5-8:
CLKG_OSC_KEY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
Oscillator key.
The CLKG_OSC_CTL register is key-protected with value 0xCB14. The
CLKG_OSC_CTL register should be written after proper key value entered. A write to
any other register on the APB bus before writing to CLKG_OSC_CTL will return the
protection to the lock state.
ADuCM302x CLKG_CLK Register Descriptions
Clocking registers (CLKG_CLK) contains the following registers.
Table 5-9:
ADuCM302x CLKG_CLK Register List
Name
Description
CLKG_CLK_CTL0
Misc clock settings
CLKG_CLK_CTL1
Clock dividers
CLKG_CLK_CTL3
System PLL
CLKG_CLK_CTL5
User clock gating control
CLKG_CLK_STAT0
Clocking status
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–19
ADuCM302x CLKG_CLK Register Descriptions
Misc clock settings
Clock Control 0 is used to configure clock sources used by various systems such as the core and memories and peripherals. All unused bits are read only returning a value of 0. Writing unused bits has no effect.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
HFXTALIE (R/W)
High frequency crystal interrupt enable
CLKMUX (R/W)
Clock mux select
LFXTALIE (R/W)
Low frequency crystal interrupt enable
RCLKMUX (R/W)
Flash reference clock and HPBUCK
clock source mux
SPLLIPSEL (R/W)
SPLL source select mux
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-11: CLKG_CLK_CTL0 Register Diagram
Table 5-10:
CLKG_CLK_CTL0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 HFXTALIE
(R/W)
High frequency crystal interrupt enable.
Controls if the core should be interrupted on a CLKG_CLK_STAT0.HFXTALOK or
CLKG_CLK_STAT0.HFXTALNOK status or if no interrupt should be generated. This
bit should never be cleared while a core interrupt is pending.
0 An interrupt to the core is not generated on a HFXTALOK or HFXTALNOK.
1 An interrupt to the core is generated on a HFXTALOK
or HFXTALNOK.
14 LFXTALIE
(R/W)
Low frequency crystal interrupt enable.
Controls if the core should be interrupted on a CLKG_CLK_STAT0.LFXTALOK or
CLKG_CLK_STAT0.LFXTALNOK status or if no interrupt should be generated. This
bit should never be cleared while a core interrupt is pending.
0 An interrupt to the core is not generated on a LFXTALOK or LFXTALNOK.
1 An interrupt to the core is generated on a LFXTALOK
or LFXTALNOK.
5–20
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CLKG_CLK Register Descriptions
Table 5-10:
CLKG_CLK_CTL0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 SPLLIPSEL
(R/W)
SPLL source select mux.
CLKG_CLK_CTL0.SPLLIPSEL selects which source clock is feed to the SPLL. The se-
lection should be made before the SPLL is enabled. Selection should not be changed
after the SPLL is enabled.
0 Internal HF oscillator is selected
1 External HF XTAL oscillator is selected
9:8 RCLKMUX
(R/W)
Flash reference clock and HPBUCK clock source mux.
These bits are to be programmed, when both external crystal and HF oscillator are stable and running. The Clock muxed output supplies Flash reference clock and HP buck
clock (200khz) Note that if option '11' is programmed, the clock-out is 16Mhz instead of 26Mhz, the dividers of following clocks get auto-configured. RCLK - divider
is bypassed. RCLK = 16Mhz. HPBUCK clock - divider is auto-configured to generate
200khz clock Note : If external xtal clock is 16MHz instead of 26MHz. Then HP
Buck non-overlapping phases increases. This is not recommended if HP buck is enabled.
0 sourcing from HFOSCCLK - 26MHz Set
CLKG_CLK_CTL0.RCLKMUX = 00 if following is true 1.
HFOSC (26Mhz) to be the source for HPBUCK Divider and flash-reference clock generators
1 reserved
2 sourcing from external HF XTAL (26MHz) Set
CLKG_CLK_CTL0.RCLKMUX = 10 if following is true 1.
HFXTAL to be the source for HPBUCK Divider and
flash-reference clock generators 2. Frequency of
HFXTAL connected to chip = 26Mhz
3 sourcing from external HF XTAL (16MHz) Set
CLKG_CLK_CTL0.RCLKMUX = 11 if following is true 1.
HFXTAL to be the source for HPBUCK Divider and
flash-reference clock generators 2. Frequency of
HFXTAL connected to chip = 16Mhz
1:0 CLKMUX
(R/W)
Clock mux select.
Determines which single shared clock source is used by the PCLK, and HCLK dividers. Ensure that an enabled active stable clock source is selected
(AON_CORE_MUX_SEL).
0 High frequency internal oscillator is selected
1 High frequency external crystal oscillator is selected
2 System PLL is selected
3 External GPIO port is selected
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–21
ADuCM302x CLKG_CLK Register Descriptions
Clock dividers
Clock Control 1 is used to set the divide rates for the HCLK, and PCLK and ACLK dividers. This register can be
written to at any time. All unused bits are read only, returning a value of 0. Writing to unused bits has no effect.
15 14 13 12 11 10 9
0
0
0
0
0
1
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
0
PCLKDIVCNT (R/W)
PCLK divide count
HCLKDIVCNT (R/W)
HCLK divide count
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
ACLKDIVCNT (R/W)
ACLK Divide Count.
Figure 5-12: CLKG_CLK_CTL1 Register Diagram
Table 5-11:
CLKG_CLK_CTL1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:16 ACLKDIVCNT
(R/W)
ACLK Divide Count..
Determines the ACLK rate based on the following equation: ACLK = ROOT_CLK/
CLKG_CLK_CTL1.ACLKDIVCNT. For example, if ROOT_CLK is 26 MHz and
CLKG_CLK_CTL1.ACLKDIVCNT = 0x1, ACLK operates at 26 MHz. The value of
CLKG_CLK_CTL1.ACLKDIVCNT takes effect after a write access to this register and
typically takes one ACLK cycle. This register can be read at any time and can be written to at any time. The reset divider count is 0x4. Value range is from 1 to 32. Values
larger than 32 are saturated to 32. Values 0 and 1 have the same results as divide by 1.
Default value of this register is configured such that ACLK = 6.5MHz
13:8 PCLKDIVCNT
(R/W)
5:0 HCLKDIVCNT
(R/W)
5–22
PCLK divide count.
Determines the PCLK rate based on the following equation: PCLK = ROOT_CLK/
CLKG_CLK_CTL1.PCLKDIVCNT. For example, if ROOT_CLK is 26 MHz and
CLKG_CLK_CTL1.PCLKDIVCNT = 0x2, PCLK operates at 13 MHz. The value of
CLKG_CLK_CTL1.PCLKDIVCNT takes effect after a write access to this register and
typically takes 2-to-4 PCLK cycles. This register can be read at any time and can be
written to at any time. The reset divider count is 0x4. Value range is from 1 to 32.
Values larger than 32 are saturated to 32. Values 0 and 1 have the same results as divide
by 1. The default value of this register is configured such that PCLK freq = 6.5MHz
HCLK divide count.
Determines the HCLK rate based on the following equation: HCLK = ROOT_CLK/
CLKG_CLK_CTL1.HCLKDIVCNT. For example, if ROOT_CLK is 26 MHz and
CLKG_CLK_CTL1.HCLKDIVCNT = 0x1, HCLK operates at 26 MHz. The value of
CLKG_CLK_CTL1.HCLKDIVCNT takes effect after a write access to this register and
typically takes 2-to-4 PCLK cycles (not HCLK cycles). This register can be read at any
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CLKG_CLK Register Descriptions
Table 5-11:
CLKG_CLK_CTL1 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
time and can be written to at any time. The reset divider count is 0x4. Value range is
from 1 to 32. Values larger than 32 are saturated to 32. Values 0 and 1 have the same
results as divide by 1. Default value of this register is configured such that HCLK =
6.5MHz
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–23
ADuCM302x CLKG_CLK Register Descriptions
System PLL
Clock Control 3 is used to control the system PLL. This register should be written to only when the PLL is not
selected as the clock source (ROOT_CLK). All unused bits are read only, returning a value of 0. Writing to unused
bits has no effect.
15 14 13 12 11 10 9
0
1
1
0
1
0
0
8
7
6
5
4
3
2
1
0
1
0
0
0
1
1
0
1
0
SPLLMSEL (R/W)
System PLL M Divider
SPLLNSEL (R/W)
System PLL N multiplier
SPLLIE (R/W)
System PLL interrupt enable
SPLLDIV2 (R/W)
System PLL division by 2
SPLLEN (R/W)
System PLL enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SPLLMUL2 (R/W)
system PLL multiply by 2
Figure 5-13: CLKG_CLK_CTL3 Register Diagram
Table 5-12:
CLKG_CLK_CTL3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
16 SPLLMUL2
(R/W)
system PLL multiply by 2.
This bit is used to configure if the VCO clock frequency should be multiplied by 2 or
1.
0 PLL out frequency = SPLLNSEL * 1 / ((SPLLDIV2+1)
* SPLLMSEL)
1 PLL out frequency = SPLLNSEL * 2 / ((SPLLDIV2+1)
* SPLLMSEL)
14:11 SPLLMSEL
(R/W)
5–24
System PLL M Divider.
System PLL M Divider. Sets the M value used to obtain the multiplication factor N/M
of the PLL. if CLKG_CLK_CTL3.SPLLMSEL <= 2, then Divider M value = 2 e.g.
0000: M set to 2 (Div by 2) 0001: M set to 2 (Div by 2) 0010: M set to 2 (Div by 2)
0011: M set to 3 (Div by 3) 0100: M set to 4 (Div by 4) 1111: M set to 15 (Div by
15)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CLKG_CLK Register Descriptions
Table 5-12:
CLKG_CLK_CTL3 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 SPLLIE
(R/W)
System PLL interrupt enable.
Controls if the core should be interrupted on a PLL lock/PLL unlock or no interrupt
generated. This bit should never be cleared while a core interrupt is pending.
0 An interrupt to the core will not be generated on a PLL
lock or PLL unlock
1 An interrupt to the core will be generated on a PLL lock
or PLL unlock
9 SPLLEN
(R/W)
System PLL enable.
Controls if the PLL should be enabled or placed in its low power state. This bit should
only be set while the System PLL is not selected as the system clock source
(CLKG_CLK_CTL0.CLKMUX).
0 The PLL is disabled and is in its power down state
1 The PLL is enabled. Initially the PLL will not run at the
selected frequency. After a stabilization period the PLL
will lock onto the selected frequency at which time it
can be selected as a system clock source (CLKMUX
bits)
8 SPLLDIV2
(R/W)
System PLL division by 2.
Controls if an optional divide by two is placed on the PLL output. This will guarantee
a balanced output duty cycle output at the cost of doubling the PLL frequency (power). This bit should not be modified after CLKG_CLK_CTL3.SPLLEN is set. This bit
can be written at the same time CLKG_CLK_CTL3.SPLLEN is set. This bit is set or
reset on need basis and based on below constraints. The VCO output range is 32MHz
to 60MHz The SPLL output range is 16MHz to 60MHz By default it is SET
0 The System PLL is not divided. Its output frequency
equals that selected by the N/M ratio
1 The System PLL is divided by two. Its output frequency
equals that selected by the N/M ratio with an additional /2 divide
4:0 SPLLNSEL
(R/W)
System PLL N multiplier.
Sets the N value used to obtain the multiplication factor N/M of the PLL. The default
value is 0b011010 (Mult by 26). Minimum valid value is 8 and writing any value less
than 8 will force it to be 8. Maximum valid value is 31. Do not program the SPLL to
an output clock lower than 16 MHz or higher than 60 MHz.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–25
ADuCM302x CLKG_CLK Register Descriptions
User clock gating control
Clock Control 5 is used to control the gates of the peripheral UCLKs.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
1
1
1
1
1
PERCLKOFF (R/W)
This bit is used to disable all clocks
connected to all peripherals
GPTCLK0OFF (R/W)
GP timer 0 user control
GPTCLK1OFF (R/W)
GP timer 1 user control
GPIOCLKOFF (R/W)
GPIO clock control
GPTCLK2OFF (R/W)
GP timer 2 user control
UCLKI2COFF (R/W)
I2C clock user control
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-14: CLKG_CLK_CTL5 Register Diagram
Table 5-13:
CLKG_CLK_CTL5 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5 PERCLKOFF
(R/W)
4 GPIOCLKOFF
(R/W)
This bit is used to disable all clocks connected to all peripherals.
0 Clocks to all peripherals are Active 1-- Clocks to all peripherals are gated off. After
setting this bit, Any read/write to any of the above module register will automatically
reset the CLKG_CLK_CTL5.PERCLKOFF to 0, and that read/write transaction will be
honored. After setting CLKG_CLK_CTL5.PERCLKOFF = 1, if user read's
CLKG_CLK_CTL5 register, CLKG_CLK_CTL5.PERCLKOFF will be automatically
cleared. And CLKG_CLK_CTL5.PERCLKOFF will read as 0. Recommended usage: 1.
User has to ensure that DMA transactions are done and no more transaction is expected from DMA 2. User has to ensure that CLKG_CLK_CTL5.PERCLKOFF bit write is
last write. And no write/read to any of above module registers is done after setting this
bit. Because otherwise CLKG_CLK_CTL5.PERCLKOFF bit will be cleared
GPIO clock control.
This bit disables the ACLK. It controls the gate on the ACLK out from ACLK Divider. This ACLK control is in Active and Flexi modes. In Hibernate and Shutdown
modes, the ACLK is always off, and this bit has no effect. Please Note that this bit
WILL NOT be automatically cleared. User has to explicitly enable or disable this bit
to control ACLK out Note : Before programming CLKG_CLK_CTL1.ACLKDIVCNT
register, this bit (CLKG_CLK_CTL5.GPIOCLKOFF) needs to be cleared to 0. Otherwise
the CLKG_CLK_CTL1.ACLKDIVCNT will not be taken into effect.
0 GPIO Clock is enabled
1 GPIO Clock is disabled
5–26
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CLKG_CLK Register Descriptions
Table 5-13:
CLKG_CLK_CTL5 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 UCLKI2COFF
(R/W)
I2C clock user control.
This bit disables the I2C UCLK. It controls the gate on the I2C UCLK in Active and
Flexi modes. In Hibernate and Shutdown modes the I2C UCLK is always off, and this
bit has no effect. Note will automatically clear this bit if I2C is accessed via the APB
bus.
0 I2C Clock is enabled
1 I2C Clock is disabled
2 GPTCLK2OFF
(R/W)
GP timer 2 user control.
This bit disables the gptclk2 (muxed version). It controls the gate on the GPTimer2
clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the GPT
clock is always off, and this bit has no effect. Note will automatically clear this bit if
GPT2 is accessed via the APB bus.
0 TMR2 clock is enabled
1 TMR2 clock is disabled
1 GPTCLK1OFF
(R/W)
GP timer 1 user control.
This bit disables the gptclk1 (muxed version). It controls the gate on the GPTimer1
clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the GPT
clock is always off, and this bit has no effect. Note will automatically clear this bit if
GPT1 is accessed via the APB bus.
0 TMR1 clock is enabled
1 TMR1 clock is disabled
0 GPTCLK0OFF
(R/W)
GP timer 0 user control.
This bit disables the gptclk0 (muxed version). It controls the gate on the GPTimer0
clock in Active and Flexi power modes. In Hibernate and Shutdown modes, the GPT
clock is always off, and this bit has no effect. Note will automatically clear this bit if
GPT0 is accessed via the APB bus.
0 TMR0 clock is enabled
1 TMR0 clock is disabled
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–27
ADuCM302x CLKG_CLK Register Descriptions
Clocking status
Clock Status is used to monitor PLL and Oscillator status. With interrupts enabled the user is free to continue to
run initialization code or idle the core while clock components stabilize.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
HFXTALNOK (R/W1C)
HF crystal not stable
SPLL (R)
System PLL status
HFXTALOK (R/W1C)
HF crystal stable
SPLLLK (R/W1C)
System PLL lock
HFXTAL (R)
HF crystal status
SPLLUNLK (R/W1C)
System PLL unlock
LFXTALNOK (R/W1C)
LF crystal not stable
LFXTAL (R)
LF crystal status
LFXTALOK (R/W1C)
LF crystal stable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 5-15: CLKG_CLK_STAT0 Register Diagram
Table 5-14:
CLKG_CLK_STAT0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 HFXTALNOK
(R/W1C)
HF crystal not stable.
This bit indicates the XTAL was successfully disabled. This bit is not associated with
continuous monitoring of the XTAL and will not be set in the event the XTAL becomes unstable. This bit is sticky. Write a 1 to this location to clear it. If enabled, an
interrupt can be associated with this bit.
0 HF crystal stable signal has not been de-asserted.
1 HF crystal stable signal has been de-asserted.
13 HFXTALOK
(R/W1C)
HF crystal stable.
This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1
to this location to clear it.
0 HF crystal stable signal has not been asserted.
1 HF crystal stable signal has been asserted.
5–28
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CLKG_CLK Register Descriptions
Table 5-14:
CLKG_CLK_STAT0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12 HFXTAL
(R/NW)
HF crystal status.
This bit assists in determining when the XTAL is initially stable and ready to use. This
bit does not perform a continuous monitoring function and will not clear in the event
an XTAL becomes unstable.
0 HF crystal is not stable or not enabled.
1 HF crystal is stable.
10 LFXTALNOK
(R/W1C)
LF crystal not stable.
This bit indicates the XTAL was successfully disabled. This bit is not associated with
continuous monitoring of the XTAL and will not be set in the event the XTAL becomes unstable. This bit is sticky. Write a 1 to this location to clear it. If enabled, an
interrupt can be associated with this bit.
0 LF crystal stable signal has not been de-asserted.
1 LF crystal stable signal has been de-asserted.
9 LFXTALOK
(R/W1C)
LF crystal stable.
This bit is sticky. It is used to interrupt the core when interrupts are enabled. Write a 1
to this location to clear it.
0 LF crystal stable signal has not been asserted.
1 LF crystal stable signal has been asserted.
8 LFXTAL
(R/NW)
LF crystal status.
This bit assists in determining when the XTAL is initially stable and ready to use. This
bit does not perform a continuous monitoring function and will not clear in the event
an XTAL becomes unstable.
0 LF crystal is not stable or not enabled.
1 LF crystal is stable
2 SPLLUNLK
(R/W1C)
System PLL unlock.
This bit is sticky. CLKG_CLK_STAT0.SPLLUNLK is set when the PLL looses its lock.
CLKG_CLK_STAT0.SPLLUNLK is used as the interrupt source to signal the core that a
lock was lost. Writing a one to this bit clears it. CLKG_CLK_STAT0.SPLLUNLK will
not set again unless the System PLL gains a lock and subsequently looses again.
0 No loss of PLL lock was detected
1 A PLL loss of lock was detected
ADuCM302x Mixed-Signal Control Processor Hardware Reference
5–29
ADuCM302x CLKG_CLK Register Descriptions
Table 5-14:
CLKG_CLK_STAT0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 SPLLLK
(R/W1C)
System PLL lock.
This bit is sticky. CLKG_CLK_STAT0.SPLLLK is set when the PLL locks.
CLKG_CLK_STAT0.SPLLLK is used as the interrupt source to signal the core that a
lock was detected. Writing a one to this bit clears it. CLKG_CLK_STAT0.SPLLLK will
not set again unless the System PLL looses lock and subsequently locks again.
0 No PLL lock event was detected
1 A PLL lock event was detected
0 SPLL
(R/NW)
System PLL status.
Indicates the current status of the PLL. Initially the System PLL will be unlocked. After a stabilization period the PLL will lock and be ready for use as the system clock
source. This is a read only bit. A write has no effect.
0 The PLL is not locked or not properly configured. The
PLL is not ready for use as the system clock source
1 The PLL is locked and is ready for use as the system
clock source
5–30
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Direct Memory Access (DMA)
6 Direct Memory Access (DMA)
The direct memory access (DMA) controller is used to perform data transfer tasks and offload these from the
ADuCM302x processor. DMA is used to provide high speed data transfer between peripherals and memory. Data
can be quickly moved by the DMA without any CPU actions. This keeps the CPU resources free for other operations.
DMA Features
The DMA supports the following features:
• 24 independent DMA channels
• Two programmable priority levels for each DMA channel
• Each priority level arbitrates using a fixed priority that is determined by the DMA channel number
• Each DMA channel can access a primary, and/or alternate channel control data structure
• Supports the following multiple transfer types:
• Memory-to-memory
• Memory-to-peripheral
• Peripheral-to-memory
• Supports the following multiple DMA cycle types:
• Basic
• Auto request
• Ping pong
• Scatter gather
• Supports multiple DMA transfer data widths (8-bit, 16-bit, and 32-bit)
• Each DMA channel can have independent source and destination increment/decrement controls
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–1
DMA Functional Description
DMA Functional Description
The DMA has 24 channels in total, each dedicated to managing memory access requests from peripherals. The
DMA Channels table shows the assignments.
Each of the DMA channels is connected to dedicated hardware DMA requests, and the software trigger is also supported on each channel. This configuration is done by software. Each DMA channel has a programmable priority
level default or high. Each priority level arbitrates using a fixed priority that is determined by the DMA channel
number.
The DMA controller supports multiple DMA transfer data widths. However, the source and destination transfer
sizes must be the same. Also, always align the source and destination addresses to the data transfer size. It has a single
output to indicate when an error condition occurs: DMA error interrupt. An error condition can occur when a bus
error happens while doing a DMA transfer, or when the DMA controller reads an invalid cycle control. The DMA
controller supports memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers and has access
to flash or SRAM0 or SRAM1 as source and destination.
Table 6-1:
DMA Channels
Channel Node
Peripheral
0
SPI2 TX
1
SPI2 RX
2
SPORT0A
3
SPORT0B
4
SPI0 Tx
5
SPI0 Rx
6
SPI1 Tx
7
SPI1 Rx
8
UART0 Tx
9
UART0 Rx
10
I2C0 Slave Tx
11
I2C0 Slave Rx
12
I2C0 Master
13
Crypto0 IN
14
Crypto0 OUT
15
Flash
16 to 23
Software DMA
ADuCM302x DMA Register List
DMA
6–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Functional Description
Table 6-2:
ADuCM302x DMA Register List
Name
Description
DMA_ADBPTR
DMA channel alternate control data base pointer
DMA_ALT_CLR
DMA channel primary-alternate clear
DMA_ALT_SET
DMA channel primary-alternate set
DMA_BS_CLR
DMA channel bytes swap enable clear
DMA_BS_SET
DMA channel bytes swap enable set
DMA_CFG
DMA Configuration
DMA_DSTADDR_CLR
DMA channel destination address decrement enable clear
DMA_DSTADDR_SET
DMA channel destination address decrement enable set
DMA_EN_CLR
DMA channel enable clear
DMA_EN_SET
DMA channel enable set
DMA_ERRCHNL_CLR
DMA Per Channel Error Clear
DMA_ERR_CLR
DMA bus error clear
DMA_INVALIDDESC_CLR
DMA Per Channel Invalid Descriptor Clear
DMA_PDBPTR
DMA channel primary control data base pointer
DMA_PRI_CLR
DMA channel priority clear
DMA_PRI_SET
DMA channel priority set
DMA_REVID
DMA Controller Revision ID
DMA_RMSK_CLR
DMA channel request mask clear
DMA_RMSK_SET
DMA channel request mask set
DMA_SRCADDR_CLR
DMA channel source address decrement enable clear
DMA_SRCADDR_SET
DMA channel source address decrement enable set
DMA_STAT
DMA Status
DMA_SWREQ
DMA channel software request
DMA Architectural Concepts
The DMA channel provides a means to transfer data between memory spaces or between memory and a peripheral
using the system interface. The DMA channel provides an efficient means of distributing data throughout the system, freeing up the processor core for other operations. Each peripheral that supports DMA transfers has its own
dedicated DMA channel or channels with its own register set that configures and controls the operating modes of
the DMA transfers.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–3
DMA Operating Modes
DMA Operating Modes
The DMA controller has two buses where one is connected to the system bus shared with the Cortex-M3 core and
the other bus is connected to 16-bit peripherals. The DMA request may stop the CPU access to the system bus for
some bus cycles, such as when the CPU and DMA target the same destination (memory or peripheral).
The DMA controller fetches channel control data structures located in the system memory to perform data transfers. The DMA-capable peripherals, when enabled to use DMA, can request the DMA controller for a transfer. At
the end of the programmed number of DMA transfers for a channel, the DMA controller generates a single cycle
dma_done interrupt corresponding to that channel. This interrupt indicates the completion of the DMA transfer.
Separate interrupt enable bits are available in the NVIC for each of the DMA channels.
Channel Control Data Structure
Every channel has two control data structures associated with it: a primary data structure and an alternate data structure. For simple transfer modes, the DMA controller uses either the primary or alternate data structure by programming the DMA_ALT_CLR register. For more complex data transfer modes, such as ping-pong or scatter-gather, the
DMA controller uses both the primary and alternate data structures. Each control data structure (primary or alternate) occupies four 32-bit locations in the memory as shown in the table below.
Table 6-3:
Channel Control Data Structure
Offset
Name
Description
0x00
SRC_END_PTR
Source End Pointer
0x04
DST_END_PTR
Destination End Pointer
0x08
CHNL_CFG
Control Data Configuration
0x0C
RESERVED
Reserved
The figure shows the entire channel control data structure for the eight DMA channel case. It uses 512 bytes of
system memory.
6–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Operating Modes
0x070
0x0FC
Control
0x078
Control
0x0F8
Destination End Pointer
0x074
Destination End Pointer
0x0F4
Source End Pointer
0x070
Source End Pointer
0x0F0
0x060
0x0EC
Control
0x068
Control
0x0E8
Destination End Pointer
0x064
0x060
Destination End Pointer
0x0E4
Source End Pointer
0x0E0
Source End Pointer
0x0DC
0x050
Control
0x058
Control
0x0D8
Destination End Pointer
0x054
0x050
Destination End Pointer
0x0D4
Source End Pointer
0x0D0
Source End Pointer
0x040
0x0CC
Control
0x048
Control
0x0C8
Destination End Pointer
0x044
Destination End Pointer
0x0C4
Source End Pointer
0x040
Source End Pointer
0x0C0
0x030
0x0BC
Control
0x038
Control
0x0B8
Destination End Pointer
0x034
Destination End Pointer
0x0B4
0x030
Source End Pointer
0x0B0
Source End Pointer
0x0AC
0x020
Control
0x028
Control
0x0A8
Destination End Pointer
0x024
Destination End Pointer
0x0A4
Source End Pointer
0x020
0x010
Source End Pointer
0x0A0
Control
0x018
Control
0x098
Destination End Pointer
0x014
0x010
Destination End Pointer
0x094
Source End Pointer
0x090
Source End Pointer
0x090
0x00C
0x08C
Control
0x008
Control
0x088
Destination End Pointer
0x004
Destination End Pointer
0x084
Source End Pointer
0x000
Source End Pointer
0x080
Figure 6-1: Memory Map for Primary DMA Structure
Before the controller can perform a DMA transfer, the data structure related to the DMA channel needs to be written to the designated location in system memory. The Source End Pointer memory location contains the end address of the source data. The Destination End Pointer memory location contains the end address of the destination
data. The Control memory location contains the channel configuration control data. This determines the source
and destination data size, number of transfers, and the number of data transfers for each arbitration.
When the DMA controller receives a request for a channel, it reads the corresponding data structure from the system memory into its internal cache. Any update to the descriptor in the system memory until dma_done interrupt
will not guarantee expected behavior, and hence, it is strongly recommended that the user not update the descriptor
before receiving dma_done.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–5
DMA Operating Modes
Source Data End Pointer
The SRC_END_PTR memory location stores the address of the last location from where data will be read as part of
DMA transfer. This memory location must be programmed with the end address of the source data before the controller can perform a DMA transfer. The controller reads this memory location when it starts the first DMA data
transfer. DMA controller does not write to this memory location.
Table 6-4:
Source Data End Pointer
Bit
Name
Description
[31:0]
SRC_END_PTR
The end address of the source data.
Destination Data End Pointer
The DST_END_PTR memory location stores the address of the last location where data will be written to as part
of DMA transfer. This memory location must be programmed with the end address of the destination data before
the controller can perform a DMA transfer. The controller reads this memory location when it starts the first DMA
data transfer. DMA controller does not write to this memory location.
Table 6-5:
Destination Data End Pointer
Bit
Name
Description
[31:0]
DST_END_PTR
The end address of the destination data.
Control Data Configuration
For each DMA transfer, the control data configuration (CHNL_CFG) memory location provides the control information for the DMA transfer to the controller.
Table 6-6:
Destination Data End Pointer
Bit
Name
Description
31 to 30
DST_INC
Destination address increment. The address increment depends on the source data
width as follows:
SRC_SIZE: byte
00: byte
01: halfword
10: word
11: no increment. Address remains set to the value that the DST_END_PTR
memory location contains.
SRC_SIZE: halfword
00: reserved
01: halfword
6–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Operating Modes
Table 6-6:
Bit
Destination Data End Pointer (Continued)
Name
Description
10: word
11: no increment. Address remains set to the value that the DST_END_PTR
memory location contains.
SRC_SIZE: word
00: reserved
01: reserved
10: word
11: no increment. Address remains set to the value that the DST_END_PTR
memory location contains.
29 to 28
RESERVED
Undefined. Write as zero
27 to 26
SRC_INC
Source address increment. The address increment depends on the source data width
as follows:
SRC_SIZE: byte
00: byte
01: halfword
10: word
11: no increment. Address remains set to the value that the SRC_END_PTR memory location contains.
SRC_SIZE: halfword
00: reserved
01: halfword
10: word
11: no increment. Address remains set to the value that the SRC_END_PTR memory location contains.
SRC_SIZE: word
00: reserved
01: reserved
10: word
11: no increment. Address remains set to the value that the SRC_END_PTR memory location contains.
25 to 24
SRC_SIZE
Size of the source data.
00: byte
01: halfword
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–7
DMA Operating Modes
Table 6-6:
Bit
Destination Data End Pointer (Continued)
Name
Description
10: word
11: reserved
23 to 18
RESERVED
Undefined. Write as zero.
17 to 14
R_Power
R_Power arbitrates after x DMA transfers.
0000: x = 1
0001: x = 2
0010: x = 4
0011: x = 8
0100: x = 16
0101: x = 32
0110: x = 64
0111: x = 128
1000: x = 256
1001: x = 512
1010 to 1111: x = 1024
NOTE: Software DMA transfers can use any value from 0000 to 1111. DMA
transfers that involve peripherals should always use 0000 with the exception of the
Crypto block, see Crypto chapter for further details. The operation of the DMA
will be indeterminate if a value other than 0000 is programmed for the DMA transfers involving peripherals.
13 to 4
N_minus_1
Total number of transfers in the current DMA cycle − 1. The 10-bit value indicates
the number of DMA transfers, minus one. The possible values are:
000: 1 DMA transfer
001: 2 DMA transfers
010: 3 DMA transfers
1111111111(0x3FF): 1024 DMA transfers.
NOTE: This value indicates the total number of transfers in the DMA cycle and
not the total number of bytes.
3
RESERVED
Undefined. Write as zero.
2 to 0
Cycle_ctrl
The operating mode of the DMA cycle.
000: Stop (Invalid).
001: Basic.
010: Auto-Request.
6–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Operating Modes
Table 6-6:
Destination Data End Pointer (Continued)
Bit
Name
Description
011: Ping-Pong.
100: Memory Scatter Gather Primary.
101: Memory Scatter Gather Alternate.
110: Peripheral Scatter Gather Primary.
111: Peripheral Scatter Gather Alternate.
During the DMA transfer process, if any error occurs during the data transfer, CHNL_CFG is written back to the
system memory, with N_minus_1 field updated to reflect the number of transfers yet to be completed. When a full
DMA cycle is complete, cycle_ctrl bits are made invalid to indicate the completion of transfer.
DMA Priority
The priority of a channel is determined by its number and priority level. Each channel can have two priority levels:
default or high. All channels at the high priority level have higher priority than all channels at the default priority
level. At the same priority level, a channel with a lower channel number has a higher priority than a channel with a
higher channel number. The DMA channel priority levels can be changed by writing into the appropriate bit in the
DMA_PRI_SET register.
Address Calculation
The DMA controller calculates the source read address based on the SRC_END_PTR, the source address increment
setting in CHNL_CFG, and the current value of the N_Minus_1.
Similarly, the destination write address is calculated based on the DST_END_PTR, destination address increment setting in CHNL_CFG, and the current value of the N_Minus_1.
Address Decrement
Address decrement can be enabled to source and destination addresses. Source address decrement can be enabled for
channels by setting appropriate bits in DMA_SRCADDR_SET. Similarly, destination address decrement can be enabled
for channels by setting the required bits in DMA_DSTADDR_SET. The values written into the source data end pointer
(SRC_END_PTR) and destination data end pointer (DST_END_PTR) are still used as the addresses for the last
transfer as part of the DMA cycle. However, the start address will be computed differently to the address increment
scheme for either source read or destination write.
If the source decrement bit is set in DMA_SRCADDR_SET a channel, its source address is computed as follows:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–9
DMA Operating Modes
If the destination decrement bit is set in DMA_DSTADDR_SET for a channel, its source address is computed as follows:
All combinations of source and destination decrement with their data movement direction are shown below.
Figure 6-4: Image Decrement
NOTE: In the previous equation, N_minus_1 is the current count of transfers to be done.
Byte swap and address decrement should not be used together for any channel. If used together, DMA data transfer
operation is unpredictable.
Endian Operation
The DMA controller does the transfer by default using a little-endian approach; however, this default behavior can
be changed by setting the corresponding channel bit in the DMA_BS_SET register. The endian operation is referred
to as byte swap.
6–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Operating Modes
Byte Swap Disabled
Byte swap is disabled by default. In this case, the data transfer is considered to be little-endian. Data arriving from a
peripheral is placed in sequence starting from the LSB of a 32-bit word.
For example, if 16 bytes of data arrive at the SPI as 0x01(start), 0x02, 0x03, 0x04 0x0F, 0x10, it is stored by the
DMA in memory as follows:
1. 04_03_02_01
2. 08_07_06_05
3. 0C_0B_0A_09
4. 10_0F_0E_0D
Byte Swap Enabled
Byte swap is enabled on any channel by setting the corresponding bit in the DMA_BS_SET register. By setting the
bit, big-endian data transfers will occur. Data arriving from the peripheral will be placed in sequence starting from
the MSB of a 32-bit word.
For example, if 16 bytes of data arrive at the SPI as 0x01(start), 0x02, 0x03, 0x04 0x0F, 0x10, it will be stored by the
DMA in memory as follows:
1. 01_02_03_04
2. 05_06_07_08
3. 09_0A_0B_0C
4. 0D_0E_0F_10
NOTE: Byte swap happens on 32-bit data boundaries. The transfer size must be a multiple of 4.
Byte swap and address decrement should not be used together for any channel. If used together, DMA data transfer
operation is unpredictable.
When using byte swap, care must be taken to ensure that the source data address is constant for the full data transfer. For example, SPI where the data source is always from the same location (a FIFO).
Byte swap functionality is independent of DMA transfer size and can be 8-bit, 16-bit, or 32-bit.
Channel Enable/Disable
Before issuing a DMA request, the DMA channel should be enabled, otherwise, the DMA request for the corresponding channel will be driven as DONE interrupt. Any DMA channel can be enabled by writing the corresponding bit in the DMA_EN_SET register. DMA controller disables the channel when the corresponding dma_done interrupt is generated. However, you can also disable any channel by writing to the corresponding bit in the
DMA_EN_CLR register.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–11
DMA Operating Modes
Whenever a channel is disabled, based on the current state of the DMA controller, it does the following:
• If the user disables the channel and there is no request pending for that channel, it will get disabled immediately.
• If the user disables the channel that is not getting serviced, but its request is posted, its pending request will be
cleared, and the channel will be disabled immediately.
• If the user disables a channel that has been selected after arbitration but yet to start transfers, the controller
completes the arbitration cycle and then disables channel.
• If the user disables the channel when it is getting serviced, controller completes the current arbitration cycle
and then disables the channel.
Master Enable
The DMA_CFG.MEN bit in the DMA_CFG register acts as a soft reset to the DMA controller. Any activity in the DMA
controller can be performed only when this bit is set to 1.
Clearing this bit to 0 clears all cached descriptors within the controller and resets the controller.
Power-down Considerations
Finish all the on-going DMA transfers before powering down the chip into hibernation. However, if the user decides
to hibernate as early as possible (current data transfers are ignored), the DMA controller should be disabled by clearing bit zero in DMA Configuration register (0x40010004 :: DMA_CFG) before going into hibernation.
NOTE: If hibernate mode is selected when a DMA transfer is in progress, the transfer will discontinue on resuming
from hibernation. The DMA returns to the disabled state.
After hibernation (or POR), the DMA should be enabled again by setting bit zero in the DMA Configuration register (0x40010004 :: DMA_CFG).
The following registers are retained in hibernate mode:
• DMA_PDBPTR
• DMA_ADBPTR
• DMA_RMSK_SET
• DMA_RMSK_CLR
• DMA_PRI_SET
• DMA_PRI_CLR
• DMA_BS_SET
• DMA_BS_CLR
• DMA_SRCADDR_SET
6–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Transfer Types
• DMA_SRCADDR_CLR
• DMA_DSTADDR_SET
• DMA_DSTADDR_CLR
DMA Transfer Types
Five types of DMA transfers are supported by DMA controller based on how it uses the primary and alternate control data structure and the number of requests required to complete a DMA transfer. The various types are selected
by programming the appropriate values into the cycle_ctrl bits in the CHNL_CFG location of the control data
structure. Based on cycle_ctrl, the following are the different DMA transfer types supported.
• Invalid
• Basic
• Auto-request
• Ping-pong
• Memory scatter-gather
• Peripheral scatter-gather
Transfer Type Usage table shows the various DMA transfer types that should be used by the peripherals and software
DMA. Use of software DMA transfer types for peripherals and vice versa is discouraged.
Table 6-7:
Transfer Type Usage
Channel Node
Peripheral
Basic
Auto Request
Ping-Pong
Ping-Pong*1
Peripheral scatter gather
Memory Scatter Gather
*1
Software Ping-Pong DMA transfer operation is different from Peripheral Ping-Pong DMA transfer operation (see the details in Ping
Pong section).
Invalid
This means that no DMA transfer is enabled for the channel. After the controller completes a DMA cycle, it sets the
cycle type to invalid to prevent it from repeating the same DMA cycle. Reading an invalid descriptor for any channel
generates a DMA error interrupt and the corresponding bit in DMA_INVALIDDESC_CLR is set.
Basic
In this mode, the controller can be configured to use either primary or alternate data structure by programming
DMA_ALT_CLR register for the corresponding channel. This mode is used for peripheral DMA transfers. While us-
ing this mode for peripherals, the r_power in CHNL_CFG should be set to 0, which means the peripheral needs to
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–13
DMA Transfer Types
present a request for every data transfer. Once the channel is enabled, when the controller receives a request, it performs the following operations:
1. The controller performs a transfer. If the number of transfers remaining is zero, the flow continues at Step 3.
2. The controller arbitrates:
a. If a higher priority channel is requesting service, the controller services that channel, or
b. If the peripheral or software signals a request to the controller, it continues at Step 1.
3. At the end of the transfer, the controller interrupts the processor using dma_done interrupt for the corresponding channel.
Auto-Request
When the controller operates in this mode, it is necessary for it to receive single request to enable it to complete the
entire DMA cycle. This allows a large data transfer to occur, without significantly increasing the latency for servicing
higher priority requests, or requiring multiple requests from the processor or peripheral. This mode is very useful for
a memory-to-memory copy application using software DMA requests.
In this mode, the controller can be configured to use either primary or alternate data structure by programming
DMA_ALT_CLR for the corresponding channel. After the channel is enabled, when the controller receives a request, it
performs the following operations.
1. The controller performs, min (2R _ Power, N) transfers for the channel. If the number of transfers remaining is
zero, the flow continues at Step 3.
2. A request for the channel is automatically generated. The controller arbitrates. If the channel has the highest
priority, the DMA cycle continues at Step 1.
3. At the end of the transfer, the controller interrupts the processor using the dma_done interrupt for that channel.
Ping-Pong
In this mode, the controller performs a DMA cycle using one of the data structures and then performs a DMA cycle
using the other data structure. The controller continues to switch from primary to alternate to primary and so on,
until it either reads a data structure that is basic/auto-request, or until the processor disables the channel.
This mode is useful for transferring data using different buffers in the memory. In a typical application, the processor is required to configure both primary and alternate data structure before starting the transfer. As the transfer progresses, the host can subsequently configure primary or alternate control data structures in the interrupt service routine when corresponding transfer ends.
The DMA controller interrupts the processor using the dma_done interrupt after the completion of transfers associated with each control data structure. The individual transfers using either the primary or the alternate control data
structures work exactly the same as a basic DMA transfer.
6–14
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Transfer Types
Software Ping-pong DMA Transfer
In this mode, if the DMA request is from software, request will be generated automatically after each arbitration
cycle until completion of primary or alternate descriptor tasks. This final descriptor should use an auto-request
transfer type. The figure below illustrates the process.
Task A : Primary, cycle_ctrl = 011, 2 R = 4, N = 6
SW Request
Task A
dma_done[C]
Task B : Alternate, cycle_ctrl = 011, 2 R = 4, N = 12
Task B
SW Request
AutoReqs
dma_done[C]
Task
C : Primary, cycle_ctrl = 011, 2 R = 2, N = 2
SW Request
Task C
dma_done[C]
Task D : Alternate, cycle_ctrl = 011, 2 R = 4, N = 5
SW Request
Task D
AutoReq
dma_done[C]
Task E : Primary, cycle_ctrl = 011, 2 R = 4, N = 7
SW Request
Task E
Auto Reqs
dma_done[C]
End : Alternate, cycle_ctrl = 000
Auto Request
Figure 6-3: Software Ping-pong DMA Transfer
Peripheral Ping-pong DMA Transfer
In this mode, if the DMA request is from a peripheral, it needs to send DMA requests after every data transfer to
complete primary or alternate descriptor tasks and the final descriptor should be programmed to use a basic transfer
type. The figure below illustrates the process.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–15
DMA Interrupts and Exceptions
Task A : Primary, cycle_ctrl = 011, 2 R = 4, N = 6
Requests
Task A
dma_done[C]
Task B : Alternate, cycle_ctrl = 011, 2 R = 4, N = 12
Reqs
Task B
dma_done[C]
Task C : Primary, cycle_ctrl = 011, 2 R = 2, N = 2
Req
Task C
dma_done[C]
Task D : Alternate, cycle_ctrl = 011, 2 R = 4, N = 5
Reqs
Task D
dma_done[C]
Task E : Primary, cycle_ctrl = 011, 2 R = 4, N = 7
Reqs
Task E
dma_done[C]
End : Alternate, cycle_ctrl = 000
Invalid
Figure 6-4: Peripheral Ping-pong DMA Transfer
DMA Interrupts and Exceptions
Memory Scatter-Gather
In this mode, the DMA controller needs to be configured to use both primary and alternate data structures. It uses
the primary data structure to program the control configuration for alternate data structure. The alternate data
structure is used for data transfers using a transfer similar to an auto-request DMA transfer. The controller arbitrates
after every primary transfer. The controller only needs one request to complete the entire transfer. This mode is used
when performing multiple memory-to-memory copy tasks. The processor can configure all of them together and is
not required to intervene in-between. The DMA controller interrupts the processor using the dma_done interrupt
when the entire scatter-gather transaction is completed using a basic cycle.
6–16
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Interrupts and Exceptions
In this mode, the controller receives an initial request and then performs four DMA transfers using the primary data
structure to program the control structure of the alternate data structure. After this transfer is completed, it starts a
DMA cycle using the alternate data structure. After the cycle is completed, the controller performs another four
DMA transfers using the primary data structure. The controller continues to switch from primary to alternate to
primary, until either:
• The Processor configures the alternate data structure for a basic cycle, or
• The DMA reads an invalid data structure.
Table 6-8:
CHNL_CFG for Primary Data Structure in Memory Scatter Gather Mode
Bit
Name
Value
Description
[31:30]
DST_INC
10
Configures the controller to use word increments for the address.
[29:28]
RESERVED
00
Undefined. Write as zero.
[27:26]
SRC_INC
10
Configures the controller to use word increments for the address.
[25:24]
SRC_SIZE
10
Configures the controller to use word transfers.
[23:18]
RESERVED
00
Undefined. Write as zero.
[17:14]
R_power
0010
Indicates that the DMA controller will perform four transfers.
[13:4]
N_minus_1
User
Configures the controller to perform N DMA transfers, where N is a multiple of 4.
[3]
RESERVED
00
Undefined. Write as zero.
[2:0]
Cycle_ctrl
100
Configures the controller to perform a memory scatter-gather DMA cycle.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–17
DMA Interrupts and Exceptions
Primary
Request
Alternate
Copy from A in
memory to
Alternate
Auto Req
Task A
Auto Req
N = 3, 2R = 4
Copy from B in
memory to
Alternate
Auto Req
Auto Reqs
Task B
N = 8, 2R = 2
Auto Req
Copy from C in
memory to
Alternate
Auto Req
Task C
Auto Req
N = 5, 2R = 8
Copy from D in
memory to
Alternate
Auto Req
Task D
N = 4, 2R = 4
dma_done[C]
Figure 6-5: Memory Scatter Gather Transfer Process
Peripheral Scatter-Gather
In this mode, the DMA controller should be configured to use both primary and alternate data structures. The controller uses the primary data structure to program the control structure of the alternate data structure. The alternate
data structure is used for actual data transfers and each transfer takes place using the alternate data structure with a
basic DMA transfer. The controller does not arbitrate after every primary transfer. This mode is used when there are
multiple peripheral-to-memory DMA tasks to be performed. The processor can configure all of them at the same
time and need not intervene in between.
This mode is very similar to memory scatter-gather mode except for arbitration and request requirements. The
DMA controller interrupts the processor using the dma_done interrupt when the entire scatter-gather transaction is
completed using a basic cycle.
In peripheral scatter-gather mode, the controller receives an initial request from a peripheral and then performs four
DMA transfers using the primary data structure to program the alternate control data structure. It then immediately
starts a DMA cycle using the al-ternate data structure, without re-arbitrating.
6–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Interrupts and Exceptions
After this cycle is completed, the controller re-arbitrates and if it receives a request from the peripheral and this has
the highest priority then it performs another four DMA transfers using the primary data structure. It then immediately starts a DMA cycle using the al-ternate data structure without re-arbitrating. The controller continues to
switch from primary to alternate to primary until either:
• The processor configures the alternate data structure for a basic cycle, or
• The DMA reads an invalid data structure
Table 6-9:
CHNL_CFG for Primary Data Structure in Peripheral Scatter Gather Mode
Bit
Name
Value
Description
[31:30]
DST_INC
10
Configures the controller to use word increments for the address.
[29:28]
RESERVED
00
Undefined. Write as zero.
[27:26]
SRC_INC
10
Configures the controller to use word increments for the address.
[25:24]
SRC_SIZE
10
Configures the controller to use word transfers.
[23:18]
RESERVED
00
Undefined. Write as zero.
[17:14]
R_power
0010
Indicates that the DMA controller will perform four transfers.
[13:4]
N_minus_1
user
Configures the controller to perform N DMA transfers, where N is a multiple of four.
[3]
RESERVED
00
Undefined. Write as zero.
[2:0]
Cycle_ctrl
110
Configures the controller to perform a memory scatter-gather DMA cycle.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–19
DMA Interrupts and Exceptions
Primary
Request
Alternate
Copy from A in
memory to
Alternate
Req
Task A
For all primary to alternate transitions,
the controller does not enter the
arbitration process and immediately
perorms the DMA transfer that the
alternate channel control data structure
specifies.
N = 3, 2R = 4
Copy from B in
memory to
Alternate
Reqs
Task B
N = 8, 2R = 2
Copy from C in
memory to
Alternate
Task C
N = 5, 2R = 8
Task D
N = 4, 2R = 4
Req
Copy from D in
memory to
Alternate
dma_done[C]
Figure 6-6: Peripheral Scatter Gather Transfer Process
Error Management
The DMA controller generates an error interrupt to the core when ever a DMA error occurs. A DMA error can
occur either because of a bus error or an invalid descriptor fetch. A bus error can occur while fetching the descriptor
or while performing a data transfer. A bus error can occur whenever a read from or write to a reserved address location happens.
When a bus error occurs, the faulty channel is automatically disabled, and the corresponding status bit in the
DMA_ERRCHNL_CLR is set. If the DMA error is enabled in the NVIC, the error will also generate an interrupt. In
addition, the CHNL_CFG data structure for the corresponding channel will be updated with the latest n_count. User
can check this to know how many successful data transfers happened before the bus error occurred.
When the controller fetches an invalid descriptor, the faulty channel is automatically disabled, and the corresponding status bit in the DMA_INVALIDDESC_CLR register is set. If the DMA error is enabled in NVIC, the error will
also generate an interrupt.
DMA Programming Model
The following section describes the programming sequence to configure the DMA.
6–20
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DMA Programming Model
Programming Guidelines
1. Enable the DMA controller in the DMA_CFG register.
2. Enable the desired DMA channel.
3. Setup the DMA base pointer.
4. Setup the DMA descriptor for data transmission.
5. Generate the software DMA request in the DMA_SWREQ register.
ADuCM302x DMA Register Descriptions
DMA (DMA) contains the following registers.
Table 6-10:
ADuCM302x DMA Register List
Name
Description
DMA_ADBPTR
DMA channel alternate control data base pointer
DMA_ALT_CLR
DMA channel primary-alternate clear
DMA_ALT_SET
DMA channel primary-alternate set
DMA_BS_CLR
DMA channel bytes swap enable clear
DMA_BS_SET
DMA channel bytes swap enable set
DMA_CFG
DMA Configuration
DMA_DSTADDR_CLR
DMA channel destination address decrement enable clear
DMA_DSTADDR_SET
DMA channel destination address decrement enable set
DMA_EN_CLR
DMA channel enable clear
DMA_EN_SET
DMA channel enable set
DMA_ERRCHNL_CLR
DMA Per Channel Error Clear
DMA_ERR_CLR
DMA bus error clear
DMA_INVALIDDESC_CLR
DMA Per Channel Invalid Descriptor Clear
DMA_PDBPTR
DMA channel primary control data base pointer
DMA_PRI_CLR
DMA channel priority clear
DMA_PRI_SET
DMA channel priority set
DMA_REVID
DMA Controller Revision ID
DMA_RMSK_CLR
DMA channel request mask clear
DMA_RMSK_SET
DMA channel request mask set
DMA_SRCADDR_CLR
DMA channel source address decrement enable clear
DMA_SRCADDR_SET
DMA channel source address decrement enable set
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–21
ADuCM302x DMA Register Descriptions
Table 6-10:
ADuCM302x DMA Register List (Continued)
Name
Description
DMA_STAT
DMA Status
DMA_SWREQ
DMA channel software request
6–22
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA channel alternate control data base pointer
The DMA_ADBPTR read-only register returns the base address of the alternate channel control data structure. This
register removes the necessity for application software to calculate the base address of the alternate data structure.
This register cannot be read when the DMA controller is in the reset state.
15 14 13 12 11 10 9
0
0
0
0
0
0
1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ADDR[15:0] (R)
Base address of the alternate data
structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDR[31:16] (R)
Base address of the alternate data
structure
Figure 6-7: DMA_ADBPTR Register Diagram
Table 6-11:
DMA_ADBPTR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 ADDR
Base address of the alternate data structure.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–23
ADuCM302x DMA Register Descriptions
DMA channel primary-alternate clear
The DMA_ALT_CLR write-only register enables the user to configure the appropriate DMA channel to use the primary control data structure. Each bit of the register represents the corresponding channel number in the DMA controller. Note: The DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scattergather and peripheral scatter-gather transfers.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Select primary data struct
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (W)
Select primary data struct
Figure 6-8: DMA_ALT_CLR Register Diagram
Table 6-12:
DMA_ALT_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(RX/W)
6–24
Select primary data struct.
Set the appropriate bit to select the primary data structure for the corresponding DMA
channel. Bit 0 corresponds to DMA channel 0 Bit M-1 corresponds to DMA channel
M-1 When Written: DMA_ALT_CLR.CHAN[C] = 0, No effect. Use the DMA_ALT_SET
register to select the alternate data structure. DMA_ALT_CLR.CHAN[C] = 1, Selects the
primary data structure for channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA channel primary-alternate set
The DMA_ALT_SET register enables the user to configure the appropriate DMA channel to use the alternate control
data structure. Reading the register returns the status of which data structure is in use for the corresponding DMA
channel. Each bit of the register represents the corresponding channel number in the DMA controller. Note: The
DMA controller sets/clears these bits automatically as necessary for ping-pong, memory scatter-gather and peripheral scatter-gather transfers.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Control struct status / select alt struct
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (R/W)
Control struct status / select alt struct
Figure 6-9: DMA_ALT_SET Register Diagram
Table 6-13:
DMA_ALT_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(R/W)
Control struct status / select alt struct.
Returns the channel control data structure status, or selects the alternate data structure
for the corresponding DMA channel. Bit 0 corresponds to DMA channel 0 Bit M-1
corresponds to DMA channel M-1 When Read: DMA_ALT_SET.CHAN[C] = 0, DMA
channel C is using the primary data structure. DMA_ALT_SET.CHAN[C] = 1, DMA
channel C is using the alternate data structure. When Written:
DMA_ALT_SET.CHAN[C] = 0, No effect. Use the DMA_ALT_CLR register to set bit [C]
to 0. DMA_ALT_SET.CHAN[C] = 1, Selects the alternate data structure for channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–25
ADuCM302x DMA Register Descriptions
DMA channel bytes swap enable clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Disable byte swap
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (W)
Disable byte swap
Figure 6-10: DMA_BS_CLR Register Diagram
Table 6-14:
DMA_BS_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(RX/W)
6–26
Disable byte swap.
The DMA_BS_CLR write-only register enables the user to configure a DMA channel to
not use byte swapping and use the default operation. Each bit of the register represents
the corresponding channel number in the DMA controller. Bit 0 corresponds to DMA
channel and bit M-1 corresponds to DMA channel M-1 When Written:
DMA_BS_CLR.CHAN[C] = 0, No effect. Use the DMA_BS_SET register to enable byte
swap on channel C. DMA_BS_CLR.CHAN[C] = 1, Disables Byte Swap on channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA channel bytes swap enable set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Byte swap status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (R/W)
Byte swap status
Figure 6-11: DMA_BS_SET Register Diagram
Table 6-15:
DMA_BS_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(R/W)
Byte swap status.
This register is used to configure a DMA channel to use byte swap. Each bit of the
register represents the corresponding channel number in the DMA controller. Bit 0
corresponds to DMA channel 0 and bit M-1 corresponds to DMA channel M-1 When
Read: DMA_BS_SET.CHAN[C] = 0, Channel C Byte Swap is disabled.
DMA_BS_SET.CHAN[C] = 1, Channel C Byte Swap is enabled. When Written:
DMA_BS_SET.CHAN[C] = 0, No effect. Use the DMA_BS_CLR register to disable byte
swap on channel C DMA_BS_SET.CHAN[C] = 1, Enables Byte Swap on channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–27
ADuCM302x DMA Register Descriptions
DMA Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MEN (W)
Controller enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-12: DMA_CFG Register Diagram
Table 6-16:
DMA_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 MEN
(RX/W)
Controller enable.
0 Disable controller
1 Enable controller
6–28
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA channel destination address decrement enable clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Disable destination address decrement
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (W)
Disable destination address decrement
Figure 6-13: DMA_DSTADDR_CLR Register Diagram
Table 6-17:
DMA_DSTADDR_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(RX/W)
Disable destination address decrement.
The DMA_DSTADDR_CLR write-only register enables the user to configure a DMA
channel to use the default destination address in increment mode. Each bit of the register represents the corresponding channel number in the DMA controller. Bit 0 corresponds to DMA channel 0 Bit M-1 corresponds to DMA channel M-1 When Written:
DMA_DSTADDR_CLR.CHAN[C] = 0, No effect. Use the DMA_DSTADDR_SET register to
enable destination address decrement on channel C DMA_DSTADDR_CLR.CHAN[C] =
1, Disables destination address decrement on channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–29
ADuCM302x DMA Register Descriptions
DMA channel destination address decrement enable set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Destination Address decrement status
/ configure destination address decrement
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (R/W)
Destination Address decrement status
/ configure destination address decrement
Figure 6-14: DMA_DSTADDR_SET Register Diagram
Table 6-18:
DMA_DSTADDR_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(R/W)
6–30
Destination Address decrement status / configure destination address decrement.
The DMA_DSTADDR_SET register is used to configure the destination address of a
DMA channel to decrement the address instead of incrementing the address after each
access. Each bit of the register represents the corresponding channel number in the
DMA controller. Bit 0 corresponds to DMA channel and bit M-1 corresponds to
DMA channel M-1 When Read: DMA_DSTADDR_SET.CHAN[C] = 0, Channel C destination address decrement is disabled. DMA_DSTADDR_SET.CHAN[C] = 1, Channel C
destination address decrement is enabled. When Written:
DMA_DSTADDR_SET.CHAN[C] = 0, No effect. Use the DMA_DSTADDR_CLR register to
disable destination address decrement on channel C DMA_DSTADDR_SET.CHAN[C] =
1, Enables destination address decrement on channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA channel enable clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Disable DMA channels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (W)
Disable DMA channels
Figure 6-15: DMA_EN_CLR Register Diagram
Table 6-19:
DMA_EN_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(RX/W)
Disable DMA channels.
This register allows for the disabling of DMA channels. This register is write only.
Each bit of the register represents the corresponding channel number in the DMA
controller. Note: The controller disables a channel automatically, by setting the appropriate bit, when it completes the DMA cycle. Set the appropriate bit to disable the corresponding channel. Bit 0 corresponds to DMA channel 0 Bit M-1 corresponds to
DMA channel M-1 When Written: DMA_EN_CLR.CHAN[C] = 0, No effect. Use the
DMA_EN_SET register to enable the channel. DMA_EN_CLR.CHAN[C] = 1, Disables
channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–31
ADuCM302x DMA Register Descriptions
DMA channel enable set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Enable DMA channels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (R/W)
Enable DMA channels
Figure 6-16: DMA_EN_SET Register Diagram
Table 6-20:
DMA_EN_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(R/W)
6–32
Enable DMA channels.
This register allows for the enabling of DMA channels. Reading the register returns the
enable status of the channels. Each bit of the register represents the corresponding
channel number in the DMA controller. Set the appropriate bit to enable the corresponding channel. Bit 0 corresponds to DMA channel 0 Bit M-1 corresponds to DMA
channel M -1 When Read: DMA_EN_SET.CHAN[C] = 0, Channel C is disabled.
DMA_EN_SET.CHAN[C] = 1, Channel C is enabled. When Written:
DMA_EN_SET.CHAN[C] = 0, No effect. Use the DMA_EN_CLR register to disable the
channel. DMA_EN_SET.CHAN[C] = 1, Enables channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA Per Channel Error Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W1C)
Per channel Bus error status/ Per channel
bus error clear
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (R/W1C)
Per channel Bus error status/ Per channel
bus error clear
Figure 6-17: DMA_ERRCHNL_CLR Register Diagram
Table 6-21:
DMA_ERRCHNL_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(R/W1C)
Per channel Bus error status/ Per channel bus error clear.
This register is used to read and clear the per channel DMA bus error status. The error
status is set if the controller encountered a bus error while performing a transfer. If a
bus error occurs on a channel, that channel is automatically disabled by the controller.
The other channels are unaffected. Write one to clear bits. When Read: 0 No bus error
occurred. 1 A bus error control is pending. When Written: 0 No effect. 1 Bit is cleared.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–33
ADuCM302x DMA Register Descriptions
DMA bus error clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W1C)
Bus error status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (R/W1C)
Bus error status
Figure 6-18: DMA_ERR_CLR Register Diagram
Table 6-22:
DMA_ERR_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(R/W1C)
6–34
Bus error status.
This register is used to read and clear the DMA bus error status. The error status is set
if the controller encountered a bus error while performing a transfer or when it reads
an invalid descriptor (whose cycle control is 3'b000). If a bus error occurs or invalid
cycle control is read on a channel, that channel is automatically disabled by the controller. The other channels are unaffected. Write one to clear bits. When Read: 0 No
bus_error/invalid cycle control occurred. 1 A bus_error/invalid cycle control is pending. When Written: 0 No effect. 1 Bit is cleared.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA Per Channel Invalid Descriptor Clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W1C)
Per channel Invalid Descriptor status/
Per channel Invalid descriptor status
clear
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (R/W1C)
Per channel Invalid Descriptor status/
Per channel Invalid descriptor status
clear
Figure 6-19: DMA_INVALIDDESC_CLR Register Diagram
Table 6-23:
DMA_INVALIDDESC_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(R/W1C)
Per channel Invalid Descriptor status/ Per channel Invalid descriptor status clear.
This register is used to read and clear the per channel DMA invalid descriptor status.
The per channel invalid descriptor status is set if the controller reads an invalid descriptor (whose cycle control is 3'b000). If it reads invalid cycle control for a channel,
that channel is automatically disabled by the controller. The other channels are unaffected. Write one to clear bits. When Read: 0 No invalid cycle control occurred. 1 An
invalid cycle control is pending. When Written: 0 No effect. 1 Bit is cleared.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–35
ADuCM302x DMA Register Descriptions
DMA channel primary control data base pointer
The DMA_PDBPTR register must be programmed to point to the primary channel control base pointer in the system
memory. The amount of system memory that must be assigned to the DMA controller depends on the number of
DMA channels used and whether the alternate channel control data structure is used. This register cannot be read
when the DMA controller is in the reset state.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ADDR[15:0] (R/W)
Pointer to the base address of the primary
data structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDR[31:16] (R/W)
Pointer to the base address of the primary
data structure
Figure 6-20: DMA_PDBPTR Register Diagram
Table 6-24:
DMA_PDBPTR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 ADDR
(R/W)
6–36
Pointer to the base address of the primary data structure.
5 + log(2) M LSBs are reserved and must be written 0. M is number of channels.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA channel priority clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHPRICLR[15:0] (W)
Configure channel for default priority
level
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHPRICLR[23:16] (W)
Configure channel for default priority
level
Figure 6-21: DMA_PRI_CLR Register Diagram
Table 6-25:
DMA_PRI_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHPRICLR
(RX/W)
Configure channel for default priority level.
The DMA_PRI_CLR write-only register enables the user to configure a DMA channel
to use the default priority level. Each bit of the register represents the corresponding
channel number in the DMA controller. Set the appropriate bit to select the default
priority level for the specified DMA channel. Bit 0 corresponds to DMA channel and
bit M-1 corresponds to DMA channel M-1 When Written:
DMA_PRI_CLR.CHPRICLR[C] = 0, No effect. Use the DMA_PRI_SET register to set
channel C to the high priority level. DMA_PRI_CLR.CHPRICLR[C] = 1, Channel C
uses the default priority level.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–37
ADuCM302x DMA Register Descriptions
DMA channel priority set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Configure channel for high priority
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (W)
Configure channel for high priority
Figure 6-22: DMA_PRI_SET Register Diagram
Table 6-26:
DMA_PRI_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(RX/W)
6–38
Configure channel for high priority.
This register enables the user to you to configure a DMA channel to use the high priority level. Reading the register returns the status of the channel priority mask. Each
bit of the register represents the corresponding channel number in the DMA controller. Returns the channel priority mask status, or sets the channel priority to high. Bit 0
corresponds to DMA channel 0, bit M-1 corresponds to DMA channel M-1 When
Read: DMA_PRI_SET.CHAN[C] = 0, DMA channel C is using the default priority level. DMA_PRI_SET.CHAN[C] = 1, DMA channel C is using a high priority level. When
Written: DMA_PRI_SET.CHAN[C] = 0, No effect. Use the DMA_PRI_CLR register to
set channel C to the default priority level. DMA_PRI_SET.CHAN[C] = 1, Channel C
uses the high priority level.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA Controller Revision ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
VALUE (R)
DMA Controller revision ID
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 6-23: DMA_REVID Register Diagram
Table 6-27:
DMA_REVID Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
DMA Controller revision ID.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–39
ADuCM302x DMA Register Descriptions
DMA channel request mask clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Clear Request Mask Set bits
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (W)
Clear Request Mask Set bits
Figure 6-24: DMA_RMSK_CLR Register Diagram
Table 6-28:
DMA_RMSK_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(RX/W)
6–40
Clear Request Mask Set bits.
This register enables DMA requests from peripherals by clearing the mask set in
DMA_RMSK_SET register. Each bit of the register represents the corresponding channel
number in the DMA controller. Set the appropriate bit to clear the corresponding
DMA_RMSK_SET.CHAN bit. Bit 0 corresponds to DMA channel 0 Bit M-1 corresponds to DMA channel M-1 When Written: DMA_RMSK_CLR.CHAN[C] = 0, No effect. Use the DMA_RMSK_SET register to disable DMA requests.
DMA_RMSK_CLR.CHAN[C] = 1, Enables peripheral associated with channel C to generate DMA requests.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA channel request mask set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Mask requests from DMA channels
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (R/W)
Mask requests from DMA channels
Figure 6-25: DMA_RMSK_SET Register Diagram
Table 6-29:
DMA_RMSK_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(R/W)
Mask requests from DMA channels.
This register disables DMA requests from peripherals. Each bit of the register represents the corresponding channel number in the DMA controller. Set the appropriate
bit to mask the request from the corresponding DMA channel. Bit 0 corresponds to
DMA channel 0 Bit M-1 corresponds to DMA channel M-1 When Read:
DMA_RMSK_SET.CHAN[C] = 0, Requests are enabled for channel C.
DMA_RMSK_SET.CHAN[C] = 1, Requests are disabled for channel C. When Written:
DMA_RMSK_SET.CHAN[C] = 0, No effect. Use the DMA_RMSK_SET register to enable
DMA requests. DMA_RMSK_SET.CHAN[C] = 1, Disables peripheral associated with
channel C from generating DMA requests.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–41
ADuCM302x DMA Register Descriptions
DMA channel source address decrement enable clear
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Disable source address decrement
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (W)
Disable source address decrement
Figure 6-26: DMA_SRCADDR_CLR Register Diagram
Table 6-30:
DMA_SRCADDR_CLR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(RX/W)
6–42
Disable source address decrement.
The DMA_SRCADDR_CLR write-only register enables the user to configure a DMA
channel to use the default source address in increment mode. Each bit of the register
represents the corresponding channel number in the DMA controller. Bit 0 corresponds to DMA channel 0 Bit M-1 corresponds to DMA channel M-1 When Written:
DMA_SRCADDR_CLR.CHAN[C] = 0, No effect. Use the DMA_SRCADDR_SET register to
enable source address decrement on channel C DMA_SRCADDR_CLR.CHAN[C] = 1,
Disables Address source decrement on channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA channel source address decrement enable set
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (R/W)
Source Address decrement status /
configure Source address decrement
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (R/W)
Source Address decrement status /
configure Source address decrement
Figure 6-27: DMA_SRCADDR_SET Register Diagram
Table 6-31:
DMA_SRCADDR_SET Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(R/W)
Source Address decrement status / configure Source address decrement.
The DMA_SRCADDR_SET register is used to configure the source address of a DMA
channel to decrement the address instead of incrementing the address after each access.
Each bit of the register represents the corresponding channel number in the DMA
controller. Bit 0 corresponds to DMA channel and bit M-1 corresponds to DMA
channel M-1 When Read: DMA_SRCADDR_SET.CHAN[C] = 0, Channel C Source Address decrement is disabled. DMA_SRCADDR_SET.CHAN[C] = 1, Channel C Source
Address decrement is enabled. When Written: DMA_SRCADDR_SET.CHAN[C] = 0, No
effect. Use the DMA_SRCADDR_CLR register to disable source address decrement on
channel C DMA_SRCADDR_SET.CHAN[C] = 1, Enables source address decrement on
channel C.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–43
ADuCM302x DMA Register Descriptions
DMA Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MEN (R)
Enable status of the controller
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
CHANM1 (R)
Number of available DMA channels
minus 1
Figure 6-28: DMA_STAT Register Diagram
Table 6-32:
DMA_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
20:16 CHANM1
(R/NW)
0 MEN
(R/NW)
Number of available DMA channels minus 1.
With 24 channels available, the register will read back 0x17
Enable status of the controller.
0 Controller is disabled
1 Controller is enabled
6–44
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x DMA Register Descriptions
DMA channel software request
The DMA_SWREQ register enables the generation of software DMA request. Each bit of the register represents the
corresponding channel number in the DMA controller. M is the number of DMA channels
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CHAN[15:0] (W)
Generate software request
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CHAN[23:16] (W)
Generate software request
Figure 6-29: DMA_SWREQ Register Diagram
Table 6-33:
DMA_SWREQ Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:0 CHAN
(RX/W)
Generate software request.
Set the appropriate bit to generate a software DMA request on the corresponding
DMA channel. Bit 0 corresponds to DMA channel 0 Bit M-1 corresponds to DMA
channel M-1 When Written: DMA_SWREQ.CHAN[C] = 0, Does not create a DMA request for channel C. DMA_SWREQ.CHAN[C] = 1, Generates a DMA request for channel C. These bits are automatically cleared by the hardware after the corresponding
software request completes.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
6–45
Reset (RST)
7 Reset (RST)
The ADuCM302x processor has the following resets:
• External
• Power-on
• Watchdog timeout
• Software system
The software system reset is provided as part of the Cortex-M3 core.
To generate a system reset through software, the application interrupt/reset control register must be set to a value of
0x05FA0004. This register is part of the NVIC subsystem and is located at address 0xE000ED0C.
For more information about software reset, refer to the ARM Cortex-M3 Technical Reference Manual.
A hardware reset is performed by toggling the SYS_HWRST pin which is active low.
The PMG_RST_STAT register indicates the source of the last reset. The register can be used during a reset exception
service routine to identify the source of the reset.
Table 7-1:
Reset
Reset Types
Reset External Pins
to Default
State
Execute
Kernel
Reset All MMRs Except PMG_RST_STAT
Reset All Pe- Valid SRAM
ripherals
Software
Yes*1
Yes
Yes
Yes
Yes/no*2
PMG_RST_STAT.SWRST = 1
Watchdog
Yes
Yes
Yes
Yes
Yes/no2
PMG_RST_STAT.WDRST = 1
External reset pin Yes
Yes
Yes
Yes
Yes/no2
PMG_RST_STAT.EXTRST = 1
POR
Yes
Yes
Yes
No
PMG_RST_STAT.POR = 1
Yes
PMG_RST_STAT After Reset
Event
PMG_RST_STAT.PORSRC has
info on cause of POR reset
*1
GPIOx will return to its default state, that is, same as a POR event.
*2
RAM is not valid in the case of a reset following a UART download.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
7–1
ADuCM302x Reset Register Description
ADuCM302x Reset Register Description
Table 7-2:
ADuCM302x Reset Register List
Name
Description
Reset
Access
PMG_RST_STAT
Reset status.
0x000000XX
R/W
7–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Debug (DBG)
8 Debug (DBG)
The ADuCM302x control processor supports the 2-wire serial wire debug (SWD) interface.
DBG Features
The ADuCM302x control processor contains several system debug components that facilitate low-cost debug, trace
and profiling, breakpoints, watch-points and code patching.
This product was intended to be a lightweight implementation of the Cortex-M3 processor. Minimal debug features
are included in the processor. All debug units are present but the debug capability is reduced.
The supported system debug components on this part are:
• Flash Patch and Breakpoint (FPB) unit to implement two breakpoints. Flash patching is not supported.
• Data Watchpoint and Trace (DWT) unit to implement one watch-point, trigger resources, and system profiling. The DWT does not support data matching for watchpoint generation because it only has one comparator.
NOTE: JTAG debug interface is not supported. In addition, embedded trace features of the processor are supported.
DBG Functional Description
This section provides information on the function of the Serial Wire Debug (SWD) interface used by the
ADuCM302x control processor.
ADuCM302x SYS Register List
Table 8-1:
ADuCM302x SYS Register List
Name
Description
SYS_ADIID
ADI Identification
SYS_CHIPID
Chip Identifier
SYS_SWDEN
Serial Wire Debug Enable
ADuCM302x Mixed-Signal Control Processor Hardware Reference
8–1
DBG Functional Description
Serial Wire Interface
The serial wire interface consists of two pins:
• SWCLK
• SWDIO
SWCLK is driven by the debug probe.
SWDIO is a bidirectional signal which may be driven by the debug probe or target depending on the protocol
phase. A non-driving idle turnaround cycle is inserted on the bus whenever data direction changes to avoid contention.
SWD Pull-up
There must be a pullup resistor on the SWDIO pin.
The SWCLK pin should be pulled to a defined state (high or low). It is recommended to pull this pin LOW.
SWD Timing
The target samples and drives SWDIO data on posedge SWCLK.
For optimum timing, the debug probe should drive SWDIO on negedge SWCLK and sample SWDIO on posedge
SWCLK.
Probe Driving
Target Sampling
Target Driving
Probe Sampling
SWCLK
SWCLK
SWDIO
SWDIO
Probe
Target
Drives
Samples
Neg Edge Pos Edge
Target
Drives
Pos Edge
Probe
Samples
Pos Edge
Target to Probe
Bus Turnaround
Probe to Target
Bus Turnaround
SWCLK
SWCLK
SWDIO
SWDIO
Probe
Target
Tristates
Drives
Neg Edge Pos Edge
delay
delay
Target
Tristates
Pos Edge
Probe
Drives
Neg Edge
Figure 8-1: SWD Timing
8–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
DBG Operating Modes
DBG Operating Modes
The ADuCM302x control processor supports the following:
Serial Wire Protocol
The Serial Wire Protocol consists of three phases:
• Packet Request
• Acknowledge Response
• Data Transfer
The debug probe always sends the packet request.
The target always sends the acknowledge response.
The data transfer direction depends on the packet request and acknowledge response.
Packet Request
The packet request sent by the debug probe is 8-bits and is always followed by a turnaround bit.
Table 8-2:
Packet Request
Bit
Description
Start
Always High = Logic 1
APnDP
Access Port = 1 or Data Port = 0
RnW
Read = 1 or Write = 0
A[2:3]
Address sent LSB first
Parity
Parity = APnDP + RnW + A[2] + A[3]
Stop
Always Low = Logic 0
Park
Always High = Logic 1
Turn
High Impedance / Non-Driving
Acknowledge Response
The acknowledge response sent by the target is 3-bits. If the target sends data for a read (RnW=1), it is followed
directly by the data transfer, there is no turnaround bit. If the debug probe sends the data transfer for a write
(RnW=0), the acknowledge is followed by a turnaround bit.
Table 8-3:
Acknowledge Response
Bit
Description
ACK[0:2]
Acknowledge Sent LSB first
[0:2]
ADuCM302x Mixed-Signal Control Processor Hardware Reference
8–3
Debug Access Port (DAP)
Table 8-3:
Acknowledge Response (Continued)
Bit
Description
100 = OK
010 = WAIT
001 = FAULT
Data Transfer
The data transfer phase consists of 32 bits of data sent LSB first [0:31], followed by a single parity bit. If the number
of bits set in the data field is odd, the parity bit is set to 1.
For reads where data is sent by the target, the data transfer is followed by a turnaround bit. For writes where data is
sent by the debug probe, there is no turnaround bit.
The data transfer phase is omitted for WAIT & FAULT responses unless the CTRL/STAT ORUNDETECT bit is
set. If the ORUNDETECT bit is set, the data transfer phase is always sent and STICKYORUN will be set if a
WAIT or FAULT response occurs.
Protocol Format
The figure shows the protocol format.
Stop
Park
Turn
A[2:3]
Parity
Stop
Park
Turn
ACK[0:2]
A[2:3]
Parity
Stop
Park
Turn
ACK[0:2]
Parity
Turn
Parity
ACK[0:2]
Turn
RnW
A[2:3]
RnW
Start
APnDP
Write
WDATA[0:31]
Turn
RDATA[0.31]
Parity
Start
APnDP
Read
Turn
RnW
Start
APnDP
Wait/Fault
Figure 8-2: Protocol Format
Debug Access Port (DAP)
The DAP is split into two ports:
• Debug Port (DP)
8–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Debug Port
• Access Port (AP)
There is a single Debug Port. There may be multiple Access Ports.
The Debug-Port has a 2-bit (4-word) address space which is separate from the system memory address space. These
registers can only be accessed through the serial wire debug interface, they cannot be accessed by the CPU.
Each Access-Port has a separate 6-bit address space allowing up to 64 word registers per access port. This address
space is separate from the debug port and system CPU address spaces. It can only be accessed by the serial wire
interface through the debug port.
On this device, there is only one Access Port available, the Memory Access-Port located at APSEL==00.
Table 8-4:
Access Ports
APSEL[7:0]
Access Port
00
Memory Access-Port
Debug Port
The Debug Port has four 32-bit read write register locations. These are used to identify and configure the interface
and to select and communicate with a particular Access Port.
Table 8-5:
Debug Port Registers
Address[3:2]
Read
Write
DPBANKSEL
00
DPIDR
ABORT
X
01
CTRL/STAT
0
DLCR
1
10
RESEND
SELECT
X
11
RDBUFF
Reserved
X
ADuCM302x SYS Register Descriptions
System Identification and Debug Enable (SYS) contains the following registers.
Table 8-6:
ADuCM302x SYS Register List
Name
Description
SYS_ADIID
ADI Identification
SYS_CHIPID
Chip Identifier
SYS_SWDEN
Serial Wire Debug Enable
ADuCM302x Mixed-Signal Control Processor Hardware Reference
8–5
ADuCM302x SYS Register Descriptions
ADI Identification
ADI Cortex device identification.
15 14 13 12 11 10 9
0
1
0
0
0
0
0
8
7
6
5
4
3
2
1
0
1
0
1
0
0
0
1
0
0
VALUE (R)
Reads a fixed value of 0x4144 to indicate
to debuggers that they are connected
to an Analog Devices implemented
Cortex based part
Figure 8-3: SYS_ADIID Register Diagram
Table 8-7:
SYS_ADIID Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/NW)
8–6
Reads a fixed value of 0x4144 to indicate to debuggers that they are connected to an
Analog Devices implemented Cortex based part.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SYS Register Descriptions
Chip Identifier
Chip identification.
15 14 13 12 11 10 9
0
0
0
0
0
0
1
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
0
1
0
PARTID (R)
Part identifier
REV (R)
Silicon revision
Figure 8-4: SYS_CHIPID Register Diagram
Table 8-8:
SYS_CHIPID Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:4 PARTID
Part identifier.
(R/NW)
3:0 REV
Silicon revision.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
8–7
ADuCM302x SYS Register Descriptions
Serial Wire Debug Enable
The SYS_SWDEN register is used to enable the Serial Wire Debug (SWD) interface. This register is reset upon an
internal power on reset or an external pin reset. This register is not affected by a software reset.
15 14 13 12 11 10 9
0
1
1
1
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
1
1
0
0
1
0
VALUE (W)
To enable SWD interface
Figure 8-5: SYS_SWDEN Register Diagram
Table 8-9:
SYS_SWDEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(RX/W)
8–8
To enable SWD interface.
Writing the SWDEN register with "en" (0x6E65) or "EN" (0x4E45) will enable the
SWD interface. Writing the SWDEN register with "rp" (0x7072) or "RP" (0x5052)
will disable the SWD interface. Writes of any other value are ignored. The SWDEN
register cannot be modified once written with "EN" or "RP". This register is reset by a
POR or PIN reset, but not software or WDT reset.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
CRYPTO
9 CRYPTO
Crypto is an accelerator block that supports the AES Cipher, NIST Block modes of operation and the SHA hash
function generator.
Advanced encryption standard, abbreviated as AES, is the specification for a symmetric key algorithm to encrypt
electronic data announced by the National Institute of Standards and Technology (NIST) in the year 2001 to replace the older DES Standard. The AES algorithm operates on a fixed data block of 128 bits. Secure Hash Algorithm, abbreviated SHA, is a hashing algorithm that works on messages parsed into 512-bit data blocks and generates a digest. This document assumes familiarity with the operation of the AES standard, NIST block cipher modes
of operation and SHA algorithms. The reader may refer to the following publications for details.
Table 9-1:
NIST Publication List
AES standard
Federal Information Processing Standard (FIPS) 197
NIST Block Modes of Operation
Special Publication-800-38A, B & C
SHA
FIPS 180-4
Crypto Features
The ADuCM302x processor supports the following features:
• 32 APB Slave.
• Two 128-bit buffers:
• Input Buffer
• Output Buffer
• Two DMA channels:
• Input buffer
• Output buffer
• AES Cipher Key Lengths supported:
• 128-bit
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–1
Crypto Functional Description
• 256-bit
• AES Cipher Key Source
• Programmable through MMR
• Supported Modes:
• AES Cipher Encryption and Decryption in ECB Mode
• AES Cipher Encryption and Decryption in CBC Mode
• AES Cipher Encryption and Decryption in CTR Mode
• AES Cipher MAC Generation Mode
• AES Cipher Encryption and Decryption in CCM Mode
• AES Cipher Encryption and Decryption in CCM* Mode
• SHA - 256 Mode
• SHA - 256 + Block Cipher Operations using the AES Cipher
Crypto Functional Description
This section provides information on the function of the Crypto block used by the ADuCM302x processor.
ADuCM302x CRYPT Register List
crypto
Table 9-2:
ADuCM302x CRYPT Register List
Name
Description
CRYPT_AESKEY0
Key Bits[ 31:0 ]
CRYPT_AESKEY1
Key Bits [ 63:32 ]
CRYPT_AESKEY2
Key Bits [ 95:64 ]
CRYPT_AESKEY3
Key Bits [ 127:96 ]
CRYPT_AESKEY4
Key Bits [ 159:128 ]
CRYPT_AESKEY5
Key Bits [ 191:160 ]
CRYPT_AESKEY6
Key Bits [ 223:192 ]
CRYPT_AESKEY7
Key Bits [ 255:224 ]
CRYPT_CCM_NUM_VALID_BYTES
NUM_VALID_BYTES
CRYPT_CFG
Configuration Register
CRYPT_CNTRINIT
Counter Initialization Vector
9–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Crypto Functional Description
Table 9-2:
ADuCM302x CRYPT Register List (Continued)
Name
Description
CRYPT_DATALEN
Payload Data Length
CRYPT_INBUF
Input Buffer
CRYPT_INTEN
Interrupt Enable Register
CRYPT_NONCE0
Nonce Bits [31:0]
CRYPT_NONCE1
Nonce Bits [63:32]
CRYPT_NONCE2
Nonce Bits [95:64]
CRYPT_NONCE3
Nonce Bits [127:96]
CRYPT_OUTBUF
Output Buffer
CRYPT_PREFIXLEN
Authentication Data Length
CRYPT_SHAH0
SHA Bits [ 31:0 ]
CRYPT_SHAH1
SHA Bits [ 63:32 ]
CRYPT_SHAH2
SHA Bits [ 95:64 ]
CRYPT_SHAH3
SHA Bits [ 127:96 ]
CRYPT_SHAH4
SHA Bits [ 159:128 ]
CRYPT_SHAH5
SHA Bits [ 191:160 ]
CRYPT_SHAH6
SHA Bits [ 223:192]
CRYPT_SHAH7
SHA Bits [ 255:224 ]
CRYPT_SHA_LAST_WORD
SHA Last Word and Valid Bits Information
CRYPT_STAT
Status Register
Crypto Block Diagram
The figure below illustrates the block diagram of the Crypto block used by the ADuCM302x processor.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–3
Crypto Operating Modes
AHB Bus
AHB Interface
Controller
Input Buffer
Controller
Output Buffer
AES Core, CBC
Controller and
SHA Logic
Figure 9-1: Crypto Block Diagram
Crypto is a 32-bit APB DMA Capable peripheral. There are two buffers provided for data I/O operations. These
buffers are 32-bit wide and will read in or read out 128-bits in four data accesses. Big Endian and Little Endian data
formats are supported.
When enabled, the block takes the data from its input buffer and gives out the processed data through the output
buffer. DMA can be used for performing these data operations. It is important for the programmer to ensure that
the configuration bits, keys and other relevant registers are set to the desired values before the block is enabled and
data transfer is initiated.
Crypto Operating Modes
The following block modes of operation are supported:
• CTR Mode Counter mode
• CBC Mode Cipher Block Chaining mode
• MAC Mode Message Authentication Code
• CCM Mode Cipher Block Chaining-Message Authentication Code Mode
There are mode enable bit fields provided in the CRYPT_CFG register which need to be set to enable the desired
mode of operation. A particular block mode is enabled by setting the appropriate bit field to 1.
The programmer should enable only one block mode of operation at a given time. The bit fields for enabling different modes of operation are: CRYPT_CFG.ECBEN, CRYPT_CFG.CTREN, CRYPT_CFG.CBCEN, CRYPT_CFG.CCMEN,
and CRYPT_CFG.CMACEN. Enabling multiple block modes will cause unpredictable results. No error or warning
will be flagged.
9–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Crypto Operating Modes
It is allowed to enable one Block mode of operation and SHA mode at the same time.
DMA Capability
The block supports use of DMA to transfer data to or from the buffers. The DMA is expected to do less than or
equal to four word transfers per DMA request on both the input and output buffers. The DMA requesting for the
buffers can be enabled by setting the bit fields CRYPT_CFG.INDMAEN/ CRYPT_CFG.OUTDMAEN bit fields provided
in the CRYPT_CFG register. The block will raise the input buffer DMA request line high till the input buffer is
filled. Similarly the DMA request on the output buffer will be held high till the output buffer is emptied.
The programmer must not change the configuration bits in the middle of a data transaction. Doing so will result in
wrong output and no error or warning will be raised.
Core Transfer
If DMA is not used, then the software is expected to keep track of the number of words that are to be transferred to
the block and read back from the block. The bit-fields that indicate the status and error conditions are available in
the CRYPT_STAT register. The interrupts for different conditions can be enabled in the CRYPT_INTEN register.
Endianness
The block supports both Big Endian and Little Endian data formats for the Payload and the Associated data.
Little Endian is a system where the most significant byte is stored in the smallest address of the word.
In Little Endian mode, Payload(P) should be written into the input buffer in the following format:
First Data Input = { P [`b15], P [`b14], P [`b13], P [`b12] }
Second Data Input = { P [`b11], P [`b10], P [ `b9], P [ `b8] }
Third Data Input = { P [ `b7], P [ `b6], P [ `b5], P [ `b4] }
Fourth Data Input = { P [ `b3], P [ `b2], P [ `b1], P [ `b0] }
In Little Endian mode, Cipher should be written into the input buffer in the following sequence:
First Data Output = { C [`b15], C [`b14], C [`b13], C [`b12] }
Second Data Output = { C [`b11], C [`b10], C [ `b9], C [ `b8] }
Third Data Output = { C [ `b7], C [ `b6], C [ `b5], C [ `b4] }
Fourth Data Output = { C [ `b3], C [ `b2], C [ `b1], C [ `b0] }
Big Endian is a system where the least significant byte is stored in the smallest address of the word. This means that
128-bit Payload (P) and Cipher (C) will be treated in the following manner:
In Big Endian mode, Payload(P) will need to be written into the input buffer in the following sequence:
First Data Input = { P [`b12], P [`b13], P [`b14], P [`b15] }
Second Data Input = { P[ `b8], P [ `b9], P [`b10], P [ `b11] }
Third Data Input = { P [ `b4], P [ `b5], P [ `b6], P [ `b7] }
Fourth Data Input = { P [ `b0], P [ `b1], P [ `b2], P [ `b3] }
In Big Endian mode, Cipher(C) will need to be written into the input buffer in the following sequence:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–5
Crypto Operating Modes
First Data Output = { C [`b12], C [`b13], C [`b14], C [`b15] }
Second Data Output = { C [ `b8], C [ `b9], C [`b10], C [ `b11] }
Third Data Output = { C [ `b4], C [ `b5], C [ `b6], C [ `b7] }
Fourth Data Output = { C [ `b0], C [ `b1], C [ `b2], C [ `b3] }
INPUT_READY_INT
This interrupt indicates that the input buffer is not full. If enabled, this will trigger interrupts as long as the Input
Buffer is not filled. Since this interrupt is used when the data buffer is being written by the core, the recommended
way is to fill the input buffer from the ISR.
OUTPUT_READY_INT
This interrupt indicates that the output buffer holds data and is waiting to be read. This will remain set as long as
the output buffer is not empty. Since this interrupt is used when the data buffer is being read by the core, the recommended way to use this is to read the entire 128-bits in the ISR.
SHA_DONE
This interrupt indicates that the SHA computation is completed. New data may be written into the input buffer or
that the hash results may be read out of the CRYPT_SHAH0 to CRYPT_SHAH7 registers.
IN_OVF_INT
This bit indicates that the input buffer overflow event has occurred. The causes for this may be:
• The output buffer has not been read. This stalls the block.
• The input data rate is higher than the rate the Crypto block can process.
When the DMA or the core program is programmed as recommended in this manual, this interrupt should not be
raised.
OUT_UDF_INT
This interrupt indicates that there has been an underflow in the Output buffer. This is not expected to occur if the
DMA is programmed as recommended in this document. If the core does not look at the status bits or does not
keep track of the number of words being read from the buffer, this interrupt can be generated.
Crypto Error Conditions
If a read is attempted from the output buffer when the output data buffer is empty, there will be an underflow error.
The block does not generate a DMA request on the Output buffer channel when the Output buffer is empty.
If the Crypto block is disabled at any stage during the computation, the data output is no longer reliable. The State
Machine will be reset.
9–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Crypto Data Transfer
If a write is attempted to the input buffer when it is full, there will be an overflow error. The block will not generate
a DMA request on the Input buffer channel when the Input buffer is full.
The input and output buffers can be flushed by writing 1 to the corresponding flush bits in the CRYPT_CFG register.
Interrupts can be enabled by writing 1 into the corresponding bits in the CRYPT_INTEN register.
Clearing interrupts is to be done by writing 1 to the respective bits in the CRYPT_STAT register.
Crypto Data Transfer
The input buffer and the output buffer hold 128-bits of data. Being a peripheral on a 32-bit APB bus, the block is
accessed by a 32-bit data bus. Therefore, 4 reads/writes will be needed to empty/fill the output/input buffer.
In SHA mode, the results are updated in the CRYPT_SHAH0.SHAHASH0 to CRYPT_SHAH7.SHAHASH7 registers
and will not be given out in the output buffer. Results for block modes of operation will be streamed out of the
output buffer.
Crypto Data Rate
Depending on the Block Mode and the Key length chosen for the AES Cipher, the rate at which data is processed
changes. The following list describes the computation time involved in different block modes of operation. The
numbers below do not include the buffer read and write time which are controlled by the DMA or Core data rates.
The rates are written for 128/256 key length cases.
• ECB Mode: 40/56 clock cycles
• CBC Mode: 40/56 clock cycles
• CTR Mode: 40/56 clock cycles
• MAC Mode: 40/56 clock cycles
• CCM Mode: 80/102 clock cycles
In block mode of operation, as soon as 128-bits of data (say Block B1) is written into the input buffer, the data is
copied internally for computation and the next 128-bit (say Block B2) of data may be written into the input buffer.
By the time block B2 is written, if computation on the block B1 is not complete, the input buffer will remain full
and further writes will not be permitted. Appropriate interrupts and status registers will be updated. As soon as
block B1 processing is completed the results are moved to the output buffer and computation begins on the B2. If
B1 is not read out of the output buffer by the time processing on B2 is completed, the block stalls. Appropriate
interrupt and status registers will be set.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–7
Crypto Status Bits
Crypto Status Bits
IN_DATA_CNT/OUT_DATA_CNT
These fields hold information about the number of words the Input and Output Buffers contain at that moment.
This information can be used in situations when the Input/output Buffers are not empty/full to know the number
of words which need to be written or read.
HASH_READY
This field indicates that the hash computation on the currently provided data is complete and the block is ready to
receive new data.
HASH_BUSY
This field indicates that hash computation is on-going. When this signal goes low, it is an indication that hash computation is complete and that the user can read out the hash result.
IN_OVF_INT/OUT_UDF_INT
This field indicates that an overflow/underflow event has occurred on the input/output buffer. The status bit is
sticky and can be cleared by writing 1 into the bit field.
Crypto Keys
The user must program the key used for the AES Cipher in the key registers from CRYPT_AESKEY0 to
CRYPT_AESKEY7.
Key Length
The AES Cipher can be used with two different Key Lengths: 128 and 256. The selection is made by setting the
CRYPT_CFG.KEYLEN bit field in the CRYPT_CFG register. The registers CRYPT_AESKEY0 to CRYPT_AESKEY7 are
used to hold the Key to be used in the AES Cipher.
Key Programming
The following list shows how the key (K) used for the AES Cipher operations are constructed from the CRYPT_AESKEYx registers:
CRYPT_AESKEY0 = K[31:0]
CRYPT_AESKEY1 = K[63:32]
CRYPT_AESKEY2 = K[95:64]
CRYPT_AESKEY3 = K[127:96]
CRYPT_AESKEY4 = K[159:128] Used only in case of Key Length 256.
9–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Crypto Power Saver Mode
CRYPT_AESKEY5 = K[191:160] Used only in case of Key Length 256.
CRYPT_AESKEY6 = K[223:192] Used only in case of Key Length 256.
CRYPT_AESKEY7 = K[255:224] Used only in case of Key Length 256.
NOTE: If the programmer changes the configuration bits (for example, encrypt), the key register should be reprogrammed to the desired key value. Not doing so will result in wrong outputs. No warning or error will be flagged.
Crypto Power Saver Mode
Enabling the Power Saver mode in the CRYPT_CFG register enables an automatic clock gating function. This reduces the clocking activity in the block to the barest minimum possible. It is recommended to keep this on because
there is not performance hit by having this enabled.
DATALENGTH
This field is used to specify the length of Payload data. This information is used in the CCM and MAC mode of
operation.
• CCM Mode: Pad the payload data with enough zeros to ensure that the total number of bits is an integral
multiple of 128. Then, program the number of 128-bit DataBlocks in the resulting aligned payload.
CRYPT_DATALEN[15:0] is provided for this purpose.
• MAC Mode: Pad the payload data to ensure that the total number of bits is an integral multiple of 128. Then,
program the number of 128-bit blocks in the aligned payload data. CRYPT_DATALEN[19:0] is provided for this
purpose.
PREFIXLENGTH
This field is used to specify the length of the Associated Data that is only authenticated. This information is used in
the CCM mode of operation.
CCM Mode: Pad the associated data enough zeroes with to ensure that the total number of bits is an integral multiple of 128. Then, program the number of 128-bit blocks in the resulting aligned payload data. Bits [15:0] are provided for this purpose.
CRYPT_NONCEx
This field is to be used to program the nonce to be used in CTR, CBC and CCM Modes of operation. The Nonce
is constructed in the following manner from the CRYPT_NONCE0 to CRYPT_NONCE3 registers:
Nonce[127:0] = {CRYPT_NONCE3[31:0], CRYPT_NONCE2[31:0], CRYPT_NONCE1[31:0], CRYPT_NONCE0[31 :0]}
Different lengths of Nonce are used in different Block modes of operation:
• CTR Mode: This mode uses a 108-Bit long Nonce. In this mode, the encryption operation is performed in the
following format:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–9
Crypto Power Saver Mode
• Ciphertext_Block = Ciph ( {Nonce[107:0], CRYPT_CNTRINIT[19:0] ) xor Payload_Block
• CBC Mode: In this mode the 128-bits of the Nonce are used. The nonce is used as the initialization vector.
• Initialization_Vector = Nonce[127:0]
• CCM Mode: In this mode 112-Bits are used. The nonce is used in the Counter Mode computation. And the
CTR mode data is constructed in the following format:
• Ciphertext_Block = Ciph ( {Nonce[111:0],Counter[15:0]} ) xor Payload_Block
• The results from the SHA hash operations are to be read out of the CRYPT_SHAH0.SHAHASH0 to
CRYPT_SHAH7.SHAHASH7 registers in the following format:
• HASH[255:0] = {CRYPT_SHAH7.SHAHASH7[31:0], CRYPT_SHAH6.SHAHASH6[31:0],
CRYPT_SHAH5.SHAHASH5[31:0], CRYPT_SHAH4.SHAHASH4[31:0], CRYPT_SHAH3.SHAHASH3[31:0],
CRYPT_SHAH2.SHAHASH2[31:0], CRYPT_SHAH1.SHAHASH1[31:0], CRYPT_SHAH0.SHAHASH0[31:0]}
CRYPT_CTRINT
This value is used to initialize the counter generating function. The counter generating function implemented in
this block is an incrementing function, i.e. this function counts up by 1 for every new DataBlock. The initialization
value for the counters can be programmed in the CRYPT_CNTRINIT register.
Counter widths provided for the CTR mode and CCM modes are described below:
• CTR Mode: 20-Bit counter. If counter starts from zero, then 16 GB of data will be processed before the counter overflows. A 20-bit register for initializing the counter is provided.
• CCM Mode: 16-Bit counter. If counter starts from zero, then 1 GB of data will be processed before the counter overflows. A 16-Bit counter initialization register is provided.
• The fixed bit-width of the counter implies that there is a limit to the maximum length of data that can be
encrypted without repeating the same counter values. This is 16 GB of Payload data in CTR Mode and 1 GB
of confidentiality data in CCM mode.
NOTE: When the counter exhausts all unique values it starts all over again from the init value. It is upto the user to
ensure the limit is not crossed if repletion of counter value needs to be avoided.
Crypto Programming Model
The following section details the programming flow description for block modes of operation.
In general, all block modes of operation require the software to perform the following operations:
• Crypto Block Configuration
• Input Data Preparation
• Data Retrieval
9–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Crypto Programming Model
The remaining part of this section lists the different registers that need to be programmed in different modes and
additional information that would be necessary for the programmers.
Enabling CRYPTO
CRYPT_CFG.BLKEN field
Key Programming
1. CRYPT_AESKEY0 to CRYPT_AESKEY7
2. CRYPT_CFG.KEYLEN field
Data Transfer
1. Format: Big_Endian in CRYPT_CFG
2. CRYPT_CFG.INDMAEN/CRYPT_CFG.OUTDMAEN field
Block Mode of Operation
The Crypto block supports the following block modes of operation:
• AES Cipher Encryption and Decryption in ECB Mode
• AES Cipher Encryption and Decryption in CBC Mode
• AES Cipher Encryption and Decryption in CTR Mode
• AES Cipher MAC Generation Mode
• AES Cipher Encryption and Decryption in CCM Mode
• AES Cipher Encryption and Decryption in CCM* Mode
NOTE: Only one mode must be enabled at a time.
Mode Specific Parameters
CTR Mode:
• CRYPT_CNTRINIT
• CRYPT_NONCE0 to CRYPT_NONCE3.
CCM/CCM* Mode:
• DATALENGTH
• PREFIXLENGTH
• CRYPT_CTRINT
• CRYPT_NONCEx
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–11
Crypto Programming Model
CBC Mode:
Initialization Vector in the CRYPT_NONCE0 to CRYPT_NONCE3 registers.
MAC Mode:
CRYPT_DATALEN – This information is used by the block to determine when the MAC results should be provided.
Payload and Associated Data Formatting
In every mode of operation, it is necessary to pad the payload and/or associated data with sufficient number of zeroes so as to make the length a multiple of 128-bits.
Mode Specific Data Format
• CBC Mode: Initialize the CRYPT_NONCE0 to CRYPT_NONCE3 registers with the Initialization Vector.
• MAC Mode: The block always gives out a 128-bit MAC result on the output buffer in the selected data format
(Big_Endian or Litte_Endian). The software needs to ensure that the desired number of bits is used
• Subkey Generation: The values of K1 and K2 needs to be used to generate the final message DataBlock. The
generation of K1, K2, padding the higher bits with ‘b10j (j = number of zeroes that on padding make the final
message DataBlock 128-bit long) and the XOR operation involved in generating the last message DataBlock is
to be handled in software.
• CCM/CCM* Mode: Any formatting function that satisfies the following three properties can be used:
• The first DataBlock uniquely determines the nonce. Note that the nonce will have to be programmed by
the software into the CRYPT_NONCE0 to CRYPT_NONCE3 registers. The block will not pick it up from the
incoming data stream directly.
• The formatted data uniquely determines Payload and Associated Data. The lengths of the Payload and
Associated Data must be programmed into the CRYPT_DATALEN and CRYPT_PREFIXLEN registers respectively.
• The counter must be initialized to a unique value distinct from any other invocation with the same key.
NOTE: CCM* has additional formatting constraints which is left to the software to implement. Once the formatting is complete, the registers CRYPT_DATALEN and CRYPT_PREFIXLEN must contain the following information:
B0
B1, B2, B3... Br
Br+1, Br+2 ...... Bu
Prefix-Len
Data-Len
Figure 9-2: Description for Data Lengths to be Programmed
Programming Flow Description for SHA Operation
1. Configuration
9–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Crypto Programming Model
The different parameters that need to be programmed are as follows:
• DMA for the Input buffer.
• Enable desired SHA mode
• Enable the Crypto block.
2. Data Preparation
Data preparation for the SHA Mode involves the following:
• If needed, append sufficient number of zeroes to the last data block to parse it into (512 64)-bit wide
chunks.
• Pad last 64-bits of the message with the length of the message in bits.
3. Data Retrieval
When all the data operation is completed, the message digest is to be read out of the HASHx registers.
Software Operation in CCM Mode
The following diagrams use the following color code:
Output
Input
Software
Operation
Figure 9-3: Color Codes
The NIST Standard for CCM mode has the following description of the CCM operation.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–13
Crypto Programming Model
CCM Mode Standard (NIST SP800 - 38c) Description
Encrypt - Generate
Formatted
Plaintext
Cipher text
CCM
Enc(MAC)
Decrypt - Validate
Formatted
Cipher text
CCM
Plaintext
MAC
Enc(MAC)
Decryption
==
MAC
VALID/INVALID
Figure 9-4: CCM Mode Standard Description
The hardware implementation for the CCM mode does the following:
CCM Mode Hardware Implementation
Encrypt - Generate
Formatted
Plaintext
CCM
Cipher text
Enc(MAC)
Decrypt - Validate
Formatted
Cipher text
Enc(MAC)
CCM
Plaintext
Enc(MAC)
==
VALID/INVALID
Figure 9-5: CCM Mode Hardware Implementation
9–14
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Crypto Programming Model
Hardware to Standard Equivalence
During Encrypt-Generate
Enc(MAC) = MAC xor AES (Counter 0)
During Decrypt-Validate
Enc(MAC’) = MAC ’ xor AES (Counter 0)
Validation of authenticity is specified in the standard to be the
following check:
VALID = (MAC = = MAC’)
The hardware implementaion flow generatesVALID by the
comparison:
VALID = (Enc(MAC) = = Enc(MAC’))
Clearly, both the comparisons are mathematically equivalent.
Figure 9-6: Hardware to Standard Equivalence
The following are the reasons for the difference in the implementation flow adopted for generation of VALID signal
in Decrypt-Validate phase:
• CMAC mode provides the MAC results and does not check the result against the received reasonable to do the
same in CCM mode.
• This approach is faster: When the system receives data that needs decryption, it receives an encrypted MAC. In
out implementation it is not necessary to decrypt the received MAC.
• The length of the MAC is selectable. This means that if the hardware were to do the comparison internally,
information regarding the length of the MAC output will need to be programmed. This adds an additional
control parameter and also increases the hardware complexity by having a variable length comparator.
• The comparison operation is simple and involves very few operations. It does not require a hardware accelerator.
• TMAC is not expected as an output from CCM operation. Only a VALID or INVALID signal is necessary. So
it does not matter if we give out Enc(MAC) or MAC.
Simultaneous SHA+Block Mode of Operation
SHA and Block Mode operations can be performed simultaneously. The following needs to be kept in mind:
• When CRYPT_CFG.BLKEN in the CRYPT_CFG register is set, the block proceeds with computation of the parameters currently programmed in the design. Therefore it is important to ensure that this bit is set last.
• When both SHA and a block mode are enabled, the data provided in the input buffer is used for both the
operations.
• SHA results will still need to be read out of the CRYPT_SHAH0.SHAHASH0 to CRYPT_SHAH7.SHAHASH7
result registers.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–15
ADuCM302x CRYPT Register Descriptions
ADuCM302x CRYPT Register Descriptions
Cryptogaphic (CRYPT) contains the following registers.
Table 9-3:
ADuCM302x CRYPT Register List
Name
Description
CRYPT_AESKEY0
Key Bits[ 31:0 ]
CRYPT_AESKEY1
Key Bits [ 63:32 ]
CRYPT_AESKEY2
Key Bits [ 95:64 ]
CRYPT_AESKEY3
Key Bits [ 127:96 ]
CRYPT_AESKEY4
Key Bits [ 159:128 ]
CRYPT_AESKEY5
Key Bits [ 191:160 ]
CRYPT_AESKEY6
Key Bits [ 223:192 ]
CRYPT_AESKEY7
Key Bits [ 255:224 ]
CRYPT_CCM_NUM_VALID_BYTES
NUM_VALID_BYTES
CRYPT_CFG
Configuration Register
CRYPT_CNTRINIT
Counter Initialization Vector
CRYPT_DATALEN
Payload Data Length
CRYPT_INBUF
Input Buffer
CRYPT_INTEN
Interrupt Enable Register
CRYPT_NONCE0
Nonce Bits [31:0]
CRYPT_NONCE1
Nonce Bits [63:32]
CRYPT_NONCE2
Nonce Bits [95:64]
CRYPT_NONCE3
Nonce Bits [127:96]
CRYPT_OUTBUF
Output Buffer
CRYPT_PREFIXLEN
Authentication Data Length
CRYPT_SHAH0
SHA Bits [ 31:0 ]
CRYPT_SHAH1
SHA Bits [ 63:32 ]
CRYPT_SHAH2
SHA Bits [ 95:64 ]
CRYPT_SHAH3
SHA Bits [ 127:96 ]
CRYPT_SHAH4
SHA Bits [ 159:128 ]
CRYPT_SHAH5
SHA Bits [ 191:160 ]
CRYPT_SHAH6
SHA Bits [ 223:192]
CRYPT_SHAH7
SHA Bits [ 255:224 ]
CRYPT_SHA_LAST_WORD
SHA Last Word and Valid Bits Information
9–16
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Table 9-3:
ADuCM302x CRYPT Register List (Continued)
Name
Description
CRYPT_STAT
Status Register
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–17
ADuCM302x CRYPT Register Descriptions
Key Bits[ 31:0 ]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [3:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [3:0]
Figure 9-7: CRYPT_AESKEY0 Register Diagram
Table 9-4:
CRYPT_AESKEY0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [3:0].
(RX/W)
9–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Key Bits [ 63:32 ]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [7:4]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [7:4]
Figure 9-8: CRYPT_AESKEY1 Register Diagram
Table 9-5:
CRYPT_AESKEY1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [7:4].
(RX/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–19
ADuCM302x CRYPT Register Descriptions
Key Bits [ 95:64 ]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [11:8]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [11:8]
Figure 9-9: CRYPT_AESKEY2 Register Diagram
Table 9-6:
CRYPT_AESKEY2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [11:8].
(RX/W)
9–20
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Key Bits [ 127:96 ]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [15:12]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [15:12]
Figure 9-10: CRYPT_AESKEY3 Register Diagram
Table 9-7:
CRYPT_AESKEY3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [15:12].
(RX/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–21
ADuCM302x CRYPT Register Descriptions
Key Bits [ 159:128 ]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [3:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [3:0]
Figure 9-11: CRYPT_AESKEY4 Register Diagram
Table 9-8:
CRYPT_AESKEY4 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [3:0].
(RX/W)
9–22
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Key Bits [ 191:160 ]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [7:4]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [7:4]
Figure 9-12: CRYPT_AESKEY5 Register Diagram
Table 9-9:
CRYPT_AESKEY5 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [7:4].
(RX/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–23
ADuCM302x CRYPT Register Descriptions
Key Bits [ 223:192 ]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [11:8]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [11:8]
Figure 9-13: CRYPT_AESKEY6 Register Diagram
Table 9-10:
CRYPT_AESKEY6 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [11:8].
(RX/W)
9–24
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Key Bits [ 255:224 ]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key: Bytes [15:12]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key: Bytes [15:12]
Figure 9-14: CRYPT_AESKEY7 Register Diagram
Table 9-11:
CRYPT_AESKEY7 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Key: Bytes [15:12].
(RX/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–25
ADuCM302x CRYPT Register Descriptions
NUM_VALID_BYTES
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
NUM_VALID_BYTES (R/W)
Number of Valid Bytes in CCM Last Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-15: CRYPT_CCM_NUM_VALID_BYTES Register Diagram
Table 9-12:
CRYPT_CCM_NUM_VALID_BYTES Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3:0 NUM_VALID_BYTES
Number of Valid Bytes in CCM Last Data.
(R/W)
9–26
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Configuration Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
KEYLEN (R/W)
Select Key Length for AES Cipher
BLKEN (R/W)
Enable BIT for the Crypto Block
ENDIAN (R/W)
Endianness
ENCR (R/W)
Encrypt or Decrypt
OUTFLUSH (W)
Output Buffer Flush
INDMAEN (R/W)
Enable DMA for Input Buffer
INFLUSH (W)
Input Buffer Flush
OUTDMAEN (R/W)
Enable DMA for Output Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
REVID (R/W)
Rev ID for Crypto module
ECBEN (R/W)
Enable ECB Mode Operation
SHADATSRC (R/W)
Select Data Input Source to SHA Engine
CTREN (R/W)
Enable CTR Mode Operation
SHAINIT (R0/W)
Restarts SHA Computation
CBCEN (R/W)
Enable CBC Mode Operation
SHA256EN (R/W)
Enable SHA-256 Operation
CCMEN (R/W)
Enable CCM/CCM* Mode Operation
CMACEN (R/W)
Enable CMAC Mode Operation
Figure 9-16: CRYPT_CFG Register Diagram
Table 9-13:
CRYPT_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:28 REVID
Rev ID for Crypto module.
(R/W)
27 SHADATSRC
Select Data Input Source to SHA Engine.
(R/W)
0 SHA takes input from input buffer
1 SHA takes input from output buffer
26 SHAINIT
Restarts SHA Computation.
(R0/W)
25 SHA256EN
Enable SHA-256 Operation.
(R/W)
20 CMACEN
Enable CMAC Mode Operation.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–27
ADuCM302x CRYPT Register Descriptions
Table 9-13:
CRYPT_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
(R/W)
19 CCMEN
Enable CCM/CCM* Mode Operation.
(R/W)
18 CBCEN
Enable CBC Mode Operation.
(R/W)
17 CTREN
Enable CTR Mode Operation.
(R/W)
16 ECBEN
Enable ECB Mode Operation.
(R/W)
9:8 KEYLEN
Select Key Length for AES Cipher.
(R/W)
0 Uses 128-bit long key
1 Reserved Reserved
2 Uses 256-bit long key
3 Reserved Reserved
6 ENDIAN
Endianness.
(R/W)
0 Little Endian Format This bit is applicable only to the
data format in the Input and Output Buffers.
1 Big Endian Format This bit is applicable only to the data format in the Input and Output Buffers.
5 OUTFLUSH
Output Buffer Flush.
(RX/W)
4 INFLUSH
Input Buffer Flush.
(RX/W)
3 OUTDMAEN
Enable DMA for Output Buffer.
(R/W)
0 Disable DMA Requesting for Output Buffer
1 Enable DMA Requesting for Output Buffer
2 INDMAEN
Enable DMA for Input Buffer.
(R/W)
0 Disable DMA Requesting for Input Buffer
1 Enable DMA Requesting for Input Buffer
1 ENCR
(R/W)
Encrypt or Decrypt.
0 Decrypt
1 Encrypt
9–28
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Table 9-13:
CRYPT_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 BLKEN
Enable BIT for the Crypto Block.
(R/W)
0 Enable Crypto Block
1 Disable Crypto Block
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–29
ADuCM302x CRYPT Register Descriptions
Counter Initialization Vector
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Counter Initialization Value
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[19:16] (R/W)
Counter Initialization Value
Figure 9-17: CRYPT_CNTRINIT Register Diagram
Table 9-14:
CRYPT_CNTRINIT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
19:0 VALUE
(R/W)
9–30
Counter Initialization Value.
This is the initialization value used in the internal counter generating functions that
are used in some modes of operation. 1. CCM/CCM* Mode: Only
CRYPT_CNTRINIT.VALUE[15:0] are used in this mode for initializing the counter initialization vector. The higher bits are ignored. 2. CTR Mode:
CRYPT_CNTRINIT.VALUE[19:0] are used in to initialize the counter initialization
vector. When the block is reset, the counters are initialized to the value programmed in
this register.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Payload Data Length
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Length of Payload Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[19:16] (R/W)
Length of Payload Data
Figure 9-18: CRYPT_DATALEN Register Diagram
Table 9-15:
CRYPT_DATALEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
19:0 VALUE
(R/W)
Length of Payload Data.
Program the length of the Payload that needs to be encrypted with the following values: 1. MAC Mode: CRYPT_DATALEN.VALUE[19:0] should be used to program the
number of 128-bit blocks in the Payload .Please refer to HRM for payload data preparation instructions. 2. CCM/CCM* Mode: CRYPT_DATALEN.VALUE[15:0] should
be used to program the number of 128-bit blocks in the Payload. Please refer to the
HRM for description regarding data preparation information.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–31
ADuCM302x CRYPT Register Descriptions
Input Buffer
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Input Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Input Buffer
Figure 9-19: CRYPT_INBUF Register Diagram
Table 9-16:
CRYPT_INBUF Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Input Buffer.
(RX/W)
9–32
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Interrupt Enable Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SHADONEN (R/W)
Enable SHA_Done Interrupt
INRDYEN (R/W)
Enable Input Ready Interrupt
OUTUNDREN (R/W)
Enable the Output Underflow Interrupt
OUTRDYEN (R/W)
Enables the Output Ready Interrupt
INOVREN (R/W)
Enable Input Overflow Interrupt.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-20: CRYPT_INTEN Register Diagram
Table 9-17:
CRYPT_INTEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5 SHADONEN
(R/W)
3 OUTUNDREN
Enable SHA_Done Interrupt.
Indicates that SHA processing is complete
Enable the Output Underflow Interrupt.
(R/W)
2 INOVREN
Enable Input Overflow Interrupt..
(R/W)
1 OUTRDYEN
Enables the Output Ready Interrupt.
(R/W)
0 INRDYEN
Enable Input Ready Interrupt.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–33
ADuCM302x CRYPT Register Descriptions
Nonce Bits [31:0]
Nonce is used in some modes of operations. Depending on the mode, different NONCE lengths will be used. 1.
CTR Mode: This takes a 108-Bit Nonce. This nonce is formed as follows - {CRYPT_NONCE3[11:0],
CRYPT_NONCE2, CRYPT_NONCE1, CRYPT_NONCE0} 2. CBC Mode: This takes a 128-Bit Nonce. This nonce is
formed as follows - {CRYPT_NONCE3, CRYPT_NONCE2, CRYPT_NONCE1, CRYPT_NONCE0} 3. CTR Mode: This
takes a 108-Bit Nonce. This nonce is formed as follows - {CRYPT_NONCE3[15:0], CRYPT_NONCE2,
CRYPT_NONCE1, CRYPT_NONCE0}
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Word 0: Nonce : Bits [31:0]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Word 0: Nonce : Bits [31:0]
Figure 9-21: CRYPT_NONCE0 Register Diagram
Table 9-18:
CRYPT_NONCE0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Word 0: Nonce : Bits [31:0].
(R/W)
9–34
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Nonce Bits [63:32]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Word 1: Nonce : Bits [63:32]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Word 1: Nonce : Bits [63:32]
Figure 9-22: CRYPT_NONCE1 Register Diagram
Table 9-19:
CRYPT_NONCE1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Word 1: Nonce : Bits [63:32].
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–35
ADuCM302x CRYPT Register Descriptions
Nonce Bits [95:64]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Word 2: Nonce : Bits [95:64]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Word 2: Nonce : Bits [95:64]
Figure 9-23: CRYPT_NONCE2 Register Diagram
Table 9-20:
CRYPT_NONCE2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Word 2: Nonce : Bits [95:64].
(R/W)
9–36
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Nonce Bits [127:96]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Word 3: Nonce : Bits [127:96]
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Word 3: Nonce : Bits [127:96]
Figure 9-24: CRYPT_NONCE3 Register Diagram
Table 9-21:
CRYPT_NONCE3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Word 3: Nonce : Bits [127:96].
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–37
ADuCM302x CRYPT Register Descriptions
Output Buffer
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
Output Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R)
Output Buffer
Figure 9-25: CRYPT_OUTBUF Register Diagram
Table 9-22:
CRYPT_OUTBUF Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Output Buffer.
(R/NW)
9–38
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Authentication Data Length
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Length of Associated Data
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-26: CRYPT_PREFIXLEN Register Diagram
Table 9-23:
CRYPT_PREFIXLEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Length of Associated Data.
Program the length of the Associated that needs to be encrypted with the following
values: CCM/CCM* Mode: 20-Bits are provided to program the number of 128-bit
blocks of the Associated Data. The higher 4-bits will be ignored. Please refer to the
CCM/CCM* section of the HRM for description regarding data preparation information.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–39
ADuCM302x CRYPT Register Descriptions
SHA Bits [ 31:0 ]
15 14 13 12 11 10 9
1
1
1
0
0
1
1
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
1
1
1
SHAHASH0[15:0] (R/W)
Word 0: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
1
1
0
1
0
1
0
0
0
0
0
1
0
0
1
SHAHASH0[31:16] (R/W)
Word 0: SHA Hash
Figure 9-27: CRYPT_SHAH0 Register Diagram
Table 9-24:
CRYPT_SHAH0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH0
Word 0: SHA Hash.
(R/W)
9–40
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
SHA Bits [ 63:32 ]
15 14 13 12 11 10 9
1
0
1
0
1
1
1
8
7
6
5
4
3
2
1
0
0
1
0
0
0
0
1
0
1
SHAHASH1[15:0] (R/W)
Word 1: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
1
1
1
0
1
1
0
1
1
0
0
1
1
1
SHAHASH1[31:16] (R/W)
Word 1: SHA Hash
Figure 9-28: CRYPT_SHAH1 Register Diagram
Table 9-25:
CRYPT_SHAH1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH1
Word 1: SHA Hash.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–41
ADuCM302x CRYPT Register Descriptions
SHA Bits [ 95:64 ]
15 14 13 12 11 10 9
1
1
1
1
0
0
1
8
7
6
5
4
3
2
1
0
1
0
1
1
1
0
0
1
0
SHAHASH2[15:0] (R/W)
Word 2: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
1
1
1
1
0
0
0
1
1
0
1
1
1
0
SHAHASH2[31:16] (R/W)
Word 2: SHA Hash
Figure 9-29: CRYPT_SHAH2 Register Diagram
Table 9-26:
CRYPT_SHAH2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH2
Word 2: SHA Hash.
(R/W)
9–42
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
SHA Bits [ 127:96 ]
15 14 13 12 11 10 9
1
1
1
1
0
1
0
8
7
6
5
4
3
2
1
0
1
0
0
1
1
1
0
1
0
SHAHASH3[15:0] (R/W)
Word 3: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
1
0
0
1
0
1
0
1
0
0
1
1
1
1
SHAHASH3[31:16] (R/W)
Word 3: SHA Hash
Figure 9-30: CRYPT_SHAH3 Register Diagram
Table 9-27:
CRYPT_SHAH3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH3
Word 3: SHA Hash.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–43
ADuCM302x CRYPT Register Descriptions
SHA Bits [ 159:128 ]
15 14 13 12 11 10 9
0
1
0
1
0
0
1
8
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
1
SHAHASH4[15:0] (R/W)
Word 4: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
1
0
1
0
0
0
1
0
0
0
0
1
1
1
0
SHAHASH4[31:16] (R/W)
Word 4: SHA Hash
Figure 9-31: CRYPT_SHAH4 Register Diagram
Table 9-28:
CRYPT_SHAH4 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH4
Word 4: SHA Hash.
(R/W)
9–44
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
SHA Bits [ 191:160 ]
15 14 13 12 11 10 9
0
1
1
0
1
0
0
8
7
6
5
4
3
2
1
0
0
1
0
0
0
1
1
0
0
SHAHASH5[15:0] (R/W)
Word 5: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
0
1
1
0
1
1
0
0
0
0
0
1
0
1
SHAHASH5[31:16] (R/W)
Word 5: SHA Hash
Figure 9-32: CRYPT_SHAH5 Register Diagram
Table 9-29:
CRYPT_SHAH5 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH5
Word 5: SHA Hash.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–45
ADuCM302x CRYPT Register Descriptions
SHA Bits [ 223:192]
15 14 13 12 11 10 9
1
1
0
1
1
0
0
8
7
6
5
4
3
2
1
0
1
1
0
1
0
1
0
1
1
SHAHASH6[15:0] (R/W)
Word 6: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
1
1
1
1
1
1
0
0
0
0
0
1
1
SHAHASH6[31:16] (R/W)
Word 6: SHA Hash
Figure 9-33: CRYPT_SHAH6 Register Diagram
Table 9-30:
CRYPT_SHAH6 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH6
Word 6: SHA Hash.
(R/W)
9–46
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
SHA Bits [ 255:224 ]
15 14 13 12 11 10 9
1
1
0
0
1
1
0
8
7
6
5
4
3
2
1
0
1
0
0
0
1
1
0
0
1
SHAHASH7[15:0] (R/W)
Word 7: SHA Hash
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
1
0
1
1
0
1
1
1
1
1
0
0
0
0
0
SHAHASH7[31:16] (R/W)
Word 7: SHA Hash
Figure 9-34: CRYPT_SHAH7 Register Diagram
Table 9-31:
CRYPT_SHAH7 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 SHAHASH7
Word 7: SHA Hash.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–47
ADuCM302x CRYPT Register Descriptions
SHA Last Word and Valid Bits Information
This register is to be written before writing the last word to SHA input register. This is to inform the SHA engine
that last word is about to be written by writing the SHA_LAST_WORD[0]. Also the no. of valid bits is to be programmed in SHA_LAST_WORD[5:1]
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
O_Bits_Valid (R/W)
Bits Valid in SHA Last Word Input
O_Last_Word (R/W)
Last SHA Input Word
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-35: CRYPT_SHA_LAST_WORD Register Diagram
Table 9-32:
CRYPT_SHA_LAST_WORD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5:1 O_BITS_VALID
(R/W)
0 O_LAST_WORD
(R/W)
9–48
Bits Valid in SHA Last Word Input.
These will indicate the number of valid bits in the last input word to SHA. This
should autoclear when SHA Done is set
Last SHA Input Word.
This should be set to indicate that last word is about to be written to the SHA engine.
This should autoclear when SHA_DONE is set
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRYPT Register Descriptions
Status Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
OUTWORDS (R)
Number of Words in the Output Buffer
INRDY (R)
Input Buffer Status
INWORDS (R)
Number of Words in the Input Buffer
OUTRDY (R)
Output Data Ready
SHABUSY (R)
SHA Busy. in Computation
INOVR (R/W1C)
Overflow in the INPUT Buffer.
SHADONE (R)
SHA Computation Complete
OUTUNDR (R/W1C)
Underflow Interrupt in the Output
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 9-36: CRYPT_STAT Register Diagram
Table 9-33:
CRYPT_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
12:10 OUTWORDS
Number of Words in the Output Buffer.
(R/NW)
9:7 INWORDS
(R/NW)
6 SHABUSY
(R/NW)
5 SHADONE
(R/NW)
Number of Words in the Input Buffer.
Number of words in the Input Buffer
SHA Busy. in Computation.
Indicates that hash computation is complete for current data. When hash computation
is complete, the current value of the hash may be read out or new data may be written
into the input buffer to proceed with further computation.
SHA Computation Complete.
Indicates that computation is ongoing for recent data. While this is set, values in the
CRYPT_SHAH0 - CRYPT_SHAH7 registers are invalid.
3 OUTUNDR
Underflow Interrupt in the Output.
(R/W1C)
2 INOVR
Overflow in the INPUT Buffer..
(R/W1C)
1 OUTRDY
(R/NW)
0 INRDY
Output Data Ready.
Output Data ready to be read
Input Buffer Status.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
9–49
ADuCM302x CRYPT Register Descriptions
Table 9-33:
CRYPT_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
Input Buffer Requires more data before computation can begin. Remains set till the
Buffer is filled.
9–50
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Serial Peripheral Interface (SPI)
10 Serial Peripheral Interface (SPI)
The Serial Peripheral Interface (SPI) is an industry-standard synchronous serial link that supports communication
with multiple SPI-compatible devices. The baseline SPI peripheral is a synchronous, four-wire interface consisting of
two data pins, one device select pin, and a gated clock pin. The two data pins allow full-duplex operation to other
SPI-compatible devices. Enhanced modes of operation such as flow control, fast mode, and read-command mode
(half-duplex operation) are also supported. In addition, a DMA mode allows for transferring several words with
minimal CPU interaction.
With a range of configurable options, the SPI ports provide a glueless hardware interface with other SPI-compatible
devices in master mode, slave mode, and multislave environments. The SPI peripheral includes programmable baud
rates, clock phase, and clock polarity. The peripheral can operate in a multislave environment by interfacing with
several other devices, acting as either a master device or a slave device. In a multislave environment, the SPI peripheral uses open-drain outputs to avoid data bus contention. The flow control features enable slow slave devices to
interface with fast master devices by providing an SPI ready pin which flexibly controls the transfers.
SPI Features
The SPI module supports the following features:
• Serial clock phase mode and serial clock polarity mode
• Loopback mode
• Continuous transfer mode
• Wired-OR output mode
• Read-command mode for half-duplex operation
• Flow control
• Multiple CS line
• CS software override
• Support for 3-pin SPI Master or Slave mode
• LSB first transfer option
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–1
SPI Functional Description
• Interrupt mode: interrupt after 1, 2, 3, 4, 5, 6, 7, or 8 bytes
SPI Functional Description
During an SPI transfer, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). A
serial clock line synchronizes shifting and sampling of the information on the two serial data lines. During a data
transfer, one SPI system acts as the link master which controls the data flow, while the other system acts as the slave,
which has data shifted into and out of it by the master. Different devices can take turn being masters, and one master may simultaneously shift data into multiple slaves (broad-cast mode).
However, only one slave may drive its output to write data back to the master at any given time. This must be enforced in the broad-cast mode, where several slaves can be selected to receive data from the master, but only one
slave can be enabled to send data back to the master.
The SPI port can be configured for master or slave operation and consists of four pins: MISO, MOSI, SCLK, and
CS. Note that the GPIOs used for SPI communication must be configured in SPI mode before enabling the SPI
peripheral. The peripheral should be enabled by setting the SPI_CTL.SPIEN bit. If not used, the peripheral must
be turned off by clearing this bit.
ADuCM302x SPI Register List
Table 10-1:
ADuCM302x SPI Register List
Name
Description
SPI_CNT
Transfer byte count
SPI_CS_CTL
Chip-Select control for multi-slave connections
SPI_CS_OVERRIDE
Chip-Select Override
SPI_CTL
SPI configuration 1
SPI_DIV
SPI baud rate selection
SPI_DMA
SPI DMA enable
SPI_FIFO_STAT
FIFO Status
SPI_FLOW_CTL
Flow Control
SPI_IEN
SPI configuration 2
SPI_RD_CTL
Read Control
SPI_RX
Receive
SPI_STAT
Status
SPI_TX
Transmit
SPI_WAIT_TMR
Wait timer for flow control
10–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPI Functional Description
MISO (Master In, Slave Out) Pin
The MISO pin is configured as an input line in master mode and an output line in slave mode. The MISO line on
the master (data in) should be connected to the MISO line in the slave device (data out). The data is transferred as
byte wide (8-bit) serial data.
MOSI (Master Out, Slave In) Pin
The MOSI pin is configured as an output line in master mode and an input line in slave mode. The MOSI line on
the master (data out) should be connected to the MOSI line in the slave device (data in). The data is transferred as
byte wide (8-bit) serial data.
SCLK (Serial Clock I/O) Pin
The master serial clock (SCLK) synchronizes the data being transmitted and received during the MOSI SCLK period. Therefore, a byte is transmitted/received after eight SCLK periods. The SCLK pin is configured as an output in
master mode and as an input in slave mode.
In the master mode, polarity and phase of the clock are controlled by the SPI_CTL register, and the bit rate is defined in the SPI_DIV register as follows:
fSERIALCLOCK =
PCLK
2 x (1+ SPIx_DIV)
The maximum data rate is 13 Mbps for a maximum PCLK frequency of 26 MHz.
In the slave mode, the SPI_CTL register must be configured with the phase and polarity of the expected input
clock. The slave accepts data from an external master up to 13 Mbps.
In both master and slave modes, data is transmitted on one edge of the SCLK signal and sampled on the other.
Therefore, the polarity and phase are configured the same for the master and slave devices.
Chip Select (CS I/O) Pin
In SPI slave mode, a transfer is initiated by the assertion of CS, which is an active low input signal. The SPI port
then transmits and receives 8-bit data until the transfer is concluded by deassertion of CS. In slave mode, CS is
always an input.
In SPI master mode, the CS is an active low output signal. It asserts itself automatically at the beginning of a transfer
and deasserts itself upon completion.
In a multi-slave environment, we would support up to 4 different slaves. The SPI master can be configured to drive
up to four CS lines (CS0, CS1, CS2, and CS3) using the SPI_CS_CTL register. Multiple CS lines can be driven
simultaneously for a broadcast access. There are also override fields to enable software driving of 0 or 1 on the active
CS line(s), which may be required for some special use cases. All other SPI pins are shared across by the slaves.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–3
SPI Functional Description
SPI Block Diagram
The figure below illustrates the SPI block diagram.
SPI
Flow Control
APB
Registers
16-bit
APB
State Machine
SCLK
Generation
SPI
(3 or 4 pins)
External
Interface
Tx/Rx FIFO
IRQ,
DMA - Req
IRQ/DMA
Generation
Figure 10-1: SPI Block Diagram
SPI Operating Modes
The SPI supports the following features.
Wired-OR Mode (WOM)
To prevent contention when the SPI is used in multislave system, the data output pins, MOSI and MISO, can be
configured to behave as open-circuit drivers. An external pull-up resistor is required when this feature is selected.
The SPI_CTL.WOM bit in the control register controls the pad enable outputs for the data lines.
General Instructions
1. SPI module operates on PCLK. So, if PCLK is stopped, this block will not work.
2. Whenever SPI configuration needs to be changed, ensure that the CS is de-asserted. This will avoid any abrupt
breaks in the SPI transfers. If the configuration changes while SPI transfer is actively going on, the behavior of
the peripheral is nondeterministic.
10–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPI Operating Modes
3. While changing configurations, program SPI_CNT register only after changing SPI_CTL, SPI_IEN registers.
Else, transfers may get started even before the configuration is changed.
SPI and Power-down Mode
In master mode, before entering power-down mode, the user should ensure that the transfers are completed by
checking the appropriate interrupts/status bits. The SPI block should then be disabled by clearing the
SPI_CTL.SPIEN bit. Only then, the power-down entry would be clean.
In slave mode, in either mode of operation (interrupt driven or DMA), the CS line level should be checked using
the SPI_STAT.CS field of SPI_STAT register to ensure that the SPI is not communicating. The SPI block should
be disabled only when the CS line is high.
While being powered-down, the following fields are retained:
• All bit-fields of SPI_CTL register except SPI_CTL.SPIEN. The SPI_CTL.SPIEN bit would be reset to 0 on
power-up and this would allow a clean start of the design at wakeup.
• SPI_IEN.IRQMODE bit-field
• SPI_DIV.VALUE bit-field
• SPI_RD_CTL.THREEPIN bit-field
• SPI_FLOW_CTL.RDYPOL bit-field
All other bit-fields are not retained. Therefore, they are all reset on power-up. On exiting the power-down mode, the
software should reprogram all the non-retained registers as required. Then, the SPI block must be re-enabled by setting the SPI_CTL.SPIEN bit.
SPIH vs SPI0/SPI1
From an SPI programming and users model perspective, SPIH, SPI0, and SPI1 are identical. The main difference
between SPIH and SPI0/1 is the internal bus interface, which they are connected to. SPIH is connected to a higher
performance Advanced Peripheral Bus (APB) which is always clocked at the higher system clock rate (HCLK) and
contains fewer modules requiring arbitration. SPI0 and SPI1 are connected to the main Advanced Peripheral Bus
(APB) which selectively can be clocked at a lower rate (PCLK) and whose latency is more uncertain due to a greater
number of modules requiring arbitration. This means that under higher data rates, SPIH can move data more efficiently and with lower latency. SPIH is recommended for use with high data rate peripherals.
Interfacing with SPI Slaves on Converters/Flash
Though the SPI transfers are usually full-duplex, in many cases, the slave works on a protocol which has a Command+Address+Read/Write Data. The write command is always unidirectional. However, the read command needs
a Tx transfer followed by an Rx transfer in a single CS frame. An example protocol is shown below.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–5
SPI Operating Modes
Figure 10-2: SPI Register Read
To support transfers like the above one, which resembles a half-duplex operation, SPI_RD_CTL.CMDEN bit should
be set. The number of bytes to be transmitted should be programmed in SPI_RD_CTL.TXBYTES field (which is 1
for the above example). The number of bytes to be received (after completing the Tx) would be specified by the
SPI_CNT.VALUE field of SPI_CNT register. In this case, SPI_CNT.VALUE should be 1.
There is also a SPI_RD_CTL.OVERLAP bit which controls if the bytes received while transmitting the command
+address bytes should be kept or ignored. If this bit is set, then SPI_CNT.VALUE would refer to the total number of
bytes in the entire frame. Some SPI read examples are given below.
Read Command with TXBYTES = 1, CNT = 4, OVERLAP = 0
CSn
MOSI
X/Z
MISO
X
Tx0
Tx1
X
X/Z
X
Rx0
Rx1
Rx2
Rx3
X
SCLK
Read Command with TXBYTES = 1, CNT = 6, OVERLAP = 1
CSn
MOSI
X/Z
Tx0
Tx1
MISO
X
Rx0
Rx1
X/Z
X
Rx2
Rx3
Rx4
Rx5
X
SCLK
Figure 10-3: SPI Read Examples
Pseudo-code Example for Read Command Mode
SPI0_DIV = 0x0001
SPI0_CTL = 0x0883
SPI0_CNT = 0x0040
SPI0_DMA = 0x0005
SPI0_RD_CTL = 0x000D
10–6
//SPI serial clk freq = ¼ of PCLK freq
//Enable SPI in master mode, ZEN=1,
//Continuous mode, TIM=0
//64 bytes to be Rxed
//Enable DMA mode and Rx-DMA request
//TXBYTES=3, CMDEN=1, Write 4 Tx bytes
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPI Operating Modes
//in two 16-bit writes (DMA mode)
SPI0_TX = 0xB6A5
SPI0_TX = 0xD8C7
read_data = SPI0_RX
//Do a dummy read of the Rx FIFO to
//initiate SPI transfers
In this case, only 4 bytes are transmitted as TXBYTES is 3. However, zeroes are sent on MOSI for the next 64 bytes
that are being received. In total, 4 bytes are transmitted and 64 bytes are received in a non-overlapping mode.
Flow Control
Several converters use a flow-control mechanism to match the required data/sample rate. The SPI master supports
the following types of flow-control:
1. Using a 16-bit timer clocked at the serial clock rate to introduce wait-states while reading data. The master
waits until the timer ends and then reads ‘SPI_FLOW_CTL.RDBURSTSZ+1’ number of bytes. It goes back to
wait state and restarts the timer. This continues until SPI_CNT.VALUE number of bytes are received.
2. Using a separate RDY pin which is connected through one of the GPIOs. The master waits until it sees an
active level in this pin. Once it detects the transition, it reads SPI_FLOW_CTL.RDBURSTSZ+1 number of
bytes and then goes back to wait state until another active level is detected. This continues until
SPI_CNT.VALUE number of bytes are received.
3. Using the MISO pin. In this mode, the master waits for an active level on the MISO pin. Once it detects the
transition, it reads SPI_FLOW_CTL.RDBURSTSZ+1 number of bytes and then goes back to wait state until
another active level is detected. This continues until SPI_CNT.VALUE number of bytes are received.
In all the above cases, SPI_CNT.VALUE needs to be an integer multiple of SPI_FLOW_CTL.RDBURSTSZ+1. Some
example flow-controlled transfers are shown below.
Read Command with TXBYTES = 1, CNT = 3, RDBURSTSZ = 0, RDY_POL = 1 (using MISO pin)
CSn
MOSI
X/Z
MISO
x
Tx1
Tx0
X/Z
x
Rx1
Rx0
Rx3
X
SCLK
Read Command with CPHA = 1, CPOL = 0, TXBYTES = 0, CNT = 4, RDBURSTSZ = 1, WAIT_TMR = 10 (using Timer)
CSn
MOSI
X/Z
MISO
X
Tx0
X/Z
X
Rx0
Rx1
X
Rx2
Rx3
X
SCLK
<- 10 SCLK Cycles ->
<- 10 SCLK Cycles ->
Figure 10-4: Flow-controlled Transfer Examples
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–7
SPI Operating Modes
NOTE: While stalling the SCLK output for flow-control or FIFO data/space unavailability, the last SCLK edge is
always a sampling edge. This is to avoid a driving edge before the stall period. That way, the slave would have an
SCLK driving edge to proceed with, after the stall period.
Though the SCLK signal idles LOW for a SPI_CTL.CPHA =0 and idles HIGH for a SPI_CTL.CPOL =1,
SPI_CTL.CPHA determines the sequence of sampling and driving edges. Therefore, for a SPI_CTL.CPHA =1, the
SCLK signal is stalled at the same level as the idle level. But, if SPI_CTL.CPHA = 0, the SCLK is stalled at the
opposite level to the idle level. At the end of a transfer (when CS is deasserted), the SCLK is always idled as per
SPI_CTL.CPOL. The following table explains this.
Table 10-2:
Flow-control
CPHA
CPOL
SCLK Idle level
SCLK Stalled level
0
0
0
1
0
1
1
0
1
0
0
0
1
1
1
1
Figure 10-5: Sample Transfer
Three Pin Mode
SPI can be used in a 3-pin mode where the data transmission/reception occurs over a single bi-directional line. The
SPI master supports this for read command mode, where the MOSI line is used for transmission of 'Command +
address' bytes and the same line is used for receiving the read data. To enable this, SPI_RD_CTL.THREEPIN and
SPI_RD_CTL.CMDEN fields of SPI_RD_CTL register should be set. Inherently, there is a half SCLK cycle between
the last sampling edge of transmit phase and the first driving edge of receive phase. However, if the slave needs a
larger turn-around time, then it should enable timer based flow-control and program the SPI_WAIT_TMR.VALUE
as required. An example 3-pin SPI transfer is shown below.
Read Command with 3-pin SPI, TXBYTES = 0, CNT = 2. RDBURSTSZ = 0, WAIT_TMR = 1 (using Timer)
CSn
MOSI
X/Z
Rx1 (driven by Slave)
Rx0 (driven by Slave)
Tx0 (driven by Master)
X/Z
SCLK
1 SCLK
1 SCLK
Figure 10-6: 3-Pin SPI Transfer
10–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPI Data Transfer
SPI Data Transfer
In master mode, the transfer and interrupt mode bit (SPI_CTL.TIM) determines the manner in which an SPI serial
transfer is initiated. If the SPI_CTL.TIM bit is set, a serial transfer is initiated after a write to the Tx FIFO occurs. If
the SPI_CTL.TIM bit is cleared, a serial transfer is initiated after a read of the Rx FIFO. The read must be done
while the SPI interface is idle. A read done during an active transfer will not initiate another transfer.
For any setting of the master mode enable (SPI_CTL.MASEN) and SPI_CTL.TIM bits, the SPI will simultaneously
receive and transmit data (provided SPI_RD_CTL.CMDEN bit is 0). Therefore, during data transmission, the SPI is
also receiving data and filling up the Rx FIFO. If the data is not read from the Rx FIFO, the overflow interrupt will
occur once the FIFO starts to overflow. If the user does not want to read the Rx data or receive overflow interrupts,
the Rx FIFO flush enable (SPI_CTL.RFLUSH) bit can be set, and the receive data will not be saved to the Rx FIFO.
Else, if the user wants to read some of the Rx data but doesnt care for an overflow condition, then this interrupt can
be disabled by clearing the SPI_IEN.RXOVR bit. Similarly, when the user only wants to receive data and does not
want to write data to the Tx FIFO, the Tx FIFO flush enable (SPI_CTL.TFLUSH) bit can be set to avoid getting
underflow interrupts from the Tx FIFO. Alternatively, if the user wants to send the FIFO data, but, does not want
underflow interrupts, then SPI_IEN.TXUNDR bit must be cleared.
Tx Initiated Transfer
For transfers initiated by a write to the Tx FIFO, the SPI will start transmitting as soon as the first byte is written to
the FIFO. The SPI transfer of the first byte happens immediately.
If the Continuous transfer enable bit (SPI_CTL.CON) is set, the transfer will continue until it is complete. This
completion is either the end of SPI_CNT.VALUE number of bytes (if SPI_CNT.VALUE > 0) or when no valid data
is available in the Tx FIFO (if SPI_CNT.VALUE = 0). Chip Select will remain asserted for the duration of the complete transfer. If SPI_CNT.FRAMECONT is cleared and SPI_CNT.VALUE > 0, the transfer will stop when all the
SPI_CNT.VALUE bytes have been transferred. If SPI_CNT.FRAMECONT is set, a new frame will be started after
every SPI_CNT.VALUE number of bytes. So, always multiples of SPI_CNT.VALUE bytes will be transferred in this
case. If there is no data/space in FIFO, the transfer will stall until it is available. Conversely, the transfer will continue while there is valid data in the FIFO.
If SPI_CTL.CON is cleared, each transfer consists of a single 8-bit serial transfer. If valid data exists in the Tx FIFO,
a new transfer is initiated after a stall period, where Chip Select is deasserted.
Rx Initiated Transfer
Transfers initiated by a read of the Rx FIFO depend on the number of bytes to be received in the FIFO. If
SPI_IEN.IRQMODE is set to 7 and a read to the Rx FIFO occurs, the SPI master initiates an 8-byte transfer. If
continuous mode is set (SPI_CTL.CON), the 8 bytes happen continuously with no deassertion of Chip Select between bytes. If continuous mode is not set, the 8 bytes will happen with stall periods between transfers, where the
Chip Select will be deasserted. However, in continuous mode, if SPI_CNT.VALUE > 0, then CS will be asserted for
the entire frame duration. SPI will introduce stall periods by not clocking SCL until FIFO space is available.
If SPI_IEN.IRQMODEis set to 6, then a read of the Rx FIFO will initiate a 7 byte transfer similar to above. If
SPI_IEN.IRQMODE is set to 1, then a read of the Rx FIFO will initiate a 2 byte transfer. Finally, a read of the FIFO
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–9
SPI Data Transfer
with SPI_IEN.IRQMODE set to 0 will initiate a single byte transfer. A read of the Rx FIFO while the SPI is receiving data will not initiate another transfer after the present transfer is complete. In continuous mode, if
SPI_CNT.VALUE> 0 and SPI_CNT.FRAMECONT = 1, read of Rx-FIFO at the end of an SPI frame (to get the last
set of bytes rxed) will always initiate a new SPI frame. Therefore, to stop SPI transfers at any given frame,
SPI_CNT.FRAMECONT bit should be cleared before reading the final set of Rx-bytes.
Full-duplex transfer with CON = 0, CNT = 4
CSn
MOSI
X/Z
Tx0
X/Z
Tx1
X/Z
Tx2
X/Z
Tx3
X/Z
MISO
X
Rx0
X
Rx1
X
Rx2
X
Rx3
X
SCLK
Rx-only transfer with CON = 1, CNT = 6, FRAMECONT = 0
CSn
MOSI
X/Z
MISO
X
X
Rx0
Rx1
X/Z
Rx2
Rx3
Rx5
Rx4
X
SCLK
Tx-only transfer with CON = 1, CNT = 3, FRAMECONT = 1
CSn
MOSI
X/Z
MISO
X
Tx0
Tx1
Tx2
X/Z
Tx3
Tx4
Tx5
X
X/Z
X
SCLK
Figure 10-7: SPI Transfers
Transfers in Slave Mode
In slave mode, a transfer is initiated by the assertion of the Chip Select of the device.
Though the master can support upto 4 CS output lines, only one CS input is used in slave mode.
The device as a slave will transmit and receive 8-bit data until the transfer is concluded by the deassertion of Chip
Select.
The SPI transfer protocol diagrams below illustrate the data transfer protocol for the SPI, and the effects of
SPI_CTL.CPHA and SPI_CTL.CPOL bits in the control register on that protocol, as indicated by T1, T2, and T3.
NOTE: Chip Select must not be tied to the ground.
10–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPI Data Transfer
Clock Cycle
Number
1
2
3
4
5
6
7
8
SPI Clock
SPI_CTL.CPOL=0
SPI Clock
SPI_CTL.CPOL=1
MOSI
(From
master)
MISO
(From Slave)
XX
XX
msb
6
5
4
3
2
1
1sb
xx
msb
6
5
4
3
2
1
1sb
xx
CS
T1
T3
T2
Figure 10-8: SPI Transfer Protocol CPHA = 0
Clock Cycle
Number
1
2
3
4
5
6
7
8
SPI Clock
SPI_CTL.CPOL=0
SPI Clock
SPI_CTL.CPOL=1
MOSI
(From
master)
MISO
(From Slave)
XX
XX
msb
6
5
4
3
2
1
1sb
xx
msb
6
5
4
3
2
1
1sb
xx
CS
T1
T2
T3
Figure 10-9: SPI Transfer Protocol CPHA = 1
SPI Data Underflow and Overflow
If the Tx transmit zeroes underflow mode bit (SPI_CTL.ZEN) is cleared, the last stale byte is shifted out when a
transfer is initiated with no valid data in the FIFO. If SPI_CTL.ZEN is set, zeros are transmitted when a transfer is
initiated with no valid data in the FIFO.
If the Rx overflow overwrite enable bit (SPI_CTL.RXOF) is set, the valid data in the Rx FIFO is overwritten by the
new serial byte received when there is no space left in the FIFO. If SPI_CTL.RXOF is cleared, the new serial byte
received is discarded when there is no space left in the FIFO.
When valid data is being overwritten in the Rx FIFO, the oldest byte is overwritten first followed by the next oldest
byte and so on.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–11
SPI Interrupts and Exceptions
SPI Interrupts and Exceptions
There is one interrupt line per SPI and eleven sources of interrupts. SPI_STAT[0] reflects the state of the interrupt
line, and {SPI_STAT[15:12], SPI_STAT[7:1]} the state of the eleven sources.
The SPI generates either Transmit Interrupt Requests (TIRQ) or Receive Interrupt Request (RIRQ). Both interrupts
cannot be enabled at the same time. The appropriate interrupt is enabled using the SPI_CTL.TIM bit in SPI_CTL
register. If SPI_CTL.TIM = 1, TIRQ is enabled. If SPI_CTL.TIM= 0, RIRQ is enabled.
All interrupts are sticky and are cleared only when the appropriate interrupt bits in SPI_STAT register are written
with a 1. The interrupt line from the device gets cleared only after all the interrupt sources are cleared.
Tx Interrupt
If SPI_CTL.TIM is set, the Tx FIFO status causes the interrupt. SPI_IEN.IRQMODE bits control when the interrupt will occur. When SPI_IEN.IRQMODE bits are set to:
000: An interrupt is generated after each byte that is transmitted. The interrupt occurs when the byte is read from
the FIFO and written to the shift register.
001: An interrupt is generated after every 2 bytes that are transmitted.
...
110: An interrupt occurs after every seventh byte that is transmitted.
111: An interrupt occurs after every eighth byte that is transmitted.
The interrupts are generated depending on the number of bytes transmitted and not on the number of bytes in the
FIFO. This is unlike the Rx interrupt which depends on the number of bytes in the Rx FIFO and not the number
of bytes received.
The status of this interrupt can be read by reading the TXIRQ status bit. The interrupt is disabled if Tx FIFO flush
enable (TFLUSH) is high.
Note that, a write to the control register, SPI_CTL, will reset the transmitted byte counter back to zero. For example, in a case where SPI_IEN.IRQMODE is set to 0x3 and after three bytes have been transmitted, SPI_CTL is written to, and then the Tx interrupt will not occur until another 4 bytes have been transmitted.
Rx Interrupt
If SPI_CTL.TIM is cleared, the Rx FIFO status causes the interrupt. Again, SPI_IEN.IRQMODE controls when the
interrupt will occur. The status of this interrupt can be read by reading the SPI_STAT.RXIRQ status bit.
Interrupts are only generated when data is written to the FIFO. For example, if SPI_IEN.IRQMODE is set to 0x0,
an interrupt is generated after the first byte is received. If the interrupt was cleared by a write-1 and the data byte
was not read from the Rx FIFO, the interrupt will not be regenerated. Another interrupt will only be generated
when another byte is received into the FIFO.
10–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPI Interrupts and Exceptions
The interrupt depends on the number of valid bytes in FIFO when the SPI is receiving data. It does not depend on
the number of bytes received over the SPI.
The interrupt is disabled if SPI_CTL.RFLUSH is left high.
Underflow/Overflow Interrupts
When a transfer starts with no data in the TX FIFO, the SPI_STAT.TXUNDR bit of the Status register gets set to
indicate an underflow condition. This will cause an interrupt if SPI_STAT.TXUNDR is set. This interrupt will occur
irrespective of what SPI_CTL.TIM bit is set to. This interrupt is disabled if SPI_CTL.TFLUSH bit is set.
If data is received when the RX FIFO is already full, this will cause the SPI_STAT.RXOVR bit of the Status register
to go high indicating an overflow condition. This will cause an interrupt if SPI_IEN.RXOVR is set. This interrupt
will occur irrespective of what SPI_CTL.TIM bit is set to. This interrupt is disabled if SPI_CTL.RFLUSH bit is set.
The Rx and Tx interrupts are cleared if the relevant flush bits are asserted or if the SPI is disabled. Otherwise, the
interrupts will stay active even if the SPI is reconfigured.
SPI Programming Model
The following section provides the SPI DMA details.
SPI DMA
Two DMA channels are dedicated to SPI, transmit and receive. The two SPI DMA channels should be configured
in the DMA controller.
It is possible to enable DMA request on 1 or 2 channels at the same time, by setting the DMA request bits for
receive or transmit in the SPI_DMA register. If only the DMA transmit request (SPI_DMA.TXEN) is enabled, the Rx
FIFO will overflow during SPI transfer unless received data is read by user code, and an overflow interrupt will be
generated. To avoid generating overflow interrupts, the Rx FIFO flush bit (SPI_CTL.RFLUSH) should be set, or the
SPI_IEN.RXOVR bit should be cleared, or the SPI interrupt be disabled in the NVIC of the core. If only the DMA
receive request (SPI_DMA.RXEN) is enabled, the Tx FIFO will underflow. Again, to avoid underflow interrupt, the
SPI_IEN.TXUNDR bit should be cleared or the SPI interrupt should be disabled in the NVIC.
The SPI Tx and Rx interrupts are not generated when DMA is used. SPI_IEN.IRQMODE is not used in transmit
mode and should be set to 3b000 in receive mode.
The DMA bit (SPI_DMA.TXEN) controls the start of a DMA transfer. DMA requests are only generated when
SPI_DMA.EN = 1. At the end of a DMA transfer, that is, when receiving a DMA SPI transfer interrupt, this bit
needs to be cleared to prevent extra DMA requests to the µDMA controller. The data still present in the Tx FIFO
will be transmitted if in Tx mode.
All DMA data transfers are 16-bit transfers, and the DMA should be programmed accordingly. For example, if 16
bytes of data are to be transferred over the SPI, the DMA should be programmed to perform eight half-word (16bit) transfers. If 17 bytes are to be transferred, nine half-word transfers would be required, the additional byte is
discarded. Data errors will occur if the DMA transfers are programmed as byte-wide transfers.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–13
SPI Programming Model
In DMA mode, the Tx/Rx FIFOs are 2 bytes wide. Bits[7:0] are first accessed by the SPI followed by the bits[15:8].
This is irrespective of count or SPI_CTL.LSB settings. For example, if SPI_CNT.VALUE = 3, then the order of
transmission/reception would be as follows. (Byte-3 is ignored).
Byte-1
Byte-0
Byte-3
Byte-2
NOTE: The SPI_CTL.LSB bit does not affect the FIFO access order in the DMA mode. It only affects how each
byte is transferred over SPI.
DMA Master Transmit Configuration
The DMA SPI Tx channel should be configured. The NVIC should be configured to enable DMA Tx master interrupt.
The SPI block must be configured as follows:
SPI_DIV = SPI_SERIAL_FREQ; //configures serial clock frequency.
SPI_CTL = 0x1043;
//enables SPI in master mode and transmit mode, Rx FIFO
//flush enabled.
SPI_CNT.VALUE = NUM_BYTES_TO transfer; //sets the number of bytes to transfer.
SPI_DMA = 0x1;
//(optional) enables FIFO to accept 16-bit
//core data writes.
SPI_TX = 0xXXXX;
//(optional) up to four 16-bit core writes can be performed
//to preload FIFO.
SPI_DMA = 0x3;
//enable DMA mode, enable Tx DMA request.
All DMA transfers are expected to be 16-bit transfers. When all data present in the DMA buffer are transmitted, the
DMA generates an interrupt. User code should disable DMA request. Data will still be in the Tx FIFO as the DMA
request is generated each time there is free space in the Tx FIFO, to keep the FIFO always full.
DMA Master Receive Configuration
The SPI_CNT register sets the number of receive bytes required by the SPI master. When the required number of
bytes has been received, no more transfers are initiated. To initiate a DMA master receive transfer, a dummy read
should be done by user code. This dummy read should not be added to the SPI_CNT number.
The counter counting the bytes as they are received is reset when SPI is disabled using the SPI_CTL.SPIEN bit in
SPI_CTL, or if the SPI_CNT register is modified by user code.
To perform SPI DMA master receive:
The DMA SPI Rx channel must be configured. The NVIC of the core must be configured to enable DMA Rx master interrupt.
The SPI block must be configured as follows:
SPI_DIV = SPI_SERIAL_FREQ; //configures serial clock frequency.
10–14
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
SPI_CTL = 0x2003;
SPI_DMA = 0x5;
SPI_CNT.VALUE = XXX;
A = SPI_RX;
//enable SPI in master mode and
//receive mode, 1 byte transfer.
//enable DMA mode, enable Rx DMA request.
//number of bytes to be received.
//dummy read.
The DMA transfer stops when the appropriate number of clock cycles has been generated. All DMA data transfers
are 16-bit transfers, and the DMA should be programmed accordingly. For example, if 16 bytes of data are to be
received over the SPI, the DMA should be programmed to perform eight 16-bit transfers. If 17 bytes are to be received, nine 16-bit transfers are required. The additional byte will be padded for the final DMA transfer. Data errors
will occur if the DMA transfers are programmed as byte wide transfers.
NOTE: DMA buffer must be of the same size as SPI_CNT.VALUE (or same size plus one if SPI_CNT.VALUE is
odd) to generate a DMA interrupt when the transfer is complete.
ADuCM302x SPI Register Descriptions
Serial Peripheral Interface (SPI) contains the following registers.
Table 10-3:
ADuCM302x SPI Register List
Name
Description
SPI_CNT
Transfer byte count
SPI_CS_CTL
Chip-Select control for multi-slave connections
SPI_CS_OVERRIDE
Chip-Select Override
SPI_CTL
SPI configuration 1
SPI_DIV
SPI baud rate selection
SPI_DMA
SPI DMA enable
SPI_FIFO_STAT
FIFO Status
SPI_FLOW_CTL
Flow Control
SPI_IEN
SPI configuration 2
SPI_RD_CTL
Read Control
SPI_RX
Receive
SPI_STAT
Status
SPI_TX
Transmit
SPI_WAIT_TMR
Wait timer for flow control
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–15
ADuCM302x SPI Register Descriptions
Transfer byte count
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
FRAMECONT (R/W)
Continue frame
VALUE (R/W)
Transfer byte count
Figure 10-10: SPI_CNT Register Diagram
Table 10-4:
SPI_CNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 FRAMECONT
(R/W)
Continue frame.
This bit should be used in conjunction with SPI_CTL.CON and SPI_CNT.VALUE
fields. It is used to control SPI data framing. If this bit is cleared, the SPI master transfers only one frame of SPI_CNT.VALUE bytes. If set, the SPI master will transfer data
in frames of SPI_CNT.VALUE bytes each. Notes: If SPI_CNT.VALUE = 0, then this
field has no effect as the SPI master will continue with transfers as long as Tx/Rx FIFO
is ready. If SPI_CTL.CON = 0, then also this field has no effect as all SPI frames are
single byte wide irrespective of other control fields.
0 If COUNT > 0, stop SPI transfers after COUNT number of bytes.
1 Continue SPI transfers as long as Tx/Rx FIFO is ready.
13:0 VALUE
(R/W)
10–16
Transfer byte count.
This field specifies the number of bytes to be transferred. It is used in both receive and
transmit transfer types. This value assures that a master mode transfer terminates at the
proper time and that 16-bit SPI_DMA transfers are byte padded or discarded as required to match odd transfer counts.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
Chip-Select control for multi-slave connections
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
SEL (R/W)
Chip-Select control
Figure 10-11: SPI_CS_CTL Register Diagram
Table 10-5:
SPI_CS_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3:0 SEL
(R/W)
Chip-Select control.
This field specifies the CS line to be used for the current SPI transfer. It is useful in a
multi-slave setup where only the CS lines are unique across the various slaves. The SPI
master can support up to 4 different CS lines. By default, CS0 is used if none of the
bits are set. Note: If multiple bits are set, the respective CS lines are active simultaneously.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–17
ADuCM302x SPI Register Descriptions
Chip-Select Override
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CTL (R/W)
CS Override Control
Figure 10-12: SPI_CS_OVERRIDE Register Diagram
Table 10-6:
SPI_CS_OVERRIDE Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1:0 CTL
(R/W)
CS Override Control.
This bit overrides the actual CS output from the master state machine. It may be needed for special SPI transfers. Note: Use it with precaution.
0 CS is not forced.
1 CS is forced to drive 1'b1.
2 CS is forced to drive 1'b0.
3 CS is not forced.
10–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
SPI configuration 1
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CSRST (R/W)
Reset Mode for CS Error bit
SPIEN (R/W)
SPI enable
TFLUSH (R/W)
SPI Tx FIFO Flush enable
MASEN (R/W)
Master mode enable
RFLUSH (R/W)
SPI Rx FIFO Flush enable
CPHA (R/W)
Serial clock phase mode
CON (R/W)
Continuous transfer enable
CPOL (R/W)
Serial Clock Polarity
LOOPBACK (R/W)
Loopback enable
WOM (R/W)
SPI Wired Or mode
OEN (R/W)
Slave MISO output enable
LSB (R/W)
LSB first transfer enable
RXOF (R/W)
RX overflow overwrite enable
TIM (R/W)
SPI transfer and interrupt mode
ZEN (R/W)
Transmit zeros enable
Figure 10-13: SPI_CTL Register Diagram
Table 10-7:
SPI_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 CSRST
(R/W)
13 TFLUSH
(R/W)
12 RFLUSH
(R/W)
11 CON
Reset Mode for CS Error bit.
If this bit is set, the bit counter will be reset after a CS error condition and the Cortex
is expected to clear the SPI_CTL.SPIEN. If this bit is clear, the bit counter will continue from where it stopped. SPI can receive the remaining bits when CS gets asserted
and Cortex has to ignore the SPI_STAT.CSERR interrupt. However, it is strongly recommended to set this bit for a graceful recovery after a CS error.
SPI Tx FIFO Flush enable.
Set this bit to flush the Tx FIFO. This bit does not clear itself and should be toggled if
a single flush is required. If this bit is left high, then either the last transmitted value or
0x00 is transmitted depending on the SPI_CTL.ZEN bit. Any writes to the Tx FIFO
are ignored while this bit is set. Clear this bit to disable Tx FIFO flushing.
SPI Rx FIFO Flush enable.
Set this bit to flush the Rx FIFO. This bit does not clear itself and should be toggled if
a single flush is required. If this bit is set all incoming data is ignored and no interrupts
are generated. If set and SPI_CTL.TIM = 0, a read of the Rx FIFO will initiate a
transfer. Clear this bit to disable Rx FIFO flushing.
Continuous transfer enable.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–19
ADuCM302x SPI Register Descriptions
Table 10-7:
SPI_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
(R/W)
10 LOOPBACK
(R/W)
9 OEN
(R/W)
8 RXOF
(R/W)
7 ZEN
(R/W)
6 TIM
(R/W)
5 LSB
Set by user to enable continuous transfer. In master mode, the transfer continues until
no valid data is available in the SPI_TX register (SPI_CTL.TIM=1) or until the Rx
FIFO is full (SPI_CTL.TIM=0). CS is asserted and remains asserted for the duration
of each 8-bit serial transfer until Tx FIFO is empty or Rx FIFO is full. Cleared by user
to disable continuous transfer. Each SPI frame then consists of a single 8-bit serial
transfer. If valid data exists in the SPI_TX register (SPI_CTL.TIM=1) or if Rx FIFO is
not full (SPI_CTL.TIM=0), then a new transfer is initiated after a stall period of 1 serial clock cycle.
Loopback enable.
Set by user to connect MISO to MOSI and test software. Cleared by user to be in normal mode.
Slave MISO output enable.
Set this bit for MISO to operate as normal. Clear this bit to disable the output driver
on the MISO pin. The MISO pin will be Open-Circuit when this bit is clear.
RX overflow overwrite enable.
Set by user, the valid data in the SPI_RX register is overwritten by the new serial byte
received. Cleared by user, the new serial byte received is discarded.
Transmit zeros enable.
Set this bit to transmit 0x00 when there is no valid data in the Tx FIFO. Clear this bit
to transmit the last transmitted value when there is no valid data in the Tx FIFO.
SPI transfer and interrupt mode.
Set by user to initiate transfer with a write to the SPI_TX register. Interrupt only occurs when SPI_IEN.IRQMODE+1 number of bytes have been transmitted. Cleared by
user to initiate transfer with a read of the SPI_RX register. Interrupt only occurs when
Rx-FIFO has SPI_IEN.IRQMODE+1 number of bytes or more.
LSB first transfer enable.
(R/W)
0 MSB transmitted first
1 LSB transmitted first
4 WOM
SPI Wired Or mode.
(R/W)
0 Normal output levels
1 Enables open circuit data output enable. External pullups required on data out pins
3 CPOL
(R/W)
Serial Clock Polarity.
0 Serial clock idles low
1 Serial clock idles high
10–20
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
Table 10-7:
SPI_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 CPHA
Serial clock phase mode.
(R/W)
0 Serial clock pulses at the end of each serial bit transfer
1 Serial clock pulses at the beginning of each serial bit
transfer
1 MASEN
(R/W)
Master mode enable.
Note: Clearing this bit issues a synchronous reset to the design and most status bits,
while other MMRs are unaffected.
0 Enable slave mode
1 Enable master mode
0 SPIEN
SPI enable.
(R/W)
0 Disable the SPI
1 Enable the SPI
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–21
ADuCM302x SPI Register Descriptions
SPI baud rate selection
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
SPI clock divider
Figure 10-14: SPI_DIV Register Diagram
Table 10-8:
SPI_DIV Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5:0 VALUE
(R/W)
10–22
SPI clock divider.
SPI_DIV.VALUE is the factor used to divide PCLK to generate the serial clock.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
SPI DMA enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RXEN (R/W)
Enable receive DMA request
EN (R/W)
Enable DMA for data transfer
TXEN (R/W)
Enable transmit DMA request
Figure 10-15: SPI_DMA Register Diagram
Table 10-9:
SPI_DMA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
2 RXEN
(R/W)
1 TXEN
(R/W)
0 EN
(R/W)
Enable receive DMA request.
If this bit is set when DMA is enabled, then a RX-DMA request is raised as long there
is valid data in Rx-FIFO.
Enable transmit DMA request.
If this bit is set and DMA is enabled, then a TX-DMA request is raised as long there is
space in Tx-FIFO. Note: This bit needs to be cleared as soon as a Tx-DMA DONE
interrupt is received to prevent extra Tx-DMA requests to the uDMA controller.
Enable DMA for data transfer.
Set by user code to start a DMA transfer. Cleared by user code at the end of DMA
transfer.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–23
ADuCM302x SPI Register Descriptions
FIFO Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RX (R)
SPI Rx FIFO status
TX (R)
SPI Tx FIFO status
Figure 10-16: SPI_FIFO_STAT Register Diagram
Table 10-10:
SPI_FIFO_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
11:8 RX
(R/NW)
SPI Rx FIFO status.
This field specifies the number of bytes in Rx FIFO when DMA is disabled. In DMA
mode, it refers to the number of half-words in Rx FIFO.
0 Rx FIFO empty
1 1 valid byte/half-word in Rx FIFO
2 2 valid bytes/half-words in Rx FIFO
3 3 valid bytes/half-words in Rx FIFO
4 4 valid bytes/half-words in Rx FIFO
5 5 valid bytes/half-words in Rx FIFO
6 6 valid bytes/half-words in Rx FIFO
7 7 valid bytes/half-words in Rx FIFO
8 8 valid bytes/half-words in Rx FIFO (Rx FIFO full)
3:0 TX
(R/NW)
SPI Tx FIFO status.
This field specifies the number of bytes in Tx FIFO when DMA is disabled. In DMA
mode, it refers to the number of half-words in Tx FIFO.
0 Tx FIFO empty
1 1 valid byte/half-word in Tx FIFO
2 2 valid bytes/half-words in Tx FIFO
3 3 valid bytes/half-words in Tx FIFO
4 4 valid bytes/half-words in Tx FIFO
5 5 valid bytes/half-words in Tx FIFO
6 6 valid bytes/half-words in Tx FIFO
7 7 valid bytes/half-words in Tx FIFO
8 8 valid bytes/half-words in Tx FIFO (Tx FIFO full)
10–24
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
Flow Control
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RDBURSTSZ (R/W)
Read data burst size minus 1
MODE (R/W)
Flow control mode
RDYPOL (R/W)
Polarity of RDY/MISO line
Figure 10-17: SPI_FLOW_CTL Register Diagram
Table 10-11:
SPI_FLOW_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
11:8 RDBURSTSZ
(R/W)
4 RDYPOL
(R/W)
Read data burst size minus 1.
This field specifies "the number of bytes to be received - 1" in a single burst from a
slave before waiting for flow-control. This is not valid if SPI_FLOW_CTL.MODE =
2'b00. For all other values of SPI_FLOW_CTL.MODE, this field is valid. This field can
take values from 0 to 15 implying a read burst of 1 to 16 bytes respectively. Note: This
mode is useful for reading fixed-width conversion results periodically.
Polarity of RDY/MISO line.
This field specifies the polarity of the RDY/MISO pin which indicates that the slave's
read data is ready. If SPI_FLOW_CTL.MODE = 2'b10, this field refers to the polarity of
RDY pin. Else if SPI_FLOW_CTL.MODE = 2'b11, this refers to the polarity of MISO
(DOUT) line. For all other values of SPI_FLOW_CTL.MODE this bit is ignored.
0 Polarity is active HIGH. SPI master waits until RDY/
MISO becomes HIGH.
1 Polarity is active LOW. SPI master waits until RDY/
MISO becomes LOW.
1:0 MODE
(R/W)
Flow control mode.
Flow control configuration for data reads. Note: When RDY signal is used for flowcontrol, it could be any signal which is tied to this RDY input of SPI module. E.g., it
could be an off-chip input (or) an on-chip timer output (or) any other control signal.
0 Flow control is disabled.
1 Flow control is based on timer (WAIT_TMR).
2 Flow control is based on RDY signal.
3 Flow control is based on MISO pin.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–25
ADuCM302x SPI Register Descriptions
SPI configuration 2
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
TXEMPTY (R/W)
Tx-FIFO Empty interrupt enable
IRQMODE (R/W)
SPI IRQ mode bits
XFRDONE (R/W)
SPI transfer completion interrupt enable
CS (R/W)
Enable interrupt on every CS edge in
slave CON mode
TXDONE (R/W)
SPI transmit done interrupt enable
TXUNDR (R/W)
Tx-underflow interrupt enable
RDY (R/W)
Ready signal edge interrupt enable
RXOVR (R/W)
Rx-overflow interrupt enable
Figure 10-18: SPI_IEN Register Diagram
Table 10-12:
SPI_IEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 TXEMPTY
(R/W)
Tx-FIFO Empty interrupt enable.
This bit enables the SPI_STAT.TXEMPTY interrupt whenever Tx-FIFO gets emptied.
0 TXEMPTY interrupt is disabled.
1 TXEMPTY interrupt is enabled.
13 XFRDONE
(R/W)
SPI transfer completion interrupt enable.
This bit enables the SPI_STAT.XFRDONE interrupt.
0 XFRDONE interrupt is disabled.
1 XFRDONE interrupt is enabled.
12 TXDONE
(R/W)
SPI transmit done interrupt enable.
This bit enables the SPI_STAT.TXDONE interrupt in read command mode. Note:
This can be used to signal the change of SPI transfer direction in read command
mode.
0 TXDONE interrupt is disabled.
1 TXDONE interrupt is enabled.
10–26
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
Table 10-12:
SPI_IEN Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 RDY
(R/W)
Ready signal edge interrupt enable.
This bit enables the SPI_STAT.RDY interrupt whenever an active edge occurs on
RDY/MISO signals. If SPI_FLOW_CTL.MODE = 2'b10, edge detection happens on
RDY signal. If SPI_FLOW_CTL.MODE = 2'b11, MISO signal is used instead of RDY.
For all other values of SPI_FLOW_CTL.MODE, this bit has no effect. The active edge
(rising/falling) is determined by the SPI_FLOW_CTL.RDYPOL bit.
0 Ready-signal edge interrupt is disabled.
1 Ready-signal edge interrupt is enabled.
10 RXOVR
Rx-overflow interrupt enable.
(R/W)
0 Rx-overflow interrupt is disabled.
1 Rx-overflow interrupt is enabled.
9 TXUNDR
Tx-underflow interrupt enable.
(R/W)
0 Tx-underflow interrupt is disabled.
1 Tx-underflow interrupt is enabled.
8 CS
(R/W)
2:0 IRQMODE
(R/W)
Enable interrupt on every CS edge in slave CON mode.
If this bit is set and the SPI module is configured as a slave in continuous mode, any
edge on CS will generate an interrupt and the corresponding status
bits(SPI_STAT.CSRISE, SPI_STAT.CSFALL) will be asserted. If this bit is not set,
then no interrupt will be generated and the status bits will not be asserted. This bit has
no effect if the SPI is not in continuous mode or if it is a master.
SPI IRQ mode bits.
These bits configure when the Tx/Rx interrupts occur in a transfer. For DMA Rx
transfer, these bits should be 3'b000.
0 Tx interrupt occurs when 1 byte has been transferred.
Rx interrupt occurs when 1 or more bytes have been received into the FIFO.
1 Tx interrupt occurs when 2 bytes have been transferred.
Rx interrupt occurs when 2 or more bytes have been received into the FIFO.
2 Tx interrupt occurs when 3 bytes have been transferred.
Rx interrupt occurs when 3 or more bytes have been received into the FIFO.
3 Tx interrupt occurs when 4 bytes have been transferred.
Rx interrupt occurs when 4 or more bytes have been received into the FIFO.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–27
ADuCM302x SPI Register Descriptions
Table 10-12:
Bit No.
SPI_IEN Register Fields (Continued)
Bit Name
Description/Enumeration
(Access)
4 Tx interrupt occurs when 5 bytes have been transferred.
Rx interrupt occurs when 5 or more bytes have been
received into the FIFO.
5 Tx interrupt occurs when 6 bytes have been transferred.
Rx interrupt occurs when 6 or more bytes have been received into the FIFO.
6 Tx interrupt occurs when 7 bytes have been transferred.
Rx interrupt occurs when 7 or more bytes have been received into the FIFO.
7 Tx interrupt occurs when 8 bytes have been transferred.
Rx interrupt occurs when the FIFO is full.
10–28
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
Read Control
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
THREEPIN (R/W)
Three pin SPI mode
CMDEN (R/W)
Read command enable
TXBYTES (R/W)
Transmit byte count minus 1 for read
command
OVERLAP (R/W)
Tx/Rx Overlap mode
Figure 10-19: SPI_RD_CTL Register Diagram
Table 10-13:
SPI_RD_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
8 THREEPIN
(R/W)
Three pin SPI mode.
This field specifies if the SPI interface has a bidirectional data pin (3-pin interface) or
dedicated unidirectional data pins for Tx and Rx (4-pin interface). This is only valid in
'Read-command' mode and when SPI_FLOW_CTL.MODE = 2'b01. If 3-pin mode is
selected, then MOSI pin will be driven by master during transmit phase and after a
wait time of SPI_WAIT_TMR SCLK cycles, the slave is expected to drive the same
MOSI pin. Note: SPI_FLOW_CTL.MODE should be programmed to 2'b01 to introduce wait states for allowing 'turn-around time'. Else, the slave only has a turn-around
time of half SCLK period (between sampling and driving edges of SCLK). If this mode
is used, set SPI_RD_CTL.OVERLAP = 0.
0 SPI is a 4-pin interface.
1 SPI is a 3-pin interface.
5:2 TXBYTES
(R/W)
Transmit byte count minus 1 for read command.
This field specifies 'the number of bytes to be transmitted - 1' before reading data from
a slave. This field can take values from 0 to 15 corresponding to 1 to 16 tx bytes . This
includes all the bytes that need to be sent out to the slave viz., 'command' and 'address'
(if required). The design doesn't differentiate between these two. It just transmits the
specified number of bytes from the Tx-FIFO. Note: If there is a latency between the
command transmission and data reception, then the number of tx-bytes (mostly 0's) to
be padded for that delay should also be accounted for in this count.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–29
ADuCM302x SPI Register Descriptions
Table 10-13:
SPI_RD_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 OVERLAP
(R/W)
Tx/Rx Overlap mode.
This bit specifies if the start of Tx and Rx overlap. In most of the slaves, the read data
starts only after the master completes the transmission of 'command+address'. This is a
'non-overlapping' transfer. In some slaves, there might be status bytes sent out while
the command is being received. So, we may want to start receiving the bytes from the
beginning of the CS frame. This is 'overlapping' mode. Note: In case of overlapping
mode, SPI_CNT.VALUE refers to the total number of bytes to be received. So, the extra status bytes (which are in addition to the actual read bytes) should be accounted for
while programming SPI_CNT.VALUE.
0 Tx-Rx overlap is disabled.
1 Tx-Rx overlap is enabled.
0 CMDEN
(R/W)
Read command enable.
SPI read command mode where a 'command + address' is transmitted and read data is
expected in the same CS frame. If this bit is cleared, all other fields of SPI_RD_CTL,
SPI_FLOW_CTL and SPI_WAIT_TMR registers don't have any effect.
0 Read command mode is disabled.
1 Read command mode is enabled.
10–30
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
Receive
This register allows access to the 8-deep receive FIFO.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BYTE2 (R)
8-bit receive buffer, used only in DMA
modes
BYTE1 (R)
8-bit receive buffer
Figure 10-20: SPI_RX Register Diagram
Table 10-14:
SPI_RX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 BYTE2
(R/NW)
7:0 BYTE1
8-bit receive buffer, used only in DMA modes.
These 8-bits are used only in the SPI_DMA mode, where all FIFO accesses happen as
half-word access. They return zeros if SPI_DMA is disabled.
8-bit receive buffer.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–31
ADuCM302x SPI Register Descriptions
Status
15 14 13 12 11 10 9
0
0
0
0
RDY (R/W1C)
Detected an edge on Ready indicator
for flow-control
1
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
IRQ (R)
SPI Interrupt status
XFRDONE (R)
SPI transfer completion
CSRISE (R/W1C)
Detected a rising edge on CS, in slave
CON mode
TXEMPTY (R/W1C)
SPI Tx FIFO empty interrupt
CSFALL (R/W1C)
Detected a falling edge on CS, in slave
CON mode
TXDONE (R/W1C)
SPI Tx Done in read command mode
TXUNDR (R/W1C)
SPI Tx FIFO underflow
CSERR (R/W1C)
Detected a CS error condition in slave
mode
TXIRQ (R/W1C)
SPI Tx IRQ
CS (R)
CS Status
RXOVR (R/W1C)
SPI Rx FIFO overflow
RXIRQ (R/W1C)
SPI Rx IRQ
Figure 10-21: SPI_STAT Register Diagram
Table 10-15:
SPI_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 RDY
(R/W1C)
14 CSRISE
(R/W1C)
13 CSFALL
Detected an edge on Ready indicator for flow-control.
This bit indicates that there was an active edge on the RDY/MISO line depending on
the flow control mode. If SPI_FLOW_CTL.MODE = 2'b10, this bit is set whenever an
active edge is detected on RDY signal. If SPI_FLOW_CTL.MODE = 2'b11, this bit is set
if an active edge is detected on MISO signal. For all other values of MODE, this bit is
always 0. The active edge (rising/falling) is determined by the
SPI_FLOW_CTL.RDYPOL. When SPI_IEN.RDY is set, this bit will cause an interrupt
and it is cleared only when '1' is written to this bit. Note: This can be used for 'staggered' flow-control on transmit side, along with a CS override if required.
Detected a rising edge on CS, in slave CON mode.
This bit indicates that there was a rising edge in CS line, when the device was a slave in
continuous mode and SPI_IEN.CS was asserted. This bit will cause an interrupt. It is
cleared when '1' is written to this bit or when SPI_CTL.SPIEN is cleared. This can be
used to identify the end of an SPI data frame.
Detected a falling edge on CS, in slave CON mode.
(R/W1C)
10–32
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
Table 10-15:
SPI_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
This bit indicates that there was a falling edge in CS line, when the device was a slave
in continuous mode and SPI_IEN.CS was asserted. This bit will cause an interrupt. It
is cleared when '1' is written to this bit or when SPI_CTL.SPIEN is cleared. This can
be used to identify the start of an SPI data frame.
12 CSERR
(R/W1C)
11 CS
(R/NW)
Detected a CS error condition in slave mode.
This bit indicates that the CS line was de-asserted abruptly by an external master, even
before the full-byte of data was transmitted completely. This bit will cause an interrupt. It is cleared when '1' is written to this bit or when SPI_CTL.SPIEN is cleared.
CS Status.
This bit reflects the actual CS status as seen by the SPI module. Note: This uses
SCLK-PCLK synchronization. So, there would be a slight delay when CS changes
state.
0 CS line is LOW.
1 CS line is HIGH.
7 RXOVR
(R/W1C)
6 RXIRQ
(R/W1C)
5 TXIRQ
(R/W1C)
4 TXUNDR
(R/W1C)
3 TXDONE
(R/W1C)
2 TXEMPTY
SPI Rx FIFO overflow.
Set when the Rx FIFO was already full when new data was loaded to the FIFO. This
bit generates an interrupt if SPI_IEN.RXOVR is set, except when SPI_CTL.RFLUSH
is set. It is cleared when '1' is written to this bit or when SPI_CTL.SPIEN is cleared.
SPI Rx IRQ.
Set when a receive interrupt occurs. Not available in DMA mode. This bit is set when
SPI_CTL.TIM is cleared and the required number of bytes have been received. It is
cleared when '1' is written to this bit or when SPI_CTL.SPIEN is cleared.
SPI Tx IRQ.
SPI Tx IRQ Status Bit. Not available in DMA mode. Set when a transmit interrupt
occurs. This bit is set when SPI_CTL.TIM is set and the required number of bytes
have been transmitted. It is cleared when '1' is written to this bit or when
SPI_CTL.SPIEN is cleared.
SPI Tx FIFO underflow.
This bit is set when a transmit is initiated without any valid data in the Tx FIFO. This
bit generates an interrupt if SPI_IEN.TXUNDR is set, except when SPI_CTL.TFLUSH
is set. It is cleared when '1' is written to this bit or when SPI_CTL.SPIEN is cleared.
SPI Tx Done in read command mode.
This bit is set when the entire transmit is completed in a read command. This bit generates an interrupt if SPI_IEN.TXDONE is set. This bit is valid only if
SPI_RD_CTL.CMDEN is set. It is cleared only when '1' is written to this bit.
SPI Tx FIFO empty interrupt.
(R/W1C)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–33
ADuCM302x SPI Register Descriptions
Table 10-15:
SPI_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
This bit is set when the Tx-FIFO is empty and SPI_IEN.TXEMPTY is set, except
when SPI_CTL.TFLUSH is set. This bit generates an interrupt. It is cleared when '1' is
written to this bit or when SPI_CTL.SPIEN is cleared.
1 XFRDONE
(R/NW)
0 IRQ
(R/NW)
10–34
SPI transfer completion.
This bit indicates the status of SPI transfer completion in master mode. It is set when
the transfer of SPI_CNT.VALUE number of bytes have been finished. In slave mode or
if SPI_CNT.VALUE = 0, this bit is invalid. If SPI_IEN.XFRDONE is set, this bit generates an interrupt. It uses the state of the master state machine to determine the completion of a SPI transfer. Therefore, a CS override would not affect this bit. It is cleared
only when '1' is written to this bit.
SPI Interrupt status.
Set to 1 when an SPI based interrupt occurs. Cleared when all the interrupt sources are
cleared.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPI Register Descriptions
Transmit
This register allows access to the 8-deep transmit FIFO.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BYTE2 (W)
8-bit transmit buffer, used only in DMA
modes
BYTE1 (W)
8-bit transmit buffer
Figure 10-22: SPI_TX Register Diagram
Table 10-16:
SPI_TX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 BYTE2
(RX/W)
7:0 BYTE1
8-bit transmit buffer, used only in DMA modes.
These 8-bits are used only in the SPI_DMA mode, where all FIFO accesses happen as
half-word access.
8-bit transmit buffer.
(RX/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
10–35
ADuCM302x SPI Register Descriptions
Wait timer for flow control
This register is only used in master mode.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Wait timer for flow-control
Figure 10-23: SPI_WAIT_TMR Register Diagram
Table 10-17:
SPI_WAIT_TMR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
10–36
Wait timer for flow-control.
This field specifies the number of SCLK cycles to wait before continuing the SPI read.
This field can take values of 0 to 65535. This field is only valid if
SPI_FLOW_CTL.MODE = 2'b01. For all other values of SPI_FLOW_CTL.MODE, this
field is ignored. A value of 0 implies a wait time of 1 SCLK cycle.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Serial Port (SPORT)
11 Serial Port (SPORT)
The ADuCM302x processor has serial ports (SPORTS) that support a variety of serial data communication protocols. In addition, the SPORTs provide a glueless hardware interface to many industry-standard data converters, codecs and other processors, including DSPs. The SPORT top module comprises of two half SPORTs (HSPORT)
with identical functionality SPORT_A and SPORT_B. Each SPORT half can be independently configured as either
a transmitter or receiver and can be coupled with the other HSPORT within the same SPORT. Each SPORT half
has the same capabilities and is programmed in the same way.
SPORT Features
Each HSPORT supports the following features:
• One bidirectional data line, configurable as either transmitter or receiver. Further, two SPORT halves can be
combined to enable full-duplex operation.
• Operation mode:
• Standard DSP serial mode
• Timer enabled mode
• Serial data words between 4 and 32 bits in length.
• Improved granularity for internal clock generation, allowing even PCLK to SPORT_CLK ratios. The SPORTs
can also accept an input clock from an external source.
• Configurable rising or falling edge of the SPORT_CLK for driving or sampling data and frame sync.
• Gated clock mode support for internal clock mode.
• Frame Sync options:
• Unframed mode
• Internal/external frame sync options
• Programmable polarity
• Early/Late Frame Sync
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–1
Signal Description
• Status flagging and optional interrupt generation for prematurely received external frame syncs.
• External frame sync signal configured as level-sensitive signal.
• Programmable bit order - MSB/LSB first.
• Programmable transfer count of 1-4095 words.
• Optional 16-bit to 32-bit word or 8 bit to 32 bit packing when SPORT is configured as receiver and 32-bit to
16-bit or 32-bit to 8 bit word unpacking when configured as Transmitter.
• Status flagging and optional interrupt generation for Transmit under-run or Receive over-flow.
• Interrupt driven transfer support.
• Dedicated DMA channel for each SPORT half.
• Transfer Finish Interrupt (TFI): An interrupt is generated when the last bit of programmed number of transfers
is transmitted out.
• Ability to route and share the clocks and/or frame sync between the SPORT halves of the SPORT module.
• SPORT_CONVT signal generation in the timer enable mode.
• Interrupt control
• One DMA channel per SPORT half.
• Each SPORT half has its own set of control registers and data buffers.
• Core can also access the data buffers.
Signal Description
Each SPORT half module has four dedicated pins, as described in the following table.
Table 11-1:
SPORT Pin Descriptions
Internal Node
Direction
Description
SPT_CLK
I/O
Transmit/Receive Serial Clock. Data and Frame Sync are driven/sampled with respect to this clock. This signal can be either internally or externally generated.
SPT_FS
I/O
Transmit/Receive Frame Sync. The frame sync pulse initiates shifting of serial data.
This signal is either generated internally or externally.
SPT_D0
I/O
Transmit/receive Data channel. Bidirectional data pin. This signal can be configured as an output to transmit serial data, or as an input to receive serial data.
SPT_CONVT
Output
This is an additional control signal used only in the case of Timer enable mode for
peripherals which require two signals for control information
• The clock and frame sync signals can be interconnected between the SPORT half pair, as explained in SPORT
pin MUX section (if required).
11–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPORT Functional Description
• The SPT_CONVT signal is used only in the timer enable mode and is explained in the Timer enable mode section.
SPORT Functional Description
The following section provides general information about functionality of the serial ports of processors:
ADuCM302x SPORT Register List
Table 11-2:
ADuCM302x SPORT Register List
Name
Description
SPORT_CTL_A
Half SPORT 'A' Control Register
SPORT_CTL_B
Half SPORT 'B' Control Register
SPORT_DIV_A
Half SPORT 'A' Divisor Register
SPORT_DIV_B
Half SPORT 'B' Divisor Register
SPORT_IEN_A
Half SPORT A's Interrupt Enable register
SPORT_IEN_B
Half SPORT B's Interrupt Enable register
SPORT_NUMTRAN_A
Half SPORT A Number of transfers register
SPORT_NUMTRAN_B
Half SPORT B Number of transfers register
SPORT_RX_A
Half SPORT 'A' Rx Buffer Register
SPORT_RX_B
Half SPORT 'B' Rx Buffer Register
SPORT_STAT_A
Half SPORT 'A' Status register
SPORT_STAT_B
Half SPORT 'B' Status register
SPORT_CNVT_A
Half SPORT 'A' CONVT width
SPORT_CNVT_B
Half SPORT 'B' CONVT width register
SPORT_TX_A
Half SPORT 'A' Tx Buffer Register
SPORT_TX_B
Half SPORT 'B' Tx Buffer Register
SPORT Block Diagram
The figure shows the top-level block diagram of the SPORT.
It shows the interfacing with the APB and DMA channel. It also shows the connection with the peripheral.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–3
SPORT Functional Description
CORE IRQ
SPT_CONVT A
SPT_FS A
HALF SPORT A
SPT_CLK A
DMA Signals
SPT_D0 A
APB Bus
SPT_CONVT B
SPT_FS B
HALF SPORT B
SPT_CLK B
DMA Signals
SPT_D0 B
CORE IRQ
Figure 11-1: Top-level Block Diagram of SPORT
The following figure shows the block diagram of a SPORT half.
Core IRQ
SPT_FS
MMR
Regis
ters
32
SPORT
transmit block
SPORT
receive block
32
TX FIFO
Control
information
DMA signals
SPT_CLK
SPT_CONVT
RX FIFO
APB signals
Control block
TX data
SPT_D0
RX
data
Figure 11-2: Half-SPORT Block Diagram
Each SPORT module consists of two separate blocks, known as half-SPORT (HSPORT) A and B, with identical
functionality. These blocks can be independently configurable as either transmitter or receiver as shown in the top
level block diagram.
Each HSPORT has its own set of control registers and data buffers. Two HSPORTs must be combined to achieve
full-duplex operation.
Multiplexer Logic
There is a multiplexing block, known as SPMUX that is integrated between the SPORT and the PinMux logic. It
allows flexibility to route and share the clock and frame sync signals between the two SPORT half pairs of the
11–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPORT Functional Description
SPORT. This feature can be used to reduce the total number of pins for the interface and is efficient when the
SPORT half pair is used for full-duplex operation.
The SPORT_CTL_A.CKMUXSEL and SPORT_CTL_A.FSMUXSEL is used to configure this feature. The control bits
of this register are as described in the "Register Descriptions" section of this chapter.
The figure below shows the operation of this multiplexer for connection between half SPORTs clocks.
SPT_CLK A
HSCLK A_IN
0
HSPORT A
HSCLK B_OUT
SPT_CLK B
HSPORT B
Figure 11-3: Multiplexer Logic when HSPORT A uses HSPORT B’s Internal Clock
The above figure shows that Half SPORT A can be programmed to obtain from the neighboring half SPORT B. If
CKAMUX (which is SPORT_CTL_A.CKMUXSEL) is 1, then it receives an internal clock of B when
SPORT_CTL_B.ICLK value is 1.
If CKAMUX (which is SPORT_CTL_A.CKMUXSEL) is 1 and SPORT_CTL_B.ICLK value is 0, both half SPORTs
get the same external clock as shown in the figure below.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–5
SPORT Functional Description
SPT_CLK A
HSCLK A_IN
HSPORT A
SPT_CLK B
CKAMUX
HSCLK B_IN
HSPORT B
Figure 11-4: Multiplexer Logic when HSPORT A and HSPORT B use the same External Clock
When CKAMUX is 0, normal operation of clock is carried out for both the half SPORTs.
The following section describes the operation of this multiplexer for connection between half SPORTs frame syncs.
SPT_FSA
0
HSFS A_IN
HSPORT A
1
FSAMUX
HSCLK B_OUT
SPT_FS B
HSPORT B
Figure 11-5: Multiplexer Logic when HSPORT A uses HSPORT B’s Internal Frame Sync
The Multiplexer Logic figure shows that Half SPORT A can be programmed to obtain frame sync from neighboring
half SPORT B. If SPORT_CTL_A.FSMUXSEL is 1, then it gets internal frame sync of B when SPORT_CTL_B.IFS
value is 1.
11–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPORT Functional Description
If FSAMUX is 1 and SPORT_CTL_B.IFS value is 0, both half SPORTs get the same external frame sync as shown
in the following diagram.
HSFS A_IN
0
SPT_FS A
1
SPT_FS B
HSPORT A
FSAMUX
HSFS B_IN
HSPORT B
Figure 11-6: Multiplexer Logic when HSPORT A and HSPORT B use the same External Frame Sync
When FSAMUX is 0, normal operation of frame sync is carried out for both the half SPORTs.
Polarity bits such as SPORT_CTL_A.CKRE,SPORT_CTL_B.CKRE, SPORT_CTL_A.LFS, and SPORT_CTL_B.LFS
should have identical settings when using muxing between two SPORT halves. The NUM_TRAN value should also
be programmed with the same number in both half SPORTs when same internal clock/frame sync is used in both
halves.
NOTE: From these tables, one can note that HSPORT A can import serial clock signal from HSPORT B, only
when it is configured in external clock mode. Similarly, it can import frame sync signal, only when it is configured
in external frame sync mode. SPORT_CTL_A register programming (for CKMUXSEL and FSMUXSEL) is required
only for HSPORT A; and not required for HSPORT B to enable this sharing.
Serial Clock
The serial clock (SPT_CLK) signal control how the data bits are driven or sampled. The frame sync signal is also
driven (in internal frame sync mode) or sampled (in external frame sync mode) with respect to serial clock signal.
The serial clock can be internally generated from processor's system clock or externally provided, based on
SPORT_CTL_x.ICLK (SPORT_CTL_A.ICLK or SPORT_CTL_B.ICLK) bit setting. If a SPORT is configured in
internal clock mode (SPORT_CTL_x.ICLK= 1), then the SPORT_DIV_x.CLKDIV (SPORT_DIV_A.CLKDIV or
SPORT_DIV_B.CLKDIV) field specifies the divider to generate serial port clock signal from its fundamental clock,
PCLK. This divisor is a 16-bit value, allowing a wide range of serial clock rates.
Use the following equation to calculate the serial clock frequency:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–7
SPORT Functional Description
f SPT_CLK =
PCLK
2x(1+SPORT_DIV_xCLKDIV)
The maximum serial data rate is 13 Mbps for a maximum PCLK frequency of 26 MHz.
In gated clock mode (explained later), the serial port can be configured to generate gated clock which is active only
for the duration of valid data.
If a SPORT is configured in external clock mode (SPORT_CTL_x.ICLK = 0), then serial clock is an input signal
and the SPORT operates in slave mode. The SPORT_DIV_x.CLKDIV is ignored.
The externally supplied serial clock is always considered as an asynchronous clock with respect to the processor system clock. Refer to the timing specifications section in the ADuCM302x Datasheet for exact AC timing specifications.
Frame Sync
Frame sync is a control signal, used to determine the start of new word or frame. Upon detecting this signal, serial
port starts shifting in or out the data bits serially based on the direction selected. The frame sync signal can be internally generated from its serial clock (SPT_CLK x) or externally provided, based on the SPORT_CTL_x.IFS
(SPORT_CTL_A.IFS or SPORT_CTL_B.IFS) bit setting.
If SPORT is configured for internal frame sync mode (SPORT_CTL_x.IFS = 1), then the SPORT_DIV_x.FSDIV
(SPORT_DIV_A.FSDIV or SPORT_DIV_B.FSDIV) field specifies the divider to generate SPT_FS x signal from the
serial clock. This divisor is a 8-bit value, allowing a wide range of frame sync rates to initiate periodic transfers.
Frame sync is generated based upon the divisor specified. The formula for the number of cycles between frame sync
pulses is:
Number of serial clocks between frame syncs = (SPORT_DIV_x.FSDIV + 1).
FSDIV is used for the internally generated SPT_CONVT signal when it is operating in timer enable mode. Therefore, for timer enable mode, this field refers to the number of serial clock cycles between SPT_CONVT pulses.
The value of SPORT_DIV_x.FSDIV should not be less than the value of the SPORT_CTL_x.SLEN
(SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN) bit field (the serial word length minus one, as this may cause an
external device to abort the current operation or cause other unpredictable results.
NOTE: After enabling the SPORT, the first internal frame sync (or CONVT in case of Timer enable mode) appears
after a delay of (SPORT_DIV_x. FSDIV + 1) serial clocks.
If a SPORT is configured in external frame sync mode (SPORT_CTL_x.IFS = 0), then SPT_FS x is an input signal
and the SPORT_DIV_x.FSDIV field of the SPORT_DIV_x (SPORT_DIV_A or SPORT_DIV_B) register is ignored.
By default, this external signal is level-sensitive. The frame sync is expected to be synchronous with the serial clock.
If not, it must meet the timing requirements that appear in the timing specification section in the ADuCM302x
Datasheet.
NOTE: Frame sync must be in the inactive (deasserted) state when the SPORT is enabled.
11–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Frame Sync
Frame Sync Options
The framing signals may be active high or active low. The SPORT_CTL_x.LFS (SPORT_CTL_A.LFS or
SPORT_CTL_B.LFS) bit selects the logic level of the frame sync signals.
• When SPORT_CTL_x.LFS = 0, the corresponding frame sync signal is active high.
• When SPORT_CTL_x.LFS = 1, the corresponding frame sync signal is active low. Active high is the default
polarity of frame sync signal.
The following sections provide generic information about how frame sync signal is used by the serial port in an
operating mode.
Data-Dependent vs Data-Independent Frame Sync
When a SPORT is configured as a transmitter (SPORT_CTL_x.SPTRAN = 1, (SPORT_CTL_A.SPTRAN or
SPORT_CTL_B.SPTRAN)) and if data-independent frame sync select (SPORT_CTL_x.DIFS,
(SPORT_CTL_A.DIFS or SPORT_CTL_B.DIFS)) bit = 0, then an internally-generated transmit frame sync is only
driven when a new data word has been loaded into the transmit buffer of the SPORT. In other words, frame sync
signal generation and therefore data transmission is data-dependent. This mode of operation allows for wait states
when data is not ready.
When SPORT is configured as receiver (SPORT_CTL_x.SPTRAN = 0) and if SPORT_CTL_x.DIFS= 0, then a receive frame sync signal is generated only when receive data buffer status is not full.
The data-independent frame sync mode allows the continuous generation of the framing signal, regardless of the
buffer status. Setting SPORT_CTL_x.DIFS activates this mode. When SPORT_CTL_x.DIFS = 1, a transmit/
receive frame sync signal is generated regardless of the transmit/receive data buffer status respectively.
NOTE: The DMA typically keeps the transmit buffer full. The application is responsible for filling the transmit
buffers with data. Else, an underflow/overflow case would arise and it would be flagged.
Early vs Late Frame Syncs
The frame sync signals can be early or late. The SPORT_CTL_x.LAFS (SPORT_CTL_A.LAFS or
SPORT_CTL_B.LAFS) bit of the serial port control register configures this option.
By default, when SPORT_CTL_x.LAFS is cleared (=0), the frame sync signal is configured as early framing signal.
This is the normal mode of operation. In this mode, the first bit of the transmit data word is available (and the first
bit of the receive data word is latched) in the serial clock cycle after the frame sync is asserted. The frame sync is not
checked again until the entire word has been transmitted (or received).
If data transmission is continuous in early framing mode (in other words, the last bit of each word is immediately
followed by the first bit of the next word), then frame sync signal occurs during the last bit of each word. Internally
generated frame syncs are asserted for one clock cycle in early framing mode.
When SPORT_CTL_x.LAFS is set (=1), late frame syncs are configured; this is the alternate mode of operation. In
this mode, the first bit of the transmit data word is available (and the first bit of the receive data word is latched) in
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–9
Frame Sync
the same serial clock cycle that the frame sync is asserted. Receive data bits are latched by serial clock edges.
Internally-generated frame syncs remain asserted for the entire length of the data word in late framing mode.
NOTE: In late frame sync case, externally generated frame syncs are expected to be asserted for the entire word
length of the data transfer. Else, unpredictable results can occur.
The following figure illustrates the two modes of frame signal timing.
Serial CLK
Early
Frame Sync
1 CLK
Late
Word Length
Frame Sync
Date
D3
D2
D1
D0
Figure 11-7: Normal Framing (Early Frame Sync) Versus Alternate Framing (Late Frame Sync)
Framed Sync and Unframed Frame Sync
The use of frame sync signal is optional in serial port communications. The SPORT_CTL_x.FSR (frame sync required) (SPORT_CTL_A.FSR or SPORT_CTL_B.FSR) bit determines whether framing signal is required.
When SPORT_CTL_x.FSR bit is set (1), a frame sync signal is required for every data word.
When SPORT_CTL_x.FSR is cleared (0), the corresponding frame sync signal is not required. A single frame sync is
required to initiate communications but it is ignored after the first bit is transferred. Data words are then transferred
continuously in what is referred to as an unframed mode. Unframed mode is appropriate for continuous reception/
transmission.
The following figure shows the framed versus unframed mode of serial port operation.
11–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPORT Functional Description
B
B
B
B
B
B
B
B
3
2
1
0
3
2
1
0
B
B
B
B
B
B
B
B
B
B
B
3
2
1
0
3
2
1
0
3
2
1
Figure 11-8: Framed Versus Unframed Data Stream
NOTE: In unframed mode of operation, the SPORT_CTL_x.DIFS bit should always be set to 1.
SPORT_CTL_x.DIFS=0 is not supported for unframed mode. Also, the SPORT_CTL_x.LAFS bit should always be
set as zero. Late frame sync is not supported for unframed mode.
Sampling Edge
The serial port uses two control signals to sample or drive the serial data:
• Serial clock (SPT_CLK) applies the bit clock for each serial data.
• Frame sync (SPT_FS) divides the data stream into frames.
These control signals can be internally generated or externally provided, determined by the SPORT_CTL_x.ICLK
(SPORT_CTL_A.ICLK or SPORT_CTL_B.ICLK) and SPORT_CTL_x.IFS (SPORT_CTL_A.IFS or
SPORT_CTL_B.IFS) bit settings.
Data and frame syncs can be sampled on the rising or falling edges of the serial port clock signals. The
SPORT_CTL_x.CKRE (SPORT_CTL_A.CKRE or SPORT_CTL_B.CKRE) bit controls the sampling edge. By default,
when SPORT_CTL_x.CKRE = 0, the processor selects the falling edge of SPT_CLK signal for sampling receive data
and external frame sync. The receive data and frame sync are sampled on the rising edge of SPT_CLK when
SPORT_CTL_x.CKRE = 1.
Transmit data and internal frame sync signals are driven (change their state) on the serial clock edge that is not selected. By default, (SPORT_CTL_x.CKRE = 0) the SPORTs drive data and frame sync signals on the rising edge of
the SPT_CLK signal and drives on falling edge when SPORT_CTL_x.CKRE= 1.
Therefore, transmit and receive functions of any two serial ports connected together should always select the same
value for SPORT_CTL_x.CKRE so that internally generated signals are driven on one edge, and received signals are
sampled on the opposite edge.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–11
SPORT Functional Description
The following figure shows the typical SPORT signals at two sides of serial communication for
SPORT_CTL_x.CKRE = 0.
DRIVE
SCLK
DRIVE
FS
SDRIVE
DATA
D6
D7
D5
D4
D3
D2
D1
D0
SAMPLED
FS
SAMPLED
DATA
D7
D6
D5
D4
D3
D2
D1
D0
Figure 11-9: Frame Sync and Data Driven on Rising Edge
When the slave samples the Frame Sync signal, the word counter is reloaded to the maximum setting. Each
SPT_CLK decrements this word counter until the full frame is received.
Therefore, if the transmitter drives the internal frame sync and data on the rising edge of serial clock, the falling edge
should be used by receiver to sample the external frame sync and data, and vice versa.
Premature Frame Sync Error Detection
A SPORT framing signal is used to synchronize transmit or receive data. In external FS mode, any frame sync received when an active frame is in progress or if frame sync truncates in between a transfer in late frame sync case, it
is called premature and is invalid.
If premature frame sync is received, the SPORT_STAT_A.FSERR or SPORT_STAT_B.FSERR bit is flagged to indicate this framing error. An optional error interrupt can be generated for this event by setting
SPORT_IEN_A.FSERRMSK and SPORT_IEN_B.FSERRMSK bits.
As shown in the following figure, the frame sync error (which sets the error bit) is triggered when an early frame
sync occurs during data transfer (transmission or reception) or for late frame sync if the period of the frame sync is
smaller than the serial word length (SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN).
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPORT Functional Description
EARLY FS
=> SPERRI INTERRUPT
DRIVE
SCLK
DRIVE
FS
SDRIVE
DATA
D6
D7
D5
D4
D3
D2
D1
D0
SAMPLED
FS
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
SLEN
COUNTER
SAMPLED
DATA
Figure 11-10: Frame Sync Error Detection
When a frame sync error occurs, SPORT_CTL_A.FSERRMODE or SPORT_CTL_B.FSERRMODE bit decides the way
this error is handled only in case of receive operation. If this bit is set, the receive data is discarded. When the next
frame sync comes, fresh receive transfer is carried out.
If this bit is zero, then the frame sync error is flagged and the transfer is continued. No action is taken with respect
to the transfer.
Serial Word Length
The SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN field of serial port control register determines the word length
of serial data to transmit and receive. Each SPORT half can independently handle word lengths up to 32 bits.
Words smaller than 32 bits are right-justified during transmit or receive buffers to least significant bit (LSB) position. However, data can be shifted-in or out in MSB first or LSB first format based on SPORT_CTL_A.LSBF or
SPORT_CTL_B.LSBF bit setting.
The value of the SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN field can be calculated as:
SLEN = Serial port word length - 1
The range of valid word length in DSP serial mode is 4-32.
Number of Transfers
The register SPORT_NUMTRAN_A or SPORT_NUMTRAN_B of serial port determines the number of word transfers.
The word length is specified in the SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN field. Each SPORT half has this
field and can be used for receive or transmit depending on the SPORT_CTL_A.SPTRAN or SPORT_CTL_B.SPTRAN
bit. This field can be programmed to the required number of word transfers to be transmitted/received. Once the
programmed number of transfers are done, the SPORT disables all the operations. That is clock will not be generated if in internal clock mode and would not be latched if in external clock mode. The frame sync is not generated
and no operation is performed for received frame syncs.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
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SPORT Functional Description
For example, if 20 transfers are programmed and word length programmed is 20 bits, after 400 bits of transfer the
SPORT would disable all the operations. If the peripheral intends to have a large transfer, this register can be
programmed to a higher value.
This register has 12 programmable bits to decide the number of transfers.
It should be noted that the clock and frame sync would not be generated once the number of transfers are finished
in internal clock mode. If it is desired that next set of transfers need to be programmed, the
SPORT_NUMTRAN_CNT_A and SPORT_NUMTRAN_CNT_Bregisters should be reprogrammed with the desired number of transfers. If the same number of transfers need to be programmed, the same value should be reprogrammed.
Also, once the number of transfers are finished, in external clock mode, no extra frame syncs are expected to be sent
to the SPORT. If new transfers need to be given, the frame sync should be sent only once the NUM_TRAN is
reprogrammed.
NOTE: In unframed mode, the number of transfers cannot be reprogrammed to perform the next set of transfers.
SPORT must be disabled and re-enabled to perform the operation for the next set of transfers in case of unframed
mode.
SPORT Transfer
The serial port is configured in transmit mode, if SPORT_CTL_A.SPTRAN or SPORT_CTL_B.SPTRAN control bit
is set. If this bit is cleared, serial port is configured in receive mode. Once a path is activated, data is shifted in response to a frame sync at the rate of serial clock. Receive data buffers are inactive when SPORT is operating in transmit mode and transmit data buffers when in receive mode. Inactive data buffers are not used and should not be
accessed. An application program must use the appropriate data buffers.
Transmit Path
The SPORT_CTL_A.SPTRAN or SPORT_CTL_B.SPTRAN control bit, when set, configures the SPORT in transmit
mode.
The SPORT_TX_A and SPORT_TX_B registers are used as the transmit data buffer (which is a three deep FIFO).
The data to be transmitted is written to the SPORT_TX_A and SPORT_TX_B registers to transmit data buffer
through the APB bus. This data is then transferred to the transmit shift register. The shift register, clocked by
SPT_CLK signal, then serially shifts out this data on SPT_D0, synchronously. If framing signal is used, the SPT_FS
signal indicates the start of the serial word transmission.
When SPORT is configured as transmitter, the enabled SPORT data pins SPT_ D0 are always driven.
NOTE: If next frame sync is assigned after a time duration greater than serial word length, then during inactive
serial clock cycles (clock cycles after data transmission in the current frame), the SPORT drives the first bit of next
word to be transmitted on the data pin. This does not cause any problem at the receiver end, as it starts sampling the
data pin only after detecting a valid frame sync. Note that this is not the case in gated clock mode as no clock is
present during inactive frame sync.
The serial port provides status of transmit data buffers and error detection logic for transmit errors such as underrun. For more information, refer to Error Detection.
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPORT Functional Description
When a serial port is configured in transmit mode, the receive data path is deactivated and do not respond to serial
clock or frame sync signals. So, reading from an empty Receive Data Buffer is not recommended in Tx mode.
Receive Path
The SPORT_CTL_A.SPTRAN bit, when cleared, configures the SPORT in receive mode. Enables the Receive path
by SPORT_CTL_A.SPTRAN or SPORT_CTL_B.SPTRAN.
The SPORT_RX_A and SPORT_RX_B registers, which are the receive data buffers (three deep FIFO), are accessible
over APB.
In Rx mode, the input shift register shifts in data bits on the SPT_D0, synchronous to the SPT_CLK. If framing
signal is used, the SPT_AFS signal indicates the beginning of the serial word being received. When an entire word is
shifted in on the channel, the data is available to be read from SPORT_RX_x.
The serial port provides the status of Receive Data buffers and error detection logic for receive errors such as overflow. For more information, refer to Error Detection.
When a serial port is configured in receive mode, the transmit path is deactivated and does not respond to serial
clock or frame sync signals. Therefore, accessing the transmit data buffer is not recommended in Rx mode.
SPORT Power Management
When the chip goes into hibernate mode, the configuration values are retained. The following registers are retained:
• SPORT_CTL_A (except DMAEN and SPEN bit fields)
• SPORT_DIV_A
• SPORT_CNVT_A
• SPORT_CTL_B (except DMAEN and SPEN bit fields)
• SPORT_DIV_B
• SPORT_CNVT_B
It should be noted that, if any transfer was going on before the chip went into hibernate, that transfer will not resume after returning from hibernate. A fresh start must be made when SPORT comes back from hibernate for the
new transfer. One should program the SPORT_NUMTRAN_A or SPORT_NUMTRAN_B register appropriately and then
program the SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN bit to enable the SPORT operation.
SPORT Operating Modes
The ADuCM302x processor has SPORT that supports the following operating modes:
• Standard serial mode
• Timer enable mode
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–15
SPORT Operating Modes
The SPORT halves within a SPORT can be independently configured for this operating mode, unless they are not
coupled together using SPMUX logic.
NOTE:
• These modes support either, cases where the clock and the frame sync are both internal or both are external.
Modes with External Frame Sync, Internal Clock and Internal Frame Sync, External Clock is not supported by
SPORT. Only for the unframed mode, external clock (SPORT_CTL_x.ICLK = 0 (SPORT_CTL_A.ICLK or
SPORT_CTL_B.ICLK)) and internal frame sync pulse (SPORT_CTL_x.IFS = 1 (SPORT_CTL_A.IFS or
SPORT_CTL_B.IFS)), generated for the start of transfer is supported.
• To change the SPORT configuration (like changing SPORT_CTL_x.SLEN (SPORT_CTL_A.SLEN or
SPORT_CTL_B.SLEN) or SPORT_CTL_x.LSBF (SPORT_CTL_A.LSBF or SPORT_CTL_B.LSBF)), clear the
SPORT_CTL_x.SPEN bit (SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN) and re-enable again by setting this
bit.
• When SPORT is operating in external clock mode, SPORT needs three Serial clocks after the SPORT is enabled before the normal operation can begin.
Mode selection
The serial port operating mode is configured in the SPORT_CTL_x.OPMODE (SPORT_CTL_A.OPMODE or
SPORT_CTL_B.OPMODE).
Standard Serial Mode
The SPORT can be configured in standard DSP serial mode by clearing the SPORT_CTL_x.OPMODE. The standard
serial mode lets programs configure serial ports to connect to a variety of serial devices such as serial data converters
and audio codecs. In order to connect to these devices, a variety of clocking, framing, and data formatting options
are available. All these options are as discussed in the above section describing the signals and the various features.
All of these options can be used in the Standard Serial Mode.
Timer Enable Mode
Some of the ADCs/DACs require two control signals for their conversion process. In order to interface with such
devices, an extra signal is required. This control signal is called SPT_CONVT signal. The timer enable mode should
be enabled in order to use this signal by programming the SPORT_CTL_x.OPMODE as 1. In this mode, a PWM
timer inside the module is used to generate the programmable CONVT signal.
The width of SPT_CONVT is programmed in the SPORT_CNVT_x.WID (SPORT_CNVT_A.WID or
SPORT_CNVT_B.WID) field. The delay between SPT_CONVT assertion and Frame sync assertion is programmed
in the SPORT_CNVT_x.CNVT2FS (SPORT_CNVT_A.CNVT2FS or SPORT_CNVT_B.CNVT2FS). This programmability provides flexibility in the use of these signals. The following figure shows these values.
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPORT Data Transfer
Serial CLK
CONVT
CONVT_WIDTH
CONVT_WIDTH
CONVT_FS_DURTN
Frame Sync
Data
Word Length
D3
D2
D1
D0
FSDIV
Figure 11-11: Signals Interfaced in Timer Enable Mode
The polarity of the SPT_CONVT signal can be programmed in the SPORT_CNVT_x.POL (SPORT_CNVT_A.POL
or SPORT_CNVT_B.POL) bit field.
The number of serial clock cycles between CONVT pulse is given by FSDIV value as explained in the Frame Sync
section. All the other programmable options defined for Frame sync in the DSP serial mode can be used in this
mode except the following options:
• External Frame Sync and External Clock cannot be used.
• Early Frame sync cannot be used.
• Unframed mode cannot be used.
NOTE: SPORT_CONVT signal is not used when DSP serial mode is in use.
SPORT Data Transfer
The SPORT uses either a core driven or DMA driven data transfers. DMA transfers can be set up to transfer a configurable number of serial words between the serial port transmit or receive data buffers and internal memory automatically. Core-driven transfers use SPORT interrupts to signal the processor core to perform single word transfers
to/from the serial port data buffers.
Single Word (Core) Transfers
Individual data words may also be transmitted or received by the serial ports, with interrupts occurring as each data
word is transmitted or received. When a serial port is enabled and corresponding DMA is disabled, the SPORT
interrupts are generated whenever a complete word has been received in the receive data buffer, or whenever the
transmit data buffer is not full. When serial port data packing is enabled, transmit and receive interrupts are generated for 32-bit packed words, not for each 16-bit or 8-bit word. When performing core driven transfers, write to the
buffer designated by the SPORT_CTL_A.SPTRAN (where A is the SPORT half ) bit setting. To avoid undetermined
behavior, check the status of appropriate data buffers when the processor core tries to read a word from a serial port's
receive buffer or writes a word to its transmit buffer. The full/empty status can be read using the
SPORT_STAT_x.DXS (SPORT_STAT_A.DXS or SPORT_STAT_B.DXS) bits.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
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SPORT Data Transfer
DMA Transfers
Direct memory access (DMA) provides a mechanism for receiving or transmitting an entire block of serial data before an interrupt is generated. When SPORT DMA is not enabled, the SPORT generates an interrupt every time it
receives or starts to transmit a data word. The processor's on-chip DMA controller handles the DMA transfer, allowing the processor core to either go to sleep or continue running other tasks until running until the entire block of
data is transmitted or received. Service routines can then operate on the block of data rather than on single words,
significantly reducing overhead.
Therefore, set the direction bit, DMA enable bit, and serial port enable bit before initiating any operations on the
SPORT data buffers. Do not try to access data buffers when the associated DMA channel of serial port is enabled.
Each SPORT half has a dedicated DMA channel for Tx and Rx data paths. In transmit mode, the DMA controller
writes to the transmit data buffer. Similarly, in receive mode, the DMA controller reads from the receive data buffer.
The DMA controller generates an interrupt at the end of the completion of a DMA transfer.
Though DMA transfers are performed with 32-bit words, the SPORTs can handle word sizes from 4 to 32 bits (as
defined by SPORT_CTL_x.SLEN (SPORT_CTL_A.SLEN or SPORT_CTL_B.SLEN) field). If serial data length is 16
bits or smaller, two data can be packed into 32-bit words for each DMA transfer. If serial data length is 8 bits or
smaller, four data can be packed into 32-bit words for each DMA transfer (as described in DATA buffer packing
section). When serial port data packing is enabled, transmit and receive DMA requests are generated for the 32-bit
packed words, not for each 16-bit or 8-bit word.
Depending on whether packing is enabled, appropriate DMA transfer width needs to be selected in the DMA controller. If packing is enabled or greater than 16 bit transfers are desired, use word transfers in DMA. If packing is not
enabled and transfer is less than 16 bits but greater than 8 bits, use half word transfers. If packing is not enabled and
transfer length is less than 8bits, use byte transfers within the DMA controller.
NOTE: DMA requests may not be serviced frequently enough to guarantee continuous data flow in case of continuous transmission/reception. Ensure that the DMA channel has the highest priority when performing such transfers.
SPORT Data Buffers
Data Buffer Status
Serial ports provide status information about data buffers. Depending on the SPORT_CTL_A.SPTRAN (where A is
the SPORT half ) bit setting, these bits reflect the status of transmit data buffers or receive data buffers. These bits
indicate whether the buffers are full, partially full or empty.
To avoid undetermined conditions, always check the buffer status to determine if the access can be made. The status
bits in the SPORT_STAT_A.DXS field always reflect the FIFO status.
Three complete 32-bit words can be stored in the receive buffer while the fourth word is being shifted in. Therefore,
four complete words can be received without the receive buffer being read, before an overflow occurs. After receiving
the fourth word completely, the shift register contents overwrite the third word if the first word has not been read
out (by the processor core or the DMA controller). When this happens, the receive overflow status is flagged
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPORT Data Buffers
through the error status bits of the SPORT_STAT_A.DERR register. The overflow status is generated after the last bit
of the fourth word is received.
Data Buffer Packing
When the SPORT is configured as a receiver with a serial data word length of 16 or less or even 8 or less, then
received data words may be packed into a 32-bit word. Similarly, if the SPORT is configured as transmitter with a
serial data word length of 16 or less, then 32-bit words being transmitted may be unpacked into two 16-bit words or
four 8 bit words. This feature is selected by the SPORT_CTL_x.PACK (SPORT_CTL_A.PACK or
SPORT_CTL_B.PACK) bit.
NOTE: If packing is not enabled for lower length transfers, bus bandwidth as well as FIFO buffers are not efficiently
used.
When SPORT_CTL_x.PACK= 01, four successive words received are packed into a single 32-bit word, or each 32bit word is unpacked and transmitted as four 8-bit words. The words with less than 16-bit are packed as [SLEN: 0],
[(SLEN+8):8], [(SLEN+16):16] and [(SLEN+24):24]. This applies to both receive (packing) and transmit (unpacking) operations. Following diagram shows the 8 bit packing. The dark region corresponds to the packed bits.
32 SLEN+24
24
SLEN+16
16 SLEN+8
8
SLEN
0
Figure 11-12: Packed Data in case of 8-Bit Packing
When PACK is assigned 10, two successive words received are packed into a single 32-bit word, or each 32-bit word
is unpacked and transmitted as two 16-bit words. The words with less than 16-bit are packed as [SLEN: 0] and
[(SLEN+16):16].This applies to both receive (packing) and transmit (unpacking) operations. Following figure shows
the 16 bit packing.
32
SLEN+16
16
SLEN
0
Figure 11-13: Packed Data in case of 16-Bit Packing
In packing, transmit and receive interrupts are generated for the 32-bit packed words, not for each 16-bit word or 8
bit word. The packing feature enables efficient utilization of the system bandwidth.
NOTE: When packing is enabled, the word length must be programmed lesser than the programmed packing. For
instance, if 8 bit packing is programmed, SLEN should be less than or equal to 7 and if 16 bit packing is programmed, SLEN should be less than or equal to 15.
SPORT Interrupts and Exceptions
Each SPORT half has an interrupt associated with it. To determine the source of an interrupt, applications should
check the interrupt status register. This section describes the various interrupt sources. In core mode, SPORT is able
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–19
SPORT Interrupts and Exceptions
to generate data interrupts for receive or transmit operations. Moreover, the SPORT modules generate error conditions which have a separate status bit for each interrupt source.
NOTE: To clear the interrupt signal, the corresponding status bit is written by 1. This clears the value of the status
bit, that is, the corresponding status bit becomes zero.
Error Detection
When the serial port is configured as a transmitter, the SPORT_STAT_A.DERR or SPORT_STAT_B.DERR bit provides transmit data buffer underflow status for the data path (it indicates that frame sync signal occurred when the
transmit data buffer was empty). The serial port transmits data whenever it detects a framing signal.
• 0 = No frame sync signal occurred when TX data buffer is empty (no underflow).
• 1 = Framing signal occurred when TX buffer was empty (underflow).
Similarly, if SPORT configured as a receiver, the SPORT_STAT_A.DERR or SPORT_STAT_B.DERR bit provides receive overflow status of receive data buffer. In other words, the SPORT indicates that a channel has received new
data when the receive buffer is full, so new data overwrites existing data. The serial port receives data whenever it
detects a framing signal.
• 0 = No frame sync signal occurred when RX data buffer is full (no overflow).
• 1 = Frame sync signal occurred when RX data buffer was full (overflow).
These error conditions would occur in case of external frame sync or when the DIFS (Data independent Frame
Sync) is set.
The SPORT_IEN_x.DERRMSK (SPORT_IEN_A.DERRMSK or SPORT_IEN_B.DERRMSK)(data error interrupt enable) bit can be used to unmask the status interrupt for data errors.
In addition to data underflow and data overflow errors, the status interrupt is also triggered optionally when frame
sync error is detected. The SPORT_IEN_x.FSERRMSK (SPORT_IEN_A.FSERRMSK or
SPORT_IEN_B.FSERRMSK)(frame sync error interrupt enable) bit unmasks the status interrupt for this frame sync
error. This frame sync error is generated due to premature frame sync. For more information about this, refer to
Premature Frame Sync Error Detection.
NOTE: A frame sync error is not detected when there is no active data transmit/receive and the frame sync pulse
occurs due to noise in the input signal.
System Transfer Interrupts
When SPORT is configured to transmit, an interrupt is generated when an attempt is made by the core to write into
a Transmit FIFO which is full. The SPORT_STAT_A.SYSDATERR or SPORT_STAT_B.SYSDATERR status indicates this Transmit FIFO overflow error.
Similarly, when SPORT is configured to receive, an interrupt is generated when an attempt is made by the core to
read from an empty Receive FIFO. The field SPORT_STAT_A.SYSDATERR or SPORT_STAT_B.SYSDATERR status now indicates Receive FIFO underflow error.
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
SPORT Interrupts and Exceptions
NOTE: When in DMA mode, SPORT does not produce a DMA request when Transmit FIFO is full or Receive
FIFO is empty. Thus, no interrupt is generated for DMA transfers.
Transfer Finish Interrupt (TFI)
The Transmit Finish Interrupt feature is used to signal the end of the transmission/reception. This feature can be
enabled by setting SPORT_IEN_A or SPORT_IEN_B bit. When the number of transfers programmed in
SPORT_NUMTRAN_A or SPORT_NUMTRAN_B field are finished, SPORT waits until all the data in the FIFO is transmitted out (including the transmit shift register) or received completely in the receive registers and then generates
the Transfer Finish Interrupt. This feature allows the user to determine that all data corresponding to understand
that data corresponding to the programmed number of transfers have been transmitted out or received completely
by the SPORT.
NOTE: Once the Transfer Finish Interrupt is obtained, the user can either reprogram the number of transfers or
disable the SPORT and re-enabled (if needed). If number of transfers need to be reprogrammed, the steps to be
followed are written under the section Number of Transfers. If SPORT should be re-enabled, the steps written in
following section of the SPORT Programming Model should be followed.
SPORT Programming Model
The following section provides general programming guidelines for SPORT:
• Write all the registers of SPORT with the desired values of configuration except the Control register.
• After configuration, write the control register (SPORT_CTL_A or SPORT_CTL_B) with desired configuration
for the transfer. SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN field must be programmed as 1.
• As soon as the SPORT_CTL_A.SPEN or SPORT_CTL_B.SPEN fields are written to 1, normal operation of the
SPORT can start based on the programmed configuration values.
The SPORT registers which need to be written with configuration values are:
• Write SPORT_DIV_A or SPORT_DIV_B to program the desired CLKDIV and FSDIV values.
• SPORT_CNVT_A or SPORT_CNVT_B register should only be written if the desired operation mode is Timer
enable mode.
• EN register is written according to the desired interrupts. For instance, if an interrupt is desired for an underflow/overflow error then SPORT_IEN_A or SPORT_IEN_B should be set.
• Write SPORT_NUMTRAN_A or SPORT_NUMTRAN_B with the desired number of transfers. This must not be
programmed to zero.
ADuCM302x SPORT Register Descriptions
Serial Port (SPORT) contains the following registers.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–21
ADuCM302x SPORT Register Descriptions
Table 11-3:
ADuCM302x SPORT Register List
Name
Description
SPORT_CTL_A
Half SPORT 'A' Control Register
SPORT_CTL_B
Half SPORT 'B' Control Register
SPORT_DIV_A
Half SPORT 'A' Divisor Register
SPORT_DIV_B
Half SPORT 'B' Divisor Register
SPORT_IEN_A
Half SPORT A's Interrupt Enable register
SPORT_IEN_B
Half SPORT B's Interrupt Enable register
SPORT_NUMTRAN_A
Half SPORT A Number of transfers register
SPORT_NUMTRAN_B
Half SPORT B Number of transfers register
SPORT_RX_A
Half SPORT 'A' Rx Buffer Register
SPORT_RX_B
Half SPORT 'B' Rx Buffer Register
SPORT_STAT_A
Half SPORT 'A' Status register
SPORT_STAT_B
Half SPORT 'B' Status register
SPORT_CNVT_A
Half SPORT 'A' CONVT width
SPORT_CNVT_B
Half SPORT 'B' CONVT width register
SPORT_TX_A
Half SPORT 'A' Tx Buffer Register
SPORT_TX_B
Half SPORT 'B' Tx Buffer Register
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Half SPORT 'A' Control Register
The SPORT_CTL_A contains transmit and receive control bits for SPORT half 'A', including serial port mode selection
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DIFS (R/W)
Data-Independent Frame Sync
SPEN (R/W)
Serial Port Enable
IFS (R/W)
Internal Frame Sync
FSMUXSEL (R/W)
Frame Sync Multiplexer Select
FSR (R/W)
Frame Sync Required
CKMUXSEL (R/W)
Clock Multiplexer Select
CKRE (R/W)
Clock Rising Edge
LSBF (R/W)
Least-Significant Bit First
OPMODE (R/W)
Operation mode
SLEN (R/W)
Serial Word Length
ICLK (R/W)
Internal Clock
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAEN (R/W)
DMA Enable
LFS (R/W)
Active-Low Frame Sync
SPTRAN (R/W)
Serial Port Transfer Direction
LAFS (R/W)
Late Frame Sync
GCLKEN (R/W)
Gated Clock Enable
PACK (R/W)
Packing Enable
FSERRMODE (R/W)
Frame Sync Error Operation
Figure 11-14: SPORT_CTL_A Register Diagram
Table 11-4:
SPORT_CTL_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26 DMAEN
(R/W)
DMA Enable.
This bit tells whether the half SPORT would send DMA request signals when the
Transmit FIFO needs any data or Receive FIFO wants to send any data to DMA
0 DMA requests are diabled
1 DMA requests are enabled
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–23
ADuCM302x SPORT Register Descriptions
Table 11-4:
SPORT_CTL_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
25 SPTRAN
(R/W)
Serial Port Transfer Direction.
The SPORT_CTL_A.SPTRAN bit selects the transfer direction (receive or transmit) for
the half SPORT's channels.
0 Receive
1 Transmit
21 GCLKEN
(R/W)
Gated Clock Enable.
The SPORT_CTL_A.GCLKEN bit enables gated clock operation for the half SPORT.
When SPORT_CTL_A.GCLKEN is enabled, the SPORT clock is active when the
SPORT is transferring data or when the frame sync changes (transitions to active
state).
0 Disable
1 Enable
20 FSERRMODE
(R/W)
Frame Sync Error Operation.
The SPORT_CTL_A.FSERRMODE bit decides the way the SPORT responds when a
frame sync error occurs.
0 Flag the Frame Sync error and continue normal operation
1 When frame Sync error occurs, discard the receive data
19:18 PACK
(R/W)
Packing Enable.
The SPORT_CTL_A.PACK bit enables the half SPORT to perform 16- to 32-bit or 8to 32- bit packing on received data and to perform 32- to 16-bit or 32- to 8- bit unpacking on transmitted data.
0 Disable
1 8-bit packing enable
2 16-bit packing enable
3 Reserved
17 LAFS
(R/W)
Late Frame Sync.
The SPORT_CTL_A.LAFS bit selects whether the half SPORT generates a late frame
sync (SPORT_AFS during first data bit) or generates an early frame sync signal
(SPORT_AFS during serial clock cycle before first data bit).
0 Early frame sync
1 Late frame sync
11–24
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Table 11-4:
SPORT_CTL_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
16 LFS
(R/W)
Active-Low Frame Sync.
The SPORT_CTL_A.LFS bit selects whether the half SPORT uses active low or active
high frame sync.
0 Active high frame sync
1 Active low frame sync
15 DIFS
(R/W)
Data-Independent Frame Sync.
The SPORT_CTL_A.DIFS bit selects whether the half SPORT uses a data-independent or data-dependent frame sync. When using a data-independent frame sync, the
half SPORT generates the sync at the interval selected by SPORT_DIV_A.FSDIV.
When using a data-dependent frame sync, the half SPORT generates the sync on the
selected interval when the transmit buffer is not empty or when the receive buffer is
not full.
0 Data-dependent frame sync
1 Data-independent frame sync
14 IFS
(R/W)
Internal Frame Sync.
The SPORT_CTL_A.IFS bit selects whether the half SPORT uses an internal frame
sync or uses an external frame sync.
Note that the externally-generated frame sync does not need to be synchronous with
the processor's system clock.
0 External frame sync
1 Internal frame sync
13 FSR
(R/W)
Frame Sync Required.
The SPORT_CTL_A.FSR selects whether or not the half SPORT requires frame sync
for data transfer.
0 No frame sync required
1 Frame sync required
12 CKRE
(R/W)
Clock Rising Edge.
The SPORT_CTL_A.CKRE selects the rising or falling edge of the SPORT_ACLK clock
for the half SPORT to sample receive data and frame sync.
0 Clock falling edge
1 Clock rising edge
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–25
ADuCM302x SPORT Register Descriptions
Table 11-4:
SPORT_CTL_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 OPMODE
(R/W)
Operation mode.
The SPORT_CTL_A.OPMODE bit selects whether the half SPORT operates in DSP
standard mode or in Timer enable mode
0 DSP standard
1 Timer_enable mode
10 ICLK
(R/W)
Internal Clock.
The SPORT_CTL_A.ICLK bit selects whether the half SPORT uses an internal or external clock.
0 External clock
1 Internal clock
8:4 SLEN
(R/W)
Serial Word Length.
The SPORT_CTL_A.SLEN bits selects word length in bits for the half SPORT's data
transfers. Word may be from 4- to 32-bits in length. The formula for selecting the
word length in bits is:
SPORT_CTL_A.SLEN = (serial word length in bits) - 1
3 LSBF
(R/W)
Least-Significant Bit First.
The SPORT_CTL_A.LSBF bit selects whether the half SPORT transmits or receives
data LSB first or MSB first.
0 MSB first sent/received
1 LSB first sent/received
2 CKMUXSEL
(R/W)
Clock Multiplexer Select.
The SPORT_CTL_A.CKMUXSEL bit enables multiplexing of the half SPORT' serial
clock. In this mode, the serial clock of the related half SPORT is used instead of the
half SPORT's own serial clock. For example, if SPORT_CTL_A.CKMUXSEL is enabled,
half SPORT 'A' uses SPORT_BCLK instead of SPORT_ACLK.
0 Disable serial clock multiplexing
1 Enable serial clock multiplexing
1 FSMUXSEL
(R/W)
Frame Sync Multiplexer Select.
The SPORT_CTL_A.FSMUXSEL bit enables multiplexing of the half SPORT' frame
sync. In this mode, the frame sync of the related half SPORT is used instead of the half
SPORT's own frame sync. For example, if SPORT_CTL_A.FSMUXSEL is enabled, half
SPORT 'A' uses SPORT_BFS instead of SPORT_AFS.
0 Disable frame sync multiplexing
1 Enable frame sync multiplexing
11–26
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Table 11-4:
SPORT_CTL_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 SPEN
(R/W)
Serial Port Enable.
The SPORT_CTL_A.SPEN bit enables the half SPORT's data channel. Note: When
this bit is cleared (changes from =1 to =0), the half SPORT automatically flushes the
channel's data buffers and disables the clock and frame sync and the counters inside
SPORT.
0 Disable
1 Enable
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–27
ADuCM302x SPORT Register Descriptions
Half SPORT 'B' Control Register
The SPORT_CTL_B contains transmit and receive control bits for SPORT half 'B', including serial port mode selection for the channels. The function of some bits in SPORT_CTL_B vary, depending on the SPORT's operating
mode. For more information, see the SPORT operating modes description. If reading reserved bits, the read value is
the last written value to these bits or is the reset value of these bits.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DIFS (R/W)
Data-Independent Frame Sync
SPEN (R/W)
Serial Port Enable
IFS (R/W)
Internal Frame Sync
LSBF (R/W)
Least-Significant Bit First
FSR (R/W)
Frame Sync Required
SLEN (R/W)
Serial Word Length
CKRE (R/W)
Clock Rising Edge
ICLK (R/W)
Internal Clock
OPMODE (R/W)
Operation mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DMAEN (R/W)
DMA Enable
LFS (R/W)
Active-Low Frame Sync
SPTRAN (R/W)
Serial Port Transfer Direction
LAFS (R/W)
Late Frame Sync
GCLKEN (R/W)
Gated Clock Enable
PACK (R/W)
Packing Enable
FSERRMODE (R/W)
Frame Sync Error Operation
Figure 11-15: SPORT_CTL_B Register Diagram
Table 11-5:
SPORT_CTL_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
26 DMAEN
(R/W)
DMA Enable.
This bit tells whether the half SPORT would send DMA request signals when the
Transmit FIFO needs any data or Receive FIFO wants to send any data to DMA
0 DMA requests are diabled
1 DMA requests are enabled
11–28
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Table 11-5:
SPORT_CTL_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
25 SPTRAN
(R/W)
Serial Port Transfer Direction.
The SPORT_CTL_B.SPTRAN bit selects the transfer direction (receive or transmit) for
the half SPORT's channels.
0 Receive
1 Transmit
21 GCLKEN
(R/W)
Gated Clock Enable.
The SPORT_CTL_B.GCLKEN bit enables gated clock operation for the half SPORT
when in DSP serial mode.
When SPORT_CTL_B.GCLKEN is enabled, the SPORT clock is active when the
SPORT is transferring data or when the frame sync changes (transitions to active
state).
0 Disable
1 Enable
20 FSERRMODE
(R/W)
Frame Sync Error Operation.
The SPORT_CTL_B.FSERRMODE bit decides the way the SPORT responds when a
frame sync error occurs.
0 Flag the Frame Sync error and continue normal operation
1 When frame Sync error occurs, discard the receive data
19:18 PACK
(R/W)
Packing Enable.
The SPORT_CTL_B.PACK bit enables the half SPORT to perform 16- to 32-bit or 8to 32- bit packing on received data and to perform 32- to 16-bit or 32- to 8- bit unpacking on transmitted data.
0 Disable
1 8-bit packing enable
2 16-bit packing enable
3 Reserved
17 LAFS
(R/W)
Late Frame Sync.
When the half SPORT is in DSP standard mode (SPORT_CTL_B.OPMODE =0) , the
SPORT_CTL_B.LAFS bit selects whether the half SPORT generates a late frame sync
(SPORT_BFS during first data bit) or generates an early frame sync signal
(SPORT_BFS during serial clock cycle before first data bit).
0 Early frame sync
1 Late frame sync
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–29
ADuCM302x SPORT Register Descriptions
Table 11-5:
SPORT_CTL_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
16 LFS
(R/W)
Active-Low Frame Sync.
When the half SPORT is in DSP standard mode (SPORT_CTL_B.OPMODE =0), the
SPORT_CTL_B.LFS bit selects whether the half SPORT uses active low or active high
frame sync.
0 Active high frame sync
1 Active low frame sync
15 DIFS
(R/W)
Data-Independent Frame Sync.
The SPORT_CTL_B.DIFS bit selects whether the half SPORT uses a data-independent or data-dependent frame sync. When using a data-independent frame sync, the
half SPORT generates the sync at the interval selected by SPORT_DIV_B.FSDIV.
When using a data-dependent frame sync, the half SPORT generates the sync on the
selected interval when the transmit buffer is not empty or when the receive buffer is
not full.
0 Data-dependent frame sync
1 Data-independent frame sync
14 IFS
(R/W)
Internal Frame Sync.
The SPORT_CTL_B.IFS bit selects whether the half SPORT uses an internal frame
sync or uses an external frame sync.
Note that the externally-generated frame sync does not need to be synchronous with
the processor's system clock.
0 External frame sync
1 Internal frame sync
13 FSR
(R/W)
Frame Sync Required.
The SPORT_CTL_B.FSR selects whether or not the half SPORT requires frame sync
for data transfer.
0 No frame sync required
1 Frame sync required
12 CKRE
(R/W)
Clock Rising Edge.
The SPORT_CTL_B.CKRE selects the rising or falling edge of the SPORT_BCLK clock
for the half SPORT to sample receive data and frame sync.
0 Clock falling edge
1 Clock rising edge
11–30
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Table 11-5:
SPORT_CTL_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 OPMODE
(R/W)
Operation mode.
The SPORT_CTL_B.OPMODE bit selects whether the half SPORT operates in DSP
standard mode or timer enable mode
0 DSP standard mode
1 Timer Enable mode
10 ICLK
(R/W)
Internal Clock.
When the half SPORT is in DSP standard mode (SPORT_CTL_B.OPMODE =0), the
SPORT_CTL_B.ICLK bit selects whether the half SPORT uses an internal or external
clock. For internal clock enabled, the half SPORT generates the SPORT_BCLK clock
signal, and the SPORT_BCLK is an output. The SPORT_DIV_B.CLKDIV serial clock
divisor value determines the clock frequency. For internal clock disabled, the
SPORT_BCLK clock signal is an input, and the serial clock divisor is ignored. Note that
the externally-generated serial clock does not need to be synchronous with the processor's system clock.
0 External clock
1 Internal clock
8:4 SLEN
(R/W)
Serial Word Length.
The SPORT_CTL_B.SLEN bits selects word length in bits for the half SPORT's data
transfers. Word may be from 4- to 32-bits in length. The formula for selecting the
word length in bits is:
SPORT_CTL_B.SLEN = (serial word length in bits) - 1
3 LSBF
(R/W)
Least-Significant Bit First.
The SPORT_CTL_B.LSBF bit selects whether the half SPORT transmits or receives
data LSB first or MSB first.
0 MSB first sent/received
1 LSB first sent/received
0 SPEN
(R/W)
Serial Port Enable.
The SPORT_CTL_B.SPEN bit enables the half SPORT's data channel. Note: When
this bit is cleared (changes from =1 to =0), the half SPORT automatically flushes the
channel's data buffers and disables the clock and frame sync and the counters inside
SPORT.
0 Disable
1 Enable
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–31
ADuCM302x SPORT Register Descriptions
Half SPORT 'A' Divisor Register
The SPORT_DIV_A contains divisor values that determine frequencies of internally-generated clocks and frame
syncs for half SPORT 'A'.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CLKDIV (R/W)
Clock Divisor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FSDIV (R/W)
Frame Sync Divisor
Figure 11-16: SPORT_DIV_A Register Diagram
Table 11-6:
SPORT_DIV_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:16 FSDIV
(R/W)
15:0 CLKDIV
(R/W)
11–32
Frame Sync Divisor.
The SPORT_DIV_A.FSDIV bits select the number of transmit or receive clock cycles
that the half SPORT counts before generating a frame sync pulse. The half SPORT
counts serial clock cycles whether these are from an internally- or an externally-generated serial clock. This field is used to measure the number of serial clock cycles before
generating CONVT signal in timer enable mode.
Clock Divisor.
The SPORT_DIV_A.CLKDIV bits select the divisor that the half SPORT uses to calculate the serial clock (SPORT_ACLK) from the processor system clock (PCLK).
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Half SPORT 'B' Divisor Register
The SPORT_DIV_B contains divisor values that determine frequencies of internally-generated clocks and frame
syncs for SPORT half 'B'.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CLKDIV (R/W)
Clock Divisor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
FSDIV (R/W)
Frame Sync Divisor
Figure 11-17: SPORT_DIV_B Register Diagram
Table 11-7:
SPORT_DIV_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:16 FSDIV
(R/W)
15:0 CLKDIV
(R/W)
Frame Sync Divisor.
The SPORT_DIV_B.FSDIV bits select the number of transmit or receive clock cycles
that the half SPORT counts before generating a frame sync pulse. The half SPORT
counts serial clock cycles whether these are from an internally- or an externally-generated serial clock. This field is used to measure the number of serial clock cycles before
generating CONVT signal in timer enable mode.
Clock Divisor.
The SPORT_DIV_B.CLKDIV bits select the divisor that the half SPORT uses to calculate the serial clock (SPORT_BCLK) from the processor system clock (PCLK).
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–33
ADuCM302x SPORT Register Descriptions
Half SPORT A's Interrupt Enable register
This register contains all the fields related to the Enable given for the various interrupts related to errors and data
requests present in the half SPORT A.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SYSDATERR (R/W)
Data error for system writes or reads
TF (R/W)
Transfer Finish Interrupt Enable
DATA (R/W)
Data request interrupt to the core
DERRMSK (R/W)
Data Error (Interrupt) Mask
FSERRMSK (R/W)
Frame Sync Error (Interrupt) Mask
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-18: SPORT_IEN_A Register Diagram
Table 11-8:
SPORT_IEN_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4 SYSDATERR
(R/W)
Data error for system writes or reads.
This field enables the half SPORT to generate the data error interrupt for the system
write resulting in TX FIFO overflow or system read resulting in a RX FIFO underflow.
0 Disable System data error interrupt
1 Enable System data error interrupt
3 DATA
(R/W)
Data request interrupt to the core.
This bit enables interrupt given to the core for a data write into transmit FIFO for
transmit or data read from the Receive FIFO.
0 Data request interrupt disable
1 Data request interrupt enable
2 FSERRMSK
(R/W)
Frame Sync Error (Interrupt) Mask.
The SPORT_IEN_A.FSERRMSK unmasks (enables) the half SPORT to generate the
frame sync error interrupt.
0 Mask (disable)
1 Unmask (enable)
11–34
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Table 11-8:
SPORT_IEN_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 DERRMSK
(R/W)
Data Error (Interrupt) Mask.
The SPORT_IEN_A.DERRMSK unmasks (enables) the half SPORT to generate the data error interrupt for the data channel.
0 Mask (disable)
1 Unmask (enable)
0 TF
(R/W)
Transfer Finish Interrupt Enable.
The SPORT_IEN_A.TF bit selects when the half SPORT issues its transmission complete interrupt once the programmed number of transfers are finished. When enabled
(SPORT_IEN_A.TF =1), when the last bit of last word of the programmed number of
transfers is shifted out or received completely, an interrupt is generated. When disabled
(SPORT_IEN_A.TF =0), no interrupt is generated by SPORT.
0 Transfer finish Interrupt is disabled
1 Transfer Finish Interrupt is Enabled
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–35
ADuCM302x SPORT Register Descriptions
Half SPORT B's Interrupt Enable register
This register contains all the fields related to the Enable given for the various interrupts related to errors and data
requests present in the half SPORT B.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SYSDATERR (R/W)
Data error for system writes or reads
TF (R/W)
Transmit Finish Interrupt Enable
DATA (R/W)
Data request interrupt to the core
DERRMSK (R/W)
Data Error (Interrupt) Mask
FSERRMSK (R/W)
Frame Sync Error (Interrupt) Mask
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-19: SPORT_IEN_B Register Diagram
Table 11-9:
SPORT_IEN_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4 SYSDATERR
(R/W)
Data error for system writes or reads.
This field enables the half SPORT to generate the data error interrupt for the system
write resulting in TX FIFO overflow or system read resulting in a RX FIFO underflow.
0 Disable System data error interrupt
1 Enable System data error interrupt
3 DATA
(R/W)
Data request interrupt to the core.
This bit enables interrupt given to the core for a data write into transmit FIFO for
transmit or data read from the Receive FIFO.
0 Data request interrupt disable
1 Data request interrupt enable
2 FSERRMSK
(R/W)
Frame Sync Error (Interrupt) Mask.
The SPORT_IEN_B.FSERRMSK unmasks (enables) the half SPORT to generate the
frame sync error interrupt.
0 Mask (disable)
1 Unmask (enable)
11–36
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Table 11-9:
SPORT_IEN_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 DERRMSK
(R/W)
Data Error (Interrupt) Mask.
The SPORT_IEN_B.DERRMSK unmasks (enables) the half SPORT to generate the data error interrupt for the data channel.
0 Mask (disable)
1 Unmask (enable)
0 TF
(R/W)
Transmit Finish Interrupt Enable.
The SPORT_IEN_B.TF bit selects when the half SPORT issues its transmission complete interrupt once the programmed number of transfers are finished. When enabled
(SPORT_IEN_B.TF =1), when the last bit of last word of the programmed number of
transfers is shifted out or received completely, an interrupt is generated. When disabled
(SPORT_IEN_B.TF =0), no interrupt is generated by SPORT
0 Transfer Finish Interrupt is disabled
1 Transfer Finish Interrupt is Enabled
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–37
ADuCM302x SPORT Register Descriptions
Half SPORT A Number of transfers register
This register specifies the number of transfers of words to transfer or receive depending on SPORT_CTL_A.SPTRAN.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Number of transfers (Half SPORT A)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-20: SPORT_NUMTRAN_A Register Diagram
Table 11-10:
SPORT_NUMTRAN_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
11:0 VALUE
Number of transfers (Half SPORT A).
(R/W)
11–38
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Half SPORT B Number of transfers register
This register specifies the number of transfers of the words to transfer or receive depending on
SPORT_CTL_B.SPTRAN.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Number of transfers (Half SPORT A)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-21: SPORT_NUMTRAN_B Register Diagram
Table 11-11:
SPORT_NUMTRAN_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
11:0 VALUE
Number of transfers (Half SPORT A).
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–39
ADuCM302x SPORT Register Descriptions
Half SPORT 'A' Rx Buffer Register
The SPORT_RX_A register buffers the half SPORT's receive data. This buffer becomes active when the half SPORT
is configured to receive data. After a complete word has been received in receive shifter, it is placed into the
SPORT_RX_A register. This data can be read in core mode (in interrupt-based or polling-based mechanism) or directly DMA'd into processor memory using DMA controller.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
Receive Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R)
Receive Buffer
Figure 11-22: SPORT_RX_A Register Diagram
Table 11-12:
SPORT_RX_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/NW)
11–40
Receive Buffer.
The SPORT_RX_A.VALUE bits hold the half SPORT's channel receive data.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Half SPORT 'B' Rx Buffer Register
The SPORT_RX_B register buffers the half SPORT's channel receive data. This buffer becomes active when the half
SPORT is configured to receive data. After a complete word has been received in receive shifter, it is placed into the
SPORT_RX_B register. This data can be read in core mode or directly DMA'd into processor memory using DMA
controller.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
Receive Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R)
Receive Buffer
Figure 11-23: SPORT_RX_B Register Diagram
Table 11-13:
SPORT_RX_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/NW)
Receive Buffer.
The SPORT_RX_B.VALUE bits hold the half SPORT's receive data.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–41
ADuCM302x SPORT Register Descriptions
Half SPORT 'A' Status register
This register contains all the status fields in the half SPORT A. Detected errors are frame sync violations or buffer
over/underflow conditions.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DXS (R)
Data Transfer Buffer Status
TFI (R/W1C)
Transmit Finish Interrupt Status
SYSDATERR (R/W1C)
System Data Error Status
DERR (R/W1C)
Data Error Status
DATA (R)
Data Buffer status
FSERR (R/W1C)
Frame Sync Error Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-24: SPORT_STAT_A Register Diagram
Table 11-14:
SPORT_STAT_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9:8 DXS
(R/NW)
Data Transfer Buffer Status.
The SPORT_STAT_A.DXS indicates the status of the half SPORT A's data buffer.
0 Empty
1 Reserved
2 Partially full
3 Full
4 SYSDATERR
(R/W1C)
System Data Error Status.
This bit indicates the error status for the half SPORT's data buffers during system
transfer of data. For transmit (SPORT_CTL_A.SPTRAN =1),
SPORT_STAT_A.SYSDATERR indicates transmit overflow status. For receive
(SPORT_CTL_A.SPTRAN =0), SPORT_STAT_A.SYSDATERR indicates receive underflow status.
0 No Error
1 System Transfer overflow for TXFIFO or System Transfer underflow for RXFIFO
3 DATA
(R/NW)
Data Buffer status.
This field indicates only the status of the data buffers in Half SPORT A.
0 Transmit FIFO is full or receive FIFO is empty
1 Transmit FIFO is not full or receive FIFO is not empty
11–42
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Table 11-14:
SPORT_STAT_A Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 FSERR
(R/W1C)
Frame Sync Error Status.
The SPORT_STAT_A.FSERR bit indicates that the half SPORT has detected a frame
sync when the bit count (bits remaining in the frame) is non-zero or it has seen frame
sync active for less than the word length in case of late frame sync.
0 No error
1 Frame Sync Error occurred
1 DERR
(R/W1C)
Data Error Status.
The SPORT_STAT_A.DERR bit indicates the error status for the half SPORT's data
buffers. During transmit (SPORT_CTL_A.SPTRAN =1), SPORT_STAT_A.DERR indicates transmit underflow status. During receive (SPORT_CTL_A.SPTRAN =0),
SPORT_STAT_A.DERR indicates receive overflow status.
0 No error
1 Error (transmit underflow or receive overflow)
0 TFI
(R/W1C)
Transmit Finish Interrupt Status.
The SPORT_STAT_A.TFI bit shows when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When it is
1, the last bit of last word of the programmed number of transfers is shifted out or
received completely. When 0, the total number of transfers are not finished.
0 Last bit is not transmitted/received
1 Last bit Transmitted/received
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–43
ADuCM302x SPORT Register Descriptions
Half SPORT 'B' Status register
This register contains all the status fields present in the half SPORT B. Detected errors are frame sync violations or
buffer over/underflow conditions.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DXS (R)
Data Transfer Buffer Status
TFI (R/W1C)
Transmit Finish Interrupt Status
SYSDATERR (R/W1C)
System Data Error Status
DERR (R/W1C)
Data Error Status
DATA (R/W1C)
Data Buffer status
FSERR (R/W1C)
Frame Sync Error Status
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-25: SPORT_STAT_B Register Diagram
Table 11-15:
SPORT_STAT_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9:8 DXS
(R/NW)
Data Transfer Buffer Status.
The SPORT_STAT_B.DXS indicates the status of the half SPORT B's data buffer.
0 Empty
1 Reserved
2 Partially full
3 Full
4 SYSDATERR
(R/W1C)
System Data Error Status.
This bit indicates the error status for the half SPORT's data buffers during system
transfer of data. For transmit (SPORT_CTL_A.SPTRAN =1),
SPORT_STAT_B.SYSDATERR indicates transmit overflow status. For receive
(SPORT_CTL_A.SPTRAN =0), SPORT_STAT_B.SYSDATERR indicates receive underflow status.
0 No Error
1 System Transfer overflow for TXFIFO or System Transfer underflow for RXFIFO
3 DATA
(R/W1C)
Data Buffer status.
This field indicates only the status of the data buffers in Half SPORT B.
0 Transmit FIFO is full or receive FIFO is empty
1 Transmit FIFO is not full or receive FIFO is not empty
11–44
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Table 11-15:
SPORT_STAT_B Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 FSERR
(R/W1C)
Frame Sync Error Status.
The SPORT_STAT_B.FSERR bit indicates that the half SPORT has detected a frame
sync when the bit count (bits remaining in the frame) is non-zero or it has seen frame
sync active for less than the word length in case of late frame sync.
0 No error
1 Error (non-zero bit count at frame sync)
1 DERR
(R/W1C)
Data Error Status.
The SPORT_STAT_B.DERR bit indicates the error status for the half SPORT B's data
buffers. During transmit (SPORT_CTL_B.SPTRAN =1), SPORT_STAT_B.DERR indicates transmit underflow status. During receive (SPORT_CTL_B.SPTRAN =0),
SPORT_STAT_B.DERR indicates receive overflow status.
0 No error
1 Error (transmit underflow or receive overflow)
0 TFI
(R/W1C)
Transmit Finish Interrupt Status.
The SPORT_STAT_B.TFI bit shows when the half SPORT issues its transmission
complete interrupt once the programmed number of transfers are finished. When it is
1, the last bit of last word of the programmed number of transfers is shifted out or
received completely. When 0, the total number of transfers are not finished.
0 Last bit is not transmitted/received
1 Last bit Transmitted/received
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–45
ADuCM302x SPORT Register Descriptions
Half SPORT 'A' CONVT width
This register contains the settings related to the CONVT signal for Half SPORT A
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
POL (R/W)
Polarity of the Convt signal
WID (R/W)
CONVT signal width: Half SPORT A
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNVT2FS (R/W)
CONVT to FS duration: Half SPORT A
Figure 11-26: SPORT_CNVT_A Register Diagram
Table 11-16:
SPORT_CNVT_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:16 CNVT2FS
(R/W)
8 POL
(R/W)
CONVT to FS duration: Half SPORT A.
This field contains the value of the number of clocks which would be programmed
corresponding to the desired time duration from assertion of CONVT signal to Frame
sync signal for Half SPORT A
Polarity of the Convt signal.
This bit decides the polarity of the Convt signal
0 Active High Polarity
1 Active low Polarity
3:0 WID
(R/W)
11–46
CONVT signal width: Half SPORT A.
This field contains the value of the number of serial clocks for which CONVT signal
should be active for Half SPORT A
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Half SPORT 'B' CONVT width register
This register contains the settings related to the CONVT signal for Half SPORT B
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
POL (R/W)
Polarity of the Convt signal
WID (R/W)
CONVT signal width: Half SPORT B
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CNVT2FS (R/W)
CONVT to FS duration: Half SPORT B
Figure 11-27: SPORT_CNVT_B Register Diagram
Table 11-17:
SPORT_CNVT_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
23:16 CNVT2FS
(R/W)
8 POL
(R/W)
CONVT to FS duration: Half SPORT B.
This field contains the value of the number of clocks which would be programmed
corresponding to the desired time duration from assertion of CONVT signal to Frame
sync signal for Half SPORT B
Polarity of the Convt signal.
This bit decides the polarity of the Convt signal
0 Active High Polarity
1 Active low Polarity
3:0 WID
(R/W)
CONVT signal width: Half SPORT B.
This field contains the value of the number of clocks which would be programmed
corresponding to the desired width of the CONVT signal for Half SPORT B
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–47
ADuCM302x SPORT Register Descriptions
Half SPORT 'A' Tx Buffer Register
The SPORT_TX_A register buffers the half SPORT's transmit data. This register must be loaded with the data to be
transmitted if the half SPORT is configured to transmit. Either a program running on the processor core may load
the data into the buffer (word-by-word process) or the DMA controller may automatically load the data into the
buffer (DMA process).
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Transmit Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Transmit Buffer
Figure 11-28: SPORT_TX_A Register Diagram
Table 11-18:
SPORT_TX_A Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(RX/W)
11–48
Transmit Buffer.
The SPORT_TX_A.VALUE bits hold the half SPORT's channel transmit data.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x SPORT Register Descriptions
Half SPORT 'B' Tx Buffer Register
The SPORT_TX_B register buffers the half SPORT's channel transmit data. This register must be loaded with the
data to be transmitted. Either a program running on the processor core may load the data into the buffer (word-byword process) or the DMA controller may automatically load the data into the buffer (DMA process).
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Transmit Buffer
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Transmit Buffer
Figure 11-29: SPORT_TX_B Register Diagram
Table 11-19:
SPORT_TX_B Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(RX/W)
Transmit Buffer.
The SPORT_TX_B.VALUE bits hold the half SPORT's transmit data.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
11–49
ADC Subsystem
12 ADC Subsystem
The ADuCM302x processor incorporates a fast, multichannel, 12-bit analog-to-digital converter (ADC) capable of
operating up to a maximum of 1.8 MSPS. The ADC controller can be setup to perform a series of conversions and
transfer data to the system using a dedicated DMA channel. This allows the processor to be in the Flexi mode (minimizing the overall device power consumption) or perform other tasks.
ADC Features
The ADC has the following features:
• 12-bit resolution.
• Programmable ADC update rate from 10 KSPS to 1.8 MSPS.
• Integrated input mux that supports up to eight channels.
• Supports temperature sensing.
• Supports battery monitoring.
• Software selectable on-chip reference voltage generation: 1.25 V, 2.5 V, VBAT.
• Software selectable internal or external reference.
• Auto Cycle Mode: Ability to automatically select a sequence of input channels for conversion.
• Averaging Function: Converted data on single or multiple channels can be averaged over up to 256 samples.
• Alert Function: Internal digital comparator for AIN0, AIN1, AIN2, and AIN3 channels. An interrupt can be
generated if the digital comparator detects an ADC result above or below the user-defined threshold.
• Supports dedicated DMA channel.
• Each channel, including temperature sensor and battery monitoring, has a dedicated data register for conversion result.
ADC Functional Description
The Figure shows the ADC subsystem.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–1
ADC Functional Description
Figure 12-1: ADC Subsystem
ADuCM302x ADC Register List
Table 12-1:
ADuCM302x ADC Register List
Name
Description
ADC_ALERT
Alert Indication
ADC_AVG_CFG
Averaging Configuration
ADC_BAT_OUT
Battery Monitoring Result
ADC_CAL_WORD
Calibration Word
ADC_CFG
ADC Configuration
ADC_CFG1
Reference Buffer Low Power Mode
ADC_CH0_OUT
Conversion Result Channel 0
ADC_CH1_OUT
Conversion Result Channel 1
ADC_CH2_OUT
Conversion Result Channel 2
ADC_CH3_OUT
Conversion Result Channel 3
ADC_CH4_OUT
Conversion Result Channel 4
ADC_CH5_OUT
Conversion Result Channel 5
ADC_CH6_OUT
Conversion Result Channel 6
ADC_CH7_OUT
Conversion Result Channel 7
ADC_CNV_CFG
ADC Conversion Configuration
ADC_CNV_TIME
ADC Conversion Time
12–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADC Functional Description
Table 12-1:
ADuCM302x ADC Register List (Continued)
Name
Description
ADC_DMA_OUT
DMA Output Register
ADC_HYS0
Channel 0 Hysteresis
ADC_HYS1
Channel 1 Hysteresis
ADC_HYS2
Channel 2 Hysteresis
ADC_HYS3
Channel 3 Hysteresis
ADC_IRQ_EN
Interrupt Enable
ADC_LIM0_HI
Channel 0 High Limit
ADC_LIM0_LO
Channel 0 Low Limit
ADC_LIM1_HI
Channel 1 High Limit
ADC_LIM1_LO
Channel 1 Low Limit
ADC_LIM2_HI
Channel 2 High Limit
ADC_LIM2_LO
Channel 2 Low Limit
ADC_LIM3_HI
Channel 3 High Limit
ADC_LIM3_LO
Channel 3 Low Limit
ADC_OVF
Overflow of Output Registers
ADC_PWRUP
ADC Power-up Time
ADC_STAT
ADC Status
ADC_TEMP1
Value of R1p25
ADC_TEMP2
Value of R2p5
ADC_TEMP_R
Value of R_virtual
ADC_TMP2_OUT
Temperature Result 2
ADC_TMP_OUT
Temperature Result
ADC_TMP_SAMP
Sampling Time for Temperature Sensor
ADC Subsystem Components
The ADC subsystem consists of the following components:
• ADC core
• ADC digital controller
• Reference buffer
• Temperature sensor
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–3
ADC Functional Description
ADC Voltage Reference Selection
The ADC can use an internal voltage reference, battery voltage, or external voltage reference for its operation.
Internal Sources
The ADuCM302x processor integrates a reference buffer that can generate either 1.25 V or 2.5 V as reference using
the integrated bandgap reference. This internal reference buffer is enabled by setting the ADC_CFG.REFBUFEN bit.
The battery voltage (VBAT) can be selected as reference by setting the ADC_CFG.VREFVBAT bit. These settings are
mutually exclusive. If the ADC_CFG.REFBUFEN and ADC_CFG.VREFVBAT bits are set, the internal reference buffer
is disabled and battery voltage (VBAT) is selected as reference voltage.
Depending on the battery range indicated by the power supply monitor, use either 2.5 V or 1.25 V as reference. The
ADC_CFG.VREFSEL bit selects the reference. If the battery voltage is above 2.75 V, select 2.5 V as reference. If the
battery voltage is less than 2.75 V, select 1.25 V as reference.
Low-Power Mode
For conversion rate less than TBD KSPS, the reference buffer offers a capability where it consumes less current when
compared with the regular operation. This mode of operation can be enabled by setting the ADC_CFG1.RBUFLP
bit.
Sink Enable
If an external bias voltage is generated that requires an inverting configuration, the reference can sink current, as
shown in ADC Subsystem Reference Buffer with Current Sink figure. A 50 uA sink current capability at 1.25 V
reference, and 100 uA sink current capability at 2.5 V reference is provided in the ADC subsystem. This can be
enabled by setting the ADC_CFG.SINKEN bit.
The Figure shows the Reference buffer with a current sink.
Figure 12-2: ADC Subsystem Reference Buffer with Current Sink
Fast Discharge of Internal Reference Buffer
For fast switching from a higher to lower reference voltage, write ADC_CFG.FAST_DISCH to 1.
For example, write ADC_CFG.FAST_DISCH to 1 while switching from:
• 2.5 V to 1.25 V
12–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADC Functional Description
• VBAT to 1.25 V
• VBAT to 2.5 V (if VBAT > 2.5 V)
External Voltage Reference
To select an external reference voltage source as ADC reference, clear the ADC_CFG.REFBUFEN and
ADC_CFG.VREFVBAT bits, and connect the external voltage reference across VREF_ADC and GND_VREFADC
pins. Ensure that the external voltage reference is not more than VBAT.
The Reference Voltage Selection table shows the programming of the various bit fields in CFG register to perform
reference voltage selection.
Table 12-2:
Reference Voltage Selection
Voltage
REFBUFEN
VREFSEL
VREFVBAT
1.25 V
1
1
0
2.5 V
1
0
0
VBAT
0
X
1
External Voltage Reference
0
X
0
NOTE: External Voltage Reference is connected to the ADC using Ext_VREF pin. This pin must not be grounded
or connected to any voltage supply. It must be floating when internal reference buffer is used.
Digital Offset Calibration
An offset correction block is used to measure and correct the offset error of the reference voltage of the ADC. For
accuracy, calibration is required.
After the ADC is powered up, to start a new calibration cycle, the ADC_CFG.STARTCAL bit must be set after ADC
is ready. The ADC_STAT.CALDONE bit is set when calibration is done. Interrupt can be enabled by setting the
ADC_IRQ_EN.CALDONE bit. The ADC_CAL_WORD register is loaded with a new calibration word at the end of calibration. This register is retained in the Hibernate mode. The ADC_CAL_WORD register can also be programmed by
the user.
NOTE: If the ADC_CAL_WORD register is programmed during conversion, the new calibration word is considered
from the next conversion cycle.
Powering the ADC
The ADC, reference buffer, and temperature sensor are powered down at the reset. The user has to explicitly power
up each of these blocks. The power-up sequence depends on the internal or external reference used.
Using External Reference or VBAT as Reference
To use the external reference or VBAT as the ADC reference, the following sequence must be employed at powerup:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–5
ADC Functional Description
1. Set the ADC_CFG.PWRUP bit to power up the ADC.
2. Set ADC_PWRUP.WAIT bits as 526/(PCLKDIVCNT of CLKCON register).
3. Set the ADC_CFG.VREFVBAT bit to use VBAT as reference voltage (if using VBAT as reference voltage).
4. Assert the ADC_CFG.EN bit and enable the ADC.
5. Wait for interrupt and write 1 to clear the ADC_STAT.RDY bit. Interrupt must be enabled by setting the
ADC_IRQ_EN.RDY bit.
6. Set the ADC_CFG.STARTCAL bit to start the calibration cycle.
The ADC subsystem is ready for operation.
Using Internal Reference Buffer
To use the internal reference buffer, the following sequence must be employed at power-up:
1. Set the ADC_CFG.PWRUP bit to power up the ADC.
2. Set ADC_PWRUP.WAIT bits as 526/(PCLKDIVCNT of CLKCON register).
3. Select 1.25 V or 2.5 V as reference voltage using the ADC_CFG.VREFSEL bit.
4. Assert the ADC_CFG.REFBUFEN bit.
5. Assert the ADC_CFG.EN bit.
6. Wait for 3.5 ms.
The ADC is ready for conversion.
One of the general-purpose timers can be used to wait for 3.5 ms. During this wait period, the part can be put
into the Flexi mode to save system power, and woken up by the GP Timer interrupt.
7. Write 1 to clear the ADC_STAT.RDY bit.
8. Set the ADC_CFG.STARTCAL bit to start the calibration cycle.
Hibernate
All components of the ADC subsystem are automatically powered down when the part goes to hibernate. This is
done to keep the power consumption minimum. After waking up from hibernate, all components must be explicitly
powered up and ready before a conversion can take place, as explained in Powering the ADC section.
However, while the ADC is in the Hibernate mode, the calibration coefficients are retained in the internal registers
of the ADC. In this way, the ADC can wake up from hibernate, and a calibrated conversion cycle can be started
immediately after the wake-up time has elapsed. A new calibration cycle, if required, can be run by asserting the
ADC_CFG.STARTCAL bit.
12–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADC Functional Description
A new calibration cycle is recommended at wake-up if the system is in the Hibernate mode for an extended period,
and the operating conditions of the ADC, temperature, and reference voltage may have changed since the last
calibration cycle.
The following register fields are retained when the chip goes into the Hibernate mode:
• CFG_VREFSEL
• CFG_VREFVBAT
• CFG_SINKEN
• PWRUP_WAIT
• CAL_WORD_VALUE
• AVG_CFG_FACTOR
• AVG_CFG_OS
• LIMx_LO_VALUE
• LIMx_HI_VALUE
• HYSx_VALUE
• HYSx_MONCYC
• TMP_SAMP_TIME
• CFG1_RBUFLP
• TEMP1_R1p25
• TEMP2_R2p5
• TEMP_R_VIRTUAL
NOTE: If a conversion is ongoing prior to the part going into the Hibernate mode, that conversion does not resume
after the part wakes up.
The ADC must be disabled before going to the Hibernate or Shutdown mode by clearing the ADC_CFG.EN bit.
Sampling and Conversion Time
The ADC can be in one of the following phases:
• Acquisition Phase: During the acquisition phase, the capacitor arrays are connected directly to the inputs to get
fully charged. The minimum required acquisition time depends on the output impedance. The timing for this
phase is programmed in the ADC_CNV_TIME.SAMPTIME bit in terms of number of clock cycles.
Acquisition phase is (SAMPTIME + 1) ACLK cycles.
The time depends on the SAMPTIME value and selected clock frequency (ACLK).
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–7
ADC Functional Description
ACLK frequency = 26 MHz / ACLKDIV
ACLKDIV can be programmed in the ACLKDIVCNT bits (8 bits) in CLKCON1 register.
• Conversion Phase: At the end of the acquisition phase, the conversion phase is initiated. The conversion is
completed by successive approximation.
NOTE: The time between two conversions must not exceed 100 us. In case, the ADC is idle for more than 100
us, a dummy conversion must be performed.
Operation
The ADC controller supports several use cases.
Single Channel Mode
The ADC can be configured to convert on a particular channel by selecting one of the channels using the
ADC_CNV_CFG.SEL bits. The ADC converts analog input, provides the CNV_DONE interrupt, and stores the result in the corresponding CHx_OUT register. A channel can be enabled by writing to the specific bit in the
ADC_CNV_CFG.SEL bits. For example, to enable channel 2, set SEL[2]. Ensure that only one bit (out of SEL[7:0],
BAT, TMP, TMP2) is set for conversion on single channel (ADC_CNV_CFG.AUTOMODE = 0).
To perform multiple conversions on a selected channel, set the ADC_CNV_CFG.MULTI bit. An interrupt is generated
if enabled, and the corresponding STAT bit is set after each conversion. The conversion output is stored in the
CHx_OUT register.
If the result is not read from the output register and the status bit is not cleared before the next conversion ends, the
conversion output overflows and new result is stored in the CHx_OUT register, resulting in data loss.
It is recommended to use DMA for multiple conversions. Delay can also be introduced between successive conversions.
NOTE: After the desired number of conversions are complete, the ADC_CNV_CFG.MULTI bit must be cleared to
stop the ADC subsystem from converting.
Auto Cycle Mode
Auto cycle mode reduces the processor overhead of sampling and reading individual channel registers. It allows the
user to select a sequence of ADC input channels and provides a single interrupt when conversions on all channels
end. Temperature sensing and battery monitoring cannot be included in the auto cycle mode. Auto cycle mode is
enabled by setting the ADC_CNV_CFG.AUTOMODE bit.
Conversions are performed starting from the lowest numbered channel to the highest numbered channel of the
channels enabled. Output for each channel is stored in the respective CHx_OUT register, and the STAT bits are set
after conversion on all channels (one sequence) is completed.
To initiate multiple conversions on selected channels, enable the ADC_CNV_CFG.MULTI bit. An interrupt is generated after each sequence completes. Delay can be introduced between successive sequences. It is recommended to
use DMA for multiple conversions due to the amount of data that can be generated.
12–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADC Functional Description
NOTE: After the desired number of conversions are complete, the ADC_CNV_CFG.MULTI bit must be cleared to
stop the ADC subsystem from converting. ADC_CNV_CFG.MULTI must be low for a minimum of one ACLK cycle.
Status bits for conversion done, alert, and overflow must be cleared before starting a next conversion.
Delay Between Conversions
The ADC_CNV_TIME.DLY bits can be programmed to set the delay between completing one sequence of channels
and starting another sequence, or multiple conversions on a single channel. This delay is in terms of number of
ACLK cycles.
Figure 12-3: Delay Between Conversions on Single Channel in Multiple Conversions Mode
Figure 12-4: Delay Between Sequences in Auto Cycle Mode
DMA
A DMA channel can be used to reduce the processor overhead by moving the ADC results directly into SRAM with
a single interrupt asserted after the required number of ADC conversions are completed. DMA can be enabled using
the ADC_CNV_CFG.DMAEN bit. The conversion result must be read from the ADC_DMA_OUT.RESULT bits. The
DMA channel can be programmed for a given number of conversions. The processor can be in the Flexi mode during this period, until the programmed number of conversions is completed and the DMA done interrupt is received.
For more information, refer to the Programming Flow section.
Interrupts
The ADC controller has an interrupt associated with it. The interrupt status register indicates the source of an interrupt. When DMA is not used, the ADC controller generates data interrupts after a conversion.
NOTE: All interrupts are Write One to Clear.
Conversion
An interrupt can be generated after each conversion is complete by setting the ADC_IRQ_EN.CNVDONE bit. Corresponding DONE bit is set in the ADC_STAT register after the completion of a conversion.
Overflow
If output data is not read from the output register by the user or DMA before the next conversion is performed on
the channel, it is overwritten. The Overflow bit is set for the respective channel in the ADC_OVF register and interrupt is generated. It remains set until it cleared by the user. This interrupt must be enabled by the user by setting the
ADC_IRQ_EN.OVF bit.
NOTE: The SEL bit must remain unchanged when a conversion is being done.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–9
ADC Functional Description
Programming Flow
After powering up, calibrating (if required), and selecting resolution, the ADC is ready for conversion.
Single Conversion on Single Channel
This mode is used to perform a single conversion on a selected channel. The ADC_CNV_CFG.SINGLE bit must set
to 1 to perform the conversion. This bit works as a write one to action bit and reads as zero. DMA is not recommended for this mode, as only a single data needs to be read. The conversion result can be read from the RESULT
bits in the corresponding Channel Output register.
The following steps describe how to program the ADC for a single conversion on a single channel (say AIN2):
1. Set ADC_CNV_CFG.SEL = 0x2 and select channel 2 for conversion.
2. Set ADC_IRQ_EN.CNVDONE = 0x1 to enable interrupt when conversion is done.
3. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
4. Interrupt is generated and STAT[2] is set when conversion is done.
5. Set cnv_result = ADC_CH0_OUT.RESULT to read the conversion result.
6. Set ADC_STAT.DONE2 = 0x1 to clear the interrupt.
Figure 12-5: Single Conversion on Single Channel
Multiple Conversion on Single Channel
The ADC_CNV_CFG.MULTI bit is used to perform multiple conversions on the selected channel. The conversions
continue until this bit is deasserted. Use DMA for this mode. This mode is similar to performing multiple back-toback single conversions on the channel with the added overhead of reading the data (else, it is overwritten) and restart conversion. When using DMA, the number of conversions to be run must be programmed in the count descriptor of the DMA.
The following steps describe how to program the ADC for a multiple conversion on a single channel (say AIN2):
1. Set ADC_CNV_CFG.SEL = 0x2 and select channel 2 for conversion.
2. Set the following DMA configurations:
a. DMA count = 2 for three conversions (DMA count = number of conversions – 1)
b. Source Address = Address of ADC_DMA_OUT register
c. Source Size = Halfword
d. Destination address of DMA as SRAM memory location address to store the conversion result
12–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADC Functional Description
e. Program the required increment in the destination address.
3. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA.
4. Set ADC_CNV_TIME.DLY = 0x14 and set the delay between two conversions.
5. Set ADC_CNV_CFG.MULTI = 0x1 to start the conversion.
dma_done is generated after three conversions (count = 2).
6. Set ADC_CNV_CFG.MULTI = 0 to clear MULTI and disable further conversions in ISR.
The conversion results can be read from the SRAM.
Figure 12-6: Multiple Conversion on Single Channel
Single Conversion in Auto Cycle Mode
Set the appropriate ADC_CNV_CFG.SEL channel bits to enable the channels included in the sequence.
The following steps describe how to program the ADC for a single conversion on a series of channels in auto cycle
mode (say AIN2, AIN4, and AIN7):
1. Set ADC_CNV_CFG.SEL = 0x94.
2. Set the following DMA configurations:
a. DMA count = 2, for three conversions (DMA count = number of conversions – 1)
b. Source Address = Address of ADC_DMA_OUT register
c. Source Size = Halfword
d. Destination address of DMA as SRAM memory location address to store the conversion result
e. Program the required increment in the destination address.
3. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA (if used).
4. Set ADC_CNV_CFG.AUTOMODE = 0x1.
5. Set ADC_CNV_TIME.DLY = 0x0.
6. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
dma_done is generated after conversion.
The conversion results can be read from the SRAM or respective Channel Out register.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–11
ADC Functional Description
Figure 12-7: Single Conversion in Auto Cycle Mode
Multiple Conversions in Auto Cycle Mode
Program the number of sequences to be run in the count descriptor of the DMA.
The following steps describe how to program the ADC for a multiple conversion on a series of channels in auto
cycle mode (say AIN0, AIN2, and AIN3):
1. Set ADC_CNV_CFG.SEL = 0x09.
2. Set ADC_CNV_TIME.DLY = 0x7E.
3. Set the following DMA configurations:
a. Source Address = Address of ADC_DMA_OUT register
b. Source Size = Halfword
c. Destination address of DMA as SRAM memory location address to store the conversion result
d. Program the required increment in the destination address.
e. count =1, for two sequences
4. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA (if used).
5. Set ADC_CNV_CFG.MULTI = 0x1 to start the conversion.
dma_done is generated after conversion.
6. Set ADC_CNV_CFG.MULTI = 0 to disable further conversions.
The conversion results can be read from the SRAM or respective Channel Out register.
Figure 12-8: Multiple Conversions in Auto Cycle Mode
Temperature Sensor
The ADC subsystem provides a temperature sensor that measures die temperature. To enable the temperature sensing, set the ADC_CFG.TMPEN bit. Wait for 300 us before starting the conversion. The temperature sensor can be
enabled along with the ADC or the reference buffer to save time.
12–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADC Functional Description
This temperature sensor is not designed for use as an absolute ambient temperature calculator. It is used as an approximate indicator of temperature of the ADuCM302x die.
Program the ADC_CNV_TIME.SAMPTIME bit to provide an acquisition time of 65 us.
Temperature can measured using the following modes.
Direct Mode
The following steps describe how to measure temperature using Direct Mode:
1. Set the ADC_CNV_CFG.TMP bit to 1.
2. Set the ADC_CNV_CFG.SINGLE bit.
3. The ADC_STAT.TMPDONE bit is set after conversion.
Interrupt is given if the ADC_IRQ_EN.CNVDONE bit is set.
4. Output code can be read from the ADC_TMP_OUT register.
Multiple conversions can be done by setting the ADC_CNV_CFG.MULTI bit instead of
ADC_CNV_CFG.SINGLE bit.
Temperature can be calculated as:
• For Vref = 1.25 V:
T(⁰C) = (adcoutcode) * R1p25 - Voff * 212)/(idealsensitivity1p25) * 212) - 273.15
• For Vref = 2.5 V:
T(⁰C) = (adcoutcode) * R2p5 - Voff * 212)/(idealsensitivity2p5)* 212) - 273.15
where,
• adcoutcode = Conversion output
• idealsensitivity1p25 = 0.001394433
• idealsensitivity2p5 = 0.001394433
• R1p25 = 1.25 (stored in the ADC_TEMP1 register in 2.14 fixed-point format)
• R2p5 = 2.5 (stored in the ADC_TEMP2 register in 2.14 fixed-point format)
• Voff = -0.001114265
For example, if Vref = 1.25 V
adcoutcode = 1632
T(⁰C) = 84.8⁰C
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–13
ADC Functional Description
Digital Reference Mode
The following steps describe how to measure temperature using Digital Reference Mode:
1. Set the ADC_CNV_CFG.TMP bit to 1.
2. Set the ADC_CNV_CFG.SINGLE bit.
3. The ADC_STAT.TMPDONE bit is set after conversion.
Interrupt is given if the ADC_IRQ_EN.CNVDONE bit is set.
4. Read the output, code1, from the ADC_TMP_OUT register.
5. Set the ADC_CNV_CFG.TMP2 bit.
6. Set the ADC_CNV_CFG.TMP bit to 1.
7. The ADC_STAT.TMP2DONE bit is set after conversion.
Interrupt is given if the ADC_IRQ_EN.CNVDONE bit is set.
8. Read the output, code2, from ADC_TMP2_OUT register after conversion.
Auto mode can also be used for Digital Reference mode.
Set the ADC_CNV_CFG.TMP and ADC_CNV_CFG.TMP2 bits. Start the conversion by setting the
ADC_CNV_CFG.SINGLE bit or ADC_CNV_CFG.MULTI bit (for multiple conversions).
Temperature can be calculated as:
T(⁰C) = [[code1/(code2 + RG * code1)] * [Rvirtualreference/idealsensitivity]] - 273.15
where,
• RG = 1.18
• Rvirtualreferencee=1.223331 (stored in the ADC_TEMP_R register in 2.14 fixed-point format)
• idealsensitivity = 0.001392736
For example, if:
• TMP = 1: Code1 = 1632
• TMP2 = 1: Code2 = 2080
T(⁰C) = 84.64 ⁰C
12–14
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADC Functional Description
Battery Monitoring
To enable battery monitoring, the ADC_CNV_CFG.BAT bit must be set. The ADC_CNV_TIME.SAMPTIME bit must
be set to obtain an acquisition time of 500 ns. Set the ADC_CNV_CFG.SINGLE bit to start conversion. The ADC
converted output can be read from the ADC_BAT_OUT register or SRAM, depending on the conversion mode.
Conversion done interrupt can be enabled for getting an interrupt after conversion is done. Clear the
ADC_CNV_CFG.BAT bit after conversion is done to reduce power consumption.
To convert ADC result to battery voltage:
VBAT = 4 * adc_out * Vref / (212 – 1)
where,
• VBAT = battery voltage
• Vref = reference voltage selected (preferred, 1.25 V)
• adc_out = ADC converted output
Over Sampling
Resolution greater than 12-bit can be achieved by oversampling. Oversampling can be enabled by writing the
ADC_AVG_CFG.OS and ADC_AVG_CFG.EN bits to 1. When oversampling is enabled, the ADC samples multiple
times and averages the result to provide the required output in the CHx_OUT register.
The value to be programmed in the ADC_AVG_CFG.FACTOR field for a required resolution is given in the Factor for
Enhanced Resolution table.
Table 12-3:
Factor for Enhanced Resolution
Resolution Required
AVG_CFG_FACTOR to be programmed
No.of Samples Used
13-bit
h02
4
14-bit
h08
16
15-bit
h20
64
16-bit
h80
256
Averaging Function
When performing multiple conversions, averaging can be enabled on all selected channels. Averaging can be performed over a maximum of 256 samples, in the steps of power of 2 (that is, 2, 4, 8, 16…256). Averaging can be
enabled by writing the ADC_AVG_CFG.OS bit to 0 and the ADC_AVG_CFG.EN bit to 1.
Averaging factor is to be programmed as factor/2 in the ADC_AVG_CFG.FACTOR bits.
For example, to average 64 samples, program ADC_AVG_CFG.FACTOR as 32 (0x20). An interrupt is generated after
averaging is complete.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–15
ADC Functional Description
In case of auto cycle mode, DMA can be enabled.
For example, to average over 16 samples, 16 values are converted, added, and then divided by 16.
If averaging is enabled in auto mode (for multiple channels), programmed number of conversions are done on one
channel (and averaged) before moving to the next channel.
Averaging for Multiple Conversions on Single Channel
The following steps describe how to perform averaging over multiple conversions on a single channel (say AIN2):
1. Set ADC_CNV_CFG.SEL = 0x2 and select Channel 2 for conversion.
2. Set ADC_IRQ_EN.CNVDONE = 0x1 to enable interrupt when conversion is done.
3. Set ADC_AVG_CFG.OS = 0.
4. Set ADC_AVG_CFG.EN = 0x1 to enable averaging.
5. Set ADC_AVG_CFG.FACTOR = 0x20 to average more than 64 samples.
6. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
7. Interrupt is generated and STAT[2] is set when conversion is done.
8. Set cnv_result = ADC_CH2_OUT.RESULT to read the conversion output.
9. Set ADC_STAT.DONE2 = 0x1 to clear the interrupt.
Averaging for Multiple Conversions in Auto Cycle Mode
The following steps describe how to perform averaging over multiple conversion on a series of channels in auto cycle
mode:
1. Set ADC_CNV_CFG.SEL = 0x30 and select Channel 5 and Channel 4 for conversion.
2. Set the following DMA configurations:
a. DMA count = 2, for three conversions (DMA count = number of conversions – 1)
b. Source Address = Address of ADC_DMA_OUT register
c. Source Size = Halfword
d. Destination address of DMA as SRAM memory location address to store the conversion result
e. Program the required increment in the destination address.
3. Set ADC_CNV_CFG.DMAEN = 0x1 and enable DMA (if used).
4. Set ADC_CNV_CFG.AUTOMODE = 0x1 to start the conversion.
5. Set ADC_AVG_CFG.OS = 0
6. Set ADC_AVG_CFG.EN = 0x1
7. Set ADC_AVG_CFG.FACTOR = 0x08 to average more than 16 samples.
12–16
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADC Functional Description
8. Set ADC_CNV_CFG.SINGLE = 0x1 to start the conversion.
dma_done is generated after conversion.
The conversion result can be read from the SRAM or respective Channel Out register.
NOTE: Averaging/Over sampling and monitoring cannot be enabled together. They are mutually exclusive.
ADC Digital Comparator
A digital comparator is provided to allow an interrupt to be triggered if the ADC input is above or below a programmable threshold. Input channels AIN0, AIN1, AIN2, and AIN3 can be used with the digital comparator. This can
be used to continuously monitor if any (or a set) of these channels stay within normal range of values. Comparators
can be enabled only in multiple conversion mode, either on single channel or in auto cycle mode. Overflow indication is disabled, as the user is not expected to read the results during monitoring.
To set up the ADC digital comparator:
• Lower threshold value must be written to 12-bit ADC_LIMx_LO.VALUE field. To enable comparison with lower limit, the EN bit of the corresponding register must be set.
• Higher threshold value must be written to 12-bit ADC_LIMx_HI.VALUE field. To enable comparison, the EN
bit of the corresponding register must be set.
• Hysteresis value can also be given for each of these channels in the ADC_HYSx.VALUE bit . It must be enabled
by setting the ADC_HYSx.EN bit.
• An alert is indicated if the ADC result crosses the threshold (ADC_LIMx_LO.VALUE or
ADC_LIMx_HI.VALUE) and does not return to its normal value within number of clock cycles programmed in
the ADC_HYSx.MONCYC bit.
The Normal value is defined as:
• For lower threshold: Above ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE
• For higher threshold: Below ADC_LIMx_HI.VALUE – ADC_HYSx.VALUE
If the converted result is above ADC_LIMx_HI.VALUE, it is monitored for the next MONCYC conversions.
If the converted results during monitoring remain above ADC_LIMx_HI.VALUE - ADC_HYSx.VALUE, an alert
is indicated.
If the converted result during monitoring is below ADC_LIMx_HI.VALUE – ADC_HYSx.VALUE, alert is not
indicated and monitoring stops.
If the converted result is below ADC_LIMx_LO.VALUE, it is monitored for the next MONCYC conversions.
If the converted results during monitoring remain below ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE, an
alert is indicated.
If the converted result during monitoring is above ADC_LIMx_LO.VALUE + ADC_HYSx.VALUE, alert is not
indicated and monitoring stops.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–17
ADC Functional Description
The ADC_ALERT register can be read to determine the source of alert. An interrupt is generated if the
ADC_IRQ_EN.ALERT bit is set.
Figure 12-9: Low-High Limits and Hysteresis
Figure 12-10: Alert Functionality
Figure 12-11: Alert Not Indicated when Conversion Result is within MONCYC Cycles
In auto cycle mode, channels are converted sequentially. If any channel crosses the threshold, it is monitored before
moving to the next channel in sequence. Monitoring stops if the channel input returns to a normal value within
MONCYC cycles or an alert is raised after MONCYC cycles.
NOTE: Hysteresis is not supported with DMA enabled.
The flowchart explains the flow of conversion when comparison is enabled on three channels in auto cycle mode.
12–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Figure 12-12: Conversion Flow for Comparison Enabled on Three Channels in Auto Cycle Mode
ADuCM302x ADC Register Descriptions
(ADC) contains the following registers.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–19
ADuCM302x ADC Register Descriptions
Table 12-4:
ADuCM302x ADC Register List
Name
Description
ADC_ALERT
Alert Indication
ADC_AVG_CFG
Averaging Configuration
ADC_BAT_OUT
Battery Monitoring Result
ADC_CAL_WORD
Calibration Word
ADC_CFG
ADC Configuration
ADC_CFG1
Reference Buffer Low Power Mode
ADC_CH0_OUT
Conversion Result Channel 0
ADC_CH1_OUT
Conversion Result Channel 1
ADC_CH2_OUT
Conversion Result Channel 2
ADC_CH3_OUT
Conversion Result Channel 3
ADC_CH4_OUT
Conversion Result Channel 4
ADC_CH5_OUT
Conversion Result Channel 5
ADC_CH6_OUT
Conversion Result Channel 6
ADC_CH7_OUT
Conversion Result Channel 7
ADC_CNV_CFG
ADC Conversion Configuration
ADC_CNV_TIME
ADC Conversion Time
ADC_DMA_OUT
DMA Output Register
ADC_HYS0
Channel 0 Hysteresis
ADC_HYS1
Channel 1 Hysteresis
ADC_HYS2
Channel 2 Hysteresis
ADC_HYS3
Channel 3 Hysteresis
ADC_IRQ_EN
Interrupt Enable
ADC_LIM0_HI
Channel 0 High Limit
ADC_LIM0_LO
Channel 0 Low Limit
ADC_LIM1_HI
Channel 1 High Limit
ADC_LIM1_LO
Channel 1 Low Limit
ADC_LIM2_HI
Channel 2 High Limit
ADC_LIM2_LO
Channel 2 Low Limit
ADC_LIM3_HI
Channel 3 High Limit
ADC_LIM3_LO
Channel 3 Low Limit
ADC_OVF
Overflow of Output Registers
12–20
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Table 12-4:
ADuCM302x ADC Register List (Continued)
Name
Description
ADC_PWRUP
ADC Power-up Time
ADC_STAT
ADC Status
ADC_TEMP1
Value of R1p25
ADC_TEMP2
Value of R2p5
ADC_TEMP_R
Value of R_virtual
ADC_TMP2_OUT
Temperature Result 2
ADC_TMP_OUT
Temperature Result
ADC_TMP_SAMP
Sampling Time for Temperature Sensor
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–21
ADuCM302x ADC Register Descriptions
Alert Indication
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
LO3 (R/W1C)
Channel 3 Low alert status
HI0 (R/W1C)
Channel 0 High alert status
HI3 (R/W1C)
Channel 3 High alert status
LO0 (R/W1C)
Channel 0 Low alert status
LO2 (R/W1C)
Channel 2 Low alert status
HI1 (R/W1C)
Channel 1 High alert status
HI2 (R/W1C)
Channel 2 High alert status
LO1 (R/W1C)
Channel 1 Low alert status
Figure 12-13: ADC_ALERT Register Diagram
Table 12-5:
ADC_ALERT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7 LO3
Channel 3 Low alert status.
(R/W1C)
6 HI3
Channel 3 High alert status.
(R/W1C)
5 LO2
Channel 2 Low alert status.
(R/W1C)
4 HI2
Channel 2 High alert status.
(R/W1C)
3 LO1
Channel 1 Low alert status.
(R/W1C)
2 HI1
Channel 1 High alert status.
(R/W1C)
1 LO0
Channel 0 Low alert status.
(R/W1C)
0 HI0
Channel 0 High alert status.
(R/W1C)
12–22
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Averaging Configuration
15 14 13 12 11 10 9
0
1
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
0
0
EN (R/W)
To enable averaging on Channels enabled
in enable register
FACTOR (R/W)
Program averaging factor for averaging
enabled channels (1-256)
OS (R/W)
Enable oversampling
Figure 12-14: ADC_AVG_CFG Register Diagram
Table 12-6:
ADC_AVG_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable averaging on Channels enabled in enable register.
(R/W)
14 OS
Enable oversampling.
(R/W)
7:0 FACTOR
Program averaging factor for averaging enabled channels (1-256).
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–23
ADuCM302x ADC Register Descriptions
Battery Monitoring Result
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of battery monitoring
is stored here
Figure 12-15: ADC_BAT_OUT Register Diagram
Table 12-7:
ADC_BAT_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of battery monitoring is stored here.
(R/NW)
12–24
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Calibration Word
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
VALUE (R/W)
Offset calibration word
Figure 12-16: ADC_CAL_WORD Register Diagram
Table 12-8:
ADC_CAL_WORD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
6:0 VALUE
Offset calibration word.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–25
ADuCM302x ADC Register Descriptions
ADC Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
FAST_DISCH (R/W)
For fast switchover of vref from 2.5
V to 1.25 V
PWRUP (R/W)
Powering up the ADC
VREFSEL (R/W)
To select Vref as 1.25 V or 2.5 V
TMPEN (R/W)
To power up temperature sensor
REFBUFEN (R/W)
To enable internal reference buffer
SINKEN (R/W)
To enable additional 50 uA sink current
capability @1.25 V, 100 uA current capability
@2.5 V
VREFVBAT (R/W)
To select Vbat (battery voltage) as Vref
EN (R/W)
To enable ADC subsystem
RST (R/W)
Resets internal buffers and registers
when high
STARTCAL (R/W)
To start a new offset calibration cycle
Figure 12-17: ADC_CFG Register Diagram
Table 12-9:
ADC_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9 FAST_DISCH
For fast switchover of vref from 2.5 V to 1.25 V.
(R/W)
8 TMPEN
To power up temperature sensor.
(R/W)
7 SINKEN
(R/W)
6 RST
To enable additional 50 uA sink current capability @1.25 V, 100 uA current capability
@2.5 V.
Resets internal buffers and registers when high.
(R/W)
5 STARTCAL
To start a new offset calibration cycle.
(R/W)
4 EN
To enable ADC subsystem.
(R/W)
3 VREFVBAT
To select Vbat (battery voltage) as Vref.
(R/W)
12–26
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Table 12-9:
ADC_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 REFBUFEN
To enable internal reference buffer.
(R/W)
0 External reference is used
1 Reference buffer is enabled
1 VREFSEL
To select Vref as 1.25 V or 2.5 V.
(R/W)
0 Vref = 2.5V
1 Vref = 1.25V
0 PWRUP
Powering up the ADC.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–27
ADuCM302x ADC Register Descriptions
Reference Buffer Low Power Mode
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RBUFLP (R/W)
Enable low-power mode for reference
buffer
Figure 12-18: ADC_CFG1 Register Diagram
Table 12-10:
ADC_CFG1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 RBUFLP
Enable low-power mode for reference buffer.
(R/W)
12–28
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Conversion Result Channel 0
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Channel 0 is stored
here
Figure 12-19: ADC_CH0_OUT Register Diagram
Table 12-11:
ADC_CH0_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Channel 0 is stored here.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–29
ADuCM302x ADC Register Descriptions
Conversion Result Channel 1
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Channel 1 is stored
here
Figure 12-20: ADC_CH1_OUT Register Diagram
Table 12-12:
ADC_CH1_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Channel 1 is stored here.
(R/NW)
12–30
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Conversion Result Channel 2
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Channel 2 is stored
here
Figure 12-21: ADC_CH2_OUT Register Diagram
Table 12-13:
ADC_CH2_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Channel 2 is stored here.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–31
ADuCM302x ADC Register Descriptions
Conversion Result Channel 3
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Channel 3 is stored
here
Figure 12-22: ADC_CH3_OUT Register Diagram
Table 12-14:
ADC_CH3_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Channel 3 is stored here.
(R/NW)
12–32
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Conversion Result Channel 4
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Channel 4 is stored
here
Figure 12-23: ADC_CH4_OUT Register Diagram
Table 12-15:
ADC_CH4_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Channel 4 is stored here.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–33
ADuCM302x ADC Register Descriptions
Conversion Result Channel 5
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Channel 5 is stored
here
Figure 12-24: ADC_CH5_OUT Register Diagram
Table 12-16:
ADC_CH5_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Channel 5 is stored here.
(R/NW)
12–34
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Conversion Result Channel 6
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Channel 6 is stored
here
Figure 12-25: ADC_CH6_OUT Register Diagram
Table 12-17:
ADC_CH6_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Channel 6 is stored here.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–35
ADuCM302x ADC Register Descriptions
Conversion Result Channel 7
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Channel 7 is stored
here
Figure 12-26: ADC_CH7_OUT Register Diagram
Table 12-18:
ADC_CH7_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Channel 7 is stored here.
(R/NW)
12–36
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
ADC Conversion Configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MULTI (R/W)
Set to start multiple conversions
SEL (R/W)
To select channel(s) to convert
SINGLE (R/W)
Set to start single conversion
BAT (R/W)
To enable battery monitoring
DMAEN (R/W)
To enable DMA channel
TMP (R/W)
To select temperature measurement 1
AUTOMODE (R/W)
To enable auto mode
TMP2 (R/W)
To select temperature measurement 2
TMPSAMP (R/W)
To enable temperature sensor sampling
Figure 12-27: ADC_CNV_CFG Register Diagram
Table 12-19:
ADC_CNV_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 MULTI
Set to start multiple conversions.
(R/W)
14 SINGLE
Set to start single conversion.
(R/W)
13 DMAEN
To enable DMA channel.
(R/W)
12 AUTOMODE
To enable auto mode.
(R/W)
11 TMPSAMP
To enable temperature sensor sampling.
(R/W)
10 TMP2
To select temperature measurement 2.
(R/W)
9 TMP
To select temperature measurement 1.
(R/W)
8 BAT
To enable battery monitoring.
(R/W)
7:0 SEL
To select channel(s) to convert.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–37
ADuCM302x ADC Register Descriptions
ADC Conversion Time
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DLY (R/W)
Delay between two consecutive conversions
in terms of number of ACLK cycles
SAMPTIME (R/W)
Number of clock cycles (ACLK) required
for sampling
Figure 12-28: ADC_CNV_TIME Register Diagram
Table 12-20:
ADC_CNV_TIME Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 DLY
Delay between two consecutive conversions in terms of number of ACLK cycles.
(R/W)
7:0 SAMPTIME
Number of clock cycles (ACLK) required for sampling.
(R/W)
12–38
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
DMA Output Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Register to store conversion result
for DMA
Figure 12-29: ADC_DMA_OUT Register Diagram
Table 12-21:
ADC_DMA_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Register to store conversion result for DMA.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–39
ADuCM302x ADC Register Descriptions
Channel 0 Hysteresis
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable hysteresis for comparison
on Channel 0
VALUE (R/W)
Hysteresis value for Channel 0
MONCYC (R/W)
Program number of conversion cycles
to monitor channel 0 before raising
alert
Figure 12-30: ADC_HYS0 Register Diagram
Table 12-22:
ADC_HYS0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable hysteresis for comparison on Channel 0.
(R/W)
14:12 MONCYC
Program number of conversion cycles to monitor channel 0 before raising alert.
(R/W)
8:0 VALUE
Hysteresis value for Channel 0.
(R/W)
12–40
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Channel 1 Hysteresis
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable hysteresis for comparison
on Channel 1
VALUE (R/W)
Hysteresis value for Channel 1
MONCYC (R/W)
Program number of conversion cycles
to monitor Channel 1 before raising
alert
Figure 12-31: ADC_HYS1 Register Diagram
Table 12-23:
ADC_HYS1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable hysteresis for comparison on Channel 1.
(R/W)
14:12 MONCYC
Program number of conversion cycles to monitor Channel 1 before raising alert.
(R/W)
8:0 VALUE
Hysteresis value for Channel 1.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–41
ADuCM302x ADC Register Descriptions
Channel 2 Hysteresis
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable hysteresis for comparison
on Channel 2
VALUE (R/W)
Hysteresis value for Channel 2
MONCYC (R/W)
Program number of conversion cycles
to monitor Channel 2 before raising
alert
Figure 12-32: ADC_HYS2 Register Diagram
Table 12-24:
ADC_HYS2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable hysteresis for comparison on Channel 2.
(R/W)
14:12 MONCYC
Program number of conversion cycles to monitor Channel 2 before raising alert.
(R/W)
8:0 VALUE
Hysteresis value for Channel 2.
(R/W)
12–42
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Channel 3 Hysteresis
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable hysteresis for comparison
on Channel 3
VALUE (R/W)
Hysteresis value for Channel 3
MONCYC (R/W)
Program number of conversion cycles
to monitor Channel 3 before raising
alert
Figure 12-33: ADC_HYS3 Register Diagram
Table 12-25:
ADC_HYS3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable hysteresis for comparison on Channel 3.
(R/W)
14:12 MONCYC
Program number of conversion cycles to monitor Channel 3 before raising alert.
(R/W)
8:0 VALUE
Hysteresis value for Channel 3.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–43
ADuCM302x ADC Register Descriptions
Interrupt Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RDY (R/W)
Set to enable interrupt when ADC is
ready to convert
CNVDONE (R/W)
Set it to enable interrupt after conversion
is done
ALERT (R/W)
Set to enable interrupt on crossing
lower or higher limit
CALDONE (R/W)
Set it to enable interrupt for calibration
done
OVF (R/W)
Set to enable interrupt in case of overflow
Figure 12-34: ADC_IRQ_EN Register Diagram
Table 12-26:
ADC_IRQ_EN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
13 RDY
Set to enable interrupt when ADC is ready to convert.
(R/W)
12 ALERT
Set to enable interrupt on crossing lower or higher limit.
(R/W)
11 OVF
Set to enable interrupt in case of overflow.
(R/W)
10 CALDONE
Set it to enable interrupt for calibration done.
(R/W)
0 CNVDONE
Set it to enable interrupt after conversion is done.
(R/W)
12–44
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Channel 0 High Limit
15 14 13 12 11 10 9
0
0
0
0
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
EN (R/W)
To enable high limit comparison on
Channel 0
VALUE (R/W)
High limit value for Channel 0
Figure 12-35: ADC_LIM0_HI Register Diagram
Table 12-27:
ADC_LIM0_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable high limit comparison on Channel 0.
(R/W)
11:0 VALUE
High limit value for Channel 0.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–45
ADuCM302x ADC Register Descriptions
Channel 0 Low Limit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable low limit comparison on Channel 0
VALUE (R/W)
Low limit value for Channel 0
Figure 12-36: ADC_LIM0_LO Register Diagram
Table 12-28:
ADC_LIM0_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable low limit comparison on Channel 0.
(R/W)
11:0 VALUE
Low limit value for Channel 0.
(R/W)
12–46
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Channel 1 High Limit
15 14 13 12 11 10 9
0
0
0
0
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
EN (R/W)
To enable high limit comparison on
Channel 1
VALUE (R/W)
High limit value for Channel 1
Figure 12-37: ADC_LIM1_HI Register Diagram
Table 12-29:
ADC_LIM1_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable high limit comparison on Channel 1.
(R/W)
11:0 VALUE
High limit value for Channel 1.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–47
ADuCM302x ADC Register Descriptions
Channel 1 Low Limit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable low limit comparison on Channel 1
VALUE (R/W)
Low limit value for Channel 1
Figure 12-38: ADC_LIM1_LO Register Diagram
Table 12-30:
ADC_LIM1_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable low limit comparison on Channel 1.
(R/W)
11:0 VALUE
Low limit value for Channel 1.
(R/W)
12–48
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Channel 2 High Limit
15 14 13 12 11 10 9
0
0
0
0
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
EN (R/W)
To enable high limit comparison on
Channel 2
VALUE (R/W)
High limit value for Channel 2
Figure 12-39: ADC_LIM2_HI Register Diagram
Table 12-31:
ADC_LIM2_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable high limit comparison on Channel 2.
(R/W)
11:0 VALUE
High limit value for Channel 2.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–49
ADuCM302x ADC Register Descriptions
Channel 2 Low Limit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable low limit comparison on Channel 2
VALUE (R/W)
Low limit value for Channel 2
Figure 12-40: ADC_LIM2_LO Register Diagram
Table 12-32:
ADC_LIM2_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable low limit comparison on Channel 2.
(R/W)
11:0 VALUE
Low limit value for Channel 2.
(R/W)
12–50
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Channel 3 High Limit
15 14 13 12 11 10 9
0
0
0
0
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
EN (R/W)
To enable high limit comparison on
Channel 3
VALUE (R/W)
High limit value for Channel 3
Figure 12-41: ADC_LIM3_HI Register Diagram
Table 12-33:
ADC_LIM3_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable high limit comparison on Channel 3.
(R/W)
11:0 VALUE
High limit value for Channel 3.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–51
ADuCM302x ADC Register Descriptions
Channel 3 Low Limit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EN (R/W)
To enable low limit comparison on Channel 3
VALUE (R/W)
Low limit value for Channel 3
Figure 12-42: ADC_LIM3_LO Register Diagram
Table 12-34:
ADC_LIM3_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 EN
To enable low limit comparison on Channel 3.
(R/W)
11:0 VALUE
Low limit value for Channel 3.
(R/W)
12–52
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Overflow of Output Registers
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
TMP2 (R/W1C)
Indicates overflow in Temperature 2
output register
CH0 (R/W1C)
Indicates overflow in Channel 0 output
register
TMP (R/W1C)
Indicates overflow in Temperature output
register
CH1 (R/W1C)
Indicates overflow in Channel 1 output
register
BAT (R/W1C)
Indicates overflow in Battery monitoring
output register
CH2 (R/W1C)
Indicates overflow in Channel 2 output
register
CH7 (R/W1C)
Indicates overflow in Channel 7 output
register
CH3 (R/W1C)
Indicates overflow in Channel 3 output
register
CH6 (R/W1C)
Indicates overflow in Channel 6 output
register
CH4 (R/W1C)
Indicates overflow in Channel 4 output
register
CH5 (R/W1C)
Indicates overflow in Channel 5 output
register
Figure 12-43: ADC_OVF Register Diagram
Table 12-35:
ADC_OVF Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
10 TMP2
Indicates overflow in Temperature 2 output register.
(R/W1C)
9 TMP
Indicates overflow in Temperature output register.
(R/W1C)
8 BAT
Indicates overflow in Battery monitoring output register.
(R/W1C)
7 CH7
Indicates overflow in Channel 7 output register.
(R/W1C)
6 CH6
Indicates overflow in Channel 6 output register.
(R/W1C)
5 CH5
Indicates overflow in Channel 5 output register.
(R/W1C)
4 CH4
Indicates overflow in Channel 4 output register.
(R/W1C)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–53
ADuCM302x ADC Register Descriptions
Table 12-35:
ADC_OVF Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 CH3
Indicates overflow in Channel 3 output register.
(R/W1C)
2 CH2
Indicates overflow in Channel 2 output register.
(R/W1C)
1 CH1
Indicates overflow in Channel 1 output register.
(R/W1C)
0 CH0
Indicates overflow in Channel 0 output register.
(R/W1C)
12–54
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
ADC Power-up Time
15 14 13 12 11 10 9
0
0
0
0
0
0
1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
1
1
0
WAIT (R/W)
Program this with 526/PCLKDIVCNT
Figure 12-44: ADC_PWRUP Register Diagram
Table 12-36:
ADC_PWRUP Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9:0 WAIT
Program this with 526/PCLKDIVCNT.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–55
ADuCM302x ADC Register Descriptions
ADC Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RDY (R/W1C)
Indicates ADC is ready to start converting,
when using external reference buffer
DONE0 (R/W1C)
Indicates conversion done on Channel 0
DONE1 (R/W1C)
Indicates conversion done on Channel 1
CALDONE (R/W1C)
Indicates calibration is done
DONE2 (R/W1C)
Indicates conversion done on Channel 2
TMP2DONE (R/W1C)
Indicates conversion is done for temperature
sensing 2
DONE3 (R/W1C)
Indicates conversion done on Channel 3
TMPDONE (R/W1C)
Indicates conversion is done for temperature
sensing
DONE4 (R/W1C)
Indicates conversion done on Channel 4
DONE5 (R/W1C)
Indicates conversion done on Channel 5
BATDONE (R/W1C)
Indicates conversion done for battery
monitoring
DONE7 (R/W1C)
Indicates conversion done on Channel 7
DONE6 (R/W1C)
Indicates conversion done on Channel 6
Figure 12-45: ADC_STAT Register Diagram
Table 12-37:
ADC_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 RDY
Indicates ADC is ready to start converting, when using external reference buffer.
(R/W1C)
14 CALDONE
Indicates calibration is done.
(R/W1C)
10 TMP2DONE
Indicates conversion is done for temperature sensing 2.
(R/W1C)
9 TMPDONE
Indicates conversion is done for temperature sensing.
(R/W1C)
8 BATDONE
Indicates conversion done for battery monitoring.
(R/W1C)
7 DONE7
Indicates conversion done on Channel 7.
(R/W1C)
6 DONE6
12–56
Indicates conversion done on Channel 6.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Table 12-37:
ADC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
(R/W1C)
5 DONE5
Indicates conversion done on Channel 5.
(R/W1C)
4 DONE4
Indicates conversion done on Channel 4.
(R/W1C)
3 DONE3
Indicates conversion done on Channel 3.
(R/W1C)
2 DONE2
Indicates conversion done on Channel 2.
(R/W1C)
1 DONE1
Indicates conversion done on Channel 1.
(R/W1C)
0 DONE0
Indicates conversion done on Channel 0.
(R/W1C)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–57
ADuCM302x ADC Register Descriptions
Value of R1p25
15 14 13 12 11 10 9
0
1
0
1
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
R1p25 (R/W)
Value of R for calculation of temperature
when Vref is 1.25 V
Figure 12-46: ADC_TEMP1 Register Diagram
Table 12-38:
ADC_TEMP1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 R1P25
Value of R for calculation of temperature when Vref is 1.25 V.
(R/W)
12–58
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Value of R2p5
15 14 13 12 11 10 9
1
0
1
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
R2p5 (R/W)
Value of R for calculation of temperature
when Vref is 2.5 V
Figure 12-47: ADC_TEMP2 Register Diagram
Table 12-39:
ADC_TEMP2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 R2P5
Value of R for calculation of temperature when Vref is 2.5 V.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
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ADuCM302x ADC Register Descriptions
Value of R_virtual
15 14 13 12 11 10 9
0
0
0
1
1
1
1
8
7
6
5
4
3
2
1
0
0
0
1
0
0
1
0
1
1
VIRTUAL (R/W)
Value of R virtual reference for calculating
temperature
Figure 12-48: ADC_TEMP_R Register Diagram
Table 12-40:
ADC_TEMP_R Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VIRTUAL
Value of R virtual reference for calculating temperature.
(R/W)
12–60
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Temperature Result 2
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Temperature measurement
2 is stored here
Figure 12-49: ADC_TMP2_OUT Register Diagram
Table 12-41:
ADC_TMP2_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Temperature measurement 2 is stored here.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–61
ADuCM302x ADC Register Descriptions
Temperature Result
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RESULT (R)
Conversion result of Temperature measurement
1 is stored here
Figure 12-50: ADC_TMP_OUT Register Diagram
Table 12-42:
ADC_TMP_OUT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RESULT
Conversion result of Temperature measurement 1 is stored here.
(R/NW)
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ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x ADC Register Descriptions
Sampling Time for Temperature Sensor
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
TIME (R/W)
Value of counter for sampling time 2
Figure 12-51: ADC_TMP_SAMP Register Diagram
Table 12-43:
ADC_TMP_SAMP Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 TIME
Value of counter for sampling time 2.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
12–63
Flash Controller (FLASH)
13 Flash Controller (FLASH)
The ADuCM302x processor includes 256 KB of embedded flash memory available for access through the flash controller. The embedded flash has a 72-bit wide data bus providing two 32-bit words of data and one corresponding 8bit ECC byte per access.
The Flash Controller is coupled with a Cache Controller module which provides two AHB ports; one port for reading Data (DCode), the other for reading Instructions (ICode). A pre-fetch mechanism is implemented in the Flash
Controller to optimize ICode read performance.
Flash writes are supported by a key-hole mechanism through APB writes to memory mapped registers. The Flash
Controller includes support for DMA based key-hole writes.
Flash Features
The flash memory used by the ADuCM302x processor includes:
ADuCM302x FLCC Register List
Table 13-1:
ADuCM302x FLCC Register List
Name
Description
FLCC_ABORT_EN_HI
IRQ Abort Enable (upper bits)
FLCC_ABORT_EN_LO
IRQ Abort Enable (lower bits)
FLCC_CMD
Command
FLCC_ECC_ADDR
ECC Status (Address)
FLCC_ECC_CFG
ECC Config
FLCC_IEN
Interrupt Enable
FLCC_KEY
Key
FLCC_KH_ADDR
WRITE Address
FLCC_KH_DATA0
WRITE Lower Data
FLCC_KH_DATA1
WRITE Upper Data
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–1
Flash Features
Table 13-1:
ADuCM302x FLCC Register List (Continued)
Name
Description
FLCC_PAGE_ADDR0
Lower Page Address
FLCC_PAGE_ADDR1
Upper Page Address
FLCC_SIGNATURE
Signature
FLCC_STAT
Status
FLCC_TIME_PARAM0
Time Parameter 0
FLCC_TIME_PARAM1
Time parameter 1
FLCC_UCFG
User Configuration
FLCC_WRPROT
Write Protection
FLCC_WR_ABORT_ADDR
Write Abort Address
Supported Features
• Pre-fetch buffer provides optimal performance when reading consecutive addresses on the ICode interface.
• Simultaneous ICode and DCode read accesses (DCode has priority on contention; simultaneous reads are possible if ICode returns buffered data from pre-fetch).
• DMA based key-hole writes (including address auto-increment for sequential accesses).
• ECC for error detection and/or correction; errors and corrections may be reported as Bus Errors (on the ICode/
DCode buses), as interrupts, or ignored.
Supported Commands
• Read: Supported through the ICode and DCode interfaces.
• Write: Provided by a key-hole mechanism through memory mapped registers.
• Mass erase: Clears all user data and program code.
• Page erase: Clears user data and/or program code from a 2KB page in flash.
• Signature: Generate and verify signatures for any set of contiguous whole pages of user data and/or program
code.
• Abort: Terminate a command in progress.
Protection and Integrity Features
• Fixed user key required for running protected commands including mass erase and page erase.
• Optional and user definable Write protection for user accessible memory.
• Optional 8-bit Error Correction Code (ECC): May be enabled by user code (off by default).
13–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Flash Functional Description
Flash Functional Description
This section provides information on the flash memory functions used by the ADuCM302x processor.
Organization
The Flash IP provides a 64 bit data bus, plus 8 bits for ECC meta-data corresponding to that data. The memory is
organized as a number of pages, each 2 KB in size plus 256 bytes reserved for ECC.
One Page
ECC
256B
Data
2KB
8 bits
64 bits
256
Figure 13-1: One Page of Flash Memory
These pages of memory are categorically divided into two sections: Info Space and User Space. Total device storage
is generally described as the size of User Space alone.
Info Space
2KB
1 page
User Space
256KB
128 Pages
Figure 13-2: Flash Info and User Spaces
Info Space is reserved for use by Analog Devices and generally stores a boot loader (aka kernel), several trim and
calibration values, and other device specific meta data. Most of info space is left readable by user code but attempted
erasures and writes will be denied.
User Space is the portion of flash memory intended for user data and program code. Several small address ranges in
user space are used by the flash controller as meta-data to enable various protection and integrity features.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–3
Flash Functional Description
Info Space User Accessible Data
While Info space is generally reserved for use only by Analog Devices, all but the top 128 bytes of info space are
readable by user code. Notably, a 64 bit Manufacture ID is located at the most significant user readable info space
address: 0x77C. Other potential read-only data may be made available to the user within the scope of the info space.
Such meta data is software defined, therefore the addresses and data types are not defined by the flash controller.
Info Space
0x7F
Reserved
0x7FC
...
...
...
...
Reserved
0x780
Manf ID 1
0x77C
Manf ID 0
0x778
Reserved
Range
32 bits Default
Manufacturer ID
location
128 bytes of protected data in into space
followed by 64 bits of Manufacturer ID
0x000
All other info space addresses are read-only.
Figure 13-3: User Readable locations in Info Space
The top 128 bytes of info space are protected and cannot be read by user code (attempted reads will return bus
errors). The remainder of the info space is freely readable by user code. None of info space may be programmed or
erased by the user (command will be denied).
Bus errors will be generated if user code attempts to read the protected range of info space; Write and Erases targeting info space will be denied and appropriate bits set in the status register.
User code may perform a Mass Erase command on the part without affecting the content of the Info Space; this
provides a mechanism to upload new user firmware and data to a device without affecting ADIs secure boot loader.
User Space Meta Data
User Space is the portion of flash memory intended for user data and program code. Several small address ranges in
user space are used by the flash controller as meta-data to enable various protection and integrity features.
The top four words of user space are reserved for a Signature, the user Write Protection word, and two reserved
words.
13–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Flash Functional Description
64 bits
Signature
Reserved
Reserved
WrProt
Uppermost page
in User Space)
(Rest of uppermost page in User Space)
Figure 13-4: User Space Meta Data
When writing to these locations, user code should take care to always write 0xFFFF_FFFF to the reserved locations.
If the user intends to write to either location at runtime, these reserved locations should remain all ONES
(0xFFFFFFFF). If data is stored to these reserved locations prior to runtime modification of the neighboring metadata spurious, ECC errors will likely be generated when this meta-data is read.
The meta-data described above is utilized by the Flash controller to enable Protection and Integrity features. These
features are implemented as described later in this manual (see Protection and Integrity). It is the responsibility of
the user to program these values. A brief description of these fields follows:
• Signature (optional): A 32-bit CRC checksum stored in the Signature field enables user code to request an integrity check of User Space.
• WrProt: A user programmable bitfield used to make blocks Flash pages read-only (protected from both writes
and erases); ADI secure bootloader reads and enforces the programmed WrProt meta-data.
Flash Access
Flash memory may be read, written, and erased by user code. Read access is provided through the Cache Controller
using two AHB ports: ICode for instructions and DCode for data. Write access is provided through key-hole writes
using APB control of memory mapped registers. The key-hole write implementation includes support for both
DMA based and manual user initiated writes.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–5
Flash Access
Read Path
AHB icode
AHB dcode
Cache
Controller
Custom Interface
Flash
Controller
APB
Write Path
Figure 13-5: Read and Write Data Paths
Bus errors are generated if user code reads from a protected or out of bounds address. Writes or Erasures of protected
addresses result in appropriate error flags set in the status register (note that address setup for writes and erasures is
automatically constrained to the flash address range).
Reading Flash
The Flash Controller provides two interfaces for reading non-volatile storage: ICode and DCode. The I-Code and
D-Code interfaces are accessed through the Cache Controller module through AHB. The Flash Controller includes
a pre-fetch buffer for ICode; due to this pre-fetch buffer it is possible to return data on both ICode and DCode
interfaces in the same cycle.
Flash memory is available to be read only after an automatic initialization process. Attempts to read during the Flash
Controllers initialization will stall. Reads will also stall if the flash controller is already busy performing another
command (for example, writing the flash) unless those reads would be satisfied by the pre-fetch buffer.
Erasing Flash
The flash controller provides page-level granularity when erasing user space (ERASEPAGE command). Alternatively,
user code may erase the entirety of user space at once (MASSERASE command). The two commands have the same
execution time.
Write protected pages cannot be erased; the command would be denied. If any pages are write protected then a mass
erase command would also be denied. Users wishing to write protect user space and also planning to perform mass
erases (for example, for future firmware upgrades) should take this into consideration.
Writing Flash
Flash memory operates by settings bits to ONE when erased, and selectively clearing bits to ZERO when writing
(programming) data. No write operation is capable of setting any bit to ONE. For this reason, generalized Write
accesses must be prefixed by an Erase operation.
13–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Flash Access
Initial uploading of user content will generally occur immediately following a Mass Erase operation. Subsequent
modification of already-written locations in flash will generally follow selective Page Erase operations with user code
taking care to copy a full page to SRAM, erase the affected page, modify the in-memory content, then finally write
the page back to Flash.
User Space protections may prevent a Page Erase operation (see Protection and Integrity: Write Protection). All User
Space protections are cleared automatically after a successful Mass Erase or Blank Check (a blank check passes if and
only if all of user space is already erased). In these two cases there is no user space content to protect.
Key-hole Writes
A Key-hole Write is an indirect write operation wherein user code programs memory mapped registers with target
Address and Data values, then commands the Flash Controller to perform a write operation in the background. The
Flash Controller supports Write access to the Flash Memory only through Key-Hole writes. This constraint on
Write access enables the Flash Controller to guarantee that writes occur properly as atomic DWORD (64-bit) operations with an associated ECC byte (if enabled; see: Protection and Integrity: ECC).
If ECC is enabled, multiple writes to a single DWORD (64-bit) location cannot be performed without erasing the
affected page between writes else ECC errors will be reported. Note that a maximum of two total writes are permitted to a single flash location (64-bit DWORD) between erasures (regardless of ECC or data values), as per the Flash
IP specifications. Writing any location more than twice per erasure may damage the non-volatile memory or reduce
its useful life. If multiple writes per location are required, user code should disable ECC for some region of flash and
target that region for these write operations.
Key-hole operations consist of writes to:
• FLCC_KH_ADDR.VALUE: The target address in Flash (for example, 0x104; note that the flash controller will
automatically trim lower bits to make the address DWORD aligned)
• FLCC_KH_DATA0.VALUE: Bits [31:0] of the 64 bit DWORD to be written (for example, 0x7654_3210)
• FLCC_KH_DATA1.VALUE: Bits[63:32] of the 64 bit DWORD to be written (for example, 0xFEDC_BA98)
• FLCC_CMD.VALUE: Assert the WRITE command in the Flash
After the WRITE command is asserted the flash controller will initiate a 64-bit dualword write to the address provided in FLCC_KH_ADDR.VALUE. Note that word (32-bit), halfword (16-bit), and byte (8-bit) writes are not supported. As only ZEROES are written to the flash, masking may be used to write individual bits or bytes as necessary
(provided the user keeps ECC and Flash IP specifications in mind - see above).
User code should refrain from writing any of these Key-hole registers when DMA access is enabled
(FLCC_UCFG.KHDMAEN is set). Writing these registers manually while DMA is enabled may result in spurious flash
writes and could put the DMA and Flash controllers out of sync, potentially hanging the DMA controller for long
periods of time (~20-40 us).
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–7
Flash Access
Burst Writes
Each 2 KB page of flash memory consists of eight rows, 256 bytes each. Design constraints for programming the
Flash IP enable back-to-back writes within a single row to complete more quickly than the equivalent writes across
row boundaries. For the purpose of optimizing writes, user code should attempt to write flash memory in (aligned)
blocks of up to 256 bytes.
Table 13-2:
Flash Addressing by Rows
Row 1023 0x3FFFC 0x3FFF8 0x3FF04 0x3FF00
Row 0 0xFC 0xF8 0x4 0x0
To benefit from this write-performance gain, the second (and subsequent) 64-bit write must be requested before the
flash controller completes the 1st write. The flag FLCC_STAT.WRALCOMP (write almost complete) is set when the
first 64-bit write operation is nearing completion (having ~20us remaining in the write cycle). This provides user
code with a manageable window of time in which to assert the next write request. This flag may be polled or an
interrupt may optionally be generated when it is asserted. Other status flags are also available:
• FLCC_STAT.CMDBUSY (command busy) High when the controller is processing a command from the CMD
register
• FLCC_STAT.WRCLOSE (key-hole closed) High during the first half of a write command, cleared when keyhole registers are free to be programmed for a subsequent write command
• FLCC_STAT.CMDCOMP (command complete) Sticky flag, set when a command is completed (write, erase and
so on). Write one to clear.
• FLCC_STAT.WRALCOMP (write almost completed) Sticky flag, set when ~20-40us remains for an on-going
write command. Write one to clear.
The following flow outlines the procedure for performing multiple writes with the potential to burst within a row:
• Wait for command busy flag to clear (to ensure on prior command is ongoing)
• Disable all interrupts so that sequenced writes to FLCC_KH_ADDR, FLCC_KH_DATA0, FLCC_KH_DATA1, and
FLCC_CMD registers will not be interrupted by an ISR which might also have flash writes
• Request first 64-bit write through the key-hole access
• Flash Controller will start the write process after the WRITE command is written to the FLCC_CMD register
• Check if the WRITE command was accepted (read FLCC_STAT register to see if any error flags are set; if the
command results in an error the write will not be performed)
• Set the FLCC_IEN.WRALCMPLT bit in the FFLCC_IEN register (to enable interrupt generation when WrAlComp is asserted) and re-enable other interrupts
• Continue the user program; the WrAlComp interrupt will vector to an interrupt service routine to request the
next write at the appropriate time
BurstWriteISR: Interrupt service routine (ISR) called when n interrupt is generated by WrAlComp
13–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Flash Access
• Disable all interrupts so that sequenced writes to FLCC_KH_ADDR, FLCC_KH_DATA0, FLCC_KH_DATA1, and
FLCC_CMD registers will not be interrupted by another ISR which might also have flash writes
At this point, read the FLCC_STAT register to verify the state of several status flags; clear the flags by writing
back the same value:
• FLCC_STAT.WRALCOMP: flag should be set indicating that there is still time for the next write to occur
for a Burst Write.
• FLCC_STAT.CMDBUSY: should be set indicating that the current write operation is still on-going.
• FLCC_STAT.CMDCOMP: should not be set; this bit would indicate that a command had already completed
and therefore the command currently in progress is not the earlier WRITE command (another function
has initiated a new command).
• FLCC_STAT.WRCLOSE: should not be set; if set, the Key-hole registers are closed and cannot be written.
This flag should clear when FLCC_STAT.WRALCOMP is asserted.
• If no further writes are required: wait for FLCC_STAT.CMDCOMP to be set, clear it, then exit the subroutine.
• Request the next 64-bit dualword write through the key-hole access (write FLCC_KH_ADDR,
FLCC_KH_DATA0, FLCC_KH_DATA1, and FLCC_CMD registers)
• Check if the WRITE command was accepted (read the FLCC_STAT register to see if any error flags are set)
• Re-enable interrupts
• Exit the ISR
User code with many write accesses to Flash should, if possible, be executed from SRAM to prevent thrashing the
flash. Write operations will cause ICode reads to stall, resulting in degraded performance when ICode access is required to fetch the next instruction (this may be partially alleviated by the Cache Controller).
Note that during a BurstWrite, the Flash controller overlaps the write operations and therefore any reported write
failures (for example, access denied due to write protection) may reflect the status of either of the two overlapped
writes. User code should interpret a BurstWrite failure as a failure for both writes being overlapped (that is, both the
current and the prior write requests).
DMA Writes
Key-hole writes generally require writing four memory mapped registers per flash write access. Refer Key-hole Writes
for additional information. An optional address auto-increment feature may reduce the APB traffic required per
flash write transaction to three register writes (FLCC_KH_DATA0, FLCC_KH_DATA1, and FLCC_CMD) for all but the
first in a series of sequential writes (first write requires setting up the start address). DMA Writes reduces the number
of APB transactions to two: every pair of FLCC_KH_DATA0 and FLCC_KH_DATA1 registers writes results in a single
flash write command executing and the address automatically incrementing to the next dword (regardless of the value of auto-increment, DMA writes will always increment in the address this manner).
To perform DMA based writes, User code must first configure the DMA Controller (a separate peripheral module)
for basic access (this DMA mode supports transferring data to/from peripherals, including the Flash Controller).
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–9
Flash Functional Description
Once the DMA Controller module has been it will sit IDLE until a DMA_REQ signal is asserted by the Flash Controller.
User code should manually write FLCC_KH_ADDR to setup the initial target address for DMA writes. The DMA
Controller should be configured to write all output data to FLCC_KH_DATA1. Each pair of DMA writes to
FLCC_KH_DATA1 will execute a single flash write command and wait for a corresponding delay before the next
DMA_REQ is made.
To start the flash controllers process of requesting data from the DMA controller, the Flash Controller must itself be
configured for DMA access. To enable DMA mode, user code must set the FLCC_UCFG.KHDMAEN bit.
Once DMA mode has been enabled (and the flash Controller is otherwise IDLE), the Flash Controller will begin
selectively driving the DMA_REQ signal to the DMA module. DMA_REQ will be driven at the appropriate time
to support BurstWrites (new requests are made once the current write operation is nearly complete).
For more information about DMA functionality, refer to Direct Memory Access (DMA).
Protection and Integrity
Integrity of Info Space
User Code does not have any control over the content of Info Space. If this integrity check fails on a Power-onReset, it will be attempted repeatedly until a preset number of attempts has occurred or the integrity check passes
(this provides some recoverability from power faults occurring during device power-up). For all other resets (except
software reset which does not re-initialize the Flash Controller), the integrity check is attempted just once.
In the event of an info space integrity check failure, it is expected that the part has failed and will either be disposed
of or returned to ADI for failure analysis. If the Info Space integrity check does not pass, the Flash Controller will
enter a special purpose debugging mode. In this mode, User Space protection is automatically asserted and the Flash
Controllers local JTAG protection is set to allow JTAG (or other Serial Wire type interface) to interact with the
ICode, DCode and APB interfaces.
In this special purpose debugging mode:
• All ICode reads return Bus Errors (no code shall be executed from the flash memory without passing the integrity check).
• All DCode reads to User Space returns Bus Errors
• All DCode reads to Info Space except the top 128 bytes are PERMITTED. Reads of the top 128 bytes return
Bus Errors.
• All WRITE commands are denied (write attempts set the appropriate error bits in the FLCC_STAT register).
• User Space protections may be bypassed only by satisfying the security requirements.
The status of the signature check after reset is read from the FLCC_STAT register. The status of ECC during signature check is available in FLCC_STAT.ECCINFOSIGN. These values are read through a normal JTAG read if the
JTAG interface is enabled.
13–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Protection and Integrity
User Space Protection
Two layers of user space protections are provided:
• Access Protection: Protects user space from all read or write operations. This protection mechanism may be
manually triggered but is typically automatically asserted in the event of system failure and/or the Serial Wire
Debug interface being enabled.
• Write Protection: User facing feature enabling blocks of user space pages to be protected against all write or
erase commands. May be set by user at runtime or by ADIs secure bootloader (user would store the desired
value in flash for the boot loader to consume during boot).
Access Protection
Access Protection is meant to prevent third parties from reading or tampering user data and program code through
JTAG or Serial Wire. Access Protection applies to the entirety of User Space. Access Protection is enabled by one of
the following three events:
• Serial Wire Debug is enabled
• Flash Initialization (info space sign check) fails
The first two enabling mechanisms are automatic features; user code does not have to configure or enable anything
for these mechanisms to enable/enforce Access Protection.
While Access Protection is enabled all User Space reads return Bus Errors, writes are denied, and erases are subject to
the FLCC_WRPROT.WORD of the FLCC_WRPROT register.
Access Protection may be bypassed by successfully executing a MASSERASE or BLANKCHECK command. Note
that the MASSERASE command is disallowed in the event that the FLCC_WRPROT (Write Protection) register has
been modified from its reset value. BLANKCHECK command is always permitted to execute but will only pass
successfully if all of User Space is already in an erased state.
Write Protection
User definable regions of User Space may be configured such that the flash controller will deny any attempts to
modify them (this affects both WRITE and ERASE commands). Write Protection may be configured at runtime or
may be stored in User Space meta-data to be loaded by the ADI secure bootloader during device boot.
NOTE: MASSERASE command is disallowed if any of the FLCC_WRPROT bits have been modified from the default
(permissive) value.
Runtime Configuration
Write Protection is configured by modifying the FLCC_WRPROT memory mapped register. FLCC_WRPROT.WORD is
a 32-bit wide bit field representing the Write Protection state for 32 similar size blocks of User Space pages. The
flash memory is divided into 128 pages of User Space storage. For Write Protection these are logically divided into
32 blocks of four pages each. Write Protection is independently controlled for each of these 32 blocks; each bit of
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–11
Protection and Integrity
FLCC_WRPROT.WORD controls the protection mechanism for a unique block of four pages of User Space. The least
significant bits of FLCC_WRPROT.WORD correspond to the least significant pages of User Space.
The WRPROT bitfield is active low: A ZERO represents active Write Protection, while a ONE represents no protection for the corresponding block of pages. The FLCC_WRPROT register is 'sticky' at ZERO: once protection is
enabled, it cannot be disabled without resetting the device.
User code may assert write protection for any block of pages by clearing the appropriate bit of FLCC_WRPROT.WORD
at any time. It is advisable to assert write protection as early as possible in user code; it is also advisable for the user
to write-protect block zero (that is, flash pages 0-3) and to place user boot and integrity checking code in this block.
In this manner, the user may opt to fully control the write protection scheme without relying on ADIs bootloader to
setup the FLCC_WRPROT register.
Meta Data Configuration
The most significant page of User Space contains a single 32-bit field representing a set of 1-bit Write Protect flags
for each of these 32 logical blocks (see User Space Meta Data), matching the functionality of the WRPROT memory mapped register.
These Write Protection bits are read from the flash by ADIs secure bootloader and stored in the FLCC_WRPROT
memory mapped register after a reset operation. The default (erased) state of flash memory is all ONES, therefore
the default FLCC_WRPROT register value is to disable protection for all pages in User Space. As described in Runtime
Configuration above, each bit of FLCC_WRPROT.WORD corresponds to the protection state for one block of four
User Space pages.
User code may clear bits in the WrProt meta-data word at runtime, or this word may be included in the initial upload of user data and program code. Keep in mind that writing the WrProt meta-data word at runtime does not
immediately affect the Write Protection state; if immediate protection is required, user code should also write the
same values to the FLCC_WRPROT memory mapped register. When writing the WrProt meta-data the user should
consider including Write Protection of the most significant page (thus protecting the meta-data from a page erase or
other modification). As with all flash locations, repeated writes (without intermediate erasures) are discouraged and
will likely cause ECC errors during read-back.
Once protection has been enabled (the corresponding bit has been cleared in FLCC_WRPROT.WORD) it cannot be
disabled without resetting the device. For this reason, once Write Protection has been enabled for any block of pages
through the User Space meta-data, it cannot be disabled without erasing the most significant page of User Space (the
page hosting the relevant meta-data) or otherwise affecting the flow of ADIs secure bootloader.
The following sequence outlines the process of programming the Write Protection meta-data word in flash:
• Ensure the most significant page of user space has been erased since the last time the meta-data was written (if
ever).
• Write the desired value for the WrProt meta-data word directly to flash (write '0' to a particular bit to enable
protection for the corresponding block). In 256 KB flash, this word is available at the address 0x3FFF0.
• Verify that the write completed successfully by polling the status register.
13–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Protection and Integrity
• Reset the device. The WrProt bits will automatically be uploaded by the ADI secure bootloader from user space
to the FLCC_WRPROT register and used to enforce the protection scheme.
Signatures
Signatures are used to check the integrity of the flash device contents. Signature calculations do not include the ECC
portion of the flash data bus nor the most significant word read from the set of pages being signed (this word is
considered meta-data and is meant to hold the expected signature value for the given set of pages).
The flash controller implements its own stand-alone CRC engine for generating and verifying signatures. Note however that this implementation matches the CRC Accelerator peripheral (with a seed of 0xFFFF_FFFF). For details
on the CRC algorithm used, refer to the CRC Accelerator chapter.
Signatures may be included in the initial upload of user data and program code (generated before being uploaded),
or may be generated and stored to flash at runtime. Generation at runtime may utilize either the CRC Accelerator or
may call on the flash controllers signature generation logic.
It should be observed that ECC bytes correspond to 64-bit DWORDS in the flash memory, therefore if ECC is
enabled the most significant 64 bits (including the 32 bit signature word) must be written all at once (else the ECC
byte will be corrupted by the second write). If using the flash controller to generate the signature value, user should
take care to leave the unused 32 bits paired with the signature word in their erased state (0xFFFF_FFFF). Failing to
do so may result in spurious ECC errors after device reset and could (depending on FLCC_WRPROT configuration)
render the device irrecoverably unusable.
The Sign command generates a signature for all data from the start page to the end page (excluding the signature
meta-data word). User code must define the start and end pages by writing FLCC_PAGE_ADDR0.VALUE and
FLCC_PAGE_ADDR1.VALUE respectively.
The following procedure should be followed to generate or verify a signature:
• Write FLCC_PAGE_ADDR0.VALUE: the start address of a contiguous set of pages (if out of bounds, the command will be denied)
• Write FLCC_PAGE_ADDR1.VALUE: the end address of a contiguous set of pages (if out of bounds, the command will be denied)
• Write FLCC_KEY.VALUE: write the User Key value to the FLCC_KEY register
• Write FLCC_CMD.VALUE: write the SIGN command to the command register.
• [WAIT]: when the command has completed the FLCC_STAT.CMDCOMP bit will be set in the FLCC_STAT
register
• If using the Flash Controller to generate a signature to write into the flash meta-data, the signature value
may be read from the FLCC_SIGNATURE register.
• The generated signature is automatically compared with the data stored in the most significant 32-bit
word of the region being signed. If the generated result does not match the stored value, a fail is reported
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–13
Protection and Integrity
in the FLCC_STAT register by asserting verify error in the FLCC_STAT.CMDFAIL bit field (10 binary
value).
While the signature is being computed all other accesses to the flash are stalled. Generating/verifying the signature
for a 256 KB block (full User Space) results in a stall duration of 32 KB flash reads (64 bits per read operation) or
approximately 64k HCLK periods.
NOTE: FLCC_PAGE_ADDR0.VALUE and FLCC_PAGE_ADDR1.VALUE addresses may be written as byte addresses
but are consumed by the flash controller as page addresses (the lower 10 address bits are ignored). SIGN command
will be denied if FLCC_PAGE_ADDR1.VALUE is less than FLCC_PAGE_ADDR0.VALUE. Signatures are always performed at a page-level granularity over continuous address ranges.
Key Register
To prevent spurious and potentially damaging flash accesses, some commands and registers are key protected. The
User Key is not a security element and is not meant to be a secret. Instead, this key protects users from negative
consequences of software bugs (especially during early software development).
UserKey
This key serves to prevent accidental access to some flash features and addresses. The key value is 0x676C_7565.
This key must be entered to run protected user commands (ERASEPAGE, SIGN, MASSERASE, and ABORT), or
to enable write access to the FLCC_UCFG or FLCC_TIME_PARAM0 and FLCC_TIME_PARAM1 registers. Once entered, the key remains valid until an incorrect value is written to the key register, or a command is written to the
FLCC_CMD register when any command is requested this key is automatically cleared. If this key is entered to enable
write access to the FLCC_UCFG or FLCC_TIME_PARAM0 and FLCC_TIME_PARAM1 registers then it is recommended to clear the key immediately after updating the register(s).
ECC
The Flash Controller provides ECC based error detection and correction for flash reads. ECC is enabled by default
for Info Space, and thus provides assurance that flash initialization functions work properly (info space signature
check unconditionally takes ECC into account).
The Flash Controller uses an 8-bit Hamming-modified code to correct 1-bit errors or detect 2-bit errors for any
dualword (64-bit) flash data access.
When enabled, the ECC engine is active during signature checks (refer to Signatures section). User code may request
a signature check of the entirety of User Space then check the FLCC_STAT.ECCERRCMD field in the FLCC_STAT
register to determine if any single or dual bit data corruptions are present in User Space.
Defaults and Configuration
In User Space, ECC is OFF by default but may be selectively enabled by using the User code. Enabling ECC requires setting the FLCC_ECC_CFG.EN bit in the FLCC_ECC_CFG register. When enabled, ECC may apply to the
entirety of User Space or may be configured to apply only to a limited range. A single page address pointer
(FLCC_ECC_CFG.PTR) is used to define the start address for ECC; all flash addresses from the start page through
the top of User Space (inclusive) will have ECC enabled when FLCC_ECC_CFG.EN is set.
13–14
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Protection and Integrity
ECC errors may be optionally reported as Bus Errors for ICode or DCode reads, or may generate interrupts. Independent error reporting options are available for 1-bit corrections and 2-bit error detections by writing the
FLCC_IEN.ECC_ERROR and FLCC_IEN.ECC_CORRECT bit fields of the FLCC_IEN register.
Error Handling
The impact of ECC errors during the information space signature check is described in Signatures. On any read
operation, if the ECC engine observes a 1 bit error it will be corrected automatically (the 1-bit error could be in the
ECC byte itself, or in the 64-bit dualword being read by the user). If a 2-bit error is observed the ECC engine can
only report the detection event (2-bit errors cannot be corrected).
Depending on when the read happens (for example, during an ICode or DCode read, or as part of a built-in command such as a signature check) appropriate flags are set in the status register (FLCC_STAT.ECCERRCMD,
FLCC_STAT.ECCRDERR, FLCC_STAT.ECCINFOSIGN, and so on). See the description field of the FLCC_STAT
register for details.
If interrupt generation is enabled in the FLCC_IEN.ECC_ERROR/ FLCC_IEN.ECC_CORRECT fields of the
FLCC_IEN register, the source address of the ECC error causing the interrupt will be available in FLCC_ECC_ADDR
for the interrupt service routine to read.
ECC Errors during Execution of 'sign' Command
ECC errors observed during signature checks will generate the appropriate status register flags after completion but
will not populate the FLCC_ECC_ADDR register.
Concurrent Errors
If ECC errors occur on DCODE and ICODE simultaneously (for example, from an ICODE prefetch match and a
DCODE flash read), then ECC error status information is prioritized as follows:
• First Priority: 2-bit ECC errors are given priority over 1bit ECC errors/corrections.
For example, if a 2-bit ECC error is observed on a DCODE read in the same cycle as a 1bit ecc error/correction on
an ICODE read, then the ECC error status is updated for DCODE only.
• Second Priority: ICODE is given priority over DCODE.
For example, if a 2-bit error is observed on an ICODE read and a DCODE read in the same cycle, then the ECC
error status is updated for ICODE only.
Read of Erased Location
When erased, the flash memory holds a value of all ONES, including the ECC byte appended to every 64 bit
DWORD. The proper ECC meta-data for 64 ONES is not 0xFF, therefore in its erased state the flash memory
holds data and ECC meta-data representing some number of bit errors.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–15
Flash Functional Description
For this reason any flash reads of erased locations will automatically bypass the ECC engine. If user code reads a
location with all ONES in both the 64 bit DWORD and the ECC byte, the read will return data without indicating
any ECC errors.
Clock and Timings
The Flash Controller is preconfigured to provide safe timing parameters for all flash operations for core clock frequencies of 26 MHz or less and reference clock frequency of 13 MHz (+/- 10%).
If the reference clock is not within 10% of 13 MHz, user code should adjust the timing parameters accordingly.
Flash Operating Modes
The flash memory used by the ADuCM302x processor supports the following power optimizing features.
Sleep Mode
The user code may put the Flash IP into a low power sleep mode by writing the SLEEP command to the
FLCC_CMD register. The Flash controller wakes the Flash IP from sleep automatically on the first flash access following a sleep command. The user code may observe the sleep state of flash by reading the FLCC_STAT.SLEEPING
bit.
NOTE: The Cache Controller, DMA reads, other peripheral, or user code may attempt to read flash memory at any
time, any of which will trigger a flash wakeup event; it is advisable that user code occasionally poll the
FLCC_STAT.SLEEPING bit to verify that the flash IP is still sleeping when the user expects it to be.
The flash controller will not honor any new commands (Write, Erase, and do on) while the flash IP is in sleep
mode; the only supported commands in this mode are IDLE and ABORT. DMA write requests will be stalled automatically by entering sleep mode.
System Interrupt based aborts (as configured through the FLCC_ABORT_EN_LO registers) are generally used to abort
any ongoing flash commands in the event of an enabled system interrupt. However, such an interrupt will not wake
the flash from sleep mode. If the system interrupt can be serviced with accessing the flash, it will remain in sleep
mode; if servicing the interrupt requires accessing the flash then the flash access itself will serve to wake the flash IP.
Waking from sleep incurs a ~5us latency before executing any reads or commands (this is a requirement of the flash
IP). User code may wake the flash IP early by executing an IDLE command. This will wake the flash IP without any
other effect on the controller.
For consistency, the ABORT command can also be used to wake the flash IP. Waking with the ABORT command
differs from waking by the IDLE command only in that the status register will report
FLCC_STAT.CMDFAIL:ABORT in order to match expected user code checks for status register values.
Power-down Mode Support
The ADuCM302x processor automatically powers down the flash IP when the device hibernates. To support this
feature, the flash controller interoperates with the power management unit and delays hibernation until any ongoing
13–16
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Flash Operating Modes
flash accesses are completed. User code is responsible for reading and evaluating flash status registers prior to entering hibernate (status registers are not retained in hibernate). The ABORT command may be used to abruptly end an
ongoing flash command but should be used sparingly to avoid eventual damage to the flash array.
Clock Gating
A series of clock gates have been inserted into the flash controller to automatically gate off unused components of
the module. No user configuration or control is required. Unused portions of the flash controller will automatically
be gated off when appropriate (for example, while in Sleep Mode the majority of the flash controller will be gated
off to save power).
Flash Interrupts and Exceptions
The Flash Controller may selectively generate interrupts for many events. The following table outlines the events
that may generate interrupts and bit fields of FLCC_IEN used to control interrupt generation for each event.
Table 13-3:
Interrupts and Bit fields
Name (Bit field)
Description
CMDFAIL
IRQ generated when a command or write operation completes with an error status.
WRALCOMP
IRQ generated when an active flash write is nearly complete and the key-hole registers are open
for another write (if fulfilled in time a BurstWrite will occur).
CMDCMPLT
IRQ generated when a command or flash write operation completes.
ECC_ERROR
IRQ is generated when 2-bit ECC errors are observed when this field is set to 2.
ECC_CORRECT
IRQ is generated when 1-bit ECC corrections are observed when this field is set to 2.
Flash Programming Model
The following section provides an example sequence to execute the Page erase command using the flash controller.
The same sequence can be used for other commands with some modifications.
Programming Guidelines
Here are the programming guidelines:
1. Program the FLCC_PAGE_ADDR0 or FLCC_PAGE_ADDR1 register with the address of the page which needs to
be erased.
2. Write the Flash User Key to the KEY register.
3. Write the command to be executed into the FLCC_CMD register.
4. Poll for the FLCC_STAT.CMDCOMP bit to be set in the FLCC_STAT register.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–17
ADuCM302x FLCC Register Descriptions
ADuCM302x FLCC Register Descriptions
Flash Controller (FLCC) contains the following registers.
Table 13-4:
ADuCM302x FLCC Register List
Name
Description
FLCC_ABORT_EN_HI
IRQ Abort Enable (upper bits)
FLCC_ABORT_EN_LO
IRQ Abort Enable (lower bits)
FLCC_CMD
Command
FLCC_ECC_ADDR
ECC Status (Address)
FLCC_ECC_CFG
ECC Config
FLCC_IEN
Interrupt Enable
FLCC_KEY
Key
FLCC_KH_ADDR
WRITE Address
FLCC_KH_DATA0
WRITE Lower Data
FLCC_KH_DATA1
WRITE Upper Data
FLCC_PAGE_ADDR0
Lower Page Address
FLCC_PAGE_ADDR1
Upper Page Address
FLCC_SIGNATURE
Signature
FLCC_STAT
Status
FLCC_TIME_PARAM0
Time Parameter 0
FLCC_TIME_PARAM1
Time parameter 1
FLCC_UCFG
User Configuration
FLCC_WRPROT
Write Protection
FLCC_WR_ABORT_ADDR
Write Abort Address
13–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
IRQ Abort Enable (upper bits)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[47:32] (R/W)
Sys IRQ abort enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[63:48] (R/W)
Sys IRQ abort enable
Figure 13-6: FLCC_ABORT_EN_HI Register Diagram
Table 13-5:
FLCC_ABORT_EN_HI Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/W)
Sys IRQ abort enable.
To allow a system interrupt to abort an ongoing flash command (for example, Erase,
Write, Sign, and so on) write a '1' to the bit in this register corresponding with the
desired system IRQ number.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–19
ADuCM302x FLCC Register Descriptions
IRQ Abort Enable (lower bits)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
Sys IRQ abort enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
Sys IRQ abort enable
Figure 13-7: FLCC_ABORT_EN_LO Register Diagram
Table 13-6:
FLCC_ABORT_EN_LO Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/W)
13–20
Sys IRQ abort enable.
To allow a system interrupt to abort an ongoing flash command (for example, Erase,
Write, Sign, and so on) write a '1' to the bit in this register corresponding with the
desired system IRQ number.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Command
Write this register to execute a specified command. The user key (see FLCC_KEY register for details) must first be
written to the FLCC_KEY Register for most command requests to be honored (see details below).
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Commands
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-8: FLCC_CMD Register Diagram
Table 13-7:
FLCC_CMD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3:0 VALUE
(R/W)
Commands.
Write command values to this register to begin a specific operation. All commands but
WRITE and IDLE require first writing the User Key to the FLCC_KEY register
0 IDLE No key is required. No command executed; if
Flash IP was in the SLEEP state, this command gracefully wakes the flash (returns command complete and
no error codes)
1 ABORT [User key] is required. The ABORT command
should be used sparingly as a last resort mechanism to
gain access to the flash IP during time-sensitive events.
For example a low voltage alarm may be cause to abort
an ongoing flash write or erase command to enable user
code to shutdown the part gracefully. Note that the flash
array may be damaged by over-use of the ABORT command. If this command is issued then any command
currently in progress will be abruptly stopped (if possible). The status will indicate command completed with
an error of ABORT. ABORT is the only command that
can be issued while another command is already in
progress (with one exception: user code may stack one
WRITE command on top of a single on-going WRITE
command; all other overlapping command combinations are invalid unless the new command is an
ABORT). If a write or erase is aborted then some flash
IP timing requirements may be violated and it is not
possible to determine if the write or erase completed
successfully. User code should read the affected locations
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–21
ADuCM302x FLCC Register Descriptions
Table 13-7:
FLCC_CMD Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
to determine the outcome of the aborted commands.
Note that an aborted command may result in a weakly
programmed flash: it is always advisable to erase the affected region and reprogram it. Depending on how far
along the flash controller is in the process of performing
a command, an ABORT is not always possible (some
flash IP timing parameters must not be violated). This is
difficult (if not impossible) to predict in software, therefore ABORTS should be considered a request which
may have no affect on actual command duration.
2 Requests flash to enter Sleep mode [User Key] is required. Requests the flash controller to put the flash to
sleep (a low power mode). When sleeping, any ICode,
DCode, or DMA transaction will wake the flash automatically. Wake-up process takes ~5us (configurable in
FLCC_TIME_PARAM1 register). If user code can predict
~5us ahead of time that the flash will be required, user
may write an IDLE command to the FLCC_CMD register
to manually wake the flash. An ABORT command is also respected for waking the part (and will return appropriate status indicating that the sleep command was
aborted). Once awoken for any reason, the part will remain awake until user code once again asserts a SLEEP
command.
3 SIGN [User key] is required. Use this command to generate a signature for a block of data. Signatures may be
generated for blocks of whole pages only. The address of
the start page should be written to the
FLCC_PAGE_ADDR0 register, the address of the end
page written to the FLCC_PAGE_ADDR1 register, and
then write this code to the FLCC_CMD register to start
the signature generation. When the command has complete the signature will be readable from the
FLCC_SIGNATURE register. More information on this
command is in 'signature' section
4 WRITE No key is required. This command takes the
address and data from the FLCC_KH_ADDR,
FLCC_KH_DATA0, and FLCC_KH_DATA1 registers and
executes a single 64-bit WRITE operation targeting the
specified address. More information can be found in
'writing to flash' and 'write protection' section.
5 Checks all of User Space; fails if any bits in user space
are cleared [User Key] is required. Performs a blank
13–22
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Table 13-7:
FLCC_CMD Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
check on all of user space. If any bits in user space are
cleared the command will fail with a READ VERIFY
status. If all of user space is FFs the command will pass.
This command is intended to support early customer
software development. When an unprogrammed part
boots with security features preventing reads and writes
of user space, this command may be used to verify that
the user space contains no proprietary information. If
this command passes read and write protection of user
space will be cleared.
6 ERASEPAGE [User key] is required. Write the address
of the page to be erased to the FLCC_PAGE_ADDR0 register, then write this code to the FLCC_CMD register.
When the erase has completed the full page will be verified (read) automatically to ensure a complete erasure. If
there is a read verify error this will be indicated in the
FLCC_STAT register. To erase multiple pages wait until
a previous page erase has completed check the status
then issue a command to start the next page erase.
7 MASSERASE [User key] is required. Erase all of flash
user space. When the erase has completed the full user
space will be verified (read) automatically to ensure a
complete erasure. If there is a read verify error this will
be indicated in the Status register.
8 Reserved
9 Reserved
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–23
ADuCM302x FLCC Register Descriptions
ECC Status (Address)
This register is updated on ECC errors or corrections as selected to generate interrupts (IRQ) in the FLCC_IEN
register. this register is not updated in the event of an ECC error or correction which instead generates a bus fault.
This register records the address of the first ECC error or correction event to generate an interrupt since the last time
the ECC status bits were cleared (or since reset). If the status bits are cleared in the same cycle as a new ECC event
(selected to generate an IRQ), a new address will be recorded and the status bits will remain set. Errors have priority
over corrections (2 or more bits corrupt = ERROR; a correction results in proper data being returned after a single
bit is corrected). If an error and a correction occur in the same cycle, this register will report the ERROR address.
When two of the same priority ECC events occur (both ERROR or both CORRECTION) the ICODE bus has
priority over DCODE. Therefore if both ICODE and DCODE buses generate the same type of ECC event in the
same cycle, the ICODE address will be stored in this register. The register cannot be cleared except by reset; it will
always hold the address of the most recently reported ECC correction or error.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
This register has the address for which
ECC error is detected
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[18:16] (R)
This register has the address for which
ECC error is detected
Figure 13-9: FLCC_ECC_ADDR Register Diagram
Table 13-8:
FLCC_ECC_ADDR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
18:0 VALUE
This register has the address for which ECC error is detected.
(R/NW)
13–24
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
ECC Config
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
PTR[7:0] (R/W)
ECC start page pointer (user should
write bits [31:8] of the start page address
into bits [31:8] of this register)
EN (R/W)
ECC Enable
INFOEN (R/W)
Info space ECC Enable bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PTR[23:8] (R/W)
ECC start page pointer (user should
write bits [31:8] of the start page address
into bits [31:8] of this register)
Figure 13-10: FLCC_ECC_CFG Register Diagram
Table 13-9:
FLCC_ECC_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:8 PTR
(R/W)
ECC start page pointer (user should write bits [31:8] of the start page address into bits
[31:8] of this register).
A byte-address for any page in flash User Space. The bottom bits of this address will be
ignored by the flash controller, forming a Page Address. When ECC is enabled and
user code reads any address from within the page specified or any more significant
page, ECC functions will be performed. Reads from less significant pages will bypass
ECC entirely.
1 INFOEN
(R/W)
0 EN
(R/W)
Info space ECC Enable bit.
ECC is enabled by default for Info Space; clearing this bit disables ECC in info space.
this bit is not key protected.
ECC Enable.
Set this bit to enable ECC on User Space. ECC will be enabled on all future flash reads
in user space from any address between ECC_CFG:POINTER through the top of
User Space (inclusive). When cleared (or accessing addresses outside the enabled
range), the flash controller will return the raw data in response to both ICode and
DCode reads of User Space; no error corrections will be made or reported.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–25
ADuCM302x FLCC Register Descriptions
Interrupt Enable
Used to specify when interrupts will be generated.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
0
ECC_ERROR (R/W)
Control whether to generate bus errors,
interrupts, or neither in response to
2-bit ECC Error events
CMDCMPLT (R/W)
Command complete interrupt enable
WRALCMPLT (R/W)
Write almost complete interrupt enable
ECC_CORRECT (R/W)
Control whether to generate bus errors,
interrupts, or neither in response to
1-bit ECC Correction events
CMDFAIL (R/W)
Command fail interrupt enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-11: FLCC_IEN Register Diagram
Table 13-10:
FLCC_IEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:6 ECC_ERROR
(R/W)
Control whether to generate bus errors, interrupts, or neither in response to 2-bit ECC
Error events.
0 Do not generate a response to ECC events
1 Generate Bus Errors in response to ECC events
2 Generate IRQs in response to ECC events
5:4 ECC_CORRECT
(R/W)
Control whether to generate bus errors, interrupts, or neither in response to 1-bit ECC
Correction events.
0 Do not generate a response to ECC events
1 Generate Bus Errors in response to ECC events
2 Generate IRQs in response to ECC events
2 CMDFAIL
(R/W)
1 WRALCMPLT
Command fail interrupt enable.
If this bit is set then an interrupt will be generated when a command or flash write
completes with an error status.
Write almost complete interrupt enable.
(R/W)
0 CMDCMPLT
(R/W)
13–26
Command complete interrupt enable.
When set, an interrupt will be generated when a command or flash write completes.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Key
When user code must write a key to access protected features, the key value must be written to this register.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Key register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Key register
Figure 13-12: FLCC_KEY Register Diagram
Table 13-11:
FLCC_KEY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(RX/W)
Key register.
Unlock protected features by writing the appropriate key value to this register
1735161189 USERKEY Write this field with hex value 0x676C7565
to enable certain registers to be modified or to allow certain commands to be executed. This key is used as a sanity check to prevent accidental modification of settings
or flash content. It is not a security component and is
not intended to be secret information.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–27
ADuCM302x FLCC Register Descriptions
WRITE Address
Write the byte-address of any byte of a 64-bit dual-word flash location to be targeted by a WRITE command. All
writes target 64-bit dual-word elements in the flash array. User code may byte-mask data to emulate byte, hword, or
word writes. Flash IP specifications warn that no location should be written more than twice between erasures.
When writing a location more than once, user should be aware that ECC meta-data cannot be updated appropriately; user code should disable ECC for the relevant region of flash. (Writing any address above the valid range of flash
memory will saturate the address to prevent aliasing; user code should take care to target valid flash address locations)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[12:0] (R/W)
Address to be written on a WRITE command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[15:13] (R/W)
Address to be written on a WRITE command
Figure 13-13: FLCC_KH_ADDR Register Diagram
Table 13-12:
FLCC_KH_ADDR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
18:3 VALUE
Address to be written on a WRITE command.
(R/W)
13–28
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
WRITE Lower Data
The lower half of 64-bit dualword data to be written to flash
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
VALUE[15:0] (R/W)
Lower half of 64-bit dual word data to
be written on a WRITE command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VALUE[31:16] (R/W)
Lower half of 64-bit dual word data to
be written on a WRITE command
Figure 13-14: FLCC_KH_DATA0 Register Diagram
Table 13-13:
FLCC_KH_DATA0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Lower half of 64-bit dual word data to be written on a WRITE command.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–29
ADuCM302x FLCC Register Descriptions
WRITE Upper Data
The lower half of 64-bit dualword data to be written to flash.
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
VALUE[15:0] (R/W)
Upper half of 64-bit dual word data to
be written on a WRITE command
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
VALUE[31:16] (R/W)
Upper half of 64-bit dual word data to
be written on a WRITE command
Figure 13-15: FLCC_KH_DATA1 Register Diagram
Table 13-14:
FLCC_KH_DATA1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/W)
13–30
Upper half of 64-bit dual word data to be written on a WRITE command.
If DMA is enabled, then this register acts as a FIFO. Writes to this register will push
the old data to lower 32 bit of 64 bit data (FLCC_KH_DATA0). When this register is
written twice (in DMA mode) the FIFO becomes full and a flash write command is
automatically be executed.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Lower Page Address
Write a byte-address to this register to select the page in which that byte exists. The selected page may be used for a
ERASEPAGE command (selecting which page to erase) or for a SIGN command (selecting the start page for a block
on which a signature should be calculated). For commands using both FLCC_PAGE_ADDR0 and
FLCC_PAGE_ADDR1, user should ensure that FLCC_PAGE_ADDR0 is always less than or equal to
FLCC_PAGE_ADDR1, else the command is denied. Writing any address above the valid range of flash memory saturates the address register to prevent aliasing in the flash memory space.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[5:0] (R/W)
Lower address bits of the page address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[8:6] (R/W)
Lower address bits of the page address
Figure 13-16: FLCC_PAGE_ADDR0 Register Diagram
Table 13-15:
FLCC_PAGE_ADDR0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
18:10 VALUE
Lower address bits of the page address.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–31
ADuCM302x FLCC Register Descriptions
Upper Page Address
Write a byte-address to this register to select the page in which that byte exists. The selected page may be used for a
SIGN command (selecting the end page for a block on which a signature should be calculated). For commands using both FLCC_PAGE_ADDR0 and FLCC_PAGE_ADDR1, user should ensure that FLCC_PAGE_ADDR0 is always less
than or equal to FLCC_PAGE_ADDR1, else the command is denied. Writing any address above the valid range of
flash memory saturates the address register to prevent aliasing in the flash memory space.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[5:0] (R/W)
Upper address bits of the page address
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[8:6] (R/W)
Upper address bits of the page address
Figure 13-17: FLCC_PAGE_ADDR1 Register Diagram
Table 13-16:
FLCC_PAGE_ADDR1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
18:10 VALUE
Upper address bits of the page address.
(R/W)
13–32
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Signature
Provides read access to the most recently generated signature.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
X X X X X X X X X X X X X X X X
VALUE[15:0] (R)
Provides read access to the most recently
generated signature
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X X X X X X X X X X X X X X X X
VALUE[31:16] (R)
Provides read access to the most recently
generated signature
Figure 13-18: FLCC_SIGNATURE Register Diagram
Table 13-17:
FLCC_SIGNATURE Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Provides read access to the most recently generated signature.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–33
ADuCM302x FLCC Register Descriptions
Status
Provides information on current command states and error detection/correction.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ECCINFOSIGN[0] (R)
ECC status of flash initialization
CMDBUSY (R)
Command busy
INIT (R)
Flash controller initialization in progress
WRCLOSE (R)
WRITE registers are closed
SIGNERR (R)
Signature check failure during initialization
CMDCOMP (R/W1C)
Command complete
OVERLAP (R/W1C)
Overlapping Command
WRALCOMP (R/W1C)
Write almost complete
ECCRDERR (R/W1C)
ECC IRQ cause
CMDFAIL (R/W1C)
Provides information on command failures
ECCERRCMD (R/W1C)
ECC errors detected during user issued
SIGN command
SLEEPING (R)
Flash array is in low power (sleep) mode
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
CACHESRAMPERR (R)
SRAM parity errors in Cache Controller
ECCINFOSIGN[1] (R)
ECC status of flash initialization
ECCDCODE (R/W1C)
DCode AHB Bus Error ECC status
ECCERRCNT (R/W1C)
ECC correction counter
ECCICODE (R/W1C)
ICode AHB Bus Error ECC status
Figure 13-19: FLCC_STAT Register Diagram
Table 13-18:
FLCC_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
29 CACHESRAMPERR
(R/NW)
13–34
SRAM parity errors in Cache Controller.
This register provides details for AHB Errors generated due to cache SRAM parity error on the ICODE bus.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Table 13-18:
FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
28:27 ECCDCODE
(R/W1C)
DCode AHB Bus Error ECC status.
Provides details for AHB Bus Errors generated due to ECC errors and/or corrections
on the DCODE bus.
0 No Error No errors or corrections reported since reset or
the register was last cleared
1 2-bit Error 2-bit ECC error has been detected and reported on AHB read access
2 1-bit Correction 1-bit ECC correction has been detected and reported on AHB read access
26:25 ECCICODE
(R/W1C)
ICode AHB Bus Error ECC status.
Provides details for AHB Bus Errors generated due to ECC errors and/or corrections
on the ICODE bus.
0 No Error No errors or corrections reported since reset or
the register was last cleared
1 2-bit Error 2-bit ECC error has been detected and reported on AHB read access
2 1-bit Correction 1-bit ECC correction has been detected and reported on AHB read access
19:17 ECCERRCNT
(R/W1C)
16:15 ECCINFOSIGN
(R/NW)
ECC correction counter.
This counter keeps track of overlapping ECC 1-bit correction reports. When configured to generate IRQs or AHB Bus Errors in the event of an ECC correction event,
this field counts the number of ECC corrections that occur after the first reported correction. The counter remains at full scale when it overflows and clears automatically
when clearing either FLCC_STAT.ECCICODE or FLCC_STAT.ECCDCODE status bits.
ECC status of flash initialization.
ECC status after the end of automatic signature check on Info space.
0 No Error No errors reported.
1 2-bit error 1 or more 2-bit ECC Errors detected during
signature check (signature check has failed)
2 1-bit error 1 or more 1-bit ECC Corrections performed
during signature check. (signature check will pass if
checksum still matches)
3 1- and 2-bit error At least one of each ECC event (1-bit
Correction and 2-bit Error) were detected during signature check (signature check will fail).
14 INIT
Flash controller initialization in progress.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–35
ADuCM302x FLCC Register Descriptions
Table 13-18:
FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
(R/NW)
13 SIGNERR
(R/NW)
11 OVERLAP
(R/W1C)
10:9 ECCRDERR
(R/W1C)
Flash controller initialization is in progress. Until this bit de-asserts AHB accesses will
stall and APB commands will be ignored.
Signature check failure during initialization.
Indicates an automatic signature check has failed during flash controller initialization.
The register value is valid only after the signature check has completed.
Overlapping Command.
This bit is set when a command is requested while another command is busy (overlapping commands will be ignored)
ECC IRQ cause.
This field reports the cause of recently generated interrupts. The controller may be
configured to generate interrupts for 1- or 2-bit ECC events by writing the appropriate
values to FLCC_IEN.ECC_ERROR and FLCC_IEN.ECC_ERROR. These bits are sticky
high until cleared by user code.
0 No Error
1 2-bit Error ECC engine detected a non-correctable 2-bit
error during AHB read access
2 1-bit Correction ECC engine corrected a 1-bit error
during AHB read access
3 1- and 2-bit Events ECC engine detected both 1- and 2bit data corruptions which triggered IRQs (note that a
single read can only report one type of event; this status
indicates that a subsequent AHB read access incurred
the alternate ECC error event) By default 1-bit ECC
corrections are reported as IRQs and 2-bit ECC errors
are reported as bus faults. It is not recommended to report both types as IRQs else the status bits become ambiguous when trying to diagnose which fault came first.
13–36
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Table 13-18:
FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
8:7 ECCERRCMD
(R/W1C)
ECC errors detected during user issued SIGN command.
ECC errors, if produced during signature commands, are reported by these bits. To
generate interrupts base on these bits user code should set the corresponding bits in
FLCC_IEN register.
0 success no error, successful flash read operation during
signature check
1 2-bit error During signature commands, 2 bit error is
detected on one or more flash locations, not corrected.
2 1-bit error 1 bit error is corrected for one or more flash
locations while doing signature commands
3 1 or 2 bit error During signature commands, 1 bit error
and 2 bit errors are detected on one or more flash locations
6 SLEEPING
(R/NW)
Flash array is in low power (sleep) mode.
Indicates that the flash array is in a low power (sleep) mode. The flash controller automatically wakes the flash when required for another data transaction. User may wake
the flash at any time by writing the IDLE command to the FLCC_CMD register. Flash
wake-up times vary but are typically ~5us. When possible, it is recommend that the
user begin waking the flash ~5us before it will be used as a performance optimization.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–37
ADuCM302x FLCC Register Descriptions
Table 13-18:
FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5:4 CMDFAIL
(R/W1C)
Provides information on command failures.
This field indicates the status of a command upon completion. If multiple commands
are executed without clearing these bits then only the first error encountered is stored.
0 success Successful completion of a command (e.g.
WRITE)
1 ignored Attempted access of a protected or out of memory location (such a command is ignored).
2 verify error Read verify error occurred. This status will
be returned for either of 2 causes; Failed erasures and/or
failed signature checks. Failed Erasure: After erasing
flash page(s) the controller reads the corresponding
word(s) to verify that the erasure completed successfully.
If data still persists, the erasure has failed and this field
reports the failure. Failed signature check: If the Sign
command is executed and the resulting signature does
not match the data stored in the most significant 32-bit
word of the sign-checked block, the sign check has
failed and this field reports the failure.
3 abort Indicates a command was aborted either by user
code (abort command issued) or by a system interrupt
(see FLCC_ABORT_EN_HI and FLCC_ABORT_EN_LO
registers for details)
3 WRALCOMP
(R/W1C)
2 CMDCOMP
(R/W1C)
1 WRCLOSE
(R/NW)
13–38
Write almost complete.
WRITE data registers are re-opened for access as an ongoing write nears completion.
Requesting another write operation* before FLCC_STAT.CMDCOMP asserts will result
in a "burst write". Burst writes take advantage of low level protocols of the Flash memory and result in significant performance gains (~15us saved from each write operation). *Note that the performance gain of a Burst Write only applies to back-to-back
writes within the same row of the flash array. See the flash IP spec for memory organization details.
Command complete.
This bit asserts when a command completes. (Automatically clears when a new command is requested) NOTE: Following a power-on-reset, the flash controller performs a
number of operations (e.g. verifying the integrity of code in info space). At the conclusion of this process the controller sets the FLCC_STAT.CMDCOMP bit to indicate that
the process has completed.
WRITE registers are closed.
The WRITE data/address registers and the command register are closed for access.
This bit is asserted part of the time while a write is in progress. If this bit is high, the
related registers are in use by the flash controller and cannot be written. This bit clears
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Table 13-18:
FLCC_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
when FLCC_STAT.WRALCOMP flag goes high, indicating that the ongoing write
command has consumed the associated data and these registers may now be overwritten with new data.
0 CMDBUSY
(R/NW)
Command busy.
This bit is asserted when the flash block is actively executing any command entered via
the command register. NOTE: There is a modest delay between requesting a command and having this bit assert; user code polling for command completion should
watch for FLCC_STAT.CMDCOMP bit rather than FLCC_STAT.CMDBUSY.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–39
ADuCM302x FLCC Register Descriptions
Time Parameter 0
[User Key] is required to write this register. This register should not be modified while a flash write or erase command is in progress. This register defines a set of parameters used to control the timing of signals driven to the Flash
Memory. The default values are appropriate for a system clock of 26 MHz and a reference clock (driven by the internal oscillator) operating within 10% of 13 MHz. The value of each timing parameter consists of a user programmable nibble (4 bits) as well as some number of hard-coded bits. User programmable bits are the most significant bits
for each parameter. Time parameters describe the number of ref-clk periods to wait when meeting the associated
timing constraint of the flash memory itself. Note that clock-domain-crossings and the constraints of signals not
described by these parameters will increase the effective delays by a small margin. When programming the time parameter registers the user should select a value approaching the minimum time for each constraint. Improper programming of this register may result in damage to the flash memory during PROGRAM or ERASE operations.
15 14 13 12 11 10 9
0
1
0
1
1
0
0
8
7
6
5
4
3
2
1
0
1
0
1
0
1
0
0
0
0
TPROG (R/W)
Program time
DIVREFCLK (R/W)
Divide Reference Clock (by 2)
TPGS (R/W)
NVSTR to Program setup time
TNVS (R/W)
PROG/ERASE to NVSTR setup time
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
0
1
1
1
0
0
0
1
0
0
1
0
1
0
1
TNVH1 (R/W)
NVSTR Hold time during Mass Erase
TNVH (R/W)
NVSTR Hold time
TERASE (R/W)
Erase Time
TRCV (R/W)
Recovery time
Figure 13-20: FLCC_TIME_PARAM0 Register Diagram
Table 13-19:
FLCC_TIME_PARAM0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:28 TNVH1
(R/W)
27:24 TERASE
(R/W)
23:20 TRCV
NVSTR Hold time during Mass Erase.
Determines the upper 4 bits of an 11 bit value loaded into the timer. The lower bits
are hard-coded to 0x14. With an ideal refclk at 13MHz: Min [0x0] = 1.5us Default
[0xB] = 110us Max [0xF] = 149us
Erase Time.
Determines the upper 4 bits of a 19 bit value loaded into the timer. The lower bits are
hard-coded to 0x7370. With an ideal refclk at 13MHz: Min [0x0] = 2.3ms Default
[0xB] = 30ms Max [0xF] = 40ms
Recovery time.
(R/W)
13–40
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Table 13-19:
FLCC_TIME_PARAM0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
Determines the upper 4 bits of an 8 bit value loaded into the timer. The lower bits are
hard-coded to 0x2. With an ideal refclk at 13MHz: Min [0x0] = 154ns Default [0x9]
= 1.1us Max [0xF] = 18.6us
19:16 TNVH
(R/W)
15:12 TPROG
(R/W)
11:8 TPGS
(R/W)
7:4 TNVS
(R/W)
0 DIVREFCLK
(R/W)
NVSTR Hold time.
Determines the upper 4 bits of an 8 bit value loaded into the timer. The lower bits are
hard-coded to 0x1. With an ideal refclk at 13MHz: Min [0x0] = 77ns Default [0x5] =
5.5us Max [0xF] = 18.5us
Program time.
Determines the upper 4 bits of a 10 bit value loaded into the timer. The lower bits are
hard-coded to 0x04. With an ideal refclk at 13MHz: Min [0x0] = 308ns Default [0x6]
= 30us Max [0xF] = 74.2us
NVSTR to Program setup time.
Determines the upper 4 bits of an 8 bit value loaded into the timer. The lower bits are
hard-coded to 0x2. With an ideal refclk at 13MHz: Min [0x0] = 154ns Default [0x9]
= 1.1us Max [0xF] = 18.6us
PROG/ERASE to NVSTR setup time.
Determines the upper 4 bits of an 8 bit value loaded into the timer. The lower bits are
hard-coded to 0x1. With an ideal refclk at 13MHz: Min [0x0] = 77ns Default [0x5] =
5.5us Max [0xF] = 18.5us
Divide Reference Clock (by 2).
If '1' the reference clock is divided by 2. All time parameters are relative to the reference clock; dividing the clock enables the selection of long time periods if necessary.
NOTE: It is unlikely that user code should ever need to modify the time parameters;
support is provided in the unlikely event that a user finds it necessary.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–41
ADuCM302x FLCC Register Descriptions
Time parameter 1
See FLCC_TIME_PARAM0 for documentation
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
0
TWK (R/W)
Wake up time
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-21: FLCC_TIME_PARAM1 Register Diagram
Table 13-20:
FLCC_TIME_PARAM1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3:0 TWK
(R/W)
13–42
Wake up time.
Determines the upper 4 bits of an 8 bit value loaded into the timer. The lower bits are
hard-coded to 0xB With an ideal refclk at 13MHz: Min [0x0] = 847ns Default [0x4] =
5.7us Max [0xF] = 19.3us
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
User Configuration
[User key] is required (see FLCC_KEY register for details). Write to this register to enable user control of DMA and
Auto-increment features. When user code has finished accessing this register, garbage data should be written to the
FLCC_KEY register to re-assert protection.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
AUTOINCEN (R/W)
Auto address increment for Key hole
access
KHDMAEN (R/W)
Key Hole DMA enable
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 13-22: FLCC_UCFG Register Diagram
Table 13-21:
FLCC_UCFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1 AUTOINCEN
(R/W)
0 KHDMAEN
(R/W)
Auto address increment for Key hole access.
When this bit is set FLCC_KH_ADDR will automatically increment by 0x8 during each
WRITE command or after each READ command. This enables user code to write a
series of sequential flash locations without having to manually set the flash address for
each write. The FLCC_KH_ADDR is incremented, and may be observed by user code,
when FLCC_STAT.WRALCOMP is asserted during a WRITE command, or when
FLCC_STAT.WRALCOMP is asserted after a READ command. When this bit is set user
code may not directly modify FLCC_KH_ADDR
Key Hole DMA enable.
The flash controller will interact with the DMA controller when this bit is set. Prior to
setting this bit, user code should: - Write the starting address to FLCC_KH_ADDR Configure the DMA controller to write data to FLCC_KH_DATA1 (address must be
DWORD aligned) - Configure the DMA controller to always write pairs of 32 bit
words (R Power = 1) - Configure the DMA controller to write an integer number of
data pairs (for an odd number of words user code must write one word manually without the help of DMA) Note that all DMA writes will automatically increment the target address (similar to the behavior of FLCC_UCFG.AUTOINCEN). The DMA controller may only be used to write sequential addresses starting from the value of
FLCC_KH_ADDR The flash controller will automatically begin write operations each
time the DMA controller provides a pair of words to write. Interaction with the DMA
controller has been designed to use burst writes which may significantly reduce overall
programming time.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–43
ADuCM302x FLCC Register Descriptions
Write Protection
[User Key] is required to modified this register. The FLCC_WRPROT register may be automatically configured during
device boot up; in this event the boot loader reads data from user space and loads that data into this register. User
code may affect non-volatile write protection by writing to the appropriate location in the flash memory (see chapter
on Protection for details). By default, the relevant location in flash is 0x3FFF0 (the 4th most significant word in user
space), but may be relocated by ADI's secure bootloader. User code may alternatively assert protection at runtime for
any unprotected blocks by directly writing this register: Blocks may have protection added but cannot have protection removed; changes will be lost on reset. This approach is suggested especially during user code development. All
write protection is cleared on a power-on-reset but note that the ADI secure bootloader will reassert write protection
as defined by the FLCC_WRPROT word in user space before enabling user access to the flash array. Therefore removing write protection can only be performed by an ERASEPAGE command of the most significant page in user space
(provided that page is not currently protected) or by a MASSERASE command. Following a successful MASSERASE command all protection of pages in user space is immediately cleared (user may write to user space immediately
following such an erase without a device reset required).
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
WORD[15:0] (R/W0C)
Clear bits to write protect related groups
of user space pages. Once cleared
these bits can only be set again by
resetting the part
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
WORD[31:16] (R/W0C)
Clear bits to write protect related groups
of user space pages. Once cleared
these bits can only be set again by
resetting the part
Figure 13-23: FLCC_WRPROT Register Diagram
Table 13-22:
FLCC_WRPROT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 WORD
(R/W0C)
Clear bits to write protect related groups of user space pages. Once cleared these bits
can only be set again by resetting the part.
Each bit of this 32 bit word represents a 32nd of the total available user space. For
256kB parts consisting of 2kB pages (128 pages) each bit represents the write protection state of a group of 4 pages. For 128kB parts consisting of 2kB pages (64 pages)
each bit represents the write protection state of a group of 2 pages. for 64kB parts consisting of 2kB pages (32 pages) each bit represents the write protection state of a single
13–44
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x FLCC Register Descriptions
Table 13-22:
Bit No.
FLCC_WRPROT Register Fields (Continued)
Bit Name
Description/Enumeration
(Access)
page. The most significant bit of this register corresponds to the most significant group
of pages in user space.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
13–45
ADuCM302x FLCC Register Descriptions
Write Abort Address
Address of recently aborted write command. This address is only populated if the aborted write command was started; if the command is aborted early enough to have no affect on the flash IP this address will not be updated.
15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
X X X X X X X X X X X X X X X X
VALUE[15:0] (R)
Holds the address targeted by an ongoing
write command and retains its value
after an ABORT event
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
X X X X X X X X X X X X X X X X
VALUE[31:16] (R)
Holds the address targeted by an ongoing
write command and retains its value
after an ABORT event
Figure 13-24: FLCC_WR_ABORT_ADDR Register Diagram
Table 13-23:
FLCC_WR_ABORT_ADDR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
(R/NW)
Holds the address targeted by an ongoing write command and retains its value after an
ABORT event.
User code may read this register to determine the flash location(s) affected a write
abort. The register value is not guaranteed to persist once a new flash command is requested, therefore user code should read this value immediately following an aborted
WRITE.
13–46
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Static Random Access Memory (SRAM)
14 Static Random Access Memory (SRAM)
This chapter provides an overview of the SRAM functionality of the ADuCM302x processor.
SRAM Features
The SRAM used by the ADuCM302x processor supports the following features:
• Low power controller for data SRAM, instruction SRAM and cache SRAM.
• Total available memory: 64 KB
• Maximum retained memory in the Hibernate mode: 32 KB
• Data SRAM is composed of 32 KB. Option to retain 8 KB or 16 KB in the Hibernate mode.
• Instruction SRAM is composed of 32 KB. Option to retain 16 KB in the Hibernate mode.
• If instruction SRAM is not enabled, the associated 32 KB can be mapped as data SRAM. In this case we have
the option to retain 8 KB, 16 KB, 24 KB or 32 KB of data SRAM.
• When cache controller is enabled, 4 KB of the Instruction SRAM will be reserved for cache data. Those 4 KB
of cache data are not retained in the Hibernate mode.
• Parity bit error detection (optional) is available on all SRAM memories. Two parity bits are associated with each
32-bit word. Parity check can be configured to be enabled/disabled in different memory regions.
• Byte, Half Word, and Word accesses are supported.
For more information, refer to SRAM Region.
SRAM Configuration
The following section describes the SRAM configuration:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
14–1
SRAM Configuration
Instruction vs Data SRAM
If the PMG_TST_SRAM_CTL.INSTREN bit is asserted, 32 KB of SRAM is mapped at start address 0x1000_0000 as
Instruction SRAM (see MODE0 in memory map). 32 KB of data SRAM is mapped in two sections, the first starting at 0x2000_0000 and the second starting at 0x2004_0000. If cache memory feature is used, only 28 KB is
available for instruction SRAM (see MODE1 in memory map).
If PMG_TST_SRAM_CTL.INSTREN bit is 0 and cache is disabled, the 64 KB of SRAM is mapped as data SRAM.
The memory is arranged in two sections, the first one (32 KB) is mapped at start address 0x2000_0000 and the
second one (32 KB) at 0x2004_0000 (see MODE2 in memory map). If cache memory feature is used, the second
section will only map 28 KB, so the total data SRAM available is 60 KB (see MODE3 in memory map).
By default, at power up and hardware reset, the 32 KB of SRAM is made available as instruction SRAM. If the user
needs to exercise the option of using a total of 64 KB data SRAM, the PMG_TST_SRAM_CTL.INSTREN bit must be
programmed to zero at the start of the user code.
When cache controller is enabled, SRAM bank 5 is not accessible. A bus error (unmapped address) is generated if an
access is attempted.
For more information, refer to the SRAM Region
SRAM Retention in Hibernate Mode
In terms of the amount of SRAM being retained during the Hibernate mode, different configurations available to
the user:
The content of the first 8 KB (Bank0) of data SRAM mapped at 0x2000_0000 is always retained. The SRAM mapped from 0x2004_0000 onwards (Bank3, Bank4, and Bank5) cannot be retained in the Hibernate mode.
If the PMG_TST_SRAM_CTL.BNK1EN bit is enabled, 8 KB of data SRAM mapped from 0x2000_2000 to
0x2000_3FFF (Bank1) is retained in the Hibernate mode.
If PMG_TST_SRAM_CTL.INSTREN = 1 and PMG_TST_SRAM_CTL.BNK2EN bit is enabled, 16 KB of instruction
SRAM mapped from 0x1000_0000 to 0x1000_3FFF (Bank2) is retained.
If PMG_TST_SRAM_CTL.INSTREN = 0, 16 KB of data SRAM mapped from 0x2000_4000 to 0x2000_7FFF is retained.
SRAM Programming Model
The SRAM programming model is explained below.
Stack
The SRAM start address is set to 0x2000_0000 and the stack pointer is set at 0x2000_2000. The stack will be written from 0x2000_1FFF downwards. The covered memory region is always be retained (see SRAM Region). To reserve a given size for the stack area, the user can declare a data array of that desired size ending at position
0x2000_1FFF. This way, the stack will not be overwritten by the compiler when allocating new variables.
14–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
SRAM Parity
SRAM Parity
For robustness, parity check can be enabled on all or a user selected group of SRAM banks. Parity check can detect
up to 2 errors per word. Parity check feature can be enabled by asserting PMG_TST_SRAM_CTL.PENBNK0 to
PMG_TST_SRAM_CTL.PENBNK5 bits for each SRAM bank. It is recommended to the user to configure this bit at
the beginning of the program code.
Parity is checked when data is read and when byte or halfword data is written. Parity is not checked when word (32
bits) write is performed. If a parity error is detected, a bus error is generated. Even if parity error is detected when
writing a byte or halfword, the write operation is completed and parity bits are updated according to the new data.
User must manage the parity error in the bus fault interrupt routine.
SRAM Initialization
If parity check is enabled, SRAM contents have to be initialized to avoid false parity errors. A dedicated hardware
can automatically initialize the selected SRAM banks and the whole process takes 1024 HCLK cycles to complete.
This hardware is fully programmable by the user so initialization can be started automatically or manually.
As initialization will overwrite the contents of the selected SRAM banks, this process must be performed before writing to those SRAMs. If during the initialization sequence, a write or read access to a SRAM bank being initialized is
detected, the access will be pending until the initialization sequence is completed. Those SRAMs banks that are not
selected to be initialized can be accessed as usual during the initialization process of the rest of the banks.
The initialization for a particular SRAM bank can be monitored for its completion by polling the appropriate
PMG_TST_SRAM_INITSTAT.BNK0 to PMG_TST_SRAM_INITSTAT.BNK5 bits in the
PMG_TST_SRAM_INITSTAT read only register. Every time a particular SRAM bank is initialized, its associated
PMG_TST_SRAM_INITSTAT.BNK0 to PMG_TST_SRAM_INITSTAT.BNK5 bits will be cleared and will remain low
until initialization is completed.
After power up, SRAM bank 0 (8 KB) is automatically initialized. This memory is always retained and will contain
the stack pointer and critical information. Its contents will not have to be overwritten in the future as initialization is
already been performed. User must avoid initializing those SRAM banks that are already initialized as they may already contain user information.
Initialization of more SRAM banks, where parity will be enabled, can be achieved at any time by writing to
PMG_TST_SRAM_CTL register. Here, the appropriate PMG_TST_SRAM_CTL.BNK0EN to
PMG_TST_SRAM_CTL.BNK5EN bits for SRAM banks which need parity to be enabled has to be set to 1; set to 1 the
PMG_TST_SRAM_CTL.STARTINIT bit. This bit will be auto-cleared to 0 after being written and will trigger the
initialization sequence.
After the Hibernate mode, the contents of non-retained SRAM banks will be lost. If these banks have parity enabled, initialization will be required.
There are two options to initialize the required SRAM banks after the Hibernate mode:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
14–3
SRAM Initialization
1. Initialize by writing to PMG_TST_SRAM_CTL.STARTINIT register after coming from the Hibernate mode.
Those SRAMs banks which PMG_TST_SRAM_CTL.BNK0EN to PMG_TST_SRAM_CTL.BNK5EN bits are set to
1 will be initialized.
2. Automatic initialization after the Hibernate mode. No write to PMG_TST_SRAM_CTL is required each time we
come back from hibernate mode. To select this automatic mode, the user has to previously set the
PMG_TST_SRAM_CTL.AUTOINIT bit in PMG_TST_SRAM_CTL register. Those SRAMs selected for initialization in this register will be automatically initialized after coming back from HIBERNATE mode.
Initialization will reset the contents of the selected memory banks. It is important that the user carefully selects
which memory banks will be initialized so no user information is lost.
The initialization sequence can be aborted at any time by writing to the PMG_TST_SRAM_CTL.ABTINIT bit in the
PMG_TST_SRAM_CTL register. This bit is self-cleared after it has been written.
Initialization in Cache and Instruction SRAM
When cache memory is used, parity can also be enabled on its associated SRAM bank (bank 5). In this case (when
SRAM bank 5 is used as cache memory) initialization is not required. The reason is that initialization is only required when we perform byte or halfword accesses to SRAM with parity check enabled. When SRAM bank 5 is
used as cache memory, all the accesses will be word accesses.
Because initialization is not required for the cache memory, the cache feature will be available right after coming
back from hibernate mode (there is no initialization time penalty). To prevent undesired bus errors, the controller
will ignore any initialization of SRAM bank 5 when cache is enabled.
As with the cache memory, the SRAM banks used as instruction memory dont require any previous initialization
when parity check is enabled on them. Consequently the instruction SRAM can be immediately accessed after coming back from hibernate mode.
If initialization were triggered on instruction SRAM, it will be committed. In case instruction SRAM was initialized
and an access to it was received, the access would be halted until initialization is completed.
ADuCM302x SRAM Register Description
Table 14-1:
ADuCM302x SRAM Register List
Name
Description
Reset
Access
PMG_TST_SRAM_INITSTAT
Initialization Status Register.
0x00000000
R/W
PMG_TST_SRAM_CTL
Control for SRAM parity and instruction
SRAM.
0x80000000
R/W
PMG_SRAMRET
Control for Retention SRAM during HIBERNATE mode.
0x00000000
R/W
For information on the PMG_TST_SRAM_INITSTAT, PMG_TST_SRAM_CTL, and PMG_SRAMRET registers, see the
Power Management (PMG) register descriptions.
14–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Cyclic Redundancy Check (CRC)
15 Cyclic Redundancy Check (CRC)
The CRC accelerator is used to compute the CRC for a block of memory locations. The exact memory location can
be in the SRAM, flash, or any combination of memory mapped registers. The CRC accelerator generates a checksum that can be used to compare with an expected signature. The final CRC comparison is the responsibility of the
processor.
CRC Features
The CRC used by the ADuCM302x processor supports the following features:
• Generate a CRC signature for a block of data.
• Programmable polynomial length of up to 32 bits.
• Operates on 32 bit of data at a time.
• MSB first as well as LSB first implementations of CRC.
• Various data mirroring capabilities.
• Initial seed to be programmed by user.
• DMA controller (using software DMA) can be used for data transfer to offload the processor.
CRC Functional Description
This section provides information on the function of the CRC accelerator used by the ADuCM302x processor.
Control for address decrement/increment options for computing the CRC on a block of memory is in the DMA
controller. For details about these options, refer to the DMA chapter.
ADuCM302x CRC Register List
CRC
Table 15-1:
ADuCM302x CRC Register List
Name
Description
CRC Control Register
ADuCM302x Mixed-Signal Control Processor Hardware Reference
15–1
CRC Functional Description
Table 15-1:
ADuCM302x CRC Register List (Continued)
Name
Description
CRC_CTL
CRC_IPDATA
Input Data Word Register
CRC_POLY
Programmable CRC Polynomial
CRC_RESULT
CRC Result Register
CRC Block Diagram
The CRC block diagram is shown below.
CRC Polynomial
CRC
Computation
Mirror Options
CRC Control
CRC Input Data
APB Interface
CRC Result
Figure 15-1: CRC Block Diagram
CRC Architectural Concepts
The CRC accelerator works on 32-bit data words which are fed to the block through the DMA channel dedicated to
the CRC accelerator or directly by the processor and the CRC accelerator guarantees immediate availability of the
CRC output.
CRC Operating Modes
The accelerator calculates CRC on the data stream it receives, 32 bits at a time, which is written into the block
either using the DMA engine or the processor directly.
15–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
CRC Operating Modes
The CRC works on 32-bit data-words. For data-words less than 32 bit in size, it is the responsibility of the processor
to pack the data into 32-bit data units. Data mirroring on the input data can be performed at bit, byte, and word
level (only for 32 bit data) before the CRC engine uses it by setting the CRC_CTL.BITMIRR, CRC_CTL.BYTMIRR,
and CRC_CTL.W16SWP bits, respectively, in CRC_CTL register.
When operating, the CRC algorithm runs on the incoming data stream written to the CRC_IPDATA register. For
every new word of data received, the CRC is computed and the CRC_RESULT register is updated with the calculated
CRC. The CRC Accelerator guarantees the immediate availability of CRC result up to the current data in the CRC
Result register and the same can be read.
The CRC engine uses the current CRC_RESULT for generating the next CRC_RESULT when a new data-word is
received. The CRC_RESULT register can be programmed with an initial seed. The bit-width of the seed value for an
n bit polynomial should be n. The seed should be justified in the CRC_RESULT register as demonstrated in the next
section.
Polynomial
The CRC Accelerator supports the calculation of the CRC using any length polynomial. The polynomial has to be
written to the CRC_POLY register. For MSB first implementation the highest power is omitted while programming
the CRC polynomial register and the polynomial is left justified. For LSB first implementation the polynomial is
right justified and the LSB is omitted. The CRC_RESULT register would contain the n bit MSBs as checksum for an
n bit CRC polynomial. The following examples illustrate the CRC polynomial.
16-bit Polynomial Programming for MSB First Calculation
Polynomial: CRC-16-CCITT, x16+x12+x5+1 = (1) 0001 0000 0010 0001 = 0x1021
The largest exponent (x16 term) is implied, so it is 0001 0000 0010 0001
When left justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
0001 0000
0010 0001
8b0
8b0
CRC Result Register (CRC_RESULT)
CRC
Result
8b0
8b0
Initial seed programmed in CRC Result Register (CRC_RESULT)
CRC
SEED
8b0
8b0
16-bit Polynomial Programming for LSB First Calculation
Polynomial: CRC-16-CCITT, x16+x12+x5+1 = 1000 0100 0000 1000 (1) = 0x8408
The smallest exponent (x0 term) is implied, so it is 1000 0100 0000 1000
ADuCM302x Mixed-Signal Control Processor Hardware Reference
15–3
CRC Operating Modes
When right justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
8b0
8b0
1000 0100
0000 1000
CRC
Result
CRC Result Register (CRC_RESULT)
8b0
8b0
Initial seed programmed in CRC Result Register (CRC_RESULT)
8b0
8b0
CRC
SEED
8-bit Polynomial Programming for MSB First Calculation
Polynomial: CRC-8-ATM, x8 + x2 + x + 1 = (1) 0000 0111= 0x07
The largest exponent (x8 term) is implied, so it is 0000 0111
When left justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
0000 0111
8b0
8b0
8b0
8b0
8b0
CRC Result Register (CRC_RESULT)
CRC RESULT
8b0
Initial seed programmed in CRC Result Register (CRC_RESULT)
CRC SEED
8b0
8b0
8b0
8-bit Polynomial Programming for LSB First Calculation
Polynomial: CRC-8-ATM, x8 + x2 + x + 1 = 1000 0011 (1) = 0x83
The smallest exponent (x0 term) is implied, so it is 1000 0011
When right justified in the polynomial register, this becomes
CRC Polynomial Register (CRC_POLY)
8b0
8b0
8b0
1000 0011
CRC Result Register (CRC_RESULT)
8b0
15–4
8b0
8b0
CRC RESULT
ADuCM302x Mixed-Signal Control Processor Hardware Reference
CRC Operating Modes
Initial seed programmed in CRC Result Register (CRC_RESULT)
8b0
8b0
8b0
CRC SEED
The CRC engine uses the following 32-bit CRC polynomial as default (IEEE 802.3):
g(x) = x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1
This is programmed for MSB First Calculation by default as shown below
0x04
0xC1
0x1D
0xB7
Reset and Hibernate Modes
1. The CRC configuration bits are retained except Block enable bit. The Block needs to be enabled again after
coming out of the Hibernate mode.
2. The CRC polynomial and CRC result registers are retained after coming out of the Hibernate mode.
Table 15-2:
Reset and Hibernate Modes
Register
Reset
Hibernate
CRC_CTL
0x0
Apart from BLKEN, all other bits retained
CRC_POLY
0x04C11DB7
Retained
CRC_IPDATA
0x0
Not retained (0x0)
CRC_RESULT
0x0
Retained
CRC Data Transfer
The data stream can be written to the block using DMA controller or by the processor directly.
CRC Interrupts and Exceptions
DMA channel generates an interrupt upon completion of data transfer to the CRC block.
CRC Programming Model
This block is provided to calculate CRC signature over block of data in the background while the core can perform
other tasks. The CRC block supports two modes of CRC calculation: core access and DMA access.
The programming details of these two modes are as follows:
CORE Access
1. Program the CRC_POLY register with the required polynomial justified as shown in the examples in the Polynomial section.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
15–5
CRC Programming Model
2. Program the CRC_RESULT register with initial seed. The seed should be justified and written to the CRC Result register as described in the previous section.
3. Kick in the CRC Accelerator block by writing into the CRC_CTL register.
a. Set the CRC_CTL.EN bit high.
The CRC_CTL.W16SWP, CRC_CTL.BITMIRR, and CRC_CTL.BITMIRR bits provide the application
with different mirror options. The details of these mirror options can be found in the Mirroring Options
for 32 bit input data with 32 bit polynomial table.
b. Set/Reset the CRC_CTL.LSBFIRST bit to indicate LSB/MSB first CRC calculation.
NOTE: All the three sub-steps in step 3 require only a single write to the CRC_CTL register.
The core can now start sending data to the CRC block by writing into the CRC_IPDATA register. The
CRC accelerator continues to calculate the CRC as long as data is written to the CRC_IPDATA register. It
is the responsibility of the application to count the number of words written to the CRC block. Once all
the words are written, the application can read the CRC_RESULT register.
4. Read the CRC_RESULT register. The CRC_RESULT register contains the n bit result in n MSB bits for MSB
first and in n LSB bits for LSB first CRC calculation.
5. Calculate CRC on the next data block. To calculate the CRC on the next block of data, repeat steps 1-4.
6. Disable the CRC accelerator block by clearing the CRC_CTL bit. This needs to be ensured in order to put the
block in low power state.
DMA Access
The CRC accelerator block supports software DMA.
1. Program the CRC_POLY register with the required polynomial left justified as shown in the example in the Polynomial section.
2. Program the CRC_RESULT register with initial seed value. The seed should be justified and written to the CRC
Result register as described in the Polynomial section.
3. Enable accelerator function by writing into CRC_CTL register.
a. Set the CRC_CTL.EN bit high.
The CRC_CTL.W16SWP, CRC_CTL.BITMIRR, and CRC_CTL.BITMIRR bits provide the application
with different mirror options. The details of these mirror options can be found in the Mirroring Options
for 32 bit input data with 32 bit polynomial table.
b. Set/Reset the CRC_CTL.LSBFIRST bit to indicate LSB/MSB first CRC calculation.
NOTE: All the previous three steps require only a single write to the CRC_CTL register.
The DMA will now start sending the CRC data by writing into the CRC_IPDATA. The CRC accelerator
block continues to calculate the CRC as long as the data is written to the CRC_IPDATA.
15–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
CRC Programming Model
4. Setup the DMA channels as required. DST_END_PNTR value is CRC_IPDATA register address. Data size is
word. Use the destination no increment option for the channel. Refer to the DMA documentation for details
about programming the DMA.
5. A dma_done interrupt signal of the DMA channel indicates the completion of data transfer to the CRC block.
6. Repeat steps 1 - 4 until all the data has been sent to the accelerator block.
7. Read the CRC_RESULT register. The CRC_RESULT register would contain the n bit result in n MSB bits for
MSB first and in n LSB bits for LSB first CRC calculations.
8. Calculate CRC on the next data block. To calculate the CRC on the next block of data, repeat steps 1-5.
9. Disable the CRC accelerator block by clearing the CRC_CTL.EN bit. This needs to be ensured to put the part
in low-power state.
Mirroring Options
The CRC_CTL.W16SWP, CRC_CTL.BITMIRR, and CRC_CTL.BYTMIRR bits of the CRC_CTL register determine
the sequence of the bits in which the CRC is calculated. The table below lists the details of all the mirroring options
used within this block for a 32-bit polynomial. Assume DIN[31:0] shown in the table below is the data being written to the CRC_IPDATA register and CIN[31:0] is the data after the mirroring of the data. The serial engine will
calculate CIN[31:0] starting with the MSB bit and ending with LSB bit in sequence, that is, CIN[31], CIN[30], .
CIN[1], CIN[0] in order.
Table 15-3:
Mirroring Options for 32 bit Input Data with 32 bit Polynomial
W16SWP BYTMIRR
BITMIRR Input Data
DIN[31:0]
CRC Input Data (CIN[31:0])
0
0
0
DIN[31:0]
CIN[31:0] = DIN[31:0]
0
0
1
DIN[31:0]
CIN[31:0] = DIN[24:31], DIN[16:23], DIN[8:15], DIN[0:7]
0
1
0
DIN[31:0]
CIN[31:0] = DIN[23:16], DIN[31:24], DIN[7:0], DIN[15:8]
0
1
1
DIN[31:0]
CIN[31:0] = DIN[16:23], DIN[24:31], DIN[0:7], DIN[8:15]
1
0
0
DIN[31:0]
CIN[31:0] = DIN[15:0], DIN[31:16]
1
0
1
DIN[31:0]
CIN[31:0] = DIN[8:15], DIN[0:7], DIN[24:31], DIN[16:23]
1
1
0
DIN[31:0]
CIN[31:0] = DIN[7:0], DIN[15:8], DIN[23:16], DIN[31:24]
1
1
1
DIN[31:0]
CIN[31:0] = DIN[0:7], DIN[8:15], DIN[16:23], DIN[24:31]
ADuCM302x CRC Register Descriptions
CRC Accelerator (CRC) contains the following registers.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
15–7
ADuCM302x CRC Register Descriptions
Table 15-4:
ADuCM302x CRC Register List
Name
Description
CRC_CTL
CRC Control Register
CRC_IPDATA
Input Data Word Register
CRC_POLY
Programmable CRC Polynomial
CRC_RESULT
CRC Result Register
15–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRC Register Descriptions
CRC Control Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
W16SWP (R/W)
Word16 Swap
EN (R/W)
CRC Peripheral Enable
BYTMIRR (R/W)
Byte Mirroring
LSBFIRST (R/W)
LSB First Calculation Order
BITMIRR (R/W)
Bit Mirroring
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
RevID (R)
Revision ID
Figure 15-2: CRC_CTL Register Diagram
Table 15-5:
CRC_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:28 REVID
Revision ID.
(R/NW)
4 W16SWP
(R/W)
Word16 Swap.
This bit will swap 16-bit half-words within a 32-bit word.
0 Word16 Swap disabled
1 Word16 Swap enabled
3 BYTMIRR
(R/W)
Byte Mirroring.
This bit will swap 8-bit bytes within each 16-bit half-word.
0 Byte Mirroring is disabled
1 Byte Mirroring is enabled
2 BITMIRR
(R/W)
Bit Mirroring.
This bit will swap bits within each byte.
0 Bit Mirroring is disabled
1 Bit Mirroring is enabled
1 LSBFIRST
LSB First Calculation Order.
(R/W)
0 MSB First CRC calculation is done
1 LSB First CRC calculation is done
ADuCM302x Mixed-Signal Control Processor Hardware Reference
15–9
ADuCM302x CRC Register Descriptions
Table 15-5:
CRC_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 EN
(R/W)
CRC Peripheral Enable.
0 CRC peripheral is disabled
1 CRC peripheral is enabled
15–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRC Register Descriptions
Input Data Word Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (W)
Data Input
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (W)
Data Input
Figure 15-3: CRC_IPDATA Register Diagram
Table 15-6:
CRC_IPDATA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
Data Input.
(RX/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
15–11
ADuCM302x CRC Register Descriptions
Programmable CRC Polynomial
15 14 13 12 11 10 9
0
0
0
1
1
1
0
8
7
6
5
4
3
2
1
0
1
1
0
1
1
0
1
1
1
VALUE[15:0] (R/W)
CRC Reduction Polynomial
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
1
VALUE[31:16] (R/W)
CRC Reduction Polynomial
Figure 15-4: CRC_POLY Register Diagram
Table 15-7:
CRC_POLY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
CRC Reduction Polynomial.
(R/W)
15–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x CRC Register Descriptions
CRC Result Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R/W)
CRC Residue
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[31:16] (R/W)
CRC Residue
Figure 15-5: CRC_RESULT Register Diagram
Table 15-8:
CRC_RESULT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:0 VALUE
CRC Residue.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
15–13
True Random Number Generator (TRNG)
16 True Random Number Generator (TRNG)
True Random Number Generator (TRNG) is used during operations where non-deterministic values are required.
This may include generating challenges for secure communication or keys used for an encrypted communication
channel. The generator can be run multiple times to generate a sufficient number of bits for the strength of the
intended operation. The true random number generator can be used to seed a deterministic random bit generator
such as one described by NIST CRC SP-800-90A.
TRNG Features
The following are the features of TRNG:
• Programmable length to obtain sufficient entropy.
• Includes an oscillator counter to characterize the sampling jitter.
TRNG Functional Description
This section provides information on the function of the TRNG used by the ADuCM302x processor.
ADuCM302x RNG Register List
Table 16-1:
ADuCM302x RNG Register List
Name
Description
RNG_CTL
RNG Control Register
RNG_DATA
RNG Data Register
RNG_LEN
RNG Sample Length Register
RNG_OSCCNT
Oscillator Count
RNG_OSCDIFF[n]
Oscillator Difference
RNG_STAT
RNG Status Register
TRNG Block Diagram
The figure below shows the block diagram of the TRNG used by the ADuCM302x processor.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
16–1
TRNG Functional Description
Previous
Oscillator Count
Ring
Oscillator
TEST
EN
6-bit Oscillator
Ripple Counter
Oscillator
Count
Difference
22-bit Synchronous
Counter
8-bit CRC
Accumulator
Sample
22-bit Sample
Counter
32-bit Data
Buffer
RNGDATA
Ready
Peripheral
Clock
RNG LEN
Figure 16-1: TRNG Block Diagram
The TRNG is based on a sampled asynchronous clock (in this implementation a ring oscillator). A CRC is used as a
compaction function to reduce a large amount of low entropy bits into a smaller amount of high entropy bits. The
CRC will accumulate a programmable number of samples determined by the sample length register.
The TRNG is enabled through the control register. The length register specifies the number of samples for which
the TRNG should run to accumulate sufficient entropy. One sample is obtained on each peripheral clock and compacted by the CRC. Once the TRNG has accumulated the programmed number of samples, the accumulated 8-bit
CRC result can be read. Software can poll a status bit or be interrupted when the RNG is ready.
Any number of iterations can be run. For example, 112 bits of entropy can be obtained by reading the 8-bit TRNG
result at least 14 times.
TRNG Oscillator Counter
The TRNG peripheral includes an oscillator counter. This on-chip counter can be used to characterize the sampling
jitter which is difficult to measure off-chip. The sample jitter is the source of entropy for the random number generator.
By counting the number of ring oscillator clocks over a given sampling period, the frequency ratio of the ring oscillator to peripheral sampling clock can be determined (and thus the ring oscillator frequency can be determined if the
peripheral clock frequency is known).
fOSCCLK
=
fPCLK
OSCCNT
X
SAMPCNT
The length of sampling time (SAMPCNT) used by the sample counter can be determined from the RNG_LEN register.
16–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
TRNG Functional Description
The sample jitter can be determined by calculating the standard deviation of multiple oscillator count values. Pseudo-code for an efficient loop to determine the average oscillator count and jitter is shown below:
sum=0; sum_sqr=0;
for(i=0;i<N;i++) {
gen_rng();
sum += osc_cnt;
sum_sqr += osc_cnt*osc_cnt;
}
avg=sum/N;
std=sqrt((sum_sqr-avg*sum)/(N-1));
The previous code has been simplified for clarity. If implemented in C:
• The sum and sum_sqr variables should be integer data types. Floating point variables could lose precision if the
sums accumulate for a sufficient length to overflow the fractional portion of the variable truncating the result.
It is desirable to keep the entire fractional portion, so the exponent of a floating point data type can be excluded.
• The sum variable will need log2(osc_cnt) + log2(N) bits of storage.
• The sum_sqr variable will need 2 × log2(osc_cnt) + log2(N) bits of storage.
• The squaring operation (osc_cnt × osc_cnt and avg × avg) will likely need a cast to a type with size at least 2 ×
log2(osc_cnt).
• The avg and std variables can take on fractional values and should be real or fixed point data types.
• The division will need a cast to a fractional data type.
For accurate jitter measurements, the standard deviation of RNG_OSCCNT should be at least one. If it is less than
one, then SAMPCNT should be increased.
The jitter of the oscillator counter encapsulates both jitter of the ring oscillator and jitter of the peripheral clock.
This can be used to determine sample jitter. If the jitter of the peripheral clock is known, the jitter of the oscillator
clock can be determined using the following equation.
OSCCNT
SAMPCNT
SAMPCNT
OSCCNT
ADuCM302x Mixed-Signal Control Processor Hardware Reference
1
f PCLK
SAMPLE
2
PCLK
+
2
OSCCLK
OSCCNT
SAMPCNT
16–3
TRNG Functional Description
RNG Entropy and Surprisal
The jitter of the sampling clocks is the source of entropy for the random number generator. Noise in the transistors
of the oscillator contributes to jitter. Accumulated long-term jitter increases with the square-root of time or the
number of clocks.
TOTAL
N
CLK
The number of samples that need to be accumulated to achieve ideal entropy of 1.0/bit depends on the amount of
jitter in the system. Entropy is calculated as follows:
average entropy =
p i lo g2(pi )
minimum entropy = min(-log2(pi ) )
The probability of each number occurring should be the same or uniform for all numbers for an ideal generator. A
deficient generator would output some numbers more frequently than others. This random number generator was
designed to retain no state such that entropy can be measured and quantified in this manner. For each random number generated, the CRC is reset and the ring oscillator starts up in the same phase. If there is insufficient entropy in
the system, then the generator will output the same number more frequently. This is by design and makes entropy
assessment possible. Insufficient entropy can be observed by setting SAMPCNT to a low value in which case some
random numbers will appear more frequently than others. SAMPCNT should be increased until the probability of
seeing each number is uniform.
The minimum entropy of the RNG can be computed by tallying a histogram of generated random numbers and
calculating the probability of the most frequent number occurring. The minimum entropy equation should be used
when determining how many true random numbers to seed to a deterministic random number generator.
The minimum value for SAMPCNT (set by RNG_LEN register) needed to obtain ideal minimum surprisal for the 8bit accumulator can be determined using the following equation. A conservative design will set SAMPCNT at least
as large as this, if not greater (to account for variations in jitter across various operating conditions).
SAMPCNT min
1
f
2
2
SAMPLE OSC
If an attacker can physically tamper the system and has control of the peripheral clock, the jitter due to the peripheral clock should be removed from the sample jitter in the previous calculation. This assumes an attacker can replace
the crystal with a low jitter clock source. A physical attacker may also use better voltage supplies that can minimize
the amount of noise in the system. If an attacker can remove or minimize the peripheral clock jitter, then the entropy source of the random number generator is reduced. The system should rely solely on the jitter of the ring oscillator, and conservatively, assume the jitter of the peripheral clock to be zero.
16–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
TRNG Functional Description
Oscillator Count Difference
There is logic built into the random number generator to calculate the difference between subsequent oscillator
count values. This can be used to calculate the variance and quantify the amount of jitter and thus entropy in the
system. This provides a measure of health of the random number generator entropy source.
The statistical sample variance is typically calculated as follows:
S2
n
1
n-1
(xi — x)2
i=1
The on-chip circuit calculates the difference in oscillator count between the current and previous sample. Since the
samples are independent and identically generated, this removes the mean.
E[X] — E[X] = 0
E[(X — X)2] = 2 2
The variance can be computed by averaging half of the square of the difference between oscillator count values.
The average can be replaced with a low pass IIR filter to track changes in the variance over time.
TRNG Interrupts and Exceptions
The TRNG block cannot generate any interrupts.
ADuCM302x RNG Register Descriptions
Random Number Generator (RNG) contains the following registers.
Table 16-2:
ADuCM302x RNG Register List
Name
Description
RNG_CTL
RNG Control Register
RNG_DATA
RNG Data Register
RNG_LEN
RNG Sample Length Register
RNG_OSCCNT
Oscillator Count
ADuCM302x Mixed-Signal Control Processor Hardware Reference
16–5
ADuCM302x RNG Register Descriptions
Table 16-2:
ADuCM302x RNG Register List (Continued)
Name
Description
RNG_OSCDIFF[n]
Oscillator Difference
RNG_STAT
RNG Status Register
16–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RNG Register Descriptions
RNG Control Register
The RNG_CTL register is used to enable the random number generator.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SINGLE (R/W)
Generate a single number
EN (R/W)
RNG Enable
Figure 16-2: RNG_CTL Register Diagram
Table 16-3:
RNG_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3 SINGLE
(R/W)
Generate a single number.
By default the RNG will generate and buffer four 8-bit values to provide a 32-bit random number. Setting this bit will cause the RNG to only generate a single 8-bit random number.
0 Buffer Word
1 Single Byte
0 EN
(R/W)
RNG Enable.
When RNG_CTL.EN is set and RNG_STAT.RNRDY is clear, the ring oscillator will be
powered up and the number of samples defined by RNG_LEN will be accumulated in
the RNG_DATA register.
0 Disable the RNG
1 Enable the RNG
ADuCM302x Mixed-Signal Control Processor Hardware Reference
16–7
ADuCM302x RNG Register Descriptions
RNG Data Register
RNG_DATA register provides the CPU with read-only access of the entropy accumulator (8-bit CRC) and data buf-
fer. When the data buffer is not enabled, an 8-bit result is provided. When the data buffer is enabled, 32-bits (four
8-bit values) are provided. The contents of this register are valid when the RNG_STAT.RNRDY bit is set. This register
is reset when the RNG_STAT.RNRDY bit is cleared. The RNG_STAT.RNRDY bit is automatically cleared when this
register is read and the CPU is not in debug halt. Reading this register by the CPU when RNG_CTL.EN is set will
cause a new random number to be generated.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BUFF[7:0] (RC)
Buffer for RNG data
VALUE (RC)
Value of the CRC accumulator
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BUFF[23:8] (RC)
Buffer for RNG data
Figure 16-3: RNG_DATA Register Diagram
Table 16-4:
RNG_DATA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
31:8 BUFF
(RC/NW)
7:0 VALUE
(RC/NW)
16–8
Buffer for RNG data.
When configured to generate 32-bit values, RNG_DATA.BUFF stores the previous three
numbers generated.
Value of the CRC accumulator.
This register provides data from the entropy compaction function (8-bit CRC accumulator).
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RNG Register Descriptions
RNG Sample Length Register
The RNG_LEN register defines the number of samples to accumulate in the CRC register when generating a random
number. The number of samples accumulated is RNG_LEN.RELOAD scaled by 2^RNG_LEN.PRESCALE.
15 14 13 12 11 10 9
0
0
1
1
0
1
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
PRESCALE (R/W)
Prescaler for the sample counter
RELOAD (R/W)
Reload value for the sample counter
Figure 16-4: RNG_LEN Register Diagram
Table 16-5:
RNG_LEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:12 PRESCALE
(R/W)
11:0 RELOAD
(R/W)
Prescaler for the sample counter.
The sample counter reload value RNG_LEN.RELOAD is scaled by
2^RNG_LEN.PRESCALE. The prescaler is a 10-bit counter. Valid values for the prescaler are 0 to 10. Values greater than 10 will saturate at the maximum prescaler value.
Reload value for the sample counter.
Defines the number of samples to accumulate in the CRC when generating a random
number.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
16–9
ADuCM302x RNG Register Descriptions
Oscillator Count
The oscillator counter counts the number of ring oscillator cycles which occur during the generation of a random
number. The oscillator counter is 28-bits. The oscillator counter will saturate at the maximum value to prevent overflow.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE[15:0] (R)
Oscillator count
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
VALUE[27:16] (R)
Oscillator count
Figure 16-5: RNG_OSCCNT Register Diagram
Table 16-6:
RNG_OSCCNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
27:0 VALUE
(R/NW)
16–10
Oscillator count.
This register is only valid when RNG_STAT.RNRDY is set.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RNG Register Descriptions
Oscillator Difference
The oscillator difference register stores the difference in RNG_OSCCNT from the current value compared to the previous value (RNG_OSCCNT[n] - RNG_OSCCNT[n-1]). This difference is represented as a signed 8-bit value. It saturates
at the maximum and minimum values. This can be used to reconstruct RNG_OSCCNT for the values currently in the
RNG_DATA buffer. This information can be used to compute the RNG_OSCCNT variance to check the health of the
random number generator and ensure there is adequate entropy.
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
DELTA (R)
Oscillator Count difference
Figure 16-6: RNG_OSCDIFF[n] Register Diagram
Table 16-7:
RNG_OSCDIFF[n] Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 DELTA
Oscillator Count difference.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
16–11
ADuCM302x RNG Register Descriptions
RNG Status Register
The RNG_STAT register indicates when the RNG has finished generating a random number.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
STUCK (R/W1C)
Sampled data stuck high or low
RNRDY (R/W1C)
Random number ready
Figure 16-7: RNG_STAT Register Diagram
Table 16-8:
RNG_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1 STUCK
(R/W1C)
0 RNRDY
(R/W1C)
Sampled data stuck high or low.
When a random number is generated, a circuit monitors the output of the sampled
ring oscillator. This circuit checks to ensure the ring oscillator output has been sampled both high and low and is not stuck at a constant value. This bit is sticky once set
and is write one to clear.
Random number ready.
This bit indicates when the value in RNG_DATA is ready to be read. An interrupt is
generated when this bit is set. The ring oscillator is stopped when this bit is set to conserve power. This bit is automatically cleared when the RNG_DATA register is read and
the CPU is not stopped in Debug Halt. This bit can also be written with one to clear.
0 Data register not ready
1 Data register is ready to be read
16–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Beeper Driver (BEEP)
17 Beeper Driver (BEEP)
The beeper driver module generates a differential square wave of programmable frequency. It is used to drive an
external piezoelectric sound component whose two terminals connect to the differential square wave output. A
standard APB interface connects this module to the system bus.
Beep Features
The beeper driver present in the MoC includes the following features:
• A module that can deliver frequencies from 8 kHz to ~0.25 kHz.
• It operates on a fixed independent 32 kHz (32768 Hz) clock source that is unaffected by changes in system
clocks.
• A timer that allows for a programmable tone durations from 4 ms to 1.02 seconds in 4 ms increments.
• Single-tone (pulse) and multitone (sequence) modes provide versatile playback options.
• In sequence mode, the beeper may be programmed to play any number of tone pairs from 1 to 254 (2 to 508
tones) or be programmed to play forever (until stopped by the user).
• Any tone may be programmed with an infinite duration, to play continuously until stopped by the user.
• Interrupts are available to indicate the start or end of any beep, the end of a sequence, or that the sequence is
nearing completion.
Beep Functional Description
This section provides information on the function of the beeper driver used by the ADuCM302x processor.
ADuCM302x BEEP Register List
Table 17-1:
ADuCM302x BEEP Register List
Name
Description
BEEP_CFG
Beeper configuration
ADuCM302x Mixed-Signal Control Processor Hardware Reference
17–1
Beep Functional Description
Table 17-1:
ADuCM302x BEEP Register List (Continued)
Name
Description
BEEP_STAT
Beeper status
BEEP_TONEA
Tone A Data
BEEP_TONEB
Tone B Data
Beep Block Diagram
The figure shows the block diagram of the beeper driver used by the ADuCM302x processor:
Beeper
Beeper Controller
IRQ
Sequence
Control
APE
MMR
Pulse Control
32kHz clk
Clock Divider
Tone
Generator
+
-
Figure 17-1: Beeper Driver
The clock divider divides the 32 kHz input clock down to frequencies between 8 kHz and ~0.25 kHz for driving
the off-chip piezoelectric component. The beeper controller block controls the tone generator, enabling and disabling its operation, and selecting the appropriate frequency output from the clock divider.
The beeper controller also tracks the durations and repeating sequences of tones. The beeper module can interrupt
the micro with one interrupt line. Its off-chip output lines are held low when the module is disabled (no voltage
across the piezoelectric component), and drive a differential square wave while tones are being played.
Beep Operating Modes
The basic operation of the beeper driver consists of writing tone data into one or both tone registers, followed by
enabling the beeper by setting the BEEP_CFG.EN bit in the BEEP_CFG register. The beeper can be started in either
pulse mode or sequence mode, depending only on the value of BEEP_CFG.SEQREPEAT when BEEP_CFG.EN gets
set. Once enabled, the module will begin playing one or more tones. During playback, the module outputs a differential square wave (VSS to VCC) with frequency and duration based on the BEEP_TONEA or BEEP_TONEB register
settings.
Pulse mode operation completes after playing exactly one tone. Sequence mode operation plays a configurable number of tones before completion. While operating in pulse or sequence mode, the BUSY bit is asserted in the
17–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Beep Operating Modes
BEEP_STAT register; this bit is cleared again upon completion of the output. An interrupt will be generated when
an event is requested. BEEP_STAT provides feedback on which of the six tracked events has occurred since the register was last cleared; any of these six events may be used for generating interrupts by selecting them in the BEEP_CFG
register.
The beeper has two modes of operation: pulse mode and sequence mode. The operating mode of the beeper is set
when the beeper is enabled and cannot be changed until the beeper is again disabled. The beeper may be disabled by
writing 0x0 to the BEEP_CFG.EN bit or by waiting for the beeper to disable itself after the current pulse or sequence
completes.
If the BEEP_CFG.SEQREPEAT bit has a non-zero value when the beeper is enabled, the beeper will operate in sequence mode. If the beeper is enabled with BEEP_CFG.SEQREPEAT set to 0x0, the beeper will operate in pulse
mode.
Pulse Mode
In pulse mode, the beeper plays back exactly one tone. Pulse mode operation begins by enabling the beeper with a
zero value in the BEEP_CFG.SEQREPEAT field. Once enabled, the beeper will play back a single tone as described
in the BEEP_TONEA register. Once playback of this tone has completed, the beeper will automatically disable itself,
clearing the BEEP_STAT.BUSY bit.
A currently playing tone may be prematurely terminated by writing 0x0 to the DUR field of the BEEP_TONEA and
BEEP_TONEB registers. When terminated, the appropriate end of the tone event bit is set in the status register and
will generate an interrupt if selected in the control register. Alternatively, all playback may be immediately terminated by disabling the beeper (clearing the BEEP_CFG.EN bit); disabling the beeper prevents any events from occurring
and, therefore, prevents an interrupt from being generated.
Interrupts will be generated as requested in the BEEP_CFG register. Note that the only events that may occur in this
mode (and thus be used to generate meaningful interrupts) are for the start and end of BEEP_TONEA playback.
Sequence Mode
In sequence mode, the beeper plays back a programmable number of tones. Sequence mode operation begins by
enabling the beeper with a non-zero value in the BEEP_CFG.SEQREPEAT field. Once enabled, the beeper will play
back a series of two-tone sequences as described in the BEEP_TONEA and BEEP_TONEB registers. The sequences will
be repeated as many times as is indicated in the BEEP_CFG.SEQREPEAT field; a value of 0xFF is a special case value
used to run the sequencer forever (or until terminated by user code). Once all iterations have been completed, the
beeper will automatically disable itself, clearing the BUSY bit of the BEEP_STAT register.
The number of remaining sequence iterations may be read from the BEEP_STAT.SEQREMAIN field of the
BEEP_STAT register. When running an infinite sequence, BEEP_STAT.SEQREMAIN will always return 0xFF. Writing BEEP_CFG.SEQREPEAT while the beeper is running in sequence mode will restart the iteration counter to that
value and immediately update the value of the BEEP_STAT.SEQREMAIN field.
Sequence mode may be prematurely terminated by writing 0x0 to the BEEP_CFG.SEQREPEAT field. Setting
BEEP_CFG.SEQREPEAT to 0x0 will cause the beeper to terminate playback and disable itself after the completion
of the current two-tone sequence. When terminated, the appropriate end of sequence event bit is set in the status
ADuCM302x Mixed-Signal Control Processor Hardware Reference
17–3
Beep Operating Modes
register and will generate an interrupt if selected in the control register. Alternatively, all playback may be immediately terminated by disabling the beeper (clearing the BEEP_CFG.EN bit); disabling the beeper prevents any events
from occurring and, therefore, prevents an interrupt from being generated.
Interrupts will be generated in sequence mode as requested in the BEEP_CFG register. All beeper events are valid for
interrupt generation in this mode.
Tones
The frequency and duration of tones played by the beeper depend on the values stored in the BEEP_TONEA and
BEEP_TONEB registers. Each of these registers describes a single independent tone. Pulse mode plays tones only
from register BEEP_TONEA, while sequence mode plays tones from both tone registers.
The tone registers are broken into three fields: a duration field (BEEP_TONEA.DUR, BEEP_TONEB.DUR), a frequency field (BEEP_TONEA.FREQ, BEEP_TONEB.FREQ), and a disable field (BEEP_TONEA.DIS, BEEP_TONEB.DIS).
Tone registers may be written at any time. Writing 0x0 to the duration field (BEEP_TONEA.DUR,
BEEP_TONEB.DUR), or setting/clearing the disable bit (BEEP_TONEA.DIS, BEEP_TONEB.DIS) of the
BEEP_TONEA and BEEP_TONEB registers for a currently playing tone will take effect immediately. All other modifications to the BEEP_TONEA and BEEP_TONEB registers take effect only the next time the tone is played; for most
use cases, this allows the next tone data to be written to while the current tone is being played.
The duration field is used to program how long a tone will play when selected for playback. Durations are measured
in units of 4 ms. Any value from 0 through 255 may be stored in the tone register. A duration of 0x0 will cause the
tone playback to end immediately. A value of 255 (0xFF) is a special case value used to program a tone for infinite
duration; once started, the tone will play continuously until user code terminates the tone (writes 0x0 to
BEEP_TONEA.DUR, BEEP_TONEB.DUR) or disables the beeper (clears the BEEP_CFG.EN bit in the BEEP_CFG
register).
The frequency field is used to program the relative frequency of the tone with respect to the source clock (32.768
kHz). Writing values 0, 1, 2, or 3 into the frequency field all have the same effect: the output will not oscillate during playback (also known as rest tone). Any value from 4 through 127 (0x7F) may be used to divide the source clock
down to the desired tone frequency. This provides a playback range from 8 kHz down to ~0.25 kHz.
The disable field is used to provide further control over the output pins of the beeper during playback. When playing a tone with the BEEP_TONEA.DIS, BEEP_TONEB.DIS bit set, the output pins behave as though the beeper
were disabled; both pins rest at Logic 0 with no dc potential between them and no oscillations. This feature is intended for use when long periods of silence exist in a programmed sequence. It may be used to prevent damage to
the piezo-electric component during these periods of silence.
Clocking and Power
The frequency and duration timers of the beeper driver are based on a 32.768 kHz input clock. The clock source is
configured system wide, selecting between an external crystal or an internal oscillator by writing to the appropriate
clock control module register (CLKG_OSC_CTL.LFCLKMUX). The selected clock only provides a stable reference for
the timers; the internal logic of the beeper is clocked by the peripheral clock (PCLK) of the system. For this reason,
the beeper cannot run while the system is in a low power mode that gates the peripheral clock (PCLK).
17–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Beep Operating Modes
Timer start events are synchronized with the 32 kHz clock. When enabling the beeper, its output may therefore be
delayed by as much as one 32 kHz clock period (30,520 ns). For a 4 MHz PCLK, this results in up to 122 PCLK
periods between starting the beeper and actually producing audio output. Any changes to the BEEP_TONEA and
BEEP_TONEB registers during this time will affect the pending audio. User code should ensure that the tone is playing before modifying the tone registers either by polling the status register or by setting an interrupt to assert on the
start-of-tone events.
User code should disable the beeper prior to entering a low power state where the peripheral clock would be gated.
Damage to the piezo-electric component may occur if the system enters a low power mode while the beeper is playing a tone due to constant, long-term dc potential across the terminals of the piezo-electric component.
Power-down Considerations
There is the possibility of irreversible damage to the external piezo beeper device if the beeper is enabled and driving
the Tone_P and Tone_N outputs under the following conditions:
1. Entering HIBERNATE power mode.
2. Entering SYS_SLEEP power mode.
3. Turning off PCLK.
The pins will not disengage automatically from the beeper module in these modes.
Beep Interrupts and Events
There are six tracked events that may occur while the beeper is running: Tone A may start or end, Tone B may start
or end, and the sequencer may end or be one step away from ending. These six events are always monitored, and
when they occur, a sticky bit is set in the BEEP_STAT register to be read by the user at some future time. These bits
remain set until cleared by user code.
Any of these six events may also be used to generate an interrupt. Selecting which events will generate interrupts is
done by setting the respective bits in the BEEP_CFG register. When an event triggers an interrupt, user code must
clear the event bit or disable the interrupt selection bit when servicing the interrupt.
When servicing a beeper interrupt, user code should check and eventually clear all event bits in the BEEP_STAT
register; multiple events may have triggered the interrupt (if enabled). Writing 0xFF to BEEP_STAT will clear all
events.
All tracked events are independently selectable for interrupt generation.
Beep Programming Model
The following sections provide general programming guidelines and procedures.
Timing Diagram
The figure shows the behavior of the beeper when programmed to generate a tone.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
17–5
Beep Programming Model
PCLK
32 k Hz_CLK
TONE_A
BEEP_CON
A
CON
Tdel
TONE_P
TONE_N
Tfreq
Figure 17-2: Timing Diagram
In this example, the tone is first written to the BEEP_TONEA register, followed by enabling the beeper by writing to
the BEEP_CFG register. Tdel illustrates the maximum one 32 kHz clock period delay between enabling the beeper
and the actual start of playback. Tfreq illustrates the output period of the two differential pins; for a 1 kHz (1024
Hz) tone, Tfreq = 0.9766 ms.
Programming Guidelines
Programming Examples
Example 1
The beeper driver is programmed for a single 1 kHz beep of 1 second length with an interrupt when the tone is
done playing.
1. Set Tone A duration to 1 ms. BEEP_TONEA: BEEP_TONEA.DUR = 0xFA; // (250 × 4 ms).
2. Set Tone A frequency to 1 kHz. BEEP_TONEA: BEEP_TONEA.FREQ = 0x20; // (32 kHz/32).
3. Interrupt at end of Tone A. BEEP_CFG: BEEP_CFG.AENDIRQ = 0x1.
4. Set the sequence repeat to zero. BEEP_CFG: BEEP_CFG.SEQREPEAT = 0x0.
5. Enable the beeper. BEEP_CFG: BEEP_CFG.EN = 0x1.
The register access sequence is BEEP_TONEA = 0x20FA and BEEP_CFG = 0x0900.
Example 2
The beeper driver is programmed for a melody of 32 two-tone sequences of the note G# for 500 ms and F# for
1000 ms with an interrupt at the end of the melody.
1. Set Tone A duration to 500 ms. BEEP_TONEA: BEEP_TONEA.DUR = 0x7D;// (125 × 4 ms).
2. Set Tone A frequency to G#. BEEP_TONEA: BEEP_TONEA.FREQ = 0x27;// (32 kHz/39 = 840 Hz).
17–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x BEEP Register Descriptions
3. Set Tone B duration to 1000 ms. BEEP_TONEB: BEEP_TONEB.DUR = 0xFA;// (250 × 4 ms).
4. Set Tone B frequency to F#. BEEP_TONEB: BEEP_TONEB.FREQ = 0x2C;//(32 kHz/44 = 745 Hz).
5. Set interrupt at end of sequence. BEEP_CFG: BEEP_CFG.SEQATENDIRQ = 0x1.
6. Set sequence repeat to 32. BEEP_CFG: BEEP_CFG.SEQREPEAT = 0x20.
7. Enable the beeper. BEEP_CFG: BEEP_CFG.EN = 0x1.
The register access sequence is: BEEP_TONEA = 0x277D, BEEP_TONEB = 0x2CFA, and BEEP_CFG = 0x8120.
ADuCM302x BEEP Register Descriptions
Beeper Driver (BEEP) contains the following registers.
Table 17-2:
ADuCM302x BEEP Register List
Name
Description
BEEP_CFG
Beeper configuration
BEEP_STAT
Beeper status
BEEP_TONEA
Tone A Data
BEEP_TONEB
Tone B Data
ADuCM302x Mixed-Signal Control Processor Hardware Reference
17–7
ADuCM302x BEEP Register Descriptions
Beeper configuration
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SEQATENDIRQ (R/W)
Sequence end IRQ
SEQREPEAT (R/W)
Beeper Sequence Repeat value
SEQNEARENDIRQ (R/W)
Sequence 1 cycle from end IRQ
EN (R/W)
Beeper Enable
BENDIRQ (R/W)
Tone B end IRQ
ASTARTIRQ (R/W)
Tone A start IRQ
BSTARTIRQ (R/W)
Tone B start IRQ
AENDIRQ (R/W)
Tone A end IRQ
Figure 17-3: BEEP_CFG Register Diagram
Table 17-3:
BEEP_CFG Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 SEQATENDIRQ
(R/W)
Sequence end IRQ.
Set this bit to request an interrupt on the event the sequencer has stopped playing
0 IRQ not generated at end of Sequence
1 IRQ generated at end of Sequence
14 SEQNEARENDIRQ
(R/W)
Sequence 1 cycle from end IRQ.
Set this bit to request an interrupt on the event the sequencer is currently running and
has just one repetition remaining before completion
0 IRQ not generated 1 tone pair before Sequence ends
1 IRQ generated 1 tone pair before sequence ends
13 BENDIRQ
(R/W)
Tone B end IRQ.
Set this bit to request an interrupt on the event BEEP_TONEB stops playing
0 IRQ not generated at end of Tone B
1 IRQ generated at end of Tone B
12 BSTARTIRQ
(R/W)
Tone B start IRQ.
Set this bit to request an interrupt on the event BEEP_TONEB starts playing
0 IRQ not generated at start of Tone B
1 IRQ generated at start of Tone B
17–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x BEEP Register Descriptions
Table 17-3:
BEEP_CFG Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 AENDIRQ
(R/W)
Tone A end IRQ.
Set this bit to request an interrupt on the event BEEP_TONEA stops playing
0 IRQ not generated at end of Tone A
1 IRQ generated at end of Tone A
10 ASTARTIRQ
(R/W)
Tone A start IRQ.
Set this bit to request an interrupt on the event BEEP_TONEA starts playing
0 IRQ not generated at start of Tone A
1 IRQ generated at start of Tone A
8 EN
(R/W)
Beeper Enable.
Write 0x1 to this bit to start playing BEEP_TONEA; Plays a single tone if
BEEP_CFG.SEQREPEAT = 0, else plays a series of two-tone sequences. Write 0x0 to
this bit at any time to end audio playback. Reading this bit always returns 0x0, read
BEEP_STAT.BUSY to determine if the beeper is currently enabled.
0 Disable module
1 Enable module
7:0 SEQREPEAT
(R/W)
Beeper Sequence Repeat value.
When the beeper transitions to an enabled state, the value of this field selects whether
the beeper runs in PULSE mode or SEQ mode. If 0x0, the beeper runs in PULSE
mode and plays back only one tone (BEEP_TONEA) before being disabled. If a nonzero value is written to this field, the beeper runs in SEQ mode and plays the two-tone
sequence (BEEP_TONEA, BEEP_TONEB) the requested number of times before being
disabled. Updates to this field have no affect while running in PULSE mode. Updates
to this field take immediate affect when running in SEQ mode.
0 Enabling will start in PULSE mode
1-254 Enabling will start in SEQ mode and play a finite number of notes
255 Enabling will start in SEQ mode and play forever until
stopped by user code
ADuCM302x Mixed-Signal Control Processor Hardware Reference
17–9
ADuCM302x BEEP Register Descriptions
Beeper status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SEQENDED (R/W1C)
Sequencer has ended
SEQREMAIN (R)
Remaining tone-pair sequence iterations
to play in SEQ mode
SEQNEAREND (R/W1C)
Sequencer last tone-pair has started
BUSY (R)
Beeper is busy
BENDED (R/W1C)
Tone B has ended
ASTARTED (R/W1C)
Tone A has started
BSTARTED (R/W1C)
Tone B has started
AENDED (R/W1C)
Tone A has ended
Figure 17-4: BEEP_STAT Register Diagram
Table 17-4:
BEEP_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 SEQENDED
(R/W1C)
14 SEQNEAREND
(R/W1C)
13 BENDED
(R/W1C)
12 BSTARTED
(R/W1C)
11 AENDED
(R/W1C)
10 ASTARTED
(R/W1C)
17–10
Sequencer has ended.
This bit is asserted whenever the beeper stops running in SEQ mode. It is cleared only
by user code writing 0x1 to this location.
Sequencer last tone-pair has started.
This bit is asserted whenever the beeper is running in SEQ mode and has only one
iteration of sequences left to play. It is cleared only by user code writing 0x1 to this
location.
Tone B has ended.
This bit is asserted whenever the beeper stops playing BEEP_TONEB. It is cleared only
by user code writing 0x1 to this location.
Tone B has started.
This bit is asserted whenever the beeper begins playing BEEP_TONEB. It is cleared only
by user code writing 0x1 to this location.
Tone A has ended.
This bit is asserted whenever the beeper stops playing BEEP_TONEA. It is cleared only
by user code writing 0x1 to this location.
Tone A has started.
This bit is asserted whenever the beeper begins playing BEEP_TONEA. It is cleared only
by user code writing 0x1 to this location.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x BEEP Register Descriptions
Table 17-4:
BEEP_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
8 BUSY
(R/NW)
Beeper is busy.
This bit is asserted after enabling the Beeper module by writing 0x1 to BEEP_CFG.EN.
The bit is cleared when the module completes its operation or when user code writes
0x0 to BEEP_CFG.EN.
0 Beeper is currently disabled
1 Beeper is currently enabled
7:0 SEQREMAIN
(R/NW)
Remaining tone-pair sequence iterations to play in SEQ mode.
After a sequence has ended, this field resets to BEEP_CFG.SEQREPEAT. This field is
updated as the beeper plays back audio in SEQ mode. Each two-tone iteration starts
by playing BEEP_TONEA and ends by playing BEEP_TONEB. This field is updated at
the conclusion of BEEP_TONEB playback and therefore during the last iteration will
return 0x1 during BEEP_TONEA and BEEP_TONEB playback. When playing an infinite sequence this field always returns 0xFF.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
17–11
ADuCM302x BEEP Register Descriptions
Tone A Data
Tone A is the first tone to play in Sequence Mode, and the only tone to play in Pulse Mode. Writing 0x0 to the
BEEP_TONEA.DUR field while Tone A is playing will immediately terminate the tone. All other writes to
BEEP_TONEA affect the next play back of the tone only and do not affect the currently playing tone.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
DIS (R/W)
Output disable
DUR (R/W)
Tone duration
FREQ (R/W)
Tone frequency
Figure 17-5: BEEP_TONEA Register Diagram
Table 17-5:
BEEP_TONEA Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 DIS
(R/W)
Output disable.
This bit is set to disable the beeper output while BEEP_TONEA is playing. The beeper
holds both of its two output pins at logic 0 when disabled. Writes to this bit take effect
immediately if BEEP_TONEA is currently playing.
0 Output enabled
1 Output disabled, no DC potential across output pins
14:8 FREQ
(R/W)
Tone frequency.
This field defines the frequency for BEEP_TONEA as integer divisions of the
32.768kHz clock. The values 0 through 3 are interpreted as 'rest-tone' and will result
in no oscillations of the beeper output pins. All other values are directly used to divide
the 32kHz input clock. Writes to this field immediately affect the output of
BEEP_TONEA if currently playing.
0-3 Rest tone (duration but no oscillation)
4-127 Oscillation at 32kHz/(FREQ)
7:0 DUR
(R/W)
Tone duration.
This field defines the duration for BEEP_TONEA in 4ms increments. Writing a value of
0x0 will immediately terminate BEEP_TONEA if currently playing. Writing a value of
0xFF will cause BEEP_TONEA to play forever once started, or until user code terminates the tone. Only a write of 0x0 will affect a currently playing tone, all other values
written will be used only the next time BEEP_TONEA is played.
0-254 Tone will play for (DUR)*4ms period
255 Tone will play for infinite duration
17–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x BEEP Register Descriptions
Tone B Data
Tone B is the second tone to play in Sequence Mode, and is not played Pulse Mode. Writing 0x0 to the
BEEP_TONEB.DUR field while Tone B is playing will immediately terminate the tone. All other writes to
BEEP_TONEB affect the next play back of the tone only and do not affect the currently playing tone.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
DIS (R/W)
Output disable
DUR (R/W)
Tone duration
FREQ (R/W)
Tone frequency
Figure 17-6: BEEP_TONEB Register Diagram
Table 17-6:
BEEP_TONEB Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 DIS
(R/W)
Output disable.
This bit is set to disable the beeper output while BEEP_TONEB is playing. The beeper
holds both of its two output pins at logic 0 when disabled. Writes to this bit take effect
immediately if BEEP_TONEB is currently playing.
0 Output enabled
1 Output disabled, no DC potential across output pins
14:8 FREQ
(R/W)
Tone frequency.
This field defines the frequency for BEEP_TONEB as integer divisions of the
32.768kHz clock. The values 0 through 3 are interpreted as 'rest-tone' and will result
in no oscillations of the beeper output pins. All other values are directly used to divide
the 32kHz input clock. Writes to this field immediately affect the output of
BEEP_TONEB if currently playing.
0-3 Rest tone (duration but no oscillation)
4-127 Oscillation at 32kHz/(FREQ)
7:0 DUR
(R/W)
Tone duration.
This field defines the duration for BEEP_TONEB in 4ms increments. Writing a value of
0x0 will immediately terminate BEEP_TONEB if currently playing. Writing a value of
0xFF will cause BEEP_TONEB to play forever once started, or until user code terminates the tone. Only a write of 0x0 will affect a currently playing tone, all other values
written will be used only the next time BEEP_TONEB is played.
0-254 Tone will play for (DUR)*4ms period
255 Tone will play for infinite duration
ADuCM302x Mixed-Signal Control Processor Hardware Reference
17–13
Timer (TMR)
18 Timer (TMR)
The ADuCM302x processor has three general-purpose timers; each with a 16-bit count-up/count-down counter
and a clock prescaler of up to 8 bit, specifically with prescale options of 1, 4, 16, 64 or 256. Up to four clocks can be
selected for the timer in a separate clocking block.
The timers have a maximum timeout range of (2 Counter_width/Clock Frequency) =
2 (16+8) /26 MHz = 0.6 s, 2 (16+8) /32 kHz = 512 s.
Some sample use cases of these timers are as follows:
• As a 1 us clock
• As a SysTick timer to provide a reference time base of 50 us to 60 us for firmware
• As a data rate counter
The data rate can range from 100 b/s to 400 Kb/s, depending on the wireless protocol.
• PWM generation
• PWM demodulation
TMR Features
The general-purpose timers used by the ADuCM302x processor supports the following features:
The timers have two modes of operation, free running or periodic.
In free running mode, the counter decrements/increments from the maximum/minimum value until zero/full scale
and starts again at the maximum/minimum value. In periodic mode, the counter decrements/increments from the
value in the load register (TMR_LOAD) until zero/full scale and starts again at the value stored in the load register.
The value of a counter can be read at any time by accessing its value register (TMR_ACURCNT.VALUE).This assuming a synchronized clock and avoids synchronization delay by returning the asynchronous (not synchronized) timer
value directly . The alternative is to read TMR_CURCNT.VALUE which returns a slightly delayed timer value. Reading
TMR_ACURCNT.VALUE when the timer and core operate on different clocks is unsupported, and the return value is
undefined in this case.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–1
TMR Functional Description
Writing the timer control register (TMR_CTL) initiates the up/down counter. An IRQ is generated each time the
value of the counter reaches zero when counting down, or each time the counter value reaches full scale when counting up. An IRQ can be cleared by writing a 1 to the corresponding bit in the clear register (TMR_CLRINT). IRQ is
also set when a selected event occurs on the event bus.
The PWM generation function may be configured to idle in either Logic 0 or Logic 1 by writing the corresponding
bit in TMR_CTL. An optional match value may be written to TMR_PWMMATCH.VALUE and enabled by writing another bit in TMR_CTL. The PWM output is generated in one of two modes: toggle or match. In toggle mode, the
PWM output toggles on timer zero/full scale which provides a 50% duty cycle with a configurable period. Match
mode provides a configurable duty cycle and a configurable period PWM output. In match mode, the PWM output
starts in the idle state as configured in the TMR_CTL register, is then asserted when the timer and match values are
equal, and is deasserted to the idle state again when the timer reaches zero/full scale.
Selectable IRQ source assertions can be used to reset the timers if the TMR_CTL.RSTEN bit is set. It can select one
from the 16 different events as trigger source as input to the block. This interrupt source can also be used as part of a
capture feature. This capture feature is also triggered by a selected IRQ source assertion. When triggered, the current
timer value is copied to TMR_CAPTURE.VALUE, and the timer continues to run. This feature can be used to determine the assertion of an event with increased accuracy.
Using the reset and capture features allows PWM demodulation to be performed on all three timers. Refer to PWM
Demodulation, for more information.
TMR Functional Description
This section provides information on the function of the general-purpose timers used by the ADuCM302x processor.
ADuCM302x TMR Register List
Table 18-1:
ADuCM302x TMR Register List
Name
Description
TMR_ALOAD
16-bit load value, asynchronous
TMR_ACURCNT
16-bit timer value, asynchronous
TMR_CAPTURE
Capture
TMR_CLRINT
Clear Interrupt
TMR_CTL
Control
TMR_LOAD
16-bit load value
TMR_PWMCTL
PWM Control Register
TMR_PWMMATCH
PWM Match Value
TMR_STAT
Status
18–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
TMR Functional Description
Table 18-1:
ADuCM302x TMR Register List (Continued)
Name
Description
TMR_CURCNT
16-bit timer value
TMR Block Diagram
The figure below illustrates the block diagram of the general-purpose timers used by the ADuCM302x processor.
TIMER
16 BIT LOAD
Clock
Sources
8 BIT PRESCALE
(1, 4, 16, 64, 256)
16 BIT UP/DOWN COUNTER
IRQ
GEN
Reset
TIMER VALUE
IRQ
CAPTURE
16 IRQ Events
Capture
MATCH VALUE
PWM LOGIC
PWM
Output
Figure 18-1: Timer 1 Block Diagram
TMR Operating Modes
The general-purpose timers used by the ADuCM302x processor supports the following modes of operation:
Free Running Mode
In free running mode, the timer is started by writing to the TMR_CTL.EN bit of the TMR_CTL register. The timer
increments from zero /full scale to full scale/zero if counting up/down. Full scale is 216 − 1 or 0xFFFF in hexadecimal format. On reaching full scale (or zero), a time out interrupt occurs, and TMR_STAT.TIMEOUT bit is set. To
clear TMR_STAT.TIMEOUT, user code must write TMR_CLRINT.TIMEOUT. The timer is reloaded with the maximum/minimum value when the time out interrupt occurs. If TMR_CTL.RLD is set, the timer will also reload when
the TMR_CLRINT.TIMEOUT bit is written 1.
Periodic Mode
In periodic mode, the initial TMR_LOAD.VALUE value should be loaded before enabling the timer. The timer is
started by writing TMR_CTL.EN bit. The counter value increments from the value stored in the TMR_LOAD.VALUE
register to full scale or decrements from the value stored in the TMR_LOAD.VALUE register to zero, depending on
the TMR_CTL.UP settings (count up/down). When the counter reaches full scale or zero, the timer generates an interrupt. The TMR_LOAD.VALUE is reloaded into the counter, and it continues counting up/down. The timer should
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–3
TMR Operating Modes
be disabled prior to changing the or TMR_LOAD.VALUE register. By default, the counter is reloaded automatically
when generating the IRQ. If TMR_CTL.RLD bit is set to one, the counter is also reloaded when user code writes
TMR_CLRINT.TIMEOUT bit. To enable timing critical modifications to the load value, a nonsynchronized write address is provided at TMR_ALOAD. Writing TMR_ALOAD bypasses synchronization logic, providing finer grained control over the load value. If the TMR_ALOAD register is changed while the timer is enabled and running on a different
clock than the core, undefined results may occur.
TMR_STAT should be read prior to writing to any timer registers following the set or clear of enable. Once
TMR_STAT.PDOKbit returns zero, registers can be modified. This assures the timer is done synchronizing timer con-
trol between the core and timer clock domains. The typical synchronization time is two timer clock periods. Any
modification to TMR_CTL.UP or TMR_CTL.MODE bits should be performed while the timer is disabled.
At any time, TMR_CURCNT.VALUE will contain a valid value to be read, synchronized to the core clock. The register
enables the counter, selects the mode, selects the prescale value, and controls the event capture function.
Toggle Mode
In toggle mode, the PWM provides a 50% duty-cycle output with configurable period. The PWM output is inverted when a timeout interrupt is generated by the timer. The period is therefore defined by the selected clock and
prescaler. If the timer is run in periodic mode (rather than free running), the PWM output also depends on the
TMR_LOAD.VALUE value. Timeout events are evaluated at the end of a timer period (potentially much longer than a
core clock period).
Match Mode
Match mode provides a configurable duty cycle and configurable period PWM output. Like toggle mode, the period
is defined by the selected clock and the prescaler, as well as TMR_LOAD.VALUE (when the timer is run in periodic
mode). The duty cycle is defined by the TMR_PWMMATCH.VALUE value. When the timers counter value is equal to
the value stored in TMR_PWMMATCH.VALUE, the PWM output is asserted. It remains asserted until the timer reaches
zero/full scale and is then deasserted. Match and timeout events are evaluated at the end of a timer period (potentially much longer than a core clock period). Match events take priority over timeout events when triggered on the
same cycle, therefore a 100% duty cycle PWM may be configured by setting TMR_PWMMATCH.VALUE equal to
TMR_LOAD.VALUE when running in periodic mode, or zero/full scale when set to free running mode. A 0% duty
cycle is only possible when running in periodic mode and may be configured by setting TMR_PWMMATCH.VALUE
outside of the range of the timers counter (TMR_LOAD.VALUE + 1 when counting down, TMR_LOAD.VALUE − 1
when counting up).
NOTE: The PWM may be configured to operate in either toggle mode or match mode. In either mode, using the
PWM output requires selecting the appropriate mux settings in the GPIO control module.
For a given clock source, prescaler, and TMR_LOAD.VALUE value, the PWM period in toggle mode is twice that of
the period in match mode, due to toggle mode inverting just once each timer counter period, while match mode
both asserts and de-asserts the PWM output. Writes to the TMR_CTL and TMR_PWMMATCH.VALUE registers while
the timer is running are supported. Note however that the PWM output will not reflect changes to TMR_CTL until
the next match or timeout event. This enables modifying the PWM behavior while maintaining a deterministic
18–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
PWM Demodulation
PWM duty cycle. It is possible to force the PWM output to match newly written settings by writing to
TMR_CLRINT or by disabling/enabling the timer.
PWM Demodulation
PWM demodulation can be implemented by enabling both the timer reset and capture features with the events logic
which allows separate count values to be read for the high and low levels of the PWM input. In practice the processor selects the appropriate PWM (GPIO) interrupt source and triggers an interrupt on the rising edge of the PWM
pulse. This resets the counters and interrupts the processor when a capture is detected. The processor modifies the
interrupt to trigger on the falling edge of the PWM pulse (before the edge occurs). This interrupt captures the high
level count in TMR_CAPTURE.VALUE and resets the counter and interrupts the processor again with the updated
capture. The processor reads this captured count and modified the interrupt to operate off the positive edge again
(before the edge occurs). This interrupt captures the low level count in TMR_CAPTURE.VALUE and resets the counter and interrupts the processor again. The processor can read this captured count. Comparing both read values indicates the PWM values. The PWM pulse widths must be wide enough to allow for the overhead of synchronization
delays, IRQ delays, and software setup that is required between the various input edges.
GPIO
GPIO_IRQ
EVENT_BUS
RESET/
EVENT_REDGE
GPT_IRQ
PRESCALE/
VALUE
CAPTURE
0 1
Don’t Care
0x350
0x300
0 1
0x348
0 1
High Count
(0x350)
Low Count
(0x300)
0 1
High Count
(0x348)
Figure 18-2: PWM Demodulation Waveforms
Clock Select
There are four clocks available for each of the four timers. The selected clock is used, along with a prescaler, to control the frequency of the timers counter logic. The available clocks are selected using TMR_CTL.CLK bits. Only synchronous clocks are used. When 32 kHz clock is selected, it is synchronized to the system clock first. Clock configuration settings are part of the clock control module. For more information, refer to System Clocks chapter.
Table 18-2:
Clock Source
Clock Select
GPT0 Clock Source
GPT1 Clock Source
GPT2 Clock Source
00
PCLK
PCLK
PCLK
01
HFOSC
HFOSC
HFOSC
10
LFOSC
LFOSC
LFOSC
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–5
Capture Event Function
Table 18-2:
Clock Source (Continued)
Clock Select
GPT0 Clock Source
GPT1 Clock Source
GPT2 Clock Source
11
LFXTAL
LFXTAL
LFXTAL
Capture Event Function
There are 16 interrupt events that can be captured by the general-purpose timers. Any one of the 16 events associated with a general-purpose timer can cause a capture of the 16-bit TMR_CURCNT register into the 16-bit GPTCAP
register. TMR_CTL.EVTRANGE has a 4-bit field selecting which of the 16 events to capture.
When the selected IRQ occurs, the TMR_CURCNT register is copied into the TMR_CAPTURE.VALUE register.
TMR_STAT.CAPTURE bit is set. The IRQ is cleared by writing 1 to TMR_CLRINT.EVTCAPT bit. The
TMR_CAPTURE.VALUE register will also hold its value and cannot be overwritten until TMR_CLRINT.EVTCAPT bit
is written with a 1.
Table 18-3:
Capture and Reset Event Function
Event Select Bits
(TMR_CTL.EVTRANGE)
GPT0 Capture Source
GPT1 Capture Source
GPT2 Capture Source
0
Wake-up timer/RTC
UART0
Ext Int 0
1
Ext Int 0
SPI0
Ext Int 1
2
Ext Int 1
SPI1
Ext Int 2
3
Ext Int 2
SPIH
Ext Int 3
4
Ext Int 3
I2C0 slave
DMA error
5
WDT
I2C0 Master
RTC
6
VREG Over
Crypto
Timer0
7
Batt. Voltage Range
RESERVED
Timer1
8
P0_8_DIN
Xtal Osc
RESERVED
9
GPIO-IntA
PLL
RESERVED
10
GPIO-IntB
RNG
RESERVED
11
Timer1
Beeper
RESERVED
12
Timer2
Ext Int 0
RESERVED
13
Flash controller
Ext Int 1
RESERVED
14
SPORT0A
Timer0
RESERVED
15
SPORT0B
Timer2
RESERVED
TMR Interrupts and Exceptions
Refer to Events (Interrupts and Exceptions), for more information.
18–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x TMR Register Descriptions
ADuCM302x TMR Register Descriptions
General Purpose Timer (TMR) contains the following registers.
Table 18-4:
ADuCM302x TMR Register List
Name
Description
TMR_ALOAD
16-bit load value, asynchronous
TMR_ACURCNT
16-bit timer value, asynchronous
TMR_CAPTURE
Capture
TMR_CLRINT
Clear Interrupt
TMR_CTL
Control
TMR_LOAD
16-bit load value
TMR_PWMCTL
PWM Control Register
TMR_PWMMATCH
PWM Match Value
TMR_STAT
Status
TMR_CURCNT
16-bit timer value
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–7
ADuCM302x TMR Register Descriptions
16-bit load value, asynchronous
Only use when a synchronous clock source is selected (TMR_CTL.CLK=00)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Load value, asynchronous
Figure 18-3: TMR_ALOAD Register Diagram
Table 18-5:
TMR_ALOAD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
18–8
Load value, asynchronous.
The Up/Down counter is periodically loaded with this value if periodic mode is selected (TMR_CTL.MODE=1). Writing TMR_ALOAD.VALUE takes advantage of having the
timer run on PCLK by bypassing clock synchronization logic otherwise required.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x TMR Register Descriptions
16-bit timer value, asynchronous
Only use when a synchronous clock source is selected (TMR_CTL.CLK=00)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Counter value
Figure 18-4: TMR_ACURCNT Register Diagram
Table 18-6:
TMR_ACURCNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/NW)
Counter value.
Reflects the current Up/Down counter value. Reading TMR_ACURCNT takes advantage
of having the timer run on PCLK by bypassing clock synchronization logic otherwise
required.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–9
ADuCM302x TMR Register Descriptions
Capture
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
16-bit captured value
Figure 18-5: TMR_CAPTURE Register Diagram
Table 18-7:
TMR_CAPTURE Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/NW)
18–10
16-bit captured value.
TMR_CAPTURE will hold its value until TMR_CLRINT.EVTCAPT is set by user code.
TMR_CAPTURE will not be over written even if another event occurs without writing
to the TMR_CLRINT.EVTCAPT.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x TMR Register Descriptions
Clear Interrupt
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EVTCAPT (W1C)
Clear captured event interrupt
TIMEOUT (W1C)
Clear timeout interrupt
Figure 18-6: TMR_CLRINT Register Diagram
Table 18-8:
TMR_CLRINT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1 EVTCAPT
(RX/W1C)
Clear captured event interrupt.
This bit is used to clear a capture event interrupt
0 No effect
1 Clear the capture event interrupt
0 TIMEOUT
(RX/W1C)
Clear timeout interrupt.
This bit is used to clear a timeout interrupt.
0 No effect
1 Clears the timeout interrupt
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–11
ADuCM302x TMR Register Descriptions
Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
1
0
1
0
SYNCBYP (R/W)
Synchronization bypass
PRE (R/W)
Prescaler
RSTEN (R/W)
Counter and prescale reset enable
UP (R/W)
Count up
EVTEN (R/W)
Event select
MODE (R/W)
Timer mode
EVTRANGE (R/W)
Event select range
EN (R/W)
Timer enable
RLD (R/W)
Reload control
CLK (R/W)
Clock select
Figure 18-7: TMR_CTL Register Diagram
Table 18-9:
TMR_CTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 SYNCBYP
(R/W)
14 RSTEN
(R/W)
13 EVTEN
(R/W)
Synchronization bypass.
Used to bypass the synchronization logic within the block. Use only with synchronous
clocks. This bit field also changes TMR_CTL.PRE max prescaler count from 3 to 0.
Counter and prescale reset enable.
Used to enable and disable the reset feature. Used in conjunction with
TMR_CTL.EVTEN and TMR_CTL.EVTRANGE: when a selected event occurs the 16 bit
counter and 8 bit prescale are reset. This is required in PWM demodulation mode.
Event select.
Used to enable and disable the capture of events. Used in conjunction with the
TMR_CTL.EVTRANGE: when a selected event occurs the current value of the Up/Down
counter is captured in TMR_CAPTURE.
0 Events will not be captured
1 Events will be captured
12:8 EVTRANGE
(R/W)
18–12
Event select range.
Timer event select range (0 - 31).
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x TMR Register Descriptions
Table 18-9:
TMR_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
7 RLD
(R/W)
Reload control.
TMR_CTL.RLD is only used for periodic mode; this bit allows the user to select wheth-
er the Up/Down counter should be reset only on a timeout event or also when
TMR_CLRINT.TIMEOUT is set
0 Up/Down counter is only reset on a timeout event
1 Resets the up/down counter when the Clear Timeout
Interrupt bit is set
6:5 CLK
(R/W)
Clock select.
Used to select a timer clock from the four available clock sources. Refer to the Clock
Source table for further details on the available clock sources
0 Select CLK Source 0(default)
1 Select CLK Source 1
2 Select CLK Source 2
3 Select CLK Source 3
4 EN
(R/W)
Timer enable.
Used to enable and disable the timer. Clearing this bit resets the timer, including the
TMR_CURCNT register.
0 Timer is disabled (default)
1 Timer is enabled
3 MODE
(R/W)
Timer mode.
This bit is used to control whether the timer runs in periodic or free running mode. In
periodic mode the up/down counter starts at the defined TMR_LOAD.VALUE; in free
running mode the up/down counter starts at 0x0000 or 0xFFFF depending on whether the timer is counting up or down.
0 Timer runs in free running mode
1 Timer runs in periodic mode (default)
2 UP
(R/W)
Count up.
Used to control whether the timer increments (counts up) or decrements (counts
down) the Up/Down counter.
0 Timer is set to count down (default)
1 Timer is set to count up
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–13
ADuCM302x TMR Register Descriptions
Table 18-9:
TMR_CTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1:0 PRE
(R/W)
Prescaler.
Controls the prescaler division factor applied to the timer's selected clock.
0 source_clock / 1 or source_clock/4 When
TMR_CTL.SYNCBYP is Set Source_Clock/1 and when
cleared Source_Clock/4
1 source_clock / 16
2 source_clock / 64
3 source_clock / 256
18–14
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x TMR Register Descriptions
16-bit load value
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Load value
Figure 18-8: TMR_LOAD Register Diagram
Table 18-10:
TMR_LOAD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Load value.
The Up/Down counter is periodically loaded with this value if periodic mode is selected (TMR_CTL.MODE=1). TMR_LOAD.VALUE writes during Up/Down counter timeout
events are delayed until the event has passed.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–15
ADuCM302x TMR Register Descriptions
PWM Control Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
IDLESTATE (R/W)
PWM Idle State
MATCH (R/W)
PWM Match enabled
Figure 18-9: TMR_PWMCTL Register Diagram
Table 18-11:
TMR_PWMCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1 IDLESTATE
(R/W)
0 MATCH
(R/W)
18–16
PWM Idle State.
This bit is used to set the PWM Idle state 0: PWM idles low 1: PWM idles high
PWM Match enabled.
This bit is used to control PWM operational mode 0: PWM in toggle mode 1: PWM
in match mode
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x TMR Register Descriptions
PWM Match Value
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
PWM Match Value
Figure 18-10: TMR_PWMMATCH Register Diagram
Table 18-12:
TMR_PWMMATCH Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
PWM Match Value.
The value is used when the PWM is operating in match mode. The PWM output is
asserted when the Up/Down counter is equal to this match value. PWM output is
deasserted again when a timeout event occurs. If the match value is never reached, or
occurs simultaneous to a timeout event, the PWM output remains idle.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–17
ADuCM302x TMR Register Descriptions
Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CNTRST (R)
Counter reset occurring
TIMEOUT (R)
Timeout event occurred
PDOK (R)
Clear Interrupt Register synchronization
CAPTURE (R)
Capture event pending
BUSY (R)
Timer Busy
Figure 18-11: TMR_STAT Register Diagram
Table 18-13:
TMR_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
8 CNTRST
(R/NW)
7 PDOK
(R/NW)
Counter reset occurring.
Indicates that the counter is currently being reset due to an event detection. For this to
work, TMR_CTL.RSTEN needs to be set
Clear Interrupt Register synchronization.
This bit is set automatically when the user sets TMR_CLRINT.TIMEOUT=1. It is
cleared automatically when the clear interrupt request has crossed clock domains and
taken effect in the timer clock domain
0 The interrupt is cleared in the timer clock domain
1 Clear Timeout Interrupt bit is being updated in the timer clock domain
6 BUSY
(R/NW)
Timer Busy.
This bit informs the user that a write to TMR_CTL is still crossing into the timer clock
domain. This bit should be checked after writing TMR_CTL and further writes should
be suppressed until this bit is cleared.
0 Timer ready to receive commands to Control Register
1 Timer not ready to receive commands to Control Register
1 CAPTURE
(R/NW)
Capture event pending.
A capture of the current timer value has occurred.
0 No capture event is pending
1 A capture event is pending
18–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x TMR Register Descriptions
Table 18-13:
TMR_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 TIMEOUT
(R/NW)
Timeout event occurred.
This bit set automatically when the value of the counter reaches zero while counting
down or reaches full scale when counting up. This bit is cleared when
TMR_CLRINT.TIMEOUT is set by the user.
0 No timeout event has occurred
1 A timeout event has occurred
ADuCM302x Mixed-Signal Control Processor Hardware Reference
18–19
ADuCM302x TMR Register Descriptions
16-bit timer value
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Current count
Figure 18-12: TMR_CURCNT Register Diagram
Table 18-14:
TMR_CURCNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/NW)
18–20
Current count.
Reflects the current Up/Down counter value. Value delayed two PCLK cycles due to
clock synchronizers.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
I2C Serial Interface (I2C)
19 I2C Serial Interface (I2C)
The ADuCM302x processor uses the I2C interface that provides both master and slave functionalities. The peripheral complies with the I2C Bus Specification, Version 2.1.
I2C Features
The I2C interface that is used by the ADuCM302x processor supports the following features:
• 2-byte transmit and receive FIFOs for the master and slave.
• Support for repeated starts.
• Support for 10-bit addressing.
• Master arbitration is supported.
• Continuous read mode for the master or up to 512 bytes fixed read.
• Clock stretching supported for the slave and the master.
• Support for four 7-bit device addresses in the slave or one 10-bit address and two 7-bit addresses.
• Support for internal and external loopback.
• Support for DMA.
• Support for bus clear.
I2C Functional Description
The I2C bus peripheral has two pins used for data transfer. SCL is a serial clock, and SDA is a serial data pin. The
pins are configured in a wired-AND format that allows arbitration in a multimaster system.
A master device can be configured to generate the serial clock. The frequency is programmed by the user in the serial
clock divisor register. The master channel can be set to operate in fast mode (400 kHz) or standard mode (100
kHz).
The I2C bus peripherals address in the I2C bus system is programmed by the user. This ID may be changed at any
time while a transfer is not in progress. The user can set up to four slave addresses that will be recognized by the
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–1
I2C Functional Description
peripheral. The peripheral is implemented with a 2-byte FIFO for each transmit and receive shift register. IRQ pins
and status bits in the control registers are available to signal to the processor core when the FIFO's need to be serviced.
ADuCM302x I2C Register List
I2C Master/Slave
Table 19-1:
ADuCM302x I2C Register List
Name
Description
I2C_ADDR1
1st master address byte
I2C_ADDR2
2nd master address byte
I2C_ALT
Hardware general call ID
I2C_ASTRETCH_SCL
Automatic stretch SCL register
I2C_BYT
Start byte
I2C_DIV
Serial clock period divisor
I2C_ID0
1st slave address device ID
I2C_ID1
2nd slave address device ID
I2C_ID2
3rd slave address device ID
I2C_ID3
4th slave address device ID
I2C_MCTL
Master control
I2C_MCRXCNT
Master current receive data count
I2C_MRX
Master receive data
I2C_MRXCNT
Master receive data count
I2C_MSTAT
Master status
I2C_MTX
Master transmit data
I2C_SCTL
Slave control
I2C_SHCTL
Shared control
I2C_SRX
Slave receive
I2C_SSTAT
Slave I2C Status/Error/IRQ
I2C_STAT
Master and slave FIFO status
I2C_STX
Slave transmit
I2C_TCTL
Timing Control Register
I2C Operating Modes
The GPIOs used for I2C communication must be configured in I2C mode before enabling the I2C peripheral.
19–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
I2C Operating Modes
Master Transfer Initiation
If the master enable bit (I2C_MCTL.MASEN) is set, a master transfer sequence will be initiated by writing a value to
the I2C_ADDR1, I2C_ADDR2, and I2C_ID3 registers. If there is valid data in the I2C_MTX and I2C_STX registers,
it will be the first byte transferred in the sequence after the address byte during a write sequence.
Slave Transfer Initiation
If the slave enable bit (I2C_SCTL.SLVEN) is set, a slave transfer sequence will be monitored for the device address
in the I2C_ID0, I2C_ID1, I2C_ID2, or I2C_ID3registers. If the device address is recognized, the part will participate in the slave transfer sequence.
Note that a slave operation always starts with the assertion of one of three interrupt sources (I2C_MSTAT.MRXREQ/
I2C_SSTAT.SRXREQ, I2C_MSTAT.MTXREQ/I2C_SSTAT.STXREQ, or I2C_SSTAT.GCINT). The software looks
for a stop interrupt to ensure that the transaction has completed correctly and to deassert the stop interrupt status
bit.
Rx/Tx Data FIFOs
The transmit datapath for both master and slave consists of Tx FIFOs 2 bytes deep, MTX and STX, and a transmit
shifter. The transmit status bits in I2C_MSTAT[1:0], and I2C_SSTAT[0] denote whether there is valid data in the
Tx FIFO. Data from the Tx FIFO is loaded into the Tx shifter when a serial byte begins transmission. If the Tx
FIFO is not full during an active transfer sequence, the transmit request bit (I2C_MSTAT.MTXREQ or
I2C_SSTAT.STXREQ) in I2C_MSTAT or I2C_SSTAT will assert.
In the slave, if there is no valid data to transmit when the Tx shifter is loaded, the transmit underflow status bit will
assert.
The master will generate a stop condition if there is no data in the transmit FIFO and the master is writing data
(direction bit = 0).
The receive datapath consists of a master and slave Rx FIFO, each two bytes deep, I2C_MRXand I2C_SRX. The
receive request interrupt bits (I2C_MSTAT.MTXREQ or I2C_SSTAT.STXREQ) in I2C_MSTAT or I2C_SSTAT indicate if there is valid data in the Rx FIFO. Data is loaded into the Rx FIFO after each byte is received.
If valid data in the Rx FIFO is overwritten by the Rx shifter, the receive overflow status bit (I2C_MSTAT.MTXREQ
or I2C_SSTAT.STXREQ) will assert.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–3
I2C Operating Modes
Prior to this the slave and interrupts
should be enabled, that is SLVEN,
IENRX, IENTX and IENSTOP should all
be set, if necessary ADR10EN and
EARLYTXR may also be set.
Write Read
to from Slave
Start
Wait for
IRQ
Read SSTA
RXREQ asserted?
N
Y
Read byte of the
indirect address
from SRX
All of indirect address
received?
N
Y
Wait for
IRQ
Read SSTA
Y
RXREQ asserted?
N
STOP asserted?
Read a byte of data
from SRX
Y
N
RXREQ asserted?
N
Verify which source
asserted IRQ and
take appropriate
action
Y
Goto Read
Slave Write
Finish
Figure 19-1: Slave Read/Write Flow
19–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
I2C Operating Modes
Read
Using indirect address
already received, read a
byte from memory and
write it to STX
Wait for
IRQ
Read SSTA
TXREQ asserted?
Y
N
STOP asserted?
Write the next byte of
data to STX
N
Y
Flush salve Tx FIFO as
there may be redundant
data left in it
Verify which source
caused the IRQ and
take action (for example,
2nd repeated start
during a read)
SlaveRead
Complete
Figure 19-2: Slave Read/Write Flow Continued: Read Portion
Master NOACK
When receiving data, the master will respond with a NACK if its FIFO is full and an attempt is made to write
another byte to the FIFO. This last byte received is not written to the FIFO and is lost.
No Acknowledge from Slave
If the slave does not want to acknowledge a read access, simply not writing data into the slave transmit FIFO will
result in a NOACK.
If the slave does not want to acknowledge a master write, assert the I2C_SCTL.NACK bit in the slave control register.
Normally, the slave will ACK all bytes written into the receive FIFO. If the receive FIFO fills up, the slave cannot
write further bytes to it, and it will not acknowledge the byte that it was not written to the FIFO. The master should
then stop the transaction.
The slave will not acknowledge a matching device address if the direction bit is 1 (read) and the transmit FIFO is
empty. Therefore, there is very little time for the microcontroller to respond to a slave transmit request and the assertion of ACK. It is recommended that I2C_SCTL.EARLYTXR is asserted for this reason.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–5
I2C Operating Modes
General Call
If the general call enable bit (I2C_SCTL.GCEN) and the slave enable bit (I2C_SCTL.SLVEN) are set, the device will
respond to a general call. If the second byte of the general call is 0x06, the I2C interface (master and slave) is reset.
The general call interrupt status will assert, and the general call ID bits (I2C_SSTAT.GCID) will be 0x1. User code
should take correct action that is reset the entire system or simple re-enable the I2C inter-face.
If the second byte is 04h (write programmable part of slave address by hardware), the general call interrupt status bit
is asserted, and the general call ID (I2C_SSTAT.GCID) will be 0x2.
The general call interrupt status bit gets set on any general call after the second byte is received, and user code
should take correct action, reprogram the device address, and so on.
If I2C_SCTL.GCEN is asserted, the slave will always acknowledge the first byte of a general call. It will acknowledge
the second byte of a general call if the second byte is 0x04 or 0x06, or if the second byte is a hardware general call,
and I2C_SCTL.HGCEN is asserted.
The ALT register contains the alternate device ID for a hardware general call sequence. If the hardware general call
enable bit (I2C_SCTL.HGCEN), I2C_SCTL.GCEN, and I2C_SCTL.SLVEN are all set, the device will recognize a
hardware general call. When a general call sequence is issued, and the second byte of the sequence is identical to
ALT, the hardware call sequence is recognized for the device.
Generation of Repeated Starts by Master
The master will generate a repeated start if the first master address byte register is written while the master is still
busy with a transaction. Once the state machine has started to transmit the device address, it is then safe to write to
the first master address byte register.
For instance if a writerepeated startread/write transaction is required, write to the first master address byte register
after the state machine starts to transmit the device address or after the first TXREQ interrupt is received. When the
transmit FIFO empties, a repeated start will be generated.
Similarly if a readrepeated startread/write transaction is required, write to the first master address byte register after
the state machine starts to transmit the device address, or after the first RXREQ interrupt is received. When the
requested receive count is reached, a repeated start will be generated.
DMA Requests
Three DMA channels are required to service the I2C master and slave. DMA enable bits are provided in the slave
control register and in the master control register.
I2C Reset Mode
The slave state machine is reset when I2C_SCTL.SLVEN is written to 0, and the master state machine is reset when
I2C_MCTL.MASEN is written to 0.
19–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
I2C Operating Modes
I2C Test Modes
The device can be placed in an internal loopback mode by setting the LOOPBACK bit in the I2C_MCTL register.
There are four FIFOs (master Tx and Rx and slave Tx and Rx); therefore in effect, the I2C peripheral can be setup
to talk to itself. External loopback can be performed if the master is setup to address the address of the slave.
I2C Low Power Mode
If the master and slave are both disabled (I2C_MCTL.MASEN = I2C_SCTL.SLVEN = 0), the device is in its lowest
power mode.
I2C Bus Clear Operation
If the master lost arbitration when the I2C_MCTL.BUSCLR bit is set, the master sends out an extra nine SCL cycles
so that the slave holding the SDA line can release it anywhere before those nine SCL cycles. If the
I2C_MCTL.STOPBUSCLR bit is asserted, the master stops sending the SCL clocks once SDA is released.
Power-down Considerations
The following points must be considered when the part is being powered down to hibernate mode. If the master/
slave is IDLE (which can be known from the respective status registers), then it can be immediately disabled by
clearing I2C_MCTL.MASEN/I2C_SCTL.SLVEN bits in the master/slave control registers respectively.
If they are active, then there are four cases:
• I2C is a master and it does Rx:
In this case, the device would be receiving data based on the count programmed in the I2C_MRXCNT register.
It would be in continuous read-mode if the I2C_MRXCNT.EXTEND (I2C_MRXCNT [8]) is set. To stop the read
transfer clear the I2C_MRXCNT.EXTEND bit and assign the I2C_MRXCNT register with I2C_MCRXCNT.VALUE
+ 1", where I2C_MCRXCNT.VALUE gives the current read count.
The "+1" signifies that there should be some room for the completion. If the newly programmed value is less
than the current count, it will receive until the current count overflows and reaches the programmed count.
This will end the transfer after receiving the next byte. Once the transaction complete interrupt is received, the
core should disable the master by clearing I2C_MCTL.MASEN bit.
• I2C is a master and it does Tx:
The s/w should flush the Tx-FIFO by setting I2C_STAT.MFLUSH (I2C_STAT.[9]) and disable Tx-request by
clearing I2C_MCTL.IENMTX (I2C_MCTL[5]). This will end the current transfer after transmitting the byte in
progress. When the transaction complete interrupt is received, it should clear I2C_MCTL.MASEN bit in
I2C_MCTL register.
NOTE: Disabling the master before completion can cause the bus to hang indefinitely.
• I2C is a slave and it does Rx:
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–7
I2C Data Transfer
The s/w should set the I2C_SCTL.NACK bit (bit-7) of I2C_SCTL register. This will give a No-Ack for the next
communication, after which, the external master has to STOP. On receiving the STOP interrupt, the core
should disable the slave by clearing I2C_SCTL.SLVEN bit of I2C_SCTL register.
• I2C is a slave and it does Tx:
Once the Slave transmit starts, it cannot No-Ack any further transaction (ACK is driven only by the master).
So, it has to wait until the external master issues a STOP condition. After receiving the STOP interrupt, the
slave can be disabled. This is a clean way to exit. However, if the slave has to be disabled immediately, then it
can be done only at the cost of wrong data getting transmitted (all FFs). This is because the SDA line will not
be driven anymore and it will be pulled up during data phase. Note that the bus will not hang in this case.
NOTE: I2C_SCTL[6] should be 0 when disabling the slave. If it was previously asserted, then it should be
cleared. Else, the slave will just hold the SCL line at 0.
I2C Data Transfer
the I2C peripheral can be programmed for data transfer through both core and DMA modes. There are dedicated
DMA channels for master and slave functionalities. Refer to the DMA chapter for the DMA channel numbers.
I2C Interrupts and Exceptions
The I2C block can generate interrupts under various conditions in both master and slave modes.
ADuCM302x I2C Register Descriptions
I2C Master/Slave (I2C) contains the following registers.
Table 19-2:
ADuCM302x I2C Register List
Name
Description
I2C_ADDR1
1st master address byte
I2C_ADDR2
2nd master address byte
I2C_ALT
Hardware general call ID
I2C_ASTRETCH_SCL
Automatic stretch SCL register
I2C_BYT
Start byte
I2C_DIV
Serial clock period divisor
I2C_ID0
1st slave address device ID
I2C_ID1
2nd slave address device ID
I2C_ID2
3rd slave address device ID
I2C_ID3
4th slave address device ID
19–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Table 19-2:
ADuCM302x I2C Register List (Continued)
Name
Description
I2C_MCTL
Master control
I2C_MCRXCNT
Master current receive data count
I2C_MRX
Master receive data
I2C_MRXCNT
Master receive data count
I2C_MSTAT
Master status
I2C_MTX
Master transmit data
I2C_SCTL
Slave control
I2C_SHCTL
Shared control
I2C_SRX
Slave receive
I2C_SSTAT
Slave I2C Status/Error/IRQ
I2C_STAT
Master and slave FIFO status
I2C_STX
Slave transmit
I2C_TCTL
Timing Control Register
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–9
ADuCM302x I2C Register Descriptions
1st master address byte
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Address byte 1
Figure 19-3: I2C_ADDR1 Register Diagram
Table 19-3:
I2C_ADDR1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
19–10
Address byte 1.
If a 7 bit address is required, Bit 7 to Bit 1 of I2C_ADDR1.VALUE are programmed
with the address and Bit 0 of I2C_ADDR1.VALUE is programmed with the direction
(read or write) If a 10 bit address is required, Bit 7 to Bit 3 of I2C_ADDR1.VALUE are
programmed with 11110, Bit 2 to Bit 1 of I2C_ADDR1.VALUE are programmed with
the 2 MSBs of the address and Bit 0 of I2C_ADDR1.VALUE is programmed to 0.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
2nd master address byte
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Address byte 2
Figure 19-4: I2C_ADDR2 Register Diagram
Table 19-4:
I2C_ADDR2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
Address byte 2.
This register is only required when addressing a slave with a 10 bit address. Bit 7 to Bit
0 of I2C_ADDR2.VALUE are programmed with the lower 8 bits of the address.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–11
ADuCM302x I2C Register Descriptions
Hardware general call ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
ID (R/W)
Slave Alt
Figure 19-5: I2C_ALT Register Diagram
Table 19-5:
I2C_ALT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 ID
(R/W)
19–12
Slave Alt.
This register is used in conjunction with I2C_SCTL.HGCEN to match a master generating a 'hardware general call'. It is used in the case where a master device cannot be
programmed with a slave's address and instead the slave has to recognise the master's
address.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Automatic stretch SCL register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SLVTMO (R)
slave automatic stretch timeout
MST (R/W)
master automatic stretch mode
MSTTMO (R)
master automatic stretch timeout
SLV (R/W)
slave automatic stretch mode
Figure 19-6: I2C_ASTRETCH_SCL Register Diagram
Table 19-6:
I2C_ASTRETCH_SCL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9 SLVTMO
(R/NW)
8 MSTTMO
(R/NW)
7:4 SLV
(R/W)
3:0 MST
(R/W)
slave automatic stretch timeout.
Asserts when slave automatic stretch timeout. Cleared when read this bit.
master automatic stretch timeout.
Asserts when master automatic stretch timeout. Cleared when read this bit.
slave automatic stretch mode.
It defines the automatic stretch mode for slave. It is referred to stretch_mode_mas. As
a slave transmitter, SCL clock will be automatically stretched start from the negative
edge of SCL, when slave TX FIFO is empty, before send ACK/NACK for address
byte, or before send data for data byte. And stretching will stop when slave TX FIFO is
no longer empty or timeout occurs. As a slave receiver, SCL clock will be automatically
stretched start from the negative edge of SCL, when slave RX FIFO is overflow, before
send ACK/NACK. And stretching will stop when slave RX FIFO is no longer overflow
or timeout occurs. Slave clock stretch mode will be automatically disabled when
slv_txint_clr is asserted. And stretch mode will restore the old value after mas_txint_clr
is cleared. Note: when stretch_mode_slv is 4b0000, I2C_SCTL.EARLYTXR must be
set to 1, otherwise CPU has no time to service slave transmit interrupt when receive
address and read request.
master automatic stretch mode.
It defines the automatic stretch mode for master. Stretching means hold SCL line
LOW, then theres more time to service the interrupt. And use a timeout to avoid bus
lockup. 0000: no SCL clock stretching 0001: stretch SCL up to 2^1 = 2 bit-times
0010: stretch SCL up to 2^2 = 4 bit-times 1110: stretch SCL up to 2^14 bit-times
1111: stretch SCL up to infinity (no timeout) Bit time is decided by I2C_DIV.HIGH
+ I2C_DIV.LOW, and count by uclk. Maximum timeout would provide approximately 2^14/400kHz = 40ms. The will be compatible with SMBus, which has a timeout of
35ms. As a master transmitter, SCL clock will be automatically stretched start from the
negative edge of SCL, when master TX FIFO is empty, before send data. And stretching will stop when master TX FIFO is no longer empty or timeout occurs. As a master
receiver, SCL clock will be automatically stretched start from the negative edge of SCL,
when master RX FIFO is overflow, before ACK/NACK. And stretching will stop when
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–13
ADuCM302x I2C Register Descriptions
Table 19-6:
I2C_ASTRETCH_SCL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
master RX FIFO is no longer overflow or timeout occurs. Master clock stretch mode
will be automatically disabled when mas_txint_clr is asserted or a new address is written. And stretch mode will restore the old value after mas_txint_clr is cleared or the
address is loaded (RESTART is sent).
19–14
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Start byte
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SBYTE (R/W)
Start byte
Figure 19-7: I2C_BYT Register Diagram
Table 19-7:
I2C_BYT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 SBYTE
(R/W)
Start byte.
This register can be used to generate a start byte at the start of a transaction. To generate a start byte followed by a normal address, first write to I2C_BYT.SBYTE then
write to the address register (I2C_ADDR1). This will drive the byte written in
I2C_BYT.SBYTE on to the bus followed by a repeated start. This register can be used
to drive any byte on to the I2C bus followed by a repeated start (not just a start byte
00000001).
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–15
ADuCM302x I2C Register Descriptions
Serial clock period divisor
15 14 13 12 11 10 9
0
0
0
1
1
1
1
8
7
6
5
4
3
2
1
0
1
0
0
0
1
1
1
1
1
HIGH (R/W)
Serial clock high time
LOW (R/W)
Serial clock low time
Figure 19-8: I2C_DIV Register Diagram
Table 19-8:
I2C_DIV Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 HIGH
(R/W)
7:0 LOW
(R/W)
19–16
Serial clock high time.
This register controls the clock high time. The timer is driven by the core clock
(UCLK). Use the following equation to derive the required high time.
I2C_DIV.HIGH = ( REQD_HIGH_TIME/UCLK_PERIOD ) - 2 For example to
generate a 400kHz SCL with a low time of 1300ns and a high time of 1200ns, with a
core clock frequency of 50MHz: LOTIME = 1300ns/20ns - 1 = 0x40 (64 decimal)
I2C_DIV.HIGH = 1200ns/20ns - 2 = 0x3A (58 decimal). This register is reset to 0x1F
which gives an SCL high time of 33 UCLK ticks. tHD:STA is also determined by the
I2C_DIV.HIGH. tHD:STA = (HIGH-1) x uclk_period. As tHD:STA must be 600ns;
with UCLK = 50MHz the minimum value for I2C_DIV.HIGH is 31. This gives an
SCL high time of 660ns.
Serial clock low time.
This register controls the clock low time. The timer is driven by the core clock
(UCLK). Use the following equation to derive the required low time. I2C_DIV.LOW =
( REQD_LOW_TIME/UCLK_PERIOD ) - 1 This register is reset to 0x1F which
gives an SCL low time of 32 UCLK ticks.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
1st slave address device ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave device ID 0
Figure 19-9: I2C_ID0 Register Diagram
Table 19-9:
I2C_ID0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
Slave device ID 0.
I2C_ID0.VALUE[7:1] is programmed with the device ID. I2C_ID0.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmed
with a 10 bit address.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–17
ADuCM302x I2C Register Descriptions
2nd slave address device ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave device ID 1
Figure 19-10: I2C_ID1 Register Diagram
Table 19-10:
I2C_ID1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
19–18
Slave device ID 1.
I2C_ID1.VALUE[7:1] is programmed with the device ID. I2C_ID1.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmed
with a 10 bit address.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
3rd slave address device ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave device ID 2
Figure 19-11: I2C_ID2 Register Diagram
Table 19-11:
I2C_ID2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
Slave device ID 2.
I2C_ID2.VALUE[7:1] is programmed with the device ID. I2C_ID2.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmed
with a 10 bit address.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–19
ADuCM302x I2C Register Descriptions
4th slave address device ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave device ID 3
Figure 19-12: I2C_ID3 Register Diagram
Table 19-12:
I2C_ID3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
19–20
Slave device ID 3.
I2C_ID3.VALUE[7:1] is programmed with the device ID. I2C_ID3.VALUE[0] is
don't care. See the I2C_SCTL.ADR10EN bit to see how this register is programmed
with a 10 bit address.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Master control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
STOPBUSCLR (R/W)
Prestop Bus-Clear
MASEN (R/W)
Master enable
BUSCLR (R/W)
Bus-Clear Enable
COMPLETE (R/W)
Start back-off disable
MTXDMA (W)
Enable master Tx DMA request
LOOPBACK (R/W)
Internal loopback enable
MRXDMA (W)
Enable master Rx DMA request
STRETCHSCL (R/W)
Stretch SCL enable
MXMITDEC (R/W)
Decrement master TX FIFO status when
a byte has been transmitted
IENMRX (R/W)
Receive request interrupt enable
IENMTX (R/W)
Transmit request interrupt enable.
IENCMP (R/W)
Transaction completed (or stop detected)
interrupt enable
IENALOST (R/W)
Arbitration lost interrupt enable
IENACK (R/W)
ACK not received interrupt enable
Figure 19-13: I2C_MCTL Register Diagram
Table 19-13:
I2C_MCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
13 STOPBUSCLR
(R/W)
12 BUSCLR
(R/W)
11 MTXDMA
(RX/W)
10 MRXDMA
(RX/W)
9 MXMITDEC
Prestop Bus-Clear.
This bit should be used in conjunction with I2C_MCTL.BUSCLR. If this bit is set, the
master will stop sending any more SCL clocks if SDA is released before 9 SCL cycles.
Bus-Clear Enable.
If this bit is set, the master will initiate a Bus-Clear operation by sending up to 9 extra
SCL cycles if the arbitration was lost. This bit is added to come out of a SDA-stuck
situation due to a misbehaving slave and hence it should be used with caution. It
should be set only when there is no other active I2C master.
Enable master Tx DMA request.
Set to 1 by user code to enable I2C master DMA Tx requests. Cleared by user code to
disable DMA mode.
Enable master Rx DMA request.
Set to 1 by user code to enable I2C master DMA Rx requests. Cleared by user code to
disable DMA mode.
Decrement master TX FIFO status when a byte has been transmitted.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–21
ADuCM302x I2C Register Descriptions
Table 19-13:
I2C_MCTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
If set to 1, the master transmit FIFO status is decremented when a byte has been transmitted. If set to 0, the master transmit FIFO status is decremented when the byte is
unloaded from the FIFO into a shadow register at the start of byte transmission.
8 IENCMP
(R/W)
7 IENACK
Transaction completed (or stop detected) interrupt enable.
Transaction completed interrupt enable. When asserted an interrupt is generated when
a STOP is detected.
ACK not received interrupt enable.
(R/W)
6 IENALOST
Arbitration lost interrupt enable.
(R/W)
5 IENMTX
Transmit request interrupt enable..
(R/W)
4 IENMRX
Receive request interrupt enable.
(R/W)
3 STRETCHSCL
(R/W)
2 LOOPBACK
(R/W)
1 COMPLETE
(R/W)
0 MASEN
(R/W)
19–22
Stretch SCL enable.
Setting this bit tells the device if SCL is 0 hold it at 0;. Or if SCL is 1 then when it
next goes to 0 hold it at 0.
Internal loopback enable.
When this bit is set SCL and SDA out of the device are muxed onto their corresponding inputs. Note that is also possible for the master to loop back a transfer to the slave
as long as the device address corresponds, i.e. external loopback.
Start back-off disable.
Setting this bit enables the device to compete for ownership even if another device is
currently driving a START condition.
Master enable.
When the bit is 1 the master is enabled. When the bit is 0 all master state machine
flops are held in reset and the master is disabled. The master should be disabled when
not in use as this will gate the clock to the master and save power. This bit should not
be cleared until a transaction has completed, see the I2C_MSTAT.TCOMP bit in the
master status register. Note that APB writable register bits are not reset by this bit.
Cleared by default.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Master current receive data count
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Current receive count
Figure 19-14: I2C_MCRXCNT Register Diagram
Table 19-14:
I2C_MCRXCNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/NW)
Current receive count.
This register gives the total number of bytes received so far. If 256 bytes are requested
then this register will read 0 when the transaction has completed.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–23
ADuCM302x I2C Register Descriptions
Master receive data
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Master receive register
Figure 19-15: I2C_MRX Register Diagram
Table 19-15:
I2C_MRX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/NW)
19–24
Master receive register.
This register allows access to the receive data FIFO. The FIFO can hold 2 bytes.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Master receive data count
15 14 13 12 11 10 9
0
0
0
0
0
0
0
EXTEND (R/W)
Extended read
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Receive count
Figure 19-16: I2C_MRXCNT Register Diagram
Table 19-16:
I2C_MRXCNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
8 EXTEND
(R/W)
7:0 VALUE
(R/W)
Extended read.
Use this bit if greater than 256 bytes are required on a read. For example, to receive
412 bytes write 1 to I2C_MRXCNT.EXTEND. Wait for the first byte to be received,
then check the I2C_MCRXCNT register for every byte received thereafter. When
I2C_MRXCNT.VALUE returns to 0, 256 bytes have been received. Then write 0x09C
to the I2C_MRXCNT register.
Receive count.
Program the number of bytes required minus one to this register. If just 1 byte is required write 0 to this register. If greater than 256 bytes are required then use
I2C_MRXCNT.EXTEND.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–25
ADuCM302x I2C Register Descriptions
Master status
15 14 13 12 11 10 9
0
1
1
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SCLFILT (R)
State of SCL Line
MTXF (R)
Master Transmit FIFO status
SDAFILT (R)
State of SDA Line
MTXREQ (R/W)
When read is master Transmit request;
when write is Clear master transmit
interrupt bit
MTXUNDR (RC)
Master Transmit Underflow
MRXREQ (R)
Master Receive request
MSTOP (RC)
STOP driven by this I2C Master
LINEBUSY (R)
Line is busy
NACKADDR (RC)
ACK not received in response to an
address
MRXOVR (RC)
Master Receive FIFO overflow
ALOST (RC)
Arbitration lost
TCOMP (RC)
Transaction complete or stop detected
MBUSY (R)
Master busy
NACKDATA (RC)
ACK not received in response to data
write
Figure 19-17: I2C_MSTAT Register Diagram
Table 19-17:
I2C_MSTAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 SCLFILT
(R/NW)
13 SDAFILT
(R/NW)
12 MTXUNDR
(RC/NW)
11 MSTOP
(RC/NW)
19–26
State of SCL Line.
This bit is the output of the glitch-filter on SCL. SCL is always pulled high when undriven.
State of SDA Line.
This bit is the output of the glitch-filter on SDA. SDA is always pulled high when undriven.
Master Transmit Underflow.
Asserts when the I2C master ends the transaction due to Tx-FIFO empty condition.
This bit is asserted only when the I2C_MCTL.IENMTX bit is set.
STOP driven by this I2C Master.
Asserts when this I2C master drives a STOP condition on the I2C bus. This bit, when
asserted, can indicate a Transaction completion, Tx-underflow, Rx-overflow or a
NACK by the slave. This is different from the I2C_MSTAT.TCOMP as this bit is not
asserted when the STOP condition occurs due to any other I2C master. No interrupt
is generated for the assertion of this bit. However, if I2C_MCTL.IENCMP = 1, every
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Table 19-17:
I2C_MSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
STOP condition will generate an interrupt and this bit can be read. When this bit is
read, it will clear status.
10 LINEBUSY
(R/NW)
9 MRXOVR
(RC/NW)
8 TCOMP
(RC/NW)
7 NACKDATA
(RC/NW)
6 MBUSY
(R/NW)
5 ALOST
(RC/NW)
4 NACKADDR
(RC/NW)
3 MRXREQ
(R/NW)
2 MTXREQ
(R/W)
Line is busy.
Asserts when a START is detected on the I2C bus. De-asserts when a STOP is detected on the I2C bus.
Master Receive FIFO overflow.
Asserts when a byte is written to the receive FIFO when the FIFO is already full.
When the bit is read it will clear status.
Transaction complete or stop detected.
Transaction complete. This bit will assert when a STOP condition is detected on the
I2C bus. If I2C_MCTL.IENCMP = 1, an interrupt will be generated when this bit asserts. This bit will only assert if the master is enabled (I2C_MCTL.MASEN = 1). This
bit should be used to determine when it is safe to disable the master. It can also be used
to wait for another master transaction to complete on the I2C bus when this master
looses arbitration. When this bit is read it will clear status. This bit can drive an interrupt.
ACK not received in response to data write.
This bit will assert when an ACK is not received in response to a data write transfer. If
I2C_MCTL.IENACK = 1, an interrupt will be generated when this bit asserts. This bit
can drive an interrupt. This bit is cleared on a read of the I2C_MSTAT register.
Master busy.
This bit indicates that the master state machine is servicing a transaction. It will be
clear if the state machine is idle or another device has control of the I2C bus.
Arbitration lost.
This bit will assert if the master looses arbitration. If I2C_MCTL.IENALOST = 1, an
interrupt will be generated when this bit asserts. This bit is cleared on a read of the
I2C_MSTAT register. This bit can drive an interrupt.
ACK not received in response to an address.
This bit will assert if an ACK is not received in response to an address. If
I2C_MCTL.IENACK = 1, an interrupt will be generated when this bit asserts. This bit
is cleared on a read of the I2C_MSTAT register. This bit can drive an interrupt.
Master Receive request.
This bit will assert when there is data in the receive FIFO. If I2C_MCTL.IENMRX = 1,
an interrupt will be generated when this bit asserts. This bit can drive an interrupt.
When read is master Transmit request; when write is Clear master transmit interrupt
bit.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–27
ADuCM302x I2C Register Descriptions
Table 19-17:
I2C_MSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
I2C_MSTAT.MTXREQ , read only. This bit will assert when the direction bit is '0' and
the transmit FIFO is not full. If I2C_MCTL.IENMTX = '1', an interrupt will be
generated when this bit asserts. mas_txint_clr: write only. When this bit is 1, master
transmit interrupt and clock stretching will be cleared. And this bit will be cleared,
upon STOP or START condition.
1:0 MTXF
(R/NW)
19–28
Master Transmit FIFO status.
These 2 bits show the master transmit FIFO status and can be decoded as follows: 00
= FIFO Empty 10 = 1 byte in FIFO 11 = FIFO Full.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Master transmit data
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Master transmit register
Figure 19-18: I2C_MTX Register Diagram
Table 19-18:
I2C_MTX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
(R/W)
Master transmit register.
For test and debug purposes, when read, this register returns the byte that is currently
being transmitted by the master. That is a byte written to the transmit register can be
read back some time later when that byte is being transmitted on the line. This register
allows access to the transmit data FIFO. The FIFO can hold 2 bytes.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–29
ADuCM302x I2C Register Descriptions
Slave control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
STXDMA (R/W)
Enable slave Tx DMA request
SLVEN (R/W)
Slave enable
SRXDMA (R/W)
Enable slave Rx DMA request
ADR10EN (R/W)
Enabled 10-bit addressing
IENREPST (R/W)
Repeated start interrupt enable
GCEN (R/W)
General call enable
STXDEC (R/W)
Decrement Slave Tx FIFO status when
a byte has been transmitted
HGCEN (R/W)
Hardware general call enable
GCSBCLR (W)
General call status bit clear
IENSTX (R/W)
Slave Transmit request interrupt enable
EARLYTXR (R/W)
Early transmit request mode
IENSRX (R/W)
Slave Receive request interrupt enable
NACK (R/W)
NACK next communication
IENSTOP (R/W)
Stop condition detected interrupt enable
Figure 19-19: I2C_SCTL Register Diagram
Table 19-19:
I2C_SCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 STXDMA
(R/W)
13 SRXDMA
(R/W)
12 IENREPST
(R/W)
11 STXDEC
(R/W)
10 IENSTX
Enable slave Tx DMA request.
Set to 1 by user code to enable I2C slave DMA Rx requests. Cleared by user code to
disable DMA mode.
Enable slave Rx DMA request.
Set to 1 by user code to enable I2C slave DMA Rx requests. Cleared by user code to
disable DMA mode.
Repeated start interrupt enable.
If 1 an interrupt will be generated when the I2C_SSTAT.REPSTART status bit asserts.
If 0 an interrupt will not be generated when the I2C_SSTAT.REPSTART status bit
asserts.
Decrement Slave Tx FIFO status when a byte has been transmitted.
If set to 1, the transmit FIFO status is decremented when a byte has been transmitted.
If set to 0, the transmit FIFO status is decremented when the byte is unloaded from
the FIFO into a shadow register at the start of byte transmission.
Slave Transmit request interrupt enable.
(R/W)
9 IENSRX
19–30
Slave Receive request interrupt enable.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Table 19-19:
I2C_SCTL Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
(R/W)
8 IENSTOP
Stop condition detected interrupt enable.
(R/W)
7 NACK
(R/W)
5 EARLYTXR
(R/W)
4 GCSBCLR
(RX/W)
3 HGCEN
(R/W)
2 GCEN
(R/W)
1 ADR10EN
(R/W)
0 SLVEN
(R/W)
NACK next communication.
If this bit is set the next communication will be NACK 'ed. This could be used for
example if during a 24xx style access, an attempt was made to write to a 'read only' or
nonexisting location in system memory. That is the indirect address in a 24xx style
write pointed to an unwritable memory location.
Early transmit request mode.
Setting this bit enables a transmit request just after the positive edge of the direction
bit SCL clock pulse.
General call status bit clear.
The I2C_SSTAT.GCINT and I2C_SSTAT.GCID bits are cleared when a '1' is written
to this bit. The I2C_SSTAT.GCINT and I2C_SSTAT.GCID bits are not reset by anything other than a write to this bit or a full reset.
Hardware general call enable.
When this bit and the I2C_SCTL.GCEN bit are set the device after receiving a general
call, address 00h and a data byte checks the contents of the I2C_ALT against the receive shift register. If they match the device has received a 'hardware general call'. This
is used if a device needs urgent attention from a master device without knowing which
master it needs to turn to. This is a call "to whom it may concern". The device that
requires attention embeds its own address into the message. The LSB of the I2C_ALT
register should always be written to a 1, as per I2C January 2000 specification.
General call enable.
This bit enables the I2C slave to ACK an I2C general call, address 0x00 (Write).
Enabled 10-bit addressing.
If this bit is clear, the slave can support four slave addresses, programmed in I2C_ID0
to I2C_ID0. When this bit is set, 10 bit addressing is enabled. One 10 bit address is
supported by the slave and is stored in I2C_ID0 and I2C_ID1, where I2C_ID0 contains the first byte of the address and the upper 5 bits must be programmed to 11110.
I2C_ID2 and I2C_ID3 can be programmed with 7 bit addresses at the same time.
Slave enable.
When '1' the slave is enabled. When '0' all slave state machine flops are held in reset
and the slave is disabled. Note that APB writable register bits are not reset.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–31
ADuCM302x I2C Register Descriptions
Shared control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RST (W)
Reset START STOP detect circuit
Figure 19-20: I2C_SHCTL Register Diagram
Table 19-20:
I2C_SHCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
0 RST
(RX/W)
19–32
Reset START STOP detect circuit.
Writing a 1 to this bit will reset the SCL and SDA synchronisers, the START and
STOP detect circuit and the LINEBUSY detect circuit. These circuits are not reset
when both the master and slave are disabled as LINEBUSY needs to assert even when
the master is not enabled. It should only be necessary to reset these circuits after a
power on reset in case SCL/SDA do not power up cleanly. Reading this bit will always
read back '0'.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Slave receive
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Slave receive register
Figure 19-21: I2C_SRX Register Diagram
Table 19-21:
I2C_SRX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
Slave receive register.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–33
ADuCM302x I2C Register Descriptions
Slave I2C Status/Error/IRQ
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
START (R)
Start and matching address
STXFSEREQ (R/W)
Slave Tx FIFO Status or early request
REPSTART (RC)
Repeated start and matching address
STXUNDR (RC)
Slave Transmit FIFO underflow
IDMAT (R)
Device ID matched
STXREQ (RC)
When read is slave transmit request;
when write is clear slave transmit interrupt
bit
STOP (RC)
Stop after start and matching address
SRXREQ (RC)
Slave Receive request
GCID (R)
General ID
SRXOVR (RC)
Slave Receive FIFO overflow
GCINT (R)
General call interrupt
NOACK (RC)
Ack not generated by the slave
SBUSY (R)
Slave busy
Figure 19-22: I2C_SSTAT Register Diagram
Table 19-22:
I2C_SSTAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 START
(R/NW)
13 REPSTART
(RC/NW)
12:11 IDMAT
(R/NW)
Start and matching address.
This bit is asserted if a start is detected on SCL/SDA and the device address matched,
or a general call(GC - 0000_0000) code is received and GC is enabled, or a High
Speed (HS - 0000_1XXX) code is received, or a start byte (0000_0001) is received. It
is cleared on receipt of either a stop or start condition.
Repeated start and matching address.
This bit is asserted if I2C_SSTAT.START is already asserted and then a repeated start
is detected. It is cleared when read or on receipt of a STOP condition. This bit can
drive an interrupt.
Device ID matched.
0 Received address matched ID register 0
1 Received address matched ID register 1
2 Received address matched ID register 2
3 Received address matched ID register 3
10 STOP
Stop after start and matching address.
(RC/NW)
19–34
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Table 19-22:
I2C_SSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
Gets set by hardware if the slave device received a STOP condition after a previous
START condition and a matching address. Cleared by a read of the I2C_SSTAT register. If I2C_SCTL.IENSTOP in the slave control register is asserted, then the slave
interrupt request will assert when this bit is set. This bit can drive an interrupt.
9:8 GCID
(R/NW)
General ID.
I2C_SSTAT.GCID is cleared when the I2C_SCTL.GCSBCLR is written to 1. These
status bits will not be cleared by a 'General call reset'.
0 No general call
1 General call reset and program address
2 General call program address
3 General call matching alternative ID
7 GCINT
(R/NW)
6 SBUSY
(R/NW)
5 NOACK
(RC/NW)
4 SRXOVR
(RC/NW)
3 SRXREQ
(RC/NW)
2 STXREQ
(RC/NW)
General call interrupt.
This bit always drives an interrupt. The bit is asserted if the slave device receives a general call of any type. To clear, write 1 to the I2C_SCTL.GCSBCLR in the slave control
register. If it was a general call reset, all registers will be at their default values. If it was
a hardware general call, the Rx FIFO holds the second byte of the general call, and this
can be compared with the I2C_ALT register.
Slave busy.
Set by hardware if the slave device receives a I2C START condition. Cleared by hardware when the address does not match an ID register, the slave device receives a I2C
STOP condition, or if a repeated start address does not match.
Ack not generated by the slave.
When asserted, it indicates that the slave responded to its device address with a
NOACK. It is asserted if there was no data to transmit and sequence was a slave read
or if the I2C_SCTL.NACK bit was set and the device was addressed. This bit is cleared
on a read of the I2C_SSTAT register.
Slave Receive FIFO overflow.
Asserts when a byte is written to the slave receive FIFO when the FIFO is already full.
Slave Receive request.
I2C_SSTAT.SRXREQ asserts whenever the slave receive FIFO is not empty. Read or
flush the slave receive FIFO to clear this bit. This bit will assert on the falling edge of
the SCL clock pulse that clocks in the last data bit of a byte. This bit can drive an
interrupt.
When read is slave transmit request; when write is clear slave transmit interrupt bit.
I2C_SSTAT.STXREQ, read only If I2C_SCTL.EARLYTXR = 0,
I2C_SSTAT.STXREQ is set when the direction bit for a transfer is received high.
There after, as long as the transmit FIFO is not full this bit will remain asserted. Initially it is asserted on the negative edge of the SCL pulse that clocks in the direction bit
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–35
ADuCM302x I2C Register Descriptions
Table 19-22:
I2C_SSTAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
(if the device address matched also). If I2C_SCTL.EARLYTXR = 1,
I2C_SSTAT.STXREQ is set when the direction bit for a transfer is received high.
There after, as long as the transmit FIFO is not full this bit will remain asserted. Initially it is asserted after the positive edge of the SCL pulse that clocks in the direction
bit (if the device address matched also). This bit is cleared on a read of the
I2C_SSTAT register. slv_txint_clr, write only. When this bit is 1, slave transmit interrupt and clock stretching will be cleared. And this bit will be cleared, when STOP or
(RE)START is received (transfer is done); TX FIFO is written (software decided it
now has more data to send); TX FIFO is empty and an ACK is received instead of a
NACK.
1 STXUNDR
(RC/NW)
0 STXFSEREQ
(R/W)
19–36
Slave Transmit FIFO underflow.
Is set if a master requests data from the device, and the Tx FIFO is empty for the rising
edge of SCL.
Slave Tx FIFO Status or early request.
If I2C_SCTL.EARLYTXR = 0, this bit is asserted whenever the slave Tx FIFO is empty. If I2C_SCTL.EARLYTXR = 1, I2C_SSTAT.STXFSEREQ is set when the direction
bit for a transfer is received high. It asserts on the positive edge of the SCL clock pulse
that clocks in the direction bit (if the device address matched also). It only asserts once
for a transfer. It is cleared when read if I2C_SCTL.EARLYTXR is asserted.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Master and slave FIFO status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
MFLUSH (W)
Flush the master transmit FIFO
STXF (R)
Slave transmit FIFO status
SFLUSH (W)
Flush the slave transmit FIFO
SRXF (R)
Slave receive FIFO status
MRXF (R)
Master receive FIFO status
MTXF (R)
Master transmit FIFO status
Figure 19-23: I2C_STAT Register Diagram
Table 19-23:
I2C_STAT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9 MFLUSH
(RX/W)
8 SFLUSH
(RX/W)
7:6 MRXF
(R/NW)
Flush the master transmit FIFO.
Writing a '1' to this bit flushes the master transmit FIFO. The master transmit FIFO
will have to flushed if arbitration is lost or a slave responds with a NACK.
Flush the slave transmit FIFO.
Writing a '1' to this bit flushes the slave transmit FIFO.
Master receive FIFO status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved
5:4 MTXF
(R/NW)
Master transmit FIFO status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–37
ADuCM302x I2C Register Descriptions
Table 19-23:
I2C_STAT Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3:2 SRXF
(R/NW)
Slave receive FIFO status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved
1:0 STXF
(R/NW)
Slave transmit FIFO status.
The status is a count of the number of bytes in a FIFO.
0 FIFO empty
1 1 bytes in the FIFO
2 2 bytes in the FIFO
3 Reserved
19–38
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x I2C Register Descriptions
Slave transmit
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Slave transmit register
Figure 19-24: I2C_STX Register Diagram
Table 19-24:
I2C_STX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 VALUE
Slave transmit register.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
19–39
ADuCM302x I2C Register Descriptions
Timing Control Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
1
0
1
FILTEROFF (R/W)
Input Filter Control
THDATIN (R/W)
Data In Hold Start
Figure 19-25: I2C_TCTL Register Diagram
Table 19-25:
I2C_TCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
8 FILTEROFF
(R/W)
Input Filter Control.
Input Filter Control. It may be desirable to disable the digital filter if PCLK rate becomes < 16MHz.
0 Digital filter is enabled and is equal to 1 PCLK
1 Digital filter is disabled. Filtering in the pad is unaffected
4:0 THDATIN
(R/W)
19–40
Data In Hold Start.
I2C_TCTL.THDATIN determines the hold time requirement that must be met before
a start or stop condition is recognized. The hold time observed between SDA and SCL
fall must exceed the programmed value to be recognized as a valid Start.
I2C_TCTL.THDATIN = ( tHD;STA) / (Clock Period). For example, at 16MHz PCLK
(62.5ns) and setting a minimum tHD;STA limit of 300ns. (300ns)/(62.5ns) = 5.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Real Time Clock (RTC)
20 Real Time Clock (RTC)
The ADuCM302x processor uses the real-time clock (RTC) that keeps track of elapsed time, in configurable time
units, using an externally attached 32,768 Hz crystal to generate a time base. When enabled, the RTC maintains a
cumulative count of elapsed time from the counts most recent redefinition (re-initialization) by the CPU or powerup value as applicable. The RTC can count from any configured initial value and roll-overs of the RTC count are
supported. The RTC is a 16-bit peripheral, but contains triple registers for any 47-bit quantities such as the elapsed
time count and alarm values.
The RTC has two configurable alarm features which permit the generation of absolute (exact time match) or periodic (every 60 increments of the RTC count) alarms.
Software is responsible for enabling and configuring the RTC and for interpreting its count value to turn this into
the time of day. The RTC logic also has a digital trim capability that is calibrated to achieve higher PPM accuracy in
tracking time.
RTC Features
The ADuCM302x processor supports the following features:
• An RTC count register with 32 integer bits and 15 fractional bits of elapsed time in configurable time units
from a programmable reference point (initial value). This register is programmed under software control.
• The RTC can count time in units of a divided-down period of the RTC base clock (nominally 32,768
Hz), where the division can be any power of two from zero to fifteen. The range of RTC time units is thus
30.52 us to 1s.
• A prescaler that divides down the RTC base clock -nominally a 32,768 Hz crystal input- by a power of two
which can be any integer from 0 to 15. Note that when programming (initializing) or re-enabling the RTC
count, or when changing the prescale division ratio, the prescaler is automatically zeroed. This is so that the
RTC count value is positioned on exact, coincident boundaries of both the start of the prescale sequence and
the modulo-60 count roll-over.
• In practical terms, this means that a CPU redefinition of the RTC count (elapsed time) can be deposited
on coincident 1-second and 1-minute boundaries, when using a time base of 1 second. The same capability is supported by the RTC for any prescaled time base.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–1
RTC Functional Description
• Two optionally-enabled, independent alarm features (one at absolute time and the other at modulo-60, periodic time) that cause a processor interrupt when the RTC count equals the alarm values. Note that such an interrupt wakes up the processor if the latter is in a sleep state.
• A digital trim capability whereby a positive or negative adjustment (in units of configured RTC time units) can
be added to the RTC count at a fixed interval to keep the RTC PPM time accuracy within target. The values
for both the adjustment and interval are calculated by running a calibration algorithm on the CPU.
• The RTC can take and preserve a snapshot of its elapsed real-time count when prompted to do so by the CPU.
This allows the CPU to associate a time stamp with an incoming data packet. The RTC preserves the snapshot
for read-back by the CPU. The snapshot is persistent and is only overwritten when the CPU issues a request to
capture a new value.
• RTC has an Output-compare feature, which is an alarm function. It sends an output pulse to an external device
via GPIO, and instructs the device to measure or perform some action at a specific time. The output-compare
events are scheduled by the CPU on the ADuCM302x processor by instructing the RTC to activate the output-compare events at a specific target time relative to the RTC real-time count.
• RTC has an Input-capture feature. Input capture is the process of taking a snapshot of the RTC real-time count
when an external device signals an event via a transition on one of the GPIO inputs to the ADuCM302x processor. An input-capture event is triggered by an autonomous measurement or action on a device, which then
signals the ADuCM302x processor that the RTC must take a snapshot of time corresponding to the event.
RTC Functional Description
This section provides information on the function of the RTC used by the ADuCM302x processor.
ADuCM302x RTC Register List
Table 20-1:
ADuCM302x RTC Register List
Name
Description
RTC_ALM0
RTC Alarm 0
RTC_ALM1
RTC Alarm 1
RTC_ALM2
RTC Alarm 2
RTC_CNT0
RTC Count 0
RTC_CNT1
RTC Count 1
RTC_CNT2
RTC Count 2
RTC_CR0
RTC Control 0
RTC_CR1
RTC Control 1
RTC_CR2IC
RTC Control 2 for Configuring Input Capture Channels
20–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
RTC Block Diagram
Table 20-1:
ADuCM302x RTC Register List (Continued)
Name
Description
RTC_CR3OC
RTC Control 3 for Configuring Output Compare Channel
RTC_CR4OC
RTC Control 4 for Configuring Output Compare Channel
RTC_FRZCNT
RTC Freeze Count
RTC_GWY
RTC Gateway
RTC_IC2
RTC Input Capture Channel 2
RTC_IC3
RTC Input Capture Channel 3
RTC_IC4
RTC Input Capture Channel 4
RTC_MOD
RTC Modulo
RTC_OC1
RTC Output Compare Channel 1
RTC_OC1ARL
RTC Auto-Reload for Output Compare Channel 1
RTC_OC1TGT
RTC Output Compare Channel 1 Target
RTC_OCMSK
RTC Masks for Output Compare Channel
RTC_SNAP0
RTC Snapshot 0
RTC_SNAP1
RTC Snapshot 1
RTC_SNAP2
RTC Snapshot 2
RTC_SR0
RTC Status 0
RTC_SR1
RTC Status 1
RTC_SR2
RTC Status 2
RTC_SR3
RTC Status 3
RTC_SR4
RTC Status 4
RTC_SR5
RTC Status 5
RTC_SR6
RTC Status 6
RTC_TRM
RTC Trim
RTC Block Diagram
A high-level block diagram of the RTC is shown below. All functionality for counting, alarm, trim, snapshot and
wake-up interrupts is located in a dedicated 32 kHz timed, always ON RTC power domain. The APB interface with
the CPU, which comprises queuing and dispatch logic for posted register writes, along with interrupts to the Cortex
NVIC are all located in a PCLK/FCLK-timed (synchronous clocks) section of the main power-gated core domain.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–3
RTC Architectural Concepts
RTC
Clock Domain,
32kHz
Crystal
Prescaler
Oscillator
Circuit
32kHz
(Analog) base
clock
RTC
Snapshot
Processor
Clock Domain,
FCLK and PCLK
Digital
Trim
RTC
Count
Interrupt
Conrol
& Status
Clock
Domain
Crossing
Control
Posted
Write
Transaction
Engine
APB
Slave
Port
Alarms
APB
Interrupt
Control
Figure 20-1: RTC High-level Block Diagram
RTC Architectural Concepts
The key use of the RTC is to provide the time keeping function and maintain the time and date in an accurate and
reliable manner with minimal power consumption. In addition to time keeping, it also provides the stopwatch and
alarm features. The RTC uses the internal counters to keep the time of the day in terms of seconds, minutes, hours,
and days. This data is enough for the user application to extract the date and time information from RTC. Interrupts can be issued periodically.
RTC Operating Modes
The RTC used by the ADuCM302x processor supports the following operations.
Initial RTC Power-Up
The RTC operates in a dedicated voltage domain which, under normal (configurable) conditions, is continuously
powered. However, when a battery is attached for the first time or replaced, a power-on reset occurs which resets all
RTC registers.
Upon detecting an RTC failure, the CPU will typically reprogram the RTCs count and digital trim registers and
clear the fail flag in the RTC control register. The CPU can optionally program the alarm registers of the RTC to
generate an interrupt when the alarm and count values match.
Persistent, Sticky RTC Wake-Up Events
Note that there is no loss of any RTC alarm event which happens when the part is in a power down mode. The
resulting interrupt due to the alarm, assuming it is enabled, is maintained asserted by the RTC so that the NVIC
will subsequently see it (an FCLK-timed version of the interrupt) when power is restored to the processor. To facilitate this, the RTC sends a 32kHz-timed version of the same interrupt to the wake-up controller in the PMU which
20–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
RTC Operating Modes
causes the digital core to be repowered. Once the CPU is woken up, it can inspect both the PMU and RTC to
understand the cause of the interrupt event for the wake up.
RTC Capacity to Accommodate Posted Writes by CPU
Note that if a posted write by the CPU to a 32 kHz-sourced MMR in the RTC is pending dispatch (in the RTC)
due to a queue of other, similar register writes to the 32 Hz domain, a second or subsequent write by the CPU to
the same RTC register cannot be stacked up or overwrite the pending transaction. Any such attempts will be rejected
by the RTC. These result in RTC_SR0.WPNDERRINT interrupt events (see the MMR details of RTC_SR0) in the
RTC.
Realignment of RTC Count to Packet-Defined Time Reference
The CPU can instruct the RTC to take a snapshot of its elapsed time count by writing a software key of 0x7627 to
the RTC_GWY MMR. This causes the combined three snap registers (RTC_SNAP2, RTC_SNAP1, and
RTC_SNAP0) to update to the current value of the three count registers (RTC_CNT2, RTC_CNT1, and
RTC_CNT0) and to maintain this snapshot until subsequently told by the CPU to overwrite it.
RTC Recommendations : Clocks and Power
The following recommendations apply for using the RTC.
Stopping PCLK
Before entering any mode which causes PCLK to stop, the CPU should first wait until there is confirmation from
the RTC that no previously posted writes have yet to complete. The CPU can check this by reading both the
RTCSR0 and RTCSR2 registers.
Ensuring No Communication across RTC Power Boundary when Powering
Down
When the CPU has advance knowledge that about a power down, it should take the following action to ensure the
integrity of the always-on half of the RTC.
• Either :
• The CPU should check and satisfy itself that there are no posted writes in the RTC awaiting execution.
• Or :
• Cancel all queued and executing posted writes in the RTC. This is achieved by writing a cancellation key
of 0xA2C5 to the RTC_GWY register which takes immediate effect.
• And :
• Do not post any further register writes to the RTC until power is lost by the core.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–5
RTC Interrupts and Exceptions
These steps ensure that no communication between the CPU and the RTC is happening and thus liable to corruption when the RTC power domains isolation barrier is subsequently activated.
RTC Interrupts and Exceptions
The RTC block can generate interrupts from multiple sources which can be unmasked by programming the
RTC_CONTROL register. The source of the interrupt will be reflected in the RTC_STATUS register.
RTC Programming Model
The following section shows the programming sequence to configure RTC for an alarm event:
Programming Guidelines
The following are the programming guidelines:
1. Reset the RTC_CNT registers to 0.
2. Configure the prescaler to divide the RTC base clock in the RTC_CR1 register.
3. Poll for the RTC synchronization bit to be set in the RTC_SR1 register as the MMR write happens in the
slower RTC domain.
4. Program the RTC_ALM0, RTC_ALM1,RTC_ALM2 registers with the intended alarm time.
5. Enable the interrupt for alarm by setting the ALMINTEN bit in the RTC_CR0 register.
6. Set the ALMEN and RTCEN bits in the RTC_CR0 register.
7. Wait for the RTC alarm interrupt which is triggered when the RTC_CNT matches the RTC_ALM value.
RTC Output Compare
Output-compare is an alarm function in the RTC. It sends an output pulse to an external device via GPIO, and
instructs the device to measure or perform some action at a specific time. The output-compare events are scheduled
by the CPU on the ADuCM302x processor by instructing the RTC to activate the output-compare events at a specific target time relative to the RTC real-time count.
The ADuCM302x supports one output-compare channel with optional masking, auto-reloading, and interrupts,
considering the degree of prescaling of the 32 kHz base clock used by the RTC to count real time. The outputcompare functionality is supported for all prescaling possibilities of the base clock, namely prescaling by power of 2
between 0 and 15, corresponding to the counting integer time between 32 kHz and 1 Hz.
The following are the output-compare capabilities of the RTC1:
• The total number of bits in the concatenated target time is 16.
20–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
RTC Input Capture
The number of fractional bits in the target depends on the degree of prescaling configured for the 32 kHz base
clock. The number of fractional bits used in the output-compare function tracks with the prescaling. The remaining bits in the 16-bit target time consist of integers from the LSB end of the integer count of the RTC.
The number of integer bits combined with the fractional bits (due to prescaling) must be 16.
• There is a 47-bit alarm feature in the RTC. However, there is no GPIO associated with it to act as an outputcompare channel. The target time for this 47-bit alarm is specified as {32_integer_bits, 15_fractional_bits}.
• For the output-compare channel, the target time is always specified down to an individual 32 kHz clock cycle
as all relevant fractional bits are included in the target time.
• For the 16-bit output-compare channels, contiguous bits in the 16-bit target time can be thermometer-code
masked out, on a per-channel basis, from the MSB end of the target.
As a result of this optional masking, the contiguous bits at the MSB end of the target time are treated as Don’t
cares, which results in dividing the periodicity of the repeating output-compare event by 2 for every bit masked
out.
In other words, if more bits are masked out from the MSB end of the target time, the modular sequence of
repeating output-compare events is shortened by a factor of 2 for that channel.
• Auto Reload: Each time an event triggers, a configurable 16-bit delta (the reload value) is added to its target
time to calculate the revised target for the next event. This allows the periodicity of repeating events to be created on this channel which is not a power of two times 32 kHz cycles.
The reloaded target time can be read by the CPU to confirm the accumulation due to reloading with each
event on that output-compare channel. The reloaded target can also be thermometer-code masked.
• The output-compare channel has a readable, sticky interrupt source bit, which activates (sticks high) whenever
an output-compare event occurs. This interrupt source bit can optionally be enabled to fan into the interrupt
and wake-up lines from the RTC.
• Whenever an output-compare event triggers on a channel, a one-cycle pulse of length 32 kHz period is exported by the RTC via the GPIOs, to an external device, prompting the device to act.
• The output-compare channel can be reconfigured and enabled/disabled on the fly, with no interruption to
channels that are not part of the reconfiguration.
RTC Input Capture
Input-capture is the process of taking a snapshot of the RTC real-time count when an external device signals an
event via a transition on one of the GPIO inputs to the ADuCM302x processor. An input-capture event is triggered
by an autonomous measurement or action on a device, which then signals to the ADuCM302x processor that the
RTC must take a snapshot of time corresponding to the event. Taking snapshot can wake up the ADuCM302x and
interrupts the CPU. The CPU can subsequently obtain information from the RTC on the exact 32 kHz cycle and
exact time of the input-capture event.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–7
RTC Input Capture
The ADuCM302x processor supports multiple input-capture channels and associated interrupts, considering the degree of prescaling of the 32 kHz base clock used by the RTC to count real time. The input-capture functionality is
supported for all prescaling possibilities of the base clock, namely prescaling by power of 2 between 0 and 15, corresponding to the counting integer time between 32 kHz and 1 Hz.
The following are the input-capture capabilities of the RTC1:
• Supports four independent input-capture channel (three 16-bit channels and one 47-bit channel):
• The three 16-bit channels snapshot the RTC elapsed count using 16 bits as follows:
{least_significant_integer_bits_to_bring_total_to_16, fractional_bits_due_to_prescaling}
The total number of bits in this concatenated capture time is 16.
The number of fractional bits in the target depends on the degree of prescaling configured for the 32 kHz
base clock. The number of fractional bits used in the input-capture function tracks with the prescaling.
The remaining bits in the 16-bit target time consist of integers from the LSB end of the integer count of
the RTC. The number of integer bits combined with the fractional bits (due to prescaling) must be 16.
• The 47-bit channel captures the absolute time for that input-capture channel, where the capture time is
given as {32_integer_bits, 15_fractional_bits}.
• For each of the four input-capture channels, the snapshot always has a resolution down to an individual 32
kHz clock cycle as all relevant fractional bits are included in the capture time.
• When an input-capture event is detected by the RTC, the accuracy of the snapshot time for the event is as
follows:
• For the three 16-bit input-capture channels, each channel captures a snapshot which is exact in time down
to the 32 kHz cycle in which the event occurred.
• For the one 47-bit input-capture channel, there is a fixed latency (delay) of one 32 kHz cycle of fractional
time in the snapshot value captured for that event.
This latency of one LSB of the fractional count can be subtracted later by the software.
• An input-capture event can be configured as a low-to-high or high-to-low transition on the GPIO input for
that channel. The polarity of this transition can be configured on a per-channel basis. The input-capture channels can individually specify the type of transition that must cause an event for it.
• Each of the four input-capture channels has a readable, sticky interrupt source bit, which activates (sticks high)
whenever an input-capture event occurs. This interrupt source bit can optionally be enabled to fan into (be a
contributory term to) the interrupt and wake-up lines from the RTC.
• User can configure one of the following global overwrite policy for all the input-capture channels in the RTC:
• When a new input-capture event occurs on a given channel, the new snapshot value overwrites the previously captured value for that individual channel.
20–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
• For a given channel, snapshot can be overwritten by a new event only if the CPU has already read the
existing snapshot value for that channel.
NOTE: In addition to the readable interrupt sources, which stick active upon reception of new input-capture events, the RTC also provides flags to the CPU confirming the read/unread status of the input-capture snapshots.
• The input-capture channels can be reconfigured and enabled/disabled on the fly, with no interruption to the
channels not part of the reconfiguration.
• The input-capture channels operate independently of each other and independently of any output-compare
channels in the RTC.
Any number of channels, ranging from 0 to 5, of the four input-capture and one output-compare channels can operate simultaneously.
ADuCM302x RTC Register Descriptions
Real-Time Clock (RTC) contains the following registers.
Table 20-2:
ADuCM302x RTC Register List
Name
Description
RTC_ALM0
RTC Alarm 0
RTC_ALM1
RTC Alarm 1
RTC_ALM2
RTC Alarm 2
RTC_CNT0
RTC Count 0
RTC_CNT1
RTC Count 1
RTC_CNT2
RTC Count 2
RTC_CR0
RTC Control 0
RTC_CR1
RTC Control 1
RTC_CR2IC
RTC Control 2 for Configuring Input Capture Channels
RTC_CR3OC
RTC Control 3 for Configuring Output Compare Channel
RTC_CR4OC
RTC Control 4 for Configuring Output Compare Channel
RTC_FRZCNT
RTC Freeze Count
RTC_GWY
RTC Gateway
RTC_IC2
RTC Input Capture Channel 2
RTC_IC3
RTC Input Capture Channel 3
RTC_IC4
RTC Input Capture Channel 4
RTC_MOD
RTC Modulo
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–9
ADuCM302x RTC Register Descriptions
Table 20-2:
ADuCM302x RTC Register List (Continued)
Name
Description
RTC_OC1
RTC Output Compare Channel 1
RTC_OC1ARL
RTC Auto-Reload for Output Compare Channel 1
RTC_OC1TGT
RTC Output Compare Channel 1 Target
RTC_OCMSK
RTC Masks for Output Compare Channel
RTC_SNAP0
RTC Snapshot 0
RTC_SNAP1
RTC Snapshot 1
RTC_SNAP2
RTC Snapshot 2
RTC_SR0
RTC Status 0
RTC_SR1
RTC Status 1
RTC_SR2
RTC Status 2
RTC_SR3
RTC Status 3
RTC_SR4
RTC Status 4
RTC_SR5
RTC Status 5
RTC_SR6
RTC Status 6
RTC_TRM
RTC Trim
20–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Alarm 0
RTC_ALM0 contains the lower 16 bits of the non-fractional (that is, prescaled) RTC alarm target time value, where
the overall alarm is defined as {RTC_ALM1, RTC_ALM0} . {RTC_ALM2}
Any write to RTC_ALM0 will pend (that is, stayed execution, with write data held in a staging-post buffer) until
corresponding writes to RTC_ALM1 and RTC_ALM2 are carried out by the CPU, so that the combined 47-bit alarm
redefinition can be executed as a single transaction. RTC_ALM0, RTC_ALM1, and RTC_ALM2 can be written in any
order, but co-ordinated, triple writes (one write to each of the three MMRs) must be carried out by the CPU to have
any effect on the RTC alarm.
Note that RTC_ALM0 can be written to regardless of whether RTC_CR0.ALMEN or RTC_CR0.CNTEN is active.
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
VALUE (R/W)
Lower 16 prescaled (that is, non-fractional)
bits of the RTC alarm target time
Figure 20-2: RTC_ALM0 Register Diagram
Table 20-3:
RTC_ALM0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
Lower 16 prescaled (that is, non-fractional) bits of the RTC alarm target time.
Note that the alarm register has a different reset value to the RTC count to avoid spurious alarms.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–11
ADuCM302x RTC Register Descriptions
RTC Alarm 1
RTC_ALM1 contains the upper 16 bits of the non-fractional (prescaled) RTC alarm target time value, where the
overall alarm is defined as {RTC_ALM1, RTC_ALM0} . {RTC_ALM2}
Any write to RTC_ALM1 will pend (that is, stayed execution, with write data held in a staging-post buffer) until
corresponding writes to RTC_ALM0 and RTC_ALM2 are carried out by the CPU, so that the combined 47-bit alarm
redefinition can be executed as a single transaction. RTC_ALM0, RTC_ALM1, and RTC_ALM2 can be written in any
order, but co-ordinated, triple writes (one write to each of the three MMRs) must be carried out by the CPU to have
any effect on the RTC alarm.
Note that RTC_ALM1 can be written to regardless of whether RTC_CR0.ALMEN or RTC_CR0.CNTEN is active.
15 14 13 12 11 10 9
1
1
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
1
1
1
1
1
1
1
VALUE (R/W)
Upper 16 prescaled (non-fractional)
bits of the RTC alarm target time
Figure 20-3: RTC_ALM1 Register Diagram
Table 20-4:
RTC_ALM1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/W)
20–12
Upper 16 prescaled (non-fractional) bits of the RTC alarm target time.
Note that the alarm register has a different reset value to the RTC count to avoid spurious alarms.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Alarm 2
RTC_ALM2 specifies the fractional (non-prescaled) bits of the RTC alarm target time value, down to an individual
32 kHz clock cycle, where the overall alarm is defined as {RTC_ALM1, RTC_ALM0}. {RTC_ALM2}.
Note that the number of valid bits (which can legitimately have values of one optionally written to them) of
RTC_ALM2 equals the number of prescale bits specified by the RTC_CR1.PRESCALE2EXP field of the RTC_CR1
MMR. If a bit position in RTC_ALM2 is set to one, such that this is incompatible with the
RTC_CR1.PRESCALE2EXP field, the whole value of RTC_ALM2 is treated by the RTC as if it is zero.
Any write to RTC_ALM2 will pend (stayed execution, with write data held in a staging-post buffer) until corresponding writes to RTC_ALM0 and RTC_ALM1 are carried out by the CPU, so that the combined 47-bit alarm redefinition
can be executed as a single transaction. RTC_ALM0, RTC_ALM1, and RTC_ALM2 can be written in any order, but coordinated, triple writes (one write to each of the three MMRs) must be carried out by the CPU to have any effect on
the RTC alarm.
RTC_ALM2 can be written to regardless of whether RTC_CR0.ALMEN or RTC_CR0.CNTEN is active.
Note that in RTC0, a value (typically zero) must still be written to RTC_ALM2 to invoke an alarm time definition
via a triple write to {RTC_ALM1, RTC_ALM0, RTC_ALM2}. This applies even though RTC0 always treats the fractional part of an alarm time as zero.
In contrast, on RTC1, full support for fractional alarm time is present, such that an alarm can be specified down to
an individual 32 kHz clock cycle using RTC_ALM2.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Fractional (non-prescaled) bits of the
RTC alarm target time
Figure 20-4: RTC_ALM2 Register Diagram
Table 20-5:
RTC_ALM2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14:0 VALUE
(R/W)
Fractional (non-prescaled) bits of the RTC alarm target time.
Note that any value written to RTC_ALM2 must be in keeping with the number of prescale bits specified by the RTC_CR1.PRESCALE2EXP field of the RTC_CR1 MMR. If
a value in RTC_ALM2 cannot be reached by the degree of prescaling configured by
RTC_CR1.PRESCALE2EXP, the whole (as opposed to the offending bit positions) of
the value of RTC_ALM2 is treated as if it were zero.
Note that in RTC0, a value (typically zero) must still be written to RTC_ALM2 in order
to invoke an alarm time definition via a triple write to {RTC_ALM1, RTC_ALM0,
RTC_ALM2}. This applies even though RTC0 always treats the fractional part of an
alarm time as zero.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–13
ADuCM302x RTC Register Descriptions
Table 20-5:
RTC_ALM2 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
20–14
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Count 0
RTC_CNT0 contains the lower 16 bits of the RTC counter which maintains a real-time count in elapsed prescaled
RTC time units.
The instantaneous value of RTC_CNT0 can be read back by the CPU. The CPU can also redefine the value in this
register. In this case, the RTC will continue its real-time count from the redefined value.
Any write to RTC_CNT0 will pend until a corresponding write to RTC_CNT1 is carried out by the CPU, so that the
combined 32-bit count redefinition can be executed as a single transaction.
RTC_CNT0 and RTC_CNT1 can be written in either order, but paired, twin writes must be carried out by the CPU to
have any effect on the RTC count. A paired write to RTC_CNT0 and RTC_CNT1 (in whichever order) zeroes the
prescaler in the RTC and thus causes a redefinition of elapsed time by the CPU to align exactly with newly-created
modulo-1 and modulo-60 boundaries.
Such a redefinition also causes the RTC to create a trim boundary and initiate a new trim interval. When the RTC
count is redefined by the CPU, no coincident trim adjustment of the count is carried out.
The RTC supports on-the-fly redefinition of RTC_CNT0 and RTC_CNT1 while RTC_CR0.CNTEN is active. Alternatively, the CPU can disable the RTC (by first taking RTC_CR0.CNTEN inactive) while redefining these registers.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Lower 16 prescaled (non-fractional)
bits of the RTC real-time count
Figure 20-5: RTC_CNT0 Register Diagram
Table 20-6:
RTC_CNT0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
Lower 16 prescaled (non-fractional) bits of the RTC real-time count.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–15
ADuCM302x RTC Register Descriptions
RTC Count 1
RTC_CNT1 contains the upper 16 bits of the RTC counter which maintains a real-time count in elapsed prescaled
RTC time units.
The instantaneous value of RTC_CNT1 can be read back by the CPU. The CPU can also redefine the value in this
register. In this case, the RTC will continue its real-time count from the redefined value.
Any write to RTC_CNT1 will pend until a corresponding write to RTC_CNT0 is carried out by the CPU, so that the
combined 32-bit count redefinition can be executed as a single transaction.
RTC_CNT1 and RTC_CNT0 can be written in either order, but paired, twin writes must be carried out by the CPU to
have any effect on the RTC count. A paired write to RTC_CNT1 and RTC_CNT0 (in whichever order) zeroes the
prescaler in the RTC and thus causes a redefinition of elapsed time by the CPU to align exactly with newly-created
modulo-1 and modulo-60 boundaries.
Such a redefinition also causes the RTC to create a trim boundary and initiate a new trim interval. When the RTC
count is redefined by the CPU, no coincident trim adjustment of the count is carried out.
The RTC supports on-the-fly redefinition of RTC_CNT1 and RTC_CNT0 while RTC_CR0.CNTEN is active. Alternatively, the CPU can disable the RTC (by first taking RTC_CR0.CNTEN inactive) while redefining these registers.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R/W)
Upper 16 prescaled (non-fractional)
bits of the RTC real-time count
Figure 20-6: RTC_CNT1 Register Diagram
Table 20-7:
RTC_CNT1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
Upper 16 prescaled (non-fractional) bits of the RTC real-time count.
(R/W)
20–16
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Count 2
RTC_CNT2 contains the fractional part of the RTC count, where the count is denominated in prescaled time units
and is given by: {RTC_CNT1, RTC_CNT0} . {RTC_CNT2}. The overall resolution of the real-time count, including
the fractional bits in RTC_CNT2, is therefore one 32 kHz clock period.
RTC_CNT2 makes available to the CPU a read-only view of the internal sequence count in the RTC prescaler as it
steps its way (in units of one 32 kHz period) from all zeros to all ones across the number of prescale sequence bits
given by the RTC_CR1.PRESCALE2EXP field of the RTC_CR1 MMR. By completely traversing such a sequence, the
prescaler effectively advances the main (non-fractional) part of the RTC count in {RTC_CNT1, RTC_CNT0} by one
prescaled time unit. The prescale sequence count thus equates to the fractional part of the main RTC count.
Note that the RTC_CNT2 register only exists in RTC1. In RTC0, the fractional part of the RTC count cannot be
read by the CPU.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Fractional bits of the RTC real-time count
Figure 20-7: RTC_CNT2 Register Diagram
Table 20-8:
RTC_CNT2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14:0 VALUE
(R/NW)
Fractional bits of the RTC real-time count.
RTC_CNT2 contains the fractional part of the RTC count, where the count is denomi-
nated in prescaled time units and is given by : {RTCCNT1, RTCCNT0} POINT
{RTCCNT2}. The overall resolution of the real-time count, including the fractional
bits in RTCCNT2, is therefore one 32 kHz clock period.
Note that RTCCNT2 is zeroed whenever any of the following events occurs : (i) the
CPU writes a new pair of values to the RTCCNT1 and RTCCNT0 registers to redefine the elapsed time units count while the RTC is enabled and this posted twin write
is executed; (ii) the CPU enables the RTC from a disabled state using the CNTEN
field of RTCCR0; (iii) while the RTC is enabled, the degree of prescaling in the RTC
is changed via the PRESCALE2EXP field of RTCCR1.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as all zeros.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–17
ADuCM302x RTC Register Descriptions
RTC Control 0
RTC_CR0 is the primary of two control registers for the RTC, the other being RTC_CR1. All mainstream RTC operations are enabled and disabled by the CPU using RTC_CR0.
The RTC_CR1 MMR is a secondary control register which expands the granularity of RTC control which is provided by RTC_CR0.
Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9
0
0
0
0
WPNDINTEN (R/W)
Enable Write Pending sourced interrupts
to the CPU
WSYNCINTEN (R/W)
Enable Write synchronization sourced
interrupts to the CPU
WPNDERRINTEN (R/W)
Enable Write pending error sourced
interrupts to the CPU when an RTC register-write
pending error occurs
ISOINTEN (R/W)
Enable RTC power-domain isolation
sourced interrupts to the CPU when
isolation of the RTC power domain is
activated and subsequently de-activated
0
0
1
8
7
6
5
4
3
2
1
0
1
1
1
0
0
0
1
0
0
CNTEN (R/W)
Global enable for the RTC
ALMEN (R/W)
Enable the RTC alarm (absolute) operation
ALMINTEN (R/W)
Enable sourced alarm interrupts to
the CPU
TRMEN (R/W)
Enable RTC digital trimming
MOD60ALMEN (R/W)
Enable RTC modulo-60 counting of time
past a modulo-60 boundary
MOD60ALMINTEN (R/W)
Enable periodic Modulo-60 RTC alarm
sourced interrupts to the CPU
MOD60ALM (R/W)
Periodic, modulo-60 alarm time in prescaled
RTC time units beyond a modulo-60
boundary
Figure 20-8: RTC_CR0 Register Diagram
20–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-9:
RTC_CR0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 WPNDINTEN
(R/W)
Enable Write Pending sourced interrupts to the CPU.
RTC_CR0.WPNDINTEN is an enable for RTC interrupts to the CPU based on the
RTC_SR0.WPNDINT sticky interrupt source field of the RTCSR0 MMR.
RTC_SR0.WPNDINT is activated whenever a pending slot for an MMR frees up due to
a posted write's being despatched for execution. These slots are drop points for new
posted writes by the CPU. The slots are one deep and there is one slot per MMR.
These slots are used whenever a posted write involves updating either a whole MMR
or some its bit fields which are sourced in the slower 32 kHz clock domain.
Note the distinction between the WPEND status and the WSYNC status of an MMR.
The former indicates whether the RTC can accept a new posted write by the CPU to
an MMR, whereas the latter indicates whether the effects of a posted write to an MMR
are subsequently visible to the CPU. See RTC_SR0.WSYNCINT and
RTC_SR0.WPNDINT fields for more details.
0 Disable RTC_SR0.WPNDINT-sourced interrupts to the
CPU.
1 Enable RTC_SR0.WPNDINT-sourced interrupts to the
CPU.
14 WSYNCINTEN
(R/W)
Enable Write synchronization sourced interrupts to the CPU.
RTC_CR0.WSYNCINTEN is an enable for RTC interrupts to the CPU based on the
RTC_SR0.WSYNCINT sticky interrupt source field of the RTCSR0 MMR.
RTC_SR0.WSYNCINT is activated whenever the effects of a posted write to a 32 kHz
sourced MMR or MMR bit field becomes visible to the CPU. The delay between the
posting and being able to see the results of the transaction is due to the queuing time
behind other posted transactions plus the synchronization time between clock domains
when the posted write is actually executed.
Note the distinction between the WPEND status and the WSYNC status of an MMR.
The former indicates whether the RTC can accept a new posted write by the CPU to
an MMR, whereas the latter indicates whether the effects of a posted write to an MMR
are subsequently visible to the CPU. See RTC_SR0.WSYNCINT and
RTC_SR0.WPNDINT fields for more details.
0 Disable RTC_SR0.WSYNCINT-sourced interrupts to the
CPU.
1 Enable RTC_SR0.WSYNCINT-sourced interrupts to the
CPU.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–19
ADuCM302x RTC Register Descriptions
Table 20-9:
RTC_CR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
13 WPNDERRINTEN
(R/W)
Enable Write pending error sourced interrupts to the CPU when an RTC registerwrite pending error occurs.
Write pending errors happen if the CPU tries to countermand a register write which is
already pending but has not yet been despatched for execution. In such circumstances,
the RTC rejects the CPU's attempt to write a new value to the register. The pending
write is executed instead when its turn arrives in the transaction queue. This queue
operates on a first-in first-out basis.
A maximum of one pending write transaction per memory-mapped register is supported by the RTC. These writes are carried out in the order in which they are received by
the RTC. Register writes take time to come to the front of the queue for despatch and
then to actually execute because of the difference in frequencies and synchronization
between the core clock domain and the much slower 32 kHz domain within the RTC.
Write pending errors, in which the RTC rejects an attempt by the CPU to post a write
when there is no room to receive it, can be avoided by the CPU by first checking the
pending status of a register in RTC_SR1 before undertaking a write to that register.
Should a RTC_SR0.WPNDERRINT error occur, the RTC will interrupt the CPU if
RTC_CR0.WPNDERRINTEN enables this course of action.
Note the distinction between the WPEND status and the WSYNC status of an MMR.
The former indicates whether the RTC can accept a new posted write by the CPU to
an MMR, whereas the latter indicates whether the effects of a posted write to an MMR
are subsequently visible to the CPU. See RTC_SR0.WSYNCINT and
RTC_SR0.WPNDINT fields for more details.
0 Don't enable interrupts if write pending errors occur in
the RTC.
1 Enable interrupts for write pending errors in the RTC.
20–20
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-9:
RTC_CR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12 ISOINTEN
(R/W)
Enable RTC power-domain isolation sourced interrupts to the CPU when isolation of
the RTC power domain is activated and subsequently de-activated.
RTC_CR0.ISOINTEN enables interrupts to the CPU based on the RTC_SR0.ISOINT
sticky interrupt source in the RTC_SR0 status register.
When power loss is imminent to all power domains on the device apart from the RTC,
the RTC activates its isolation barrier so that it can continue to operate independently
of the core. When power is subsequently restored to the rest of the device, the RTC
activates the RTC_SR0.ISOINT interrupt source to act as a sticky record of the power
loss event just finishing. This activation occurs as the RTC lowers its isolation barrier
once it knows that the core has regained power.
If enabled by RTC_CR0.ISOINTEN, the RTC will interrupt the CPU based on
RTC_SR0.ISOINT. The CPU can then inspect the RTC_SR0.ISOINT field to discover that it (the CPU) has recovered from a total loss of power.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable RTC_SR0.ISOINT-sourced interrupts to the
CPU.
1 Enable RTC_SR0.ISOINT-sourced interrupts to the
CPU.
11 MOD60ALMINTEN
(R/W)
Enable periodic Modulo-60 RTC alarm sourced interrupts to the CPU.
RTC_CR0.MOD60ALMINTEN allows the CPU to enable a periodic, repeating interrupt
from the RTC at a displacement time in RTC time units given by
RTC_CR0.MOD60ALM beyond a modulo-60 boundary.
Note that for such interrupts to occur, the detection of an alarm time beyond a modulo-60 boundary must first be enabled using RTC_CR0.MOD60ALMEN. Once such an
event has been detected and stickily recorded, the value of
RTC_CR0.MOD60ALMINTEN controls whether an interrupt is issued by the RTC for
that event.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable periodic interrupts due to modulo-60 RTC
elapsed time.
1 Enable periodic interrupts due to modulo-60 RTC
elapsed time.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–21
ADuCM302x RTC Register Descriptions
Table 20-9:
RTC_CR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10:5 MOD60ALM
(R/W)
Periodic, modulo-60 alarm time in prescaled RTC time units beyond a modulo-60
boundary.
RTC_CR0.MOD60ALM allows the CPU to position a periodic (repeating) alarm inter-
rupt from the RTC at any integer number of prescaled RTC time units from a modulo-60 boundary (roll-over event) of the value in {RTC_CNT1, RTC_CNT0}.
Boundaries are defined in the following way. The RTC realigns itself to create coincident modulo-60 and modulo-1 (where modulo-1 is an ordinary count increment
event) boundaries whenever any of the following events occurs: (i) the CPU writes a
new pair of values to the RTC_CNT1and RTC_CNT0 registers to redefine the elapsed
time units count while the RTC is enabled and this posted twin write is executed (ii)
the CPU enables the RTC from a disabled state using the RTC_CR0.CNTEN field (iii)
while the RTC is enabled by RTCEN, the degree of prescaling in the RTC is changed
via the RTC_CR1.PRESCALE2EXP field.
Values of 0 to 59 are allowed for MOD60ALM. If a greater value is configured, this
will be treated as zero prescaled RTC time units.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as all zeros.
30 Example of setting a modulo-60 periodic interrupt from
the RTC to be issued to the CPU at 30 time units past a
modulo-60 boundary.
55 Example of setting a modulo-60 periodic interrupt from
the RTC to be issued to the CPU at 55 time units past a
modulo-60 boundary.
4 MOD60ALMEN
(R/W)
Enable RTC modulo-60 counting of time past a modulo-60 boundary.
RTC_CR0.MOD60ALMEN enables the RTC to detect and record until cleared by the
CPU the periodic interrupt condition of RTC_CNT1 and RTC_CNT0 having reached
RTC_CR0.MOD60ALM number of prescaled RTC time units past a modulo-60 boundary.
Note that RTC_CR0.MOD60ALMEN enables the detection of this condition, whereas
RTC_CR0.MOD60ALMINTEN enables the generation of a resultant interrupt.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable determination of modul0-60 RTC elapsed time.
1 Enable determination of modulo-60 RTC elapsed time.
20–22
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-9:
RTC_CR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 TRMEN
(R/W)
Enable RTC digital trimming.
Trimming of the RTC allows the real-time count in prescaled RTC time units to be
adjusted on a periodic basis to track time with better accuracy. RTC_CR0.TRMEN enables this adjustment, provided the RTC is enabled via RTC_CR0.CNTEN.
The exact nature of the trim (period, number of prescaled RTC time units to be added
or subtracted) is defined in the RTC_TRM register.
Note that if RTC_CR0.TRMEN is activated from a disabled state while
RTC_CR0.CNTEN is also active, this will cause a trim interval boundary to occur and a
new trim interval will begin. No trim adjustment of the RTC count occurs on such
RTC_CR0.TRMEN activation. A whole, enabled trim interval must have elapsed before
any adjustment is made.
0 Digital trimming of the RTC count value is disabled.
1 Trim is enabled.
2 ALMINTEN
(R/W)
Enable sourced alarm interrupts to the CPU.
RTC_CR0.ALMINTEN gives the CPU extra control over whether an alarm event (alarm
count matches the RTC count) should trigger an interrupt. Under normal conditions,
RTC_CR0.ALMINTEN is set active, most notably when the detection of an alarm condition is enabled by RTC_CR0.ALMEN.
Note that if RTC_CR0.ALMINTEN is active (alarm interrupts enabled) but the alarm
itself is disabled (RTC_CR0.ALMEN inactive), no interrupts will occur.
0 Disable alarm interrupts.
1 Enable an interrupt if RTC alarm and count values
match.
1 ALMEN
(R/W)
Enable the RTC alarm (absolute) operation.
RTC_CR0.ALMEN must be set active for the alarm logic to function and for any alarm
event to be detected. Such an event is defined as a match between the values of the
RTC count and alarm registers, namely RTC_CNT1, RTC_CNT0, RTC_CNT2,
RTC_ALM1, RTC_ALM0 and RTC_ALM2.
Count and alarm values and match conditions are all defined on a 47-bit basis, although the constituent registers are individually 16 bits wide.
When enabled by RTC_CR0.ALMEN, the detection of an alarm event is held in the
sticky interrupt source bit field, RTC_SR0.ALMINT. Note that for alarm detection to
function and be controlled by RTC_CR0.ALMEN, the overriding RTC_CR0.CNTEN
global enable for the RTC must also be active.
0 Disable detection of alarm events.
1 Enable detection of alarm events.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–23
ADuCM302x RTC Register Descriptions
Table 20-9:
RTC_CR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 CNTEN
(R/W)
Global enable for the RTC.
RTC_CR0.CNTEN enables counting of elapsed real time and acts as a master enable for
the RTC.
Note that if the RTC is disabled via RTC_CR0.CNTEN, no time is counted, no alarm
or modulo-60 interrupt conditions are detected, no alarm or modulo-60 interrupts are
issued and no trimming occurs. However, all interrupt sources can be cleared by the
CPU irrespective of the value of CNTEN.
If the RTC is enabled by activating RTC_CR0.CNTEN , this event causes a realignment
of the prescaler, the trim interval and the modulo-60 counter used by the RTC to generate RTC_SR0.MOD60ALMINT-sourced interrupts. The RTC initiates a modulo-1
boundary, a modulo-60 boundary and a new trim interval whenever RTC_CR0.CNTEN
is activated. No trim adjustment to the RTC count is made when RTC_CR0.CNTEN is
activated from a disabled state.
0 Disable the RTC.
1 Enable the RTC.
20–24
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Control 1
RTC_CR1 register expands the granularity of RTC control which is already available via RTC_CR0.
RTC_CR1 allows additional sticky interrupt sources in RTC_SR2 to be enabled. These sources fan into the RTC pe-
ripheral interrupt to optionally tell the CPU when (i) the RTC count has changed, (ii) a prescaled (modulo-1) gated-clock event has occurred to advance the RTC count, (iii) a trim boundary (and thus trimming) has occurred, (iv)
the 32-bit RTC count in {RTC_CNT1, RTC_CNT0} has rolled over and (v) the modulo-60 version of the RTC count
has rolled over.
Note that RTC_CR1 is only configurable in RTC1, whereas in RTC0 it is a read-only register with fixed (reset) settings.
Nonetheless, if the CPU attempts to write to RTC_CR1 on RTC0, the write is accepted and enqueued for execution
with normal RTC_SR2.WPNDCR1MIR and RTC_SR2.WSYNCCR1MIR indications, as on RTC1, in terms of the
progress of the posted write. However, because the bit fields in RTC_CR1 on RTC0 are read-only, such a write, when
executed, has no effect.
In contrast, full write configurability of RTC_CR1 is supported on RTC1.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
PRESCALE2EXP (R/W)
Prescale power of 2 division factor for
the RTC base clock
8
7
6
5
4
3
2
1
0
1
1
1
1
0
0
0
0
0
CNTINTEN (R/W)
Enable for the RTC count interrupt source
PSINTEN (R/W)
Enable for the prescaled, modulo-1
interrupt source
CNTMOD60ROLLINTEN (R/W)
Enable for the RTC modulo-60 count
roll-over interrupt source in RTC Status
2 Register
RTCTRMINTEN (R/W)
Enable for the RTC Trim interrupt source
CNTROLLINTEN (R/W)
Enable for the RTC count roll-over interrupt
source in RTC Status 2 Register
Figure 20-9: RTC_CR1 Register Diagram
Table 20-10:
RTC_CR1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
8:5 PRESCALE2EXP
(R/W)
Prescale power of 2 division factor for the RTC base clock.
RTC_CR1.PRESCALE2EXP defines the power of two by which the RTC base clock
(nominally 32 kHz) is prescaled (divided in frequency) before being used to count
time by advancing the contents of the {RTC_CNT1, RTC_CNT0} MMRs.
Note that this bit field is only configurable in RTC1. In RTC0, the field is read-only
and contains a value of 0xF, signifying a fixed prescaling of 2 to the power of 15. This
is because RTC0 always counts real time at 1Hz.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–25
ADuCM302x RTC Register Descriptions
Table 20-10:
RTC_CR1 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
In contrast, RTC1 can prescale the clock by any power of two in the interval [15,0] to
use as its time base.
0 Prescale the RTC base clock by 2^0 = 1.
1 Prescale the RTC base clock by 2^1 = 2.
2 Prescale the RTC base clock by 2^2 = 4.
3 Prescale the RTC base clock by 2^3 = 8.
4 Prescale the RTC base clock by 2^4 = 16.
5 Prescale the RTC base clock by 2^5 = 32.
6 Prescale the RTC base clock by 2^6 = 64.
7 Prescale the RTC base clock by 2^7 = 128.
8 Prescale the RTC base clock by 2^8 = 256.
9 Prescale the RTC base clock by 2^9 = 512.
10 Prescale the RTC base clock by 2^10 = 1024.
11 Prescale the RTC base clock by 2^11 = 2048.
12 Prescale the RTC base clock by 2^12 = 4096.
13 Prescale the RTC base clock by 2^13 = 8192.
14 Prescale the RTC base clock by 2^14 = 16384.
15 Prescale the RTC base clock by 2^15 = 32768.
4 CNTMOD60ROLLINT(R/W) EN
Enable for the RTC modulo-60 count roll-over interrupt source in RTC Status 2 Register.
This bit field only exists in RTC1. In RTC0, the field is reserved and reads back as
zero.
0 Disable RTC_SR2.CNTMOD60ROLLINT as a fan-in
term of the RTC peripheral interrupt.
1 Enable RTC_SR2.CNTMOD60ROLLINT as a fan-in term
of the RTC peripheral interrupt.
3 CNTROLLINTEN
(R/W)
Enable for the RTC count roll-over interrupt source in RTC Status 2 Register.
This bit field only exists in RTC1. In RTC0, the field is reserved and reads back as
zero.
0 Disable RTC_SR2.CNTROLLINT as a fan-in term of the
RTC peripheral interrupt.
1 Enable RTC_SR2.CNTROLLINT as a fan-in term of the
RTC peripheral interrupt.
20–26
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-10:
RTC_CR1 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 RTCTRMINTEN
(R/W)
Enable for the RTC Trim interrupt source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable RTC_SR2.TRMINT as a fan-in term of the RTC
peripheral interrupt.
1 Enable RTC_SR2.TRMINT as a fan-in term of the RTC
peripheral interrupt.
1 PSINTEN
(R/W)
Enable for the prescaled, modulo-1 interrupt source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable RTC_SR2.PSINT as a fan-in term of the RTC
peripheral interrupt.
1 Enable RTC_SR2.PSINT as a fan-in term of the RTC
peripheral interrupt.
0 CNTINTEN
(R/W)
Enable for the RTC count interrupt source.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 Disable RTC_SR2.CNTINT as a fan-in term of the RTC
peripheral interrupt.
1 Enable RTC_SR2.CNTINT as a fan-in term of the RTC
peripheral interrupt.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–27
ADuCM302x RTC Register Descriptions
RTC Control 2 for Configuring Input Capture Channels
RTC_CR2IC is a control register for configuring enables related to input-capture channels. RTC_CR2IC contains en-
ables for both the input-capture function itself for each channel, as well as enables for whether an event on a channel
should contribute to the interrupt lines from the RTC to both the CPU and the wake-up controller. Note that this
register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
1
0
0
0
0
0
RTCICOWUSEN (R/W)
Enable Overwrite of Unread Snapshots
for all RTC Input Capture Channels
RTCIC4IRQEN (R/W)
Interrupt Enable for the RTC Input Capture
Channel 4
1
8
7
6
5
4
3
2
1
0
1
1
0
1
0
0
0
0
0
RTCIC0EN (R/W)
Enable for the RTC Input Capture Channel 0
RTCIC2EN (R/W)
Enable for the RTC Input Capture Channel 2
RTCIC3EN (R/W)
Enable for the RTC Input Capture Channel 3
RTCIC3IRQEN (R/W)
Interrupt Enable for the RTC Input Capture
Channel 3
RTCIC4EN (R/W)
Enable for the RTC Input Capture Channel 4
RTCIC2IRQEN (R/W)
Interrupt Enable for the RTC Input Capture
Channel 2
RTCIC0LH (R/W)
Polarity of the active-going capture
edge for the RTC Input Capture Channel 0
RTCIC0IRQEN (R/W)
Interrupt Enable for the RTC Input Capture
Channel 0
RTCIC2LH (R/W)
Polarity of the active-going capture
edge for the RTC Input Capture Channel 2
RTCIC4LH (R/W)
Polarity of the active-going capture
edge for the RTC Input Capture Channel 4
RTCIC3LH (R/W)
Polarity of the active-going capture
edge for the RTC Input Capture Channel 3
Figure 20-10: RTC_CR2IC Register Diagram
20–28
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-11:
RTC_CR2IC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 RTCICOWUSEN
(R/W)
Enable Overwrite of Unread Snapshots for all RTC Input Capture Channels.
RTC_CR2IC.RTCICOWUSEN controls whether snapshots for input capture channels
are automatically overwritten whenever a new capture event occurs, even if a previously-captured snapshot has not yet been read by the CPU. By default,
RTC_CR2IC.RTCICOWUSEN is enabled, which means that input capture events always
cause a new snapshot value to be taken for the channel in question. In other words, an
input capture event causes a snapshot overwrite.
If RTC_CR2IC.RTCICOWUSEN is de-activated to 1'b0, the sticky persistence of snapshots for all input capture channels is extended, such that the snapshot will stick and
will not be overwritten, even for a new input capture event on that channel, until the
snapshot has been read by the CPU. Such persistence is on a per-channel basis.
Snapshots for all input capture channels are thus independently persistent until they
are read.
In summary, when RTC_CR2IC.RTCICOWUSEN is 1'b1, the snapshots for all input
capture channels relate to the most recent capture event on each channel. In contrast,
when RTC_CR2IC.RTCICOWUSEN is 1'b0, the snapshots reflect the first-occurring
capture event, per channel, since the CPU last read a snapshot for that particular channel.
0 Snapshots for input capture channels are independently,
stickily persistent until first read and then subject to a
capture event. Overwrites of unread snapshots are not
enabled.
1 Snapshots for input capture channels independently and
stickily persist until new capture events occur. Overwrites of unread snapshots are enabled.
14 RTCIC4IRQEN
(R/W)
Interrupt Enable for the RTC Input Capture Channel 4.
RTC_CR2IC.RTCIC4IRQEN, active high, determines whether the sticky interrupt
source RTC_SR3.RTCIC4IRQ is enabled to fan in as a contributory term to the RTC
IRQ interrupt line to the CPU.
0 Disable RTC_SR3.RTCIC4IRQ from contributing to
the RTC interrupts to both the CPU and the wake-up
controller.
1 Enable RTC_SR3.RTCIC4IRQ as a contributory fan-in
term to the RTC interrupts to both the CPU and the
wake-up controller.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–29
ADuCM302x RTC Register Descriptions
Table 20-11:
RTC_CR2IC Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
13 RTCIC3IRQEN
(R/W)
Interrupt Enable for the RTC Input Capture Channel 3.
RTC_CR2IC.RTCIC3IRQEN, active high, determines whether the sticky interrupt
source RTC_SR3.RTCIC3IRQ is enabled to fan in as a contributory term to the RTC
IRQ interrupt line to the CPU.
0 Disable RTC_SR3.RTCIC3IRQ from contributing to
the RTC interrupts to both the CPU and the wake-upcontroller.
1 Enable RTC_SR3.RTCIC3IRQ as a contributory fan-in
term to the RTC interrupts to both the CPU and the
wake-up controller.
12 RTCIC2IRQEN
(R/W)
Interrupt Enable for the RTC Input Capture Channel 2.
RTC_CR2IC.RTCIC2IRQEN, active high, determines whether the sticky interrupt
source RTC_SR3.RTCIC2IRQ is enabled to fan in as a contributory term to the RTC
IRQ interrupt line to the CPU.
0 Disable RTC_SR3.RTCIC2IRQ from contributing to
the RTC interrupts to both the CPU and the wake-up
controller.
1 Enable RTC_SR3.RTCIC2IRQ as a contributory fan-in
term to the RTC interrupts to both the CPU and the
wake-up controller.
10 RTCIC0IRQEN
(R/W)
Interrupt Enable for the RTC Input Capture Channel 0.
RTC_CR2IC.RTCIC0IRQEN, active high, determines whether the sticky interrupt
source RTC_SR3.RTCIC0IRQ enabled to fan in as a contributory term to the RTC
IRQ interrupt line to the CPU.
0 Disable RTC_SR3.RTCIC0IRQ from contributing to
the RTC interrupt to the CPU.
1 Enable RTC_SR3.RTCIC0IRQ as a contributory fan-in
term to the RTC interrupt to the CPU.
9 RTCIC4LH
(R/W)
Polarity of the active-going capture edge for the RTC Input Capture Channel 4.
RTC_CR2IC.RTCIC4LH selects whether an input capture event on the RTC_IC4
channel is defined as a low-to-high (LH) or high-to-low transition of the GPIO input
for that channel.
0 The RTC_IC4 channel uses a high-to-low transition on
its GPIO pin to signal an input capture event.
1 The RTC_IC4 channel uses a low-to-high transition on
its GPIO pin to signal an input capture event.
20–30
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-11:
RTC_CR2IC Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
8 RTCIC3LH
(R/W)
Polarity of the active-going capture edge for the RTC Input Capture Channel 3.
RTC_CR2IC.RTCIC3LH selects whether an input capture event on the RTC_IC3
channel is defined as a low-to-high (LH) or high-to-low transition of the GPIO input
for that channel.
0 The RTC_IC3 channel uses a high-to-low transition on
its GPIO pin to signal an input capture event.
1 The RTC_IC3 channel uses a low-to-high transition on
its GPIO pin to signal an input capture event.
7 RTCIC2LH
(R/W)
Polarity of the active-going capture edge for the RTC Input Capture Channel 2.
RTC_CR2IC.RTCIC2LH selects whether an input capture event on the RTC_IC2
channel is defined as a low-to-high (LH) or high-to-low transition of the GPIO input
for that channel.
0 The RTC_IC2 channel uses a high-to-low transition on
its GPIO pin to signal an input capture event.
1 The RTC_IC2 channel uses a low-to-high transition on
its GPIO pin to signal an input capture event.
5 RTCIC0LH
(R/W)
Polarity of the active-going capture edge for the RTC Input Capture Channel 0.
RTC_CR2IC.RTCIC0LH selects whether an input capture event on the RTC_IC0
channel is defined as a low-to-high (LH) or high-to-low transition of the GPIO input
for that channel.
0 The RTC_IC0 channel uses a high-to-low transition on
its GPIO pin to signal an input capture event.
1 The RTC_IC0 channel uses a low-to-high transition on
its GPIO pin to signal an input capture event.
4 RTCIC4EN
(R/W)
Enable for the RTC Input Capture Channel 4.
RTC_CR2IC.RTCIC4EN, active high, is a global enable for the Input Capture 4 channel (externally-prompted snapshot), RTC_IC4.
0 Disable the 16-bit input-capture channel RTC_IC4.
1 Enable the 16-bit input-capture channel RTC_IC4.
3 RTCIC3EN
(R/W)
Enable for the RTC Input Capture Channel 3.
RTC_CR2IC.RTCIC3EN, active high, is a global enable for the Input Capture 3 channel (externally-prompted snapshot), RTC_IC3.
0 Disable the 16-bit input-capture channel RTC_IC3.
1 Enable the 16-bit Input-capture channel RTC_IC3.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–31
ADuCM302x RTC Register Descriptions
Table 20-11:
RTC_CR2IC Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 RTCIC2EN
(R/W)
Enable for the RTC Input Capture Channel 2.
RTC_CR2IC.RTCIC2EN, active high, is a global enable for the Input Capture 2 channel (externally-prompted snapshot), RTC_IC2.
0 Disable the 16-bit input-capture channel RTC_IC2.
1 Enable the 16-bit input-capture channel RTC_IC2.
0 RTCIC0EN
(R/W)
Enable for the RTC Input Capture Channel 0.
RTC_CR2IC.RTCIC0EN, active high, is a global enable for the RTC_IC0 functionali-
ty related only to GPIO prompting of input capture into the 47-bit snapshot registers
{RTC_SNAP1, RTC_SNAP0} binary point {RTC_SNAP2}. Note that
RTC_CR2IC.RTCIC0EN has no effect on CPU-originated snapshots, which are
prompted by a write of the specific key value of 0x7627 to the RTC_GWY register.
0 Disable externally-requested (GPIO, non-CPU) snapshots for the 47-bit input-capture channel RTC_IC0.
1 Enable externally-requested (GPIO, non-CPU) snapshots for the 47-bit input-capture channel RTC_IC0.
20–32
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Control 3 for Configuring Output Compare Channel
RTC_CR3OC is a control register for configuring enables related to 16-bit output-compare channel. RTC_CR3OC
contains enables for both the output-compare function itself for each channel, as well as enables for whether an
event on a channel should contribute to the interrupt lines from the RTC to both the CPU and the wake-up controller. Note that the 47-bit RTC_OC0 channel is not controlled by RTC_CR3OC. This is because RTCOC0 is a
synonym for the main 47-bit RTC alarm (whose interrupt source is ALMINT), which is controlled by the
RTC_CR0.ALMEN and RTC_CR0.ALMINTEN fields Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
RTCOC1IRQEN (R/W)
Interrupt Enable for Output Compare
Channel 1
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCOC1EN (R/W)
Enable for Output Compare Channel 1
Figure 20-11: RTC_CR3OC Register Diagram
Table 20-12:
RTC_CR3OC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9 RTCOC1IRQEN
(R/W)
Interrupt Enable for Output Compare Channel 1.
RTC_CR3OC.RTCOC1IRQEN, active high, determines whether the sticky interrupt
source RTC_SR3.RTCOC1IRQ is enabled to fan in as a contributory term to the RTC
IRQ interrupt lines to both the CPU and the wake-up controller.
0 Disable RTC_SR3.RTCOC1IRQ from contributing to
the RTC interrupts to both the CPU and the wake-up
controller.
1 Enable RTC_SR3.RTCOC1IRQ as a contributory fan-in
term to the RTC interrupts to both the CPU and the
wake-up controller.
1 RTCOC1EN
(R/W)
Enable for Output Compare Channel 1.
RTC_CR3OC.RTCOC1EN, active high, is a global enable for the output-compare channel (scheduled alarm), RTC_OC1.
0 Disable the 16-bit output-compare channel RTC_OC1.
1 Enable the 16-bit output-compare channel RTC_OC1.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–33
ADuCM302x RTC Register Descriptions
RTC Control 4 for Configuring Output Compare Channel
RTC_CR4OC is a control register for configuring enables related to masking and auto-reloading of the 16-bit outputcompare channel RTC_OC1. Note that this register only exists in RTC1. In RTC0, the register address is reserved
and reads back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
RTCOC1ARLEN (R/W)
Enable for auto-reloading when output
compare match occurs
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCOC1MSKEN (R/W)
Enable for thermometer-code masking
of the Output Compare 1 Channel
Figure 20-12: RTC_CR4OC Register Diagram
Table 20-13:
RTC_CR4OC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9 RTCOC1ARLEN
(R/W)
Enable for auto-reloading when output compare match occurs.
If auto-reloading of RTC_OC1 is enabled via RTC_CR4OC.RTCOC1ARLEN, the contents of RTC_OC1ARL are added, modulo 16, to the value of RTC_OC1 whenever an
optionally masked match occurs for the output compare channel RTC_OC1.
This is expressed as RTC_OC1 = RTC_CR4OC.RTCOC1ARLEN ? RTC_OC1 +
RTC_OC1ARL : RTC_OC1 In such circumstances, RTC_OC1 acts as a repeating alarm,
whereby those bits which are not masked in the reload value effectively define the step
size (offset) from the current time to the next output compare alarm.
0 Disable auto-reloading of RTC_OC1 and instead maintain its target value whenever an enabled output compare event occurs on that channel.
1 Enable auto-reloading of RTC_OC1 from RTC_OC1ARL
whenever an enabled output compare event occurs on
that channel.
20–34
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-13:
RTC_CR4OC Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 RTCOC1MSKEN
(R/W)
Enable for thermometer-code masking of the Output Compare 1 Channel.
RTC_CR4OC.RTCOC1MSKEN is used to optionally enable masking of matches between
RTC_OC1 and RTC count, when determining whether a scheduled alarm should be activated for Output Compare Channel 1 RTC_OC1. When enabled via
RTC_CR4OC.RTCOC1MSKEN, a four-bit code, embedded in RTC_OCMSK, is decoded
out to a 16-bit thermometer-code mask and applied to bit positions in both RTC_OC1
and 16 least significant {integer, fractional} bits with meaning (bearing in mind prescaling) in the lower end of the RTC count given by {RTC_CNT0, RTC_CNT2}.
0 Do not apply a mask to the 16-bit Output Compare
channel RTC_OC1.
1 Apply a thermometer-decoded mask to the 16-bit Output Compare channel RTC_OC1 provided that channel
is enabled via RTC_CR3OC.RTCOC1EN
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–35
ADuCM302x RTC Register Descriptions
RTC Freeze Count
RTC Freeze Count MMR allows a coherent, triple 16-bit read of the 47-bit RTC count contained in {RTC_CNT2,
RTC_CNT1, RTC_CNT0}.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCFRZCNT (R)
RTC Freeze Count
Figure 20-13: RTC_FRZCNT Register Diagram
Table 20-14:
RTC_FRZCNT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RTCFRZCNT
(R/NW)
RTC Freeze Count.
The RTC Freeze Count MMR allows a coherent, triple 16-bit read of the 47-bit RTC
count contained in RTC_CNT2, RTC_CNT1, RTC_CNT0.
RTC_FRZCNT.RTCFRZCNT is always read in sequences of three reads (though these
can be spread out in time, or have other APB accesses interspersed), such that the first
read in the sequence returns the current value of RTC_CNT0. Simultaneously, with this
first read, a snapshot is taken and frozen of the value of {RTC_CNT2, RTC_CNT1} so
that in the second and third reads in the sequence of RTC_FRZCNT.RTCFRZCNT, the
snapshot values of RTC_CNT2 and RTC_CNT1 are returned respectively.
In this way, a triple read of RTC_FRZCNT.RTCFRZCNT gives an overall 47 bits of the
RTC count which belong together and are coherent with each other, even though during this RTC_FRZCNT.RTCFRZCNT read-out sequence, the actual (continuing) value
of {RTC_CNT2, RTC_CNT1, RTC_CNT0} keeps advancing while the RTC counts real
time.
The RTC_SR6.RTCFRZCNTPTR pointer MMR field of RTCSR6 both indicates the
sequence number in the triple read and also acts a read data select for the value returned when RTC_FRZCNT.RTCFRZCNT is read. Normally, the
RTC_SR6.RTCFRZCNTPTR pointer keeps advancing by one, starting from 2'b00, with
every read of RTC_FRZCNT.RTCFRZCNT, wrapping from 2'b10 to 2'b00.
However, if the CPU wishes to zero the RTC_SR6.RTCFRZCNTPTR pointer and thus
re-initialize the 0-1-2 sequence for reads of RTC_FRZCNT.RTCFRZCNT, the CPU can
do this by writing a software key, RTC_SW_RTCFRZCNT_KEY, of value 16'h9376,
to the RTC_GWY gateway MMR.
20–36
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Gateway
RTC_GWY is a gateway MMR address through which the CPU can order actions to be taken within the RTC. The
CPU does this by writing specific keys to RTC_GWY. Note that RTC_GWY reads back as all zeros.
The RTC supports the following independent, software-keyed commands :(i) Cancel all posted and executing write transactions in the RTC with immediate effect.
(ii) Capture a sticky snapshot of the {RTC_CNT1, RTC_CNT0, RTC_CNT2} MMRs into {RTC_SNAP1, RTC_SNAP0,
RTC_SNAP2}.
(iii) Zero the RTC_SR6.RTCFRZCNTPTR pointer and re-initialize a 0-1-2 sequence for reads of
RTC_FRZCNT.RTCFRZCNT.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SWKEY (W)
Software-keyed command issued by
the CPU
Figure 20-14: RTC_GWY Register Diagram
Table 20-15:
RTC_GWY Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 SWKEY
(RX/W)
Software-keyed command issued by the CPU.
The RTC_GWY MMR is the write target for activating software-keyed commands issued by the CPU to the RTC.Details of the supported keys are as follows :(i) A FLUSH_RTC software key (delivered via a register write to RTC_GWY) of value
0xa2c5 causes the RTC to flush (discard) all posted write transactions and to immediately stop any transaction that is currently executing. It is envisaged that this key
would only be used by the CPU when power loss to the core is imminent and the
CPU wants to cleanly and quickly terminate communication activity across the RTC's
power domain boundary before the always-on half of the RTC activates its isolation
barrier.
(ii) A SNAPSHOT_RTC key of value 0x7627 (delivered via a register write to
RTC_GWY) causes the RTC to take a sticky snapshot of the value of {RTC_CNT1,
RTC_CNT0, RTC_CNT2} and store it in {RTC_SNAP1, RTC_SNAP0, RTC_SNAP2}.
Snapshots are sticky (persistent) until a new one is requested.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–37
ADuCM302x RTC Register Descriptions
RTC Input Capture Channel 2
RTC_IC2 is a read-only snapshot of the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit
RTC count at the most recent event on input capture channel 2. Note that this register only exists in RTC1. In
RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCIC2 (R)
RTC Input Capture Channel 2
Figure 20-15: RTC_IC2 Register Diagram
Table 20-16:
RTC_IC2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RTCIC2
(R/NW)
RTC Input Capture Channel 2.
It is a read-only snapshot of the 16 least significant {integer, fractional} bits with meaning in the lower end of the RTC count given by {RTC_CNT0, RTC_CNT2}, taking account of prescaling. A snaphot of RTC time is placed with this alignment into
RTC_IC2.RTCIC2 when prompted to do so by an external requesting input into the
RTC on input capture channel 2. Such an event overwrites any value captured previously in RTC_IC2.RTCIC2.
Note that the RTC_IC2.RTCIC2 input capture channel function itself is enabled by
RTC_CR2IC.RTCIC2EN. In addition, if enabled by RTC_CR2IC.RTCIC2IRQEN, the
RTC can also issue an optional interrupt to the CPU upon an input capture event on
RTC_IC2.RTCIC2.
20–38
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Input Capture Channel 3
RTC_IC3is a read-only snapshot of the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit
RTC count at the most recent event on input capture channel 3. Note that this register only exists in RTC1. In
RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCIC3 (R)
RTC Input Capture Channel 3
Figure 20-16: RTC_IC3 Register Diagram
Table 20-17:
RTC_IC3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RTCIC3
(R/NW)
RTC Input Capture Channel 3.
It is a read-only snapshot of the 16 least significant {integer, fractional} bits with meaning in the lower end of the RTC count given by {RTC_CNT0, RTC_CNT2}, taking account of prescaling. A snaphot of RTC time is placed with this alignment into
RTC_IC3 when prompted to do so by an external requesting input into the RTC on
input capture channel 3. Such an event overwrites any value captured previously in
RTC_IC3.
Note that the RTC_IC3 input capture channel function itself is enabled by
RTC_CR2IC.RTCIC3EN. In addition, if enabled by RTC_CR2IC.RTCIC3IRQEN, the
RTC can also issue an optional interrupt to the CPU upon an input capture event on
RTC_IC3.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–39
ADuCM302x RTC Register Descriptions
RTC Input Capture Channel 4
RTC_IC4 is a read-only snapshot of the 16 lowest {integer_bits, fractional_bits} with meaning of the main 47-bit
RTC count at the most recent event on input capture channel 4. Note that this register only exists in RTC1. In
RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCIC4 (R)
RTC Input Capture Channel 4
Figure 20-17: RTC_IC4 Register Diagram
Table 20-18:
RTC_IC4 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RTCIC4
(R/NW)
RTC Input Capture Channel 4.
It is a read-only snapshot of the 16 least significant {integer, fractional} bits with meaning in the lower end of the RTC count given by {RTC_CNT0, RTC_CNT2}, taking account of prescaling. A snaphot of RTC time is placed with this alignment into
RTC_IC4.RTCIC4 when prompted to do so by an external requesting input into the
RTC on input capture channel 4. Such an event overwrites any value captured previously in RTC_IC4.RTCIC4.
Note that the RTC_IC4.RTCIC4 input capture channel function itself is enabled by
RTC_CR2IC.RTCIC4EN. In addition, if enabled by RTC_CR2IC.RTCIC4IRQEN, the
RTC can also issue an optional interrupt to the CPU upon an input capture event on
RTC_IC4.RTCIC4.
20–40
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Modulo
RTC_MOD is a read-only register which makes available RTC_MOD.CNTMOD60, which is the modulo-60 equivalent of
the {RTC_CNT1, RTC_CNT0} count value. This modulo-60 value is equal to the displacement in prescaled RTC time
units past the most recent modulo-60 roll-over event. A roll-over is a synonym for a modulo-60 boundary.
Boundaries are defined in the following way. The RTC realigns itself to create coincident modulo-60 and modulo-1
boundaries whenever either of the following events occurs :
(i) the CPU writes a new pair of values to the RTC_CNT1 and RTC_CNT0 registers to redefine the elapsed time units
count while the RTC is enabled and this posted twin write is subsequently executed or
(ii) the CPU enables the RTC from a disabled state using the RTC_CR0.CNTEN field.
Other read-only fields accessible via the RTC_MOD MMR are the magnitude of the most recent increment to the
RTC count, RTC_MOD.INCR and confirmation as to whether this increment coincided with a trim boundary,
RTC_MOD.TRMBDY. Note that the same increment is applied by the RTC to both its absolute (32-bit) count and the
modulo-60 equivalent.
To facilitate debug and to clarify the relationship between RTC_MOD.CNTMOD60 and {RTC_CNT1, RTC_CNT0}, the
upper bits of RTCMOD are padded out with the LSBs of {RTC_CNT1, RTC_CNT0}. This allows
RTC_MOD.CNTMOD60 and part of {RTC_CNT1, RTC_CNT0} to be read out at the same time and their alignment
with each other to be understood.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
CNT0_4TOZERO (R)
Mirror of RTC Count 0 Register [4:0]
8
7
6
5
4
3
2
1
0
0
0
1
0
0
0
0
0
0
CNTMOD60 (R)
Modulo-60 value of prescaled RTC Count
1 and RTC Count 0 Registers
TRMBDY (R)
Trim boundary indicator that the most
recent RTC count increment has coincided
with trimming of the count value
INCR (R)
Most recent increment value added
to the RTC Count in RTC Count 1 and
RTC Count 0 Registers
Figure 20-18: RTC_MOD Register Diagram
Table 20-19:
RTC_MOD Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:11 CNT0_4TOZERO
(R/NW)
Mirror of RTC Count 0 Register [4:0].
It is a mirror of RTC_CNT0[4:0], available for simultaneous read-back along with the
RTC_MOD.CNTMOD60 field.
Having this mirror available at the same time allows the relationship between the modulo-60 and absolute versions of the RTC count to be better understood and debugged.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–41
ADuCM302x RTC Register Descriptions
Table 20-19:
RTC_MOD Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 TRMBDY
(R/NW)
Trim boundary indicator that the most recent RTC count increment has coincided
with trimming of the count value.
0 Trimming has not occurred at the most recent increment of the RTC count.
1 Trimming has occurred at the most recent increment of
the RTC count
9:6 INCR
(R/NW)
Most recent increment value added to the RTC Count in RTC Count 1 and RTC
Count 0 Registers.
It is a read-only value by which the RTC count has most recently been incremented.
Under normal circumstances, when the RTC is enabled, this value will be one. However, when trimming occurs, RTC_MOD.INCR can be any integer value between zero and
eight, depending on the trim configuration in the RTC_TRM MMR.
5:0 CNTMOD60
(R/NW)
Modulo-60 value of prescaled RTC Count 1 and RTC Count 0 Registers.
It counts from 0 to 59, and then rolls over to 0 again. It advances (and is trimmed) in
tandem with the main RTC count in {RTC_CNT1, RTC_CNT0}.{RTC_CNT2}.
It is zeroed whenever any of the following events occurs:
(i) A normal roll-over from a value of 59 when advancing at a prescaled time unit (ii)
whenever the CPU writes a new pair of values to the RTC_CNT1 and RTC_CNT0 registers to redefine the elapsed time count while the RTC is enabled and this posted twin
write is executed (iii) the CPU enables the RTC from a disabled state using the
RTC_CR0.CNTEN (iv) while the RTC is enabled via RTC_CR0.CNTEN, the degree of
prescaling in the RTC is changed via the RTC_CR1.PRESCALE2EXP field.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as all zeros.
20–42
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Output Compare Channel 1
RTC_OC1 is the scheduled alarm time for output capture channel 1 with respect to the 16 lowest {integer_bits, frac-
tional_bits} with meaning of the main 47-bit RTC count. The upper bits of the main RTC count, beyond these 16
bit positions, are don't cares for the purposes of the 16-bit RTC_OC1 output compare channel.
Note that if auto-reloading on the RTC_OC1 output-compare channel is enabled using
RTC_CR4OC.RTCOC1ARLEN, the CPU is given visibility of both the starting value in the output-compare sequence
and the current, cumulative target value, taking account of reloads.
In such circumstances, a read-back of the RTC_OC1 register always returns the starting value of such a reload sequence, whereas a read-back of the RTC_OC1TGT register returns the value of the current target value for the
RTC_OC1 channel, including the effects of cumulative reloads.
If reloading is not enabled, the read-back values of RTC_OC1 and RTC_OC1TGT are the same, namely the starting
(and not reloaded because not enabled) output-compare value in RTC_OC1.
Note that this register only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's
reset value.
15 14 13 12 11 10 9
1
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCOC1 (R/W)
RTC Output Compare 1 Channel. Scheduled
alarm target time with optional auto-reload
Figure 20-19: RTC_OC1 Register Diagram
Table 20-20:
RTC_OC1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RTCOC1
(R/W)
RTC Output Compare 1 Channel. Scheduled alarm target time with optional autoreload.
It has an additional auto-reload capability which can optionally be enabled to take effect whenever an output compare match occurs. It contains a 16-bit target value which
causes an output compare alarm activation whenever there is a masked match between
{RTC_CNT0[(15 - PRESCALE2EXP):0], RTC_CNT2[15:0]} and {RTC_OC1[(15 PRESCALE2EXP):0], {(16 - PRESCALE2EXP){1'b0}}, RTC_OC1[(PRESCALE2EXP - 1):0]}
The active-high mask for the match, i.e. don't-care bit positions for the comparison, is
defined as {TCODEMSK1[(15 - PRESCALE2EXP):0], {(16 - PRESCALE2EXP)
{1'b1}}, TCODEMSK1[(PRESCALE2EXP - 1):0]}, where TCODEMSK1[15:0] is a
thermometer-decoded mask defined by RTCOC1MSKEN ? (16'hFFFF <<
RTCOCMSK[3:0]) : 16'h0000
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–43
ADuCM302x RTC Register Descriptions
Table 20-20:
Bit No.
RTC_OC1 Register Fields (Continued)
Bit Name
Description/Enumeration
(Access)
When an output compare match occurs, the value in RTC_OC1.RTCOC1 is either
maintained or auto-reloaded from a separate 16-bit register. This update is given by
RTC_OC1.RTCOC1 = RTC_CR4OC.RTCOC1ARLEN ? RTC_OC1.RTCOC1 +
RTC_OC1ARL.RTCOC1ARL : RTC_OC1.RTCOC1.
RTC_OC1.RTCOC1 acts as a repeating alarm in both cases. If auto-reloading is enabled,
those bits which are not masked in the reload value effectively define the step size (offset) from the current time to the next output compare alarm. If not auto-reloading (i.e.
if maintaining the value of RTC_OC1.RTCOC1), the periodicity of the output compare
function is a power of 2, given by the unmasked bits in RTC_OC1.RTCOC1, whose value forms a displacement from the modulo roll-over of these bits.
RTC_OC1.RTCOC1 gives the user the ability to schedule repeating alarms whose target
time is checked against the 16 least significant {integer_bits, fractional_bits} of the
RTC count defined by {RTC_CNT1, RTC_CNT0} binary point {RTC_CNT2}, using only
those fractional bits in RTC_CNT2 which have meaning, taking into account the degree
of prescaling of the base 32 kHz clock.
For example, if prescaling by 2^15 from 32 kHz to 1 Hz, there are 15 meaningful fractional bits and thus (16-15)=1 integer bit, all of which are monitored in the form of
{1_integer_bit, 15_fractional_bits} to see if there is a match against the 16-bit value in
RTC_OC1.RTCOC1. In determining such a match, contiguous bits within the target
range of {RTC_CNT0, RTC_CNT2} can be treated as don't cares (from the MSB end of
interest downwards) using a thermometer-decoded, active-high mask, having values in
the series 16'h0000 (no bits masked), 16'8000 (MSBit masked), 16'hC000 (2 MSBits
masked), 16'hE000, 16'hF000, ..., 16'hFFF0, 16'hFFF8, 16'hFFFC (only the 2
LSBits unmasked), 16'hFFFE (only the LSBit unmasked), 16'hFFFF (all bits masked,
implying continuous output compare matches).
In another example of prescaling, this time by 2^2, i.e. dividing the 32 kHz base clock
by just 4 and therefore counting integer time at 8 kHz, there are only 2 meaningful
fractional bits and so matches against RTC_OC1.RTCOC1 use {14_integer_bits, 2_fractional_bits} of the RTC count. Again, bit positions in this comparison can be masked
as described above.
The philosophy of taking into account the degree of prescaling when aligning
RTC_OC1.RTCOC1 and its mask around the binary point in the RTC count is to give
the user the same number (16) of usable, meaningful bits for the output compare function. This allows users to trade off less prescaling, and therefore fewer fractional bits,
against having a greater reach of integer bits for the output compare function and vice
versa. When more prescaling is selected by the user, the output compare target time is
expressed more in fractional bits and less so in integer bits. As prescaling is reduced,
the opposite is true, so that output compares are expressed more in integer bits.
This ensures a quite versatile output compare function which doesn't lessen in capability as a result of the degree of prescaling of the RTC's base clock.
20–44
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Auto-Reload for Output Compare Channel 1
RTC_OC1ARL contains the 16-bit reload value which is optionally (enabled by RTC_CR4OC.RTCOC1ARLEN) added
to the cumulative value of RTC_OC1, visible in the RTC_OC1TGT register, whenever a enabled output compare event
occurs on that channel. Note that only RTC_OC1 of all the output compare channels has this reload capability. The
use of RTC_OC1ARL allows a repeating alarm whose periodicity either is or is not a power of 2 to be put into effect
for RTC_OC1. If reloading is not enabled, the read-back values of RTC_OC1 and RTC_OC1TGT are the same, namely
the starting (and not reloaded because not enabled) output-compare value in RTC_OC1. Note that this register only
exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCOC1ARL (R/W)
Auto-reload value when output compare
match occurs
Figure 20-20: RTC_OC1ARL Register Diagram
Table 20-21:
RTC_OC1ARL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RTCOC1ARL
(R/W)
Auto-reload value when output compare match occurs.
If auto-reloading of RTC_OC1 is enabled via RTC_CR4OC.RTCOC1ARLEN, the contents of this register field are added, modulo 16, to the value of RTCOC1 whenever an
optionally masked match occurs for the RTC_OC1 output compare channel. This is expressed as RTC_OC1.RTCOC1 = RTC_CR4OC.RTCOC1ARLEN ? RTC_OC1.RTCOC1 +
RTC_OC1ARL.RTCOC1ARL : RTC_OC1.RTCOC1
In such circumstances, RTCOC1 acts as a repeating alarm, whereby those bits which
are not masked in the reload value effectively define the step size (offset) from the current time to the next output compare alarm.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–45
ADuCM302x RTC Register Descriptions
RTC Output Compare Channel 1 Target
Read-only register which reflects the current, cumulative target alarm time for the RTC_OC1 channel, taking account
of any auto-reloading upon output-compare events. Note that RTC_OC1TGT only exists in RTC1. In RTC0, the
register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
1
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCOC1TGT (R)
Current, cumulative target time for
Output Compare Channel 1, taking account
of any auto-reloading
Figure 20-21: RTC_OC1TGT Register Diagram
Table 20-22:
RTC_OC1TGT Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RTCOC1TGT
(R/NW)
Current, cumulative target time for Output Compare Channel 1, taking account of
any auto-reloading.
RTC_OC1TGT.RTCOC1TGT is a read-only register which gives visibility to the CPU of
the current target value for the output-compare channel RTC_OC1, taking account of
any possible auto-reloading.
Note that if auto-reloading is not enabled by RTC_CR4OC.RTCOC1ARLEN, the value
returned by RTC_OC1TGT.RTCOC1TGT is identical to that of the RTC_OC1 register,
i.e. the starting value for the RTC_OC1 output-compare channel.
However, if auto-reloading is enabled, a read-back of RTC_OC1TGT.RTCOC1TGT returns the current, cumulative target value for the RTC_OC1 channel, having started the
output-compare sequence from the value contained in the RTC_OC1 register and then
reloaded, i.e. additively accumulated a new target time (offset by the value in
RTC_OC1ARL.RTCOC1ARL) every time an output-compare event occurs.
Note that any of the following configuration changes, when synchronized to the 32
kHz domain, causes a re-initialization of the cumulative RTC_OC1TGT.RTCOC1TGT
target time, such that it is set back again to the starting value in the RTC_OC1 register
for any subsequent auto-reload sequence. In other words, any of the following will
cause a new reload sequence to be begun, with RTC_OC1TGT.RTCOC1TGT re-initialized to the value in RTC_OC1:
[1] A redefinition occurs of the starting value itself due to a write to the RTC_OC1
MMR.
[2] Whenever RTC_CR3OC.RTCOC1EN transitions from 0 to 1, thus enabling the
RTC_OC1 output-compare channel.
[3] Whenever RTC_CR4OC.RTCOC1ARLEN transitions from 1 to 0, thus disabling auto-reloading for RTC_OC1.
[4] Whenever the reload value (offset) in RTC_OC1ARL.RTCOC1ARL is redefined.
20–46
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-22:
Bit No.
RTC_OC1TGT Register Fields (Continued)
Bit Name
Description/Enumeration
(Access)
Note that RTC_OC1TGT.RTCOC1TGT is sourced in the 32 kHz domain and WSYNC
flags for any related MMR redefinitions should be checked to be 1'b1 (i.e. effects
synchronized to the PCLK domain) if such redefinitions affect the target time for the
RTC_OC1 channel, reflected in RTC_OC1TGT.RTCOC1TGT.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–47
ADuCM302x RTC Register Descriptions
RTC Masks for Output Compare Channel
It contains four 4-bit encoded masks, which are decoded out to four 16-bit thermometer-code masks to define contiguous don't care bit positions for target alarm times in the 16-bit output compare channel. Note that this register
only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCOCMSK (R/W)
Concatenation of thermometer-encoded
masks for the 16-bit output compare
channels
Figure 20-22: RTC_OCMSK Register Diagram
Table 20-23:
RTC_OCMSK Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 RTCOCMSK
(R/W)
Concatenation of thermometer-encoded masks for the 16-bit output compare channels.
It contains four 4-bit thermometer-encoded masks, concatenated into a 16-bit register.
Bits [3:0] when thermometer-decoded out to 16-bit values, act as an optional mask,
enabled by RTC_CR4OC.RTCOC1MSKEN, used in the determination of matches with
the RTC count for output compare channel RTC_OC1.
For output compare channel<n>, an active-high mask for matches with the RTC
count, i.e. don't-care bit positions for the comparison, is defined as {TCODEMSK<n>[(15 - PRESCALE2EXP):0], {(16 - PRESCALE2EXP){1'b1}}, TCODEMSK<n>[(PRESCALE2EXP - 1):0]}, where TCODEMSK<n>[15:0] is a thermometer-decoded mask defined by RTCOC<n>MSKEN ? (16'hFFFF <<
RTCOCMSK[(nx4)+:4]) : 16'h0000, where the index, n, lies in the range 0 to 3.
Thermometer masks, independently decoded for each of the four 16-bit output compare channels, thus take on a value from the following series : 16'h0000 (no bits
masked), 16'8000 (MSBit masked), 16'hC000 (2 MSBits masked), 16'hE000,
16'hF000, ..., 16'hFFF0, 16'hFFF8, 16'hFFFC (only the 2 LSBits unmasked),
16'hFFFE (only the LSBit unmasked), 16'hFFFF (all bits masked, implying continuous output compare matches).
20–48
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Snapshot 0
It is a sticky snapshot of the value of RTC_CNT0. It is updated (along with its counterparts RTC_SNAP1 and
RTC_SNAP2), thereby overwriting any previous value of {RTC_SNAP1, RTC_SNAP0}. {RTC_SNAP2}, whenever either of the following two events occurs:
(i) the CPU writes a snapshot request key of 16'h7627 to the RTC_GWY MMR.
(ii) an input-capture event occurs on the RTC_IC0 channel when enabled, provided the setting
RTC_CR2IC.RTCICOWUSEN allows such overwriting.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Constituent part of the 47-bit RTC Input
Capture Channel 0, containing a sticky
snapshot of RTC Count 0 Register
Figure 20-23: RTC_SNAP0 Register Diagram
Table 20-24:
RTC_SNAP0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/NW)
Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky
snapshot of RTC Count 0 Register.
It is part of the 47-bit Input Capture channel RTC_IC0. This channel takes a sticky
snapshot of the 47-bit RTC count in {RTC_CNT1, RTC_CNT0} binary point
{RTC_CNT2} and stores it in {RTC_SNAP1, RTC_SNAP0} . {RTC_SNAP2}. Note that
this snapshot only updates (i.e. overwrites itself with the current value of the RTC
count) if either (i) it is instructed to do so via a positive edge on the requesting input
into the RTC from the GPIOs for RTC_IC0, or (ii) the CPU writes the specific key
value of 0x7627 to the RTC_GWY.
Unlike the 16-bit input capture channels (RTC_IC1, RTC_IC2, RTC_IC3 and
RTC_IC4), the 47-bit input capture channel RTC_IC0 is the only one which has the
additional capability of being able take a snapshot of the RTC count at the prompting
of the CPU. All the other input compare channels simply react to a requesting input
into the RTC from the GPIOs to take a snapshot.
Note that the RTC_IC0 input capture channel function itself for requesting GPIO inputs is enabled by RTC_CR2IC.RTCIC0EN. Only when RTC_CR2IC.RTCIC0EN is
high will a GPIO requester cause an input capture on RTC_IC0. Notwithstanding the
value of RTC_CR2IC.RTCIC0EN, the CPU can always explicitly request a snapshot to
be captured into {RTC_SNAP1, RTC_SNAP0} binary point {RTC_SNAP2} by writing
the appropriate key to RTC_GWY. This independence of a CPU-initiated snapshot over
the value of RTC_CR2IC.RTCIC0EN is for legacy software reasons.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–49
ADuCM302x RTC Register Descriptions
Table 20-24:
Bit No.
RTC_SNAP0 Register Fields (Continued)
Bit Name
Description/Enumeration
(Access)
In addition, if enabled by RTC_CR2IC.RTCIC0IRQEN, the RTC can also issue an optional interrupt to the CPU upon a GPIO-originated (not CPU-originated) input
capture event on RTC_IC0.
The values reflected by RTC_SNAP0, RTC_SNAP1, and RTC_SNAP2 favour giving visibility to the RTC_IC0 channel over a software-initiated snapshot. For this reason, a
software snapshot is only persistent until either of the following events happens (i) a
new RTC_IC0 event occurs or (ii) the CPU does a triplet of register reads of
RTC_SNAP0, RTC_SNAP1, and RTC_SNAP2.
Note that the RTC_SR6.RTCIC0SNAP field indicates whether the value in
RTC_SNAP0, RTC_SNAP1, or RTC_SNAP2 are due to an RTC_IC0 input capture or a
software-initiated snapshot.
Note also that for RTC_IC0 to be considered read by the CPU and thus for a posted
read of RTC_IC0 to the 32 kHz domain to allow RTC_SR6.RTCIC0UNR to update
and thus cause RTC_SR4.RSYNCIC0 to ultimately return to its 1'b1 confirmation value of completion of a synchronised read, the CPU has to read all three RTC_SNAP0,
RTC_SNAP1, and RTC_SNAP2 registers. This is the case even if the CPU is only interested in, for example, 16 of the total 47 snapshot bits available for RTC_IC0.
20–50
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Snapshot 1
RTC_SNAP1 is a sticky snapshot of the value of RTC_CNT1. It is updated (along with its counterparts RTC_SNAP0
and RTC_SNAP2, thereby overwriting any previous value of {RTC_SNAP1, RTC_SNAP0}. {RTC_SNAP2}, whenever
either of the following two events occurs:
(i) the CPU writes a snapshot request key of 16'h7627 to the RTC_GWY MMR.
(ii) an input-capture event occurs on the RTCIC0 channel when enabled, provided the setting of
RTC_CR2IC.RTCICOWUSEN allows such overwriting.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Constituent part of the 47-bit RTC Input
Capture Channel 0, containing a sticky
snapshot of RTC Count 1 Register
Figure 20-24: RTC_SNAP1 Register Diagram
Table 20-25:
RTC_SNAP1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 VALUE
(R/NW)
Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky
snapshot of RTC Count 1 Register.
It is a part of the 47-bit Input Capture channel RTC_IC0. This channel takes a sticky
snapshot of the 47-bit RTC count in {RTC_CNT1, RTC_CNT0} binary point
{RTC_CNT0} and stores it in { RTC_SNAP1, RTC_SNAP0} binary point {RTC_SNAP2}.
Note that this snapshot only updates (i.e. overwrites itself with the current value of the
RTC count) if either (i) it is instructed to do so via a positive edge on the requesting
input into the RTC from the GPIOs for RTCIC0, or (ii) the CPU writes the specific
key value of 0x7627 to the RTC_GWY register.
Unlike the 16-bit input capture channels (RTCIC1, RTCIC2, RTCIC3 and
RTCIC4), the 47-bit input capture channel RTCIC0 is the only one which has the
additional capability of being able take a snapshot of the RTC count at the prompting
of the CPU. All the other input compare channels simply react to a requesting input
into the RTC from the GPIOs to take a snapshot.
Note that the RTCIC0 input capture channel function itself for requesting GPIO inputs is enabled by RTC_CR2IC.RTCIC0EN. Only when RTC_CR2IC.RTCIC0EN is
high will a GPIO requester cause an input capture on RTCIC0. Notwithstanding the
value of RTC_CR2IC.RTCIC0EN, the CPU can always explicitly request a snapshot to
be captured into {RTC_SNAP1, RTC_SNAP0} . {RTC_SNAP2} by writing the appropriate key to RTC_GWY. This independence of a CPU-initiated snapshot over the value of
RTC_CR2IC.RTCIC0EN is for legacy software reasons.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–51
ADuCM302x RTC Register Descriptions
Table 20-25:
Bit No.
RTC_SNAP1 Register Fields (Continued)
Bit Name
Description/Enumeration
(Access)
In addition, if enabled by RTC_CR2IC.RTCIC0IRQEN, the RTC can also issue an optional interrupt to the CPU upon a GPIO-originated (not CPU-originated) input
capture event on RTCIC0.
The values reflected by RTC_SNAP0, RTC_SNAP1, RTC_SNAP2 favour giving visibility
to the RTCIC0 channel over a software-initiated snapshot. For this reason, a software
snapshot is only persistent until either of the following events happens (i) a new
RTCIC0 event occurs or (ii) the CPU does a triplet of register reads of RTC_SNAP0,
RTC_SNAP1, RTC_SNAP2.
Note that the RTC_SR6.RTCIC0SNAP field indicates whether the value in
RTC_SNAP0, RTC_SNAP1, or RTC_SNAP2 are due to an RTCIC0 input capture or a
software-initiated snapshot.
Note also that for RTCIC0 to be considered read by the CPU and thus for a posted
read of RTCIC0 to the 32 kHz domain to allow RTC_SR6.RTCIC0UNR to update
and thus cause RTC_SR4.RSYNCIC0 to ultimately return to its 1'b1 confirmation value of completion of a synchronised read, the CPU has to read all three RTC_SNAP0,
RTC_SNAP1, RTC_SNAP2 registers. This is the case even if the CPU is only interested
in, for example, 16 of the total 47 snapshot bits available for RTCIC0.
20–52
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Snapshot 2
Sticky snapshot of the value of RTC_CNT2. It is updated (along with its counterparts RTC_SNAP0 and
RTC_SNAP1), thereby overwriting any previous value of {RTC_SNAP1, RTC_SNAP0}. {RTC_SNAP2}, whenever either of the following two events occurs:
(i) the CPU writes a snapshot request key of 16'h7627 to the RTC_GWY MMR.
(ii) an input-capture event occurs on the RTCIC0 channel when enabled, provided the setting of
RTC_CR2IC.RTCICOWUSEN allows such overwriting.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
VALUE (R)
Constituent part of the 47-bit RTC Input
Capture Channel 0, containing a sticky
snapshot of RTC Count 2 Register
Figure 20-25: RTC_SNAP2 Register Diagram
Table 20-26:
RTC_SNAP2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14:0 VALUE
(R/NW)
Constituent part of the 47-bit RTC Input Capture Channel 0, containing a sticky
snapshot of RTC Count 2 Register.
It is part of the 47-bit Input Capture channel RTCIC0.
This channel takes a sticky snapshot of the 47-bit RTC count in {RTC_CNT1,
RTC_CNT0} binary point {RTC_CNT2} and stores it in {RTC_SNAP1, RTC_SNAP0} binary point {RTC_SNAP2}.
Note that this snapshot only updates (i.e. overwrites itself with the current value of the
RTC count) if either (i) it is instructed to do so via a positive edge on the requesting
input into the RTC from the GPIOs for RTCIC0, or (ii) the CPU writes the specific
key value of 0x7627 to the RTC_GWY register.
Unlike the 16-bit input capture channels (RTCIC1, RTCIC2, RTCIC3 and
RTCIC4), the 47-bit input capture channel RTCIC0 is the only one which has the
additional capability of being able take a snapshot of the RTC count at the prompting
of the CPU. All the other input compare channels simply react to a requesting input
into the RTC from the GPIOs to take a snapshot.
Note that the RTCIC0 input capture channel function itself for requesting GPIO inputs is enabled by RTC_CR2IC.RTCIC0EN. Only when RTC_CR2IC.RTCIC0EN is
high will a GPIO requester cause an input capture on RTCIC0. Notwithstanding the
value of RTC_CR2IC.RTCIC0EN, the CPU can always explicitly request a snapshot to
be captured into {RTC_SNAP1, RTC_SNAP0} . {RTC_SNAP2} by writing the appropriate key to RTC_GWY. This independence of a CPU-initiated snapshot over the value of
RTC_CR2IC.RTCIC0EN is for legacy software reasons.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–53
ADuCM302x RTC Register Descriptions
Table 20-26:
Bit No.
RTC_SNAP2 Register Fields (Continued)
Bit Name
Description/Enumeration
(Access)
In addition, if enabled by RTC_CR2IC.RTCIC0IRQEN, the RTC can also issue an optional interrupt to the CPU upon a GPIO-originated (not CPU-originated) input capture event on RTCIC0.
The values reflected by RTC_SNAP0, RTC_SNAP1, RTC_SNAP2 favour giving visibility
to the RTCIC0 channel over a software-initiated snapshot. For this reason, a software
snapshot is only persistent until either of the following events happens (i) a new
RTCIC0 event occurs or (ii) the CPU does a triplet of register reads of RTC_SNAP0,
RTC_SNAP1, RTC_SNAP2.
Note that the RTC_SR6.RTCIC0SNAP indicates whether the value in RTC_SNAP0,
RTC_SNAP1, or RTC_SNAP2 are due to an RTCIC0 input capture or a software-initiated snapshot.
Note also that for RTCIC0 to be considered read by the CPU and thus for a posted
read of RTCIC0 to the 32 kHz domain to allow RTC_SR6.RTCIC0UNR to update
and thus cause RTC_SR4.RSYNCIC0 to ultimately return to its 1'b1 confirmation value of completion of a synchronized read, the CPU has to read all three RTC_SNAP0,
RTC_SNAP1, and RTC_SNAP2 registers. This is the case even if the CPU is only interested in, for example, 16 of the total 47 snapshot bits available for RTCIC0.
20–54
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Status 0
Information on RTC operation is made available to the CPU via three status registers RTC_SR0, RTC_SR1, and
RTC_SR2. These registers include all flags related to CPU interrupt sources and error conditions within the RTC.
Note that there is a one-for-one correspondence between bit positions in RTC_SR0 and RTC_SR1 in terms of their
WSYNC<mmr> and WPEND<mmr> fields respectively. The WSYNC status for an MMR in RTC_SR0 is located
at the same bit position as the WPEND status for the same MMR in RTC_SR1.
The distinction between WSYNC and WPEND is as follows. If a posted write transaction to an MMR in the RTC
has completed execution and the effects of the transaction are visible to the processor, the WSYNC status for the
MMR in question is set to 1. Otherwise, if the effects of a posted transaction to an MMR are not yet visible, the
WSYNC status for that MMR is 0.
WPEND, on the other hand, indicates whether there is room in the RTC to accept a new posted write to a given
MMR. If a previously posted write to an MMR is awaiting execution and is occupying the drop point for posted
writes to that MMR, the WPEND status of the MMR concerned is 1. Otherwise, if the RTC has room to accept a
new posted write for an individual MMR, the WPEND status for that MMR is 0.
Posted writes take time to complete if they concern MMRs or MMR fields which are sourced in the 32 kHz clock
domain of the RTC. These MMRs (all fields) are as follows : RTC_CR0, RTC_CNT0, RTC_CNT1, RTC_ALM0,
RTC_ALM1, RTC_ALM2, RTC_TRM, RTC_CR1.
The following sticky interrupt source fields of the RTC_SR0 MMR are also sourced in the 32 kHz domain:
RTC_SR0.ALMINT, RTC_SR0.MOD60ALMINT, RTC_SR0.ISOINT. Any write-one-to-clear clearances of these interrupt source fields accumulate (if still pending) into a common posted write transaction for the RTC_SR0 MMR.
This determines the WPEND status of the RTC_SR0 MMR itself.
Note that the results of posted clearances of interrupt source fields in RTC_SR0 are immediately visible by the processor. For this reason, the WSYNC status of RTC_SR0 is always 1, to confirm that results of writes (clearances) are
immediately available to the CPU.
Note that the WPEND status and WSYNC status for the RTC_SR0 are encompassing values for the MMR as a
whole. There is no distinction made in these status values as to how many interrupt source fields are being cleared at
the same time by a single posted write to RTC_SR0.
The RTC_SR1 status register, in comparison, is a read-only status register. RTC_SR1 has no WPEND or WSYNC
status values, as there are never any posted writes to the MMR. RTC_SR2, on the other hand, is a read-write status
register, containing RW1C interrupt sources but all of these reside wholly in the processor's clock domain and can
be cleared instantly. Hence RTC_SR2 has no WPEND or WSYNC values associated with it.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–55
ADuCM302x RTC Register Descriptions
15 14 13 12 11 10 9
0
0
1
1
1
1
1
8
7
6
5
4
3
2
1
0
1
1
0
0
0
0
0
0
0
WSYNCTRM (R)
Synchronization status of posted writes
to RTC Trim Register
ALMINT (R/W1C)
Alarm interrupt source
MOD60ALMINT (R/W1C)
Modulo-60 RTC alarm interrupt source
WSYNCALM1 (R)
Synchronization status of posted writes
to RTC Alarm 1 Register
ISOINT (R/W1C)
RTC power-domain isolation interrupt
source
WSYNCALM0 (R)
Synchronization status of posted writes
to RTC Alarm 0 Register
WPNDERRINT (R/W1C)
Write pending error interrupt source
WSYNCCNT1 (R)
Synchronization status of posted writes
to RTC Count 1 Register
WSYNCINT (R/W1C)
Write synchronization interrupt
WPNDINT (R/W1C)
Write pending interrupt
WSYNCCNT0 (R)
Synchronization status of posted writes
to RTC Count 0 Register
WSYNCSR0 (R)
Synchronization status of posted clearances
to interrupt sources in RTC Status 0
Register
WSYNCCR0 (R)
Synchronization status of posted writes
to RTC Control 0 Register
Figure 20-26: RTC_SR0 Register Diagram
Table 20-27:
RTC_SR0 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
13 WSYNCTRM
(R/NW)
Synchronization status of posted writes to RTC Trim Register.
It indicates if the effects of a posted write to RTC_TRM are visible to the CPU.
If RTC_SR0.WSYNCTRM is low, a posted write to RTC_TRM is currently queued up or
in the process of being executed, but the results of this transaction are not yet visible to
the CPU.
When RTC_SR0.WSYNCTRM goes high and thereby activates the
RTC_SR0.WSYNCINT sticky interrupt source, the effects of a write to RTC_TRM are
then available to the processor.
The delay in the visibility of results is due to (i) the queuing time behind transactions
which were posted earlier and (ii) the synchronisation delay between RTC clock domains during the actual execution.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
20–56
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-27:
RTC_SR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12 WSYNCALM1
(R/NW)
Synchronization status of posted writes to RTC Alarm 1 Register.
It indicates if the effects of a posted write to RTC_ALM1 are visible to the CPU.
If RTC_SR0.WSYNCALM1 is low, a posted write to RTC_ALM1 is currently queued up
or in the process of being executed, but the results of this transaction are not yet visible
to the CPU.
When RTC_SR0.WSYNCALM1 goes high and thereby activates the
RTC_SR0.WSYNCINT sticky interrupt source, the effects of a write to RTC_ALM1 are
then available to the processor.
The delay in the visibility of results is due to (i) the queuing time behind transactions
which were posted earlier, (ii) any waiting for co-ordinated writes to be posted to
RTC_ALM0 and RTC_ALM2 (since only co-ordinated, triple writes are ever despatched
for execution of a redefinition of the RTC alarm) and (iii) the synchronisation delay
between RTC clock domains during the actual execution.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
11 WSYNCALM0
(R/NW)
Synchronization status of posted writes to RTC Alarm 0 Register.
It indicates if the effects of a posted write to RTC_ALM0 are visible to the CPU.
If RTC_SR0.WSYNCALM0 is low, a posted write to RTC_ALM0 is currently queued up
or in the process of being executed, but the results of this transaction are not yet visible
to the CPU.
When RTC_SR0.WSYNCALM0 goes high and thereby activates the
RTC_SR0.WSYNCINT sticky interrupt source, the effects of a write to RTC_ALM0 are
then available to the processor.
The delay in the visibility of results is due to (i) the queuing time behind transactions
which were posted earlier, (ii) any waiting for co-ordinated writes to be posted to
RTC_ALM1 and RTC_ALM2 (since only co-ordinated, triple writes are ever despatched
for execution of a redefinition of the RTC alarm) and (iii) the synchronisation delay
between RTC clock domains during the actual execution.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–57
ADuCM302x RTC Register Descriptions
Table 20-27:
RTC_SR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 WSYNCCNT1
(R/NW)
Synchronization status of posted writes to RTC Count 1 Register.
It indicates if the effects of a posted write to RTC_CNT1 are visible to the CPU.
If RTC_SR0.WSYNCCNT1 is low, a posted write to RTC_CNT1 is currently queued up
or in the process of being executed, but the results of this transaction are not yet visible
to the CPU.
When RTC_SR0.WSYNCCNT1 goes high and thereby activates the
RTC_SR0.WSYNCINT sticky interrupt source, the effects of a write to RTC_CNT1 are
then available to the processor.
The delay in the visibility of results is due to (i) the queuing time behind transactions
which were posted earlier, (ii) any waiting for a paired write to be posted to RTC_CNT0
(since only paired writes are ever despatched for execution of an RTC count definition)
and (iii) the synchronization delay between RTC clock domains during the actual execution.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
9 WSYNCCNT0
(R/NW)
Synchronization status of posted writes to RTC Count 0 Register.
It indicates if the effects of a posted write to RTC_CNT0 are visible to the CPU.
If RTC_SR0.WSYNCCNT0 is low, a posted write to RTC_CNT0 is currently queued up
or in the process of being executed, but the results of this transaction are not yet visible
to the CPU.
When RTC_SR0.WSYNCCNT0 goes high and thereby activates the
RTC_SR0.WSYNCINT sticky interrupt source, the effects of a write to RTC_CNT0 are
then available to the processor.
The delay in the visibility of results is due to (i) the queuing time behind transactions
which were posted earlier, (ii) any waiting for a paired write to be posted to RTC_CNT1
(since only paired writes are ever despatched for execution of an RTC count redefinition) and (iii) the synchronisation delay between RTC clock domains during the actual
execution.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
20–58
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-27:
RTC_SR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
8 WSYNCSR0
(R/NW)
Synchronization status of posted clearances to interrupt sources in RTC Status 0 Register.
It indicates if the effects of a posted write to RTC_SR0 are visible to the CPU.
RTC_SR0.WSYNCSR0 always reads back as 1 because the only writes which can or
need to be posted to RTC_SR0 are clearances of 32 kHz sourced interrupt sources.
These sources are RTC_SR0.ALMINT, RTC_SR0.MOD60ALMINT, and
RTC_SR0.ISOINT. The interrupt sources concerned by such posted clearances to
RTC_SR0 are masked (to inactive) by the RTC for the duration of the posting until
actual execution. The net effect of this is that the CPU always sees an interrupt source
as being immediately cleared, regardless of where it is sourced. For this reason,
RTC_SR0.WSYNCSR0 always reads back as 1.
Note that no posting (or associated masking) is needed for clearances of
RTC_SR0.WPNDERRINT, RTC_SR0.WSYNCINT and RTC_SR0.WPNDINT, as these
fields are sourced in the core's clock domain. Hence, their clearance is immediate.
0 Results of a posted write are not yet visible to the CPU.
1 Results of a posted write are visible to the CPU.
7 WSYNCCR0
(R/NW)
Synchronization status of posted writes to RTC Control 0 Register.
It indicates if the effects of a posted write to RTC_CR0 are visible to the CPU.
If RTC_SR0.WSYNCCR0 is low, a posted write to RTC_CR0 is currently queued up or
in the process of being executed, but the results of this transaction are not yet visible to
the CPU.
When RTC_SR0.WSYNCCR0 goes high and thereby activates the
RTC_SR0.WSYNCINT sticky interrupt source, the effects of a write to RTC_CR0 are
then available to the processor.
The delay in the visibility of results is due to both the queuing time behind transactions which were posted earlier, along with the synchronisation delay between the RTC
clock domains during the actual execution.
0 Results of a posted write are not yet visible by the CPU.
1 Results of a posted write are visible by the CPU.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–59
ADuCM302x RTC Register Descriptions
Table 20-27:
RTC_SR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
6 WPNDINT
(R/W1C)
Write pending interrupt.
Sticky interrupt source which is activated whenever room frees up for the CPU to post
a new write transaction to a 32 kHz sourced MMR or MMR bit field in the RTC.
In response to a RTC_SR0.WPNDINT interrupt, the CPU can read the WPEND fields
in RTC_SR1 and RTC_SR2 to determine which MMR most recently freed up as a result of the despatch by the RTC for execution of a previously-posted write transaction.
Note the distinction between the WPEND status and the WSYNC status of an MMR.
The former indicates whether the RTC can accept a new posted write by the CPU to
an MMR, whereas the latter indicates whether the effects of a posted write to an MMR
are subsequently visible to the CPU. See the description of the WPEND<MMR> and
WSYNC<MMR> fields of RTC_SR2 and RTC_SR0 for more details.
If the WPEND status of an MMR in RTC_SR1 or RTC_SR2 is active 1, any attempt
by the CPU to post a further write transaction to the same MMR will be rejected by
the RTC, since there is no room to accept the posting. Such a scenario results in activation of the RTC_SR0.WPNDERRINT interrupt source in RTC_SR0.
Any MMR or MMR bit field which does not have a WSYNC status field in RTC_SR0
or a WPEND status field in RTC_SR1 is independent of the 32 kHz domain. This
means that writes to such MMRs or MMR fields are executed immediately, upon receipt by the RTC. These write are not posted, nor do they pend.
Examples of such immediately-executed writes are clearances by the CPU of the
WSYNCERRINT, RTC_SR0.WSYNCINT and RTC_SR0.WPNDINT sticky interrupt
source fields.
Like all interrupt sources in the RTC, the RTC_SR0.WPNDINT field has a corresponding enable bit in RTC_CR0 which determines whether it should contribute to the RTC
peripheral interrupt which is sent to the CPU.
To enable a RTC_SR0.WPNDINT interrupt, set RTC_CR0.WPNDINTEN to 1.
RTC_SR0.WPNDINT is cleared by writing 1.
0 There has been no change in the pending status of any
posted write transaction in the RTC since WPENDINT
was last cleared.
1 A posted write transaction has been dispatched since
WPENDINT was last cleared, thus freeing up a slot for
a new posted write by the CPU to the same MMR.
20–60
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-27:
RTC_SR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5 WSYNCINT
(R/W1C)
Write synchronization interrupt.
Sticky interrupt source which is activated whenever a posted write transaction to a 32
kHz sourced MMR or MMR bit field completes and whose effects are then visible to
the CPU.
When an RTC interrupt is generated due to activation of RTC_SR0.WSYNCINT, the
CPU can read back RTC_SR0 and RTC_SR2 to see which MMR(s) has/have most recently changed its/their synchronization status, visible through the
RTC_SR0.WSYNCCR0, RTC_SR0.WSYNCSR0, RTC_SR0.WSYNCCNT0,
RTC_SR0.WSYNCCNT1, RTC_SR0.WSYNCALM0, RTC_SR0.WSYNCALM1, WSYNCALM2, RTC_SR0.WSYNCTRM and WSYNCCR1 bit fields.
Thus, by checking the WSYNC fields of RTC_SR0 and RTC_SR2, the CPU can identify which posted write transaction has just completed and caused the
RTC_SR0.WSYNCINT interrupt source to stick (or restick if already active).
RTC_SR0.WSYNCINT is cleared by writing a 1 to its bit position in RTC_SR0.
Note especially that clearances of any interrupt sources in RTC_SR0 take immediate
effect in terms of the CPU's view of those source values. For this reason, such clearances do not re-activate RTC_SR0.WSYNCINT, as the CPU requires no further confirmation as to when it can see the sources cleared. Thus, the RTC_SR0.WSYNCSR0 is always reads back as 1, indicating that the effects of a write transaction to RTC_SR0 are
visible.
Note that the pend status of any transaction really indicates the RTC's ability to accept
another posted write to the same MMR requiring interaction with the 32kHz domain.
The WPEND fields in RTC_SR0 and RTC_SR1 can be viewed as indicators of "room
to accept a posted write". Each MMR has one independent (from any of the other
MMRs) pend slot into which a write transaction can be posted by the CPU.
Any MMR or MMR bit field which does not have a WSYNC status field in RTC_SR0
or RTC_SR2 or a WPEND status field in RTC_SR1 is independent of the 32 kHz domain. This means that writes to such MMRs or MMR fields are executed immediately,
upon receipt by the RTC. These write are not posted, nor do they pend.
Examples of such immediately-executed writes are clearances by the CPU of the
RTC_SR0.WPNDERRINT, RTC_SR0.WSYNCINT and RTC_SR0.WPNDINT sticky interrupt source fields within RTC_SR0, as well as all interrupt source fields in
RTC_SR2.
Like all interrupt sources in the RTC, the RTC_SR0.WSYNCINT field has a corresponding enable bit in RTC_CR0 which determines whether it should contribute to the
RTC peripheral interrupt which is sent to the CPU. To enable a RTC_SR0.WSYNCINT
interrupt, set RTC_CR0.WSYNCINTEN to 1.
0 Since the CPU last cleared RTC_SR0.WSYNCINT, there
has been no occurrence of the effects of a posted write
transaction to a 32kHz-sourced MMR or MMR bit
field have becoming newly visible to the CPU's clock
domain.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
1 Since the CPU last cleared RTC_SR0.WSYNCINT, the
effects of a posted write transaction to a 32kHz-sourced
20–61
MMR or MMR bit field have becoming newly visible
to
the CPU's clock domain.
ADuCM302x RTC Register Descriptions
Table 20-27:
RTC_SR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
4 WPNDERRINT
(R/W1C)
Write pending error interrupt source.
Sticky interrupt source which indicates that an error has occurred because the CPU attempted to write to an RTC register while a previous write to the same register was
pending execution.
A maximum of one pending write transaction per MMR is supported by the RTC
when such writes are to MMRs which are sourced in the 32 kHz domain. These pendtype MMRs are RTC_CR0, RTC_CNT0, RTC_CNT1, RTC_ALM0, RTC_ALM1,
RTC_ALM2, RTC_TRM, RTC_CR1, RTC_CR2IC, RTC_CR3OC, RTC_CR4OC,
RTC_OCMSK, RTC_OC1ARL, RTC_OC1.
Note that write-one clearances to interrupt source bit fields in the status registers
RTC_SR0 and RTC_SR3 can never cause a pending error because such clearances are
cumulative and non-destructive of currently-pending clearances. The latter cannot be
overwritten or undone by posting yet more clearances, all of which are accumulated
into any pending transaction for RTC_SR0 or RTC_SR3.
Note that in the RTC, all MMR writes are carried out in the order in which they are
received from the APB. Register writes to MMRs or MMR bit fields sourced in the 32
kHz domain take time to complete because of synchronization between the core clock
domain and the much slower 32 kHz domain.
Synchronization errors can be avoided by the CPU by first checking in RTC_SR1 or
RTC_SR5 the WPEND pending status of a register before undertaking a write to that
register. The WPEND status of an MMR indicates whether the RTC can accept a new
posted write to that MMR. Should an error occur due to the CPU posting a write
when there is no room, the RTC will interrupt the CPU provided
RTC_CR0.WPNDERRINTEN enables the RTC_SR0.WPNDERRINT interrupt source.
Note that if multiple write pending errors (i.e. rejected posted writes) occur,
RTC_SR0.WPNDERRINT sticks active at the first occurrence.
RTC_SR0.WPNDERRINT is cleared by writing one to its bit position.
0 No posted write has been rejected by the RTC since
RTC_SR0.WPNDERRINT is last cleared by the CPU.
1 A posted write has been rejected by the RTC due to a
previously-posted write to the same MMR which is still
awaiting execution. Such a rejection has occurred since
the CPU last cleared RTC_SR0.WPNDERRINT.
20–62
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-27:
RTC_SR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 ISOINT
(R/W1C)
RTC power-domain isolation interrupt source.
Sticky interrupt source which indicates whether the RTC has had to activate its powerdomain isolation barrier due to a power loss in the core. When the core regains power,
the CPU can read ISOINT to inform itself of such a power event.
When power loss is imminent to all power domains on the device apart from the RTC,
the RTC activates its isolation barrier so that it can continue to operate independently
of the core. When power is subsequently restored to the rest of the device, the RTC
activates the RTC_SR0.ISOINT interrupt source to act as a sticky record of the power
loss event just finishing. This activation occurs as the RTC lowers its isolation barrier
once it knows that the core has regained power.
If enabled by RTC_CR0.ISOINTEN, the RTC will interrupt the CPU based on
RTC_SR0.ISOINT. The CPU can then inspect the RTC_SR0.ISOINT field to discover that it (the CPU) has recovered from a total loss of power. To enable an RTC
interrupt to the CPU due to the activation of RTC_SR0.ISOINT, set
RTC_CR0.ISOINTEN to 1.
RTC_SR0.ISOINT can be cleared by the CPU by writing 1 to its bit position.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 The always-on RTC power domain has not activated its
isolation from the core since the RTC_SR0.ISOINT interrupt source was last cleared by the CPU.
1 The always-on RTC power domain has activated and
subsequently de-activated its isolation from the core due
to a power event. This event occurred since
RTC_SR0.ISOINT was last cleared by the CPU.
2 MOD60ALMINT
(R/W1C)
Modulo-60 RTC alarm interrupt source.
Sticky flag which is the source of an optionally-enabled interrupt to the CPU. This interrupt is activated once every 60 increments of {RTC_CNT1, RTC_CNT0}, at a displacement of RTC_CR0.MOD60ALM increments past a modulo-60 boundary.
It is enabled and its target time is configured using the RTC_CR0.MOD60ALMINTEN
and RTC_CR0.MOD60ALM respectively. It is cleared by writing a value of one to its bit
position.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 RTC_SR0.MOD60ALMINT interrupt event has not occurred since this bit was last cleared by the CPU.
1 RTC_SR0.MOD60ALMINT interrupt event has occurred
since this bit was last cleared by the CPU.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–63
ADuCM302x RTC Register Descriptions
Table 20-27:
RTC_SR0 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 ALMINT
(R/W1C)
Alarm interrupt source.
Sticky flag which is the source of an optionally-enabled interrupt to the CPU. It indicates that an alarm event has occurred due to a match between the RTC count and
alarm register values. A match is defined as the value in {RTC_CNT1 , RTC_CNT0} .
{RTC_CNT2} equating to the alarm time given by {RTC_ALM1, RTC_ALM0} .
{RTC_ALM2}. The detection of such an event is enabled by RTC_CR0.ALMEN in
RTCCR0, assuming that RTC_CR0.CNTEN is also enabled.
It is cleared by writing a value of one to its bit position.
0 RTC_SR0.ALMINT interrupt event has not occurred
since this bit was last cleared by the CPU.
1 RTC_SR0.ALMINT interrupt event has occurred since
this bit was last cleared by the CPU.
20–64
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Status 1
Information on RTC operation is made available to the CPU via three status registers RTC_SR0, RTC_SR1 and
RTC_SR2. These registers include all flags related to CPU interrupt sources and error conditions within the RTC.
Note that there is a one-for-one correspondence between bit positions in RTC_SR0 and RTC_SR1 in terms of their
WSYNC<mmr> and WPEND<mmr> fields respectively. The WSYNC status for an MMR in RTC_SR0 is located
at the same bit position as the WPEND status for the same MMR in RTC_SR1.
The distinction between WSYNC and WPEND is as follows. If a posted write transaction to an MMR in the RTC
has completed execution and the effects of the transaction are visible to the processor, the WSYNC status for the
MMR in question is set to 1. Otherwise, if the effects of a posted transaction to an MMR are not yet visible, the
WSYNC status for that MMR is 0.
WPEND, on the other hand, indicates whether there is room in the RTC to accept a new posted write to a given
MMR. If a previously posted write to an MMR is awaiting execution and is occupying the drop point for posted
writes to that MMR, the WPEND status of the MMR concerned is 1. Otherwise, if the RTC has room to accept a
new posted write for an individual MMR, the WPEND status for that MMR is 0.
Posted writes take time to complete if they concern MMRs or MMR fields which are sourced in the 32 kHz clock
domain of the RTC. These MMRs (all fields) are as follows: RTC_CR0, RTC_CNT0, RTC_CNT1, RTC_ALM0,
RTC_ALM1, RTC_ALM2, RTC_TRM, RTC_CR1
The following sticky interrupt source fields of the RTC_SR0 MMR are also sourced in the 32 kHz domain :
RTC_SR0.ALMINT, RTC_SR0.MOD60ALMINT, RTC_SR0.ISOINT. Any write-one-to-clear clearances of these interrupt source fields accumulate (if still pending) into a common posted write transaction for the RTC_SR0 MMR.
This determines the WPEND status of the RTC_SR0 MMR itself.
Note that the results of posted clearances of interrupt source fields in RTC_SR0 are immediately visible by the processor. For this reason, the WSYNC status of RTC_SR0 is always 1, to confirm that results of writes (clearances) are
immediately available to the CPU.
Note that the WPEND status and WSYNC status for the RTC_SR0 are encompassing values for the MMR as a
whole. There is no distinction made in these status values as to how many interrupt source fields are being cleared at
the same time by a single posted write to RTC_SR0.
The RTC_SR1 status register, in comparison, is a read-only status register. RTC_SR1 has no WPEND or WSYNC
status values, as there are never any posted writes to the MMR. RTC_SR2, on the other hand, is a read-write status
register, containing RW1C interrupt sources but all of these reside wholly in the processor's clock domain and can
be cleared instantly. Hence, RTC_SR2 has no WPEND or WSYNC values associated with it.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–65
ADuCM302x RTC Register Descriptions
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
WPNDTRM (R)
Pending status of posted writes to RTC
Trim Register
WPNDCR0 (R)
Pending status of posted writes to RTC
Control 0 Register
WPNDALM1 (R)
Pending status of posted writes to RTC
ALARM 1 Register
WPNDSR0 (R)
Pending status of posted clearances
of interrupt sources in RTC Status 0
Register
WPNDALM0 (R)
Pending status of posted writes to RTC
ALARM 0 Register
WPNDCNT1 (R)
Pending status of posted writes to RTC
Count 1 Register
WPNDCNT0 (R)
Pending status of posted writes to RTC
Count 0 Register
Figure 20-27: RTC_SR1 Register Diagram
Table 20-28:
RTC_SR1 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
13 WPNDTRM
(R/NW)
Pending status of posted writes to RTC Trim Register.
Indicates, if a posted register write to RTC_TRM is currently pending (i.e. buffered and
enqueued) and awaiting execution and therefore no further write to the same MMR
can be accepted at this time.
0 The RTC can accept a new posted write to the
RTC_TRM MMR.
1 A previously-posted write to RTC_TRM is still awaiting
execution, so no new posting to this MMR can be accepted.
12 WPNDALM1
(R/NW)
Pending status of posted writes to RTC ALARM 1 Register.
Indicates, if a posted register write to RTC_ALM1 is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to the
RTC_ALM1 MMR.
1 A previously-posted write to RTC_ALM1 is still awaiting
execution, so no new posting to this MMR can be accepted.
20–66
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-28:
RTC_SR1 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
11 WPNDALM0
(R/NW)
Pending status of posted writes to RTC ALARM 0 Register.
Indicates, if a posted register write to RTC_ALM0 is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to the
RTC_ALM0 MMR.
1 A previously-posted write to RTC_ALM0 is still awaiting
execution, so no new posting to this MMR can be accepted.
10 WPNDCNT1
(R/NW)
Pending status of posted writes to RTC Count 1 Register.
Indicates, if a posted register write to RTC_CNT1 is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to the
RTC_CNT1 MMR.
1 A previously-posted write to RTC_CNT1 is still awaiting
execution, so no new posting to this MMR can be accepted.
9 WPNDCNT0
(R/NW)
Pending status of posted writes to RTC Count 0 Register.
Indicates, if a posted register write to RTC_CNT0 is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to the
RTC_CNT0 MMR.
1 A previously-posted write to RTC_CNT0 is still awaiting
execution, so no new posting to this MMR can be accepted.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–67
ADuCM302x RTC Register Descriptions
Table 20-28:
RTC_SR1 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
8 WPNDSR0
(R/NW)
Pending status of posted clearances of interrupt sources in RTC Status 0 Register.
It indicates if posted clearances of interrupt sources in RTC_SR0 are currently pending
(i.e. buffered and enqueued) and awaiting execution. Note the further posted clearances can always be accepted and accumulated into the same pending transaction for
RTC_SR0, as such an accumulation is non-destructive of previously-posted clearances.
This is in contrast to the case for other MMRs where posted write data (as opposed to
posted clearances) cannot be aggregated into one transaction.
0 The RTC can accept new posted clearances of interrupt
sources in RTC_SR0 located in the 32 kHz domain.
1 A previously-posted clearance of interrupt sources in
RTC_SR0 maintained in the 32 kHz domain is still
awaiting execution. Additional clearances can still be
aggregated into the existing, pending transaction.
7 WPNDCR0
(R/NW)
Pending status of posted writes to RTC Control 0 Register.
Indicates if a posted register write to RTC_CR0 is currently pending (i.e. buffered and
enqueued) and awaiting execution and therefore no further write to the same MMR
can be accepted at this time.
0 The RTC can accept a new posted write to RTC_CR0.
1 A previously-posted write to RTC_CR0 is still awaiting
execution, so no new posting to this MMR can be accepted.
20–68
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Status 2
It is a status register which further complements the status information provided by RTC_SR0 and RTC_SR1. Note
that RTC1 has full RTC_SR2 functionality, RTC0 has reduced features. Details of RTC0 differences are given in
individual bit fields of RTC_SR2.
RTC_SR2 contains optionally-enabled (via RTC_CR1) sticky interrupt sources which are fan-in terms of the RTC
peripheral interrupt. These tell the CPU when (i) the RTC count has changed, (ii) the prescaled gated clock which
controls the advancement of the RTC count has activated, (iii) a trim boundary (and thus trimming) has occurred,
(iv) the 32-bit RTC count has rolled over and (v) the modulo-60 version of the RTC count has rolled over.
All interrupt sources in RTC_SR2 are sticky, active high, level signals. Each one can individually be cleared by writing a value of 1'b1 to its bit position in RTC_SR2.
RTC_SR2 also contains mirrors of WSYNC and WPEND flags from RTC_SR1 and RTC_SR0.
15 14 13 12 11 10 9
1
1
0
0
WSYNCALM2MIR (R)
Synchronization status of posted writes
to RTC Alarm 2 Register
WSYNCCR1MIR (R)
Synchronization status of posted writes
to RTC Control 1 Register
WPNDALM2MIR (R)
Pending status of posted writes to RTC
Alarm 2 Register
WPNDCR1MIR (R)
Pending status of posted writes to RTC
Control 1 Register
TRMBDYMIR (R)
Mirror of the RTCTRMBDY field of RTC
Modulo Register
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CNTINT (R/W1C)
RTC count interrupt source
PSINT (R/W1C)
RTC prescaled, modulo-1 boundary
interrupt source
TRMINT (R/W1C)
RTC Trim interrupt source
CNTROLLINT (R/W1C)
RTC count roll-over interrupt source
CNTMOD60ROLLINT (R/W1C)
RTC modulo-60 count roll-over interrupt
source
CNTROLL (R)
RTC count roll-over
CNTMOD60ROLL (R)
RTC count modulo-60 roll-over
Figure 20-28: RTC_SR2 Register Diagram
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–69
ADuCM302x RTC Register Descriptions
Table 20-29:
RTC_SR2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 WSYNCALM2MIR
(R/NW)
Synchronization status of posted writes to RTC Alarm 2 Register.
WSYNCALM2 indicates if the effects of a posted write to RTC_ALM2 are visible to the
CPU.
If WSYNCALM2 is low, a posted write to RTC_ALM2 is currently queued up or in the
process of being executed, but the results of this transaction are not yet visible to the
CPU. When WSYNCALM2 goes high and thereby activates the
RTC_SR0.WSYNCINT sticky interrupt source, the effects of a write to RTC_ALM2 are
then available to the processor.
0 Results of a posted write to RTC_CR1 are not yet visible
by the CPU.
1 Results of a posted write to RTC_CR1 are visible by the
CPU.
14 WSYNCCR1MIR
(R/NW)
Synchronization status of posted writes to RTC Control 1 Register.
WSYNCCR1 indicates if the effects of a posted write to RTC_CR1 are visible to the
CPU.
If WSYNCCR1 is low, a posted write to RTC_CR1 is currently queued up or in the
process of being executed, but the results of this transaction are not yet visible to the
CPU. When WSYNCCR1 goes high and thereby activates the RTC_SR0.WSYNCINT
sticky interrupt source, the effects of a write to RTC_CR1 are then available to the processor.
0 The RTC can accept a new posted write to RTC_CR1.
1 A previously-posted write to RTC_CR1 is still awaiting
execution, so no new posting to this MMR can be accepted.
13 WPNDALM2MIR
(R/NW)
Pending status of posted writes to RTC Alarm 2 Register.
WPENDALM2 indicates if a posted register write to RTC_ALM2 is currently pending
(i.e. buffered and enqueued) and awaiting execution and therefore no further write to
the same MMR can be accepted at this time.
0 Results of a posted write to RTC_CR1 are not yet visible
by the CPU.
1 Results of a posted write to RTC_CR1 are visible by the
CPU.
20–70
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-29:
RTC_SR2 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12 WPNDCR1MIR
(R/NW)
Pending status of posted writes to RTC Control 1 Register.
WPENDCR1 indicates if a posted register write to RTC_CR1 is currently pending (i.e.
buffered and enqueued) and awaiting execution and therefore no further write to the
same MMR can be accepted at this time.
0 The RTC can accept a new posted write to RTC_CR1.
1 A previously-posted write to RTC_CR1 is still awaiting
execution, so no new posting to this MMR can be accepted.
7 TRMBDYMIR
(R/NW)
6 CNTMOD60ROLL
(R/NW)
Mirror of the RTCTRMBDY field of RTC Modulo Register.
RTCTRMBDY_MIRROR is a read-only mirror of the value of RTC_MOD.TRMBDY
MMR. It is included here so that when RTC_SR2 is read, the influence will be indicated of any trimming on a roll-over of the main RTC count or its modulo-60 equivalent.
RTC count modulo-60 roll-over.
It indicates whether the current modulo-60 value of the RTC count given by
RTC_MOD.CNTMOD60 MMR has come about due to a roll-over from/through its maximum possible value to/through its minimum possible value when incremented at the
most recent, prescaled time unit. (Note that trimming can cause the "through" rather
than the "from" or "to" cases mentioned above.)
When the CPU reacts to an interrupt due to the RTC_SR2.CNTMOD60ROLLINT interrupt source, or alternatively if the CPU coincidentally when inspecting RTC_SR2
sees RTC_SR2.CNTMOD60ROLLINT stickily set, it can use RTC_SR2.CNTMOD60ROLL
to confirm if the value in RTCCNTMOD60 is still reflective of the roll-over or has
moved on since the actual occurrence. The latter could be the case if the CPU were
tardy in its response to an RTC interrupt caused by RTC_SR2.CNTMOD60ROLLINT or
else if RTC_SR2.CNTMOD60ROLLINT were not enabled as a contributory interrupt
source for the RTC.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 The modulo-60 value of the RTC real-time count in
RTCCNTMOD60 has not arisen due to a roll-over.
1 The modulo-60 value of the RTC real-time count currently in RTCCNTMOD60 has rolled over from a value at or within trimming distance of its maximum to a
value at or within trimming distance of its minimum.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–71
ADuCM302x RTC Register Descriptions
Table 20-29:
RTC_SR2 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5 CNTROLL
(R/NW)
RTC count roll-over.
It indicates whether the current value of the RTC real-time count given by
{RTC_CNT1, RTC_CNT0} . {RTC_CNT2} has come about due to a roll-over from/
through its maximum possible value to/through its minimum possible value when incremented at the most recent, prescaled time unit. (Note that trimming can cause the
"through" rather than the "from" or "to" cases mentioned above.)
When the CPU reacts to an interrupt due to the RTCCNTROLLINT interrupt
source, or alternatively if the CPU [coincidentally when inspecting RTC_SR2 sees
RTC_SR2.CNTROLLINT stickily set, it can use RTC_SR2.CNTROLL to confirm if the
values in RTC_CNT1, RTC_CNT0 and RTC_CNT2 are still reflective of the roll-over or
have moved on since the actual occurrence. The latter could be the case if the CPU
were tardy in its response to an RTC interrupt caused by RTC_SR2.CNTROLLINT or
else if RTC_SR2.CNTROLLINT were not enabled as a contributory interrupt source for
the RTC.
0 The RTC real-time count in {RTC_CNT1, RTC_CNT0} .
{RTC_CNT2} has not arisen due to a roll-over.
1 The RTC real-time count currently in {RTC_CNT1,
RTC_CNT0} . {RTC_CNT2} has rolled over from a value
at or within trimming distance of its maximum to a value at or within trimming distance of its minimum.
4 CNTMOD60ROLLINT
(R/W1C)
RTC modulo-60 count roll-over interrupt source.
It sticks active high when the modulo-60 equivalent of the {RTC_CNT1, RTC_CNT0}
count value rolls over from 59 to zero or is trimmed such that these values are spanned.
Such a roll-over event happens every 60 prescaled increments of the RTC count, or
fewer if positive (additive) trimming is active.
Note that for RTC_SR2.CNTMOD60ROLLINT to cause an interrupt from the RTC, the
corresponding enable bit for this interrupt fan-in term,
RTC_CR1.CNTMOD60ROLLINTEN must be active high.
This interrupt source is cleared by writing one to its bit position in RTC_SR2.
Note that this bit field only exists in RTC1. In RTC0, the field is reserved and reads
back as zero.
0 The modulo-60 value of {RTC_CNT1, RTC_CNT0} in
RTCCNTMOD60 has not rolled over since
RTC_SR2.CNTMOD60ROLLINT was last cleared.
1 The modulo-60 value of {RTCCNT1, RTCCNT0} in
RTCCNTMOD60 has rolled over since
RTC_SR2.CNTMOD60ROLLINT was last cleared.
20–72
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-29:
RTC_SR2 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 CNTROLLINT
(R/W1C)
RTC count roll-over interrupt source.
It sticks active high when the {RTC_CNT1, RTC_CNT0} count value rolls over from
(2^32-1) to zero or is trimmed such that the trim increment causes the RTC to pass
through (potentially spanning) these maximum and minimum values.
Note that for RTC_SR2.CNTROLLINT to cause an interrupt from the RTC, the corresponding enable bit for this interrupt fan-in term, RTC_CR1.CNTROLLINTEN must
be active high.
This interrupt source is cleared by writing one to its bit position in RTC_SR2.
Note that in RTC0, the CPU can only obtain information about
RTC_SR2.CNTROLLINT by reading it. RTC_SR2.CNTROLLINT cannot be enabled as
an interrupt fan-in term for RTC0 because of the absence of the
RTC_CR1.CNTROLLINTEN. In contrast, full interrupt capability is available for
RTC1.
0 {RTC_CNT1, RTC_CNT0} has not rolled over since
RTC_SR2.CNTROLLINT was last cleared.
1 {RTC_CNT1, RTC_CNT0} has rolled over since
RTC_SR2.CNTROLLINT was last cleared.
2 TRMINT
(R/W1C)
RTC Trim interrupt source.
It sticks active high when a trim boundary occurs at the end of an enabled trim interval and the value of {RTC_CNT1, RTC_CNT0} is adjusted according to the settings of
RTC_TRM.
Note that for RTC_SR2.TRMINT to cause an interrupt from the RTC, the corresponding enable bit for this interrupt fan-in term, RTC_CR1.RTCTRMINTEN, must be active
high.
This interrupt source is cleared by writing one to its bit position in RTC_SR2.
Note that in RTC0, the CPU can only obtain information about RTC_SR2.TRMINT
by reading it. RTC_SR2.TRMINT cannot be enabled as an interrupt fan-in term for
RTC0 because of the absence of the RTC_CR1.RTCTRMINTEN In contrast, full interrupt capability is available for RTC1.
0 An RTC trim interval boundary has not occurred since
RTC_SR2.TRMINT was last cleared.
1 An RTC trim interval boundary has occurred since
RTC_SR2.TRMINT was last cleared.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–73
ADuCM302x RTC Register Descriptions
Table 20-29:
RTC_SR2 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 PSINT
(R/W1C)
RTC prescaled, modulo-1 boundary interrupt source.
It sticks active high whenever the gated clock which defines the prescaled RTC time
unit (and hence the advancement of the RTC count) is activated.
Note that for RTC_SR2.PSINT to cause an interrupt from the RTC, the corresponding enable bit for this interrupt fan-in term, RTC_CR1.PSINTEN, must be active high.
This interrupt source is cleared by writing one to its bit position in RTC_SR2.
Note that in RTC0, the CPU can only obtain information about RTC_SR2.PSINT by
reading it. RTC_SR2.PSINT cannot be enabled as an interrupt fan-in term for RTC0
because of the absence of the RTC_CR1.PSINTEN In contrast, full interrupt capability
is available for RTC1.
0 The prescaled gated clock for the RTC count in
{RTCCNT1, RTCCNT0, RTCCNT2} has not activated since RTC_SR2.PSINT was last cleared.
1 The prescaled gated clock for the RTC count in
{RTCCNT1, RTCCNT0, RTCCNT2} has activated
since RTC_SR2.PSINT was last cleared.
0 CNTINT
(R/W1C)
RTC count interrupt source.
It sticks active high whenever the value of {RTC_CNT1, RTC_CNT0} changes. Note that
such an event is not the same as the occurrence of a prescaled RTC time unit
(RTC_SR2.PSINT), since the RTC count can either be redefined or trimmed which
may or may not lead to value changes.
This interrupt source is cleared by writing one to its bit position in RTC_SR2.
Note that in RTC0, the CPU can only obtain information about RTC_SR2.CNTINT
by reading it. RTC_SR2.CNTINT cannot be enabled as an interrupt fan-in term for
RTC0 because of the absence of the RTC_CR1.CNTINTEN. In contrast, full interrupt
capability is available for RTC1.
0 The value of {RTC_CNT1, RTC_CNT0} has not changed
since RTC_SR2.CNTINT was last cleared.
1 The value of {RTC_CNT1, RTC_CNT0} has changed
since RTC_SR2.CNTINT was last cleared.
20–74
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Status 3
It is a status register containing write-one-to-clear, interrupt sources which stick active high whenever events occur
for enabled input capture or output compare channels. Note that this register only exists in RTC1. In RTC0, the
register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RTCOC1IRQ (R/W1C)
Sticky Interrupt Source for Output Compare
Channel 1
RTCIC0IRQ (R/W1C)
Sticky Interrupt Source for the RTC Input
Capture Channel 0
ALMINTMIR (R)
Read-only mirror of the ALMINT interrupt
source in RTC Status 0 Register, acting
as RTCOC0IRQ
RTCIC2IRQ (R/W1C)
Sticky Interrupt Source for the RTC Input
Capture Channel 2
RTCIC3IRQ (R/W1C)
Sticky Interrupt Source for the RTC Input
Capture Channel 3
RTCIC4IRQ (R/W1C)
Sticky Interrupt Source for the RTC Input
Capture Channel 4
Figure 20-29: RTC_SR3 Register Diagram
Table 20-30:
RTC_SR3 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9 RTCOC1IRQ
(R/W1C)
Sticky Interrupt Source for Output Compare Channel 1.
This interrupt source sticks high whenever a scheduled alarm event occurs for the enabled (via RTC_CR3OC.RTCOC1EN) output compare channel RTC_OC1.
RTC_SR3.RTCOC1IRQ is cleared by writing a value of 1'b1 to its bit position. If enabled via RTC_CR3OC.RTCOC1IRQEN, the RTC_SR3.RTCOC1IRQ source is included
as a contributory term to the RTC interrupt lines sent to the CPU and the wake-up
controller.
0 No enabled output compare event has occurred on the
RTC_OC1 channel since the CPU last cleared this bit.
1 An enabled output compare event has occurred on the
RTC_OC1 channel since the CPU last cleared this bit.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–75
ADuCM302x RTC Register Descriptions
Table 20-30:
RTC_SR3 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
8 ALMINTMIR
(R/NW)
Read-only mirror of the ALMINT interrupt source in RTC Status 0 Register, acting as
RTCOC0IRQ.
Read-only mirror of RTC_SR0.ALMINT which is the equivalent of an RTCOC0IRQ
interrupt source. Note that the 47-bit absolute-time alarm function in the RTC which
causes RTC_SR0.ALMINT to activate doubles up as the RTC_OC0 output compare
channel.
0 An ALMINT interrupt event has not occurred since the
RTC_SR0.ALMINT interrupt source bit was last cleared
by the CPU.
1 An ALMINT interrupt event has occurred since the
RTC_SR0.ALMINT interrupt source bit was last cleared
by the CPU.
4 RTCIC4IRQ
(R/W1C)
Sticky Interrupt Source for the RTC Input Capture Channel 4.
This interrupt source in RTC_SR3 sticks high whenever an enabled (via
RTC_CR2IC.RTCIC4EN) input requester to the RTC asks for a snapshot of the RTC
count to be taken for the RTC_IC4 input capture channel. It is cleared by writing a
value of 1'b1 to its bit position.
0 No enabled input capture event has occurred on the
RTC_IC4 channel since the CPU last cleared this bit.
1 An enabled input capture event has occurred on the
RTC_IC4 channel since the CPU last cleared this bit.
3 RTCIC3IRQ
(R/W1C)
Sticky Interrupt Source for the RTC Input Capture Channel 3.
This interrupt source in RTC_IC3 sticks high whenever an enabled (via
RTC_CR2IC.RTCIC3EN) input requester to the RTC asks for a snapshot of the RTC
count to be taken for the RTC_IC3 input capture channel. It is cleared by writing a
value of 1'b1 to its bit position.
0 No enabled input capture event has occurred on the
RTC_IC3 channel since the CPU last cleared this bit.
1 An enabled input capture event has occurred on the
RTC_IC3 channel since the CPU last cleared this bit.
20–76
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-30:
RTC_SR3 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 RTCIC2IRQ
(R/W1C)
Sticky Interrupt Source for the RTC Input Capture Channel 2.
This interrupt source in RTC_SR3 sticks high whenever an enabled (via
RTC_CR2IC.RTCIC2EN) input requester to the RTC asks for a snapshot of the RTC
count to be taken for the RTC_IC2 input capture channel. It is cleared by writing a
value of 1'b1 to its bit position.
0 No enabled input capture event has occurred on the
RTC_IC2 channel since the CPU last cleared this bit.
1 An enabled input capture event has occurred on the
RTC_IC2 channel since the CPU last cleared this bit.
0 RTCIC0IRQ
(R/W1C)
Sticky Interrupt Source for the RTC Input Capture Channel 0.
This interrupt source in RTC_SR3 sticks high whenever an enabled (via
RTC_CR2IC.RTCIC0EN) input requester (non-CPU) to the RTC asks for a snapshot
of the RTC count to be taken for the RTC_IC0 input capture channel. It is cleared by
writing a value of 1'b1 to its bit position. Note that RTC_SR3.RTCIC0IRQ is unaffected by CPU-prompted snapshots, requested by writing a specific key value of
0x7627 to the RTC_GWY register.
0 No enabled, non-CPU input capture event has occurred
on the RTC_IC0 channel since the CPU last cleared
this bit.
1 An enabled, non-CPU input capture event has occurred
on the RTC_IC0 channel since the CPU last cleared
this bit.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–77
ADuCM302x RTC Register Descriptions
RTC Status 4
It is a status register which provides the synchronization status of posted writes and posted reads to those registers
related to input capture and output control which are sourced in the 32 kHz always-on half of the RTC. A WSYNC
value of zero for a given register means the results of a previously-posted write to that register are not yet visible to
the CPU. A WSYNC value of one for a register means no posted write to that register has yet to complete execution.
Likewise, an RSYNC value of zero for a given register means the results of a previously-posted read of that register
are not yet visible to the CPU. An RSYNC value of one for a register means no posted read of that register has yet to
complete execution. Note that RTC_SR4 only exists in RTC1. In RTC0, the register address is reserved and reads
back as the register's reset value.
15 14 13 12 11 10 9
0
1
1
1
0
RSYNCIC4 (R)
Synchronization status of posted reads
of RTC Input Channel 4
RSYNCIC3 (R)
Synchronization status of posted reads
of RTC Input Channel 3
RSYNCIC2 (R)
Synchronization status of posted reads
of RTC Input Channel 2
RSYNCIC0 (R)
Synchronization status of posted reads
of RTC Input Channel 0
1
0
8
7
6
5
4
3
2
1
0
0
0
1
1
1
1
1
1
1
WSYNCSR3 (R)
Synchronization status of posted clearances
to interrupt sources in RTC Status 3
Register
WSYNCCR2IC (R)
Synchronization status of posted writes
to RTC Control 2 for Configuring Input
Capture Channels Register
WSYNCCR3OC (R)
Synchronization status of posted writes
to RTC Control 3 for Configuring Output
Compare Channel Register
WSYNCOC1 (R)
Synchronization status of posted writes
to RTC Output Compare Channel 1 Register
WSYNCCR4OC (R)
Synchronization status of posted writes
to RTC Control 4 for Configuring Output
Compare Channel Register
WSYNCOC1ARL (R)
Synchronization status of posted writes
to RTC Auto-Reload for Output Compare
Channel 1 Register
WSYNCOCMSK (R)
Synchronization status of posted writes
to RTC Masks for Output Compare Channel
Register
Figure 20-30: RTC_SR4 Register Diagram
20–78
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-31:
RTC_SR4 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 RSYNCIC4
(R/NW)
Synchronization status of posted reads of RTC Input Channel 4.
It indicates if the effects of a posted write to RTCOC4 are visible to the CPU.
If RTC_SR4.RSYNCIC4 is low, a posted write to RTCOC4 is currently queued up or
in the process of being executed, but the results of this transaction are not yet visible to
the CPU. When RTC_SR4.RSYNCIC4 goes high and thereby activates the WSYNCINT sticky interrupt source, the effects of a write to RTCOC4 are then available to
the processor.
0 The results (change in unread status) of a read of
RTC_IC4 are not yet visible to the CPU.
1 The results (change in unread status) of a read of
RTC_IC4 are now visible to the CPU.
13 RSYNCIC3
(R/NW)
Synchronization status of posted reads of RTC Input Channel 3.
It indicates if the effects of a posted write to RTCOC4 are visible to the CPU.
If RTC_SR4.RSYNCIC3 is low, a posted write to RTCOC4 is currently queued up or
in the process of being executed, but the results of this transaction are not yet visible to
the CPU. When RTC_SR4.RSYNCIC3 goes high and thereby activates the WSYNCINT sticky interrupt source, the effects of a write to RTCOC4 are then available to
the processor.
0 The results (change in unread status) of a read of
RTC_IC3 are not yet visible to the CPU.
1 The results (change in unread status) of a read of
RTC_IC3 are now visible to the CPU.
12 RSYNCIC2
(R/NW)
Synchronization status of posted reads of RTC Input Channel 2.
It indicates if the effects of a posted write to RTCOC4 are visible to the CPU.
If RTC_SR4.RSYNCIC2 is low, a posted write to RTCOC4 is currently queued up or
in the process of being executed, but the results of this transaction are not yet visible to
the CPU. When RTC_SR4.RSYNCIC2 goes high and thereby activates the WSYNCINT sticky interrupt source, the effects of a write to RTCOC4 are then available to
the processor.
0 The results (change in unread status) of a read of
RTC_IC2 are not yet visible to the CPU.
1 The results (change in unread status) of a read of
RTC_IC2 are now visible to the CPU.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–79
ADuCM302x RTC Register Descriptions
Table 20-31:
RTC_SR4 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
10 RSYNCIC0
(R/NW)
Synchronization status of posted reads of RTC Input Channel 0.
It indicates if the effects of a posted write to RTCOC4 are visible to the CPU.
If RTC_SR4.RSYNCIC0 is low, a posted write to RTCOC4 is currently queued up or
in the process of being executed, but the results of this transaction are not yet visible to
the CPU. When RTC_SR4.RSYNCIC0 goes high and thereby activates the
WSYNCINT sticky interrupt source, the effects of a write to RTCOC4 are then available to the processor.
0 The results (change in unread status) of a read of
RTC_IC0 are not yet visible to the CPU.
1 The results (change in unread status) of a read of
RTC_IC0 are now visible to the CPU.
6 WSYNCOC1
(R/NW)
Synchronization status of posted writes to RTC Output Compare Channel 1 Register.
It indicates if the effects of a posted write to RTC_OC1 are visible to the CPU.
If RTC_SR4.WSYNCOC1 is low, a posted write to RTC_OC1 is currently queued up or
in the process of being executed, but the results of this transaction are not yet visible to
the CPU. When RTC_SR4.WSYNCOC1 goes high and thereby activates the WSYNCINT sticky interrupt source, the effects of a write to RTC_OC1 are then available to
the processor.
0 The results of a posted write to RTC_OC1 are not yet
visible to the CPU.
1 The results of a posted write to RTC_OC1 are now visible to the CPU.
5 WSYNCOC1ARL
(R/NW)
Synchronization status of posted writes to RTC Auto-Reload for Output Compare
Channel 1 Register.
It indicates if the effects of a posted write to RTC_OC1ARL are visible to the CPU.
If RTC_SR4.WSYNCOC1ARL is low, a posted write to RTC_OC1ARL is currently
queued up or in the process of being executed, but the results of this transaction are
not yet visible to the CPU. When RTC_SR4.WSYNCOC1ARL goes high and thereby activates the WSYNCINT sticky interrupt source, the effects of a write to RTC_OC1ARL
are then available to the processor.
0 The results of a posted write to RTC_OC1ARL are not
yet visible to the CPU.
1 The results of a posted write to RTC_OC1ARL are now
visible to the CPU.
20–80
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-31:
RTC_SR4 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
4 WSYNCOCMSK
(R/NW)
Synchronization status of posted writes to RTC Masks for Output Compare Channel
Register.
It indicates if the effects of a posted write to RTC_OCMSK are visible to the CPU.
If RTC_SR4.WSYNCOCMSK is low, a posted write to RTC_OCMSK is currently queued
up or in the process of being executed, but the results of this transaction are not yet
visible to the CPU. When RTC_SR4.WSYNCOCMSK goes high and thereby activates
the WSYNCINT sticky interrupt source, the effects of a write to RTC_OCMSK are then
available to the processor.
0 The results of a posted write to RTC_OCMSK are not yet
visible to the CPU.
1 The results of a posted write to RTC_OCMSK are now
visible to the CPU.
3 WSYNCCR4OC
(R/NW)
Synchronization status of posted writes to RTC Control 4 for Configuring Output
Compare Channel Register.
It indicates if the effects of a posted write to RTC_CR4OC are visible to the CPU.
If RTC_SR4.WSYNCCR4OC is low, a posted write to RTC_CR4OC is currently queued
up or in the process of being executed, but the results of this transaction are not yet
visible to the CPU. When RTC_SR4.WSYNCCR4OC goes high and thereby activates
the WSYNCINT sticky interrupt source, the effects of a write to RTC_CR4OC are then
available to the processor.
0 The results of a posted write to RTC_CR4OC are not yet
visible to the CPU.
1 The results of a posted write to RTC_CR4OC are now
visible to the CPU.
2 WSYNCCR3OC
(R/NW)
Synchronization status of posted writes to RTC Control 3 for Configuring Output
Compare Channel Register.
It indicates if the effects of a posted write to RTC_CR3OC are visible to the CPU.
If RTC_SR4.WSYNCCR3OCis low, a posted write to RTC_CR3OC is currently queued
up or in the process of being executed, but the results of this transaction are not yet
visible to the CPU. When RTC_SR4.WSYNCCR3OC goes high and thereby activates
the WSYNCINT sticky interrupt source, the effects of a write to RTC_CR3OC are then
available to the processor.
0 The results of a posted write to RTC_CR3OC are not yet
visible to the CPU.
1 The results of a posted write to RTC_CR3OC are now
visible to the CPU.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–81
ADuCM302x RTC Register Descriptions
Table 20-31:
RTC_SR4 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 WSYNCCR2IC
(R/NW)
Synchronization status of posted writes to RTC Control 2 for Configuring Input Capture Channels Register.
It indicates if the effects of a posted write to RTC_CR2IC are visible to the CPU.
If RTC_SR4.WSYNCCR2IC is low, a posted write to RTC_CR2IC is currently queued
up or in the process of being executed, but the results of this transaction are not yet
visible to the CPU. When RTC_SR4.WSYNCCR2IC goes high and thereby activates
the WSYNCINT sticky interrupt source, the effects of a write to RTC_CR2IC are then
available to the processor.
0 The results of a posted write to RTC_CR2IC are not yet
visible to the CPU.
1 The results of a posted write to RTC_CR2IC are now
visible to the CPU.
0 WSYNCSR3
(R/NW)
Synchronization status of posted clearances to interrupt sources in RTC Status 3 Register.
It indicates if the effects of a posted write to RTC_SR3 are visible to the CPU.
RTC_SR4.WSYNCSR3 always reads back as 1 because the only writes which can or
need to be posted to RTC_SR3 are clearances of 32 kHz sourced interrupt sources.
These sources are RTCIC0IRQ, RTCIC1IRQ, RTCIC2IRQ, RTCIC3IRQ,
RTCIC4IRQ, RTCOC1IRQ, RTCOC2IRQ, RTCOC3IRQ and RTCOC4IRQ. The
interrupt sources concerned by such posted clearances to RTC_SR3 are masked (to inactive) by the RTC for the duration of the posting until actual execution. The net effect of this is that the CPU always sees an interrupt source as being immediately
cleared, regardless of where it is sourced. For this reason, RTC_SR4.WSYNCSR3 always
reads back as one.
0 Results of a posted interrupt clearance to RTC_SR3 are
not yet visible to the CPU.
1 Results of a posted interrupt clearance to RTC_SR3 are
visible to the CPU.
20–82
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
RTC Status 5
It is a status register which provides the pending (i.e. buffered and enqueued) status of posted writes to those registers related to input capture and output control which are sourced in the 32 kHz always-on half of the RTC. A
WPEND value of one for a given register means a previously-posted write to that register is currently queued up in a
one-deep buffer and has yet to begin execution. When WPEND is therefore one, no further write to the register in
question can be accommodated by the RTC until the existing write begins execution and vacates the buffer. When
WPEND is zero for a register, there is room in the RTC to accept a new posted write to that register. Note that
RTC_SR5 only exists in RTC1. In RTC0, the register address is reserved and reads back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
RPENDIC4 (R)
Pending status of posted reads of RTC
Input Channel 4
RPENDIC3 (R)
Pending status of posted reads of RTC
Input Channel 3
RPENDIC2 (R)
Pending status of posted reads of RTC
Input Channel 2
RPENDIC0 (R)
Pending status of posted reads of RTC
Input Channel 0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
WPNDSR0 (R)
Pending status of posted clearances
of interrupt sources in RTC Status 3
Register
WPENDCR2IC (R)
Pending status of posted writes to RTC
Control 2 for Configuring Input Capture
Channels Register
WPENDCR3OC (R)
Pending status of posted writes to RTC
Control 3 for Configuring Output Compare
Channel Register
WPENDOC1 (R)
Pending status of posted writes to Output
Compare Channel 1
WPENDCR4OC (R)
Pending status of posted writes to RTC
Control 4 for Configuring Output Compare
Channel Register
WPENDOC1ARL (R)
Pending status of posted writes to RTC
Auto-Reload for Output Compare Channel
1 Register
WPENDOCMSK (R)
Pending status of posted writes to RTC
Masks for Output Compare Channel
Register
Figure 20-31: RTC_SR5 Register Diagram
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–83
ADuCM302x RTC Register Descriptions
Table 20-32:
RTC_SR5 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
14 RPENDIC4
(R/NW)
Pending status of posted reads of RTC Input Channel 4.
WSYNCOC4 indicates if the effects of a posted write to RTCOC4 are visible to the
CPU.
If WSYNCOC4 is low, a posted write to RTCOC4 is currently queued up or in the
process of being executed, but the results of this transaction are not yet visible to the
CPU. When WSYNCOC4 goes high and thereby activates the WSYNCINT sticky
interrupt source, the effects of a write to RTCOC4 are then available to the processor.
0 The RTC can accept new reads of RTC_IC4 and post
this change in the unread status (to read) to the 32 kHzsourced RTC_SR6.RTCIC4UNR bit field.
1 A previously-posted change (to read) in the unread status of RTC_IC4, maintained at RTC_SR6.RTCIC4UNR
in the 32kHz domain, is still awaiting execution. However, additional reads of RTC_IC4 can be aggregated into the existing, pending transaction.
13 RPENDIC3
(R/NW)
Pending status of posted reads of RTC Input Channel 3.
WSYNCOC4 indicates if the effects of a posted write to RTCOC4 are visible to the
CPU.
If WSYNCOC4 is low, a posted write to RTCOC4 is currently queued up or in the
process of being executed, but the results of this transaction are not yet visible to the
CPU. When WSYNCOC4 goes high and thereby activates the WSYNCINT sticky
interrupt source, the effects of a write to RTCOC4 are then available to the processor.
0 The RTC can accept new reads of RTC_IC3 and post
this change in the unread status (to read) to the 32kHzsourced RTC_SR6.RTCIC3UNR bit field.
1 A previously-posted change (to read) in the unread status of RTC_IC3, maintained at RTC_SR6.RTCIC3UNR
in the 32kHz domain, is still awaiting execution. However, additional reads of RTC_IC3 can be aggregated into the existing, pending transaction.
20–84
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-32:
RTC_SR5 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
12 RPENDIC2
(R/NW)
Pending status of posted reads of RTC Input Channel 2.
WSYNCOC4 indicates if the effects of a posted write to RTCOC4 are visible to the
CPU.
If WSYNCOC4 is low, a posted write to RTCOC4 is currently queued up or in the
process of being executed, but the results of this transaction are not yet visible to the
CPU. When WSYNCOC4 goes high and thereby activates the WSYNCINT sticky
interrupt source, the effects of a write to RTCOC4 are then available to the processor.
0 The RTC can accept new reads of RTC_IC2 and post
this change in the unread status (to read) to the 32 kHzsourced RTC_SR6.RTCIC2UNR bit field.
1 A previously-posted change (to read) in the unread status of RTC_IC2, maintained at RTC_SR6.RTCIC2UNR
in the 32kHz domain, is still awaiting execution. However, additional reads of RTC_IC2 can be aggregated into the existing, pending transaction.
10 RPENDIC0
(R/NW)
Pending status of posted reads of RTC Input Channel 0.
WSYNCOC4 indicates if the effects of a posted write to RTCOC4 are visible to the
CPU.
If WSYNCOC4 is low, a posted write to RTCOC4 is currently queued up or in the
process of being executed, but the results of this transaction are not yet visible to the
CPU. When WSYNCOC4 goes high and thereby activates the WSYNCINT sticky
interrupt source, the effects of a write to RTCOC4 are then available to the processor.
0 The RTC can accept new reads of RTC_IC0 and post
this change in the unread status (to read) to the 32kHzsourced RTC_SR6.RTCIC0UNR bit field.
1 A previously-posted change (to read) in the unread status of RTC_IC0, maintained at RTC_SR6.RTCIC0UNR
in the 32kHz domain, is still awaiting execution. However, additional reads of RTC_IC0 can be aggregated into the existing, pending transaction.
6 WPENDOC1
(R/NW)
Pending status of posted writes to Output Compare Channel 1.
It indicates if a posted register write to RTC_OC1 is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to RTC_OC1.
1 A previously-posted write to RTC_OC1 is still awaiting
execution, so no new posting to this MMR can be accepted.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–85
ADuCM302x RTC Register Descriptions
Table 20-32:
RTC_SR5 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5 WPENDOC1ARL
(R/NW)
Pending status of posted writes to RTC Auto-Reload for Output Compare Channel 1
Register.
It indicates if a posted register write to RTC_OC1ARL is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_OC1ARL.
1 A previously-posted write to RTC_OC1ARL is still awaiting execution, so no new posting to this MMR can be
accepted.
4 WPENDOCMSK
(R/NW)
Pending status of posted writes to RTC Masks for Output Compare Channel Register.
It indicates if a posted register write to RTC_OCMSK is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_OCMSK.
1 A previously-posted write to RTC_OCMSK is still awaiting execution, so no new posting to this MMR can be
accepted.
3 WPENDCR4OC
(R/NW)
Pending status of posted writes to RTC Control 4 for Configuring Output Compare
Channel Register.
It indicates if a posted register write to RTC_CR4OC is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_CR4OC.
1 A previously-posted write to RTC_CR4OC is still awaiting execution, so no new posting to this MMR can be
accepted.
20–86
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-32:
RTC_SR5 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 WPENDCR3OC
(R/NW)
Pending status of posted writes to RTC Control 3 for Configuring Output Compare
Channel Register.
It indicates if a posted register write to RTC_CR3OC is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_CR3OC.
1 A previously-posted write to RTC_CR3OC is still awaiting execution, so no new posting to this MMR can be
accepted.
1 WPENDCR2IC
(R/NW)
Pending status of posted writes to RTC Control 2 for Configuring Input Capture
Channels Register.
It indicates if a posted register write to RTC_CR2IC is currently pending (i.e. buffered
and enqueued) and awaiting execution and therefore no further write to the same
MMR can be accepted at this time.
0 The RTC can accept a new posted write to
RTC_CR2IC.
1 A previously-posted write to RTC_CR2IC is still awaiting execution, so no new posting to this MMR can be
accepted.
0 WPNDSR0
(R/NW)
Pending status of posted clearances of interrupt sources in RTC Status 3 Register.
It indicates if posted clearances of interrupt sources in RTC_SR3 are currently pending
(i.e. buffered and enqueued) and awaiting execution. Note the further posted clearances can always be accepted and accumulated into the same pending transaction for
RTC_SR3, as such an accumulation is non-destructive of previously-posted clearances.
This is in contrast to the case for other MMRs where posted write data (as opposed to
posted clearances) cannot be aggregated into one transaction.
0 The RTC can accept new posted clearances of interrupt
sources in RTCSR3 located in the 32kHz domain.
1 A previously-posted clearance of interrupt sources in
RTCSR3 maintained in the 32kHz domain is still
awaiting execution. Additional clearances can still be aggregated into the existing, pending transaction.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–87
ADuCM302x RTC Register Descriptions
RTC Status 6
It is a status register which provides the unread status of snapshots of input-capture channels, RTC_IC0, RTC_IC2,
RTC_IC3 and RTC_IC4. Both the captured snapshots themselves and the sticky flags, RTCIC<channel number>UNR, which indicate if the snapshots have been read by the CPU, are all sourced in the in the 32 kHz alwayson half of the RTC. Note that RTC_SR6 only exists in RTC1. In RTC0, the register address is reserved and reads
back as the register's reset value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
RTCFRZCNTPTR (R)
Pointer for the triple-read sequence
of the RTC Freeze Count MMR
RTCIC0UNR (R)
Sticky unread status of the RTC Input
Capture Channel 0
RTCIC0SNAP (R)
Confirmation that RTC Snapshot 0, 1,
2 registers reflect the value of RTC Input
Capture Channel 0
RTCIC2UNR (R)
Sticky unread status of the RTC Input
Capture Channel 2
RTCIC4UNR (R)
Sticky unread status of the RTC Input
Capture Channel 4
RTCIC3UNR (R)
Sticky unread status of the RTC Input
Capture Channel 3
Figure 20-32: RTC_SR6 Register Diagram
20–88
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-33:
RTC_SR6 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
10:9 RTCFRZCNTPTR
(R/NW)
Pointer for the triple-read sequence of the RTC Freeze Count MMR.
It indicates the sequence number for the next read in triple-read sequences of the
RTC_FRZCNT MMR.
The RTC Freeze Count MMR, RTC_FRZCNT, allows a coherent triple 16-bit read of
the 47-bit RTC count contained in {RTC_CNT2, RTC_CNT1, RTC_CNT0}.
RTC_FRZCNT is always read in sequences of three reads (although these can be spread
out in time, or have other APB accesses interspersed), such that the first read in the
sequence returns the current value of RTC_CNT0. Simultaneously, with this first read, a
snapshot is taken and frozen of the value of {RTC_CNT2, RTC_CNT1} so that in the
second and third reads in the sequence of RTC_FRZCNT, the snapshot values of
RTC_CNT2 and RTC_CNT1 are returned respectively.
In this way, a triple read of RTC_FRZCNT gives an overall 47 bits of the RTC count
which belong together and are coherent with each other, even though during this
RTC_FRZCNT read-out sequence, the actual (continuing) value of {RTC_CNT2,
RTC_CNT1, RTC_CNT0} keeps advancing while the RTC counts real time.
The RTC_SR6 pointer MMR field both indicates the sequence number in the triple
read and also acts a read data select for the value returned when RTC_FRZCNT is read.
Normally, the RTC_SR6.RTCFRZCNTPTR pointer keeps advancing by one, starting
from 2'b00, with every read of RTC_FRZCNT, wrapping from 2'b10 to 2'b00.
However, if the CPU wishes to zero the RTC_SR6.RTCFRZCNTPTR pointer and thus
re-initialise the 0-1-2 sequence for reads of RTC_FRZCNT, the CPU can do this by
writing a software key, RTC_SW_RTCFRZCNT_KEY, of value 16'h9376, to the
RTC_GWY gateway MMR.
0 The next read of RTC_FRZCNT will cause both of the
following to happen : (i) The read data for
RTC_FRZCNT will be the current value of RTC_CNT0
and (ii) A coherent snapshot of the current value of
{RTC_CNT2, RTC_CNT1} will be taken for return during
the subsequent two reads of RTC_FRZCNT. The value
which can be read in RTC_SNAP0, RTC_SNAP1, and
RTC_SNAP2 is due to a software-initiated snapshot.
1 The next read of RTC_FRZCNT will be the second in a
triple-read sequence and will return the snapshot of
RTC_CNT1 which was taken when the first read of
RTC_FRZCNT in the sequence occurred.
2 The next read of RTC_FRZCNT will be the third in a triple-read sequence and will return the snapshot of
RTC_CNT2 which was taken when the first read of
RTC_FRZCNT in the sequence occurred.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–89
ADuCM302x RTC Register Descriptions
Table 20-33:
RTC_SR6 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
8 RTCIC0SNAP
(R/NW)
Confirmation that RTC Snapshot 0, 1, 2 registers reflect the value of RTC Input Capture Channel 0.
This flag indicates if RTC_SNAP0, RTC_SNAP1, and RTC_SNAP2 registers reflect the
value of the 47-bit RTC_IC0 channel or the value of a software-initiated snapshot of
the RTC count.
0 The value which can be read in RTCSNAP0,
RTCSNAP1 and RTCSNAP2 is due to a software-initiated snapshot.
1 The value which can be read in RTC_SNAP0,
RTC_SNAP1, and RTC_SNAP2 is due to an RTC_IC0
input-capture event.
4 RTCIC4UNR
(R/NW)
Sticky unread status of the RTC Input Capture Channel 4.
It is a sticky, 32 kHz sourced flag which indicates if a new, unread snapshot exists for
input capture channel RTC_IC4. RTC_SR6.RTCIC4UNR sticks high, just like
RTC_SR3.RTCIC4IRQ, upon an enabled capture event for RTC_IC4. However,
RTC_SR6.RTCIC4UNR is only de-activated low when the CPU actually reads a snapshot contained in the RTC_IC4 MMR.
Note that if RTC_CR2IC.RTCICOWUSEN is configured low, meaning don't overwrite
unread input capture snapshots, the value of RTC_SR6.RTCIC4UNR determines
whether a new capture event on the RTC_IC4 channel is allowed overwrite the contents of the RTC_IC4 MMR. Thus, if RTC_CR2IC.RTCICOWUSEN is zero and
RTC_SR6.RTCIC4UNR is one, no new input capture snapshot is taken into RTC_IC4
until the existing unread contents are first read.
Using RTC_CR2IC.RTCICOWUSEN and RTC_SR6.RTCIC4UNR in this way allows the
CPU the choice of having RTC_IC4 stick with the first, unread capture event on that
channel, as opposed to having RTC_IC4 stick with the most recent capture event, regardless of CPU reads. Both such captures modes are available to the CPU. The choice
of mode applies concurrently to all input capture channels.
0 No new, unread snapshot is contained in RTC_IC4 for
that input-capture channel.
1 An unread snapshot is contained in RTC_IC4 for that
input-capture channel.
20–90
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-33:
RTC_SR6 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 RTCIC3UNR
(R/NW)
Sticky unread status of the RTC Input Capture Channel 3.
It is a sticky, 32 kHz sourced flag which indicates if a new, unread snapshot exists for
input capture channel RTC_IC3. RTC_SR6.RTCIC3UNR sticks high, just like
RTC_SR3.RTCIC3IRQ, upon an enabled capture event for RTC_IC3. However,
RTC_SR6.RTCIC3UNR is only de-activated low when the CPU actually reads a snapshot contained in the RTC_IC3 MMR.
Note that if RTC_CR2IC.RTCICOWUSEN is configured low, meaning don't overwrite
unread input capture snapshots, the value of RTC_SR6.RTCIC3UNR determines
whether a new capture event on the RTC_IC3 channel is allowed overwrite the contents of the RTC_IC3 MMR. Thus, if RTC_CR2IC.RTCICOWUSEN is zero and
RTC_SR6.RTCIC3UNR is one, no new input capture snapshot is taken into RTC_IC3
until the existing unread contents are first read.
Using RTC_CR2IC.RTCICOWUSEN and RTC_SR6.RTCIC3UNR in this way allows the
CPU the choice of having RTC_IC3 stick with the first, unread capture event on that
channel, as opposed to having RTC_IC3 stick with the most recent capture event, regardless of CPU reads. Both such captures modes are available to the CPU. The choice
of mode applies concurrently to all input capture channels.
0 No new, unread snapshot is contained in RTC_IC3 for
that input-capture channel.
1 An unread snapshot is contained in RTC_IC3 for that
input-capture channel.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–91
ADuCM302x RTC Register Descriptions
Table 20-33:
RTC_SR6 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 RTCIC2UNR
(R/NW)
Sticky unread status of the RTC Input Capture Channel 2.
It is a sticky, 32 kHz sourced flag which indicates if a new, unread snapshot exists for
input capture channel RTC_IC2. RTC_SR6.RTCIC2UNR sticks high, just like
RTC_SR3.RTCIC2IRQ, upon an enabled capture event for RTC_IC2. However,
RTC_SR6.RTCIC2UNR is only de-activated low when the CPU actually reads a snapshot contained in the RTC_IC2 MMR.
Note that if RTC_CR2IC.RTCICOWUSEN is configured low, meaning don't overwrite
unread input capture snapshots, the value of RTC_SR6.RTCIC2UNR determines
whether a new capture event on the RTC_IC2 channel is allowed overwrite the contents of the RTC_IC2 MMR. Thus, if RTC_CR2IC.RTCICOWUSEN is zero and
RTC_SR6.RTCIC2UNR is one, no new input capture snapshot is taken into RTC_IC2
until the existing unread contents are first read.
Using RTC_CR2IC.RTCICOWUSEN and RTC_SR6.RTCIC2UNR in this way allows the
CPU the choice of having RTC_IC2 stick with the first, unread capture event on that
channel, as opposed to having RTC_IC2 stick with the most recent capture event, regardless of CPU reads. Both such captures modes are available to the CPU. The choice
of mode applies concurrently to all input capture channels.
0 No new, unread snapshot is contained in RTC_IC2 for
that input-capture channel.
1 An unread snapshot is contained in RTC_IC2 for that
input-capture channel.
20–92
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-33:
RTC_SR6 Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
0 RTCIC0UNR
(R/NW)
Sticky unread status of the RTC Input Capture Channel 0.
It is a sticky, 32 kHz sourced flag which indicates if a new, unread snapshot exists for
input capture channel RTC_IC0. RTC_SR6.RTCIC0UNR sticks high, just like
RTC_SR3.RTCIC0IRQ, upon an enabled capture event for RTC_IC0. However,
RTC_SR6.RTCIC0UNR is only de-activated low when the CPU actually reads a snapshot contained in the RTC_IC0 MMR.
Note that if RTC_CR2IC.RTCICOWUSEN is configured low, meaning don't overwrite
unread input capture snapshots, the value of RTC_SR6.RTCIC0UNR determines
whether a new capture event on the RTC_IC0 channel is allowed overwrite the contents of the RTC_IC0 MMR. Thus, if RTC_CR2IC.RTCICOWUSEN is zero and
RTC_SR6.RTCIC0UNR is one, no new input capture snapshot is taken into RTC_IC0
until the existing unread contents are first read.
Using RTC_CR2IC.RTCICOWUSEN and RTC_SR6.RTCIC0UNR in this way allows the
CPU the choice of having RTC_IC0 stick with the first, unread capture event on that
channel, as opposed to having RTC_IC0 stick with the most recent capture event, regardless of CPU reads. Both such captures modes are available to the CPU. The choice
of mode applies concurrently to all input capture channels.
0 No new, unread snapshot is contained in RTC_IC0 for
that input-capture channel.
1 An unread snapshot is contained in RTC_IC0 for that
input-capture channel.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–93
ADuCM302x RTC Register Descriptions
RTC Trim
RTC_TRM contains the trim value and interval for a periodic adjustment of the RTC count value to track time with
the required accuracy. Trimming is enabled and disabled via the RTC_CR0.TRMEN bit. For trimming to occur, the
global enable for the RTC, RTC_CR0.CNTEN, must also be active.
15 14 13 12 11 10 9
0
0
0
0
0
0
1
IVL2EXPMIN (R/W)
Minimum power-of-two interval of prescaled
RTC time units, which RTC Trim Register
can select
8
7
6
5
4
3
2
1
0
1
1
0
0
1
1
0
0
0
VALUE (R/W)
Trim value in prescaled RTC time units
to be added or subtracted from the
RTC count at the end of a periodic interval
selected by RTC Trim Register
IVL (R/W)
Trim interval in prescaled RTC time units
ADD (R/W)
Trim Polarity
Figure 20-33: RTC_TRM Register Diagram
Table 20-34:
RTC_TRM Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
9:6 IVL2EXPMIN
(R/W)
Minimum power-of-two interval of prescaled RTC time units, which RTC Trim Register can select.
It configures the range of trim intervals which are available to the RTC at any one
time. The range is from (1'b1 << RTC_TRM.IVL2EXPMIN) to (1'b1 <<
(RTC_TRM.IVL2EXPMIN + 3)), selectable via RTC_TRM.IVL.
The minimum supported value of RTC_TRM.IVL2EXPMIN is 2. The maximum supported value (and default) is 14. If a user configures the RTC with a value outside the
range [2,14], the default value of 14 will be used.
20–94
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-34:
RTC_TRM Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
5:4 IVL
(R/W)
Trim interval in prescaled RTC time units.
It specifies the interval at the end of which a periodic adjustment of RTC_TRM.VALUE
prescaled RTC time units is made to the RTC count.
Note that a trim boundary is created and a new trim interval is instigated if any of the
following occurs : (i) The RTC is re-enabled from a disabled state via
RTC_CR0.CNTEN (ii) trimming is re-enabled from a disabled state via
RTC_CR0.TRMEN (iii)RTC_CNT0 and RTC_CNT1 MMRs are redefined via paired
writes, thus creating new modulo-1 and modulo-60 RTC count boundaries (iv) the
RTC_TRM MMR is redefined (v) the RTC_CR1.PRESCALE2EXP field is changed from
its current value.
When a new trim interval is created under any of the above changes, the progression to
date through any existing trim interval and any coincident trimming (if enabled) of the
RTC count are immediately discarded. This is because all of the above events imply
that the count starts/carries on from such a changing event with an alignment and value which are correct. Hence, a new trim interval is initiated in such circumstances and
only after the count in RTC_CNT0 and RTC_CNT1 has advanced by an increment
equal to RTC_TRM.IVL prescaled time units after such an event, will trimming actually be carried out.
Note that the period of trimming (i.e. RTC_TRM.IVL) is aligned to the most recent
trim occurrence (i.e. trim boundary for continuous trimming) or trim instigation (one
of the above-mentioned changing events). There is no alignment to an absolute value
or the toggling of a specific bit position within the RTC_CNT0 and RTC_CNT1 MMRs.
0 Trim interval is (1'b1 << RTC_TRM.IVL2EXPMIN) prescaled RTC time units. Equivalent to 4 hours 33 minutes 04 seconds if prescaling to count time at 1Hz.
1 Trim interval is (1'b1 << (RTC_TRM.IVL2EXPMIN +
1)) prescaled RTC time units. Equivalent to 9 hours 06
minutes 08 seconds if prescaling to count time at 1 Hz.
2 Trim interval is (1'b1 << (RTC_TRM.IVL2EXPMIN +
2)) prescaled RTC time units. Equivalent to 18 hours
12 minutes 16 seconds if prescaling to count time at
1Hz.
3 Trim interval is (1'b1 << (RTC_TRM.IVL2EXPMIN +
3)) prescaled RTC time units. Equivalent to 36 hours
24 minutes 32 seconds if prescaling to count time at
1Hz.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–95
ADuCM302x RTC Register Descriptions
Table 20-34:
RTC_TRM Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 ADD
(R/W)
Trim Polarity.
It specifies whether RTC_TRM.VALUE is a positive (additive) or negative (subtractive)
adjustment of the RTC count.
Note that a negative trim is implemented as a stall of the RTC count, whereas a positive trim results in an increment which is greater than the normal value of one. The
RTC count is never decremented as a result of trimming, as to do so would mean going back in time.
See the description of the RTC_TRM.VALUE field for more details.
0 Subtract (by means of a stall) RTC_TRM.VALUE prescaled RTC time units from the RTC count at a period
defined by RTC_TRM.IVL.
1 Add RTC_TRM.VALUE prescaled RTC time units to the
RTC count at a period defined by RTC_TRM.IVL.
2:0 VALUE
(R/W)
Trim value in prescaled RTC time units to be added or subtracted from the RTC
count at the end of a periodic interval selected by RTC Trim Register.
A trim adjustment of +/- 0,1,2,3,4,5,6,7 prescaled RTC time units in the RTC count
(at a period defined by RTC_TRM.IVL) can be specified using RTC_TRM.VALUE.
Note that positive (additive) trim adjustments result in an increment of more than one
(time being skipped) to the RTC count. Negative (subtractive) adjustments result in a
stall of the count, where the length of the stall equals the trim value to be subtracted
from the count. The count is never decremented due to trimming, as such a course of
action would mean going back in time which would be undesirable.
Note that if an RTC interrupt event is configured to occur at a time which is coincidentally trimmed, the interrupt behaviour is as follows. If the interrupt time is trimmed out (skipped) because of a positive trim, the interrupt issues at the end of the
trim. For negative trims which coincidentally stall the RTC count at the target time for
the interrupt event, the interrupt issues at the first occurrence of the target time.
0 Make no adjustment to the RTC count at the end of a
trim interval.
1 Add or subtract one prescaled RTC time unit to the
RTC count at the end of a trim interval.
2 Add or subtract (depending on RTC_TRM.ADD) two
prescaled RTC time units to the RTC count at the end
of a trim interval.
3 Add or subtract (depending on RTC_TRM.ADD) three
prescaled RTC time units to the RTC count at the end
of a trim interval.
20–96
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x RTC Register Descriptions
Table 20-34:
Bit No.
RTC_TRM Register Fields (Continued)
Bit Name
Description/Enumeration
(Access)
4 Add or subtract (depending on RTC_TRM.ADD) four
prescaled RTC time units to the RTC count at the end
of a trim interval.
5 Add or subtract (depending on RTC_TRM.ADD) five
prescaled RTC time units to the RTC count at the end
of a trim interval.
6 Add or subtract (depending on RTC_TRM.ADD) six prescaled RTC time units to the RTC count at the end of a
trim interval.
7 Add or subtract (depending on RTC_TRM.ADD) seven
prescaled RTC time units to the RTC count at the end
of a trim interval.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
20–97
Universal Asynchronous Receiver/Transmitter (UART)
21 Universal Asynchronous Receiver/Transmitter (UART)
The ADuCM302x processor uses the UART peripheral that is a serial full duplex universal asynchronous receiver/
transmitter, compatible with the industry-standard 16450/16550. The serial communication follows an asynchronous protocol supporting various word length, stop bits, and parity generation options.
UART Features
This UART also contains interrupt handling hardware and provides a fractional divider that facilitates high accuracy
baud rate generation.
Interrupts may be generated from a number of unique events, such as data buffer full/empty, transfer error detection, and break detection.
While the UART implementation supports modem control signals, only serial Tx and Rx functionality is supported.
The following modem inputs are tied high internally:
• UART_COMMSR.DCD
• UART_COMMSR.RI
• UART_COMMSR.DSR
• UART_COMMSR.CTS
The following modem outputs are not connected:
• UART_COMMCR.RTS
• UART_COMMCR.DTR
• UART_COMMCR.OUT1
• UART_COMMCR.OUT2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–1
UART Functional Description
UART Functional Description
The UART peripheral supports industry standard asynchronous serial communication and can transfer data through
the transmit and receive pins. It supports the word lengths from 7 to 12 bits. Transmit operation is initiated by
writing to the transmit holding register (UART_COMTX). Receive operation uses the same data format as the transmit
configuration, except for the number of stop bits, which is always one.
ADuCM302x UART Register List
Table 21-1:
ADuCM302x UART Register List
Name
Description
UART_COMACR
Auto Baud Control
UART_COMASRH
Auto Baud Status (High)
UART_COMASRL
Auto Baud Status (Low)
UART_COMCTL
UART control register
UART_COMDIV
Baudrate divider
UART_COMFBR
Fractional Baud Rate
UART_COMFCR
FIFO Control
UART_COMIEN
Interrupt Enable
UART_COMIIR
Interrupt ID
UART_COMLCR
Line Control
UART_COMLCR2
second Line Control
UART_COMLSR
Line Status
UART_COMMCR
Modem Control
UART_COMMSR
Modem Status
UART_COMRFC
RX FIFO byte count
UART_COMRSC
RS485 half-duplex Control
UART_COMRX
Receive Buffer Register
UART_COMSCR
Scratch buffer
UART_COMTFC
TX FIFO byte count
UART_COMTX
Transmit Holding Register
UART Operations
Serial Communications
The asynchronous serial communication protocol supports the following options:
21–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
UART Operations
• 5 to 8 data bits.
• 1, 2 or 1 and 1/2 stop bits.
• None, or even or odd parity.
• Programmable over sample rate by 4, 8, 16, 32.
• Baudrate = (PCLK / ((M + N/2048) × 2OSR+2 × UART_COMDIV))
where,
OSR = 0 to 3
UART_COMDIV = 1 to 65536
M = 1 to 3
N = 0 to 2047
All data words require a start bit and at least one stop bit. This creates a range from 7 bits to 12 bits for each word.
Transmit operation is initiated by writing to the transmit holding register (UART_COMTX). After a synchronization
delay, the data is moved to the transmit shift register where it will be shifted out at a baud (bit) rate equal to PCLK ÷
(2OSR+2 × UART_COMDIV) ÷ (M + N ÷ 2048) with start, stop, and parity bits appended as required. All data words
begin with a low going start bit. The transfer of the transmit holding register to the transmit shift register causes the
transmit register empty status bit (UART_COMLSR.THRE) to be set.
Receive operation uses the same data format as the transmit configuration, except for the number of stop bits, which
is always one. After detecting the start bit, the received word is shifted to the receive shift register. After the appropriate number of bits (including stop bits) are received, the receive shift register is transferred to the receive buffer register, after the appropriate synchronization delay, and the receive buffer register full status flag (UART_COMIIR.STA)
is updated.
A sampling clock equal to 2OSR+2 times the baud rate is used to sample the data as close to the midpoint of the bit
as possible. A receive filter is also present that removes spurious pulses less than the sampling clock period.
NOTE: Data is transmitted and received least significant bit first, that is, transmit shift register, Bit 0.
Baudrate Generator
To bypass the fractional divider, set UART_COMFBR.FBEN =0 to bypass.
This results in a Baudrate = (PCLK / (2OSR+2 × UART_COMDIV)).
To estimate the UART_COMFBR.DIVN and UART_COMFBR.DIVM values, the fractional baudrate generator fine
tunes the baudrate if the integer UART_COMDIV gives an unreasonable error to the rate.
NOTE: Setting UART_COMDIV to 0 disables the UART logic.
The following tables show example baud rates assuming a 26 MHz and 16 MHz input clock.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–3
UART Operating Modes
Table 21-2:
Baud Rate Examples Based on 26 MHz PCLK
Baud Rate
OSR
COMDIV
DIVM
DIVN
Actual
Error
9600
3
24
3
1078
9600.29
0.0031%
19200
3
12
3
1078
19200.59
0.0031%
38400
3
8
2
1321
38397.64
−0.0062%
57600
3
4
3
1078
57601.77
0.0031%
115200
3
4
1
1563
115203.5
0.0031%
230400
3
2
1
1563
230407.1
0.0031%
460800
3
1
1
1563
460814.2
0.0031%
921,600
2
1
1
1563
921628.4
0.0031%
1,000,000
2
1
1
1280
1000000
0.0%
1,500,000
2
1
1
171
1499775
-0.0150%
Table 21-3:
Baud Rate Examples Based on a 16 MHz PCLK
Baud Rates
OSR
COMDIV
DIVM
DIVN
Actual
% Error
9600
3
17
3
131
9599.25
−0.0078%
19200
3
8
3
523
19199.04
−0.0050%
38400
3
4
3
523
38398.08
−0.0050%
57600
3
8
1
174
57605.76
0.0100%
115200
3
2
2
348
115211.5
0.0100%
230400
3
2
1
174
230423
0.0100%
460800
3
1
1
174
460846.1
0.0100%
921,600
2
1
1
174
921692.2
0.0100%
1,000,000
2
1
1
0
1000000
0.0000%
1,500,000
1
1
1
683
1499816.9
-0.012%
UART Operating Modes
The UART used by the ADuCM302x processor supports the following modes.
IO Mode
In this mode, the software moves the data to and from the UART. This is accomplished by interrupt service routines
that respond to the transmit and receive interrupts by either reading or writing data as appropriate. In this mode, the
software must respond within a certain time to prevent overrun errors in the receive channel.
The IO mode also requires polling the status flags to determine when it is okay to move data.
21–4
ADuCM302x Mixed-Signal Control Processor Hardware Reference
UART Operating Modes
This mode is processor intensive and used only if the system can tolerate the overhead. Interrupts can be disabled
using the UART interrupt enable register (UART_COMIEN).
Writing to the transmit holding register when it is not empty, or reading from the receive buffer register when it is
not full produces an incorrect result. In the former case, the transmit holding register is overwritten by the new word
and the previous word is never transmitted, and in the latter case, the previously received word is read again. These
errors must be avoided in software by correctly using either interrupts or status register polling. These errors are not
detected in the hardware.
DMA Mode
In this mode, user code does not move data to and from the UART. The DMA request signals to the DMA block
are generated indicating that the UART is ready to transmit or receive data. These DMA request signals can be disabled in the UART_COMIEN register.
UART Interrupts
The UART peripheral has one output signal to the core interrupt controller representing all Rx and Tx interrupts.
The UART interrupt identification register (UART_COMIIR) must be read by the software to determine the cause of
the interrupt.
In the IO mode, interrupts may be generated for the following cases:
• Receive buffer register full
• Receive overrun error
• Receive parity error
• Receive framing error
• Receive FIFO timeout if FIFO (16550) is enabled
• Break interrupt (SIN held low)
• Modem status interrupt (changes to UART_COMMSR.DCD, UART_COMMSR.RI, UART_COMMSR.DSR, or
UART_COMMSR.CTS)
• Transmit holding register empty
FIFO Mode (16550)
The 16-byte deep TX FIFO and RX FIFOs are implemented so that the UART is compatible with the industrystandard 16550.
By default, the FIFOs are disabled. They are enabled by setting the UART_COMFCR.FIFOEN bit. When enabled, the
internal FIFOs are activated, allowing 16 bytes (and 3 bits of error data per byte in the RX FIFO) to be stored in
both receive and transmit modes. This minimizes the system overhead and maximizes the system efficiency.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–5
Auto Baud-rate Detection
The interrupt and/or DMA trigger level of the RX FIFO are programmed by the UART_COMFCR.RFTRIG bit. The
DMA requests are programmed by the UART_COMFCR.FDMAMD bit. The DMA Mode 1 only works when FIFO is
enabled, and works like burst mode.
Auto Baud-rate Detection
The Auto Baud Detection (ABD) block is used to match the baud rates of two UART devices automatically without
pre-assumptions. The receiver must be enabled to detect the mode before a common baud rate is configured.
The UART_COMACR.ABE bit enables the receiver to work in the Auto Baud Detection mode. A 20-bit counter logic
counts the number of cycles between the programmed rising or falling edge and another rising or falling edge. An
interrupt is generated once the expected edges are reached. The counter may overflow and generate timeout interrupt (for example, continuous break condition, or no expected edges).
Auto Baud must be disabled to clear internal counter and re-enabled for another run (if required).
Based on the UART baud rate configuration, the Auto Baud Detection result can be calculated in the following way:
CNT[19:0] = CountedBits × 2OSR+2 × DIV × (DIVM + DIVN ÷ 2048)
if CNT < 8 × CountedBits, OSR = 0, DIV = 1, DIVN = 512 × CNT ÷ CountedBits - 2048,
else if CNT < 16 × CountedBits, OSR = 1, DIV = 1, DIVN = 256 ×CNT ÷ CountedBits - 2048,
else if CNT < 32 × CountedBits, OSR = 2, DIV = 1, DIVN = 128 ×CNT ÷ CountedBits - 2048,
else if CNT > = 32 × CountedBits, OSR = 3,
if CNT exactly divided by (32 × CountedBits), DIV = CNT ÷ 32 ÷ CountedBits,
else DIV = 2log2(CNT ÷ 32 ÷ CountedBits)
DIVN = 64 × CNT ÷ DIV ÷ CountedBits - 2048
NOTE: To reduce truncation error, DIVM always set to 1. DIV is set to nearest power of 2.
CountedBits is the effective bit number between an active starting edge and ending edge. It is determined by the
application code on selected edges and character used for Auto Baud Detection.
RS485 Half-Duplex Mode
To support RS485 multiplexing TX and RX as half-duplexing, SOUT_EN is implemented. The transmit driver
must be enabled when SOUT_EN is asserted.
21–6
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Receive Line Inversion
Receive Line Inversion
For specific applications such as UART communication through optical link, the receive line may work at the opposite level (that is, idling at low level). The UART_COMCTL.RXINV register cannot invert the receive line for this
purpose.
NOTE: Do not use Receive line inversion with RS485 application.
Configure the UART_COMCTL.RXINV register before configuring the UART and enabling Auto Baud.
Clock Gating
The clock driving the UART logic is automatically gated off when idle, and not accessed. This automatic clock gating cannot be disabled by the UART_COMCTL.FORCECLKON register.
UART and Power-Down Modes
Complete the on-going UART transfers before powering down the chip into the Hibernate mode. Else, disable the
UART by clearing the UART_COMDIV register before going into hibernation.
NOTE: If Hibernate mode is selected while a UART transfer is on, the transfer does not continue on returning from
hibernation. All the intermediate data, states, status logic in the UART are cleared. However, the TX pads (SOUT
and SOUT_EN, if pin mux is selected) may remain active in the Hibernate mode while transmitting.
After hibernation, the UART can be enabled by setting the UART_COMDIV register (if previously cleared). If DMA
mode is needed, COMIEN[5:4] must be configured.
For a clean wake-up, disable the UART block by clearing the UART_COMDIV register before entering into the Hibernate mode.
The following registers are retained through hibernate mode. All the rest registers and internal logic are cleared to
hardware default value.
• UART_COMIEN.ELSI, UART_COMIEN.ERBFI
• UART_COMLCR.BRK, UART_COMLCR.SP, UART_COMLCR.EPS, UART_COMLCR.PEN, UART_COMLCR.STOP,
UART_COMLCR.WLS
• UART_COMFCR.RFTRIG, UART_COMFCR.FDMAMD, UART_COMFCR.FIFOEN
• UART_COMFBR.FBEN, UART_COMFBR.DIVM, UART_COMFBR.DIVN
• UART_COMDIV.DIV
• UART_COMLCR2.OSR
• UART_COMCTL.RXINV, UART_COMCTL.FORCECLKON
• UART_COMRSC.DISTX, UART_COMRSC.DISRX, UART_COMRSC.OENSP, UART_COMRSC.OENP
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–7
ADuCM302x UART Register Descriptions
ADuCM302x UART Register Descriptions
(UART) contains the following registers.
Table 21-4:
ADuCM302x UART Register List
Name
Description
UART_COMACR
Auto Baud Control
UART_COMASRH
Auto Baud Status (High)
UART_COMASRL
Auto Baud Status (Low)
UART_COMCTL
UART control register
UART_COMDIV
Baudrate divider
UART_COMFBR
Fractional Baud Rate
UART_COMFCR
FIFO Control
UART_COMIEN
Interrupt Enable
UART_COMIIR
Interrupt ID
UART_COMLCR
Line Control
UART_COMLCR2
second Line Control
UART_COMLSR
Line Status
UART_COMMCR
Modem Control
UART_COMMSR
Modem Status
UART_COMRFC
RX FIFO byte count
UART_COMRSC
RS485 half-duplex Control
UART_COMRX
Receive Buffer Register
UART_COMSCR
Scratch buffer
UART_COMTFC
TX FIFO byte count
UART_COMTX
Transmit Holding Register
21–8
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
Auto Baud Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EEC (R/W)
Ending Edge Count
ABE (R/W)
Auto Baud enable
SEC (R/W)
Starting Edge Count
DNIEN (R/W)
enable done interrupt
TOIEN (R/W)
enable time-out interrupt
Figure 21-1: UART_COMACR Register Diagram
Table 21-5:
UART_COMACR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
11:8 EEC
Ending Edge Count.
(R/W)
0 first edge
1 second edge
2 third edge
3 fourth edge
4 fifth edge
5 sixth edge
6 seventh edge
7 eighth edge
8 ninth edge
6:4 SEC
Starting Edge Count.
(R/W)
0 first edge (always the falling edge of START bit)
1 second edge
2 third edge
3 fourth edge
4 fifth edge
5 sixth edge
6 seventh edge
7 eighth edge
2 TOIEN
enable time-out interrupt.
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–9
ADuCM302x UART Register Descriptions
Table 21-5:
UART_COMACR Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
1 DNIEN
enable done interrupt.
(R/W)
0 ABE
Auto Baud enable.
(R/W)
21–10
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
Auto Baud Status (High)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CNT[19:12] (R)
Auto Baud Counter value
Figure 21-2: UART_COMASRH Register Diagram
Table 21-6:
UART_COMASRH Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 CNT
Auto Baud Counter value.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–11
ADuCM302x UART Register Descriptions
Auto Baud Status (Low)
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
CNT[11:0] (R)
Auto Baud Counter value
DONE (RC)
Auto Baud Done successfully
NEETO (RC)
Timed out due to no valid ending edge
found
BRKTO (RC)
Timed out due to long time break condition
NSETO (RC)
Timed out due to no valid start edge
found
Figure 21-3: UART_COMASRL Register Diagram
Table 21-7:
UART_COMASRL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:4 CNT
Auto Baud Counter value.
(R/NW)
3 NEETO
Timed out due to no valid ending edge found.
(RC/NW)
2 NSETO
Timed out due to no valid start edge found.
(RC/NW)
1 BRKTO
Timed out due to long time break condition.
(RC/NW)
0 DONE
Auto Baud Done successfully.
(RC/NW)
21–12
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
UART control register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
1
0
0
0
0
0
0
0
0
REV (R)
UART revision ID
ForceClkOn (R/W)
Force UCLKg on
RXINV (R/W)
invert receiver line
Figure 21-4: UART_COMCTL Register Diagram
Table 21-8:
UART_COMCTL Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:8 REV
UART revision ID.
(R/NW)
4 RXINV
invert receiver line.
(R/W)
0 don't invert receiver line (idling high)
1 invert receiver line (idling low)
1 FORCECLKON
Force UCLKg on.
(R/W)
0 UCLKg automatically gated
1 UCLKg always working
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–13
ADuCM302x UART Register Descriptions
Baudrate divider
Be aware: internal UART baud generation counters are restarted whenever COMDIV register accessed by writing,
regardless same or different value.
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DIV (R/W)
Baud rate divider
Figure 21-5: UART_COMDIV Register Diagram
Table 21-9:
UART_COMDIV Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15:0 DIV
(R/W)
21–14
Baud rate divider.
The range of allowed DIV values is from 1 to 65535. value 0 disables UART logic.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
Fractional Baud Rate
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
FBEN (R/W)
Fractional baud rate generator enable
DIVN (R/W)
Fractional baud rate N divide bits 0 to
2047.
DIVM (R/W)
Fractional baud rate M divide bits 1 to 3
Figure 21-6: UART_COMFBR Register Diagram
Table 21-10:
UART_COMFBR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
15 FBEN
(R/W)
12:11 DIVM
(R/W)
10:0 DIVN
Fractional baud rate generator enable.
The generating of fractional baud rate can be described by the following formula and
the final baud rate of UART operation is calculated as Baudrate = (UCLK / (2 * (M +
N/2048) * 16 * COMDIV) )
Fractional baud rate M divide bits 1 to 3.
This bit should not be 0 when Fractional Baud Rate enabled
Fractional baud rate N divide bits 0 to 2047..
(R/W)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–15
ADuCM302x UART Register Descriptions
FIFO Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RFTRIG (R/W)
RX FIFO Trig level
FIFOEN (R/W)
FIFO enable as to work in 16550 mode
FDMAMD (R/W)
FIFO DMA mode
RFCLR (W)
clear RX FIFO
TFCLR (W)
clear TX FIFO
Figure 21-7: UART_COMFCR Register Diagram
Table 21-11:
UART_COMFCR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:6 RFTRIG
RX FIFO Trig level.
(R/W)
0 1 byte to trig RX interrupt
1 4 byte to trig RX interrupt
2 8 byte to trig RX interrupt
3 14 byte to trig RX interrupt
3 FDMAMD
FIFO DMA mode.
(R/W)
0 in DMA mode 0, RX DMA request will be asserted
whenever there's data in RBR or RX FIFO and de-assert
whenever RBR or RX FIFO is empty; TX DMA request
will be asserted whenever THR or TX FIFO is empty
and de-assert whenever data written to
1 in DMA mode 1, RX DMA request will be asserted
whenever RX FIFO trig level or time out reached and
de-assert thereafter when RX FIFO is empty; TX DMA
request will be asserted whenever TX FIFO is empty
and de-assert thereafter when TX FIFO is completely
filled up full;
2 TFCLR
clear TX FIFO.
(RX/W)
1 RFCLR
clear RX FIFO.
(RX/W)
0 FIFOEN
FIFO enable as to work in 16550 mode.
(R/W)
21–16
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
Interrupt Enable
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
EDMAR (R/W)
DMA requests in receive mode
ERBFI (R/W)
Receive buffer full interrupt
EDMAT (R/W)
DMA requests in transmit mode
ETBEI (R/W)
Transmit buffer empty interrupt
EDSSI (R/W)
Modem status interrupt
ELSI (R/W)
Rx status interrupt
Figure 21-8: UART_COMIEN Register Diagram
Table 21-12:
UART_COMIEN Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
5 EDMAR
DMA requests in receive mode.
(R/W)
0 DMA requests disabled
1 DMA requests enabled
4 EDMAT
DMA requests in transmit mode.
(R/W)
0 DMA requests are disabled
1 DMA requests are enabled
3 EDSSI
(R/W)
Modem status interrupt.
Interrupt is generated when any of COMMSR[3:0] are set.
0 Interrupt disabled
1 Interrupt enabled
2 ELSI
Rx status interrupt.
(R/W)
0 Interrupt disabled
1 Interrupt enabled
1 ETBEI
Transmit buffer empty interrupt.
(R/W)
0 Interrupt disabled
1 Interrupt enabled
0 ERBFI
Receive buffer full interrupt.
(R/W)
0 Interrupt disabled
1 Interrupt enabled
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–17
ADuCM302x UART Register Descriptions
Interrupt ID
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
1
FEND (R)
FIFO enabled
NIRQ (RS)
Interrupt flag
STA (RC)
Interrupt status
Figure 21-9: UART_COMIIR Register Diagram
Table 21-13:
UART_COMIIR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:6 FEND
FIFO enabled.
(R/NW)
0 FIFO not enabled, 16450 mode
3 FIFO enabled, 16550 mode
3:1 STA
(RC/NW)
Interrupt status.
When NIRQ is low (active-low), this indicates an interrupt and the STA bit decoding
below is used.
0 Modem status interrupt (Read COMMSR to clear)
1 Transmit buffer empty interrupt (Write to COMTX or
read COMIIR to clear)
2 Receive buffer full interrupt (Read COMRX to clear)
3 Receive line status interrupt (Read COMLSR to clear)
6 Receive FIFO timed out (Read COMRX to clear)
0 NIRQ
Interrupt flag.
(RS/NW)
21–18
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
Line Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
BRK (R/W)
Set Break
WLS (R/W)
Word Length Select
SP (R/W)
Stick Parity
STOP (R/W)
Stop Bit
EPS (R/W)
Parity Select
PEN (R/W)
Parity Enable
Figure 21-10: UART_COMLCR Register Diagram
Table 21-14:
UART_COMLCR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
6 BRK
Set Break.
(R/W)
0 Normal TxD operation
1 Force TxD to 0
5 SP
(R/W)
Stick Parity.
Used to force parity to defined values. When set, the parity will be based on the following bit settings : EPS = 1 and PEN = 1, parity will be forced to 0. EPS = 0 and
PEN = 1, parity will be forced to 1. EPS = X and PEN = 0, no parity will be transmitted
0 Parity will not be forced based on EPS and PEN
1 Parity forced based on EPS and PEN
4 EPS
(R/W)
Parity Select.
This bit only has meaning if parity is enabled (PEN set)
0 Odd parity will be transmitted and checked
1 Even parity will be transmitted and checked
3 PEN
(R/W)
Parity Enable.
Used to control if the parity bit is transmitted and checked. The value transmitted and
the value checked will be based on the settings of EPS and SP.
0 Parity will not be transmitted or checked
1 Parity will be transmitted and checked
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–19
ADuCM302x UART Register Descriptions
Table 21-14:
UART_COMLCR Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
2 STOP
(R/W)
Stop Bit.
Used to control the number of stop bits transmitted. In all cases only the first stop bit
will be evaluated on data received.
0 Send 1 stop bit regardless of the word length (WLS).
1 Send a number of stop bits based on the word length as
follows: WLS = 00, 1.5 stop bits transmitted (5-bit
word length) WLS = 01 or 10 or 11, 2 stop bits transmitted (6 or 7 or 8-bit word length)
1:0 WLS
(R/W)
Word Length Select.
Selects the number of bits per transmission.
0 5 bits
1 6 bits
2 7 bits
3 8 bits
21–20
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
second Line Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
1
0
OSR (R/W)
Over Sample Rate
Figure 21-11: UART_COMLCR2 Register Diagram
Table 21-15:
UART_COMLCR2 Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
1:0 OSR
Over Sample Rate.
(R/W)
0 over sample by 4
1 over sample by 8
2 over sample by 16
3 over sample by 32
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–21
ADuCM302x UART Register Descriptions
Line Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
1
1
0
0
0
0
0
FIFOERR (RC)
data byte(s) in RX FIFO have either parity
error, frame error or break indication.
only used in 16550 mode; Read-clear
if no more error in RX FIFO
DR (RC)
Data Ready
TEMT (R)
COMTX and Shift Register Empty Status
PE (RC)
Parity Error
THRE (R)
COMTX Empty
FE (RC)
Framing Error
OE (RC)
Overrun Error
BI (RC)
Break Indicator
Figure 21-12: UART_COMLSR Register Diagram
Table 21-16:
UART_COMLSR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7 FIFOERR
(RC/NW)
6 TEMT
data byte(s) in RX FIFO have either parity error, frame error or break indication. only
used in 16550 mode; Read-clear if no more error in RX FIFO.
COMTX and Shift Register Empty Status.
(R/NW)
0 COMTX has been written to and contains data to be
transmitted. Care should be taken not to overwrite its
value.
1 COMTX and the transmit shift register are empty and
it is safe to write new data to COMTX. Data has been
transmitted.
5 THRE
(R/NW)
COMTX Empty.
THRE is cleared when COMTX is written.
0 COMTX has been written to and contains data to be
transmitted. Care should be taken not to overwrite its
value.
1 COMTX is empty and it is safe to write new data to
COMTX. The previous data may not have been transmitted yet and can still be present in the shift register.
21–22
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
Table 21-16:
UART_COMLSR Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
4 BI
(RC/NW)
Break Indicator.
If set, this bit will self clear after COMLSR is read.
0 SIN was not detected to be longer than the maximum
word length.
1 SIN was held low for more than the maximum word
length.
3 FE
(RC/NW)
Framing Error.
If set, this bit will self clear after COMLSR is read.
0 No invalid Stop bit was detected.
1 An invalid Stop bit was detected on a received word.
2 PE
(RC/NW)
Parity Error.
If set, this bit will self clear after COMLSR is read.
0 No parity error was detected.
1 A parity error occurred on a received word.
1 OE
(RC/NW)
Overrun Error.
If set, this bit will self clear after COMLSR is read.
0 Receive data has not been overwritten.
1 Receive data was overwritten by new data before
COMRX was read.
0 DR
(RC/NW)
Data Ready.
This bit is cleared only by reading COMRX. This bit will not self clear.
0 COMRX does not contain new receive data.
1 COMRX contains receive data that should be read.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–23
ADuCM302x UART Register Descriptions
Modem Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
LOOPBACK (R/W)
Loopback mode
DTR (R/W)
Data Terminal Ready
OUT2 (R/W)
Output 2
RTS (R/W)
Request to send
OUT1 (R/W)
Output 1
Figure 21-13: UART_COMMCR Register Diagram
Table 21-17:
UART_COMMCR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4 LOOPBACK
(R/W)
Loopback mode.
In loop back mode, the SOUT is forced high. The modem signals are also directly
connected to the status inputs (RTS to CTS, DTR to DSR, OUT1 to RI, and OUT2
to DCD).
0 Normal operation - loopback disabled
1 Loopback enabled
3 OUT2
Output 2.
(R/W)
0 Force nOUT2 to a logic 1
1 Force nOUT2 to a logic 0
2 OUT1
Output 1.
(R/W)
0 Force nOUT1 to a logic 1
1 Force nOUT1 to a logic 0
1 RTS
Request to send.
(R/W)
0 Force nRTS to a logic 1
1 Force nRTS to a logic 0
0 DTR
(R/W)
Data Terminal Ready.
0 Force nDTR to a logic 1
1 Force nDTR to a logic 0
21–24
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
Modem Status
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
X X X X X X X X
DCD (R)
Data Carrier Detect
DCTS (R)
Delta CTS
RI (R)
Ring Indicator
DDSR (R)
Delta DSR
DSR (R)
Data Set Ready
TERI (R)
Trailing Edge RI
CTS (R)
Clear To Send
DDCD (R)
Delta DCD
Figure 21-14: UART_COMMSR Register Diagram
Table 21-18:
UART_COMMSR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7 DCD
(R/NW)
Data Carrier Detect.
This bit reflects the direct status complement of the nDCD pin.
0 nDCD is currently logic high
1 nDCD is currently logic low
6 RI
(R/NW)
Ring Indicator.
This bit reflects the direct status complement of the nRI pin
0 nRI is currently logic high
1 nRI is currently logic low
5 DSR
(R/NW)
Data Set Ready.
This bit reflects the direct status complement of the nDSR pin
0 nDSR is currently logic high
1 nDSR is currently logic low
4 CTS
(R/NW)
Clear To Send.
This bit reflects the direct status complement of the nCTS pin
0 nCTS is currently logic high
1 nCTS is currently logic low
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–25
ADuCM302x UART Register Descriptions
Table 21-18:
UART_COMMSR Register Fields (Continued)
Bit No.
Bit Name
Description/Enumeration
(Access)
3 DDCD
(R/NW)
Delta DCD.
If set, this bit will self clear after COMMSR is read.
0 nDCD has not changed state since COMMSR was last
read
1 nDCD changed state since COMMSR last read
2 TERI
(R/NW)
Trailing Edge RI.
If set, this bit will self clear after COMMSR is read.
0 nRI has not changed from 1 to 0 since COMMSR last
read
1 nRI changed from 1 to 0 since COMMSR last read
1 DDSR
(R/NW)
Delta DSR.
If set, this bit will self clear after COMMSR is read.
0 nDSR has not changed state since COMMSR was last
read
1 nDSR changed state since COMMSR last read
0 DCTS
(R/NW)
Delta CTS.
If set, this bit will self clear after COMMSR is read.
0 nCTS has not changed state since COMMSR was last
read
1 nCTS changed state since COMMSR last read
21–26
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
RX FIFO byte count
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RFC (R)
Current RX FIFO data bytes
Figure 21-15: UART_COMRFC Register Diagram
Table 21-19:
UART_COMRFC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4:0 RFC
Current RX FIFO data bytes.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–27
ADuCM302x UART Register Descriptions
RS485 half-duplex Control
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
DISTX (R/W)
Hold off TX when receiving
OENP (R/W)
SOUT_EN polarity
DISRX (R/W)
disable RX when transmitting
OENSP (R/W)
SOUT_EN de-assert before full stop
bit(s)
Figure 21-16: UART_COMRSC Register Diagram
Table 21-20:
UART_COMRSC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
3 DISTX
Hold off TX when receiving.
(R/W)
2 DISRX
disable RX when transmitting.
(R/W)
1 OENSP
SOUT_EN de-assert before full stop bit(s).
(R/W)
0 SOUT_EN de-assert same time as full stop bit(s)
1 SOUT_EN de-assert half-bit earlier than full stop bit(s)
0 OENP
(R/W)
SOUT_EN polarity.
0 high active
1 low active
21–28
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
Receive Buffer Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
RBR (R)
Receive Buffer Register
Figure 21-17: UART_COMRX Register Diagram
Table 21-21:
UART_COMRX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 RBR
Receive Buffer Register.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–29
ADuCM302x UART Register Descriptions
Scratch buffer
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SCR (R/W)
Scratch
Figure 21-18: UART_COMSCR Register Diagram
Table 21-22:
UART_COMSCR Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 SCR
(R/W)
21–30
Scratch.
The scratch register is an 8-bit register used to store intermediate results. The value
contained in Scratch Register does not affect UART functionality or performance. Only 8 bits of this register are implemented. Bits 15 to 8 are read only and always return
0x00 when read. Writable with any value from 0 to 255. A read will return the last
value written.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
ADuCM302x UART Register Descriptions
TX FIFO byte count
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
TFC (R)
Current TX FIFO data bytes
Figure 21-19: UART_COMTFC Register Diagram
Table 21-23:
UART_COMTFC Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
4:0 TFC
Current TX FIFO data bytes.
(R/NW)
ADuCM302x Mixed-Signal Control Processor Hardware Reference
21–31
ADuCM302x UART Register Descriptions
Transmit Holding Register
15 14 13 12 11 10 9
0
0
0
0
0
0
0
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
THR (W)
Transmit Holding Register
Figure 21-20: UART_COMTX Register Diagram
Table 21-24:
UART_COMTX Register Fields
Bit No.
Bit Name
Description/Enumeration
(Access)
7:0 THR
Transmit Holding Register.
(RX/W)
21–32
ADuCM302x Mixed-Signal Control Processor Hardware Reference
Watchdog Timer (WDT)
22 Watchdog Timer (WDT)
The watchdog timer is used to recover from an illegal software state. Once enabled by the user code, it requires
periodic servicing to prevent it from forcing a reset or an interrupt of the processor.
WDT Features
The watchdog timer is clocked by 32 kHz clock. The watchdog is clocked at all times except during reset, hibernate,
shutdown and debug mode. The timer is a 16-bit count-down counter with a programmable prescaler. The prescaler
source is selectable and can be scaled by factors of 1, 16, or 256. A WDT timeout can generate a reset or an interrupt. The WDT_CTL.IRQ bit selects an interrupt instead of a reset; this is intended to be a debug feature. The interrupt can be cleared by writing 0xCCCC to the WDT_RESTART write-only register.
WDT Functional Description
ADuCM302x WDT Register List
Table 22-1:
ADuCM302x WDT Register List
Name
Description
WDT_CCNT
Current count value
WDT_CTL
Control
WDT_LOAD
Load value
WDT_RESTART
Clear interrupt
WDT_STAT
Status
WDT Block Diagram
The figure below illustrates the block diagram of the WDT used by the ADuCM302x processor.
ADuCM302x Mixed-Signal Control Processor Hardware Reference
22–1
WDT Operating Modes
timer_wd
16 Bit Load
32 KHz
clock
Watchdog Reset
Prescale
(1,16, 256)
16 Bit Down
Counter
IRQ
16 Bit
Down
MMR
Readable
Counter
Count
Value
Figure 22-1: Watchdog Timer Block Diagram
WDT Operating Modes
After a valid reset, the watchdog timer is reset in the hardware as follows:
1. WDT_CTL = 0x00E9
2. WDT_LOAD = 0x1000
3. WDT_CCNT = 0x1000
This enables the watchdog timer with a timeout value of 32 seconds. This initial configuration can be modified by
user code; however, setting the WDT_CTL.EN bit will also set the WDT_STAT.LOCKED bit and write-protect
WDT_CTL and WDT_LOAD.VALUE (the load value). Only a reset will clear the write protection and
WDT_STAT.LOCKED bit and allow reconfiguration of the timer.
If the WDT_CTL register is not modified, the user code can change WDT_LOAD.VALUE at any time. If the
WDT_CTL.EN bit is cleared (prior to any write of the WDT_CTL register), the timer is disabled. Doing so allows the
timer settings to be modified, and the timer can be re-enabled. As soon as the timer is re-enabled by a write to the
WDT_CTL register, the watchdog configuration is locked to prevent any inadvertent modification to the register values.
If the watchdog timer is set to free-running mode (WDT_CTL.MODE = 0), the watchdog timer value will decrement
from 0x1000 to zero, wrap around to 0x1000 and continue to decrement.
To achieve a timeout value greater or less than 0x1000 (~32 sec with default prescale = 2), periodic mode should be
used (WDT_CTL.MODE = 1), and WDT_LOAD.VALUE and WDT_CTL.PRE written with the values corresponding to
the desired timeout period. The maximum timeout is ~8min (WDT_LOAD.VALUE = 0xFFFF, WDT_CTL.PRE = 2).
When periodic mode is chosen, the timer value will decrement from the WDT_LOAD.VALUE value to zero, wrap
around to WDT_LOAD.VALUE again and continue to decrement.
22–2
ADuCM302x Mixed-Signal Control Processor Hardware Reference
WDT Operating Modes
At any time, WDT_CCNT.VALUE will contain a valid value to be read, synchronized to the APB clock.
When the watchdog timer decrements to 0, a reset or an interrupt is generated. This reset can be prevented by writing the value 0xCCCC to the WDT_RESTART register before the expiration period. A write to WDT_RESTARTwill
cause the watchdog timer to reload with the WDT_LOAD.VALUE value (or 0x1000 if in free-running mode) immediately to begin a new timeout period and start to count again. If any value other than 0xCCCC is written, a reset or
interrupt is generated.
When the timer is disabled by clearing the WDT_CTL.EN bit, both the internal prescaler and counter will be cleared.
The counter will be reloaded with the value corresponding to the WDT_CTL.MODE bit setting once re-enabled.
The WDT setup is re-initialized/reset only after a POR or system reset.
The watchdog reset assertion duration will be one PCLK period when generated by a wrong WDT_RESTART access;
the reset due to timeout will be a full 32 KHz clock period.
Watchdog Synchronization
The watchdog timer has three status bits in the WDT_STAT register, WDT_STAT.COUNTING, WDT_STAT.LOADING,
and WDT_STAT.CLRIRQ , which indicate that synchronization between fast clock and slow clock domains is in
progress for the WDT_CTL, WDT_LOAD.VALUE and WDT_RESTART registers respectively. No 'write' to WDT_CTL
and WDT_LOAD.VALUE registers should occur while the corresponding synchronization bit is set.
Watchdog Power Modes behavior
The watchdog timer is automatically disa