ETC RC9624DP

RC96V24DP
Single Device Data/Fax Modem Data Pump
The Rockwell RC96V24DP is a low power, V.22 bis 2400 bps data/fax modem
data pump in a single VLSI package. The RC2324DPL is identical to the
RC96V24DP except fax modes are not provided. In this document, all
references to the RC96V24DP also apply to the RC2324DPL except for the fax
modes and as otherwise noted.
The modem operates over the public switched telephone network (PSTN), as
well as on point-to-point leased lines.
The modem supports data modes meeting the requirements specified in
CCITT recommendations V.22 bis, V.22, V.23, and V.21, as well as Bell 212A and
Bell 103.
The modem supports fax modes meeting the requirements specified in
CCITT V.29, V.27 ter, and V.21 channel 2 synchronous.
Internal HDLC support eliminates the need for an external serial input/output
(SIO) device or comparable functions in the host controller in products
incorporating error correction and T.30 protocols.
The modem includes two CMOS VLSI functions – a digital signal processor
(DSP) and an integrated analog function (IA). The RC96V24DP integrates these
functions into a single 68-pin plastic leaded chip carrier (PLCC).
Detailed hardware and software interface information is described in the
Designer's Guide (Order No. 822).
•
•
•
•
•
•
•
•
•
•
•
•
•
Functional Block Diagram
•
•
•
•
2
SERIAL
INTERFACE
(5)
Product Features
2
TELEPHONE
LINE
INTERFACE
RC96V24DP
MODEM
DEVICE
•
•
•
•
SPEAKER
AMPLIFIER
(OPTIONAL)
HOST
PARALLEL
BUS
INTERFACE
(17)
•
4
EYE
PATTERN
GENERATOR
(OPTIONAL)
•
•
•
D96V24DSA
Single CMOS VLSI device
Low power requirements
– Single voltage: + 5 Vdc ±5%
– Operating: 300 mW (typical)
– Sleep: 15 mW (typical)
2-wire operation
– Full- duplex (FDX) for data modes
– Half-duplex (HDX) for fax modes
Data configurations:
– V.22 bis, V.22, V.23, V.21
– Bell 212A, Bell 103
Fax configurations (RC96V24DP):
– V.29, V.27 ter, V.21 Channel 2
Voice mode
DTMF detection
Receive dynamic range: -9 dBm to -43 dBm
Transmit level: -10 dBm ±1 dB using internal
hybrid circuit; attentuation selectable in 1 dB
steps
Multi-mode data/fax detection support
V.22 bis fallback/fall-forward -2400/1200 bps
Serial data: synchronous and asynchronous
Parallel data: synchronous (including HDLC)
and asynchronous
Programmable ring detect
Programmable dialer
Programmable tone detect bandpass filters
Adjustable speaker output to monitor
received signal
Diagnostics
Host bus interface memory for
configuration, control, and parallel data;
8086 microprocessor bus compatible
5-pin serial data interface; TTL compatible
Equalization
– Adaptive equalizer in receiver
– Selectable and programmable fixed
compromise equalizers in both receiver
and transmitter
Loopback configurations
– Local analog, local digital, and remote
digital
Answer and originate handshake in data
modes
Training sequences for fax modes
Leased line operation
Ordering Information
Marketing Number
Manufacturing Number
Package
RC96V24DP
R6653-12
68 pin PLCC
RC96V24DP
R6653-17
100 pin PQFP
RC9624DP
R6653-16
68 pin PLCC
RC9624DP
R6653-21
100 pin PQFP
RC2324DPL
R6653-15
68 pin PLCC
RC2324DPL
R6653-20
100 pin PQFP
NOTE:
RC2324DPL does not support fax capabilities.
RC9624DP does not support voice.
Copyright © 1998 Rockwell Semiconductor Systems, Inc. All rights reserved.
Print date: September 1998
Rockwell Semiconductor Systems, Inc. reserves the right to make changes to its products or specifications to improve
performance, reliability, or manufacturability. Information furnished is believed to be accurate and reliable. However, no
responsibility is assumed for its use; nor for any infringement of patents or other rights of third parties which may result from its
use. No license is granted by its implication or otherwise under any patent or intellectual property rights of Rockwell
Semiconductor Systems, Inc.
Rockwell Semiconductor Systems, Inc. products are not designed or intended for use in life support appliances, devices, or systems
where malfunction of a Rockwell Semiconductor Systems, Inc. product can reasonably be expected to result in personal injury or
death. Rockwell Semiconductor Systems, Inc. customers using or selling Rockwell Semiconductor Systems, Inc. products for use
in such applications do so at their own risk and agree to fully indemnify Rockwell Semiconductor Systems, Inc. for any damages
resulting from such improper use or sale.
Specifications are subject to change without notice.
PRINTED IN THE UNITED STATES OF AMERICA
1.0 Functional Description
1.1 Overview
The Rockwell RC96V24DP is a low power, V.22 bis 2400 bps data/fax modem
data pump in a single VLSI package.
1.2 Technical Specifications
1.2.1 Configurations And Rates
The selectable modem configurations, along with the corresponding signaling
(baud) rates and data rates, are listed in Table 1-1 (CONF bits).
Note: Bit names refer to control or status bits in DSP interface memory which
are set or reset by the host processor (see Table 3-1 and Table 3-2).
1.2.2 Data Encoding
The data encoding conforms to CCITT recommendations V.29, V.27 ter, V.22 bis,
V.22, V.23, or V.21, or to Bell 212A or 103, depending on the selected
configuration.
1.2.3 Tone Generation
Answer Tone: A CCITT (2100 ±15 Hz) or Bell (2225 ±10 Hz) answer tone can
be generated.
Guard Tone: A1800 ±20 Hz guard tone can be generated (enabled by the GTE
bit).
DTMF Tones: Dual tone multi-frequency (DTMF) tones can be generated with a
frequency accuracy of ±1.5%.
User Defined Tones: A user-defined single or dual tone can be generated from
200 Hz to 3000 Hz ±5 Hz.
D96V24DSA
1-1
RC96V24DP
1.0 Functional Description
Single Device Data/Modem Data Pump
1.2 Technical Specifications
1.2.4 Tone Detection
Answer Tone and Call Progress Tones: Tones can be detected as follows:
•
•
•
•
•
•
Call progress frequency range: 340 ±5 Hz to 640 ±5HZ
Answer tone frequency ranges: CCITT (2100 ±15Hz), Bell (2225 ±10 Hz),
or Bell FSK originate tone (1270 ±10 Hz)
Detection range: -9 dBm to -43 dBm
Default detection threshold: -43 dBm
Response time: 75 ±2 ms
The passband and tone detect threshold can be changed in DSP RAM.
V.23 and V21 Tones: Tones can be detected as follows:
•
•
•
•
•
•
V.23 forward channel mark: 1300 ±10 Hz
V.23 backward channel mark: 390 ±10 Hz
V.21 high band mark (1650 ±10 Hz) or low band mark (980 ±10 Hz)
Detection range: -9 dBm to -43 dBm
Default detection threshold: -43 dBm
Response time: 25 ± 2 ms
The passbands and tone detect thresholds can also be changed in the DSP
RAM.
1.2.4.1 DTMF Detection
1.2.4.2 Equalizers
The modem can detect a valid DTMF tone pair (indicated by DTDET) and load a
corresponding hexadecimal code into the modem interface memory (DTDIG).
Equalization functions are incorporated that improve performance when
operating over low quality lines.
Automatic Adaptive Equalizer. An automatic adaptive equalizer in the receiver
compensates for transmission line amplitude and group delay distortion.
Updating of the taps can be enabled or disabled (EQFZ bit). The equalizer taps
can also be reset (EQRES bit).
Fixed Compromise Equalizers. Fixed compromise equalizers are provided in
the transmitter and receiver. The equalizers are programmable in DSP RAM.
1.2.4.3 Transmit Level
The transmitter output level is -10 dBm ±1 dB using the internal hybrid circuit.
The attentuation is selectable from 0 dBm to -15 dBm in 1 dB steps (TLVL bits).
1.2.4.4 Transmit Timing
Transmitter timing is selectable between internal (±0.01%), external, or loopback
(TXCLK bits). When external clock is selected, the external clock rate must equal
the desired data rate ±0.01% with a duty cycle of 50 ±20%.
1.2.4.5 Scrambler/
Descrambler
The modem incorporates a self-synchronizing scrambler/descrambler satisfying
the applicable CCITT or Bell requirement. The scrambler and descrambler can be
enabled or disabled (SDIS and DDIS bits, respectively).
1-2
D96V24DSA
RC96V24DP
1.0 Functional Description
Single Device Data/Modem Data Pump
1.2.4.6 Receive Level
1.2 Technical Specifications
The receiver satisfies performance requirements for a received line signal from
-9 dBm to -43 dBm. The default RLSD turn-on and RLSD turn-off thresholds are
-43 dBm and -48 dBm, respectively. The RLSD threshold levels are
programmable in DSP RAM.
1.2.4.7 Receiver Timing
The modem can track a frequency error up to ±0.03% in the associated transmit
timing source.
1.2.4.8 Carrier
Recovery
The modem can track a frequency offset up to ±7 Hz in the received carrier with
less than a 0.2 dB degradation in bit error rate (BER).
D96V24DSA
1-3
RC96V24DP
1.0 Functional Description
Single Device Data/Modem Data Pump
1.2 Technical Specifications
Table 1-1. Configurations, Signaling and Data Rates
Transmitter Carrier
Frequency (Hz) ±0.01%
Data Rate
(bps)
Baud
Bits Per
Constellation
Sample
Rate
Modulation
Answer2
Originate2
±0.01%
(Symbols/
Sec)
Symbol
Points
(Samples/
Sec)
V.22 bis
QAM
2400
1200
24003
600
4
16
7200
V.22
DPSK
2400
2400
1200
1200
12003
600
600
2
1
4
2
7200
7200
Configuration
Data Modes
6003
Bell 212A
DPSK
2400
1200
12003
600
2
4
7200
Bell 103
FSK
2225 M
2025 S
1270 M
1070 S
0-3004
0-3004
1
1
7200
V.21
FSK
1650 M
1850 S
980 M
1180 S
0-3004
0-3004
1
1
7500
FSK
1300 M
2100 S
1300 M
2100 S
1200
1200
1
1
96005
FSK
390 M
450 S
390 M
450 S
75
75
1
1
7200
V.29
QAM
QAM
QAM
1700
1700
1700
1700
1700
1700
9600
7200
4800
2400
2400
2400
4
3
2
16
8
4
9600
7200
9600
V.27 ter
DPSK
DPSK
1800
1800
1800
1800
4800
2400
1600
1200
3
2
8
4
9600
9600
FSK
1650 M
1850 S
1650 M
1850 S
300
300
1
1
9600
V.23 Forward
5
Channel
V.23 Backward
Channel5
Fax Modes6
V.21 channel 2
Dial/Call
Progress Mode
600
7200
Tone Generator/
Tone Detector
Mode
600
7200
Notes:
(1) Modulation legend:
QAM
Quadrature Amplitude Modulation
DPSK
Differential Phase Shift Keying
FSK
Frequency Shift Keying
(2) M indicates a mark condition; S indicates a space condition.
(3) Synchronous accuracy = ±0.01%; asynchronous accuracy = -2.5% to +1.0% (+2.3% if extended overspeed is selected).
(4) Value is upper limit for serial (e.g. 0-300).
(5) RC2324DPL only.
(6) RC96V24DP only.
(7) 9600 samples per sec in V.23 FDX Tx75/Rx1200; 7200 samples per second in V.23 FDX Tx1200/Rx75.
1-4
D96V24DSA
RC96V24DP
1.0 Functional Description
Single Device Data/Modem Data Pump
1.2 Technical Specifications
Table 1-2. Dial Digits/Tone Pairs
1.2.4.9 RTS-CTS TurnOn and Turn-Off
Sequences
Dial Digit
Tone 1 (Hz)
Tone 2 (Hz)
1
697
1209
2
697
1336
3
697
1447
4
770
1209
5
770
1336
6
770
1447
7
852
1209
8
852
1336
9
852
1477
0
941
1336
*
941
1209
#
941
1477
Spare B
967
1633
RTS ON to CTS ON and RTS OFF to CTS OFF response times are listed in
Table 1-3.
In V.21, the transmitter turns off within 10 ms after RTS goes OFF.
For V.29, the turn-off sequence consists of approximately 5 ms of remaining
data and scrambled ones followed by a 50 ms period of no transmitted energy.
For V.27 ter, the turn-off sequence consists of approximately 7 ms of
remaining data and scrambled ones at 1200 baud or approximately 7.5 ms of data
and scrambled ones at 1600 baud followed by a 20 ms period of no transmitted
energy.
1.2.5 Serial or Parallel Interface
The TPDM bit selects serial or parallel interface.
Serial Interface. The five hardware lines (RXD, TXD, TDCLK, RDCLK, and
XTCLK) are supported by four control and status bits in the interface memory
(CTS, DSR, RTS, and RLSD).
Parallel Interface. A 8086-compatible parallel microprocessor bus is supported.
D96V24DSA
1-5
RC96V24DP
1.0 Functional Description
Single Device Data/Modem Data Pump
1.2 Technical Specifications
1.2.6 Voice Mode
Transmit Voice. Transmit voice samples can be sent to the modem digital-toanalog converter (DAC) from the host through the transmit data buffer.
Receive Voice. Received voice samples from the modem analog-to-digital
converter (ADC) can be read by the host from the receive data buffer.
1.2.7 Asynchronous Conversion
Asynchronous mode is selected by the ASYNC bit. The asynchronous character
format is 1 start bit, 5 to 8 data bits (WDSZ bits), an optional parity bit (PARSL
and PEN bits), and 1 or 2 stop bits (STB bit). Valid character size, including all
bits, is 7, 8, 9, 10 or 11 bits per character.
Table 1-3. RTS-CTS Response Times
Configuration
Turn On
Time
Turn Off
Time
Data Modes
V.22 bis, V.22, and Bell 212A (CC bit = 0)
≤ 2 ms
≤ 2 ms
V.22 bis, V.22, and Bell 212A (CC bit =1)
270 ms
≤ 2 ms
V.21 and Bell 103
2-5 ms
10 ms
V.23 (RC96V24DP and RC2324DPL only)
11 ms
≤ 2 ms
V.29 (All speeds)
253 ms
≤ 2 ms
V.27 4800
898 ms
≤ 2 ms
V.27 2400
1133 ms
9 ms
V.21
20 ms
4 ms
V.29 (All speeds)
253 ms
≤ 2 ms
V.27 4800
1103 ms
≤ 2 ms
V.27 2400
1338 ms
9 ms
V.21
3095 ms
4 ms
Fax Modes (RC96V24DP only)
Echo Protector Tone Disabled (NV25 = 1)
Echo Protector Tone Enabled (NV25 = 0)
Signalling Rate Range. Signalling rate range is selectable by the EXOS bit:
• Basic range: +1% to -2.5%
• Extended overspeed range: +2.3% to -2.5%
Break. Break is handled as described in V.22 bis.
1-6
D96V24DSA
RC96V24DP
1.0 Functional Description
Single Device Data/Modem Data Pump
1.2.7.1 Power and
Environmental
Requirements
1.2 Technical Specifications
The power requirements are specified in Table 1-4. The environmental
specifications are listed in Table 1-5.
Table 1-4. Modem Power Requirements
Voltage
Mode
Current (Typ)
@ 25°C
Current (Max)
@ 0°C
5VDC ±5%
Operating
60 mA
90 mA
Sleep
3 mA
4.5 mA
Note:
Input voltage ripple ≤ 0.1 volts peak-to-peak. The amplitude of any frequency
between 20 kHz and 150 kHz must be less than 500 microvolts peak.
Table 1-5. Modem Environmental Specifications
Parameter
Specification
Temperature
Operating
0º C to 70º C (32º F to 158º F)
Storage
-40º C to 80º C (-40º F to 176º F)
Relative Humidity
Up to 90% noncondensing, or a
wet bulb temperature up to 35º C,
whichever is less.
Altitude
-200 feet to +10,000 feet
D96V24DSA
1-7
RC96V24DP
1.0 Functional Description
Single Device Data/Modem Data Pump
1.2 Technical Specifications
1-8
D96V24DSA
2.0
2.0 Hardware Interface
The modem functional hardware interface signals are shown in Figure 2-1. In this
diagram, any point that is active low is represented by a small circle at the signal
point.
Edge triggered inputs are denoted by a small triangle (e.g., TDCLK). OpenCollector (open-source or open-drain) outputs are denoted by a small half-circle
(e.g., IRQ). Active low signals are overscored (e.g., POR).
A dock intended to activate logic on its rising edge (low-to-high transition) is
called active low (e.g., RDCLK), while a clock Intended to activate logic on its
falling edge (high-to-low transition) is called active high (e.g., TDCLK). When a
clock input is associated with a small circle, the input activates on a falling edge.
If no circle is shown, the input activates on a rising edge.
The modem pin assignments are shown in Figure 2-2. The pin assignments are
listed by pin number in Table 2-1.
The hardware interface signal functions are summarized by major interface in
Table 2-2.
The digital and analog interface characteristics are defined in Table 2-3 and
Table 2-4, respectively.
D96V24DSA
2-1
RC96V24DP
2.0 Hardware Interface
Single Device Data/Modem Data Pump
Figure 2-1. RC9623DP Functional Interface Signals
OSCILLOSCOPE
TXD
TDCLK
SERIAL
INTERFACE
XTCLK
RXD
EYEX
RDCLK
EYEY
EYESYNC
RC96V24DP
MODEM
DEVICE
READ
WRITE
DATA BUS (8)
HOST
PROCESSOR
BUS
INTERFACE
D0-D7
ADDRESS BUS (5)
RS0-RS4
EYE
PATTERN
GENERATOR
(OPTIONAL)
EYECLK
RXA
TXA1
TXA2
DECODER
CS
RADVR
IRQ
TELEPHONE
LINE
INTERFACE
RING
RBDVR
+5V
XTLI
CRYSTAL
XTLO
SPKR
SPEAKER
AMPLIFIER
(OPTIONAL)
+5V
DGND
RESET
AGND
NOTE: REQUIRED EXTERNAL COMPONENTS
ARE NOT SHOWN
2-2
D96V24DSA
RC96V24DP
2.0 Hardware Interface
Single Device Data/Modem Data Pump
9
8
7
6
5
4
3
2
1
68
67
66
65
64
63
62
61
EYESYNC
EYEX
EYEY
RING
SLEEP
TEST1
RS0
RS1
RS2
RS3
RS4
READ
CS
WRITE
IRQ
D0
D1
Figure 2-2. RC9623DP Pin Signals
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
D2
D3
D4
D5
D6
D7
DGND2
SPKR
+5VA
MODEI
TSTBI
TRSTI
TDACI
RADCO
RRSTI
RSTBI
NC
RRSTO
RDCLK
RXD
TXA2
TXA1
RXA
RFILO
AGCIN
VC
NC
NC
NC
RBDVR
AGND
RADVR
SLEEPI
RADCI
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
RESET
XTAI
XTALP
+5VD
GP18
GP16
XTCLK
DGND1
TXD
TDCLK
TRSTO
TSTBO
TDACO
RADCI
RAGCO
MODEO
RSTBO
Table 2-1. RC9623DP Modem Device Pin Signals
Pin Number
Signal Name
I/O Type
1
RS2
IA
2
RS1
IA
3
RS0
IA
4
TEST1
5
SLEEP
6
RING
7
EYEY
OB
8
EYEX
OB
9
EYESYNC
OB
10
RESET
ID
11
XTLI
IE
12
XTLO
OB
13
+5VD
14
GP18
D96V24DSA
OA
OA
2-3
RC96V24DP
2.0 Hardware Interface
Single Device Data/Modem Data Pump
Table 2-1. RC9623DP Modem Device Pin Signals (Continued)
2-4
Pin Number
Signal Name
I/O Type
15
GP16
OA
16
XTCLK
IA
17
DGND1
18
TXD
IA
19
TDCLK
OA
20
TRSTO
MI
21
TSTBO
MI
22
TDACO
MI
23
RADCI
MI
24
RAGCO
MI
25
MODEO
MI
26
RSTBO
MI
27
RRSTO
MI
28
RDCLK
OA
29
RXD
OA
30
TXA2
O(DD)
31
TXA1
O(DD)
32
RXA
I(DA)
33
RFILO
MI
34
AGCIN
MI
35
VC
36
NC
37
NC
38
NC
39
RBDVR
40
AGND
41
RADRV
OD
42
SLEEP1
IA
43
RAGCI
MI
44
NC
45
RSTBI
D96V24DSA
OD
MI
RC96V24DP
2.0 Hardware Interface
Single Device Data/Modem Data Pump
Table 2-1. RC9623DP Modem Device Pin Signals (Continued)
Pin Number
Signal Name
I/O Type
46
RRSTI
MI
47
RADCO
MI
48
TDACI
MI
49
TRSTI
MI
50
TSTBI
MI
51
MODE1
MI
52
+5VA
53
SPKR
54
DGND2
55
D7
IA/OB
56
D6
IA/OB
57
D5
IA/OB
58
D4
IA/OB
59
D3
IA/OB
60
D2
IA/OB
61
D1
IA/OB
62
D0
IA/OB
63
IRQ
OC
64
WRITE
IA
65
CS
IA
66
READ
IA
67
RS4
IA
68
RS3
IA
O(OF)
Notes:
(1) MI = Modem Interconnection
(2) NC = No connection (may have internal connection; leave pin disconnected (open).
(3) I/O types are described in Table 2-3 (digital signals) and Table 2-4 (analog signals).
D96V24DSA
2-5
RC96V24DP
2.0 Hardware Interface
Single Device Data/Modem Data Pump
Table 2-2. Hardware Interface Signal Definitions
Label
I/O Type
Signal/Definition
OVERHEAD SIGNALS
XTLI
IEOB
Crystal/Clock ln and Crystal Out. The DSP must be connected to an external crystal
circuit consisting of a 24.00014 MHz crystal and two capacitors. Alternatively, XTLI,
may be driven with a buffered clock (e.g., square wave generator) or a sine wave
oscillator.
RESET
ID
+5VD
PWR
+5V Digital Supply. +5V ±5% is required.
+5VA
PWR
+5V Analog Supply. +5V ±5% is required.
DGND
GND
Digital Ground.
DGND
GND
Analog Ground.
Reset. The active low RESET input resets the internal modem logic. Upon transition of
RESET from low-to-high, the DSP interface memory bits are set to the default values.
SERIAL INTERFACE
Five TTL-level hardware interface circuits implement a CCITT V.24-compatible serial
data interface with control signals provided through the DSP interface memory.
RDCLK
OA
Receive Data Clock. In synchronous mode, the modem outputs a Receive Data Clock
(RDCLK in the form of 50 ±1% duty cycle square wave. The low-to-high transitions of
this output coincide with the center of received data bits.
TDCLK
OA
Transmit Data Clock. In synchronous mode, the modem outputs a Transmit Data Clock
(TDCLK). The TDCLK clock frequency is data rate ±0.01% with a duty cycle of 50 ±1%.
XTCLK
IA
External Transmit Clock. In synchronous mode, an external transmit data clock input
(XTCLK) can be supplied.
RXD
OA
TXD
IA
Received Data. The modem presents received serial data on the Received Data (RXD)
output and to the interface memory Receive Data Register (RBUFFER) in both serial and
parallel modes.
Transmitted Data. The modem obtains serial data to be transmitted on the TXD input in
serial mode, or from the interface memory Transmit Data Register (TBUFFER) in
parallel mode. (See TPDM bit.)
PARALLEL MICROPROCESSOR INTERFACE
Address, data, control and interrupt hardware interface signals implement an 8086compatible parallel microprocessor interface to a host processor. This parallel interface
allows the host to change modem configuration, read or write channel and diagnostic
data, and supervise modem operation by writing control bits and reading status bits.
2-6
D0-D7
IA/OA
CS
IA
Data Lines. Eight bidirectional data lines (DO-D7) provide parallel transfer of data
between the host and the modem.
Chip Select. The active low Chip Select (CS) input enables parallel data transfer over
the microprocessor bus.
D96V24DSA
RC96V24DP
2.0 Hardware Interface
Single Device Data/Modem Data Pump
Table 2-2. Hardware Interface Signal Definitions (Continued)
Label
I/O Type
RS0-RS4
IA
READ
IAIA
Signal/Definition
PARALLEL MICROPROCESSOR INTERFACE (con’t)
WRITE
Register Select Lines. The five active high Register Select inputs (RS0 - RS4) address
Interface memory registers in the modem when CS is low. These lines are typically
connected to address lines A0-A4 to address one of 32 8-bit internal interface memory
registers (00-1F). The selected register can be read from, or written into, via the 8-bit
parallel data bus (DO-D7).
Read Enable and Write Enable. Reading or writing is controlled by the host pulsing
either READ or WRITE input low, respectively, during the microprocessor bus access
cycle.
During a write cycle, data from the data bus is copied into the addressed DSP interlace
memory register, with high and low bus levels representing one and zero bit states,
respectively.
IRQ
OA
Interrupt Request. The IRQ output structure is an open-drain field-effect-transistor
(FET). The IRQ output can be enabled in the interface memory to allow immediate
indication of change of conditions in the modem. The use of IRQ is optional depending
upon modem application.
HYBRID CIRCUIT
TXA1
O(DF)
Transmit Analog 1 and 2. The TXA1 and TXA2 outputs are differential outputs 180
degrees out of phase with each other.
RXA
I(DA)
Receive Analog. RXA is a single-ended receive data input from the telephone line
interface or an optional external hybrid circuit.
VC
OA
TXA2
Centerpolnt Voltage. VC is a +2.5 VDC centerpoint voltage which serves as the internal
'analog ground' reference point.
TELEPHONE LINE INTERFACE
RADVR
OD
Relay A Driver. RADVR is an open drain output which can directly drive a relay with
greater than 360 Q coil resistance and having a 'must operate' voltage of no greater
than 4.0 VDC.
The RADVR output is controlled by the state of the RA bit, except in pulse dial mode.
When RA is a 1, the RADVR output is active which applies current to the relay coil.
In a typical application, RADVR is connected to the normally open Off-Hook relay. In
this case, RADVR active closes the Off-Hook relay to connect the modem to the
telephone line.
RBDVR
OD
Relay B Driver. RBDVR is an open drain output which can directly drive a relay with
greater than 360 Q coil resistance and having a 'must operate' voltage of no greater
than 4.0 VDC.
RBDVR output is controlled by the state of the RB bit. When RB is a 1, the RBDVR
output is active which applies current to the relay coil.
In a typical application, RBDVR is connected to the normally closed Talk/Data relay. In
this case, RBDVR active opens the relay to disconnect the handset from the telephone
line.
RING
IA
Ring Frequency. A low-going edge on the RING input initiates a ring frequency
measurement. A valid ring detection is indicated by the RI bit.
D96V24DSA
2-7
RC96V24DP
2.0 Hardware Interface
Single Device Data/Modem Data Pump
Table 2-2. Hardware Interface Signal Definitions (Continued)
Label
I/O Type
Signal/Definition
SPEAKER INTERFACE
SPKR
O(DF)
Speaker Analog Output. The SPKR output reflects the received analog input signal. The
SPKR on/off and three levels of attenuation are controlled by interface memory bits.
When the speaker is turned off, the SPKR output is clamped to the voltage at the VC
pin. The SPKR output can drive an impedance as low as 300 ohms. In a typical
application, the SPKR output is an input to an external LM386 audio power amplifier.
SLEEP MODE SIGNALS
SLEEP
OA
SLEEP1
IA
Sleep Mode Output and Sleep Mode Input. SLEEP output high indicates the DSP is
operating in its normal mode. SLEEP low indicates that the DSP is in the sleep mode.
This signal must be connected to the SLEEP1 input to power down the IA in the sleep
mode. SLEEP can also be used to control power to other devices (e.g., as a speaker
enable).
DIAGNOSTIC SIGNALS
Four signals provide the timing and data necessary to create an oscilloscope quadrature
eye pattern. The eye pattern is simply a display of the received baseband constellation.
By observing this constellation, common line disturbances can usually be identified.
EYEX,
OB
Eye Pattern Data X and Eye Pattern Data Y. The EYEX and EYEY outputs provide two
serial bit streams containing data for display on the oscilloscope horizontal (X) axis and
vertical (Y) axis, respectively. This serial digital data can be converted to analog form
using two shift registers and two digital-to-analog converters (DACs).
OA
Eye Pattern Clock. EYECLK is a clock for use by the serial-to-parallel converters. The
EYECLK output is a 7200/9600 Hz clock.
EYEY
EYECLK
(RRSTO)
EYESYNC
OB
Eye Pattern Sync. EYESYNC is a strobe for word synchronization. The falling edge of
EYESYNC may be used to transfer the 8-bit word from the shift register to a holding
register. Digital-to-analog conversion can then be performed for driving the X and Y
inputs of an oscilloscope.
MODEM INTERCONNECT
RFILO
MI
Receive Filter Output. RFILO is the output of the internal receive analog filter which
must be connected to AGCIN through a 0.1 µF, 20%, DC decoupling capacitor.
AGCIN
MI
Receive AGC Gain Amplifier Input. See RFILO.
MODEO (DSP)
MI
Mode Control. Serial IA mode control bits. Direct modem interconnect line.
MI
Transmitter DAC Signal. Transmitter serial digital DAC signal. Direct modem
interconnect line.
MI
Transmitter Strobe. Transmitter 576 kHz digital timing reference. Direct modem
interconnect line.
MI
Transmitter Reset. Transmitter 7200/9600 Hz digital timing reference. Direct modem
interconnect line.
MODEI (IA)
TDACO (DSP),
TDACI (IA)
TSTBO (DSP),
TSTBI (IA)
TRSTO (DSP),
TRSTI (IA)
2-8
D96V24DSA
RC96V24DP
2.0 Hardware Interface
Single Device Data/Modem Data Pump
Table 2-2. Hardware Interface Signal Definitions (Continued)
Label
I/O Type
Signal/Definition
RADCI (DSP),
MI
Receiver ADC Signal. Receiver serial digital ADC signal. Direct modem interconnect
line.
MI
Receiver AGC Signal. Receiver serial digital AGC signal. Direct modem interconnect
line.
MI
Receiver Strobe. Receiver 576 kHz digital timing reference. Direct modem interconnect
line.
MI
Receiver Reset. Receiver 7200/9600 Hz digital timing reference. Direct modem
interconnect line.
MODEM INTERCONNECT (con’t)
RADCO (IA)
RAGCO (DSP),
RAGCI (IA)
RSRBO (DSP),
RSRBI (IA)
RRSTO (DSP),
RRSTI (IA)
Table 2-3. Digital Interface Characteristics
Parameter
Input High Voltage
Symbol
Min.
Typ.
Max.
2.0
0.8 (Vcc)
–
–
Vcc
Vcc
Input Low Voltage
VIL
-0.3
–
0.8
Vdc
Input Low Current
IIL
–
–
-400
µA
Output High Voltage
VOH
Types OA and OB
Type OD
Output Low Voltage
ITSI
Power Dissipation
PD
Operating
Sleep
Note:
–
–
–
Vcc
VOL
Three–State Input Current
(Off)
Vcc = 5.25V
Vdc
3.5
–
Types OA and OC
Type OB
Type OD
Test Conditions(1)
Vdc
VIH
Type IA
Type ID
Units
ILOAD = -100 µA
ILOAD = 0 mA
Vdc
–
–
–
–
–
0.4
0.4
0.75
–
–
±10
ILOAD = 1.6 mA
ILOAD = 0.8 mA
ILOAD = 15 mA
µA
VIN = 0.4 to Vcc -1
mW
–
–
300
15
450
22.5
(1) Test Conditions: Vcc = 5V ±5%, TA = 0°C to 70°C (unless otherwise noted).
D96V24DSA
2-9
RC96V24DP
2.0 Hardware Interface
Single Device Data/Modem Data Pump
Table 2-4. Analog Interface Characteristics
2-10
Name
Type
RXA
I (DA)
1458 type op amp input
TXA1, TXA2
O (DD)
1458 type op amp output
SPKR
O (DF)
1458 type op amp output
D96V24DSA
Characteristic
3.0 Software Interface
3.1 Interface Memory
The DSP communicates with the host by means of a dual-port, interface memory
The interface memory in the DSP contains thirty-two 8-bit registers, labeled
register 00 through 1F. Each register can be read from, or written into, by both the
host and the DSP. The host communicates with the DSP interface memory via the
microprocessor bus.
The host can control modem operation by writing control bits to DSP interface
memory and writing parameter values to DSP RAM through the interface
memory. The host can monitor modem operation by reading status bits from DSP
interface memory and reading parameter values from DSP RAM through
interface memory.
3.2 Interface Memory Map
A memory map of DSP interface memory identifying the contents of the 32
addressable registers is shown in Table 3-1. These 8-bit registers may be read or
written during any host read or write cycle. In order to operate on a single bit or
group of bits in a register, the host must read a register then mask out unwanted
data. When writing a single bit or group of bits in a register, the host must
perform a read-modify-write operation. That is, the host must read the entire
register, set or reset the necessary bits without altering the other register bits, then
write the unaffected and modified bits back into the interface memory register.
3.3 Interface Memory Bit Functions
Table 3-2 summarizes the functions of the individual bits in the interface memory.
Bits in the interface memory are referred to using the format Z:Q. The register
number is denoted by Z (00 through iF) and the bit number is located by Q (0
through 7, where 0 = LSB).
D96V24DSA
3-1
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.3 Interface Memory Bit Functions
Table 3-1. Interface Memory Map
Register
Function
Register
Address
(Hex)
Bit
7
6
5
4
3
2
1
0
1F
NSIA
NCIA
–
NSIE
NEWS
NCIE
–
NEWC
1E
TDBIA
RDBIA
TDBIE
–
TDBE
RDBIE
–
RDBF
1D
XACC
–
–
–
IOX
XCRD
XWT
XCR
YCRD
YWT
YCR
Interrupt Handling
1C
1B
RAM Access,
Control and Status
X RAM ADDRESS (XADD)
YACC
–
–
–
–
1A
Y RAM ADDRESS (YADD)
19
X RAM DATA MSB (XDAM)
18
X RAM DATA LSB (XDAL)
17
Y RAM DATA MSB (YDAM)
16
Y RAM DATA LSB (YDAL)
–
15
–
–
–
–
–
–
–
–
–
14
–
–
–
–
–
–
–
–
13
TLVL
VOL
TXCLK
Control
12
Transmit Data
Buffer
11
CONFIGURATION (CONF)
–
–
–
10
–
–
–
–
TXP
SYNCD
FLAGS
TRANSMIT DATA BUFFER (TBUFFER)
0F
RLSD
FED
CTS
DSR
RI
0E
RTDET
BRKD
PE
FE
OE
0D
–
PNDET
S1DET
SCR1
U1DET
0C
EDET
–
–
–
0B
TONEA
TONEB
TONEC
ATV25
ATBELL
0A
–
–
–
–
09
NV25
CC
DTMF
08
ASYNC
TPDM
07
RDLE
RDL
06
BRKS
EXOS
05
–
–
–
04
EQRES
SWRES
03
NRZIE
02
01
TM
SPEED
SADET
–
–
PNSUC
DTDET
BEL103
–
–
–
CRCS
ORG
LL
DATA
–
SLEEP
–
DDIS
TRFZ
–
RTRN
RTS
L2ACT
–
L3ACT
RB
RA
ABORT
PEN
STB
TXSQ
CEQE
RCEQ
TXVOC
–
–
–
EQFZ
IFIX
AGCFZ
CRFZ
HDLC
SPLIT
–
ARC
SDIS
GTE
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
RXP
Status
PARSL
DTDIG
WDSZ
Control
Receive Data Buffer
00
Note:
3-2
RECEIVE DATA BUFFER (RBUFFER)
‘ – ’ in the BIT columns indicates reserved for modem use only.
D96V24DSA
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.3 Interface Memory Bit Functions
Table 3-2. Interface Memory Bit Functions
Mnemonic
Memory
Location
ABORT
07:0
HDLC Abort. Controls sending of continuous mark in HDLC mode.
AGCFZ
04:1
AGC Freeze. inhibits updating of the receiver AGC.
ARC
03:3
Automatic Rate Change Enable. Enables automatic on-line rate change sequence.
ASYNC
08:7
Asynchronous/Synchronous. Selects asynchronous or synchronous data mode.
ATBELL
OB:3
Bell Answer Tone Detected. Reports detection status of 2225 Hz answer tone.
ATV25
OB:4
V25 Answer Tone Detected. Reports detection status of 2100 Hz answer tone.
BEL1O3
OB:0
Bell 103 Mark Frequency Detected. Reports detection status of 1270 Hz Bell 103 mark.
BRKD
OE:6
Break Detected. Reports receipt status of continuous space.
BRKS
06:7
Break Sequence. Controls sending of continuous space in parallel asynchronous mode.
CC
09:6
Controlled Carrier. Selects controlled or constant carrier mode.
CEQ
05:3
Compromise Equalizer Enable. Enables the transmit passband digital compromise
equalizer.
CONF
12:0-7
CRCS
OA:0
CRC Sending. Reports the sending status of the CRC (2 bytes) in HDLC mode.
CRFZ
04:0
CarrIer Recovery Freeze. Disables update of the receiver’s carrier recovery phase lock
loop.
CTS
OF:5
Clear to Send. Reports that the training sequence has been completed (see TPDM).
DATA
09:2
Data Mode. Selects idle or data mode.
DDIS
08:4
Descrambler Disable. Disables the receiver’s descrambler circuit.
DSR
OF:4
Data Set Ready. Reports the data transfer state.
DTDET
OB:1
DTMF Digit Detected. Reports that a valid DTFM digit has been detected.
DTDIG
00:0-3
DTMF
09:5
DTMF Dial Select. Selects either DTMF or pulse dialing in the dial mode.
EDET
00:7
Early DTMF Detect. Reports detection of the high group frequency of the DTMF tone
pair.
EQFZ
04:3
Equalizer Freeze. inhibits the update of the receiver’s adaptive equalizer taps.
EQRES
04:7
Equalizer Reset. Resets the receiver adaptive equalizer taps to zero.
EXOS
06:6
Extended Overspeed. Selects extended overspeed mode in asynchronous mode.
FE
OE:4
Framing Error. Reports framing error detection or detection of an ABORT sequence.
FED
OF:6
Fast Energy Detected. Reports energy above the turn-on threshold is being detected.
Name/Description
Modem Configuration Select. Selects the modem operating mode.
Detected DTMF Digit. Contains the hexadecimal code of the detected DTMF digit.
D96V24DSA
3-3
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.3 Interface Memory Bit Functions
Table 3-2. Interface Memory Bit Functions (Continued)
3-4
Mnemonic
Memory
Location
FLAGS
OF:0
Flag Sequence. Reports transmission status of the Flag sequence in HDLC mode, or
transmission of a constant mark in parallel asynchronous mode.
GTE
03:1
Guard Tone Enable. Enables transmission of the 1800 Hz guard tone (CCITT
configuration only).
HDLC
03:6
High Level Data Link Control. Enables HDLC protocol support in parallel data mode.
IFIX
04:2
Eye Fix. Forces EYEX and EYEY serial data to be rotated equalizer output.
IOX
1D:3
I/O Register Select. Specifies that the X RAM ADDRESS (XADD) is an internal I/O
register address.
L2ACT
07:5
Loop 2 (Local Digital Loopback) Activate. Selects connection of the receiver’s digital
output Internally to the transmitter’s digital input (locally activated digital loopback).
L3ACT
07:3
Loop 3 (Local Analog Loopback) Activate. Selects connection of the transmitter’s
analog output Internally to the receiver’s analog input (local analog Ioopback).
LL
09:3
Leased Line. Selects leased line data mode or handshake mode.
NCIA
1F:6
NEWC Interrupt Active. Reports that the cause of an interrupt request was completion of
a configuration change. (See NEWC and NCIE.)
NCIE
1F:2
NEWC interrupt Enable. Enables the assertion of IRQ and the setting of the NCIA bit.
NEWC
I F:0
New Configuration. Initiates a new configuration; cleared by the modem upon
completion of configuration change. This bit can cause IRQ to be asserted. (See NCIE
and NCIA.)
NEWS
1F:3
New Status. Reports the detection of a change In selected status bits. This bit can cause
IRQ to be asserted. (See NSIE and NSIA.)
NSIA
1F:7
NEWS Interrupt Active. Reports that the cause of an interrupt request was a status bit
change. (See NEWS and NSIE.)
NSIE
1F:4
NEWS interrupt Enable. Enables the assertion of IRQ and the setting of the NSIA bit.
(See NEWS.)
NV25
09:7
Disable V.25 Answer Sequence (Data Modes), Disable Echo Suppressor Tone (Fax
Modes). Disables the transmitting of the 2100 Hz CCI1T answer tone when a handshake
sequence Is initiated In a data mode or disables sending of the echo suppressor tone in a
fax mode.
OE
OE:3
Overrun Error. Reports overrun status of the Receiver Data Buffer (RBUFFER).
ORG
09:4
Originate. Selects originate or answer mode.
PE
OE:5
Parity Error. Reports parity error status or bad CRC
PNSUC
OB:2
PN Success. Indicates that the receiver has detected the PN portion of the training
sequence.
RA
07:1
Relay A Activate. Activates the RADRV output.
PARSL
06:4.5
Name/Description
Parity Select. Selects stuff, space, even, or odd parity in the asynchronous parallel data
mode.
D96V24DSA
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.3 Interface Memory Bit Functions
Table 3-2. Interface Memory Bit Functions (Continued)
Mnemonic
Memory
Location
RB
07:2
RBUFFER
00:0-7
RDBF
1E:0
Receiver Data Buffer Full. Reports the status (full or not full) of the Receiver Data Buffer
(RBUFFER). (See RDBIE and RDBIA.)
RDBIA
1E:6
Receiver Data Buffer interrupt Active. Reports that the cause of an interrupt request Is
the Receiver Data Buffer (RBUFFER) full. (See RDBF and RDBIE.)
RDBIE
I E:2
Receiver Data Buffer interrupt Enable. Enables the assertion of IRQ and the setting of
the RDBIA bit when RBUFFER is full. (See RDBF and RDBIA.)
RDL
07:6
Remote Digital Loopback Request. initiates a request for the remote modem to go into
digital loop-back.
RDLE
07:7
Remote Digital Loopback Response Enable. Enables the modem to respond to the
remote modem’s digital loopback request.
PEN
06:3
Parity Enable. Enables generation/checking of parity in asynchronous parallel data
mode.
RCEQ
05:2
Receiver Compromise Equalizer Enable. Controls insertion of the receive passband
digital compromise equalizer into the receive path.
RI
0F:3
Ring Indicator. Reports detection status of a valid ringing signal.
RTDET
0E:7
Retrain Detected. Reports detection status of a retrain request sequence.
RTRN
08:1
Retrain. Controls sending of the retrain request or automatic rate change to the remote
modem.
RTS
08:0
Request to Send. Requests the transmitter to send data.
RLSD
0F:7
Received Line Signal Detector. Reports detection status of the carrier and the receipt of
valid data.
RXP
01:0
Received Parity bit. This bit is the received parity bit (or ninth data bit).
S1DET
00:5
S1 Sequence Detected. Reports detection status of the S1 sequence.
SADET
00:2
Scrambled Alternating Ones Sequence Detected. Reports detection status of the
Scrambled Alternating Ones sequence.
SCR1
00:4
Scrambled Ones Sequence Detected. Reports detection status of Scrambled Ones
sequence.
SDIS
03:2
Scrambler Disable. Disables the transmitter scrambler.
SLEEP
09:0
Sleep Mode. Controls entry Into the SLEEP mode. The modem requires a pulse on the
RESET pin to return to normal operation.
SPEED
0E:0-2
SPLIT
03:5
Extended Overspeed TX/RX Split. Limits transmit data to the basic overspeed rate.
STB
06:2
Stop Bit Number. Selects the number of stop bits in asynchronous mode.
SWRES
04:6
Software Reset. Causes the modem to reinitialize to Its power turn-on state.
Name/Description
Relay B Activate. Activates the RBDVR output.
Receive Data Buffer. Contains the received byte of data.
Speed Indication. Reports the data rate at the completion of a connection.
D96V24DSA
3-5
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.3 Interface Memory Bit Functions
Table 3-2. Interface Memory Bit Functions (Continued)
3-6
Mnemonic
Memory
Location
TBUFFER
10:0-7
TDBE
1E:3
Transmitter Data Buffer Empty. Reports the status (empty or not empty) of the Transmit
Data Buffer (TBUFFER). (See TDBIE and TDBIA.)
TDBIA
1E:7
Transmitter Data Buffer Interrupt Active. Reports that the cause of an interrupt request
Is the Transmit Data Buffer (TBUFFER) empty. (See TDBE and TDBIE.)
TDBIE
1E:5
Transmitter Data Buffer interrupt Enable. Enables assertion of IRQ and the setting of the
TDBIA bit when the TBUFFER is empty. (See TDBE and TDBIA.)
TLVL
13:4-7
Transmit Level Attenuation Select. Selects the transmitter analog output level
attenuation In 1 dB steps. The host can fine tune the transmit level to a value lying within
a 1 dB step In DSP RAM.
TM
0F:2
Test Mode. Reports active status of the selected test mode.
TONEA
0B:7
Tone Filter A Energy Detected. Reports status of energy above the threshold detection
by the Call Progress Monitor filter in the Dial Configuration or 1300 Hz FSK tone energy
detection by the Tone A bandpass filter In the Tone Detector configuration.
TONEB
OB:6
Tone Filter B Energy Detected. Reports status of 390 Hz FSK tone energy detection by
the Tone B bandpass filter in the Tone Detector configuration.
TONEC
05:5
Tone Filter C Energy Detected. Reports status of 1650 Hz or 980 Hz (selected by the
ORG bit) FSK tone energy detection by the Tone C bandpass filter in the Tone Detector
configuration.
TPDM
08:6
Transmitter Parallel Data Mode. Selects transmitter parallel or serial mode.
TRFZ
08:3
Timing Recovery Freeze. Inhibits the update of the receiver’s timing recovery algorithm.
TXCLK
13:0,1
TXP
11:0
Transmit Parity Bit (or 9th Data Bit). This bit Is the stuffed parity bit (or ninth data bit)
for transmission.
TXSQ
05:4
Transmitter Squelch. Disables transmission of energy.
TXVOC
05:1
Transmit Voice. Enables the sending of voice samples.
U1DET
OD:3
Unscrambled Ones Detected. Reports detection status of the Unscrambled Ones
sequence.
WDSZ
06:0,1
Data Word Size. Selects the number of data bits per character in asynchronous mode (5,
6, 7. or 8).
VOL
13:2-3
Volume Control. Two-bit encoded speaker volume selects volume off or one of three
volume on levels.
XACC
1D:7
X RAM Access Enable. Controls DSP access of the X RAM associated with the address
in XADD and the XCR bit. XWT determines it a read or write is performed.
XADD
1C:0-7
X RAM Address. Contains the X RAM address used to access the DSP’s X Data RAM or X
Coefficient RAM (selected by XCR) via the X RAM Data LSB and MSB registers.
Name/Description
Transmitter Data Buffer. Contains the byte to be transmitted in the parallel mode.
Transmit Clock Select. Selects the transmitter data clock (internal, disable, slave, or
external).
D96V24DSA
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.4 DSP RAM Access
Table 3-2. Interface Memory Bit Functions (Continued)
Mnemonic
Memory
Location
Name/Description
XCR
1D:0
X Coefficient RAM Select. Controls XADD access to the DSP’s X Coefficient RAM or the
X Data RAM.
XCRD
1D:2
X RAM Continuous Read. Enables read of X RAM every sample from the location
addressed by XADD independent of the XACC and XWT bits.
XDAL
18:0-7
X RAM Data LSB. The least significant byte of the 16-bit X RAM data word used in
reading or writing X RAM locations in the DSR
XDAM
19:0-7
X RAM Data MSB. The most significant byte of the 16-bit X RAM data word used In
reading or writing X RAM locations in the DSR
XWT
1D:1
X RAM Write. Controls the reading of data from, or the writing of data to, the X RAM
Data registers (18 and 19) using the X RAM location addressed by XADD and XCR.
YACC
1B:7
Y RAM Access Enable. Controls DSP access of the Y RAM associated with the address
In YADD and the YCR bit. YWT determines if a read or write is performed.
YADD
1A0-7
Y RAM Address. Contains the Y RAM address used to access the DSP’s V Data RAM or V
Coefficient RAM (selected by YCR) via the Y RAM Data LSB and MSB registers.
YCR
15:0
Y Coefficient RAM Select. Controls YADD access to the DSP’s Y Coefficient RAM or the
Y Data RAM.
YCRD
15:2
Y RAM Continuous Read. Enables read of Y RAM every sample from the location
addressed by YADD Independent of the YACC and YWT bits.
YDAL
16:0-7
Y RAM Data LSB. The least significant byte of the 16-bit Y RAM data word used in
reading or writing Y RAM locations in the DSP
YDAM
17:0-7
Y RAM Data MSB. The most significant byte of the 16-bit Y RAM data word used in
reading or writing Y RAM locations in the DSP.
YWT
1B:1
Y RAM Write. Controls the reading of data from, or the writing of data to. the Y RAM
Data registers (16 and 17) using the Y RAM location addressed by YADD and YCR.
3.4 DSP RAM Access
The DSP contains four sections of 16-bit wide random access memory (RAM).
Because the DSP is optimized for performing complex arithmetic, the RAM is
organized into real (X RAM) and imaginary (Y RAM) sections, as well as data
and coefficient sections. The host processor can access (read or write) the X
RAM only, the Y RAM only, or both the X RAM and the Y RAM simultaneously
in either the data or coefficient section.
D96V24DSA
3-7
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.5 Interface Memory Access to DSP RAM
3.5 Interface Memory Access to DSP RAM
The DSP Interface memory acts as an intermediary during host to DSP RAM or
DSP RAM to host data exchanges. The addresses stored in modem Interface
memory RAM Address registers (i. e., XADD and YADD) by the host, in
conjunction with the data or coefficient RAM bits (i. e., XCR and YCR)
determine the DSP RAM addresses for data access.
3.6 Host Programmable Data
The parameters available In DSP RAM are listed in Table 3-3 along with the X
RAM or Y RAM address and corresponding XCR or YCR bit value. The scaling
for the host programmable data is described in the Modem Designer’s Guide.
Table 3-3. DSP RAM Parameters
No.
XCR/YCR(1)
X RAM
Addr
Y RAM
Addr
1
0-1E
1
0
–
First coefficient, Real (1) (Data/Fax)
1
10
–
Last Coefficient, Real (17) (Data)
1
1E
–
Last Coefficient, Real (31) (Fax)
Parameter
Adaptive Equalizer Coefficients, Real
1
1
0-1E
Adaptive Equalizer Coefficients, Imag.
1
–
0
First Coefficient, Imag. (1) (Data/Fax)
1
–
10
Last Coefficient, Imag. (17) (Data)
1
–
1E
Last Coefficient, Imag. (31) (Fax)
3
0
49
–
Rotated Error, Real
4
0
–
49
Rotated Error, Imaginary
5
0
3F
–
Max AGC Gain Word
6
0
71
–
Pulse Dial Interdigit Time
7
0
7C
–
Tone Dial Interdigit Time
8
0
72
–
Pulse Dial Relay Make Time
9
0
7D
–
Pulse Dial Relay Break Time
10
0
7E
–
DTMF Duration
2
3-8
D96V24DSA
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.6 Host Programmable Data
Table 3-3. DSP RAM Parameters (Continued)
No.
XCR/YCR(1)
X RAM
Addr
Y RAM
Addr
11
0
6C
–
Tone 1 Angle Increment Per Sample (TXDPHI1)
12
0
6D
–
Tone 2 Angle Increment Per Sample (TXDPHI2)
13
0
6E
–
Tone 1 Amplitude (TXAMP1)
14
0
6F
–
Tone 2 Amplitude (TXAMP2)
15
0
73
–
Max Samples Per Ring Frequency Period (RDMAXP)
16
0
74
–
Min Samples Per Ring Frequency Period (RDMINP)
17
0
5E
–
Real Part of Error
18
0
–
5E
Imaginary Part of Error
19
0
–
3D
Rotation Angle for Carrier Recovery
20
0
59
–
Rotated Equalizer Output, Real
21
0
–
59
Rotated Equalizer Output, Imaginary
22
0
3C
–
Lower Part of Phase Error
23
0
–
3C
Upper Part of Phase Error
24
1
3F
–
Upper Part of AGC Gain Word
25
1
3E
–
Lower Part of AGC Gain Word
26
1
2E
–
Average Power
27
1
2D
–
Phase Error
28
1
2F
–
Tone Power (TONEA)
29
1
30
–
Tone Power (ATBELL, BEL103, or TONEB)
30
1
31
–
Tone Power (TONEC, ATV25)
31
1
36
–
Tone Detect Threshold for TONEA (THDA)
32
1
37
–
Tone Detect Threshold for ATBELL, BEL103, or TONEB (THDB)
33
1
38
–
Tone Detect Threshold for TONEC or ATV25 (THDC)
Parameter
D96V24DSA
3-9
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.7 Modem Interface Circuit
Table 3-3. DSP RAM Parameters (Continued)
XCR/YCR(1)
X RAM
Addr
Y RAM
Addr
1
–
6C
Biquad 1 Coefficient α0
1
–
6D
Biquad 1 Coefficient α1
1
–
6E
Biquad 1 Coefficient α2
1
–
6F
Biquad 1 Coefficient β1
1
–
70
Biquad 1 Coefficient β2
1
–
71-75
Biquad 2 Coefficients α0 – β2
1
–
76-7A
Biquad 3 Coefficients α0 – β2
1
–
7B-7F
Biquad 4 Coefficients α0 – β2
1
–
62-66
Biquad 5 Coefficients α0 – β2
1
–
67-6B
Biquad 6 Coefficients α0 – β2
35
0
32
–
Turn-on Threshold
36
1
79
–
Turn-off Threshold
37
1
–
21
RLSD Turn-off Time
38
0
70
–
Transmit Level Output Attenuation
39
1
52
–
Eye Quality Monitor (EQM)
No.
34
Parameter
Note: (1)XCR if an XRAM address is listed; YCR if a YRAM address is listed.
3.7 Modem Interface Circuit
The recommended modem Interface circuit is shown in Figure 3-1.
3-10
D96V24DSA
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.7 Modem Interface Circuit
Figure 3-1. Typical Modem Interface Circuit
VCC
C14
.1
L1
47
C9
12
10%
20V
100
U7
D0
D1
D2
D3
D4
D5
D6
D7
IRQ*
WRITE*
READ*
CS*
RS4
RS3
RS2
RS1
RS0
XTCLK
TXD
T D C LK
RDCLK*
RXD
R E S ET*
Y1
3
VCC
TEST*
RRSTO
RRSTI
EYESYNC
EYEX
EYEY
RESET*
D0
D1
D2
D3
D4
D5
D6
D7
IRQ*
WRITE*
READ*
CS*
RS4
RS3
RS2
RS1
RS0
XTCLK
TXD
TDCLK
RDCLK*
RXD
GP16
DGND1
DGND2
AGND
52
12
11
22
48
25
51
20
49
26
45
21
50
47
23
24
43
39
41
32
31
30
35
6
34
33
5
42
53
36
37
38
44
14
VAA
XTLO
XTLI
TDACO
TDACI
MODEO
MODEI
TRSTO
TRSTI
RSTBO
RSTBI
TSTBO
TSTBI
RADCO
RADCI
RAGCO
RAGCI
RBVDR*
RADVR
RXA
TXA1
TXA2
VC
RING*
AGCIN
RFILO
SLEEP*
SLEEPI*
SPKR
NC
NC
NC
NC
GP18
1 6 .000312MHZ
C7
5 6 PF 5%
VCC
RADVR*
RXA
TXA1
TXA2
RING*
C5 2200
pF
C12
.1
TO DAA
INTERFACE
C18
.1 uF
6
1
EYECLK
EYESYNC
E Y EX
EYEY
13
4
27
46
9
8
7
10
62
61
60
59
58
57
56
55
63
64
66
65
67
68
1
2
3
16
18
19
28
29
15
17
54
40
2
C8
.1
DECOUPLING CAPS
C 1 7 5 6 PF 5%
R12
R E S ET*
C21
.1
1
C8
.1
R13
1 8 0k
C15
.1
2
7
3
C10
C18
1 0 0 0 pF
.1
C11
.1
+
U6
LM386
C16
220
16V
LS1
5
-
4
8
VCC
VCC
161201
C13
10
16V
RC96V24
Figure 3-2. Typical DAA Interface Circuit
RADVR*
C20
.1
R6
536
1%
4
C4
.022uF
LINE
VCC
R 1 0 18
1
2
3
D4
1 N 749A
RV1
V150LA2
TTC143
J4
T E L CO4/6
TOP
RELAY
VCC
D5
1 N 749A
TXA1
8
1
2
3
4
5
6
7
K1
T1
RXA
R1
R3
100K
TXA2
5
2
RING*
4
3
6
1
4 N 35
18
1W
C3
.47
10%
250V
U1
D3
1 N 4148
R2
7.5K
1W
D1
1 N 970B
C2
.001
10%
1KV
C1
.001
10%
1KV
8
1
2
3
4
5
6
7
J3
T E L CO4/6
TOP
D2
1 N 970B
D96V24DSA
3-11
RC96V24DP
3.0 Software Interface
Single Device Data/Modem Data Pump
3.7 Modem Interface Circuit
3-12
D96V24DSA
Because
Communication
Matters™
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D96V24DSA