Quad, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V ADC AD9219 Data Sheet 4 ADCs integrated into 1 package 94 mW ADC power per channel at 65 MSPS SNR = 60 dB (to Nyquist) ENOB = 9.7 bits SFDR = 78 dBc (to Nyquist) Excellent linearity DNL = ±0.2 LSB (typical) INL = ±0.3 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 315 MHz full-power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full-chip and individual-channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment GENERAL DESCRIPTION The AD9219 is a quad, 10-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. FUNCTIONAL BLOCK DIAGRAM AVDD PDWN DRVDD AD9219 10 VIN + A VIN – A PIPELINE ADC VIN + B VIN – B PIPELINE ADC VIN + C VIN – C PIPELINE ADC VIN + D VIN – D PIPELINE ADC SERIAL LVDS D+A D–A SERIAL LVDS D+B D–B SERIAL LVDS D+C D–C SERIAL LVDS D+D D–D 10 10 10 VREF SENSE REFT REFB DRGND + – REF SELECT FCO+ 0.5V SERIAL PORT INTERFACE DATA RATE MULTIPLIER FCO– DCO+ DCO– RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK– 05726-001 FEATURES Figure 1. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual-channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features designed to maximize flexibility and minimize system cost, such as programmable clock and data alignment and programmable digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI). The AD9219 is available in an RoHS compliant, 48-lead LFCSP. It is specified over the industrial temperature range of −40°C to +85°C. PRODUCT HIGHLIGHTS 1. 2. 3. 4. 5. Small Footprint. Four ADCs are contained in a small, spacesaving package. Low power of 94 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9228 (12-bit), and AD9259 (14-bit). Rev. E Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved. AD9219 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 Analog Input Considerations ................................................... 20 Applications ....................................................................................... 1 Clock Input Considerations ...................................................... 23 General Description ......................................................................... 1 Serial Port Interface (SPI) .............................................................. 31 Functional Block Diagram .............................................................. 1 Hardware Interface..................................................................... 31 Product Highlights ........................................................................... 1 Memory Map .................................................................................. 33 Revision History ............................................................................... 2 Reading the Memory Map Table .............................................. 33 Specifications..................................................................................... 4 Reserved Locations .................................................................... 33 AC Specifications.......................................................................... 5 Default Values ............................................................................. 33 Digital Specifications ................................................................... 6 Logic Levels ................................................................................. 33 Switching Specifications .............................................................. 7 Evaluation Board ............................................................................ 37 Timing Diagrams .............................................................................. 8 Power Supplies ............................................................................ 37 Absolute Maximum Ratings.......................................................... 10 Input Signals................................................................................ 37 Thermal Impedance ................................................................... 10 Output Signals ............................................................................ 37 ESD Caution ................................................................................ 10 Default Operation and Jumper Selection Settings ................. 38 Pin Configuration and Function Descriptions ........................... 11 Alternative Analog Input Drive Configuration...................... 39 Equivalent Circuits ......................................................................... 13 Outline Dimensions ....................................................................... 53 Typical Performance Characteristics ........................................... 15 Ordering Guide .......................................................................... 53 Theory of Operation ...................................................................... 20 REVISION HISTORY 12/11—Rev. D to Rev. E Added Exposed Pad Notation to Figure 5 ................................... 11 Changes to Output Signals Section and Figure 71 ..................... 37 Change to Default Operation and Jumper Selection Settings Section .............................................................................................. 38 Change to Figure 74 ....................................................................... 41 Changed LFCSP_WQ to LFCSP_VQ Throughout .................... 53 Added Endnote 2 in Ordering Guide .......................................... 53 5/10—Rev. C to Rev. D Updated Outline Dimensions ....................................................... 52 Changes to Ordering Guide .......................................................... 52 4/10—Rev. B to Rev. C Changes to Table 16 ........................................................................ 33 Updated Outline Dimensions ....................................................... 52 7/07—Rev. A to Rev. B Changes to Figure 2 and Figure 4 ................................................... 7 Changes to Table 17 ........................................................................ 50 5/07—Rev. 0 to Rev. A Changes to Features ..........................................................................1 Changes to Logic Output (SDIO/ODM) Section ..........................5 Added Endnote 3 to Table 3 .............................................................5 Changes to Pipeline Latency ............................................................6 Changes to Figure 2 to Figure 4 .......................................................7 Changes to Figure 10...................................................................... 12 Changes to Figure 15, Figure 23 to Figure 26 Captions ............ 14 Changes to Figure 16, Figure 37, Figure 39, and Figure 40....... 14 Added Figure 46 and Figure 47 .................................................... 20 Change to Figure 50 ....................................................................... 21 Changes to Figure 51...................................................................... 21 Changes to Clock Duty Cycle Considerations Section ............. 22 Changes to Power Dissipation and Power-Down Mode Section .......................................................... 23 Changes to Figure 58...................................................................... 23 Changes to Figure 61 to Figure 63 Captions ............................... 25 Change to Table 8 ........................................................................... 25 Changes to Digital Outputs and Timing Section ....................... 26 Changes to Table 9 Endnote.......................................................... 26 Added Table 10 ............................................................................... 27 Deleted Figure 62 and Figure 63 .................................................. 27 Rev. E | Page 2 of 56 Data Sheet AD9219 Changes to RBIAS Pin Section ......................................................28 Changes to Figure 67 ......................................................................29 Changes to Hardware Interface Section .......................................30 Added Figure 68 ..............................................................................31 Changes to Table 15 ........................................................................31 Changes to Reading the Memory Map Table Section ................32 Changes to Output Signals Section ...............................................36 Changes to Figure 71 ......................................................................36 Changes to Default Operation and Jumper Selection Settings Section ................................................ 37 Changes to Alternative Analog Input Drive Configuration Section .............................................................................................. 38 Changes to Figure 74 ...................................................................... 40 Changes to Table 17 ........................................................................ 48 Changes to Ordering Guide ........................................................... 52 4/06—Revision 0: Initial Version Rev. E | Page 3 of 56 AD9219 Data Sheet SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 1. Parameter1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage (1 V Mode) REFERENCE Output Voltage Error (VREF = 1 V) Load Regulation at 1.0 mA (VREF = 1 V) Input Resistance ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation2 CROSSTALK CROSSTALK (Overrange Condition)3 Temperature Min 10 Full Full Full Full Full Full Full AD9219-40 Typ Max Guaranteed ±1 ±2 ±0.4 ±0.3 ±0.1 ±0.15 Full Full Full ±2 ±17 ±21 Full Full Full ±2 3 6 Full Full Full Full 2 AVDD/2 7 315 Full Full Full Full Full Full Full Full Full 1.7 1.7 1 1.8 1.8 130 30 295 2 72 −100 −100 Min 10 AD9219-65 Typ Max Guaranteed ±1 ±2 ±2 ±0.3 ±0.15 ±0.3 ±8 ±8 ±1.2 ±0.7 ±0.4 ±0.4 ±8 ±8 ±3.5 ±0.7 ±0.4 ±0.75 ±2 ±17 ±21 ±30 ±2 3 6 1.7 1.7 1.8 1.8 177 33 378 2 72 −100 −100 ±30 Rev. E | Page 4 of 56 mV mV kΩ V p-p V pF MHz 1.9 1.9 190 37 408 5.8 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed. Can be controlled via the SPI. 3 Overrange condition is specific with 6 dB of the full-scale input range. 2 mV mV % FS % FS LSB LSB ppm/°C ppm/°C ppm/°C 2 AVDD/2 7 315 1.9 1.9 142 32 313 5.8 Unit Bits V V mA mA mW mW mW dB dB Data Sheet AD9219 AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 2. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST HARMONIC (Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz WORST OTHER (Excluding Second or Third) fIN = 2.4 MHz fIN = 19.7 MHz fIN = 35 MHz fIN = 70 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)— AIN1 and AIN2 = −7.0 dBFS fIN1 = 15 MHz, fIN2 = 16 MHz fIN1 = 70 MHz, fIN2 = 71 MHz 1 Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Min 60.0 59.8 9.67 71 AD9219-40 Typ Max 61.2 60.5 61.0 60.9 59.0 61.1 60.3 60.9 60.8 58.8 9.87 9.76 9.84 9.82 9.51 84 82 80 79 Full Full Full Full −84 −82 −80 −79 Full Full Full Full −90 −90 −90 −88 25°C 25°C 81.5 79.5 Min 68 −71 −77 AD9219-65 Typ Max 60.2 60.2 60.2 60.1 dB dB dB dB 60.1 60.1 60.0 59.8 dB dB dB dB 9.71 9.71 9.71 9.69 Bits Bits Bits Bits 78 78 77 72 dBc dBc dBc dBc −80 −80 −77 −72 dBc dBc dBc dBc −78 −78 −80 −80 −68 −70 78.1 74.5 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed. Rev. E | Page 5 of 56 Unit dBc dBc dBc dBc dBc dBc AD9219 Data Sheet DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 3. Parameter1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage2 Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM)3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 μA) DIGITAL OUTPUTS (D + x, D − x), (ANSI-644) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D + x, D − x), (Low Power, Reduced Signal Option) Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) Temperature Min Full Full 25°C 25°C 250 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 AD9219-40 Typ Max Min CMOS/LVDS/LVPECL 1.2 30 0.5 3.6 0.3 1.2 70 0.5 DRVDD + 0.3 0.3 1.2 0 1.79 454 1.375 Offset binary 250 1.30 Offset binary 1 V V kΩ pF DRVDD + 0.3 0.3 V V kΩ pF 1.79 0.05 150 1.10 3.6 0.3 30 2 0.05 454 1.375 Offset binary Rev. E | Page 6 of 56 mV V LVDS 150 1.10 250 1.30 Offset binary See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed. This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO pins sharing the same connection. 2 V V LVDS 247 1.125 LVDS Full Full V V kΩ pF 70 0.5 30 2 247 1.125 3.6 0.3 30 0.5 LVDS Full Full mV p-p V kΩ pF 1.2 20 1.5 3.6 0.3 Unit CMOS/LVDS/LVPECL 250 1.2 20 1.5 Full Full AD9219-65 Typ Max mV V Data Sheet AD9219 SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted. Table 4. AD9219-40 Parameter1, 2 CLOCK3 Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) Temp Min Full Full Full Full 40 OUTPUT PARAMETERS3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD)4 Full Full Full Full Full 2.0 Typ AD9219-65 Max Min Typ Max 65 10 10 12.5 12.5 7.7 7.7 DCO to Data Delay (tDATA)4 Full (tSAMPLE/20) − 300 (tSAMPLE/20) + 300 (tSAMPLE/20) − 300 2.5 300 300 2.5 tFCO + (tSAMPLE/20) (tSAMPLE/20) 4 Full (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 (tSAMPLE/20) − 300 (tSAMPLE/20) (tSAMPLE/20) + 300 ps Full ±50 ±150 ±50 ±150 ps 25°C 25°C Full 600 375 8 600 375 8 ns μs CLK cycles 25°C 25°C 25°C 500 <1 1 500 <1 2 ps ps rms CLK cycles DCO to FCO Delay (tFRAME) Data to Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time 2.0 3.5 2.0 1 3.5 MSPS MSPS ns ns 2.5 300 300 2.5 tFCO + (tSAMPLE/20) (tSAMPLE/20) 2.0 3.5 Unit 3.5 (tSAMPLE/20) + 300 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details of how these tests were completed. Measured on standard FR-4 material. 3 Can be adjusted via the SPI. 4 tSAMPLE/20 is based on the number of bits divided by 2 because the delays are based on half duty cycles. 2 Rev. E | Page 7 of 56 ns ps ps ns ns ps AD9219 Data Sheet TIMING DIAGRAMS N–1 VIN ± x tA N tEL tEH CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA D–x MSB N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D4 N–9 D3 N–9 D2 N–9 D1 N–9 D0 N–9 MSB N–8 D8 N–8 D7 N–8 D6 N–8 D5 N–8 05726-040 D+x Figure 2. 10-Bit Data Serial Stream, MSB First (Default) N–1 VIN ± x tA N tEH CLK– tEL CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA MSB N–9 D10 N–9 D9 N–9 D8 N–9 D7 N–9 D6 N–9 D5 N–9 D+x Figure 3. 12-Bit Data Serial Stream, MSB First Rev. E | Page 8 of 56 D4 N–9 D3 N–9 D2 N–9 D1 N–9 D0 N–9 MSB N–8 D10 N–8 05726-039 D–x Data Sheet AD9219 N–1 VIN ± x tA N tEL tEH CLK– CLK+ tCPD DCO– DCO+ tFRAME tFCO FCO– FCO+ tPD tDATA D–x D0 N–9 D1 N–9 D2 N–9 D3 N–9 D4 N–9 D5 N–9 D6 N–9 D7 N–9 D8 N–9 LSB N–8 D0 N–8 D1 N–8 D2 N–8 05726-041 LSB N–9 D+x Figure 4. 10-Bit Stream, LSB First Rev. E | Page 9 of 56 AD9219 Data Sheet ABSOLUTE MAXIMUM RATINGS Table 5. Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D + x, D − x, DCO+, DCO−, FCO+, FCO−) CLK+, CLK− VIN + x, VIN − x SDIO/ODM PDWN, SCLK/DTP, CSB REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) With Respect To Rating AGND DRGND DRGND DRVDD DRGND −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +0.3 V −2.0 V to +2.0 V −0.3 V to +2.0 V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. THERMAL IMPEDANCE Table 6. AGND AGND AGND AGND AGND AGND −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +3.9 V −0.3 V to +2.0 V −0.3 V to +2.0 V −40°C to +85°C Air Flow Velocity (m/sec) 0.0 1.0 2.5 1 θJA1 24 21 19 θJB θJC 12.6 1.2 Unit °C/W °C/W °C/W θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad soldered to PCB. ESD CAUTION 150°C 300°C −65°C to +150°C Rev. E | Page 10 of 56 Data Sheet AD9219 VIN + C AVDD AVDD REFT REFB VREF SENSE RBIAS AVDD VIN + B VIN – B 46 45 44 43 42 41 40 39 38 37 PIN 1 INDICATOR AVDD 1 36 AVDD AVDD 2 35 AVDD VIN – D 3 34 VIN – A 33 VIN + A 5 32 AVDD AVDD 6 31 PDWN 30 CSB 8 29 SDIO/ODM AVDD 9 28 SCLK/DTP AVDD 10 27 AVDD 11 26 DRGND DRVDD 12 25 DRVDD EXPOSED PADDLE, PIN 0 (BOTTOM OF PACKAGE) VIN + D 4 AD9219 DCO+ 24 23 DCO– 21 FCO– FCO+ 22 D + A 20 17 D–B D + C 16 15 D–C D–D 13 DRGND D + D 14 CLK+ D – A 19 TOP VIEW CLK– 7 D + B 18 AVDD NOTES 1. THE EXPOSED PAD MUST BE CONNECTED TO ANALOG GROUND. Figure 5. 48-Lead LFCSP Pin Configuration, Top View Table 7. Pin Function Descriptions Pin No. 0 1, 2, 5, 6, 9, 10, 27, 32, 35, 36, 39, 45, 46 11, 26 12, 25 3 4 7 8 13 14 15 16 17 18 19 20 21 22 23 24 28 29 Mnemonic AGND AVDD Description Analog Ground (Exposed Paddle) 1.8 V Analog Supply DRGND DRVDD VIN − D VIN + D CLK− CLK+ D−D D+D D−C D+C D−B D+B D−A D+A FCO− FCO+ DCO− DCO+ SCLK/DTP SDIO/ODM Digital Output Driver Ground 1.8 V Digital Output Driver Supply ADC D Analog Input Complement ADC D Analog Input True Input Clock Complement Input Clock True ADC D Digital Output Complement ADC D Digital Output True ADC C Digital Output Complement ADC C Digital Output True ADC B Digital Output Complement ADC B Digital Output True ADC A Digital Output Complement ADC A Digital Output True Frame Clock Output Complement Frame Clock Output True Data Clock Output Complement Data Clock Output True Serial Clock/Digital Test Pattern Serial Data IO/Output Driver Mode Rev. E | Page 11 of 56 05726-003 VIN – C 48 47 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9219 Pin No. 30 31 33 34 37 38 40 41 42 43 44 47 48 Data Sheet Mnemonic CSB PDWN VIN + A VIN − A VIN − B VIN + B RBIAS SENSE VREF REFB REFT VIN + C VIN − C Description Chip Select Bar Power-Down ADC A Analog Input True ADC A Analog Input Complement ADC B Analog Input Complement ADC B Analog Input True External resistor sets the internal ADC core bias current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) ADC C Analog Input True ADC C Analog Input Complement Rev. E | Page 12 of 56 Data Sheet AD9219 EQUIVALENT CIRCUITS DRVDD V V D– VIN ± x D+ DRGND Figure 6. Equivalent Analog Input Circuit CLK+ V 05726-005 05726-030 V Figure 9. Equivalent Digital Output Circuit 10Ω 10kΩ 1.25V 10kΩ SCLK/DTP AND PDWN 10Ω 1kΩ 30kΩ 05726-033 05726-032 CLK– Figure 7. Equivalent Clock Input Circuit Figure 10. Equivalent SCLK/DTP and PDWN Input Circuit RBIAS 350Ω 05726-031 30kΩ 05726-035 SDIO/ODM 100Ω Figure 8. Equivalent SDIO/ODM Input Circuit Figure 11. Equivalent RBIAS Circuit Rev. E | Page 13 of 56 AD9219 Data Sheet AVDD 70kΩ CSB 1kΩ 6kΩ Figure 12. Equivalent CSB Input Circuit Figure 14. Equivalent VREF Circuit 1kΩ 05726-036 SENSE 05726-037 05726-034 VREF Figure 13. Equivalent SENSE Circuit Rev. E | Page 14 of 56 Data Sheet AD9219 TYPICAL PERFORMANCE CHARACTERISTICS 0 0 AIN = –0.5dBFS SNR = 61.22dB ENOB = 9.88 BITS SFDR = 85.20dBc –40 –60 –80 –100 –40 –60 –80 0 2 4 6 8 10 12 14 16 18 –120 20 05726-058 –100 05726-056 –120 AIN = –0.5dBFS SNR = 59.81dB ENOB = 9.64 BITS SFDR = 70.02dBc –20 AMPLITUDE (dBFS) AMPLITUDE (dBFS) –20 0 5 10 FREQUENCY (MHz) Figure 15. Single-Tone 32k FFT with fIN = 2.4 MHz, fSAMPLE = 40 MSPS AMPLITUDE (dBFS) –40 –60 –80 –40 –60 –80 05726-076 –100 0 2 4 6 8 10 12 14 16 18 –120 20 05726-059 AMPLITUDE (dBFS) 30 AIN = –0.5dBFS SNR = 59.68dB ENOB = 9.62 BITS SFDR = 70.86dBc –20 –100 0 5 10 FREQUENCY (MHz) 15 20 25 30 FREQUENCY (MHz) Figure 19. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 40 MSPS 0 0 AIN = –0.5dBFS SNR = 59.93dB ENOB = 9.66 BITS SFDR = 77.58dBc AIN = –0.5dBFS SNR = 59.93dB ENOB = 9.66 BITS SFDR = 63.51dBc –20 AMPLITUDE (dBFS) –20 –40 –60 –80 –40 –60 –80 –100 05726-057 –100 0 5 10 15 20 25 30 –120 05726-053 AMPLITUDE (dBFS) 25 0 AIN = –0.5dBFS SNR = 59.87dB ENOB = 9.65 BITS SFDR = 81.68dBc –20 –120 20 Figure 18. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS 0 –120 15 FREQUENCY (MHz) 0 5 10 15 20 25 30 FREQUENCY (MHz) FREQUENCY (MHz) Figure 20. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 65 MSPS Figure 17. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 65 MSPS Rev. E | Page 15 of 56 AD9219 Data Sheet 90 0 AIN = –0.5dBFS SNR = 56.72dB ENOB = 9.13 BITS SFDR = 66.41dBc –20 85 2V p-p, SFDR –40 SNR/SFDR (dB) AMPLITUDE (dBFS) 80 –60 –80 75 70 65 60 2V p-p, SNR –100 0 5 10 15 20 25 50 10 30 05726-063 05726-054 –120 55 15 Figure 21. Single-Tone 32k FFT with fIN = 190 MHz, fSAMPLE = 65 MSPS 25 30 35 40 Figure 24. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 40 MSPS 90 0 AIN = –0.5dBFS SNR = 58.57dB ENOB = 9.44 BITS SFDR = 57.95dBc –20 85 2V p-p, SFDR 80 –40 SNR/SFDR (dB) AMPLITUDE (dBFS) 20 ENCODE (MSPS) FREQUENCY (MHz) –60 75 70 65 –80 60 2V p-p, SNR –100 0 5 10 15 20 25 50 10 30 05726-061 05726-055 –120 55 20 30 40 50 60 ENCODE (MSPS) FREQUENCY (MHz) Figure 25. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 65 MSPS Figure 22. Single-Tone 32k FFT with fIN = 250 MHz, fSAMPLE = 65 MSPS 90 90 85 85 2V p-p, SFDR 80 SNR/SFDR (dB) 75 70 65 60 15 20 25 70 65 30 35 40 2V p-p, SNR 55 50 10 05726-065 55 50 10 2V p-p, SFDR 75 60 2V p-p, SNR 05726-060 SNR/SFDR (dB) 80 20 30 40 50 60 ENCODE (MSPS) ENCODE (MSPS) Figure 26. SNR/SFDR vs. Encode, fIN = 35 MHz, fSAMPLE = 65 MSPS Figure 23. SNR/SFDR vs. Encode, fIN = 10.3 MHz, fSAMPLE = 40 MSPS Rev. E | Page 16 of 56 Data Sheet AD9219 100 100 2V p-p, SFDR 60 50 2V p-p, SNR 40 70dB REFERENCE 30 2V p-p, SFDR 60 50 2V p-p, SNR 40 70dB REFERENCE 30 20 05726-062 20 10 0 –60 fIN = 35MHz fSAMPLE = 65MSPS 80 70 70 SNR/SFDR (dB) 90 fIN = 10.3MHz fSAMPLE = 40MSPS –50 –40 –30 –20 –10 05726-067 80 SNR/SFDR (dB) 90 10 0 –60 0 –50 Figure 27. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 40 MSPS fIN = 35MHz fSAMPLE = 40MSPS 2V p-p, SFDR 50 2V p-p, SNR 40 70dB REFERENCE 30 20 –40 –60 –80 05726-066 –100 10 –50 –40 –30 –20 –10 –120 0 0 2 4 6 Figure 28. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 40 MSPS 0 fIN = 10.3MHz fSAMPLE = 65MSPS AMPLITUDE (dBFS) 50 2V p-p, SNR 70dB REFERENCE 20 16 18 20 –40 –60 –80 05726-064 –100 10 0 –60 14 –50 –40 –30 –20 –10 0 –120 05726-049 SNR/SFDR (dB) 2V p-p, SFDR 60 30 12 AIN1 AND AIN2 = –7dBFS SFDR = 79.13dBc IMD2 = 79.56dBc IMD3 = 79.66dBc –20 40 10 Figure 31. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 40 MSPS 100 70 8 FREQUENCY (MHz) ANALOG INPUT LEVEL (dBFS) 80 0 AIN1 AND AIN2 = –7dBFS SFDR = 82.54dBc IMD2 = 88.33dBc IMD3 = 81.77dBc –20 60 90 –10 05726-048 SNR/SFDR (dB) 70 0 –60 –20 0 AMPLITUDE (dBFS) 80 –30 Figure 30. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 65 MSPS 100 90 –40 ANALOG INPUT LEVEL (dBFS) ANALOG INPUT LEVEL (dBFS) 0 2 4 6 8 10 12 14 16 18 20 FREQUENCY (MHz) ANALOG INPUT LEVEL (dBFS) Figure 29. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 65 MSPS Rev. E | Page 17 of 56 Figure 32. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, fSAMPLE = 40 MSPS AD9219 Data Sheet 0 90 AIN1 AND AIN2 = –7dBFS SFDR = 78.53dBc IMD2 = 78.61dBc IMD3 = 78.17dBc –20 85 2V p-p, SFDR SINAD/SFDR (dB) AMPLITUDE (dBFS) 80 –40 –60 –80 75 70 65 2V p-p, SINAD 60 –100 0 5 10 15 20 25 50 –40 30 05726-069 05726-050 –120 55 –20 FREQUENCY (MHz) 40 60 80 Figure 36. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 65 MSPS 1.0 0 AIN1 AND AIN2 = –7dBFS SFDR = 74.90dBc IMD2 = 83.52dBc IMD3 = 74.56dBc –20 0.8 0.6 0.4 –40 INL (LSB) –60 –80 0.2 0 –0.2 –0.4 –0.6 05726-052 –100 0 5 10 15 20 25 05726-070 AMPLITUDE (dBFS) 20 TEMPERATURE (°C) Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz, fSAMPLE = 65 MSPS –120 0 –0.8 –1.0 30 0 200 400 FREQUENCY (MHz) 600 800 1000 CODE Figure 34. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz, fSAMPLE = 65 MSPS Figure 37. INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS 0.5 80 0.4 2V p-p, SFDR 0.3 0.2 70 DNL (LSB) 65 60 0 –0.1 –0.2 2V p-p, SNR –0.3 05726-068 55 50 0.1 1 10 100 1000 05726-071 SNR/SFDR (dB) 75 –0.4 –0.5 0 200 400 600 800 CODES ANALOG INPUT FREQUENCY (MHz) Figure 38. DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS Figure 35. SNR/SFDR vs. Analog Input Frequency, fSAMPLE = 65 MSPS Rev. E | Page 18 of 56 1000 Data Sheet AD9219 0 –45.5 –20 AMPLITUDE (dBFS) –45.0 –46.5 –47.0 –47.5 –40 –60 –80 –48.0 10 05726-082 –100 15 20 25 30 35 40 45 –120 50 05726-051 CMRR (dB) –46.0 NPR = 51.72dB NOTCH = 18.0MHz NOTCH WIDTH = 3.0MHz 0 5 10 1.2 25 30 0 0 LSB rms –1 FUNDAMENTAL LEVEL (dB) 1.0 0.8 0.6 0.4 –2 –3dB CUTOFF = 315MHz –3 –4 –5 –6 –7 N–3 N–2 N–1 N N+1 N+2 N+3 CODE 05726-084 –8 0.2 05726-080 NUMBER OF HITS (Millions) 20 Figure 41. Noise Power Ratio (NPR), fSAMPLE = 65 MSPS Figure 39. CMRR vs. Frequency, fSAMPLE = 65 MSPS 0 15 FREQUENCY (MHz) FREQUENCY (MHz) –9 –10 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) Figure 40. Input-Referred Noise Histogram, fSAMPLE = 65 MSPS Figure 42. Full-Power Bandwidth vs. Frequency, fSAMPLE = 65 MSPS Rev. E | Page 19 of 56 AD9219 Data Sheet THEORY OF OPERATION The AD9219 architecture consists of a pipelined ADC divided into three sections: a 4-bit first stage followed by eight 1.5-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers. The data is then serialized and aligned to the frame and data clocks. ANALOG INPUT CONSIDERATIONS The analog input to the AD9219 is a differential switchedcapacitor circuit designed for processing differential input signals. This circuit can support a wide common-mode range while maintaining excellent performance. By using an input common-mode voltage of midsupply, users can minimize signal-dependent errors and achieve optimum performance. The clock signal alternately switches the input circuit between sample mode and hold mode (see Figure 43). When the input circuit is switched to sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. A small resistor in series with each input can help reduce the peak transient current injected from the output stage of the driving source. In addition, low-Q inductors or ferrite beads can be placed on each leg of the input to reduce high differential capacitance at the analog inputs and therefore achieve the maximum bandwidth of the ADC. Such use of lowQ inductors or ferrite beads is required when driving the converter front end at high IF frequencies. Either a shunt capacitor or two single-ended capacitors can be placed on the inputs to provide a matching passive network. This ultimately creates a low-pass filter at the input to limit unwanted broadband noise. See the AN-742 Application Note, the AN-827 Application Note, and the Analog Dialogue article “Transformer-Coupled Front-End for Wideband A/D Converters” (Volume 39, April 2005) for more information at www.analog.com. In general, the precise values depend on the application. The analog inputs of the AD9219 are not internally dc-biased. Therefore, in ac-coupled applications, the user must provide this bias externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function over a wider range with reasonable performance, as shown in Figure 44 to Figure 47. H CPAR H VIN + x CSAMPLE S S S S CSAMPLE VIN – x H 05726-006 H CPAR Figure 43. Switched-Capacitor Input Circuit Rev. E | Page 20 of 56 Data Sheet AD9219 90 80 75 85 SFDR (dBc) SFDR (dBc) 80 60 SNR (dB) 55 75 70 65 SNR (dB) 50 60 45 55 40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 50 0.2 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 44. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz, fSAMPLE = 65 MSPS Figure 46. SNR/SFDR vs. Common-Mode Voltage, fIN = 2.4 MHz, fSAMPLE = 40 MSPS 80 90 75 SFDR (dBc) 85 70 80 SNR/SFDR (dB) 65 60 SNR (dB) 55 SFDR (dBc) 75 70 65 SNR (dB) 50 60 40 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ANALOG INPUT COMMON-MODE VOLTAGE (V) 55 50 0.2 05726-101 45 05726-073 SNR/SFDR (dB) 05726-102 SNR/SFDR (dB) 65 05726-072 SNR/SFDR (dB) 70 0.4 0.6 0.8 1.0 1.2 1.4 ANALOG INPUT COMMON-MODE VOLTAGE (V) Figure 45. SNR/SFDR vs. Common-Mode Voltage, fIN = 30 MHz, fSAMPLE = 65 MSPS Figure 47. SNR/SFDR vs. Common-Mode Voltage, fIN = 30 MHz, fSAMPLE = 40 MSPS Rev. E | Page 21 of 56 1.6 AD9219 Data Sheet ADT1-1WT 1:1 Z RATIO For best dynamic performance, the source impedances driving VIN + x and VIN − x should be matched such that commonmode settling errors are symmetrical. These errors are reduced by the common-mode rejection of the ADC. An internal reference buffer creates the positive and negative reference voltages, REFT and REFB, respectively, that define the span of the ADC core. The output common-mode of the reference buffer is set to midsupply, and the REFT and REFB voltages and span are defined as C R 2V p-p 49.9Ω VIN + x ADC AD9219 *CDIFF R AVDD VIN – x C 1kΩ AGND *CDIFF IS OPTIONAL 05726-008 1kΩ 0.1μF Figure 48. Differential Transformer-Coupled Configuration for Baseband Applications REFT = 1/2 (AVDD + VREF) REFB = 1/2 (AVDD − VREF) Span = 2 × (REFT − REFB) = 2 × VREF 2V p-p 16nH ADT1-1WT 0.1μF 1:1 Z RATIO 16nH 33Ω VIN + x 65Ω 499Ω 16nH It can be seen from these equations that the REFT and REFB voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the VREF voltage. 2.2pF ADC AD9219 1kΩ 33Ω VIN – x AVDD Maximum SNR performance is achieved by setting the ADC to the largest span in a differential configuration. In the case of the AD9219, the largest input span available is 2 V p-p. 05726-047 1kΩ 0.1μF 1kΩ Figure 49. Differential Transformer-Coupled Configuration for IF Applications Differential Input Configurations Single-Ended Input Configuration There are several ways to drive the AD9219 either actively or passively; however, optimum performance is achieved by driving the analog input differentially. For example, using the AD8332 differential driver to drive the AD9219 provides excellent performance and a flexible interface to the ADC (see Figure 51) for baseband applications. This configuration is commonly used for medical ultrasound systems. A single-ended input may provide adequate performance in costsensitive applications. In this configuration, SFDR and distortion performance degrade due to the large input common-mode swing. If the application requires a single-ended input configuration, ensure that the source impedances on each input are well matched in order to achieve the best possible performance. A full-scale input of 2 V p-p can be applied to the ADC’s VIN + x pin while the VIN − x pin is terminated. Figure 50 details a typical singleended input configuration. For applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration (see Figure 48 and Figure 49), because the noise performance of most amplifiers is not adequate to achieve the true performance of the AD9219. AVDD C R Regardless of the configuration, the value of the shunt capacitor, C, is dependent on the input frequency and may need to be reduced or removed. 0.1µF 49.9Ω ADC AD9219 *CDIFF AVDD 1kΩ 25Ω 0.1µF VIN + x 1kΩ R VIN – x C 1kΩ 05726-009 2V p-p *CDIFF IS OPTIONAL Figure 50. Single-Ended Input Configuration 0.1μF LOP 0.1μF 120nH VIP AVDD VOH INH AD8332 22pF 0.1μF 680nH LNA VGA + VOL LON 274Ω 187Ω VIN 680nH 10kΩ VIN + x 10kΩ AVDD 33Ω LMD 18nF 68pF 33Ω 1kΩ ADC AD9219 10kΩ VIN – x 10kΩ LPF 05726-007 1V p-p 187Ω 0.1μF Figure 51. Differential Input Configuration Using the AD8332 with Two-Pole, 16 MHz Low-Pass Filter Rev. E | Page 22 of 56 Data Sheet AD9219 Figure 52 shows a preferred method for clocking the AD9219. The low jitter clock source is converted from a single-ended signal to a differential signal using an RF transformer. The back-toback Schottky diodes across the secondary transformer limit clock excursions into the AD9219 to approximately 0.8 V p-p differential. This helps prevent the large voltage swings of the clock from feeding through to other portions of the AD9219, and it preserves the fast rise and fall times of the signal, which are critical to low jitter performance. CLK+ 50Ω CLK 0.1µF CLK 05726-024 0.1µF 0.1µF CLK– 100Ω 0.1µF CLK 50Ω* ADC AD9219 CLK– 240Ω 05726-025 50Ω* 240Ω *50Ω RESISTORS ARE OPTIONAL Figure 53. Differential PECL Sample Clock AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1µF CLK+ 0.1µF CLK+ CLK 0.1µF CLK– LVDS DRIVER 100Ω 0.1µF CLK ADC AD9219 CLK– 50Ω* 05726-026 50Ω* 0.1µF CLK+ ADC AD9219 CLK– Figure 56. Single-Ended 3.3 V CMOS Sample Clock CLK+ PECL DRIVER OPTIONAL 100Ω *50Ω RESISTOR IS OPTIONAL 0.1µF CLK CMOS DRIVER 0.1µF Another option is to ac-couple a differential PECL signal to the sample clock input pins as shown in Figure 53. The AD9510/ AD9511/AD9512/AD9513/AD9514/AD9515 family of clock drivers offers excellent jitter performance. 0.1µF AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 CLK 50Ω* Figure 52. Transformer-Coupled Differential Clock CLK+ 39kΩ Figure 55. Single-Ended 1.8 V CMOS Sample Clock CLK– AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 ADC AD9219 *50Ω RESISTOR IS OPTIONAL ADC AD9219 SCHOTTKY DIODES: HSM2812 CLK+ CLK– 0.1µF CLK+ 0.1µF OPTIONAL 100Ω 0.1µF CLK+ 100Ω 0.1µF CMOS DRIVER 0.1µF ADT1-1WT, 1:1Z 0.1µF XFMR CLK+ CLK 50Ω* Mini-Circuits® 0.1µF AD9510/AD9511/ AD9512/AD9513/ AD9514/AD9515 0.1µF 05726-027 For optimum performance, the AD9219 sample clock inputs (CLK+ and CLK−) should be clocked with a differential signal. This signal is typically ac-coupled to the CLK+ and CLK− pins via a transformer or capacitors. These pins are biased internally and require no additional biasing. CLK− pin should be bypassed to ground with a 0.1 μF capacitor in parallel with a 39 kΩ resistor (see Figure 55). Although the CLK+ input circuit supply is AVDD (1.8 V), this input is designed to withstand input voltages of up to 3.3 V and therefore offers several selections for the drive logic voltage. 05726-028 CLOCK INPUT CONSIDERATIONS *50Ω RESISTORS ARE OPTIONAL Figure 54. Differential LVDS Sample Clock In some applications, it is acceptable to drive the sample clock inputs with a single-ended CMOS signal. In such applications, CLK+ should be driven directly from a CMOS gate, and the Clock Duty Cycle Considerations Typical high speed ADCs use both clock edges to generate a variety of internal timing signals. As a result, these ADCs may be sensitive to the clock duty cycle. Commonly, a 5% tolerance is required on the clock duty cycle to maintain dynamic performance characteristics. The AD9219 contains a duty cycle stabilizer (DCS) that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. This allows a wide range of clock input duty cycles without affecting the performance of the AD9219. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. However, some applications may require the DCS function to be off. If so, keep in mind that the dynamic range performance can be affected when operated in this mode. See the Memory Map section for more details on using this feature. Jitter in the rising edge of the input is an important concern, and it is not reduced by the internal stabilization circuit. The duty cycle control loop does not function for clock rates of less than 20 MHz nominal. The loop has a time constant associated with it that must be considered in applications where the clock rate can change dynamically. This requires a wait time of 1.5 μs to 5 μs after a dynamic clock frequency increase (or decrease) before the DCS loop is relocked to the input signal. During the period that the loop is not locked, the DCS loop is bypassed and the internal device timing is dependent on the duty cycle of the input clock signal. In such applications, it may be appropriate to disable the duty cycle stabilizer. In all other applications, enabling the DCS circuit is recommended to maximize ac performance. Rev. E | Page 23 of 56 AD9219 Data Sheet Clock Jitter Considerations Power Dissipation and Power-Down Mode High speed, high resolution ADCs are sensitive to the quality of the clock input. The degradation in SNR at a given input frequency (fA) due only to aperture jitter (tJ) can be calculated by As shown in Figure 58 and Figure 59, the power dissipated by the AD9219 is proportional to its sample rate. The digital power dissipation does not vary significantly because it is determined primarily by the DRVDD supply and bias current of the LVDS output drivers. SNR Degradation = 20 × log 10(1/2 × π × fA × tJ) In this equation, the rms aperture jitter represents the root mean square of all jitter sources, including the clock input, analog input signal, and ADC aperture jitter. IF undersampling applications are particularly sensitive to jitter (see Figure 57). 360 140 AVDD CURRENT 340 120 320 100 10 15 20 25 30 ENCODE (MSPS) 35 40 390 AVDD CURRENT 370 330 100 310 80 70 60 10 BITS 10 100 ANALOG INPUT FREQUENCY (MHz) 290 DRVDD CURRENT 40 0.125 ps 0.25 ps 0.5 ps 1.0 ps 2.0 ps 270 20 0 1000 POWER (mW) 12 BITS 350 TOTAL POWER 120 10 20 30 40 ENCODE (MSPS) 50 60 250 Figure 59. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS Figure 57. Ideal SNR vs. Input Frequency and Jitter Rev. E | Page 24 of 56 05726-078 80 CURRENT (mA) 140 14 BITS 180 200 160 90 05726-074 0 200 Figure 58. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS 05726-038 SNR (dB) DRVDD CURRENT 180 16 BITS 30 1 240 220 RMS CLOCK JITTER REQUIREMENT 100 40 260 20 110 50 280 60 120 60 TOTAL POWER POWER (mW) 80 40 Refer to the AN-501 Application Note and to the AN-756 Application Note for more in-depth information about jitter performance as it relates to ADCs at www.analog.com. 130 300 CURRENT (mA) The clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9219. Power supplies for clock drivers should be separated from the ADC output driver supplies to avoid modulating the clock signal with digital noise. Low jitter, crystal-controlled oscillators are the best clock sources. If the clock is generated from another type of source (by gating, dividing, or another method), it should be retimed by the original clock during the last step. Data Sheet AD9219 By asserting the PDWN pin high, the AD9219 is placed into power-down mode. In this state, the ADC typically dissipates 3 mW. During power-down, the LVDS output drivers are placed into a high impedance state. If any of the SPI features are changed before the power-down feature is enabled, the chip continues to function after PDWN is pulled low without requiring a reset. The AD9219 returns to normal operating mode when the PDWN pin is pulled low. This pin is both 1.8 V and 3.3 V tolerant. placed as close to the receiver as possible. If there is no far-end receiver termination or there is poor differential trace routing, timing errors may result. To avoid such timing errors, it is recommended that the trace length be less than 24 inches and that the differential output traces be close together and at equal lengths. An example of the FCO and data stream with proper trace length and position is shown in Figure 60. There are several other power-down options available when using the SPI. The user can individually power down each channel or put the entire device into standby mode. The latter option allows the user to keep the internal PLL powered when fast wake-up times (~600 ns) are required. See the Memory Map section for more details on using these features. Digital Outputs and Timing The AD9219 differential outputs conform to the ANSI-644 LVDS standard on default power-up. This can be changed to a low power, reduced signal option (similar to the IEEE 1596.3 standard) via the SDIO/ODM pin or SPI. The LVDS standard can further reduce the overall power dissipation of the device by approximately 15 mW. See the SDIO/ODM Pin section or Table 16 in the Memory Map section for more information. The LVDS driver current is derived on-chip and sets the output current at each output equal to a nominal 3.5 mA. A 100 Ω differential termination resistor placed at the LVDS receiver inputs results in a nominal 350 mV swing at the receiver. The AD9219 LVDS outputs facilitate interfacing with LVDS receivers in custom ASICs and FPGAs for superior switching performance in noisy environments. Single point-to-point net topologies are recommended with a 100 Ω termination resistor 05726-077 In power-down mode, low power dissipation is achieved by shutting down the reference, reference buffer, PLL, and biasing networks. The decoupling capacitors on REFT and REFB are discharged when entering power-down mode and must be recharged when returning to normal operation. As a result, the wake-up time is related to the time spent in the power-down mode: shorter cycles result in proportionally shorter wake-up times. With the recommended 0.1 μF and 2.2 μF decoupling capacitors on REFT and REFB, approximately 1 sec is required to fully discharge the reference buffer decoupling capacitors and approximately 375 μs is required to restore full operation. CH1 500mV/DIV = DCO CH2 500mV/DIV = DATA CH3 500mV/DIV = FCO 2.5ns/DIV Figure 60. LVDS Output Timing Example in ANSI-644 Mode (Default) An example of the LVDS output using the ANSI-644 standard (default) data eye and a time interval error (TIE) jitter histogram with trace lengths less than 24 inches on standard FR-4 material is shown in Figure 61. Figure 62 shows an example of trace lengths exceeding 24 inches on standard FR-4 material. Notice that the TIE jitter histogram reflects the decrease of the data eye opening as the edge deviates from the ideal position. It is the user’s responsibility to determine if the waveforms meet the timing budget of the design when the trace lengths exceed 24 inches. Additional SPI options allow the user to further increase the internal termination (increasing the current) of all four outputs in order to drive longer trace lengths (see Figure 63). Even though this produces sharper rise and fall times on the data edges and is less prone to bit errors, the power dissipation of the DRVDD supply increases when this option is used. In addition, notice in Figure 63 that the histogram is improved compared with that shown in Figure 62. See the Memory Map section for more details. Rev. E | Page 25 of 56 AD9219 Data Sheet EYE: ALL BITS ULS: 10000/15600 EYE: ALL BITS 400 EYE DIAGRAM VOLTAGE (V) EYE DIAGRAM VOLTAGE (V) 500 0 ULS: 9599/15599 200 0 –200 –400 –500 –1ns –0.5ns 0ns 0.5ns –1ns 1ns –0.5ns 0ns 0.5ns 1ns 50 0 –100ps 0ps 100ps 0 –150ps Figure 61. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Less than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only EYE: ALL BITS EYE DIAGRAM VOLTAGE (V) 200 ULS: 9600/15600 –100ps –50ps 0ps 50ps 100ps 150ps Figure 63. Data Eye for LVDS Outputs in ANSI-644 Mode with 100 Ω Internal Termination on and Trace Lengths Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only The format of the output data is offset binary by default. An example of the output coding format can be found in Table 8. To change the output data format to twos complement, see the Memory Map section. 0 Table 8. Digital Output Coding Code 1023 512 511 0 –200 –1ns –0.5ns 0ns 0.5ns 1ns 100 50 0 –150ps (VIN + x) − (VIN − x), Input Span = 2 V p-p (V) +1.00 0.00 −0.001953 −1.00 Digital Output Offset Binary (D9 ... D0) 1111 1111 11 1000 0000 00 0111 1111 11 0000 0000 00 Data from each ADC is serialized and provided on a separate channel. The data rate for each serial stream is equal to 10 bits times the sample clock rate, with a maximum of 650 Mbps (10 bits × 65 MSPS = 650 Mbps). The lowest typical conversion rate is 10 MSPS. However, if lower sample rates are required for a specific application, the PLL can be set up via the SPI to allow encode rates as low as 5 MSPS. See the Memory Map section for details on enabling this feature. –100ps –50ps 0ps 50ps 100ps 150ps 05726-044 TIE JITTER HISTOGRAM (Hits) 50 05726-042 TIE JITTER HISTOGRAM (Hits) 100 05726-043 TIE JITTER HISTOGRAM (Hits) 100 Figure 62. Data Eye for LVDS Outputs in ANSI-644 Mode with Trace Lengths Greater than 24 Inches on Standard FR-4, External 100 Ω Far Termination Only Rev. E | Page 26 of 56 Data Sheet AD9219 Two output clocks are provided to assist in capturing data from the AD9219. The DCO is used to clock the output data and is equal to five times the sample clock (CLK) rate. Data is clocked out of the AD9219 and must be captured on the rising and falling edges of the DCO that supports double data rate (DDR) capturing. The FCO is used to signal the start of a new output byte and is equal to the sample clock rate. See the timing diagram shown in Figure 2 for more information. Table 9. Flexible Output Test Modes Output Test Mode Bit Sequence 0000 0001 Pattern Name Off (default) Midscale short 0010 +Full-scale short 0011 −Full-scale short 0100 Checkerboard 0101 0110 0111 PN sequence long1 PN sequence short1 One-/zero-word toggle 1000 1001 User input 1-/0-bit toggle 1010 1× sync 1011 One bit high 1100 Mixed frequency 1 Digital Output Word 1 N/A 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) N/A N/A 1111 1111 (8-bit) 11 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 11 1111 1111 1111 (14-bit) Register 0x19 to Register 0x1A 1010 1010 (8-bit) 10 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 10 1010 1010 1010 (14-bit) 0000 1111 (8-bit) 00 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 00 0000 0111 1111 (14-bit) 1000 0000 (8-bit) 10 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 10 0000 0000 0000 (14-bit) 1010 0011 (8-bit) 10 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 10 1000 0110 0111 (14-bit) Digital Output Word 2 N/A Same Subject to Data Format Select N/A Yes Same Yes Same Yes 0101 0101 (8-bit) 01 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 01 0101 0101 0101 (14-bit) N/A N/A 0000 0000 (8-bit) 00 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 00 0000 0000 0000 (14-bit) Register 0x1B to Register 0x1C N/A No Yes Yes No No No N/A No N/A No N/A No All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. Rev. E | Page 27 of 56 AD9219 Data Sheet When the SPI is used, the DCO phase can be adjusted in 60° increments relative to the data edge. This enables the user to refine system timing margins if required. The default DCO+ and DCO− timing, as shown in Figure 2, is 90° relative to the output data edge. An 8-, 12-, or 14-bit serial stream can also be initiated from the SPI. This allows the user to implement and test compatibility with lower and higher resolution systems. When changing the resolution to a 12-bit serial stream, the data stream is lengthened. See Figure 3 for the 12-bit example. However, when using the 12-bit option, the data stream stuffs two 0s at the end of the 12-bit serial data. When the SPI is used, all of the data outputs can also be inverted from their nominal state. This is not to be confused with inverting the serial stream to an LSB-first mode. In default mode, as shown in Figure 2, the MSB is first in the data output serial stream. However, this can be inverted so that the LSB is first in the data output serial stream (see Figure 4). There are 12 digital output test pattern options available that can be initiated through the SPI. This is a useful feature when validating receiver capture and timing. Refer to Table 9 for the output bit sequencing options available. Some test patterns have two serial sequential words and can be alternated in various ways, depending on the test pattern chosen. Note that some patterns do not adhere to the data format select option. In addition, custom user-defined test patterns can be assigned in the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode options except PN sequence short and PN sequence long can support 8- to 14-bit word lengths in order to verify data capture to the receiver. The PN sequence short pattern produces a pseudorandom bit sequence that repeats itself every 29 − 1 or 511 bits. A description of the PN sequence and how it is generated can be found in Section 5.1 of the ITU-T 0.150 (05/96) standard. The only difference is that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values). Table 10. PN Sequence Initial Value 0x0df 0x0a6e02 Sequence PN Sequence Short PN Sequence Long First Three Output Samples (MSB First) 0x37e, 0x135, 0x0cc 0x359, 0x07f, 0x170 Consult the Memory Map section for information on how to change these additional digital output timing features through the SPI. SDIO/ODM Pin The SDIO/ODM pin is for use in applications that do not require SPI mode operation. This pin can enable a low power, reduced signal option (similar to the IEEE 1596.3 reduced range link output standard) if it and the CSB pin are tied to AVDD during device power-up. This option should only be used when the digital output trace lengths are less than 2 inches from the LVDS receiver. When this option is used, the FCO, DCO, and outputs function normally, but the LVDS signal swing of all channels is reduced from 350 mV p-p to 200 mV p-p, allowing the user to further reduce the power on the DRVDD supply. For applications where this pin is not used, it should be tied low. In this case, the device pin can be left open, and the 30 kΩ internal pull-down resistor pulls this pin low. This pin is only 1.8 V tolerant. If applications require this pin to be driven from a 3.3 V logic level, insert a 1 kΩ resistor in series with this pin to limit the current. Table 11. Output Driver Mode Pin Settings Selected ODM Normal Operation ODM The PN sequence long pattern produces a pseudorandom bit sequence that repeats itself every 223 − 1 or 8,388,607 bits. A description of the PN sequence and how it is generated can be found in Section 5.6 of the ITU-T 0.150 (05/96) standard. The only differences are that the starting value must be a specific value instead of all 1s (see Table 10 for the initial values) and the AD9219 inverts the bit stream with relation to the ITU standard. Rev. E | Page 28 of 56 ODM Voltage 10 kΩ to AGND AVDD Resulting Output Standard ANSI-644 (default) Low power, reduced signal option Resulting FCO and DCO ANSI-644 (default) Low power, reduced signal option Data Sheet AD9219 SCLK/DTP Pin RBIAS Pin The SCLK/DTP pin is for use in applications that do not require SPI mode operation. This pin can enable a single digital test pattern if it and the CSB pin are held high during device powerup. When SCLK/DTP is tied to AVDD, the ADC channel outputs shift out the following pattern: 1000 0000 0000. The FCO and DCO function normally while all channels shift out the repeatable test pattern. This pattern allows the user to perform timing alignment adjustments among the FCO, DCO, and output data. For normal operation, this pin should be tied to AGND through a 10 kΩ resistor. This pin is both 1.8 V and 3.3 V tolerant. To set the internal core bias current of the ADC, place a resistor (nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The resistor current is derived on-chip and sets the AVDD current of the ADC to a nominal 232 mA at 65 MSPS. Therefore, it is imperative that at least a 1% tolerance on this resistor be used to achieve consistent performance. Table 12. Digital Test Pattern Pin Settings Selected DTP Normal Operation DTP DTP Voltage 10 kΩ to AGND Resulting D + x and D − x Normal operation 1000 0000 0000 Resulting FCO and DCO Normal operation Voltage Reference A stable, accurate 0.5 V voltage reference is built into the AD9219. This is gained up internally by a factor of 2, setting VREF to 1.0 V, which results in a full-scale differential input span of 2 V p-p. The VREF is set internally by default; however, the VREF pin can be driven externally with a 1.0 V reference to improve accuracy. Additional and custom test patterns can also be observed when commanded from the SPI port. Consult the Memory Map section for information about the options available. When applying the decoupling capacitors to the VREF, REFT, and REFB pins, use ceramic low ESR capacitors. These capacitors should be close to the ADC pins and on the same layer of the PCB as the AD9219. The recommended capacitor values and configurations for the AD9219 reference pin are shown in Figure 64. CSB Pin Table 13. Reference Settings AVDD Normal operation The CSB pin should be tied to AVDD for applications that do not require SPI mode operation. By tying CSB high, all SCLK and SDIO information is ignored. This pin is both 1.8 V and 3.3 V tolerant. Selected Mode External Reference Internal, 2 V p-p FSR Rev. E | Page 29 of 56 SENSE Voltage AVDD Resulting VREF (V) N/A AGND to 0.2 V 1.0 Resulting Differential Span (V p-p) 2 × external reference 2.0 AD9219 Data Sheet Internal Reference Operation External Reference Operation A comparator within the AD9219 detects the potential at the SENSE pin and configures the reference. If SENSE is grounded, the reference amplifier switch is connected to the internal resistor divider (see Figure 64), setting VREF to 1 V. The use of an external reference may be necessary to enhance the gain accuracy of the ADC or to improve thermal drift characteristics. Figure 67 shows the typical drift characteristics of the internal reference in 1 V mode. The REFT and REFB pins establish the input span of the ADC core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage of the reference pin for either an internal or an external reference configuration. When the SENSE pin is tied to AVDD, the internal reference is disabled, allowing the use of an external reference. The external reference is loaded with an equivalent 6 kΩ load. An internal reference buffer generates the positive and negative full-scale references, REFT and REFB, for the ADC core. Therefore, the external reference must be limited to a nominal 1.0 V. If the reference of the AD9219 is used to drive multiple converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 66 depicts how the internal reference voltage is affected by loading. 5 0 –5 VIN – x VREF ERROR (%) VIN + x REFT ADC CORE 0.1µF 0.1µF + 2.2µF REFB –10 –15 –20 0.1µF VREF 0.1µF SELECT LOGIC 05726-083 –25 1µF 0.5V –30 SENSE 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 CURRENT LOAD (mA) 05726-010 Figure 66. VREF Accuracy vs. Load 0.02 Figure 64. Internal Reference Configuration 0 –0.02 VIN + x –0.04 VIN – x ADC CORE 0.1µF 0.1µF + VREF ERROR (%) REFT 2.2µF REFB –0.14 0.1µF R2 –0.10 SELECT LOGIC 0.5V 05726-081 + –0.16 –0.18 –40 SENSE R1 –20 0 20 40 TEMPERATURE (°C) Figure 67. Typical VREF Drift 05726-011 1µF –0.08 –0.12 0.1µF VREF –0.06 Figure 65. External Reference Operation Rev. E | Page 30 of 56 60 80 Data Sheet AD9219 SERIAL PORT INTERFACE (SPI) The AD9219 serial port interface allows the user to configure the converter for specific functions or operations through a structured register space provided in the ADC. This may provide the user with additional flexibility and customization, depending on the application. Addresses are accessed via the serial port and can be written to or read from via the port. Memory is organized into bytes that can be further divided into fields, as documented in the Memory Map section. Detailed operational information can be found in the AN-877 Application Note, Interfacing to High Speed ADCs via SPI, at www.analog.com. There are three pins that define the SPI: SCLK, SDIO, and CSB (see Table 14). The SCLK pin is used to synchronize the read and write data presented to the ADC. The SDIO pin is a dualpurpose pin that allows data to be sent to and read from the internal ADC memory map registers. The CSB pin is an active low control that enables or disables the read and write cycles. Table 14. Serial Port Pins Pin SCLK SDIO CSB Function Serial Clock. The serial shift clock input. SCLK is used to synchronize serial interface reads and writes. Serial Data Input/Output. A dual-purpose pin. The typical role for this pin is as an input or output, depending on the instruction sent and the relative position in the timing frame. Chip Select Bar (Active Low). This control gates the read and write cycles. The falling edge of the CSB in conjunction with the rising edge of the SCLK determines the start of the framing sequence. During an instruction phase, a 16-bit instruction is transmitted followed by one or more data bytes, which is determined by Bit Field W0 and Bit Field W1. An example of the serial timing and its definitions can be found in Figure 69 and Table 15. During normal operation, CSB is used to signal to the device that SPI commands are to be received and processed. When CSB is brought low, the device processes SCLK and SDIO to obtain instructions. Normally, CSB remains low until the communication cycle is complete. However, if connected to a slow device, CSB can be brought high between bytes, allowing older microcontrollers enough time to transfer data into shift registers. CSB can be stalled when transferring one, two, or three bytes of data. When W0 and W1 are set to 11, the device enters streaming mode and continues to process data, either reading or writing, until CSB is taken high to end the communication cycle. This allows complete memory transfers without requiring additional instructions. Regardless of the mode, if CSB is taken high in the middle of a byte transfer, the SPI state machine is reset and the device waits for a new instruction. In addition to the operation modes, the SPI port configuration influences how the AD9219 operates. For applications that do not require a control port, the CSB line can be tied and held high. This places the remainder of the SPI pins into their secondary modes, as defined in the SDIO/ODM Pin and SCLK/DTP Pin sections. CSB can also be tied low to enable 2-wire mode. When CSB is tied low, SCLK and SDIO are the only pins required for communication. Although the device is synchronized during power-up, the user should ensure that the serial port remains synchronized with the CSB line when using this mode. When operating in 2-wire mode, it is recommended to use a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB line, streaming mode can be entered but not exited. In addition to word length, the instruction phase determines if the serial frame is a read or write operation, allowing the serial port to be used to both program the chip and read the contents of the on-chip memory. If the instruction is a readback operation, performing a readback causes the SDIO pin to change from an input to an output at the appropriate point in the serial frame. Data can be sent in MSB- or LSB-first mode. MSB-first mode is the default at power-up and can be changed by adjusting the configuration register. For more information about this and other features, see the AN-877 Application Note, Interfacing to High Speed ADCs via SPI. HARDWARE INTERFACE The pins described in Table 14 compose the physical interface between the user’s programming device and the serial port of the AD9219. The SCLK and CSB pins function as inputs when using the SPI. The SDIO pin is bidirectional, functioning as an input during write phases and as an output during readback. If multiple SDIO pins share a common connection, care should be taken to ensure that proper VOH levels are met. Assuming the same load for each AD9219, Figure 68 shows the number of SDIO pins that can be connected together and the resulting VOH level. This interface is flexible enough to be controlled by either serial PROMS or PIC microcontrollers, providing the user with an alternative method, other than a full SPI controller, to program the ADC (see the AN-812 Application Note at www.analog.com). Rev. E | Page 31 of 56 1.800 1.795 1.790 1.785 1.780 1.775 1.770 1.765 1.760 1.755 1.750 1.745 1.740 1.735 1.730 1.725 1.720 1.715 Data Sheet If the user chooses not to use the SPI, these dual-function pins serve their secondary functions when the CSB is strapped to AVDD during device power-up. See the Theory of Operation section for details on which pin-strappable functions are supported on the SPI pins. For users who wish to operate the ADC without using the SPI, remove any connections from the CSB, SCLK/DTP, and SDIO/ODM pins. By disconnecting these pins from the control bus, the ADC can function in its most basic operation. Each of these pins has an internal termination that floats to its respective level. 0 10 20 30 40 50 60 70 80 90 100 NUMBER OF SDIO PINS CONNECTED TOGETHER 05726-103 VOH (V) AD9219 Figure 68. SDIO Pin Loading tDS tS tHI tCLK tDH tH tLO CSB SCLK DON’T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 D5 D4 D3 D2 D1 D0 DON’T CARE 05726-012 SDIO DON’T CARE DON’T CARE Figure 69. Serial Timing Details Table 15. Serial Timing Definitions Parameter tDS tDH tCLK tS tH tHI tLO tEN_SDIO Timing (Minimum, ns) 5 2 40 5 2 16 16 10 tDIS_SDIO 10 Description Setup time between the data and the rising edge of SCLK Hold time between the data and the rising edge of SCLK Period of the clock Setup time between CSB and SCLK Hold time between CSB and SCLK Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK falling edge (not shown in Figure 69) Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising edge (not shown in Figure 69) Rev. E | Page 32 of 56 Data Sheet AD9219 MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS Each row in the memory map register table (Table 16) has eight address locations. The memory map is divided into three sections: the chip configuration register map (Address 0x00 to Address 0x02), the device index and transfer register map (Address 0x05 and Address 0xFF), and the ADC functions register map (Address 0x08 to Address 0x22). Undefined memory locations should not be written to except when writing the default values suggested in this data sheet. Addresses that have values marked as 0 should be considered reserved and have a 0 written into their registers during power-up. The leftmost column of the memory map indicates the register address number, and the default value is shown in the second rightmost column. The (MSB) Bit 7 column is the start of the default hexadecimal value given. For example, Address 0x09, the clock register, has a default value of 0x01, meaning that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in binary. This setting is the default for the duty cycle stabilizer in the on condition. By writing a 0 to Bit 6 of this address followed by a 0x01 in Register 0xFF (transfer bit), the duty cycle stabilizer turns off. It is important to follow each writing sequence with a transfer bit to update the SPI registers. For more information on this and other functions, consult the AN-877 Application Note, Interfacing to High Speed ADCs via SPI at www.analog.com. DEFAULT VALUES When the AD9219 comes out of a reset, critical registers are preloaded with default values. These values are indicated in Table 16, where an X refers to an undefined feature. LOGIC LEVELS An explanation of various registers follows: “Bit is set” is synonymous with “bit is set to Logic 1” or “writing Logic 1 for the bit.” Similarly, “clear a bit” is synonymous with “bit is set to Logic 0” or “writing Logic 0 for the bit.” Rev. E | Page 33 of 56 AD9219 Data Sheet Table 16. Memory Map Register Addr. (MSB) (Hex) Register Name Bit 7 Chip Configuration Registers 00 chip_port_config 0 01 chip_id 02 chip_grade Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 LSB first 1 = on 0 = off (default) Soft reset 1 = on 0 = off (default) 1 1 Soft reset 1 = on 0 = off (default) LSB first 1 = on 0 = off (default) (LSB) Bit 0 Default Value (Hex) 0 0x18 8-bit Chip ID Bits [7:0] (AD9219 = 0x03), (default) X Child ID [6:4] (identify device variants of Chip ID) 000 = 65 MSPS 001 = 40 MSPS Device Index and Transfer Registers 05 device_index_A X X FF X ADC Functions 08 modes 09 0D 0x02 X X X X Read only Data Channel B 1 = on (default) 0 = off X Default Notes/ Comments The nibbles should be mirrored so that LSB- or MSB-first mode is set correctly regardless of shift mode. Default is unique chip ID, different for each device. This is a readonly register. Child ID used to differentiate graded devices. Clock Channel FCO 1 = on 0 = off (default) X Data Channel D 1 = on (default) 0 = off X Data Channel C 1 = on (default) 0 = off X Data Channel A 1 = on (default) 0 = off SW transfer 1 = on 0 = off (default) 0x0F Bits are set to determine which on-chip device receives the next write command. X Clock Channel DCO 1 = on 0 = off (default) X 0x00 Synchronously transfers data from the master shift register to the slave. X X X X X 0x00 Determines various generic modes of chip operation. clock X X X X X Internal power-down mode 000 = chip run (default) 001 = full power-down 010 = standby 011 = reset X X Duty cycle stabilizer 1 = on (default) 0 = off 0x01 Turns the internal duty cycle stabilizer on and off. test_io User test mode 00 = off (default) 01 = on, single alternate 10 = on, single once 11 = on, alternate once Reset PN long gen 1 = on 0 = off (default) Reset PN short gen 1 = on 0 = off (default) Output test mode—see Table 9 in the Digital Outputs and Timing section. 0000 = off (default) 0001 = midscale short 0010 = +FS short 0011 = −FS short 0100 = checkerboard output 0101 = PN 23 sequence 0110 = PN 9 sequence 0111 = one-/zero-word toggle 1000 = user input 1001 = 1-/0-bit toggle 1010 = 1× sync 1011 = one bit high 1100 = mixed bit frequency (format determined by output_mode) 0x00 When this register is set, the test data is placed on the output pins in place of normal data. device_update Rev. E | Page 34 of 56 Data Sheet AD9219 Addr. (Hex) 14 Register Name output_mode (MSB) Bit 7 X 15 output_adjust 16 Bit 5 X X Bit 6 0 = LVDS ANSI-644 (default) 1 = LVDS low power (IEEE1596.3 similar) X output_phase X 19 user_patt1_lsb 1A Bit 4 X (LSB) Bit 1 Bit 0 00 = offset binary (default) 01 = twos complement Default Value (Hex) 0x00 Bit 3 X Bit 2 Output invert 1 = on 0 = off (default) Output driver termination 00 = none (default) 01 = 200 Ω 10 = 100 Ω 11 = 100 Ω X X X X X 0x03 B7 B6 B5 B4 0011 = output clock phase adjust (0000 through 1010) 0000 = 0° relative to data edge 0001 = 60° relative to data edge 0010 = 120° relative to data edge 0011 = 180° relative to data edge (default) 0101 = 300° relative to data edge 0110 = 360° relative to data edge 1000 = 480° relative to data edge 1001 = 540° relative to data edge 1010 = 600° relative to data edge 1011 to 1111 = 660° relative to data edge B3 B2 B1 B0 user_patt1_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 1B user_patt2_lsb B7 B6 B5 B4 B3 B2 B1 B0 0x00 1C user_patt2_msb B15 B14 B13 B12 B11 B10 B9 B8 0x00 21 serial_control LSB first 1 = on 0 = off (default) X X X 000 = 10 bits (default, normal bit stream) 001 = 8 bits 010 = 10 bits 011 = 12 bits 100 = 14 bits 0x00 22 serial_ch_stat X X X X <10 MSPS, low encode rate mode 1 = on 0 = off (default) X Channel powerdown 1 = on 0 = off (default) 0x00 Rev. E | Page 35 of 56 X X Channel output reset 1 = on 0 = off (default) X 0x00 0x00 Default Notes/ Comments Configures the outputs and the format of the data. Determines LVDS or other output properties. Primarily functions to set the LVDS span and common-mode levels in place of an external resistor. On devices that utilize global clock divide, determines which phase of the divider output is used to supply the output clock. Internal latching is unaffected. User-defined pattern, 1 LSB. User-defined pattern, 1 MSB. User-defined pattern, 2 LSB. User-defined pattern, 2 MSB. Serial stream control. Default causes MSB first and the native bit stream (global). Used to power down individual sections of a converter (local). AD9219 Data Sheet Power and Ground Recommendations Exposed Paddle Thermal Heat Slug Recommendations When connecting power to the AD9219, it is recommended that two separate 1.8 V supplies be used: one for analog (AVDD) and one for digital (DRVDD). If only one supply is available, it should be routed to the AVDD first and then tapped off and isolated with a ferrite bead or a filter choke preceded by decoupling capacitors for the DRVDD. The user can employ several different decoupling capacitors to cover both high and low frequencies. These should be located close to the point of entry at the PC board level and close to the parts, with minimal trace lengths. It is required that the exposed paddle on the underside of the ADC be connected to analog ground (AGND) to achieve the best electrical and thermal performance of the AD9219. An exposed continuous copper plane on the PCB should mate to the AD9219 exposed paddle, Pin 0. The copper plane should have several vias to achieve the lowest possible resistive thermal path for heat dissipation to flow through the bottom of the PCB. These vias should be solder-filled or plugged. A single PC board ground plane should be sufficient when using the AD9219. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections, optimum performance can be easily achieved. To maximize the coverage and adhesion between the ADC and PCB, partition the continuous copper plane by overlaying a silkscreen on the PCB into several uniform sections. This provides several tie points between the ADC and PCB during the reflow process, whereas using one continuous plane with no partitions only guarantees one tie point. See Figure 70 for a PCB layout example. For detailed information on packaging and the PCB layout of chip scale packages, see the AN-772 Application Note, A Design and Manufacturing Guide for the Lead Frame Chip Scale Package (LFCSP), at www.analog.com. 05726-013 SILKSCREEN PARTITION PIN 1 INDICATOR Figure 70. Typical PCB Layout Rev. E | Page 36 of 56 Data Sheet AD9219 EVALUATION BOARD each section. At least one 1.8 V supply is needed for AVDD_DUT and DRVDD_DUT; however, it is recommended that separate supplies be used for analog and digital signals and that each supply have a current capability of 1 A. To operate the evaluation board using the VGA option, a separate 5.0 V analog supply (AVDD_5 V) is needed. To operate the evaluation board using the SPI and alternate clock options, a separate 3.3 V analog supply (AVDD_3.3 V) is needed in addition to the other supplies. The AD9219 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and configurations. The converter can be driven differentially using a transformer (default) or an AD8332 driver. The ADC can also be driven in a single-ended fashion. Separate power pins are provided to isolate the DUT from the drive circuitry of the AD8332. Each input configuration can be selected by changing the connection of various jumpers (see Figure 73 to Figure 77). Figure 71 shows the typical bench characterization setup used to evaluate the ac performance of the AD9219. It is critical that the signal sources used for the analog input and clock have very low phase noise (<1 ps rms jitter) to realize the optimum performance of the converter. Proper filtering of the analog input signal to remove harmonics and lower the integrated or broadband noise at the input is also necessary to achieve the specified noise performance. INPUT SIGNALS When connecting the clock and analog sources to the evaluation board, use clean signal generators with low phase noise, such as Rohde & Schwarz SMHU or HP8644 signal generators or the equivalent, as well as a 1 m, shielded, RG-58, 50 Ω coaxial cable. Enter the desired frequency and amplitude from the ADC specifications tables. Typically, most Analog Devices evaluation boards can accept approximately 2.8 V p-p or 13 dBm sine wave input for the clock. When connecting the analog input source, it is recommended to use a multipole, narrow-band, band-pass filter with 50 Ω terminations. Good choices of such band-pass filters are available from TTE, Allen Avionics, and K&L Microwave, Inc. The filter should be connected directly to the evaluation board if possible. See Figure 73 to Figure 81 for the complete schematics and layout diagrams demonstrating the routing and grounding techniques that should be applied at the system level. POWER SUPPLIES This evaluation board has a wall-mountable switching power supply that provides a 6 V, 2 A maximum output. Connect the supply to the rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz. The other end of the supply is a 2.1 mm inner diameter jack that connects to the PCB at P503. Once on the PC board, the 6 V supply is fused and conditioned before connecting to three low dropout linear regulators that supply the proper bias to each of the various sections on the board. OUTPUT SIGNALS The default setup uses the Analog Devices HSC-ADC-FIFO5INTZ to interface with the Analog Devices standard dual-channel FIFO data capture board (HCS-ADC-EVALCZ). Two of the eight channels can be evaluated at the same time. For more information on the channel settings and optional settings of these boards, visit www.analog.com/FIFO. When operating the evaluation board in a nondefault condition, L504 to L507 can be removed to disconnect the switching power supply. This enables the user to bias each section of the board individually. Use P501 to connect a different supply for WALL OUTLET 100V TO 240V AC 47Hz TO 63Hz + – + AVDD_3.3V GND VCC GND – GND AVDD_5V XFMR INPUT INTERPOSER BOARD AD9219 EVALUATION BOARD CLK 3.3V 3.3V + CH A TO CH D 10-BIT SERIAL LVDS SPI Figure 71. Evaluation Board Connection Rev. E | Page 37 of 56 HSC-ADC-EVALCZ FIFO DATA CAPTURE BOARD PC RUNNING ADC ANALYZER AND SPI USER SOFTWARE USB CONNECTION SPI SPI SPI 05726-014 ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER BAND-PASS FILTER 1.8V – DRVDD_DUT – GND ROHDE & SCHWARZ, SMHU, 2V p-p SIGNAL SYNTHESIZER 1.8V + + GND 5.0V – SWITCHING POWER SUPPLY AVDD_DUT 6V DC 2A MAX AD9219 Data Sheet DEFAULT OPERATION AND JUMPER SELECTION SETTINGS A differential LVPECL clock can also be used to clock the ADC input using the AD9515 (U202). Populate R225 and R227 with 0 Ω resistors and remove R217 and R218 to disconnect the default clock path inputs. In addition, populate C207 and C208 with a 0.1 μF capacitor and remove C210 and C211 to disconnect the default clock path outputs. The AD9515 has many pin-strappable options that are set to a default mode of operation. Consult the AD9515 data sheet for more information about these and other options. The following is a list of the default and optional settings or modes allowed on the AD9219 Rev. A evaluation board. POWER: Connect the switching power supply that is provided in the evaluation kit between a rated 100 V ac to 240 V ac wall outlet at 47 Hz to 63 Hz and P503. AIN: The evaluation board is set up for a transformercoupled analog input with an optimum 50 Ω impedance match of 200 MHz of bandwidth (see Figure 72). For more bandwidth response, the differential capacitor across the analog inputs can be changed or removed. The common mode of the analog inputs is developed from the center tap of the transformer or AVDD_DUT/2. 0 –2 PDWN: To enable the power-down feature, short J201 to AVDD on the PDWN pin. SCLK/DTP: To enable one of the two digital test patterns on the digital outputs of the ADC, use J204. If J204 is tied to AVDD during device power-up, Test Pattern 10 0000 0000 is enabled. See the SCLK/DTP Pin section for details. SDIO/ODM: To enable the low power, reduced signal option (similar to the IEEE 1595.3 reduced range link LVDS output standard), use J203. If J203 is tied to AVDD during device power-up, it enables the LVDS outputs in a low power, reduced signal option from the default ANSI-644 standard. This option changes the signal swing from 350 mV p-p to 200 mV p-p, reducing the power of the DRVDD supply. See the SDIO/ODM Pin section for more details. CSB: To enable processing of the SPI information on the SDIO and SCLK pins, tie J202 low in the always enable mode. To ignore the SDIO and SCLK information, tie J202 to AVDD. Non-SPI Mode: For users who wish to operate the DUT without using SPI, remove Jumpers J302, J303, and J304. This disconnects the CSB, SCLK/DTP, and SDIO/ODM pins from the control bus, allowing the DUT to operate in its simplest mode. Each of these pins has internal termination and will float to its respective level. D + x, D − x: If an alternative data capture method to the setup shown in Figure 73 is used, optional receiver terminations, R206 to R211, can be installed next to the high speed backplane connector. –3dB CUTOFF = 200MHz –4 AMPLITUDE (dBFS) In addition, an on-board oscillator is available on the OSC201 and can act as the primary clock source. The setup is quick and involves installing R212 with a 0 Ω resistor and setting the enable jumper (J205) to the on position. If the user wishes to employ a different oscillator, two oscillator footprint options are available (OSC201) to check the ADC performance. –6 –8 –10 –12 –16 05726-085 –14 0 50 100 150 200 250 300 350 400 450 500 FREQUENCY (MHz) Figure 72. Evaluation Board Full-Power Bandwidth VREF: VREF is set to 1.0 V by tying the SENSE pin to ground, R237. This causes the ADC to operate in 2.0 V p-p full-scale range. A separate external reference option using the ADR510 is also included on the evaluation board. Populate R231 and R235 and remove C214. Proper use of the VREF options is noted in the Voltage Reference section. RBIAS: RBIAS has a default setting of 10 kΩ (R201) to ground and is used to set the ADC core bias current. CLOCK: The default clock input circuitry is derived from a simple transformer-coupled circuit using a high bandwidth 1:1 impedance ratio transformer (T201) that adds a very low amount of jitter to the clock path. The clock input is 50 Ω terminated and ac-coupled to handle single-ended sine wave types of inputs. The transformer converts the single-ended input to a differential signal that is clipped before entering the ADC clock inputs. Rev. E | Page 38 of 56 Data Sheet AD9219 ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION The following is a brief description of the alternative analog input drive configuration using the AD8332 dual VGA. If this drive option is in use, some components may need to be populated, in which case all the necessary components are listed in Table 17. For more details on the AD8332 dual VGA, including how it works and its optional pin settings, consult the AD8332 data sheet. To configure the analog input to drive the VGA instead of the default transformer option, the following components need to be removed and/or changed. Remove R102, R115, R128, R141, R161, R162, R163, R164, T101, T102, T103, and T104 in the default analog input path. Populate R101, R114, R127, and R140 with 0 Ω resistors in the analog input path. Populate R105, R113, R118, R124, R131, R137, R151, and R160 with 0 Ω resistors in the analog input path to connect the AD8332. Populate R152, R153, R154, R155, R156, R157, R158, R159, C103, C105, C110, C112, C117, C119, C124, and C126 with 10 kΩ resistors to provide an input common-mode level to the ADC analog inputs. Remove R305, R306, R313, R314, R405, R406, R412, and R424 to configure the AD8332. In this configuration, L301 to L308 and L401 to L408 are populated with 0 Ω resistors to allow signal connection and use of a filter if additional requirements are necessary. Rev. E | Page 39 of 56 AD9219 Data Sheet AVDD_DUT R105 DNP CH_A P102 VGA INPUT CONNECTION DNP INH1 AIN CHANNEL A R101 P101 DNP AIN R103 R102 0Ω 64.9Ω C101 0.1µF R104 0Ω R152 DNP FB102 R108 10Ω 33Ω T101 6 1 R106 DNP 5 CM1 2 CM1 4 3 VIN_A R161 499Ω C103 DNP C104 2.2pF R109 1kΩ FB103 R110 33Ω 10Ω C105 DNP R156 DNP R107 DNP R113 FB101 DNP 10Ω C102 0.1µF CH_A CM1 VIN_A E101 AVDD_DUT R111 1kΩ R112 1kΩ C106 DNP C107 0.1µF AVDD_DUT AVDD_DUT CH_B R153 DNP FB105 R121 10Ω 33Ω T102 6 1 FB104 10Ω C108 0.1µF CM2 R117 0Ω 2 5 3 4 R162 499Ω C110 DNP C111 2.2pF R123 1kΩ FB106 R122 33Ω 10Ω C112 DNP R157 DNP CM2 R120 DNP R124 C109 DNP 0.1µF CH_B R116 0Ω AIN VIN_B R119 DNP VIN_B CM2 E102 AVDD_DUT P106 VGA INPUT CONNECTION DNP INH3 AIN CHANNEL C R127 P105 DNP AIN R129 R128 0Ω 64.9Ω R130 0Ω C113 DNP FB108 R134 10Ω 33Ω 6 R132 DNP 2 5 3 4 CM3 VIN_C R163 499Ω C117 DNP C118 2.2pF R135 1kΩ FB109 R136 33Ω 10Ω C119 DNP VIN_C R158 DNP R133 DNP R137 FB107 DNP 10Ω C116 0.1µF CH_C CM3 E103 AVDD_DUT R138 1kΩ R139 1kΩ VGA INPUT CONNECTION INH4 CHANNEL D R140 P107 DNP AIN R141 64.9Ω C121 0.1µF C120 DNP AVDD_DUT AVDD_DUT CH_D R151 DNP R155 DNP FB111 R146 10Ω 33Ω T104 1 P108 DNP AIN R142 0Ω FB110 C122 10Ω 0.1µF CM4 2 3 6 R144 DNP 5 4 R160 R143 DNP 0Ω C123 0.1µF CH_D CM4 CM4 VIN_D R164 499Ω C124 DNP C125 2.2pF R148 1kΩ FB112 R147 33Ω 10Ω C126 DNP R159 DNP R145 DNP VIN_D E104 AVDD_DUT AVDD_DUT AVDD_DUT R154 DNP T103 1 CM3 C114 0.1µF R131 DNP CH_C C115 0.1µF R125 1kΩ R126 1kΩ R149 1kΩ R150 1kΩ C128 0.1µF C127 DNP DNP: DO NOT POPULATE Figure 73. Evaluation Board Schematic, DUT Analog Inputs Rev. E | Page 40 of 56 AVDD_DUT 05726-015 VGA INPUT CONNECTION INH2 CHANNEL B R114 P103 DNP AIN R115 64.9Ω P104 DNP R118 DNP P201 ENCODE INPUT ENC DNP P203 CLOCK CIRCUIT ENC AVDD AVDD VIN – D VIN + D AVDD AVDD CLK– CLK+ AVDD AVDD DRGND DRVDD C224 0.1µF R216 0Ω 2 R201 10kΩ AVDD AVDD VIN – A VIN + A AVDD PDWN C216 0.1µF R218 0Ω R217 0Ω OPT_CLK OPT_CLK 5 6 2 1 R221 10kΩ 1 1 U202 J201 J202 1 CR201 HSMS2812 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 DNP: DO NOT POPULATE DNP DNP R235 DNP R236 DNP R237 0Ω DNP R234 DNP VREF SELECT 3 3 C211 0.1µF C210 0.1µF 19 18 22 23 R240 243Ω C209 0.1µF DNP C208 0.1µF DNP 1 1 CLK VREF = EXTERNAL E203 LVDS OUTPUT E202 CLK VREF = 1V C217 0.1µF C218 0.1µF AVDD_3.3V AVDD_3.3V S10 AVDD_3.3V S9 AVDD_3.3V S8 AVDD_3.3V S7 AVDD_3.3V S6 LVPECL OUTPUT C215 0.1µF DNP CLIP SINE OUT (DEFAULT) CLK R243 100Ω R241 243Ω R255 0Ω R254 DNP CLK R253 0Ω R251 0Ω R249 0Ω R247 0Ω R245 0Ω R252 DNP R250 DNP R248 DNP R246 DNP R244 DNP C207 0.1µF DNP AVDD_3.3V S5 AVDD_3.3V S4 AVDD_3.3V S3 AVDD_3.3V S2 AVDD_3.3V S1 AVDD_3.3V S0 R242 100Ω DTP ENABLE ODM ENABLE ALWAYS ENABLE SPI PWDN ENABLE SDO_CHB CSB4_CHB CSB3__CHB SDI_CHB SCLK_CHB R265 0Ω R263 0Ω R261 0Ω R259 0Ω R257 0Ω CHD CHC CHB CHA FCO DCO C219 0.1µF C220 0.1µF C221 0.1µF NC = NO CONNECT R264 DNP R262 DNP R260 DNP R258 DNP R256 DNP VSENSE_DUT VREF = 0.5V VREF = 0.5V(1+R232/R233) REMOVE C214 WHEN USING EXTERNAL VREF C213 0.1µF R233 DNP R232 DNP DNP C214 1µF VREF_DUT REFERENCE CIRCUIT R231 DNP J203 1 3 SDIO_ODM J204 3 1 SCLK_DTP CSB_DUT R202 100kΩ R230 10kΩ R229 4.99kΩ GND_PAD 2 CLK OUT0 3 OUT0B CLKB AD9515 SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30 5 SYNCB OUT1 SIGNAL=DNC;27,28 OUT1B E201 R224 0Ω R223 0Ω R239 10kΩ C212 0.1µF V+ AVDD_DUT R228 470kΩ ADR510 1V TRIM/NC V– OPTIONAL CLOCK DRIVE CIRCUIT R222 4.02kΩ AVDD_3.3V AVDD_DUT GND DRVDD_DUT AVDD_DUT AVDD_DUT VIN_A VIN_A AVDD_DUT R226 49.9Ω DNP C206 0.1µF R238 DNP R220 DNP T201 3 4 R227 0Ω DNP R225 0Ω DNP 36 35 34 33 32 31 30 29 28 27 26 25 AVDD_3.3V CSB SDIO/ODM SCLK/DTP AVDD DRGND DRVDD DISABLE R219 R215 DNP 10kΩ OPT_CLK J205 ENABLE R214 10kΩ OPT_CLK C205 0.1µF VFAC3H-L R213 49.9kΩ VREF_DUT VSENSE_DUT AD9219LFCSP OSC201 14 VCC OE 1 12 VCC' OE' 3 10 5 OUT' GND' 8 OUT GND 7 R212 0Ω DNP C203 0.1µF AVDD_3.3V OPTIONAL CLOCK OSCILLATOR 1 2 3 4 5 6 7 8 9 10 11 12 AVDD_3.3V AVDD_DUT AVDD_DUT VIN_D VIN_D AVDD_DUT AVDD_DUT CLK CLK AVDD_DUT AVDD_DUT GND DRVDD_DUT CHD CHD U201 C201 0.1µF VIN_C VIN_C C202 2.2µF REFERENCE DECOUPLING AVDD_DUT VIN_B VIN_B C204 0.1µF AVDD_DUT AVDD_DUT CHC CHC CHB R266 100kΩ - DNP R203 100kΩ 48 47 46 45 44 43 42 41 40 39 38 37 VIN – C VIN + C AVDD AVDD REFT REFB VREF SENSE RBIAS AVDD VIN + B VIN – B D–D D+D D–C D+C D–B D+B D–A D+A FCO– FCO+ DCO– DCO+ 13 14 15 16 17 18 19 20 21 22 23 24 CHB CHA CHA FCO FCO R267 100kΩ - DNP R204 100kΩ 2 Figure 74. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface 3 1 1 DCO DCO AVDD_DUT R205 10kΩ U203 2 VREF S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0 Rev. E | Page 41 of 56 3 33 2 RSET 32 2 VS 1 2 GND 31 CW 6 7 8 9 10 11 12 13 14 15 16 25 AVDD_DUT C3 C4 C5 C6 C7 C8 C9 GNDCD2 GNDCD3 GNDCD4 GNDCD5 GNDCD6 GNDCD7 GNDCD8 45 46 47 48 49 50 D3 43 D4 44 D5 D6 D7 D8 D9 D10 GNDCD9 C10 A1 A2 A3 A4 A5 A6 A7 A8 A9 GNDAB1 GNDAB2 GNDAB3 GNDAB4 GNDAB5 GNDAB6 GNDAB7 GNDAB8 B1 B2 B3 B4 B5 B6 B7 B8 B9 11 12 13 14 15 16 17 18 19 C222 0.1µF C223 0.1µF R205–R211 OPTIONAL OUTPUT TERMINATIONS HEADER 6469169-1 1 2 21 3 22 4 23 5 24 25 6 26 7 27 8 28 9 29 51 D1 41 C1 31 GNDAB10 30 C10 B10 20 10 GNDAB9 52 32 C2GNDCD1 D2 42 33 53 34 35 54 36 55 37 56 38 57 39 58 40 59 60 P202 GNDCD10 DIGITAL OUTPUTS SDO_CHA CSB2_CHA CSB1_CHA SDI_CHA SCLK_CHA CHD R211 DNP CHC R210 DNP CHB R209 DNP CHA R208 DNP R207 FCO DNP DCO R206 DNP 05726-016 OPTIONAL EXT REF Data Sheet AD9219 CH_C CH_D POPULATE L301-L308 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. CH_C Data Sheet CH_D AD9219 R301 DNP R302 DNP L306 L307 0Ω 0Ω 16 15 14 13 12 11 10 9 C321 0.1µF AVDD_5V R314 10kΩ DNP VG C313 0.1µF C314 0.1µF 6 7 8 INH2 VPS2 LON2 RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2 RCLAMP PIN HILO PIN = LO = ±50mV HILO PIN = H = ±75mV R311 10kΩ DNP C310 0.1µF 19 18 17 VOL2 VOH2 COMM 20 LMD1 LMD2 4 5 R310 187Ω R317 274Ω C322 0.018µF C325 0.1µF C326 10µF R318 10kΩ C323 22pF C318 22pF L309 120nH C319 0.1µF DNP: DO NOT POPULATE C309 1000pF L310 120nH C324 0.1µF INH4 INH3 Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit Rev. E | Page 42 of 56 05726-017 C317 0.018µF C320 0.1µF C308 0.1µF MODE PIN POSITIVE GAIN SLOPE = 0-1.0V NEGATIVE GAIN SLOPE = 2.25V-5.0V R316 274Ω NC 22 21 VOL1 VPSV COMM VOH1 1 2 3 C316 0.1µF R309 187Ω AVDD_5V C315 10µF AVDD_5V R315 10kΩ R306 374Ω AD8332 LON1 VPS1 INH1 ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 C312 0.1µF R308 187Ω 24 23 R307 187Ω 25 26 27 28 29 30 31 32 C311 0.1µF C306 C307 0.1µF 0.1µF R305 374Ω U301 C304 DNP L308 0Ω R304 DNP AVDD_5V POWER DOWN ENABLE (0-1V = DISABLE POWER) AVDD_5V C305 0.1µF R312 10kΩ R313 10kΩ DNP HILO PIN HI GAIN RANGE = 2.25V-5.0V LO GAIN RANGE = 0-1.0V OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL C AND CHANNEL D 2 C303 L305 DNP 0Ω R303 DNP EXTERNAL VARIABLE GAIN DRIVE VG VARIABLE GAIN CIRCUIT (0-1.0V DC) VG GND CW AVDD_5V R320 R319 39kΩ 10kΩ JP301 C302 L302 L303 DNP L304 0Ω 0Ω 0Ω 1 C301 L301 DNP 0Ω OPTIONAL VGA DRIVE CIRCUIT FOR CHANNEL A AND CHANNEL B R414 10kΩ C413 10µF C410 0.1µF C409 0.1µF C414 0.1µF R411 10kΩ 25 26 27 28 29 30 31 32 CH_B ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 U401 R407 187Ω C405 0.1µF R408 187Ω R405 374Ω C415 0.018µF R415 274Ω Figure 76. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface Circuit (Continued) L409 120nH C416 0.1µF INH2 C419 0.1µF AD8332 R409 187Ω C422 0.1µF L410 120nH C421 22pF INH1 C417 0.1µF VG R413 10kΩ DNP C423 0.1µF R424 10kΩ DNP DNP: DO NOT POPULATE C426 R417 10µF 10kΩ C424 0.1µF C412 0.1µF POPULATE L401-L408 WITH 0Ω RESISTORS OR DESIGN YOUR OWN FILTER. C425 0.1µF 16 15 14 13 12 11 10 9 R410 187Ω C411 1000pF RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2 R406 374Ω S401 3 4 RESET/REPROGRAM 1 2 C427 0.1µF 8 VSS 7 GP0 6 GP1 CR401 MCLR/ GP2 5 GP3 PIC12F629 R419 261Ω 4 1 VDD 2 GP5 3 GP4 U402 AVDD_5V J402 AVDD_3.3V E401 +5V = PROGRAMMING = AVDD_5V +3.3V = NORMAL OPERATION = AVDD_3.3V MCLR/GP3 7 8 9 10 C418 22pF C406 C407 0.1µF 0.1µF C408 0.1µF C404 DNP L408 0Ω R404 DNP C403 L405 DNP 0Ω R403 DNP L406 L407 0Ω 0Ω C402 L402 L403 DNP L404 0Ω 0Ω 0Ω 20 POWER DOWN ENABLE (0–1V = DISABLE POWER) CH_A C401 L401 DNP 0Ω SPI CIRCUITRY FROM FIFO CSB1_CHA R423 0-DNP R422 0-DNP R421 0-DNP R426 0Ω R402 DNP J401 PICVCC 1 2 GP1 3 4 GP0 5 6 05726-018 AVDD_5V R412 10kΩ DNP HILO PIN HI GAIN RANGE = 2.25V-5.0V LO GAIN RANGE = 0-1.0V 24 23 R430 10kΩ R429 10kΩ R425 10kΩ SCLK_CHA R428 0Ω CH_B AVDD_5V 22 21 VOL1 VPSV LMD1 LMD2 4 5 NC SDI_CHA R420 0Ω CH_A 19 18 17 VOL2 VOH2 COMM INH2 VPS2 LON2 6 7 8 COMM VOH1 LON1 VPS1 INH1 1 2 3 AVDD_5V OPTIONAL AVDD_5V Rev. E | Page 43 of 56 C420 R416 0.018µF 274Ω AVDD_5V RCLAMP PIN HILO PIN = LO = ±50mV HILO PIN = H = ±75mV MODE PIN POSITIVE GAIN SLOPE = 0-1.0V NEGATIVE GAIN SLOPE = 2.25V-5.0V R418 4.75kΩ VCC 5 Y2 4 U404 2 GND 3 A2 VCC 5 Y2 4 NC7WZ16 1 A1 Y1 6 U403 2 GND 3 A2 C428 0.1µF AVDD_DUT CSB_DUT SCLK_DTP C429 0.1µF AVDD_DUT R431 1kΩ AVDD_DUT SDIO_ODM R433 1kΩ AVDD_3.3V REMOVE WHEN USING OR PROGRAMMING PIC (U402) R432 NC7WZ07 1kΩ Y1 6 1 A1 SDO_CHA R427 0Ω R401 DNP Data Sheet AD9219 PICVCC GP1 GP0 MCLR/GP3 PIC PROGRAMMING HEADER 1 3 2 + C501 10µF 3.3V_AVDD DUT_DRVDD P4 4 P5 5 P6 6 P7 7 3 INPUT L501 10µH L508 10µH L502 10µH L503 10µH OUTPUT4 OUTPUT4 OUTPUT1 2 4 4 2 2 L505 10µH C513 1µF L504 10µH AVDD_5V +3.3V AVDD_3.3V +1.8V AVDD_DUT +5.0V R501 261Ω DUT_DRVDD DUT_AVDD C507 0.1µF C534 1µF PWR_IN C532 1µF PWR_IN 3 3 C517 0.1µF C525 0.1µF C527 0.1µF C519 0.1µF INPUT 2 OUTPUT4 4 OUTPUT1 2 OUTPUT4 4 OUTPUT1 ADP3339AKC-5 U504 INPUT ADP3339AKC-3.3 U502 C516 0.1µF C524 0.1µF C526 0.1µF C518 0.1µF DECOUPLING CAPACITORS CR501 PWR_IN DRVDD_DUT +1.8V DRVDD_DUT C509 0.1µF AVDD_3.3V C505 0.1µF AVDD_DUT C503 0.1µF AVDD_5V 4 3 CHOKE_COIL 1 FER501 C515 1µF C506 10µF C508 10µF C504 10µF C502 10µF D501 S2A_RECT 2A DO-214AA OUTPUT1 ADP3339AKC-1.8 U503 INPUT ADP3339AKC-1.8 DNP: DO NOT POPULATE C512 1µF PWR_IN C514 1µF PWR_IN 3 DUT_AVDD P2 2 P3 3 U501 5V_AVDD P501 P1 1 P8 8 F501 SMDC110F OPTIONAL POWER INPUT P503 D502 3A SHOT_RECT DO-214AB C528 0.1µF C520 0.1µF C535 1µF L507 10µH C533 1µF L506 10µH H2 H1 H4 H3 C530 0.1µF C522 0.1µF C531 0.1µF C523 0.1µF 5V_AVDD 3.3V_AVDD MOUNTING HOLES CONNECTED TO GROUND C529 0.1µF C521 0.1µF 05726-019 POWER SUPPLY INPUT 6V, 2V MAXIMUM GND 1 GND 1 GND 1 Rev. E | Page 44 of 56 GND Figure 77. Evaluation Board Schematic, Power Supply Inputs 1 AD9219 Data Sheet AD9219 05726-020 Data Sheet Figure 78. Evaluation Board Layout, Primary Side Rev. E | Page 45 of 56 Data Sheet 05726-021 AD9219 Figure 79. Evaluation Board Layout, Ground Plane Rev. E | Page 46 of 56 AD9219 05726-022 Data Sheet Figure 80. Evaluation Board Layout, Power Plane Rev. E | Page 47 of 56 Data Sheet 05726-023 AD9219 Figure 81. Evaluation Board Layout, Secondary Side (Mirrored Image) Rev. E | Page 48 of 56 Data Sheet AD9219 Table 17. Evaluation Board Bill of Materials (BOM)1 Device PCB Capacitor Package PCB 402 Value PCB 0.1 μF, ceramic, X5R, 10 V, 10% tol Manufacturer Manufacturer’s Part Number Murata GRM155R71C104KA88D 4 Reference Designator AD9219LFCSP_REVA C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, C217, C218, C219, C220, C221, C222, C223, C224, C310, C311, C312, C313, C314, C316, C319, C320, C321, C324, C325, C409, C410, C412, C414, C416, C417, C419, C422, C423, C424, C425, C427, C428, C429, C503, C505, C507, C509, C516, C517, C518, C519, C520, C521, C522, C523, C524, C525, C526, C527, C528, C529, C530, C531 C104, C111, C118, C125 Capacitor 402 Murata GRM1555C1H2R2GZ01B 4 4 C315, C326, C413, C426 Capacitor 805 Murata GRM219R60J106KE19D 5 1 C202 Capacitor 603 Murata GRM188C70J225KE20D 6 2 C309, C411 Capacitor 402 Murata GRM155R71H102KA01D 7 4 C317, C322, C415, C420 Capacitor 402 AVX 0402YC183KAT2A 8 4 C318, C323, C418, C421 Capacitor 402 Murata GRM1555C1H220JZ01D 9 1 C501 Capacitor 1206 Rohm TCA1C106M8R 10 9 Capacitor 603 Murata GRM188R61C105KA93D 11 8 Capacitor 805 GRM21BR71H104KA01L 4 Capacitor 603 Murata GRM188R60J106M 13 1 CR201 Diode SOT-23 2 CR401, CR501 LED 603 Agilent Technologies Panasonic HSMS2812-TRIG 14 15 1 D502 Diode DO-214AB 0.1 μF, ceramic, X7R, 50 V, 10% tol 10 μF, ceramic, X5R, 6.3 V, 20% tol 30 V, 20 mA, dual Schottky Green, 4 V, 5 m candela 3 A, 30 V, SMC Murata 12 C214, C512, C513, C514, C515, C532, C533, C534, C535 C305, C306, C307, C308, C405, C406, C407, C408 C502, C504, C506, C508 2.2 pF, ceramic, COG, 0.25 pF tol, 50 V 10 μF, 6.3 V ±10% ceramic, X5R 2.2 μF, ceramic, X5R, 6.3 V, 10% tol 1000 pF, ceramic, X7R, 25 V, 10% tol 0.018 μF, ceramic, X7R, 16 V, 10% tol 22 pF, ceramic, NPO, 5% tol, 50 V 10 μF, tantalum, 16 V, 20% tol 1 μF, ceramic, X5R, 6.3 V, 10% tol SK33-TP 16 1 D501 Diode DO-214AA 2 A, 50 V, SMC 17 1 F501 Fuse 1210 18 1 FER501 Choke coil 2020 6.0 V, 2.2 A tripcurrent resettable fuse 10 μH, 5 A, 50 V, 190 Ω @ 100 MHz Micro Commercial Co. Micro Commercial Co. Tyco/Raychem Murata DLW5BSN191SQ2L Item 1 2 Qty. 1 75 3 Rev. E | Page 49 of 56 LNJ314G8TRA S2A-TP NANOSMDC110F-2 AD9219 Data Sheet Device Ferrite bead Package 603 Value 10 Ω, test freq 100 MHz, 25% tol, 500 mA Manufacturer Murata Manufacturer’s Part Number BLM18BA100SN1B 1 Reference Designator FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 JP301 Connector 2-pin Samtec TSW-102-07-G-S 21 2 J205, J402 Connector 3-pin Samtec TSW-103-07-G-S 22 1 J201 to J204 Connector 12-pin Samtec TSW-104-08-G-T 23 1 J401 Connector 10-pin Samtec TSW-105-08-G-D 24 8 L501, L502, L503, L504, L505, L506, L507, L508 Ferrite bead 1210 Murata BLM31PG500SN1L 25 4 L309, L310, L409, L410 Inductor 402 Murata LQG15HNR12J02B 26 16 Resistor 805 NIC Components NRC10ZOTRF 27 1 L301, L302, L303, L304, L305, L306, L307, L308, L401, L402, L403, L404, L405, L406, L407, L408 OSC201 100 mil header jumper, 2-pin 100 mil header jumper, 3-pin 100 mil header male, 4 × 3 triple row straight 100 mil header, male, 2 × 5 double row straight 10 μH, bead core 3.2 × 2.5 × 1.6 SMD, 2 A 120 nH, test freq 100 MHz, 5% tol, 150 mA 0 Ω, 1/8 W, 5% tol Oscillator SMT Valpey Fisher VFAC3H-L-65MHz 28 5 P101, P103, P105, P107, P201 Connector SMA Johnson Components 142-0710-851 29 1 P202 Connector Header Tyco 6469169-1 30 1 P503 Connector 0.1", PCMT Switchcraft RAPC722X 31 15 Resistor 402 NIC Components NRC04J103TRF 32 14 Resistor 402 0 Ω, 1/16 W, 5% tol NIC Components NRC04Z0TRF 33 4 R201, R205, R214, R215, R221, R239, R312, R315, R318, R411, R414, R417, R425, R429, R430 R103, R117, R129, R142, R216, R217, R218, R223, R224, R237, R420, R426, R427, R428 R102, R115, R128, R141 Resistor 402 4 R104, R116, R130, R143 Resistor 603 35 15 Resistor 402 36 8 R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R431, R432, R433 R108, R110, R121, R122, R134, R136, R146, R147 NIC Components NIC Components NIC Components NRC04F64R9TRF 34 64.9 Ω, 1/16 W, 1% tol 0 Ω, 1/10 W, 5% tol 1 kΩ, 1/16 W, 1% tol Resistor 402 33 Ω, 1/16 W, 5% tol NIC Components NRC04J330TRF Item 19 Qty. 12 20 Clock oscillator, 65.00 MHz, 3.3 V Side-mount SMA for 0.063" board thickness 1469169-1, right angle 2-pair, 25 mm, header assembly SC1153, power supply connector 10 kΩ, 1/16 W, 5% tol Rev. E | Page 50 of 56 NRC06Z0TRF NRC04F1001TRF Data Sheet AD9219 Item 37 Qty. 4 Reference Designator R161, R162, R163, R164 Device Resistor Package 402 38 3 R202, R203, R204 Resistor 402 39 1 R222 Resistor 402 40 1 R213 Resistor 402 41 1 R229 Resistor 402 42 2 R230, R319 Potentiometer 3-lead 43 1 R228 Resistor 402 44 1 R320 Resistor 402 45 8 Resistor 402 46 4 R307, R308, R309, R310, R407, R408, R409, R410 R305, R306, R405, R406 Resistor 402 47 4 R316, R317, R415, R416 Resistor 402 48 11 Resistor 201 49 1 R245, R247, R249, R251, R253, R255, R257, R259, R261, R263, R265 R418 Resistor 402 50 1 R419 Resistor 402 51 1 R501 Resistor 603 52 2 R240, R241 Resistor 402 53 2 R242, R243 Resistor 402 54 1 S401 Switch SMD 55 5 T101, T102, T103, T104, T201 Transformer CD542 56 2 U501, U503 IC SOT-223 57 2 U301, U401 IC LFCSP, CP-32 58 1 U504 IC SOT-223 Value 499 Ω, 1/16 W, 1% tol 100 kΩ, 1/16 W, 1% tol 4.02 kΩ, 1/16 W, 1% tol 49.9 Ω, 1/16 W, 0.5% tol 4.99 kΩ, 1/16 W, 5% tol 10 kΩ, cermet trimmer potentiometer, 18-turn top adjust, 10%, 1/2 W 470 kΩ, 1/16 W, 5% tol 39 kΩ, 1/16 W, 5% tol 187 Ω, 1/16 W, 1% tol 374 Ω, 1/16 W, 1% tol 274 Ω, 1/16 W, 1% tol 0 Ω, 1/20 W, 5% tol Manufacturer NIC Components NIC Components NIC Components Susumu 4.75 kΩ, 1/16 W, 1% tol 261 Ω, 1/16 W, 1% tol 261 Ω, 1/16 W, 1% tol 243 Ω, 1/16 W, 1% tol 100 Ω, 1/16 W, 1% tol Light touch, 100GE, 5 mm ADT1-1WT, 1:1 impedance ratio transformer ADP3339AKC-1.8, 1.5 A, 1.8 V LDO regulator AD8332ACP, ultralow noise precision dual VGA ADP3339AKC-5 Rev. E | Page 51 of 56 Manufacturer’s Part Number NRC04F4990TRF NRC04F1003TRF NRC04F4121TRF RR0510R-49R9-D NIC Components BC Components NRC04F4991TRF NIC Components NIC Components NIC Components NIC Components NIC Components Panasonic NRC04J474TRF NIC Components NIC Components NIC Components NIC Components NIC Components Panasonic NRC04J472TRF Mini-Circuits ADT1-1WT+ Analog Devices ADP3339AKCZ-1.8 Analog Devices AD8332ACPZ Analog Devices ADP3339AKCZ-5 CT94EW103 NRC04J393TRF NRC04F1870TRF NRC04F3740TRF NRC04F2740TRF ERJ-1GE0R00C NRC04F2610TRF NRC06F2610TRF NRC04F2430TRF NRC04F1000TRF EVQ-PLDA15 AD9219 Data Sheet Item 59 60 Qty. 1 1 Reference Designator U502 U201 Device IC IC Package SOT-223 LFCSP, CP-48-1 61 1 U203 IC SOT-23 62 1 U202 IC 63 1 U403 IC 64 1 U404 IC 65 1 U402 IC LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC 1 Value ADP3339AKC-3.3 AD9219BCPZ-65, quad, 10-bit, 65 MSPS serial LVDS 1.8 V ADC ADR510ARTZ, 1.0 V, precision low noise shunt voltage reference AD9515BCPZ Manufacturer Analog Devices Analog Devices Manufacturer’s Part Number ADP3339AKCZ-3.3 AD9219BCPZ-65 Analog Devices ADR510ARTZ Analog Devices AD9515BCPZ NC7WZ07 Fairchild NC7WZ07P6X_NL NC7WZ16 Fairchild NC7WZ16P6X_NL Flash prog mem 1k × 14, RAM size 64 × 8, 20 MHz speed, PIC12F controller series Microchip PIC12F629-I/SN This BOM is RoHS compliant. Rev. E | Page 52 of 56 Data Sheet AD9219 OUTLINE DIMENSIONS 0.30 0.23 0.18 0.60 MAX 0.60 MAX 37 36 PIN 1 INDICATOR 6.85 6.75 SQ 6.65 48 0.50 REF 1.00 0.85 0.80 12° MAX 0.80 MAX 0.65 TYP 13 12 0.22 MIN 5.50 REF 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.20 REF SEATING PLANE 5.50 SQ 5.45 (BOTTOM VIEW) 0.50 0.40 0.30 PIN 1 INDICATOR *5.55 EXPOSED PAD 25 24 TOP VIEW 1 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 WITH EXCEPTION TO EXPOSED PAD DIMENSION. 02-23-2010-C 7.10 7.00 SQ 6.90 Figure 82. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-8) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9219ABCPZ-40 AD9219ABCPZRL7-40 AD9219ABCPZ-65 AD9219ABCPZRL7-65 AD9219-65EBZ 1 2 Notes 2 Temperature Range −40°C to +85°C −40°C to +85°C −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ], 7” Tape and Reel Evaluation Board Z = RoHS Compliant Part. Interposer board (HSC-ADC-FIFO5-INTZ) is required to connect to HSC-ADC-EVALCZ data capture board. Rev. E | Page 53 of 56 Package Option CP-48-8 CP-48-8 CP-48-8 CP-48-8 AD9219 Data Sheet NOTES Rev. E | Page 54 of 56 Data Sheet AD9219 NOTES Rev. E | Page 55 of 56 AD9219 Data Sheet NOTES ©2006–2011 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05726-0-12/11(E) Rev. E | Page 56 of 56