AD AD9228BCPZ-65

Quad, 12-bit, 40/65 MSPS
Serial LVDS 1.8 V A/D Converter
AD9228
Four ADCs integrated into 1 package
119 mW ADC power per channel at 65 MSPS
SNR = 70 dB (to Nyquist)
Excellent linearity
DNL = ±0.3 LSB (typical)
INL = ±0.4 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power reduced signal option, IEEE 1596.3 similar
Data and frame clock outputs
315 MHz full power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital
converter (ADC) with an on-chip sample-and-hold circuit that
is designed for low cost, low power, small size, and ease of use.
The product operates at a conversion rate of up to 65 MSPS and
is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for the
appropriate LVDS serial data rate. A data clock (DCO) for
FUNCTIONAL BLOCK DIAGRAM
PDWN
AVDD
DRVDD
AD9228
12
VIN+A
VIN–A
PIPELINE
ADC
VIN+B
VIN–B
PIPELINE
ADC
VIN+C
VIN–C
PIPELINE
ADC
VIN+D
VIN–D
PIPELINE
ADC
SERIAL
LVDS
D+A
D–A
SERIAL
LVDS
D+B
D–B
SERIAL
LVDS
D+C
D–C
SERIAL
LVDS
D+D
D–D
12
12
12
VREF
SENSE
REFT
REFB
DRGND
+
–
REF
SELECT
FCO+
0.5V
SERIAL PORT
INTERFACE
DATA RATE
MULTIPLIER
FCO–
DCO+
DCO–
RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK–
05727-001
FEATURES
Figure 1.
capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI®).
The AD9228 is available in a Pb-free, 48-lead LFCSP package. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
Small Footprint. Four ADCs are contained in a small, spacesaving package; low power of 119 mW/channel at 65 MSPS.
2.
Ease of Use. A data clock output (DCO) is provided that
operates up to 390 MHz and supports double data rate
operation (DDR).
3.
User Flexibility. Serial port interface (SPI) control offers a wide
range of flexible features to meet specific system requirements.
4.
Pin-Compatible Family. This includes the AD9287 (8-bit),
AD9219 (10-bit), and AD9259 (14-bit).
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
AD9228
TABLE OF CONTENTS
Features .............................................................................................. 1
Analog Input Considerations ................................................... 19
Applications....................................................................................... 1
Clock Input Considerations...................................................... 21
General Description ......................................................................... 1
Serial Port Interface (SPI).............................................................. 29
Functional Block Diagram .............................................................. 1
Hardware Interface..................................................................... 29
Product Highlights ........................................................................... 1
Memory Map .................................................................................. 31
Revision History ............................................................................... 2
Reading the Memory Map Table.............................................. 31
Specifications..................................................................................... 3
Reserved Locations .................................................................... 31
AC Specifications.......................................................................... 4
Default Values ............................................................................. 31
Digital Specifications ................................................................... 5
Logic Levels................................................................................. 31
Switching Specifications .............................................................. 6
Evaluation Board ............................................................................ 35
Timing Diagrams.............................................................................. 7
Power Supplies ............................................................................ 35
Absolute Maximum Ratings............................................................ 9
Input Signals................................................................................ 35
Thermal Impedance ..................................................................... 9
Output Signals ............................................................................ 35
ESD Caution.................................................................................. 9
Default Operation and Jumper Selection Settings................. 36
Pin Configuration and Function Descriptions........................... 10
Alternative Analog Input Drive Configuration...................... 37
Equivalent Circuits ......................................................................... 12
Outline Dimensions ....................................................................... 51
Typical Performance Characteristics ........................................... 14
Ordering Guide .......................................................................... 51
Theory of Operation ...................................................................... 19
REVISION HISTORY
4/06—Revision 0: Initial Version
Rev. 0 | Page 2 of 52
AD9228
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
Parameter 1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Voltage (1 V Mode)
REFERENCE
Output Voltage Error (VREF = 1 V)
Load Regulation @ 1.0 mA (VREF = 1 V)
Input Resistance
ANALOG INPUTS
Differential Input Voltage Range (VREF = 1 V)
Common-Mode Voltage
Differential Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation (Including Output Drivers)
Power-Down Dissipation
Standby Dissipation 2
CROSSTALK
CROSSTALK (Overrange Condition) 3
Temperature
Min
12
Full
Full
Full
Full
Full
Full
Full
AD9228-40
Typ
Max
Guaranteed
±1
±2
±0.4
±0.3
±0.25
±0.4
Full
Full
Full
±2
±17
±21
Full
Full
Full
±2
3
6
Full
Full
Full
Full
2
AVDD/2
7
315
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1
1.8
1.8
155
31
335
2
72
−100
−100
Min
12
AD9228-65
Typ
Max
Guaranteed
±1
±2
±2
±0.3
±0.3
±0.4
±8
±8
±1.2
±0.7
±0.5
±1
±8
±8
±3.5
±0.7
±0.65
±1
±2
±17
±21
±30
±2
3
6
1.7
1.7
1.8
1.8
232
34
478
2
72
−100
−100
mV
mV
% FS
% FS
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
±30
2
AVDD/2
7
315
1.9
1.9
170
34
367
5.8
Unit
Bits
mV
mV
kΩ
V p-p
V
pF
MHz
1.9
1.9
245
38
510
5.8
V
V
mA
mA
mW
mW
mW
dB
dB
See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
Can be controlled via SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.
2
Rev. 0 | Page 3 of 52
AD9228
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
EFFECTIVE NUMBER OF BITS (ENOB)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
WORST HARMONIC (Second or Third)
WORST OTHER (Excluding Second or Third)
TWO-TONE INTERMODULATION DISTORTION (IMD)—
AIN1 AND AIN2 = −7.0 dBFS
1
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
fIN1 = 15 MHz,
fIN2 = 16 MHz
fIN1 = 70 MHz,
fIN2 = 71 MHz
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
AD9228-40
Min Typ
Max
70.5
68.5 70.2
70.2
70.0
70.3
68.0 69.8
69.7
69.5
11.4
11.1 11.37
11.37
11.33
85
72
82
80
80
−85
−82
−72
−80
−80
−90
−90
−80
−90
−90
80.8
75.0
AD9228-65
Min Typ
Max
70.2
70.0
68.5 70.0
69.5
70.0
70.0
68.0 69.8
69.0
11.37
11.33
11.1 11.33
11.25
85
85
73
84
74
−85
−85
−84
−73
−74
−90
−90
−90
−79
−88
77.8
77.0
Unit
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
Rev. 0 | Page 4 of 52
AD9228
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter 1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage 2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)
Logic 1 Voltage (IOH = 50 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D+, D−), (ANSI-644)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D+, D−),
(Low Power, Reduced Signal Option)1
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
1
2
AD9228-40
Typ
Max
Temperature
Min
Full
Full
25°C
25°C
250
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Full
Full
25°C
25°C
1.2
0
Full
Full
1.79
Full
Full
247
1.125
AD9228-65
Typ
Max
Min
CMOS/LVDS/LVPECL
CMOS/LVDS/LVPECL
250
1.2
20
1.5
1.2
30
0.5
3.6
0.3
1.2
70
0.5
V
V
kΩ
pF
3.6
0.3
V
V
kΩ
pF
DRVDD + 0.3
0.3
V
V
kΩ
pF
70
0.5
DRVDD + 0.3
0.3
1.2
0
30
2
30
2
1.79
0.05
0.05
454
1.375
Offset binary
250
1.30
Offset binary
V
V
LVDS
247
1.125
LVDS
150
1.10
3.6
0.3
30
0.5
LVDS
Full
Full
mV p-p
V
kΩ
pF
1.2
20
1.5
3.6
0.3
Unit
454
1.375
Offset binary
mV
V
LVDS
150
1.10
250
1.30
Offset binary
mV
V
See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
This is specified for LVDS and LVPECL only.
Rev. 0 | Page 5 of 52
AD9228
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
AD9228-40
Parameter 1
CLOCK 2
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
Temp
Min
Full
Full
Full
Full
40
OUTPUT PARAMETERS2
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD) 3
Full
Full
Full
Full
Full
2.0
DCO to Data Delay (tDATA)3
3
Typ
AD9228-65
Max
Min
Typ
Max
65
10
10
12.5
12.5
7.7
7.7
2.0
3.5
2.0
3.5
MSPS
MSPS
ns
ns
Full
(tSAMPLE/24) − 300
2.7
300
300
2.7
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24) + 300
(tSAMPLE/24) − 300
2.7
300
300
2.7
tFCO +
(tSAMPLE/24)
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
Full
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
(tSAMPLE/24) − 300
(tSAMPLE/24)
(tSAMPLE/24) + 300
ps
±150
±50
±150
ps
2.0
3.5
Unit
3.5
ns
ps
ps
ns
ns
DCO to FCO Delay (tFRAME)
Data to Data Skew
(tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power Down)
Pipeline Latency
Full
±50
25°C
25°C
Full
600
375
10
600
375
10
ns
μs
CLK
cycles
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
25°C
25°C
25°C
500
<1
1
500
<1
2
ps
ps rms
CLK
cycles
1
See the AN-835 Application Note, “Understanding High Speed ADC Testing and Evaluation,” for a complete set of definitions and how these tests were completed.
Can be adjusted via the SPI interface.
3
tSAMPLE/24 is based on the number of bits divided by 2 because the delays are based on half duty cycles.
2
Rev. 0 | Page 6 of 52
AD9228
TIMING DIAGRAMS
N-1
AIN
tA
N
tEH
CLK–
tEL
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
tPD
MSB
N – 10
D10
N – 10
D9
N – 10
D8
N – 10
D7
N – 10
D6
N – 10
D5
N – 10
D4
N – 10
D3
N – 10
D2
N – 10
D1
N – 10
D0
N – 10
MSB
N–9
D10
N–9
D1
N–10
D0
N–10
MSB
N–9
D8
N–9
D7
N–9
D6
N–9
D5
N–9
D+
05727-039
tDATA
D–
Figure 2. 12-Bit Data Serial Stream (Default)
N-1
AIN
tA
N
tEL
tEH
CLK–
CLK+
tCPD
DCO–
DCO+
tFRAME
tFCO
FCO–
FCO+
tPD
tDATA
D–
MSB
N–10
D8
N–10
D7
N–10
D6
N–10
D5
N–10
D4
N–10
D3
N–10
D2
N–10
05727-040
D+
Figure 3. 10-Bit Data Serial Stream
Rev. 0 | Page 7 of 52
AD9228
N-1
AIN
tA
N
tEH
tEL
CLK–
CLK+
tCPD
DCO–
DCO+
tFCO
tFRAME
FCO–
FCO+
tPD
tDATA
LSB
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
LSB
(N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 10) (N – 9)
D+
Figure 4. 12-Bit Data Serial Stream, LSB First
Rev. 0 | Page 8 of 52
D0
(N – 9)
05727-041
D–
AD9228
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
AVDD
DRVDD
AGND
AVDD
Digital Outputs
(D+, D−, DCO+,
DCO−, FCO+, FCO−)
CLK+, CLK−
VIN+, VIN−
SDIO/ODM
PDWN, SCLK/DTP, CSB
REFT, REFB, RBIAS
VREF, SENSE
ENVIRONMENTAL
Operating Temperature
Range (Ambient)
Maximum Junction
Temperature
Lead Temperature
(Soldering, 10 sec)
Storage Temperature
Range (Ambient)
With
Respect To
Rating
AGND
DRGND
DRGND
DRVDD
DRGND
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−2.0 V to +2.0 V
−0.3 V to +2.0 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL IMPEDANCE
Table 6.
AGND
AGND
AGND
AGND
AGND
AGND
−0.3 V to +3.9 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +2.0 V
−0.3 V to +2.0 V
Air Flow Velocity (m/s)
0.0
1.0
2.5
1
θJA1
24°C/W
21°C/W
19°C/W
θJB
θJC
12.6°C/W
1.2°C/W
θJA for a 4-layer PCB with solid ground plane (simulated). Exposed pad
soldered to PCB.
−40°C to +85°C
150°C
300°C
−65°C to +150°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 9 of 52
AD9228
AVDD
AVDD
REFT
REFB
VREF
SENSE
RBIAS
AVDD
VIN + B
VIN – B
45
44
43
42
41
40
39
38
37
PIN 1
INDICATOR
AVDD 1
36
AVDD
35
AVDD
34
VIN – A
33
VIN + A
AVDD 5
32
AVDD
AVDD 6
31
PDWN
30
CSB
CLK+ 8
29
SDIO/ODM
AVDD 9
28
SCLK/DTP
AVDD 10
27
AVDD
DRGND 11
26
DRGND
DRVDD 12
25
DRVDD
AVDD 2
VIN – D 3
EXPOSED PADDLE, PIN 0
(BOTTOM OF PACKAGE)
VIN + D 4
AD9228
DCO+ 24
23
DCO–
21
FCO–
FCO+ 22
D + A 20
D – A 19
D – B 17
D + C 16
D – C 15
D – D 13
D + D 14
D + B 18
TOP VIEW
CLK– 7
05727-003
VIN + C
46
VIN – C
48
47
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. 48-Lead LFCSP Top View
Table 7. Pin Function Descriptions
Pin No.
0
1, 2, 5, 6, 9, 10, 27, 32,
35, 36, 39, 45, 46
11, 26
12, 25
3
4
7
8
13
14
15
16
17
18
19
20
21
22
23
24
28
29
30
31
33
34
Name
AGND
AVDD
Description
Analog Ground (Exposed Paddle)
1.8 V Analog Supply
DRGND
DRVDD
VIN − D
VIN + D
CLK−
CLK+
D−D
D+D
D−C
D+C
D−B
D+B
D−A
D+A
FCO−
FCO+
DCO−
DCO+
SCLK/DTP
SDIO/ODM
CSB
PDWN
VIN + A
VIN − A
Digital Output Driver Ground
1.8 V Digital Output Driver Supply
ADC D Analog Input—Complement
ADC D Analog Input—True
Input Clock—Complement
Input Clock—True
ADC D Complement Digital Output
ADC D True Digital Output
ADC C Complement Digital Output
ADC C True Digital Output
ADC B Complement Digital Output
ADC B True Digital Output
ADC A Complement Digital Output
ADC A True Digital Output
Frame Clock Output—Complement
Frame Clock Output—True
Data Clock Output—Complement
Data Clock Output—True
Serial Clock/Digital Test Pattern
Serial Data Input-Output/Output Driver Mode
CSB
Power-Down
ADC A Analog Input—True
ADC A Analog Input—Complement
Rev. 0 | Page 10 of 52
AD9228
Pin No.
37
38
40
41
42
43
44
47
48
Name
VIN − B
VIN + B
RBIAS
SENSE
VREF
REFB
REFT
VIN + C
VIN − C
Description
ADC B Analog Input—Complement
ADC B Analog Input—True
External Resistor Sets the Internal ADC Core Bias Current
Reference Mode Selection
Voltage Reference Input/Output
Differential Reference (Negative)
Differential Reference (Positive)
ADC C Analog Input—True
ADC C Analog Input—Complement
Rev. 0 | Page 11 of 52
AD9228
EQUIVALENT CIRCUITS
DRVDD
V
V
D–
VIN
D+
V
05727-005
05727-030
V
DRGND
Figure 9. Equivalent Digital Output Circuit
Figure 6. Equivalent Analog Input Circuit
10Ω
CLK
10kΩ
1.25V
10kΩ
SCLK/PDWN
10Ω
1kΩ
30kΩ
05727-033
05727-032
CLK
Figure 7. Equivalent Clock Input Circuit
Figure 10. Equivalent SCLK/PDWN Input Circuit
RBIAS
350Ω
05727-031
30kΩ
05727-035
SDIO/ODM
100Ω
Figure 11. Equivalent RBIAS Circuit
Figure 8. Equivalent SDIO/ODM Input Circuit
Rev. 0 | Page 12 of 52
AD9228
AVDD
1kΩ
05727-034
VREF
6kΩ
Figure 12. Equivalent CSB Input Circuit
Figure 14. Equivalent VREF Circuit
1kΩ
05727-036
SENSE
05727-037
70kΩ
CSB
Figure 13. Equivalent SENSE Circuit
Rev. 0 | Page 13 of 52
AD9228
TYPICAL PERFORMANCE CHARACTERISTICS
0
–40
–60
–80
–40
–60
–80
05727-052
0
2
4
6
8
10
12
14
16
18
–120
20
05727-054
–100
–100
–120
AIN = –0.5dBFS
SNR = 69.62dB
ENOB = 10.96 BITS
SFDR = 72.48dBc
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
AIN = –0.5dBFS
SNR = 70.51dB
ENOB = 11.38 BITS
SFDR = 86.00dBc
0
5
10
Figure 15. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 40 MSPS
0
AIN = –0.5dBFS
SNR = 70.38dB
ENOB = 11.40 BITS
SFDR = 81.13dBc
25
30
AIN = –0.5dBFS
SNR = 68.74dB
ENOB = 10.88 BITS
SFDR = 72.99dBc
–20
AMPLITUDE (dBFS)
–40
–60
–80
–100
–40
–60
–80
05727-085
–100
0
2
4
6
8
10
12
14
16
18
–120
20
05727-055
AMPLITUDE (dBFS)
–20
0
5
10
FREQUENCY (MHz)
0
0
25
30
AIN = –0.5dBFS
SNR = 67.68dB
ENOB = 10.95 BITS
SFDR = 62.23dBc
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–40
–60
–80
0
5
10
15
20
25
30
FREQUENCY (MHz)
–120
05727-056
–100
05727-053
–120
20
Figure 19. Single-Tone 32k FFT with fIN = 120 MHz, fSAMPLE = 65 MSPS
AIN = –0.5dBFS
SNR = 70.53dB
ENOB = 11.38 BITS
SFDR = 86.04dBc
–20
15
FREQUENCY (MHz)
Figure 16. Single-Tone 32k FFT with fIN = 35 MHz, fSAMPLE = 40 MSPS
AMPLITUDE (dBFS)
20
Figure 18. Single-Tone 32k FFT with fIN = 70 MHz, fSAMPLE = 65 MSPS
0
–120
15
FREQUENCY (MHz)
FREQUENCY (MHz)
0
5
10
15
20
25
30
FREQUENCY (MHz)
Figure 20. Single-Tone 32k FFT with fIN = 170 MHz, fSAMPLE = 65 MSPS
Figure 17. Single-Tone 32k FFT with fIN = 2.3 MHz, fSAMPLE = 65 MSPS
Rev. 0 | Page 14 of 52
AD9228
0
84
AIN = –0.5dBFS
SNR = 67.58dB
ENOB = 10.93 BITS
SFDR = 68.39dBc
–20
82
SNR/SFDR (dB)
AMPLITUDE (dBFS)
80
–40
–60
–80
2V p-p, SFDR
78
76
74
05727-057
–120
70
0
5
10
15
20
25
68
10
30
2V p-p, SNR
15
25
30
35
40
Figure 24. SNR/SFDR vs. fSAMPLE, fIN = 35 MHz, fSAMPLE = 40 MSPS
Figure 21. Single-Tone 32k FFT with fIN = 190 MHz, fSAMPLE = 65 MSPS
90
AIN = –0.5dBFS
SNR = 65.56dB
ENOB = 10.6 BITS
SFDR = 62.72dBc
–20
20
ENCODE (MSPS)
FREQUENCY (MHz)
0
05727-061
72
–100
85
SNR/SFDR (dB)
–60
–80
–100
75
70
0
5
10
15
20
25
2V p-p, SNR
60
10
30
20
FREQUENCY (MHz)
40
50
60
Figure 25. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
90
84
2V p-p, SFDR
82
85
2V p-p, SFDR
80
SNR/SFDR (dB)
80
75
70
2V p-p, SNR
15
20
25
78
76
74
72
65
70
05727-059
SNR/SFDR (dB)
30
ENCODE (MSPS)
Figure 22. Single-Tone 32k FFT with fIN = 250 MHz, fSAMPLE = 65 MSPS
60
10
05727-062
65
05727-058
–120
80
30
35
68
10
40
ENCODE (MSPS)
05727-064
AMPLITUDE (dBFS)
2V p-p, SFDR
–40
2V p-p, SNR
20
30
40
50
60
ENCODE (MSPS)
Figure 23. SNR/SFDR vs. fSAMPLE, fIN = 10.3 MHz, fSAMPLE = 40 MSPS
Figure 26. SNR/SFDR vs. fSAMPLE, fIN = 35 MHz, fSAMPLE = 65 MSPS
Rev. 0 | Page 15 of 52
AD9228
100
100
2V p-p, SFDR
SNR/SFDR (dB)
70
60
80dB
REFERENCE
50
2V p-p, SNR
40
60
40
30
20
20
10
–50
–40
–30
–20
–10
2V p-p, SNR
50
30
05727-065
SNR/SFDR (dB)
70
80dB
REFERENCE
10
0
–60
0
–50
–40
Figure 27. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 40 MSPS
0
F IN = 35MHz
F SAMPLE = 40MSPS
AMPLITUDE (dBFS)
80dB
REFERENCE
2V p-p, SNR
40
30
20
–40
–60
–80
05727-066
–100
10
–50
–40
–30
–20
–10
–120
0
05727-049
SNR/SFDR (dB)
60
0
2
4
6
100
0
2V p-p, SFDR
AMPLITUDE (dBFS)
60
2V p-p, SNR
30
20
–50
–40
–30
–20
16
18
20
–10
–40
–60
–80
–100
05727-068
10
0
–60
14
–120
0
ANALOG INPUT LEVEL (dBFS)
05727-050
SNR/SFDR (dB)
70
40
12
AIN1 AND AIN2 = –7dBFS
SFDR = 74.76dBc
IMD2 = 81.03dBc
IMD3 = 75.00dBc
–20
80
80dB
REFERENCE
10
Figure 31. Two-Tone 32k FFT with fIN1 = 15 MHz and fIN2 = 16 MHz,
fSAMPLE = 40 MSPS
Figure 28. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 40 MSPS
F IN = 10.3MHz
F SAMPLE = 65MSPS
8
FREQUENCY (MHz)
ANALOG INPUT LEVEL (dBFS)
50
0
2V p-p, SFDR
70
90
–10
AIN1 AND AIN2 = –7dBFS
SFDR = 80.75dBc
IMD2 = 85.53dBc
IMD3 = 80.83dBc
–20
80
0
–60
–20
Figure 30. SNR/SFDR vs. Analog Input Level, fIN = 35 MHz, fSAMPLE = 65 MSPS
100
50
–30
ANALOG INPUT LEVEL (dBFS)
ANALOG INPUT LEVEL (dBFS)
90
2V p-p, SFDR
80
80
0
–60
FIN = 35MHz
FSAMPLE = 65MSPS
90
05727-070
90
F IN = 10.3MHz
F SAMPLE = 40MSPS
0
2
4
6
8
10
12
14
16
18
20
FREQUENCY (MHz)
Figure 29. SNR/SFDR vs. Analog Input Level, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Rev. 0 | Page 16 of 52
Figure 32. Two-Tone 32k FFT with fIN1 = 70 MHz and fIN2 = 71 MHz,
fSAMPLE = 40 MSPS
AD9228
0
90
AIN1 AND AIN2 = –7dBFS
SFDR = 78.15dBc
IMD2 = 77.84dBc
IMD3 = 88.94dBc
–20
85
SNR/SFDR (dB)
AMPLITUDE (dBFS)
2V p-p, SFDR
–40
–60
–80
80
75
70
2V p-p, SINAD
05727-048
–120
0
5
10
15
20
25
60
–40
30
05727-072
65
–100
–20
0
FREQUENCY (MHz)
Figure 33. Two-Tone 32k FFT with fIN1 = 15 MHz and
fIN2 = 16 MHz, fSAMPLE = 65 MSPS
0
80
0.4
0.3
0.2
INL (LSB)
–60
–80
0.1
0
–0.1
–0.2
–0.3
05727-051
–100
0
5
10
15
20
25
05727-073
AMPLITUDE (dBFS)
60
0.5
–40
–120
40
Figure 36. SINAD/SFDR vs. Temperature, fIN = 10.3 MHz, fSAMPLE = 65 MSPS
AIN1 AND AIN2 = –7dBFS
SFDR = 76.75dBc
IMD2 = 77.56dBc
IMD3 = 77.01dBc
–20
20
TEMPERATURE (°C)
–0.4
–0.5
30
0
500
1000
1500
2000
2500
3000
3500
4000
CODE
FREQUENCY (MHz)
Figure 34. Two-Tone 32k FFT with fIN1 = 70 MHz and
fIN2 = 71 MHz, fSAMPLE = 65 MSPS
Figure 37. INL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
0.5
90
0.4
85
2Vp-p, SFDR
0.3
80
DNL (LSB)
70
2Vp-p, SNR
65
0.1
0
–0.1
–0.2
60
50
1
10
100
05727-074
–0.3
55
05727-071
SNR/SFDR (dB)
0.2
75
–0.4
–0.5
1000
0
500
1000
1500
2000
2500
3000
3500
CODE
ANALOG INPUT LEVEL (dBFS)
Figure 38. DNL, fIN = 2.4 MHz, fSAMPLE = 65 MSPS
Figure 35. SNR/SFDR vs. fIN, fSAMPLE = 65 MSPS
Rev. 0 | Page 17 of 52
4000
AD9228
0
–30
–35
NPR = 60.83dB
NOTCH = 18.0MHz
NOTCH WIDTH = 3.0MHz
–20
AMPLITUDE (dBFS)
CMRR (dB)
–40
–45
–50
–55
–40
–60
–80
–60
05727-075
–70
0
5
10
15
20
25
30
–120
35
05727-076
–100
–65
0
5
10
Figure 39. CMRR vs. Frequency, fSAMPLE = 65 MSPS
25
30
0
0.26 LSB rms
–1
FUNDAMENTAL LEVEL (dB)
1.0
0.8
0.6
0.4
–2
–3dB CUTOFF = 315MHz
–3
–4
–5
–6
–7
N–3
N–2
N–1
N
N+1
N+2
N+3
CODE
05727-077
–8
0.2
05727-086
NUMBER OF HITS (Millions)
20
Figure 41. Noise Power Ratio (NPR), fSAMPLE = 65 MSPS
1.2
0
15
FREQUENCY (MHz)
FREQUENCY (MHz)
–9
–10
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 40. Input Referred Noise Histogram, fSAMPLE = 65 MSPS
Figure 42. Full Power Bandwidth vs. Frequency, fSAMPLE = 65 MSPS
Rev. 0 | Page 18 of 52
AD9228
THEORY OF OPERATION
The AD9228 architecture consists of a pipelined ADC that is
divided into three sections: a 4-bit first stage followed by eight
1.5-bit stages and a final 3-bit flash. Each stage provides
sufficient overlap to correct for flash errors in the preceding
stages. The quantized outputs from each stage are combined
into a final 12-bit result in the digital correction logic. The
pipelined architecture permits the first stage to operate on a
new input sample while the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched-capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
realizing the maximum bandwidth of the ADC. Such use of
low-Q inductors or ferrite beads is required when driving the
converter front end at high IF frequencies. Either a shunt capacitor
or two single-ended capacitors can be placed on the inputs to
provide a matching passive network. This ultimately creates a
low-pass filter at the input to limit any unwanted broadband
noise. See the AN-742 Application Note, the AN-827 Application
Note, and the Analog Dialogue article “Transformer-Coupled
Front-End for Wideband A/D Converters” for more information
on this subject. In general, the precise values depend on the
application.
The analog inputs of the AD9228 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device so that VCM = AVDD/2 is recommended for optimum performance, but the device can function
over a wider range with reasonable performance, as shown in
Figure 44 and Figure 45.
The output staging block aligns the data, carries out the error
correction, and passes the data to the output buffers. The data is
then serialized and aligned to the frame and output clock.
90
SFDR (dBc)
85
80
The analog input to the AD9228 is a differential switched-capacitor
circuit designed for processing differential input signals. The input
can support a wide common-mode range and maintain excellent
performance. An input common-mode voltage of midsupply
minimizes signal-dependent errors and provides optimum
performance.
SNR/SFDR (dB)
ANALOG INPUT CONSIDERATIONS
75
SNR (dB)
70
65
60
50
0.2
H
0.6
0.8
1.0
1.2
1.4
1.6
Figure 44. SNR/SFDR vs. Common-Mode Voltage,
fIN = 2.4 MHz, fSAMPLE = 65 MSPS
H
CSAMPLE
S
S
S
S
90
SFDR (dBc)
85
CSAMPLE
H
SNR/SFDR (dB)
80
05727-006
H
Figure 43. Switched-Capacitor Input Circuit
The clock signal alternately switches the input circuit between
sample mode and hold mode (see Figure 43). When the input
circuit is switched into sample mode, the signal source must be
capable of charging the sample capacitors and settling within
one-half of a clock cycle. A small resistor in series with each
input can help reduce the peak transient current injected from
the output stage of the driving source. In addition, low-Q inductors
or ferrite beads can be placed on each leg of the input to reduce
the high differential capacitance seen at the analog inputs, thus
Rev. 0 | Page 19 of 52
75
SNR (dB)
70
65
60
55
50
0.2
05727-079
CPAR
CPAR
0.4
ANALOG INPUT COMMON MODE VOLTAGE (V)
VIN+
VIN–
05727-078
55
0.4
0.6
0.8
1.0
1.2
1.4
ANALOG INPUT COMMON MODE VOLTAGE (V)
Figure 45. SNR/SFDR vs. Common-Mode Voltage,
fIN = 30 MHz, fSAMPLE = 65 MSPS
1.6
AD9228
ADT1–1WT
1:1 Z RATIO
For best dynamic performance, the source impedances driving
VIN+ and VIN− should be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates the positive and negative reference voltages, REFT
and REFB, respectively, that define the span of the ADC core.
The output common-mode of the reference buffer is set to
midsupply, and the REFT and REFB voltages and span are
defined as
2V p-p
49.9Ω
C
R
VIN+
ADC
AD9228
*CDIFF
R
AVDD
VIN–
C
1kΩ
AGND
*CDIFF IS OPTIONAL
05727-008
1kΩ
0.1μF
Figure 46. Differential Transformer Coupled Configuration
for Baseband Applications
REFT = 1/2 (AVDD + VREF)
REFB = 1/2 (AVDD − VREF)
Span = 2 × (REFT − REFB) = 2 × VREF
2V p-p
16nH
ADT1–1WT
0.1μF 1:1 Z RATIO 16nH
65Ω
It can be seen from these equations that the REFT and REFB
voltages are symmetrical about the midsupply voltage and, by
definition, the input span is twice the value of the VREF voltage.
499Ω
16nH
33Ω
2.2pF
VIN+
ADC
AD9228
1kΩ
33Ω
VIN–
AVDD
05727-047
1kΩ
Maximum SNR performance is always achieved by setting the
ADC to the largest span in a differential configuration. In the
case of the AD9228, the largest input span available is 2 V p-p.
Figure 47. Differential Transformer Coupled Configuration for IF Applications
Differential Input Configurations
Single-Ended Input Configuration
There are several ways in which to drive the AD9228 either
actively or passively. In either case, the optimum performance is
achieved by driving the analog input differentially. One example
is by using the AD8332 differential driver. It provides excellent
performance and a flexible interface to the ADC (see Figure 49)
for baseband applications. This configuration is common for
medical ultrasound systems.
A single-ended input may provide adequate performance in
cost-sensitive applications. In this configuration, SFDR and
distortion performance degrade due to the large input commonmode swing. If the application requires a single-ended input
configuration, ensure that the source impedances on each input
are well matched in order to achieve the best possible performance.
A full-scale input of 2 V p-p can still be applied to the ADC’s VIN+
pin while the VIN− pin is terminated. Figure 48 details a typical
single-ended input configuration.
0.1μF
1kΩ
However, the noise performance of most amplifiers is not
adequate to achieve the true performance of the AD9228. For
applications where SNR is a key parameter, differential transformer coupling is the recommended input configuration. Two
examples are shown in Figure 46 and Figure 47.
AVDD
C
R
0.1µF
49.9Ω
In any configuration, the value of the shunt capacitor, C, is
dependent on the input frequency and may need to be reduced
or removed.
ADC
AD9228
*CDIFF
AVDD
1kΩ 25Ω
0.1µF
VIN+
1kΩ
R
VIN–
C
1kΩ
05727-009
2V p-p
*CDIFF IS OPTIONAL
Figure 48. Single-Ended Input Configuration
0.1μF
VIP
0.1μF 120nH
VOH
INH
1V p-p
187Ω
AD8332
22pF
0.1μF
LNA
VGA
374Ω
LMD
VOL
LON
18nF
274Ω
VIN+
VIN
187Ω
R
VIN–
VREF
0.1μF
0.1μF
0.1μF
Figure 49. Differential Input Configuration Using the AD8332
Rev. 0 | Page 20 of 52
ADC
AD9228
C
1.0kΩ
0.1μF
R
1.0kΩ
10μF
05727-007
LOP
AD9228
For optimum performance, the AD9228 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
This signal is typically ac-coupled into the CLK+ and CLK− pins
via a transformer or capacitors. These pins are biased internally
and require no additional bias.
Figure 50 shows one preferred method for clocking the AD9228.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9228 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9228 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
CLK+ should be directly driven from a CMOS gate, and the
CLK− pin should be bypassed to ground with a 0.1 μF capacitor
in parallel with a 39 kΩ resistor (see Figure 53). Although the
CLK+ input circuit supply is AVDD (1.8 V), this input is
designed to withstand input voltages up to 3.3 V, making the
selection of the drive logic voltage very flexible.
0.1µF
CLOCK
INPUT
CLK
50Ω*
OPTIONAL
0.1µF
100Ω
AD9510/1/2/3/4/5
CMOS DRIVER
CLK+
ADC
AD9228
CLK
0.1µF
CLK–
0.1µF
39kΩ
05727-027
CLOCK INPUT CONSIDERATIONS
*50Ω RESISTOR IS OPTIONAL
Figure 53. Single-Ended 1.8 V CMOS Sample Clock
50Ω
ADC
AD9228
100Ω
0.1µF
CLK–
SCHOTTKY
DIODES:
HSM2812
0.1µF
CLOCK
INPUT
CLK+
CLK+
100Ω
AD9510/1/2/3/4/5
0.1µF PECL DRIVER
0.1µF
CLK
50Ω*
240Ω
50Ω*
ADC
AD9228
CLK–
05727-025
CLOCK
INPUT
0.1µF
CLK
240Ω
*50Ω RESISTORS ARE OPTIONAL
Figure 51. Differential PECL Sample Clock
0.1µF
CLOCK
INPUT
CLK+
AD9510/1/2/3/4/5
0.1µF LVDS DRIVER
100Ω
0.1µF
CLK
50Ω*
50Ω*
0.1µF
CLK+
ADC
AD9228
CLK–
Figure 54. Single-Ended 3.3 V CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9228 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9228. When the DCS is on, noise and distortion performance are nearly flat for a wide range of duty cycles. The DCS
function cannot be turned off.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 10 clock cycles
to allow the DLL to acquire and lock to the new rate.
0.1µF
CLK
OPTIONAL 0.1µF
100Ω
CLK
ADC
AD9228
CLK–
05727-026
CLOCK
INPUT
AD9510/1/2/3/4/5
CMOS DRIVER
*50Ω RESISTOR IS OPTIONAL
If a low jitter clock is available, another option is to ac-couple a
differential PECL signal to the sample clock input pins as shown
in Figure 51. The AD9510/AD9511/AD9512/AD9513/AD9514/
AD9515 family of clock drivers offers excellent jitter performance.
0.1µF
CLK
0.1µF
Figure 50. Transformer Coupled Differential Clock
CLOCK
INPUT
0.1µF
50Ω*
05727-024
0.1µF
CLOCK
INPUT
05727-028
MIN-CIRCUITS
ADT1–1WT, 1:1Z
0.1µF
XFMR
*50Ω RESISTORS ARE OPTIONAL
Figure 52. Differential LVDS Sample Clock
Rev. 0 | Page 21 of 52
AD9228
Clock Jitter Considerations
Power Dissipation and Power-Down Mode
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
As shown in Figure 56 and Figure 57, the power dissipated by
the AD9228 is proportional to its sample rate. The digital power
dissipation does not vary much because it is determined primarily
by the DRVDD supply and bias current of the LVDS output drivers.
360
180
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
130
340
AVDD CURRENT
140
320
120
300
TOTAL POWER
100
280
80
260
60
240
40
220
DRVDD CURRENT
20
0
POWER (mW)
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9228.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
160
CURRENT (mA)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 55).
200
10
15
20
25
30
35
40
180
ENCODE (MSPS)
05727-089
SNR degradation = 20 × log 10 [1/2 × π × fA × tJ]
Figure 56. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 40 MSPS
250
480
460
200
RMS CLOCK JITTER REQUIREMENT
AVDD CURRENT
440
100
16 BITS
90
14 BITS
80
50
40
30
1
400
380
100
360
340
50
10 BITS
0.125 ps
0.25 ps
0.5 ps
1.0 ps
2.0 ps
10
100
ANALOG INPUT FREQUENCY (MHz)
0
10
DRVDD CURRENT
20
30
320
40
ENCODE (MSPS)
1000
50
60
300
05727-081
70
60
420
TOTAL POWER
150
12 BITS
05727-038
SNR (dB)
110
POWER (mW)
CURRENT (mA)
120
Figure 57. Supply Current vs. fSAMPLE for fIN = 10.3 MHz, fSAMPLE = 65 MSPS
Figure 55. Ideal SNR vs. Input Frequency and Jitter
Rev. 0 | Page 22 of 52
AD9228
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode; shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 μF and 2.2 μF decoupling
capacitors on REFT and REFB, it takes approximately 1 sec to
fully discharge the reference buffer decoupling capacitors and
375 μs to restore full operation.
There are a number of other power-down options available
when using the SPI port interface. The user can individually
power down each channel or put the entire device into standby
mode. This allows the user to keep the internal PLL powered
when fast wake-up times (~600 ns) are required. See the
Memory Map section for more details on using these features.
Digital Outputs and Timing
The AD9228 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to a
low power, reduced signal option similar to the IEEE 1596.3
standard using the SDIO/ODM pin or via the SPI. This LVDS
standard can further reduce the overall power dissipation of the
device by roughly 15 mW. See the SDIO/ODM Pin section or
Table 15 in the Memory Map section for more information. The
LVDS driver current is derived on-chip and sets the output
current at each output equal to a nominal 3.5 mA. A 100 Ω
differential termination resistor placed at the LVDS receiver
inputs results in a nominal 350 mV swing at the receiver.
The AD9228 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far-end receiver termination and poor differential
trace routing may result in timing errors. It is recommended
that the trace length is no longer than 24 inches and that the
differential output traces are kept close together and at equal
lengths. An example of the FCO and data stream with proper
trace length and position can be found in Figure 58.
05727-045
By asserting the PDWN pin high, the AD9228 is placed in
power-down mode. In this state, the ADC typically dissipates
3 mW. During power-down, the LVDS output drivers are placed in
a high impedance state. The AD9228 returns to normal operating
mode when the PDWN pin is pulled low. This pin is both 1.8 V
and 3.3 V tolerant.
CH1 200mV/DIV = DCO
CH2 200mV/DIV = DATA
CH3 500mV/DIV = FCO
2.5ns/DIV
Figure 58. LVDS Output Timing Example in ANSI Mode (Default)
An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 59. Figure 60 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches. Additional
SPI options allow the user to further increase the internal termination (increasing the current) of all four outputs in order to
drive longer trace lengths (see Figure 61). Even though this
produces sharper rise and fall times on the data edges and is less
prone to bit errors, the power dissipation of the DRVDD supply
increases when this option is used. Also notice in Figure 61 that
the histogram has improved. See the Memory Map section for
more details.
Rev. 0 | Page 23 of 52
AD9228
EYE: ALL BITS
ULS: 10000/15600
EYE: ALL BITS
400
EYE DIAGRAM VOLTAGE (V)
EYE DIAGRAM VOLTAGE (V)
500
0
ULS: 9599/15599
200
0
–200
–400
–500
–1ns
–0.5ns
0ns
0.5ns
–1ns
1ns
–0.5ns
0ns
0.5ns
1ns
50
0
–100ps
–0ps
0
–150ps
100ps
Figure 59. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
than 24 Inches on Standard FR-4
EYE: ALL BITS
EYE DIAGRAM VOLTAGE (V)
200
–100ps
–50ps
–0ps
50ps
100ps
150ps
Figure 61. Data Eye for LVDS Outputs in ANSI Mode with 100 Ω Termination
on and Trace Lengths Greater than 24 Inches on Standard FR-4
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 8.
If it is desired to change the output data format to twos
complement, see the Memory Map section.
ULS: 9600/15600
Table 8. Digital Output Coding
0
Code
4095
2048
2047
0
–200
–1ns
–0.5ns
0ns
0.5ns
Digital Output Offset Binary
(D11 ... D0)
1111 1111 1111
1000 0000 0000
0111 1111 1111
0000 0000 0000
Data from each ADC is serialized and provided on a separate
channel. The data rate for each serial stream is equal to 12 bits
times the sample clock rate, with a maximum of 780 Mbps
(12 bits × 65 MSPS = 780 Mbps). The lowest typical conversion
rate is 10 MSPS. However, if lower sample rates are required for
a specific application, the PLL can be set up for encode rates
lower than 10 MSPS via the SPI. This allows encode rates as low
as 5 MSPS. See the Memory Map section to enable this feature.
05727-044
50
0
–150ps
(VIN+) − (VIN−), Input
Span = 2 V p-p (V)
+1.00
0.00
−0.000488
−1.00
1ns
100
TIE JITTER HISTOGRAM (Hits)
50
05727-042
TIE JITTER HISTOGRAM (Hits)
100
05727-043
TIE JITTER HISTOGRAM (Hits)
100
–100ps
–50ps
–0ps
50ps
100ps
150ps
Figure 60. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4
Rev. 0 | Page 24 of 52
AD9228
Two output clocks are provided to assist in capturing data from
the AD9228. The DCO is used to clock the output data and is
equal to six times the sampling clock (CLK) rate. Data is
clocked out of the AD9228 and must be captured on the rising
and falling edges of the DCO that supports double data rate
(DDR) capturing. The frame clock out (FCO) is used to signal
the start of a new output byte and is equal to the sampling clock
rate. See the timing diagram shown in Figure 2 for more
information.
Table 9. Flex Output Test Modes
Output Test
Mode Bit
Sequence
0000
0001
Pattern Name
OFF (default)
Midscale Short
0010
+Full-Scale Short
0011
−Full-Scale Short
0100
Checker Board
0101
0110
0111
PN Sequence Long 1
PN Sequence Short1
One/Zero Word Toggle
1000
1001
User Input
One/Zero Bit Toggle
1010
1× Sync
1011
One Bit High
1100
Mixed Frequency
1
Digital Output Word 1
N/A
1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
N/A
N/A
1111 1111 (8-bit)
11 1111 1111 (10-bit)
1111 1111 1111 (12-bit)
11 1111 1111 1111 (14-bit)
Register 0x19 to Register 0x1A
1010 1010 (8-bit)
10 1010 1010 (10-bit)
1010 1010 1010 (12-bit)
10 1010 1010 1010 (14-bit)
0000 1111 (8-bit)
00 0001 1111 (10-bit)
0000 0011 1111 (12-bit)
00 0000 0111 1111 (14-bit)
1000 0000 (8-bit)
10 0000 0000 (10-bit)
1000 0000 0000 (12-bit)
10 0000 0000 0000 (14-bit)
1010 0011 (8-bit)
10 0110 0011 (10-bit)
1010 0011 0011 (12-bit)
10 1000 0110 0111 (14-bit)
Digital Output Word 2
N/A
Same
Subject
to Data
Format
Select
N/A
Yes
Same
Yes
Same
Yes
0101 0101 (8-bit)
01 0101 0101 (10-bit)
0101 0101 0101 (12-bit)
01 0101 0101 0101 (14-bit)
N/A
N/A
0000 0000 (8-bit)
00 0000 0000 (10-bit)
0000 0000 0000 (12-bit)
00 0000 0000 0000 (14-bit)
Register 0x1B to Register 0x1C
N/A
No
Yes
Yes
No
No
No
N/A
No
N/A
No
N/A
No
PN, or pseudorandom number, sequence is determined by the number of bits in the shift register. The long sequence is 23 bits and the short sequence is
9 bits. How the sequence is generated and utilized is described in the ITU O.150 standard. In general, the polynomial, X23 + X18 + 1 (long) and X9 + X5 + 1
(short), defines the pseudorandom sequence.
Rev. 0 | Page 25 of 52
AD9228
When using the serial port interface (SPI), the DCO phase can
be adjusted in 60° increments relative to the data edge. This
enables the user to refine system timing margins if required.
The default DCO timing, as shown in Figure 2, is 90° relative to
the output data edge.
An 8-, 10-, and 14-bit serial stream can also be initiated from
the SPI. This allows the user to implement and test compatibility
to lower and higher resolution systems. When changing the
resolution to an 8- or 10-bit serial stream, the data stream is
shortened. See Figure 3 for the 10-bit example. However, when
using the 14-bit option, the data stream stuffs two 0s at the end
of the normal 14-bit serial data.
When using the SPI, all of the data outputs can also be inverted
from their nominal state. This is not to be confused with
inverting the serial stream to an LSB-first mode. In default
mode, as shown in Figure 2, the MSB is represented first in the
data output serial stream. However, this can be inverted so that
the LSB is represented first in the data output serial stream (see
Figure 4).
There are 12 digital output test pattern options available that
can be initiated through the SPI. This is a useful feature when
validating receiver capture and timing. Refer to Table 9 for the
output bit sequencing options available. Some test patterns have
two serial sequential words and can be alternated in various
ways, depending on the test pattern chosen. It should be noted
that some patterns may not adhere to the data format select
option. In addition, customer user patterns can be assigned in
the 0x19, 0x1A, 0x1B, and 0x1C register addresses. All test mode
options can support 8- to 14-bit word lengths in order to verify
data capture to the receiver.
Please consult the Memory Map section for information on how
to change these additional digital output timing features through
the serial port interface or SPI.
SDIO/ODM Pin
This pin is for applications that do not require SPI mode operation.
The SDIO/ODM pin can enable a low power, reduced signal option
similar to the IEEE 1596.3 reduced range link output standard if
this pin and the CSB pin are tied to AVDD during device powerup. This option should only be used when the digital output trace
lengths are less than 2 inches in length to the LVDS receiver. The
FCO, DCO, and outputs still work as usual, but the LVDS signal
swing of all channels is reduced from 350 mV p-p to 200 mV p-p.
This output mode allows the user to further lower the power on
the DRVDD supply. For applications where this pin is not used,
it should be tied low. In this case, the device pin can be left open,
and the 30 kΩ internal pull-down resistor pulls this pin low. This
pin is only 1.8 V tolerant. If applications require this pin to be
driven from a 3.3 V logic level, insert a 1 kΩ resistor in series
with this pin to limit the current.
Table 10. Output Driver Mode Pin Settings
Selected ODM
Normal
operation
ODM
ODM Voltage
10 kΩ to AGND
AVDD
Resulting
Output Standard
ANSI-644
(default)
Resulting
FCO and DCO
ANSI-644
(default)
Low power,
reduced signal
option
Low power,
reduced
signal
option
SCLK/DTP Pin
This pin is for applications that do not require SPI mode operation.
The serial clock/digital test pattern (SCLK/DTP) pin can enable
a single digital test pattern if this pin and the CSB pin are held
high during device power-up. When the DTP is tied to AVDD,
all the ADC channel outputs shift out the following pattern:
1000 0000 0000. The FCO and DCO outputs still work as usual
while all channels shift out the repeatable test pattern. This pattern
allows the user to perform timing alignment adjustments among
the FCO, DCO, and output data. For normal operation, this pin
should be tied to AGND through a 10 kΩ resistor. This pin is
both 1.8 V and 3.3 V tolerant.
Table 11. Digital Test Pattern Pin Settings
Selected DTP
Normal
operation
DTP
DTP Voltage
10 kΩ to AGND
AVDD
Resulting
D+ and D−
Normal
operation
1000 0000 0000
Resulting
FCO and DCO
Normal operation
Normal operation
Additional and custom test patterns can also be observed when
commanded from the SPI port. Consult the Memory Map
section to choose from the different options available.
CSB Pin
The chip select bar (CSB) pin should be tied to AVDD for
applications that do not require SPI mode operation. By tying
CSB high, all SCLK and SDIO information is ignored. This pin
is both 1.8 V and 3.3 V tolerant.
RBIAS Pin
To set the internal core bias current of the ADC, place a resistor
(nominally equal to 10.0 kΩ) to ground at the RBIAS pin. The
resistor current is derived on-chip and sets the ADC’s AVDD
current to a nominal 232 mA at 65 MSPS. Therefore, it is
imperative that at least a 1% tolerance on this resistor be used to
achieve consistent performance. If SFDR performance is not as
critical as power, simply adjust the ADC core current to achieve
a lower power. Figure 62 and Figure 63 show the relationship
between the dynamic range and power as the RBIAS resistance
is changed. Nominally, we use a 10.0 kΩ value, as indicated by
the dashed line.
Rev. 0 | Page 26 of 52
AD9228
75
90
SNR
65
SFDR (dBc)
80
SFDR
75
60
70
55
65
50
24
2
4
6
8
10
12
14
16
18
20
22
SNR (dBc)
70
05727-063
85
Internal Reference Operation
RESISTANCE (kΩ)
Figure 62. SFDR vs. RBIAS
A comparator within the AD9228 detects the potential at the
SENSE pin and configures the reference. If SENSE is grounded,
the reference amplifier switch is connected to the internal
resistor divider (see Figure 64), setting VREF to 1 V.
The REFT and REFB pins establish their input span of the ADC
core from the reference configuration. The analog input fullscale range of the ADC equals twice the voltage at the reference
pin for either an internal or an external reference configuration.
If the reference of the AD9228 is used to drive multiple
converters to improve gain matching, the loading of the reference by the other converters must be considered. Figure 66
depicts how the internal reference voltage is affected by loading.
600
VIN+
VIN–
REFT
500
ADC
CORE
IAVDD (mA)
400
0.1µF
0.1µF
+
2.2µF
REFB
300
1µF
200
0.1µF
SELECT
LOGIC
0.5V
SENSE
05727-082
100
3
8
13
18
23
05727-010
0
0.1µF
VREF
RESISTANCE (kΩ)
Figure 63. IAVDD vs. RBIAS
Figure 64. Internal Reference Configuration
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9228. This is gained up by a factor of 2 internally, setting
VREF to 1.0 V, which results in a full-scale differential input span
of 2 V p-p. The VREF is set internally by default; however, the
VREF pin can be driven externally with a 1.0 V reference to
achieve more accuracy.
VIN+
VIN–
REFT
ADC
CORE
+
2.2µF
0.1µF
0.1µF
AVDD
SELECT
LOGIC
0.5V
SENSE
05727-046
1µF
Table 12. Reference Settings
Selected
Mode
External
Reference
Internal,
2 V p-p FSR
0.1µF
REFB
VREF
When applying the decoupling capacitors to the VREF, REFT,
and REFB pins, use ceramic low ESR capacitors. These capacitors
should be close to the ADC pins and on the same layer of the
PCB as the AD9228. The recommended capacitor values and
configurations for the AD9228 reference pin can be found in
Figure 64.
0.1µF
SENSE
Voltage
AVDD
Resulting
VREF (V)
N/A
AGND to 0.2 V
1.0
Resulting
Differential
Span (V p-p)
2 × external
reference
2.0
Rev. 0 | Page 27 of 52
Figure 65. External Reference Operation
AD9228
0.20
External Reference Operation
0.10
5
–0.05
–0.10
–0.15
–0.20
–40
–20
0
20
40
Figure 67. Typical VREF Drift
–5
–10
–15
–20
–25
05727-083
VREF ERROR (%)
0
TEMPERATURE (°C)
0
–30
0.05
05727-084
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. The external
reference is loaded with an equivalent 6 kΩ load. An internal
reference buffer generates the positive and negative full-scale
references, REFT and REFB, for the ADC core. Therefore, the
external reference must be limited to a nominal of 1.0 V.
0.15
VREF ERROR (%)
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift characteristics. Figure 67 shows the typical drift characteristics of the
internal reference in 1 V mode.
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
CURRENT LOAD (mA)
Figure 66. VREF Accuracy vs. Load
Rev. 0 | Page 28 of 52
60
80
AD9228
SERIAL PORT INTERFACE (SPI)
The AD9228 serial port interface allows the user to configure
the converter for specific functions or operations through a
structured register space provided inside the ADC. This gives
the user added flexibility and customization depending on the
application. Addresses are accessed via the serial port and can
be written to or read from via the port. Memory is organized
into bytes that can be further divided down into fields, as documented in the Memory Map section. Detailed operational
information can be found in the Analog Devices user manual
Interfacing to High Speed ADCs via SPI.
There are three pins that define the serial port interface or SPI
to this particular ADC. They are the SCLK, SDIO, and CSB
pins. The SCLK (serial clock) is used to synchronize the read
and write data presented to the ADC. The SDIO (serial data
input/output) is a dual-purpose pin that allows data to be sent
to and read from the internal ADC memory map registers. The
CSB (chip select bar) is an active low control that enables or
disables the read and write cycles (see Table 13).
Table 13. Serial Port Pins
Pin
SCLK
SDIO
CSB
Function
Serial Clock. The serial shift clock in. SCLK is used to
synchronize serial interface reads and writes.
Serial Data Input/Output. A dual-purpose pin. The
typical role for this pin is an input or output, depending
on the instruction sent and the relative position in the
timing frame.
Chip Select Bar (Active Low). This control gates the read
and write cycles.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing sequence. During
an instruction phase, a 16-bit instruction is transmitted followed
by one or more data bytes, which is determined by Bit Fields
W0 and W1. An example of the serial timing and its definitions
can be found in Figure 68 and Table 14. In normal operation,
CSB is used to signal to the device that SPI commands are to be
received and processed. When CSB is brought low, the device
processes SCLK and SDIO to process instructions. Normally,
CSB remains low until the communication cycle is complete.
However, if connected to a slow device, CSB can be brought
high between bytes, allowing old microcontrollers enough time
to transfer data into shift registers. CSB can be stalled when
transferring one, two, or three bytes of data. When W0 and W1
are set to 11, the device enters streaming mode and continues
to process data, either reading or writing, until the CSB is taken
high to end the communication cycle. This allows complete
memory transfers without having to provide additional instructions. Regardless of the mode, if CSB is taken high in the
middle of any byte transfer, the SPI state machine is reset and
the device waits for a new instruction.
In addition to the operation modes, the SPI port can be
configured to operate in different manners. For applications
that do not require a control port, the CSB line can be tied and
held high. This places the remainder of the SPI pins in their
secondary mode as defined in the Serial Port Interface (SPI)
section. CSB can also be tied low to enable 2-wire mode. When
CSB is tied low, SCLK and SDIO are the only pins required for
communication. Although the device is synchronized during
power-up, caution must be exercised when using this mode to
ensure that the serial port remains synchronized with the CSB
line. When operating in 2-wire mode, it is recommended to use
a 1-, 2-, or 3-byte transfer exclusively. Without an active CSB
line, streaming mode can be entered but not exited.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip and read the contents
of the on-chip memory. If the instruction is a readback operation,
performing a readback causes the serial data input/output (SDIO)
pin to change direction from an input to an output at the
appropriate point in the serial frame.
Data can be sent in MSB- or LSB-first mode. MSB-first mode
is the default at power-up and can be changed by adjusting the
configuration register. For more information about this and
other features, see the user manual Interfacing to High Speed
ADCs via SPI.
HARDWARE INTERFACE
The pins described in Table 13 compose the physical interface
between the user’s programming device and the serial port of
the AD9228. The SCLK and CSB pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
This interface is flexible enough to be controlled by either serial
PROMS or PIC mirocontrollers. This provides the user an
alternative method, other than a full SPI controller, to program
the ADC (see the AN-812 Application Note).
If the user chooses not to use the SPI interface, these pins serve
a dual function and are associated with secondary functions
when the CSB is strapped to AVDD during device power-up.
See the Theory of Operation section for details on which pinstrappable functions are supported on the SPI pins.
Rev. 0 | Page 29 of 52
AD9228
tDS
tS
tHI
tCLK
tDH
tH
tLO
CSB
SCLK DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
05727-012
SDIO DON’T CARE
DON’T CARE
Figure 68. Serial Timing Details
Table 14. Serial Timing Definitions
Parameter
tDS
tDH
tCLK
tS
tH
tHI
tLO
Timing (minimum, ns)
5
2
40
5
2
16
16
Description
Set-up time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Set-up time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Rev. 0 | Page 30 of 52
AD9228
MEMORY MAP
READING THE MEMORY MAP TABLE
RESERVED LOCATIONS
Each row in the memory map table has eight address locations.
The memory map is roughly divided into three sections: chip
configuration register map (Address 0x00 to Address 0x02), device
index and transfer register map (Address 0x05 and Address 0xFF),
and program register map (Address 0x08 to Address 0x25).
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have a 0 written into their registers during power-up.
The left-hand column of the memory map indicates the register
address number in hexadecimal. The default value of this address is
shown in hexadecimal in the right-hand column. The Bit 7 (MSB)
column is the start of the default hexadecimal value given. For
example, Hexadecimal Address 0x09, Clock, has a hexadecimal
default value of 0x01. This means Bit 7 = 0, Bit 6 = 0, Bit 5 = 0,
Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001
in binary. This setting is the default for the duty cycle stabilizer in
the on condition. By writing a 0 to Bit 6 at this address, the duty
cycle stabilizer turns off. For more information on this and other
functions, consult the user manual Interfacing to High Speed
ADCs via SPI.
Coming out of reset, critical registers are preloaded with default
values. These values are indicated in Table 15, where an X refers
to an undefined feature.
DEFAULT VALUES
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Rev. 0 | Page 31 of 52
AD9228
Table 15. Memory Map Register
Addr.
Bit 7
(Hex)
Parameter Name (MSB)
Chip Configuration Registers
00
chip_port_config 0
01
chip_id
02
chip_grade
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB first
1 = on
0 = off
(default)
Soft
reset
1 = on
0 = off
(default)
1
1
Soft
reset
1 = on
0 = off
(default)
LSB first
1 = on
0 = off
(default)
Bit 0
(LSB)
Default
Value
(Hex)
0
0x18
8-bit Chip ID Bits 7:0
(AD9228 = 0x02), (default)
X
Child ID 6:4
(identify device variants of Chip ID)
000 = 65 MSPS,
001 = 40 MSPS
Device Index and Transfer Registers
05
device_index_A
X
X
FF
X
ADC Functions
08
modes
09
0D
0x02
X
X
X
X
Read
only
Data
Channel
B
1 = on
(default)
0 = off
X
Default Notes/
Comments
The nibbles
should be
mirrored so that
LSB- or MSB-first
mode registers
correctly
regardless of
shift mode.
Default is unique
chip ID, different
for each device.
This is a readonly register.
Child ID used to
differentiate
graded devices.
Clock
Channel
FCO
1 = on
0 = off
(default)
X
Data
Channel
D
1 = on
(default)
0 = off
X
Data
Channel
C
1 = on
(default)
0 = off
X
Data
Channel
A
1 = on
(default)
0 = off
SW
transfer
1 = on
0 = off
(default)
0x0F
Bits are set to
determine which
on-chip device
receives the next
write command.
X
Clock
Channel
DCO
1 = on
0 = off
(default)
X
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
X
X
X
X
X
0x00
Determines
various generic
modes of chip
operation.
clock
X
X
X
X
X
Internal power-down mode
000 = chip run (default)
001 = full power-down
010 = standby
011 = reset
X
X
Duty
cycle
stabilizer
1 = on
(default)
0 = off
0x01
Turns the
internal duty
cycle stabilizer
on and off.
test_io
User test mode
00 = off (default)
01 = on, single alternate
10 = on, single once
11 = on, alternate once
Reset PN
long gen
1 = on
0 = off
(default)
Reset
PN short
gen
1 = on
0 = off
(default)
Output test mode—see Table 9 in the
Digital Outputs and Timing section
0x00
When set, the
test data is
placed on the
output pins in
place of normal
data.
device_update
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checker board output
0101 = PN 23 sequence
0110 = PN 9
0111 = one/zero word toggle
1000 = user input
1001 = one/zero bit toggle
1010 = 1× sync
1011 = one bit high
1100 = mixed bit frequency
(format determined by output_mode)
Rev. 0 | Page 32 of 52
AD9228
Addr.
(Hex)
14
Parameter Name
output_mode
Bit 7
(MSB)
X
15
output_adjust
X
Bit 6
0 = LVDS
ANSI
(default)
1 = LVDS
low
power,
(IEEE
1596.3
similar)
X
16
output_phase
X
19
user_patt1_lsb
1A
Bit 5
X
Bit 4
X
Bit 0
(LSB)
Bit 1
00 = offset binary
(default)
01 = twos
complement
Default
Value
(Hex)
0x00
Bit 3
X
Bit 2
Output
invert
1 = on
0 = off
(default)
Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X
X
X
X
X
0x03
B7
B6
B5
B4
0011 = output clock phase adjust
(0000 through 1010)
(Default: 180° relative to DATA edge)
0000 = 0° relative to DATA edge
0001 = 60° relative to DATA edge
0010 = 120° relative to DATA edge
0011 = 180° relative to DATA edge
0100 = 240° relative to DATA edge
0101 = 300° relative to DATA edge
0110 = 360° relative to DATA edge
0111 = 420° relative to DATA edge
1000 = 480° relative to DATA edge
1001 = 540° relative to DATA edge
1010 = 600° relative to DATA edge
1011 to 1111 = 660° relative to DATA edge
B3
B2
B1
B0
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
0x00
1B
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
1C
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
0x00
21
serial_control
LSB first
1 = on
0 = off
(default)
X
X
X
000 = 12 bits (default, normal bit
stream)
001 = 8 bits
010 = 10 bits
011 = 12 bits
100 = 14 bits
0x00
22
serial_ch_stat
X
X
X
X
<10
MSPS,
low
encode
rate
mode
1 = on
0 = off
(default)
X
Channel
powerdown
1 = on
0 = off
(default)
0x00
Rev. 0 | Page 33 of 52
X
X
Channel
output
reset
1 = on
0 = off
(default)
X
0x00
0x00
Default Notes/
Comments
Configures the
outputs and the
format of the
data.
Determines
LVDS or other
output properties.
Primarily functions to set the
LVDS span and
common-mode
levels in place of
an external
resistor.
On devices that
utilize global
clock divide,
determines
which phase of
the divider
output is used to
supply the
output clock.
Internal latching
is unaffected.
User-defined
pattern, 1 LSB.
User-defined
pattern, 1 MSB.
User-defined
pattern, 2 LSB.
User-defined
pattern, 2 MSB.
Serial stream
control. Default
causes MSB first
and the native
bit stream
(global).
Used to power
down individual
sections of a
converter (local).
AD9228
Power and Ground Recommendations
Exposed Paddle Thermal Heat Slug Recommendations
When connecting power to the AD9228, it is recommended
that two separate 1.8 V supplies be used: one for analog (AVDD)
and one for digital (DRVDD). If only one supply is available, it
should be routed to the AVDD first and then tapped off and
isolated with a ferrite bead or a filter choke preceded by
decoupling capacitors for the DRVDD. The user can employ
several different decoupling capacitors to cover both high and
low frequencies. These should be located close to the point of
entry at the PC board level and close to the parts with minimal
trace length.
It is required that the exposed paddle on the underside of the
ADC is connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9228. An
exposed continuous copper plane on the PCB should mate to
the AD9228 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the PCB.
These vias should be solder filled or plugged.
A single PC board ground plane should be sufficient when
using the AD9228. With proper decoupling and smart partitioning of the PC board’s analog, digital, and clock sections,
optimum performance is easily achieved.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This provides
several tie points between the two during the reflow process.
Using one continuous plane with no partitions only guarantees
one tie point between the ADC and PCB. See Figure 69 for a
PCB layout example. For detailed information on packaging
and the PCB layout of chip scale packages, see the AN-772
Application Note, “A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP),” at www.analog.com.
05727-013
SILKSCREEN PARTITION
PIN 1 INDICATOR
Figure 69. Typical PCB Layout
Rev. 0 | Page 34 of 52
AD9228
EVALUATION BOARD
each section. At least one 1.8 V supply is needed with a 1 A current
capability for AVDD_DUT and DRVDD_DUT; however, it is
recommended that separate supplies be used for both analog
and digital. To operate the evaluation board using the VGA
option, a separate 5.0 V analog supply is needed. The 5.0 V
supply, or AVDD_5 V, should have a 1 A current capability. To
operate the evaluation board using the SPI and alternate clock
options, a separate 3.3 V analog supply is needed in addition to
the other supplies. The 3.3 V supply, or AVDD_3.3 V, should
have a 1 A current capability as well.
The AD9228 evaluation board provides all of the support circuitry required to operate the ADC in its various modes and
configurations. The converter can be driven differentially through a
transformer (default) or through the AD8332 driver. The ADC
can also be driven in a single-ended fashion. Separate power pins
are provided to isolate the DUT from the AD8332 drive circuitry.
Each input configuration can be selected by proper connection
of various jumpers (see Figure 72 to Figure 76). Figure 70 shows
the typical bench characterization setup used to evaluate the ac
performance of the AD9228. It is critical that the signal sources
used for the analog input and clock have very low phase noise
(<1 ps rms jitter) to realize the optimum performance of the
converter. Proper filtering of the analog input signal to remove
harmonics and lower the integrated or broadband noise at the
input is also necessary to achieve the specified noise performance.
INPUT SIGNALS
When connecting the clock and analog source, use clean signal
generators with low phase noise, such as Rohde & Schwarz SMHU
or HP8644 signal generators or the equivalent. Use a 1 m, shielded,
RG-58, 50 Ω coaxial cable for making connections to the evaluation board. Enter the desired frequency and amplitude from the
ADC specifications tables. Typically, most ADI evaluation boards
can accept ~2.8 V p-p or 13 dBm sine wave input for the clock.
When connecting the analog input source, it is recommended
to use a multipole, narrow-band, band-pass filter with 50 Ω
terminations. ADI uses TTE, Allen Avionics, and K&L types of
band-pass filters. The filter should be connected directly to the
evaluation board if possible.
See Figure 72 to Figure 80 for the complete schematics and
layout diagrams that demonstrate the routing and grounding
techniques that should be applied at the system level.
POWER SUPPLIES
This evaluation board comes with a wall-mountable switching
power supply that provides a 6 V, 2 A maximum output. Simply
connect the supply to the rated 100 V ac to 240 V ac wall outlet
at 47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter
jack that connects to the PCB at P503. Once on the PC board,
the 6 V supply is fused and conditioned before connecting to
three low dropout linear regulators that supply the proper bias
to each of the various sections on the board.
OUTPUT SIGNALS
The default setup uses the HSC-ADC-FPGA high speed
deserialization board to deserialize the digital output data and
convert it to parallel CMOS. These two channels interface
directly with the ADI standard dual-channel FIFO data capture
board (HSC-ADC-EVALA-DC). Two of the four channels can
then be evaluated at the same time. For more information on
channel settings on these boards and their optional settings,
visit www.analog.com/FIFO.
When operating the evaluation board in a nondefault condition,
L504 to L507 can be removed to disconnect the switching
power supply. This enables the user to bias each section of the
board individually. Use P501 to connect a different supply for
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
–
+
–
+
–
+
AVDD_3.3V
GND
3.3V_D
GND
1.5V_FPGA
GND
VCC
GND
3.3V
+
AD9228
EVALUATION BOARD
CLK
1.5V
–
GND
AVDD_5V
XFMR
INPUT
3.3V
3.3V
+
CHA–CHD
12-BIT
SERIAL
LVDS
HSC-ADC-FPGA
HIGH SPEED
DESERIALIZATION
BOARD 2 CH
SPI
Figure 70. Evaluation Board Connection
Rev. 0 | Page 35 of 52
12-BIT
PARALLEL
CMOS
SPI
HSC-ADC-EVALA-DC
FIFO DATA
CAPTURE
BOARD
USB
CONNECTION
SPI
PC
RUNNING
ADC
ANALYZER
AND SPI
USER
SOFTWARE
SPI
05727-014
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
BAND-PASS
FILTER
1.8V
–
DRVDD_DUT
–
GND
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
1.8V
+
+
GND
5.0V
–
SWITCHING
POWER
SUPPLY
AVDD_DUT
6V DC
2A MAX
AD9228
DEFAULT OPERATION AND JUMPER SELECTION
SETTINGS
50 Ω terminated and ac-coupled to handle single-ended
sine wave types of inputs. The transformer converts the
single-ended input to a differential signal that is clipped
before entering the ADC clock inputs.
The following is a list of the default and optional settings or
modes allowed on the AD9228 Rev. A evaluation board.
•
POWER: Connect the switching power supply that is
supplied in the evaluation kit between a rated 100 V ac
to 240 V ac wall outlet at 47 Hz to 63 Hz and P503.
•
AIN: The evaluation board is set up for a transformercoupled analog input with optimum 50 Ω impedance
matching out to 200 MHz (see Figure 71). For more
bandwidth response, the differential capacitor across the
analog inputs can be changed or removed. The common
mode of the analog inputs is developed from the center
tap of the transformer or AVDD_DUT/2.
A differential LVPECL clock can also be used to clock the
ADC input using the AD9515 (U202). Simply populate
R225 and R227 with 0 Ω resistors and remove R217 and
R218 to disconnect the default clock path inputs. In addition,
populate C207 and C208 with a 0.1 μF capacitor and remove
C210 and C211 to disconnect the default cloth path outputs.
The AD9515 has many pin-strappable options that are set
to a default working condition. Consult the AD9515 data
sheet for more information about these and other options.
If using an oscillator, two oscillator footprint options are
also available (OSC201) to check the ADC performance.
J205 gives the user flexibility in using the enable pin, which
is common on most oscillators.
0
–2
–3dB CUTOFF = 200MHz
AMPLITUDE (dBFS)
–4
•
PDWN: To enable the power-down feature, simply short
J201 to the on position (AVDD) on the PDWN pin.
•
SCLK/DTP: To enable one of the two digital test patterns
on the digital outputs of the ADC, use J204. If J204 is tied to
AVDD during device power-up, Test Pattern 1000 0000 0000
will be enabled. See the SCLK/DTP Pin section for details.
•
SDIO/ODM: To enable the low power, reduced signal option
similar to the IEEE 1595.3 reduced range link LVDS output
standard, use J203. If J203 is tied to AVDD during device
power-up, it enables the LVDS outputs in a low power,
reduced signal option from the default ANSI standard.
This option changes the signal swing from 350 mV p-p to
200 mV p-p, which reduces the power of the DRVDD supply.
See the SDIO/ODM Pin section for more details.
•
CSB: To enable the SPI information on the SDIO and
SCLK pins that is to be processed, simply tie J202 low in
the always enable mode. To ignore the SDIO and SCLK
information, tie J202 to AVDD.
•
D+, D−: If an alternative data capture method to the setup
described in Figure 72 is used, optional receiver terminations,
R206 to R211, can be installed next to the high speed backplane connector.
–6
–8
–10
–12
–16
05727-088
–14
0
50
100
150
200
250
300
350
400
450
500
FREQUENCY (MHz)
Figure 71. Evaluation Board Full Power Bandwidth
•
VREF: VREF is set to 1.0 V by tying the SENSE pin to
ground, R237. This causes the ADC to operate in 2.0 V p-p
full-scale range. A separate external reference option using
the ADR510 or ADR520 is also included on the evaluation
board. Simply populate R231 and R235 and remove C214.
Proper use of the VREF options is noted in the Voltage
Reference section.
•
RBIAS: RBIAS has a default setting of 10 kΩ (R201) to
ground and is used to set the ADC core bias current. To
further lower the core power (excluding the LVDS driver
supply), simply change the resistor setting. However,
performance of the ADC will degrade depending on the
resistor chosen. See RBIAS section for more information.
•
CLOCK: The default clock input circuitry is derived from a
simple transformer-coupled circuit using a high bandwidth
1:1 impedance ratio transformer (T201) that adds a very
low amount of jitter to the clock path. The clock input is
Rev. 0 | Page 36 of 52
AD9228
ALTERNATIVE ANALOG INPUT DRIVE
CONFIGURATION
The following is a brief description of the alternative analog
input drive configuration using the AD8332 dual VGA. If this
particular drive option is in use, some components may need to
be populated, in which case all the necessary components are
listed in Table 16. For more details on the AD8332 dual VGA,
including how it works and its optional pin settings, consult the
AD8332 data sheet.
To configure the analog input to drive the VGA instead of the
default transformer option, the following components need to
be removed and/or changed.
•
Remove R102, R115, R128, R141, T101, T102, T103, and
T104 in the default analog input path.
•
Populate R101, R114, R127, and R140 with 0 Ω resistors in
the analog input path.
•
Populate R106, R107, R119, R120, R132, R133, R144, and
R145 with 10 kΩ resistors to provide an input commonmode level to the analog input.
•
Populate R105, R113, R118, R124, R131, R137, R151, and
R160 with 0 Ω resistors in the analog input path.
Currently, L301 to L308 and L401 to L408 are populated with 0 Ω
resistors to allow signal connection. This area allows the user to
design a filter if additional requirements are necessary.
Rev. 0 | Page 37 of 52
AD9228
AVDD_DUT
R105
DNP
CH_A
P102
VGA INPUT CONNECTION DNP
INH1 AIN
CHANNEL A
R101
P101
DNP
AIN
R103
R102
0Ω
64.9Ω
C101
0.1µF
R104
0Ω
R152
DNP
FB102 R108
10Ω 33Ω
T101
6
1
R106
DNP
5
CM1 2
CM1
4
3
VIN_A
R161
499Ω C103
DNP
C104
2.2pF
R109
1kΩ
FB103 R110
33Ω
10Ω
C105
DNP
R156
DNP
R107
DNP
R113
FB101
DNP
10Ω C102
0.1µF CH_A
CM1
VIN_A
E101
AVDD_DUT
R111
1kΩ R112
1kΩ
C106
DNP
C107
0.1µF
AVDD_DUT
AVDD_DUT
CH_B
R153
DNP
FB105 R121
10Ω 33Ω
T102
6
1
FB104
10Ω C108
0.1µF
CM2
R117
0Ω
2
5
3
4
R162
499Ω C110
DNP
C111
2.2pF
R123
1kΩ
FB106 R122
33Ω
10Ω
C112
DNP
R157
DNP
CM2
R120
DNP
R124
C109
DNP
0.1µF CH_B
R116
0Ω
AIN
VIN_B
R119
DNP
VIN_B
CM2
E102
AVDD_DUT
P106
VGA INPUT CONNECTION DNP
INH3 AIN
CHANNEL C
R127
P105
DNP
AIN
R129
R128
0Ω
64.9Ω
R130
0Ω
C113
DNP
FB108 R134
10Ω 33Ω
6
R132
DNP
2
5
3
4
CM3
VIN_C
R163
499Ω C117
DNP
C118
2.2pF
R135
1kΩ
FB109 R136
33Ω
10Ω
C119
DNP
VIN_C
R158
DNP
R133
DNP
R137
FB107
DNP
10Ω C116
0.1µF CH_C
CM3
E103
AVDD_DUT
R138
1kΩ R139
1kΩ
VGA INPUT CONNECTION
INH4
CHANNEL D
R140
P107
DNP
AIN
R141
64.9Ω
C121
0.1µF
C120
DNP
AVDD_DUT
AVDD_DUT
CH_D
R151
DNP
R155
DNP
FB111 R146
10Ω 33Ω
T104
1
P108
DNP
AIN
R142
0Ω
FB110 C122
10Ω 0.1µF
CM4 2
3
6
R144
DNP
5
4
R160
R143
DNP
0Ω C123
0.1µF CH_D
CM4
CM4
VIN_D
R164
499Ω C124
DNP
C125
2.2pF
R148
1kΩ
FB112 R147
33Ω
10Ω
C126
DNP
R159
DNP
R145
DNP
VIN_D
E104
AVDD_DUT
AVDD_DUT
AVDD_DUT
R154
DNP
T103
1
CM3
C114
0.1µF
R131
DNP
CH_C
C115
0.1µF
R125
1kΩ R126
1kΩ
R149
1kΩ R150
1kΩ
C128
0.1µF
C127
DNP
DNP: DO NOT POPULATE
Figure 72. Evaluation Board Schematic, DUT Analog Inputs
Rev. 0 | Page 38 of 52
AVDD_DUT
05727-015
VGA INPUT CONNECTION
INH2
CHANNEL B
R114
P103
DNP
AIN
R115
64.9Ω
P104
DNP
R118
DNP
P201
ENCODE
INPUT
ENC
DNP
P203
CLOCK CIRCUIT
ENC
AVDD
AVDD
VIN–D
VIN+D
AVDD
AVDD
CLK–
CLK+
AVDD
AVDD
DRVDD
DRGND
C224
0.1µF
R216
0Ω
2
R201
10kΩ
C216
0.1µF
R218
0Ω
R217
0Ω
OPT_CLK
OPT_CLK
AVDD
AVDD
VIN–A
VIN+A
AVDD
PDWN
5
6
2
1
R221
10kΩ
U202
J202
J203
GND_PAD
1
CR201
HSMS2812
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
DNP: DO NOT POPULATE
DNP VREF = 0.5V(1+R232/R233)
R236
DNP
R237
0Ω
DNP
R235
DNP
3
3
3
23
C211
0.1µF
C210
0.1µF
R240
243Ω
C209
0.1µF
DNP
C208
0.1µF
DNP
1
1
CLK
E203
LVDS OUTPUT
E202
CLK
C217
0.1µF
C218
0.1µF
AVDD_3.3V
AVDD_3.3V
S10
AVDD_3.3V
S9
AVDD_3.3V
S8
AVDD_3.3V
S7
AVDD_3.3V
S6
VREF = 1V
VREF = EXTERNAL
LVPECL OUTPUT
C215
0.1µF
DNP
CLIP SINE OUT (DEFAULT)
CLK
R243
100Ω
R241
243Ω
R255
0Ω
R254
DNP
CLK
R253
0Ω
R251
0Ω
R249
0Ω
R247
0Ω
R245
0Ω
R252
DNP
R250
DNP
R248
DNP
R246
DNP
R244
DNP
C207
0.1µF
DNP
AVDD_3.3V
S5
AVDD_3.3V
S4
AVDD_3.3V
S3
AVDD_3.3V
S2
AVDD_3.3V
S1
AVDD_3.3V
S0
R242
100Ω
DTP ENABLE
ODM ENABLE
ALWAYS ENABLE SPI
PWDN ENABLE
SDO_CHB
CSB4_CHB
CSB3__CHB
SDI_CHB
SCLK_CHB
R265
0Ω
R263
0Ω
R261
0Ω
R259
0Ω
R257
0Ω
CHD
CHC
CHB
CHA
FCO
DCO
C219
0.1µF
C220
0.1µF
C221
0.1µF
NC = NO CONNECT
R264
DNP
R262
DNP
R260
DNP
R258
DNP
R256
DNP
VSENSE_DUT
VREF = 0.5V
DNP
R234
DNP
VREF SELECT
REMOVE C214 WHEN USING EXTERNAL VREF
C213
0.1µF R233
DNP
DNP
C214
1µF
R232
DNP
SDIO_ODM
J204 3
1
SCLK_DTP
1
J201
R230
10kΩ
VREF_DUT
R231
DNP
REFERENCE CIRCUIT
2 CLK
OUT0
22
3
CLKB
OUT0B
AD9515
SIGNAL=AVDD_3.3V;4,17,20,21,24,26,29,30
5
SYNCB
OUT1 19
SIGNAL=DNC;27,28
OUT1B 18
E201
R224
0Ω
R223
0Ω
R239
10kΩ
1
1
CSB_DUT
R202
100kΩ
AVDD_DUT
R228
470kΩ
C212
0.1µF
R229
4.99kΩ
OPTIONAL CLOCK DRIVE CIRCUIT
R222
4.02kΩ
AVDD_3.3V
AVDD_DUT
DRVDD_DUT
GND
AVDD_DUT
AVDD_DUT
VIN_A
VIN_A
AVDD_DUT
R226
49.9Ω
DNP
C206
0.1µF
R238
DNP
R220
DNP
T201
3
4
R227
0Ω
DNP
R225
0Ω
DNP
36
35
34
33
32
31
30
29
28
27
26
25
AVDD_3.3V
CSB
SDIO/ODM
SCLK/DTP
AVDD
DRVDD
DRGND
DISABLE
R219
R215
DNP
10kΩ
OPT_CLK
J205
ENABLE
R214
10kΩ
OPT_CLK
C205
0.1µF
CB3LV-3C
R213
49.9kΩ
VREF_DUT
VSENSE_DUT
AD9228LFCSP
OSC201
14 VCC
OE 1
12 VCC' OE' 3
10
5
OUT' GND'
8 OUT GND 7
R212
0Ω
DNP
C203
0.1µF
AVDD_3.3V
OPTIONAL CLOCK
OSCILLATOR
1
2
3
4
5
6
7
8
9
10
11
12
AVDD_3.3V
AVDD_DUT
AVDD_DUT
VIN_D
VIN_D
AVDD_DUT
AVDD_DUT
CLK
CLK
AVDD_DUT
AVDD_DUT
DRVDD_DUT
GND
U201
C201
0.1µF
VIN_C
VIN_C
C202
2.2µF
REFERENCE
DECOUPLING
AVDD_DUT
AVDD_DUT
C204
0.1µF
AVDD_DUT
VIN_B
VIN_B
48
47
46
45
44
43
42
41
40
39
38
37
AVDD_DUT
R205
10kΩ
VIN–C
VIN+C
AVDD
AVDD
REFT
REFB
VREF
SENSE
RBIAS
AVDD
VIN+B
VIN–B
D–D
D+D
D–C
D+C
D–B
D+B
D–A
D+A
FCO–
FCO+
DCO–
DCO+
CHD
CHD
R266
100kΩ - DNP
R203
100kΩ
RSET 32
CHC
CHC
CHB
CHB
CHA
CHA
FCO
FCO
R267
100kΩ - DNP
R204
100kΩ
2
Figure 73. Evaluation Board Schematic, DUT, VREF, Clock Inputs, and Digital Output Interface
3
1
1
13
14
15
16
17
18
19
20
21
22
23
24
U203
ADR510/20
1V
VOUT
TRIM/NC
2
VREF
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Rev. 0 | Page 39 of 52
3
33
2
VS 1
2
DCO
DCO
GND
2
GND 31
CW
6
7
8
9
10
11
12
13
14
15
16
25
AVDD_DUT
C3
GNDCD2
D3 43
44
45
46
47
48
49
50
A1
A2
A3
A4
A5
A6
A7
A8
A9
GNDAB1
GNDAB2
GNDAB3
GNDAB4
GNDAB5
GNDAB6
GNDAB7
GNDAB8
B1
B2
B3
B4
B5
B6
B7
B8
B9
11
12
13
14
15
16
17
18
19
C222
0.1µF
C223
0.1µF
R205–R211
OPTIONAL OUTPUT
TERMINATIONS
HEADERM1469169_1
1
2
21
3
22
4
23
5
24
25
6
26
7
27
8
28
9
29
51
D1 41
C1
31 GNDAB10
30
C10
B10 20
10
GNDAB9
52
32 C2GNDCD1 D2 42
33
53
P202
GNDCD10
60
D10
C10
GNDCD9
40
59
D9
C9
39
GNDCD8
58
D8
C8
38
GNDCD7
57
D7
C7
37
GNDCD6
56
D6
C6
36
GNDCD5
55
D5
C5
35
GNDCD4
54
D4
C4
34
GNDCD3
DIGITAL OUTPUTS
SDO_CHA
CSB2_CHA
CSB1_CHA
SDI_CHA
SCLK_CHA
CHD R211
DNP
CHC R210
DNP
CHB R209
DNP
CHA R208
DNP
R207
FCO DNP
DCO R206
DNP
05727-016
OPTIONAL
EXT REF
AD9228
CH_C
CH_C
CH_D
POPULATE L301-L308 WITH 0Ω
RESISTORS OR DESIGN YOUR
OWN FILTER.
CH_D
AD9228
R301
DNP
R302
DNP
L306 L307
0Ω
0Ω
16
15
14
13
12
11
10
9
C321
0.1µF
R314
10kΩ
DNP
VG
C313
0.1µF
C314
0.1µF
6
7
8
INH2
VPS2
LON2
RCLMP
GAIN
MODE
VCM2
VIN2
VIP2
COM2
LOP2
RCLAMP PIN
HILO PIN = LO = ±50mV
HILO PIN = H = ±75mV
AVDD_5V
19
18
17
VOL2
VOH2
COMM
20
LMD1
LMD2
4
5
R311
10kΩ
DNP
C310
0.1µF
R317
274Ω
C325
0.1µF
C326
10µF
C322
0.018µF
R318
10kΩ
C323
22pF
C318
22pF
L309
120nH
C319
0.1µF
DNP: DO NOT POPULATE
C309
1000pF
R310
187Ω
L310
120nH
C324
0.1µF
INH4
INH3
Figure 74. Evaluation Board Schematic, Optional DUT Analog Input Drive
Rev. 0 | Page 40 of 52
05727-017
C317
0.018µF
C320
0.1µF
C308
0.1µF
MODE PIN
POSITIVE GAIN SLOPE = 0-1.0V
NEGATIVE GAIN SLOPE = 2.25V-5.0V
R316
274Ω
NC
22
21
VOL1
VPSV
COMM
VOH1
1
2
3
C316
0.1µF
R309
187Ω
AVDD_5V
C315
10µF
AVDD_5V
R315
10kΩ
R306
374Ω
AD8332
LON1
VPS1
INH1
ENBV
ENBL
HILO
VCM1
VIN1
VIP1
COM1
LOP1
C312
0.1µF
R308
187Ω
24
23
R307
187Ω
25
26
27
28
29
30
31
32
C311
0.1µF
C306 C307
0.1µF 0.1µF
R305
374Ω
U301
C304
DNP L308
0Ω
R304
DNP
AVDD_5V
POWER DOWN ENABLE
(0-1V = DISABLE POWER)
AVDD_5V
C305
0.1µF
R312
10kΩ
R313
10kΩ
DNP
HILO PIN
HI GAIN RANGE = 2.25V-5.0V
LO GAIN RANGE = 0-1.0V
OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS C AND D
2
C303
L305 DNP
0Ω R303
DNP
EXTERNAL VARIABLE GAIN DRIVE
VG
VARIABLE GAIN CIRCUIT
(0-1.0V DC)
VG
GND
CW
AVDD_5V
R320
R319
39kΩ
10kΩ
JP301
C302
L302 L303 DNP L304
0Ω
0Ω
0Ω
1
C301
L301 DNP
0Ω
R414
10kΩ
C413
10µF
C410
0.1µF
C409
0.1µF
C414
0.1µF
R411
10kΩ
POWER DOWN ENABLE
(0–1V = DISABLE POWER)
OPTIONAL VGA DRIVE CIRCUIT FOR CHANNELS A AND B
25
26
27
28
29
30
31
32
CH_B
R407
187Ω
ENBV
ENBL
HILO
VCM1
VIN1
VIP1
COM1
LOP1
R408
187Ω
R405
374Ω
Figure 75. Evaluation Board Schematic, Optional DUT Analog Input Drive and SPI Interface (Continued)
L409
120nH
C416
0.1µF
INH2
C419
0.1µF
RCLMP
GAIN
MODE
VCM2
VIN2
VIP2
COM2
LOP2
C422
0.1µF
L410
120nH
C421
22pF
INH1
C417
0.1µF
VG
C412
0.1µF
R413
10kΩ
DNP
R424
10kΩ
DNP
DNP: DO NOT POPULATE
C426 R417
10µF 10kΩ
C424
0.1µF
C423
0.1µF
POPULATE L401-L408 WITH 0Ω
RESISTORS OR DESIGN YOUR
OWN FILTER.
C425
0.1µF
16
15
14
13
12
11
10
9
R410
187Ω
C411
1000pF
S401
3
4
RESET/REPROGRAM
1
2
C427
0.1µF
8
VSS
7
GP0
6
GP1
CR401
MCLR/
GP2 5
GP3
PIC12F629
R419
261Ω
4
1 VDD
2
GP5
3
GP4
U402
AVDD_5V
J402
AVDD_3.3V
7
8
9 10
C418
22pF
AD8332
R409
187Ω
R406
374Ω
C408
0.1µF
E401
+5V = PROGRAMMING = AVDD_5V
+3.3V = NORMAL OPERATION = AVDD_3.3V
MCLR/GP3
C415
0.018µF
R415
274Ω
C406 C407
0.1µF 0.1µF
L406 L407
0Ω
0Ω
C404
DNP L408
0Ω
R404
DNP
CH_B
C403
L405 DNP
0Ω R403
DNP
C405
0.1µF
U401
CH_A
R402
DNP
SPI CIRCUITRY FROM FIFO
CSB1_CHA
R423
0-DNP
R422
0-DNP
R421
0-DNP
R426
0Ω
C401
L401 DNP
0Ω
24
23
R430
10kΩ
R429
10kΩ
R425
10kΩ
SCLK_CHA
R428
0Ω
C402
L402 L403 DNP L404
0Ω
0Ω
0Ω
J401
PICVCC 1
2
GP1
3
4
GP0 5
6
05727-018
AVDD_5V
R412
10kΩ
DNP
HILO PIN
HI GAIN RANGE = 2.25V-5.0V
LO GAIN RANGE = 0-1.0V
20
NC
AVDD_5V
22
21
VOL1
VPSV
LMD1
LMD2
4
5
SDI_CHA
R420
0Ω
CH_A
19
18
17
VOL2
VOH2
COMM
INH2
VPS2
LON2
6
7
8
COMM
VOH1
LON1
VPS1
INH1
1
2
3
AVDD_5V
OPTIONAL
AVDD_5V
Rev. 0 | Page 41 of 52
R416
C420
0.018µF 274Ω
AVDD_5V
RCLAMP PIN
HILO PIN = LO = ±50mV
HILO PIN = H = ±75mV
MODE PIN
POSITIVE GAIN SLOPE = 0-1.0V
NEGATIVE GAIN SLOPE = 2.25V-5.0V
R418
4.75kΩ
VCC 5
Y2 4
U404
2 GND
3 A2
VCC 5
Y2 4
NC7WZ16
1 A1
Y1 6
U403
2 GND
3 A2
C428
0.1µF
SCLK_DTP
AVDD_DUT
CSB_DUT
C429
0.1µF
AVDD_DUT
R431
1kΩ
AVDD_DUT
SDIO_ODM
R433
1kΩ
AVDD_3.3V
REMOVE WHEN USING
OR PROGRAMMING PIC (U402)
R432
NC7WZ07
1kΩ
Y1 6
1 A1
SDO_CHA
R427
0Ω
R401
DNP
AD9228
PICVCC
GP1
GP0
MCLR/GP3
PIC PROGRAMMING HEADER
1
3
2
+
C501
10µF
3.3V_AVDD
DUT_DRVDD
P4 4
P5 5
P6 6
P7 7
3
INPUT
L501
10µH
L508
10µH
L502
10µH
L503
10µH
OUTPUT4
OUTPUT4
OUTPUT1
2
4
4
2
2
L505
10µH
C513
1µF
L504
10µH
AVDD_5V
+3.3V AVDD_3.3V
+1.8V AVDD_DUT
+5.0V
R501
261Ω
DUT_DRVDD
DUT_AVDD
C507
0.1µF
C534
1µF
PWR_IN
C532
1µF
PWR_IN
3
3
C517
0.1µF
C525
0.1µF
C527
0.1µF
C519
0.1µF
INPUT
2
OUTPUT4 4
OUTPUT1
2
OUTPUT4 4
OUTPUT1
ADP33339AKC-5
U504
INPUT
ADP33339AKC-3.3
U502
C516
0.1µF
C524
0.1µF
C526
0.1µF
C518
0.1µF
DECOUPLING CAPACITORS
CR501
PWR_IN
DRVDD_DUT +1.8V DRVDD_DUT
C509
0.1µF
AVDD_3.3V
C505
0.1µF
AVDD_DUT
C503
0.1µF
AVDD_5V
4
3
CHOKE_COIL
1
FER501
C515
1µF
C506
10µF
C508
10µF
C504
10µF
C502
10µF
D501
S2A_RECT
2A
DO-214AA
OUTPUT1
ADP33339AKC-1.8
U503
INPUT
ADP33339AKC-1.8
DNP: DO NOT POPULATE
C512
1µF
PWR_IN
C514
1µF
PWR_IN
3
DUT_AVDD
P2 2
P3 3
U501
5V_AVDD
P501
P1 1
P8 8
F501
SMDC110F
OPTIONAL POWER INPUT
P503
GND
1
GND
1
GND
1
Rev. 0 | Page 42 of 52
GND
Figure 76. Evaluation Board Schematic, Power Supply Inputs
1
D502
3A
SHOT_RECT
DO-214AB
C528
0.1µF
C520
0.1µF
C535
1µF
L507
10µH
C533
1µF
L506
10µH
H2
H1
H4
H3
C530
0.1µF
C522
0.1µF
C531
0.1µF
C523
0.1µF
5V_AVDD
3.3V_AVDD
MOUNTING HOLES
CONNECTED TO GROUND
C529
0.1µF
C521
0.1µF
05727-019
POWER SUPPLY INPUT
6V, 2V MAXIMUM
AD9228
05727-020
AD9228
Figure 77. Evaluation Board Layout, Primary Side
Rev. 0 | Page 43 of 52
05727-021
AD9228
Figure 78. Evaluation Board Layout, Ground Plane
Rev. 0 | Page 44 of 52
05727-022
AD9228
Figure 79. Evaluation Board Layout, Power Plane
Rev. 0 | Page 45 of 52
05727-023
AD9228
Figure 80. Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. 0 | Page 46 of 52
AD9228
Table 16. Evaluation Board Bill of Materials (BOM)
Item
1
2
Qnty.
per
Board
1
75
3
4
4
4
5
REFDES
AD9228LFCSP_REVA
C101, C102, C107,
C108, C109, C114,
C115, C116, C121,
C122, C123, C128,
C201, C203, C204,
C205, C206, C210,
C211, C212, C213,
C216, C217, C218,
C219, C220, C221,
C222, C223, C224,
C310, C311, C312,
C313, C314, C316,
C319, C320, C321,
C324, C325, C409,
C410, C412, C414,
C416, C417, C419,
C422, C423, C424,
C425, C427, C428,
C429, C503, C505,
C507, C509, C516,
C517, C518, C519,
C520, C521, C522,
C523, C524, C525,
C526, C527, C528,
C529, C530, C531
C104, C111, C118,
C125
Device
PCB
Capacitor
Pkg.
PCB
402
Value
PCB
0.1 μF, ceramic,
X5R, 10 V, 10% tol
Mfg.
Mfg. Part Number
Panasonic
ECJ-0EB1A104K
Capacitor
402
Murata
GRM1555C1H2R2GZ01B
Capacitor
805
AVX
08056D106KAT2A
1
C315, C326, C413,
C426
C202
Capacitor
603
Panasonic
ECJ-1VB0J225K
6
2
C309, C411
Capacitor
402
Kemet
C0402C102K3RACTU
7
4
Capacitor
402
AVX
0402YC183KAT2A
8
4
Capacitor
402
Kemet
C0402C220J5GACTU
9
1
C317, C322, C415,
C420
C318, C323, C418,
C421
C501
Capacitor
1206
Rohm
TCA1C106M8R
10
9
Capacitor
603
2.2 pF, ceramic,
COG, 0.25 pF tol,
50 V
10 μF, 6.3 V ±10%
ceramic, X5R
2.2 μF, ceramic,
X5R, 6.3 V, 10% tol
1000 pF, ceramic,
X7R, 25 V, 10% tol
0.018 μF, ceramic,
X7R, 16 V, 10% tol
22 pF, ceramic,
NPO, 5% tol, 50 V
10 μF, tantalum,
16 V, 20% tol
1 μF, ceramic, X5R,
6.3 V, 10% tol
Panasonic
ECJ-1VB0J105K
11
8
Capacitor
805
0.1 μF, ceramic,
X7R, 50 V, 10% tol
AVX
08055C104KAT2A
12
4
Panasonic
ECJ-1VB0J106M
13
Agilent
Technologies
Panasonic
HSMS2812
Micro
Commercial Co.
Micro
Commercial Co.
SK33MSCT
Capacitor
603
1
C214, C512, C513,
C514, C515, C532,
C533, C534, C535
C305, C306, C307,
C308, C405, C406,
C407, C408
C502, C504, C506,
C508
CR201
Diode
SOT-23
14
2
CR401, CR501
LED
603
15
1
D502
Diode
DO-214AB
10 μF, ceramic,
X5R, 6.3 V, 20% tol
30 V, 20 mA, dual
Schottky
Green, 4 V, 5 m
candela
3 A, 30 V, SMC
16
1
D501
Diode
DO-214AA
2 A, 50 V, SMC
Rev. 0 | Page 47 of 52
LNJ306G8TRA
S2A
AD9228
Item
17
Qnty.
per
Board
1
REFDES
F501
Device
Fuse
Pkg.
1210
18
1
FER501
Choke Coil
2020
19
12
Ferrite bead
603
20
1
FB101, FB102, FB103,
FB104, FB105, FB106,
FB107, FB108, FB109,
FB110, FB111, FB112
JP301
Connector
2-pin
21
2
J205, J402
Connector
3-pin
22
1
J201 to J204
Connector
12-pin
23
1
J401
Connector
10-pin
24
8
L501, L502, L503, L504,
L505, L506, L507, L508
Ferrite bead
1210
25
4
L309, L310, L409, L410
Inductor
402
26
16
Resistor
805
27
1
L301, L302, L303, L304,
L305, L306, L307, L308,
L401, L402, L403, L404,
L405, L406, L407, L408
OSC201
Oscillator
SMT
28
5
P101, P103, P105,
P107, P201
Connector
SMA
29
1
P202
Connector
HEADER
30
1
P503
Connector
0.1", PCMT
31
15
Resistor
402
32
14
Resistor
402
33
4
Resistor
402
34
4
R201, R205, R214,
R215, R221, R239,
R312, R315, R318,
R411, R414, R417,
R425, R429, R430
R103, R117, R129,
R142, R216, R217,
R218, R223, R224,
R237, R420, R426,
R427, R428
R102, R115, R128,
R141
R104, R116, R130,
R143
Resistor
603
Value
6.0 V, 2.2 A tripcurrent resettable
fuse
10 μH, 5 A, 50 V,
190 Ω @ 100 MHz
10 Ω, test freq
100 MHz, 25% tol,
500 mA
Mfg.
Tyco/Raychem
Mfg. Part Number
NANOSMDC110F-2
Murata
DLW5BSN191SQ2L
Murata
BLM18BA100SN1
100 mil header
jumper, 2-pin
100 mil header
jumper, 3-pin
100 mil header
male, 4 × 3 triple
row straight
100 mil header,
male, 2 × 5 double
row straight
10 μH, bead core
3.2 × 2.5 × 1.6
SMD, 2 A
120 nH, test freq
100 MHz, 5% tol,
150 mA
0 Ω, 1/8 W, 5% tol
Samtec
TSW-102-07-G-S
Samtec
TSW-103-07-G-S
Samtec
TSW-104-08-G-T
Samtec
TSW-105-08-G-D
Panasonic-ECG
EXC-CL3225U1
Murata
LQG15HNR12J02B
Panasonic
ERJ-6GEY0R00V
CTS REEVES
CB3LV-3C-65M0000-T
Johnson
Components
142-0711-821
Tyco
1469169-1
Switchcraft
SC1153
Panasonic
ERJ-2GEJ103X
0 Ω, 1/16 W,
5% tol
Panasonic
ERJ-2GE0R00X
64.9 Ω, 1/16 W,
1% tol
0 Ω, 1/10 W,
5% tol
Panasonic
ERJ-2RKF64R9X
Panasonic
ERJ-3GEY0R00V
Clock oscillator,
65.00 MHz, 3.3 V
Side-mount SMA
for 0.063" board
thickness
1469169-1, right
angle 2-pair,
25 mm, header
assembly
RAPC722, power
supply connector
10 kΩ, 1/16 W,
5% tol
Rev. 0 | Page 48 of 52
AD9228
Item
35
Qnty.
per
Board
15
36
8
37
4
38
3
REFDES
R109, R111, R112,
R123, R125, R126,
R135, R138, R139,
R148, R149, R150,
R431, R432, R433
R108, R110, R121,
R122, R134, R136,
R146, R147
R161, R162, R163,
R164
R202, R203, R204
Device
Resistor
Pkg.
402
Value
1 kΩ, 1/16 W,
1% tol
Mfg.
Panasonic
Mfg. Part Number
ERJ-2RKF1001X
Resistor
402
33 Ω, 1/16 W, 5%
tol
Panasonic
ERJ-2GEJ330X
Resistor
402
Panasonic
ERJ-2RKF4990X
Resistor
402
Panasonic
ERJ-2RKF1003X
R222
Resistor
402
Panasonic
ERJ-2RKF4021X
1
R213
Resistor
402
Susumu
RR0510R-49R9-D
41
1
R229
Resistor
402
Panasonic
ERJ-2RKF4991X
42
2
R230, R319
Potentiometer
3-lead
BC
Components
CT-94W-103
43
1
R228
Resistor
402
Yageo America
9C04021A4703JLHF3
44
1
R320
Resistor
402
Susumu
RR0510P-393-D
45
8
Resistor
402
Panasonic
ERJ-2RKF1870X
46
4
Resistor
402
ERJ-2RKF3740X
4
Resistor
402
Panasonic
ERJ-2RKF2740X
48
11
Resistor
201
374 Ω, 1/16 W,
1% tol
274 Ω, 1/16 W,
1% tol
0 Ω, 1/20 W, 5% tol
Panasonic
47
Panasonic
ERJ-1GE0R00C
49
4
R307, R308, R309,
R310, R407, R408,
R409, R410
R305, R306, R405,
R406
R316, R317, R415,
R416
R245, R247, R249,
R251, R253, R255,
R257, R259, R261,
R263, R265
R418
499 Ω, 1/16 W,
1% tol
100 kΩ, 1/16 W,
1% tol
4.02 kΩ, 1/16 W,
1% tol
49.9 Ω, 1/16 W,
0.5% tol
4.99 kΩ, 1/16 W,
5% tol
10 kΩ, Cermet
trimmer
potentiometer,
18 turn top adjust,
10%, 1/2 W
470 kΩ, 1/16 W,
5% tol
39 kΩ, 1/16 W,
5% tol
187 Ω, 1/16 W,
1% tol
39
1
40
Resistor
402
Panasonic
ERJ-2RKF4751X
50
1
R419
Resistor
402
Panasonic
ERJ-2RKF2610X
51
1
R501
Resistor
603
Panasonic
ERJ-3EKF2610V
52
2
R240, R241
Resistor
402
Panasonic
ERJ-2RKF2430X
53
2
R242, R243
Resistor
402
Panasonic
ERJ-2RKF1000X
54
1
S401
Switch
SMD
Panasonic
EVQ-PLDA15
55
5
T101, T102, T103, T104,
T201
Transformer
CD542
Mini-Circuits
ADT1-1WT
56
2
U501, U503
IC
SOT-223
4.75 kΩ, 1/16 W,
1% tol
261 Ω, 1/16 W,
1% tol
261 Ω, 1/16 W,
1% tol
243 Ω, 1/16 W,
1% tol
100 Ω, 1/16 W,
1% tol
LIGHT TOUCH,
100GE, 5 mm
ADT1-1WT, 1:1
impedance ratio
transformer
ADP33339AKC-1.8,
1.5 A, 1.8 V LDO
regulator
ADI
ADP33339AKC-1.8
Rev. 0 | Page 49 of 52
AD9228
Item
57
Qnty.
per
Board
2
REFDES
U301, U401
Device
IC
Pkg.
LFCSP,
CP-32
58
59
60
1
1
1
U504
U502
U201
IC
IC
IC
SOT-223
SOT-223
LFCSP,
CP-48-1
61
1
U203
IC
SOT-23
62
1
U202
IC
63
1
U403
IC
64
1
U404
IC
65
1
U402
IC
LFCSP
CP-32-2
SC70,
MAA06A
SC70,
MAA06A
8-SOIC
Value
AD8332ACP,
ultralow noise
precision dual
VGA
ADP33339AKC-5
ADP33339AKC-3.3
AD9228-65, quad,
12-bit, 65 MSPS
serial LVDS 1.8 V
ADC
ADR510AR, 1.0 V,
precision low
noise shunt
voltage reference
AD9515
Mfg.
ADI
Mfg. Part Number
AD8332ACP
ADI
ADI
ADI
ADP33339AKC-5
ADP33339AKC-3.3
AD9228BCPZ-65
ADI
ADR510AR
ADI
AD9515BCPZ
NC7WZ07
Fairchild
NC7WZ07P6X
NC7WZ16
Fairchild
NC7WZ16P6X
Flash prog
mem 1kx14,
RAM size 64 × 8,
20 MHz speed,
PIC12F controller
series
Microchip
PIC12F629-I/SN
Rev. 0 | Page 50 of 52
AD9228
OUTLINE DIMENSIONS
7.00
BSC SQ
0.60 MAX
0.60 MAX
37
36
PIN 1
INDICATOR
TOP
VIEW
48
1
5.25
5.10 SQ
4.95
(BOTTOM VIEW)
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
12° MAX
PIN 1
INDICATOR
EXPOSED
PAD
6.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
0.30
0.23
0.18
0.05 MAX
0.02 NOM
0.50 BSC
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 81. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9228BCPZ-40 1
AD9228BCPZRL-401
AD9228BCPZ-651
AD9228BCPZRL-651
AD9228-65EB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape and Reel
Evaluation Board
Z = Pb-free part.
Rev. 0 | Page 51 of 52
Package Option
CP-48-1
CP-48-1
CP-48-1
CP-48-1
AD9228
NOTES
©2006 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05727–0–4/06(0)
Rev. 0 | Page 52 of 52

Open as PDF

Similar pages: AD AD9252BCPZRL7-50; AD AD9222BCPZ-40; AD AD9212BCPZRL7-40; AD AD9252ABCPZ-50; AD AD9212ABCPZ-40; AD AD9637BCPZ-80; AD9257 (Rev. A) - Analog Devices; AD AD9254; AD AD9246BCPZ-105; AD AD9601; AD AD9239; AD AD9626BCPZ-250; AD AD9253BCPZ-80; AD AD9633BCPZ-125; AD AD9271BSVZ-50; AD AD9639; AD AD9467BCPZRL7-250; AD AD9230BCPZ-210; AD AD9251BCPZRL7-65; AD AD9434BCPZRL7-370; AD AD6672BCPZRL7-250; AD AD9642BCPZ-210