LTC3415 - 7A, PolyPhase Synchronous Step-Down Regulator

LTC3415
7A, PolyPhase
Synchronous Step-Down
Regulator
DESCRIPTION
FEATURES
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High Efficiency: Up to 96%
7A Output Current at VIN = 3V
Adjustable Frequency: 1.5MHz Nominal
PolyPhase Operation (Up to 12 Phases)
Spread Spectrum Frequency Modulation
Output Tracking and Margining
±1% Reference Accuracy
2.5V to 5.5V VIN Range
Phase Lockable from 0.75MHz to 2.25MHz
Selectable Burst Mode® Operation
Low Dropout Operation: 100% Duty Cycle
Low Quiescent Current: 450μA
Current Mode Operation for Excellent Line and Load
Transient Response
Shutdown Mode Draws Only 0.2μA Supply Current
Available in 38-Pin (5mm × 7mm) QFN Package
APPLICATIONS
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Point of Load Power Supply
Portable Instruments
Distributed Power Systems
Battery-Powered Equipment
The LTC®3415 is a high efficiency, monolithic synchronous
buck regulator using a phase lockable constant frequency,
current mode architecture. PolyPhase® operation allows
multiple LTC3415s to run out of phase while using minimal input and output capacitance. The operating supply
range is from 5.5V down to 2.5V, making it suitable for
single Lithium-Ion battery as well as point of load power
supply applications. Burst Mode operation provides high
efficiency at low load currents. 100% duty cycle provides
low dropout operation that extends operating time in battery-operated systems.
The operating frequency is internally set at 1.5MHz, allowing the use of small surface mount inductors. For
switching-noise sensitive applications, it can be externally
synchronized from 0.75MHz to 2.25MHz. The PHMODE
pin allows user control of the phase of the outgoing clock
signal. The current sense comparator is factory trimmed
for accurate output current sharing. Burst Mode operation
is inhibited during synchronization or when the MODE pin
is pulled low to reduce noise and RF interference.
, LT, LTC, LTM, Burst Mode and PolyPhase are registered trademarks of Linear
Technology Corporation. All other trademarks are the property of their respective owners.
Protected by U.S. Patents, including 5481178, 6580258, 6304066, 6127815, 6498466,
6611131.
TYPICAL APPLICATION
VIN, 2.5V to 5.5V
SVIN
CLKIN
PVIN
Efficiency and Power Loss
SW
22μF
x3
SW
PLLLPF
SW
LTC3415
SW
VOUT
1.8V
0.2μH
TRACK
FB
EFFICIENCY
1
60
0.1
50
40
POWER LOSS
30
MODE
0.01
20
PGOOD
ITH
47μF
x3
EFFICIENCY (%)
PHMODE
70
SGND
10
0
0.01
PGND
120k
3415 TA01
POWER LOSS (W)
80
RUN
10
90
SW
CLKOUT
60k
100
0.1
1
LOAD CURRENT (A)
2.5V
3.3V
5V 0.001
10
3415 TA01B
Figure 1. High Efficiency Step-Down Converter
3415fa
1
LTC3415
PIN CONFIGURATION
SVIN, PVIN Voltage ....................................... –0.3V to 6V
PLLLPF, PGOOD Voltages .............................–0.3V to VIN
CLKIN, PHMODE, MODE Voltages ...............–0.3V to VIN
CLKOUT Voltage .......................................... –0.3V to 2V
ITH, ITHM, VFB, TRACK Voltages ....................–0.3V to VIN
MGN, BSEL, RUN Voltages ..........................–0.3V to VIN
SW Voltage (DC) ............................–0.3V to (VIN + 0.3V)
Peak SW Sink and Source Current ............................15A
Operating Ambient Temperature
Range (Note 2)......................................... –40°C to 85°C
Junction Temperature (Note 5) ............................. 125°C
Storage Temperature.............................. –65°C to 125°C
ITH
ITHM
SVIN
PVIN
CLKOUT
TOP VIEW
PVIN
(Note 1)
RUN
ABSOLUTE MAXIMUM RATINGS
38 37 36 35 34 33 32
NC 1
31 NC
SGND 2
30 TRACK
PLLLPF 3
29 VFB
PVIN 4
28 PVIN
PVIN 5
27 PVIN
SW 6
26 SW
39
SW 7
25 SW
SW 8
24 SW
SW 9
23 SW
MODE 10
22 PGOOD
CLKIN 11
21 BSEL
20 MGN
PHMODE 12
PGND
PGND
PGND
PGND
PGND
PGND
PGND
13 14 15 16 17 18 19
UHF PACKAGE
38-LEAD (7mm × 5mm) PLASTIC QFN
TJMAX = 125°C, θJA = 34°C/W, θJC = 1.1°C/W
EXPOSED PAD (PIN 39) IS PGND
MUST BE SOLDERED TO PCB
ORDER INFORMATION
LEAD FREE FINISH
TAPE AND REEL
PART MARKING
PACKAGE DESCRIPTION
TEMPERATURE RANGE
LTC3415EUHF#PBF
LTC3415EUHF#TRPBF
3415
38-Lead (5mm × 7mm) QFN Package
–40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
SVIN
Signal Input Voltage Range
VFB
Regulated Feedback Voltage
(Note 3)
ΔVFB
Reference Voltage Line Regulation
VIN = 2.5V to 5.5V (Note 3)
VLOADREG
Output Voltage Load Regulation
ΔVPGOOD
Power Good Range
RPGOOD
Power Good Pull-Down Resistance
CONDITIONS
MIN
TYP
2.375
Measured in Servo Loop, VITH = 0.3V
Measured in Servo Loop, VITH = 0.9V
l
0.590
l
l
±7
1mA Load, VIN = 3.3V
MAX
UNITS
5.5
V
0.596
0.602
V
0.15
0.3
%/V
0.1
–0.05
0.2
–0.2
%
%
±10
±13
%
25
40
Ω
3415fa
2
LTC3415
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VIN = 3.3V unless otherwise specified.
SYMBOL
PARAMETER
CONDITIONS
MIN
IQ
Input DC Bias Current
Active Current
Sleep
Shutdown
(Note 4)
VFB = 0.57V, MODE = 0V
VFB = 0.63V, MODE = VIN
VRUN = 0V
1.3
TYP
MAX
UNITS
1350
450
0.2
μA
μA
μA
5
1.5
1.7
MHz
fOSC
Switching Frequency
fSYNC
SYNC Capture Range
2.25
MHz
RPFET
RDS(ON) of P-Channel FET
ISW = 100mA
32
40
mΩ
RNFET
RDS(ON) of N-Channel FET
ISW = 100mA
25
32
mΩ
ILIMIT
Peak Current Limit
VITH = 1V (Note 6)
11
13
15
A
VUVLO
Undervoltage Lockout Threshold
SVIN Rising
SVIN Falling
2.05
1.85
2.2
2.0
2.35
2.15
V
V
ILSW
SW Leakage Current
VRUN = 0V, VIN = 5.5V
0.1
5
μA
0.75
SS Delay
Internal Soft-Start Delay
gm
Error Amplifier’s Transconductance
140
RUN
Run Input Threshold
PGOOD Delay
PGOOD Falling Edge Delay
%MARGINING
Output Voltage Margining Percentage
MGN HI, BSEL LOW
MGN HI, BSEL HI
MGN HI, BSEL = SVIN/2
MGN LOW, BSEL LOW
MGN LOW, BSEL HI
MGN LOW, BSEL = SVIN/2
TRACK
Tracking Threshold (Rising)
Tracking Threshold (Falling)
Tracking Disable Threshold
RUN = VIN
RUN = 0V
VFB Slavemode
RUN Rising
RUN Falling
μs
1.7
2
2.2
mmho
1.4
1.2
1.5
1.3
1.6
1.4
V
V
35
3
8
13
–3
–8
–13
5
10
15
–5
–10
–15
μs
7
12
17
–7
–12
–17
%
%
%
%
%
%
0.57
0.18
VIN – 0.5
V
V
V
VFB Slavemode (EA Disable) Threshold
VIN – 0.5
V
ITH Internal
Switch Over Threshold for Internal
Compensation
VIN – 0.5
V
OV
Output Overvoltage Threshold
VFB Rising
7
10
13
%
–7
–10
–13
%
1
3
%
UV
Output Undervoltage Threshold
VFB Falling
VHYST
OV/UV Hysteresis
VFB Returning to Regulation
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTC3415E is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls.
Note 3: The LTC3415 is tested in a feedback loop that adjusts VFB to
achieve a specified error amplifier output voltage (ITH).
Note 4: Dynamic supply current is higher due to the internal gate charge
being delivered at the switching frequency.
Note 5: TJ is calculated from the ambient temperature TA and power
dissipation as follows: LTC3415: TJ = TA + PD (34°C/W).
Note 6: Current Limit is measured with internal servo loop while forcing
VITH = 1V.
Note 7: This IC includes overtemperature protection that is intended
to protect the device during momentary overload conditions. Junction
temperature will exceed 125°C when overtemperature protection is active.
Continuous operation above the specified maximum operating junction
temperature may impair device reliability.
3415fa
3
LTC3415
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss vs
Load Current (3 Operating Modes)
(Reference Figure 13)
100
VOUT = 1.8V
VIN = 3.3V
40
1.4
35
0.1
50
40
% (Burst)
% (PSKIP)
% (FC)
W (Burst)
W (PSKIP)
W (FC)
30
20
10
0
0.001
0.01
0.1
1
LOAD CURRENT (A)
0.01
1.2
VO = 1.2V PULSE SKIP
ON-RESISTANCE (mΩ)
EFFICIENCY (%)
60
POWER LOSS (mW)
1
70
1.0
0.8
0.6
VO = 1.2V BURST MODE
0.4
0.2
0.001
10
0
3
2.5
3.5
4
4.5
INPUT VOLTAGE (V)
3415 G01
25
NFET
20
15
10
5
0
2.25
5.5
3415 G03
Load Regulation
(Reference Figure 13)
3.25
4.25
INPUT VOLTAGE (V)
5.25
3415 G04
Load Step
(Reference Figure 13)
0.5
40
FC MODE
VIN = 3.3V
VOUT = 1.8V
0.4
35
0.3
LOAD REGULATION (%)
POWER PMOS
30
25
POWER NMOS
VOUT
(AC)
100mV/
DIV
0.2
0.1
IL 5A/
DIV
0
–0.1
IOUT
5A/DIV
–0.2
–0.3
20
–0.4
15
–100
30
5
RDSON vs Temperature
RDSON (mΩ)
RDSON vs VIN
1.6
PFET
80
SUPPLY CURRENT (mA)
90
Supply Current vs VIN
10
VIN = 3.3V
VOUT = 1.8V
–0.5
–50
100
0
50
TEMPERATURE (°C)
150
0
1
2
3
6
4
5
LOAD CURRENT (A)
7
3415 G05
3415 G08
Efficiency and Power Loss vs Load
Current Force Continuous Mode
100
2.0
90
10
VOUT = 1.8V
80
EFFICIENCY (%)
1.8
1.6
1.4
70
EFFICIENCY
1
60
50
40
30
POWER LOSS
20
1.2
10
–50
0
50
100
TEMPERATURE (°C)
150
3415 G11
0
0.01
0.1
1
LOAD CURRENT (A)
0.1
POWER LOSS (mW)
OSCILLATOR FREQUENCY (MHz)
8
3415 G06
Oscillator Frequency
vs Temperature
1.0
–100
40μs/DIV
FORCED CONTINUOUS
ILOAD = 0.1A TO 5A
2.5V
3.3V
5V 0.01
10
3415 G02
3415fa
4
LTC3415
TYPICAL PERFORMANCE CHARACTERISTICS
Efficiency and Power Loss
Burst Mode Operation
80
100
EFFICIENCY
1
60
50
0.1
40
POWER LOSS
30
10
0
0.01
0.1
1
LOAD CURRENT (A)
70
1
60
50
40
0.1
30
0.01
20
EFFICIENCY
80
POWER LOSS
20
2.5V
3.3V
5V 0.001
10
0.1
1
LOAD CURRENT (A)
3415 G09
3415 G10
Switch Leakage Current
vs Input Voltage
Output Tracking
200
VOUT2 =
3.3V/7A
500mV/DIV
VOUT1 =
1.8V/14A
500mV/DIV
500μs/DIV
2.5V
3.3V
5V 0.01
10
10
0
0.01
POWER LOSS (mW)
70
10
VOUT = 1.8V
90
POWER LOSS (mW)
EFFICIENCY (%)
10
VOUT = 1.8V
EFFICIENCY (%)
90
175
LEAKAGE CURRENT (nA)
100
Efficiency and Power Loss
Pulse-Skip Mode Operation
150
125
MAIN SWITCH
100
75
50
3415 G07
SYNCHRONOUS
SWITCH
25
0
2.5
3
4
3.5
4.5
5
INPUT VOLTAGE (V)
5.5
6
3415 G12
3415fa
5
RUN
37
1.5V
THERMAL
SHDN
RUN
COMP
SVIN
EA
0.66V
0.54V
OVDET
UVDET
MODE
10
OV
UV
EA DISABLE
+
–
+
–
PGOOD
22
EXT/INT
COMP
0.2V
ITHBUF
HIGH BURST-EN
LOW FORCE-CONT.
FLOAT PULSE-SKIP
MODE FUNCTION
IMAX + SLOPE
CLAMP
1.5V CLAMP
OSC
VIN –0.5V
32
ITH
VFB
COMP
+
ITH
BUFFER
–
SLOPE
COMP
SGND
(GM = 2M )
VIN –0.5V
INT. SS
18MHz/12
OSC
SPREAD
SPECTRUM
SHUTDOWN
INT.
SHDN
29
VFB
33
ITHMINUS
CLKOUT
38
PHMODE
12
2V TO 2.2V
UVLO
TRACK
FALLING
COMP
+
–
–
0.18V
21
MARGINING
MUX
0.1ms
INTERNAL SS
0.66V
0.63V
0.6V
0.57V
0.54V
+
TRACK
30
20
MGN BSEL
HIGH 180° (2-PHASE)
LOW 120° (3-PHASE)
FLOAT 90° (4-PHASE)
PHMODE CLKOUT
HIGH SPR
LOW FREE-RUN
SYNC PLL-SYNC
CLKIN FUNCTION
2
INTVCC
GENERATOR
–
+
–
+
+
–
PLLLPF
3
V1P8
Ω
PLL
34
Q
Q
RS LATCH
R
S
BURST
50mV
EN
SWITCHING
LOGIC
AND
BLANKING
CIRCUIT
SLEEP
20% PEAK
BURST CLAMP
NICMP
IRCMP
ANTISHOOTTHRU
ICOMP
+
+
–
–
–
6
+
CLKIN
11
SVIN
+
–
–
+
BG
TG
COMP FOR SHORT-CIRCUIT PROTECTION
CHECKS INDUCTOR CURRENT ZERO CROSSING
–
+
3415 FD
PGND
13,14,15,16,17,18,19
0.025Ω
SW
6,7,8,9,23,24,25,26
0.032Ω
PVIN
4,5,27,28,35,36
LTC3415
FUNCTIONAL DIAGRAM
3415fa
LTC3415
PIN FUNCTIONS
SGND (Pin 2): Signal Ground. Return ground path for
all analog and low power circuitry. Single connection to
PGND on system board.
BSEL (Pin 21): Margining Bit Select Pin. Tying BSEL low
selects ±5%, tying it high selects ±10%. Tying it to VIN/2
selects ±15%.
PLLLPF (Pin 3): Phase-Locked-Loop Lowpass Filter. The
PLL’s lowpass filter is tied to this pin. In spread spectrum
mode, placing a capacitor here to SGND controls the slew
rate from one frequency to the next. Alternatively, floating
this pin allows normal running frequency at 1.5MHz, tying
this pin to SVIN forces the part to run at 1.33 times its normal
frequency (2MHz), tying it to ground forces the frequency
to run at 0.67 times its normal frequency (1MHz).
PGOOD (Pin 22): Output Power GOOD with Open-Drain
Logic. PGOOD is pulled to ground when the voltage on
the VFB pin is not within ±10% of its set point. Disabled
during margining and during slave mode operation (VFB
tied to VIN).
PVIN (Pins 4, 5, 27, 28, 35, 36): Power VIN. Input voltage
to the on chip power MOSFETs. Must be closely decoupled
to PGND.
SW (Pins 6, 7, 8, 9, 23, 24, 25, 26): Switch Node Connection to the Inductor. This pin swings from PVIN to
PGND.
MODE (Pin 10): Mode Select Input. Tying this pin high
enables Burst Mode operation. Tying this pin low enables
force continuous operation. Tying it to VIN/2 enables pulseskipping operation.
CLKIN (Pin 11): External Synchronization Input to Phase
Detector. This pin is internally terminated to SGND with a
50k resistor. The phase-locked-loop will force the internal
top power PMOS turn on to be synchronized with the
rising edge of the CLKIN signal. Connect this pin to SVIN
to enable spread spectrum modulation. During external
synchronization, make sure the PLLLPF pin is not tied to
VIN or GND.
PHMODE (Pin 12): Phase Selector Input. This pin determines the phase relationship between the internal oscillator and CLKOUT. Tie it high for 2-phase operation, tie it
low for 3-phase operation, and tie it to VIN/2 for
4-phase operation.
PGND (Pins 13-19): Power Ground. Return path of internal
N-channel power MOSFETs. Connect this pin with the (–)
terminals of CIN and COUT.
MGN (Pin 20): Margining Pin. Tying this pin to a voltage
between 0.5V and SVIN – 0.5V disables the margining
function and allows normal operation. Tying it high enables
positive margining (5, 10, or 15%). Tying it low enables
negative margining (–5, –10, or –15%).
VFB (Pin 29): Input to the error amplifier that compares
the feedback voltage to the internal 0.6V reference voltage.
This pin is normally connected to a resistive divider from
the output voltage. In PolyPhase operation, tying VFB to
SVIN disables its own internal error amplifier and connects
the master’s ITH voltage to its current comparator.
TRACK (Pin 30): Track Input Pin. This allows the user to
control the rise time of the output. Putting a voltage below
0.57V on this pin bypasses the reference input into the error amplifier and servos the VFB pin to the TRACK voltage.
Above 0.57V, the tracking function stops and the internal
reference again controls the error amplifier. During shutdown, if TRACK is not tied to SVIN, then TRACK’s voltage
needs to be below 0.18V before the chip shuts down even
though RUN is already low. Do not float this pin.
ITH (Pin 32): Error Amplifier Output and Switching
Regulator Compensation Point. The current comparator’s
threshold increases with this control voltage. The normal
voltage range of this pin is from 0V to 1.5V. It’s also the
positive input to the internal ITH differential amplifier. Tying
ITH to SVIN enables the internal compensation.
ITHM (Pin 33): Negative Input to the Internal ITH Differential
Amplifier. Tie this pin to SGND for single phase operation.
For PolyPhase, tie the master’s ITHM to SGND while connecting all of the ITHM pins together.
SVIN (Pin 34): Signal Input Voltage. Connect this pin to
PVIN through a 1Ω and 0.1μF lowpass filter.
RUN (Pin 37): Run Control Input. Tying this pin above
1.5V turns on the part.
CLKOUT (Pin 38): Output Clock Signal for PolyPhase
Operation. The phase of CLKOUT is determined by the
state of the PHMODE pin.
Exposed Pad (Pin 39): Power Ground. Must be connected
to electrical ground on PCB.
3415fa
7
LTC3415
OPERATION
Main Control Loop
The LTC3415 is a constant frequency, current mode,
monolithic step down regulator. In normal operation,
the internal top P-channel power MOSFET turns on each
cycle when the oscillator sets the RS latch, and turns
off when the current comparator ICOMP resets the RS
latch. The peak inductor current at which ICOMP resets
the RS latch is controlled by the voltage on the ITH pin,
which is the output of error amplifier EA. The FB pin
allows EA to receive an output feedback voltage from
an external resistive divider. When the load current increases, it causes a slight decrease in the feedback voltage relative to the 0.596V reference, which in turn causes
ITH voltage to increase until the average inductor current
matches the new load current. While the top P-channel
power MOSFET is off, the bottom N-Channel power MOSFET
is turned on until either the inductor current starts to reverse, as indicated by the current reversal comparator
IRCMP, or the beginning of the next cycle.
The main control loop is shut down by pulling the RUN pin
below 1.5V (VTRACK = SVIN or VTRACK < 0.18V). Tying RUN
higher than 1.5V allows operation to begin. To control the
rise time of the output, a voltage ramp can be applied to
the TRACK pin. The FB voltage will servo to the TRACK
voltage until TRACK goes above 0.57V, which is when
PGOOD is high and the output is in normal regulation.
If TRACK is not used (tied high), then an internal 100μs
soft-start will ramp up the output.
Burst Mode Operation
The LTC3415 is capable of Burst Mode operation in which
the power MOSFETs operate intermittently based on load
demand, thus saving quiescent current. For applications
where maximizing the efficiency at very light loads is a
high priority, Burst Mode operation should be applied. To
enable Burst Mode operation, simply tie the MODE pin to
VIN. During this operation, the peak current of the inductor
is set to approximately 20% of the maximum peak current
value in normal operation even though the voltage at the
ITH pin indicates a lower value. The voltage at the ITH pin
drops when the inductor’s average current is greater than
the load requirement. As the ITH voltage drops below 0.2V,
the BURST comparator trips, causing the internal sleep
line to go high and turn off both power MOSFETs.
In sleep mode, the internal circuitry is partially turned off,
reducing the quiescent current to about 450μA. The load
current is now being supplied from the output capacitor.
When the output voltage drops, causing ITH to rise above
0.25V, the internal sleep line goes low, and the LTC3415
resumes normal operation. The next oscillator cycle will
turn on the top power MOSFET and the switching cycle
repeats.
Pulse-Skipping Mode Operation
In applications where fixed frequency operation, low
output ripple and high efficiency at intermediate current
is desired, pulse-skipping mode should be used. Pulseskipping operation allows the LTC3415 to skip cycles at
low output loads, thus increasing efficiency by reducing
switching current. Tying the MODE pin to VIN/2 enables
pulse-skipping operation. This allows discontinuous
conduction mode (DCM) operation down to near the limit
defined by the chip’s minimum on-time (about 100ns).
Below this output current level, the converter will begin
to skip cycles in order to maintain output regulation.
Increasing the output load current slightly, above the
minimum required for discontinuous conduction mode,
allows constant frequency PWM.
Forced Continuous Operation
In applications where fixed frequency operation is more
critical than low current efficiency, and where the lowest
output ripple is desired, forced continuous operation should
be used. Forced continuous operation can be enabled by
tying the MODE pin to GND. In this mode, inductor current is allowed to reverse during low output loads, the ITH
voltage is in control of the current comparator threshold
throughout, and the top MOSFET always turns on with each
oscillator pulse. During start-up, forced continuous mode is
disabled and inductor current is prevented from reversing
until the LTC3415’s output voltage is in regulation.
3415fa
8
LTC3415
OPERATION
overvoltage comparator during the time the LTC3415’s
internal reference is powering up. As a result, the bottom
switch turns on until the amount of reverse current trips
the INEGLIM comparator threshold.
Short-Circuit Protection
When the output is shorted to ground, the LTC3415
will drop cycles to allow the inductor time to decay and
prevent the current from running away. Under this fault
condition, the top P-channel power MOSFET turns on for
a minimum on-time and is held off for as long as it takes
for the inductor current to decay to a safe level.
Multiphase Operation
For output loads that demand more than 7A of current,
multiple LTC3415s can be cascaded to run out of phase to
provide more output current without increasing input and
output voltage ripple. The CLKIN pin allows the LTC3415
to synchronize to an external clock (between 0.75MHz and
2.25MHz) and the internal phase-locked-loop allows the
LTC3415 to lock onto CLKIN’s phase as well. The CLKOUT
signal can be connected to the CLKIN pin of the following
LTC3415 stage to line up both the frequency and the phase
of the entire system. Tying the PHMODE pin to SVIN, SGND,
or SVIN/2 generates a phase difference (between CLKIN
and CLKOUT) of 180 degrees, 120 degrees, or 90 degrees
respectively, which corresponds to 2-phase, 3-phase, or
4-phase operation. A total of 12 phases can be cascaded
to run simultaneously out of phase with respect to each
Output Overvoltage
If the LTC3415’s output voltage exceeds the regulation
point by 10%, which is reflected as a VFB voltage of 0.66V
or above, the LTC3415 will attempt to bring back to regulation by shutting off the top P-channel power MOSFET
and turning on the bottom N-Channel power MOSFET for
as long as needed to lower VOUT. However, if the reverse
current flowing from VOUT back through the bottom
N-Channel power MOSFET to PGND is greater than 7A,
the INEGLIM comparator trips and shuts off the bottom
N-Channel power MOSFET to protect it from being destroyed. This scenario can happen when the LTC3415 tries
to start into a pre-charged load, which could trigger the
0
+120
SVIN
180
+120
CLKIN CLKOUT
SVIN
PHMODE
PHASE 1
CLKIN CLKOUT
PHMODE
PHASE 2
3415 F02a
Figure 2a. 2-Phase Operation
0
CLKIN CLKOUT
120
+120
CLKIN CLKOUT
PHMODE
240
+120
CLKIN CLKOUT
PHMODE
PHASE 1
PHMODE
PHASE 2
PHASE 3
3415 F02b
Figure 2b. 3-Phase Operation
0
CLKIN CLKOUT
SVIN
2
PHMODE
PHASE 1
90
+90
SVIN
2
CLKIN CLKOUT
PHMODE
PHASE 2
180
+90
SVIN
2
CLKIN CLKOUT
PHMODE
PHASE 3
270
+90
SVIN
2
CLKIN CLKOUT
PHMODE
PHASE 4
3415 F02c
Figure 2c. 4-Phase Operation
3415fa
9
LTC3415
OPERATION
other by programming the PHMODE pin of each LTC3415
to different levels. For example, a slave stage that is 180
degrees out of phase from the master can generate a
CLKOUT signal that is 300 degrees (PHMODE = 0) away
from the master for the next stage, which then can generate a CLKOUT signal that’s 420, or 60 degrees (PHMODE
= SVIN/2) away from the master for its following stage.
0
120
CLKIN CLKOUT
+120
PHMODE
PHASE 1
A multiphase power supply significantly reduces the amount
of ripple current in both the input and output capacitors.
The RMS input ripple current is divided by, and the effective
ripple frequency is multiplied by, the number of phases used
(assuming that the input voltage is greater than the number
(420)
60
240
CLKIN CLKOUT
PHMODE
Refer to Figure 2 for configurations of 2-phase, 3-phase,
4-phase, 6-phase and 12-phase operation.
+120
SVIN
CLKIN CLKOUT
+180
PHMODE
PHASE 3
180
CLKIN CLKOUT
+120
PHMODE
PHASE 5
300
CLKIN CLKOUT
PHMODE
+120
SVIN
2
CLKIN CLKOUT
PHMODE
PHASE 4
PHASE 2
PHASE 6
3415 F02d
Figure 2d. 6-Phase Operation
0
CLKIN CLKOUT
SVIN
2
PHMODE
+90
SVIN
2
180
CLKIN CLKOUT
+90
SVIN
2
PHMODE
CLKIN CLKOUT
+90
PHMODE
CLKIN CLKOUT
PHMODE
PHASE 4
PHASE 7
PHASE 10
120
210
300
(420)
60
PHMODE
+90
SVIN
2
CLKIN CLKOUT
PHMODE
PHASE 5
PHASE 8
240
330
+90
CLKIN CLKOUT
PHMODE
(390)
30
270
PHASE 1
CLKIN CLKOUT
SVIN
2
90
+120
SVIN
2
CLKIN CLKOUT
PHMODE
PHASE 11
PHASE 3
+120
SVIN
2
CLKIN CLKOUT
+90
PHMODE
PHASE 2
150
+90
SVIN
2
CLKIN CLKOUT
+90
PHMODE
PHASE 6
3415 F02e
CLKIN CLKOUT
SVIN
2
PHMODE
PHASE 9
+90
SVIN
2
CLKIN CLKOUT
PHMODE
PHASE 12
Figure 2e. 12-Phase Operation
3415fa
10
LTC3415
OPERATION
The worst-case RMS ripple current for a single stage design
peaks at an input voltage of twice the output voltage. The
worst case RMS ripple current for a two stage design results in peak outputs of 1/4 and 3/4 of input voltage. When
the RMS current is calculated, higher effective duty factor
results and the peak current levels are divided as long as
the current in each stage is balanced. Refer to Application
Note 19 for a detailed description of how to calculate RMS
current for the single stage switching regulator. Figures 4 and
5 illustrate how the input and output currents are reduced
by using an additional phase. For a 2-phase converter,
the input current peaks drop in half and the frequency is
doubled. The input capacitor requirement is thus reduced
theoretically by a factor of four! Just imagine the possibility
of capacitor savings with even higher number of phases!
together, the amount of output current delivered from each
LTC3415 is nearly the same.
Different ground potentials among LTC3415 stages, caused
by physical distances and ground noises, could cause an
offset to the absolute ITH value seen by each stage. To
ensure that the ground level doesn’t affect the ITH value,
the LTC3415 uses a differential driver that takes as input
not just the ITH pin, but also the ITHM pin. The ITHM pins
of all the LTC3415 stages should be tied together and then
connected to the SGND at only one point.
1.0
0.9
0.8
1 PHASE
0.7
DIC(P-P)
VO/L
of phases used times the output voltage). The output ripple
amplitude is also reduced by the number of phases used.
Figure 3 graphically illustrates the principle.
0.6
0.5
0.4
0.3
Output Current Sharing
0.2
SINGLE PHASE
SW1 V
ICIN
0.1
0
0.1 0.2
DUAL PHASE
SW1 V
SW2 V
IL1
ICOUT
IL2
ICOUT
0.8
0.9
Figure 4. Normalized Output Ripple Current vs Duty Factor
[IRMSʺ 0.3 (DIC(PP))]
0.6
0.5
1 PHASE
0.4
0.3
2 PHASE
0.2
0.1
0
ICIN
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
3415 F04
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
When multiple LTC3415s are cascaded to drive a common load, accurate output current sharing is essential to
achieve optimal performance and efficiency. Otherwise,
if one stage is delivering more current than another, then
the temperature between the two stages will be different,
and that could translate into higher switch RDS(ON), lower
efficiency, and higher RMS ripple. Each LTC3415 is trimmed
such that when the ITH pins of multiple LTC3415s are tied
2 PHASE
0.1 0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
3415 F05
3415 F03
RIPPLE
Figure 5. Normalized RMS Input Ripple Current vs Duty Factor
for 1 and 2 Output Stages
Figure 3. Single and 2-Phase Current Waveforms
3415fa
11
LTC3415
OPERATION
Phase-Locked-Loop Operation
In order to synchronize to an external signal, the LTC3415
has an internal phase-locked-loop comprised of an internal voltage controlled oscillator and phase detector.
This allows the top P-channel power MOSFET turn-on to
be locked to the rising edge of an external source. The
frequency range of the voltage controlled oscillator is
+50% around the center frequency. Leaving the PLLLPF
pin floating corresponds to a free-running frequency of
approximately 1.5MHz. Tying PLLLPF directly to SVIN
corresponds to 1.33x of center frequency (2MHz) while
tying PLLLPF to ground corresponds to 0.67x of center
frequency (1MHz).
The phase detector used is an edge sensitive digital type
which provides zero degree phase shift between the external
and internal oscillators. The output of the phase detector
is a complementary pair of current sources charging or
discharging the external filter network on the PLLLPF pin.
See Figure 6.
If the external frequency, CLKIN, is greater than the oscillator frequency fOSC, current is sourced continuously,
pulling up the PLLLPF pin. When the external frequency is
less than fOSC, current is sunk continuously, pulling down
the PLLLPF pin. If the external and internal frequencies
are the same but exhibit a phase difference, the current
sources turn on for an amount of time corresponding to
the phase difference. Thus the voltage on the PLLLPF pin
is adjusted until the phase and frequency of the external
and internal oscillators are identical. The CLKIN pin must
be driven from a low impedance source such as a logic
gate located close to the pin. The loop filter components
(CLP, RLP) smooth out the current pulses from the phase
detector and provide a stable input to the voltage controlled
oscillator. The filter components determine how fast the
loop acquires lock. Typically RLP = 10k and CLP is 100pf
to 1000pf.
The CLKOUT pin provides a signal to synchronize following stages of LTC3415s. Its amplitude is 0V to 2V and its
phase with respect to the internal oscillator (or CLKIN) is
controlled by the PHMODE pin.
Internal/External ITH Compensation
During single phase operation, the user can simplify the
loop compensation by tying the ITH pin to SVIN to enable
internal compensation. This connects an internal 50k
resistor in series with a 50pF cap to the output of the
error amplifier (internal ITH compensation point). This is
a trade-off for simplicity instead of OPTI-LOOP ® optimization, where ITH components are external and are selected
to optimize the loop transient response with minimum
output capacitance. See Checking Transient Response in
the Applications Information section.
OPTI-LOOP is a registered trademark of Linear Technology Corporation.
2V
PHASE
DETECTOR
EXTERNAL
OSC
RLP
10k
CLP
PLLLPF
CLKIN
50k
DIGITAL
PHASE
FREQUENCY
DETECTOR
OSC
3415 F06
Figure 6. Phase-Locked-Loop Block Diagram
3415fa
12
LTC3415
OPERATION
In multiphase operation where all the ITH pins of each
LTC3415 are tied together to achieve accurate load sharing,
internal compensation is not allowed. External compensation components need to be properly selected for optimal
transient response and stable operation.
Master/Slave Operation
In multiphase single-output operation, the user has the
option to run in multi-master mode where all the VFB, ITH,
and output pins of the stages are tied to each other. All
the error amplifiers are effectively operating in parallel and
the total gm of the system is increased by the number of
stages. The ITH value, which dictates how much current
is delivered to the load from each stage, is averaged and
smoothed out by the external ITH compensation components. However, in certain applications, the resulting higher
gm from multiple LTC3415s can make the system loop
harder to compensate. In this case, the user can choose
an alternative mode of operation.
The second mode of operation is single-master operation
where only the error amplifier of the master stage is used
while the error amplifiers of the other stages (slaves) are
disabled. The slave’s error amplifier is disabled by tying
its VFB pin to SVIN, which also disables the internal overvoltage comparator and power-good indicator. The master’s
error amplifier senses the output through its VFB pin and
drives the ITH pins of all the stages. To account for ground
voltage differences among the stages, the user should
tie all ITHM pins together and then tie it to the master’s
signal ground. As a result, not only is it easier to do loop
compensation, this single-master operation should also
provide for more accurate current sharing among stages
because it prevents the error amplifier’s output (ITH) of
each stage from interfering with that of another stage.
Spread Spectrum Operation
Switching Regulators can be particularly troublesome
where electromagnetic interference (EMI) is concerned.
Switching regulators operate on a cycle-by-cycle basis to
transfer power to an output. In most cases, the frequency
of operation is fixed or is a constant based on the output
load. This method of conversion creates large components
of noise at the frequency of operation (fundamental) and
multiples of the operating frequency (harmonics).
To reduce this noise, the LTC3415 can run in spread
spectrum operation by tying the CLKIN pin to SVIN. In
spread spectrum operation, the LTC3415’s internal oscillator is designed to produce a clock pulse whose period
is random on a cycle-by-cycle basis but fixed between
70% and 130% of the nominal frequency. This has the
benefit of spreading the switching noise over a range of
frequencies, thus significantly reducing the peak noise.
Figures 7 and 8 show how the spread spectrum feature
of the LTC3415 significantly reduces the peak harmonic
–10
AMPLITUDE (dBm)
–30
–14.1dBm
–40
–50
–60
–70
–80
–20
–30
AMPLITUDE (dBm)
–20
–10
VIN = 5V
VOUT = 1.8V
RBW = 100Hz
–50
–60
–70
–80
–90
–100
–100
Figure 7. LTC3415’s Output Noise Spectrum Analysis in
Free-Running Constant Frequency Operation
–37.3dBm
–40
–90
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
FREQUENCY (MHz)
3415 F07
VIN = 5V
VOUT = 1.8V
RBW = 100Hz
1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 2.0
FREQUENCY (MHz)
3415 F08
Figure 8. LTC3415’s Output Noise Spectrum Analysis in Spread
Spectrum Operation
3415fa
13
LTC3415
OPERATION
noise vs free-running constant frequency operation. Spread
spectrum operation is disabled if CLKIN is tied to ground
or if it’s driven by an external frequency synchronization
signal.
frequency applications may approach this minimum ontime limit and care should be taken to ensure that:
tON(MIN) <
VOUT
(f • VIN )
Dropout Operation
When the input supply voltage decreases toward the output
voltage, the duty cycle will increase toward the maximum
on-time. Further reduction of the supply voltage forces the
P-channel power MOSFET to remain on for more than one
cycle until it reaches 100% duty cycle. The output voltage
will then be determined by the input voltage minus the
voltage drop across the P-channel power MOSFET and
the inductor.
Slope Compensation and Inductor Peak Current
Slope compensation provides stability by preventing subharmonic oscillations. It works by internally adding a ramp
to the inductor current signal at duty cycles in excess of
30%. This causes the internal current comparator to trip
earlier. The ITH clamp is also reached earlier than conditions in which the duty cycle is below 30%. As a result,
the maximum inductor peak current is lower for higher
duty cycle operations.
To compensate for this loss in maximum inductor peak
current during high duty cycles, the LTC3415 uses a patented scheme that raises the ITH clamp level (proportional
to the amount of slope compensation) when the duty cycle
is greater than 30%.
Minimum On-Time Considerations
Minimum on-time, tON(MIN), is the smallest amount
of time that the LTC3415 is capable of turning the top
P-channel power MOSFET on and off again. It is determined
by the internal timing delays. The minimum on-time for
the LTC3415 is about 100ns. Low duty cycle and high
If the duty cycle falls below what can be accommodated
by the minimum on-time, the LTC3415 will begin to skip
cycles. The output voltage will continue to be regulated,
but the ripple current and ripple voltage will increase.
If an application can operate close to the minimum on-time
limit, an inductor must be chosen that has low enough
inductance to provide sufficient ripple amplitude to meet
the minimum on-time requirement. As a general rule, keep
the inductor ripple current equal or greater than 30% of
the IOUT(MAX) at VIN(MAX).
Output Margining
For a convenient system stress test on the LTC3415’s output, the user can program the LTC3415’s output to ±5%,
±10% or ±15% of its normal operational voltage.
The MGN pin, when connected to a voltage between 0.5V
and SVIN – 0.SV allows normal operation. When the MGN
pin is low, it forces negative margining, in which the output
voltage is below the regulation point. When MGN is high, the
output voltage is forced to above the regulation point. The
amount of output voltage margining is determined by the
BSEL pin. When BSEL is low, it’s 5%. When BSEL is high,
it’s 10%. When BSEL is VIN/2, it’s 15%. When margining
is active, the internal output overvoltage and undervoltage
comparators are disabled and PGOOD remains high.
Output Power-Good
When the LTC3415’s output voltage is within a ±10%
window of the regulation point, which is reflected back
as a VFB voltage in the range of 0.54V to 0.66V, the output
voltage is good and the PGOOD pin is pulled high with
the external resistor.
3415fa
14
LTC3415
OPERATION
Otherwise, an internal open-drain pull down device (20Ω)
will pull the PGOOD pin low. In certain computer systems
today, the PGOOD pin is used as a resetting signal while
the output voltage is dynamically changed from one level
to another. To prevent unwanted power resetting during
output voltage changes, the LTC3415’s PGOOD falling
and rising edges include a blanking delay equivalent to
approximately 10μs per every volt of VIN.
Output Voltage Programming
The output voltage is set by an external resistive divider
according to the following equation:
R2 VOUT = 0.596V • 1+ R1 The resistive divider allows pin VFB to sense a fraction of
the output voltage as shown in Figure 9.
Output Tracking and Sequencing
Some microprocessor, ASIC and DSP chips need two
power supplies with different voltage levels. These systems often require voltage sequencing between the core
power supply and the I/O power supply. Without proper
sequencing, latch-up failure or excessive current draw
may occur that could result in damage to the processor’s
I/O ports or the I/O ports of supporting system devices
such as memory, FPGAs or data converters. To ensure
that the I/O loads are not driven until the core voltage is
properly biased, tracking of the core supply voltage and
the I/O supply voltage is necessary.
Voltage tracking is enabled by applying a voltage to the
TRACK pin. When the voltage on the TRACK pin is below
0.57V, the feedback voltage will regulate to this tracking
voltage. When the tracking voltage exceeds 0.57V, tracking
is disabled and the feedback voltage will regulate to the
internal reference voltage.
VOUT
Voltage Tracking
R2
CFF
The LTC3415 allows the user to program how its output
voltage ramps during start-up by means of the TRACK
pin. Through this pin, the output voltage can be set up to
either coincidentally or ratiometrically track another output
voltage as shown in Figure 10.
VFB
LTC3415
R1
SGND
3415 F09
Figure 9. Setting the Output Voltage
VOUT1
VOUT2
OUTPUT VOLTAGE
OUTPUT VOLTAGE
VOUT2
VOUT1
3415 F10
TIME
(10a) Coincident Tracking
TIME
(10b) Ratiometric Sequencing
Figure 10. Two Different Modes of Output Voltage Sequencing
3415fa
15
LTC3415
OPERATION
its midpoint to the TRACK pin of the LTC3415 as shown
in Figure 11. The ratio of this divider should be selected
the same as that of VOUT1’s resistive divider. To implement
the ratiometric sequencing in Figure 10b, no extra resistive divider is necessary. Simply connect the TRACK pin
to VFB of the master.
If the voltage on the TRACK pin is less than 0.57V, voltage
tracking is enabled. During voltage tracking, the output
voltage is regulated by the tracking voltage through a resistive divider network. The output voltage during tracking
can be calculated with the following equation:
R2 VOUT = VTRACK 1+ ,VTRACK < 0.57V
R1 An alternative method of tracking is shown in Figure 12.
For the circuit of Figure 12, the following equations can
be used to determine the resistor values:
R2 VOUT1 = 0.596V 1+ R1 R4 + R5 VOUT2 = 0.596V 1+
R3 V
R4 = R3 OUT2 – 1
VOUT1 Voltage tracking can be accomplished by sensing a fraction of the output voltage from another regulator. This is
typically done by using a resistive divider to attenuate the
output voltage that is being tracked. Setting this resistive
divider equal to the feedback resistive divider will force the
regulator outputs to be equal to each other during tracking. If tracking is not desired, connect the TRACK pin to
SVIN. Do not leave the TRACK pin floating. To implement
the coincident tracking shown in Figure 10a, connect an
extra resistive divider to the output of VOUT2 and connect
VOUT2
VOUT2
R4
R2
R2
TO
TRACK
PIN
TO
VFB2(MASTER)
PIN
TO
TRACK
PIN
R3
R1
R1
TO
VFB2(MASTER)
PIN
3415 F11
(11b) Ratiometric Setup
(11a) Coincident Tracking Setup
Figure 11. Setup for Tracking and Ratiometric Sequencing
VOUT2
R5
R4
VFB
LTC3415
R3
SGND
VOUT1
R2
VFB
TRACK
LTC3415
R1
SGND
3415 F12
Figure 12. Dual Voltage System with Tracking
3415fa
16
LTC3415
OPERATION
During ramp down of the output, if the TRACK pin is not
tied to VIN, then the LTC3415 will maintain normal operation even though the RUN pin is programmed low. Only
when the TRACK pin is below 0.18V will the RUN signal
be gated through internally and shut down the part. This
way, coincident tracking and ratiometric sequencing of the
two outputs are accomplished during both start-up and
shutdown. An output current load, however, needs to be
present during this time in order to discharge the output
because when TRACK is below 0.57V, forced continuous
operation is not allowed and inductor current, therefore,
is prevented from going negative.
For applications that do not require tracking or sequencing, simply tie the TRACK pin to SVIN to let RUN control
the turn on/off of the LTC3415. Connecting TRACK to
SVIN also enables the ~100μs of internal soft-start during
start-up.
3415fa
17
LTC3415
APPLICATIONS INFORMATION
CIN and COUT Selection
The input capacitance, CIN, is needed to filter the trapezoidal
wave current at the source of the top MOSFET. To prevent
large voltage transients from occurring, a low ESR input
capacitor sized for the maximum RMS current should be
used. The maximum RMS current is given by:
IRMS ≅IOUT(MAX)
VOUT
VIN
VIN
–1
VOUT
This formula has a maximum at VIN = 2VOUT, where IRMS
= IOUT/2. This simple worst-case condition is commonly
used for design because even significant deviations do
not offer much relief. Note that ripple current ratings from
capacitor manufacturers are often based on only 2000
hours of life which makes it advisable to further derate
the capacitor, or choose a capacitor rated at a higher
temperature than required.
Several capacitors may also be paralleled to meet size or
height requirements in the design. For low input voltage
applications, sufficient bulk input capacitance is needed to
minimize transient effects during output load changes.
The selection of COUT is determined by the effective series
resistance (ESR) that is required to minimize voltage ripple
and load step transients as well as the amount of bulk
capacitance that is necessary to ensure that the control
loop is stable. Loop stability can be checked by viewing
the load transient response. The output ripple, ΔVOUT, is
determined by:
1 VOUT IL ESR+
8fCOUT and RMS current handling requirements. Dry tantalum,
special polymer, aluminum electrolytic, and ceramic
capacitors are all available in surface mount packages.
Special polymer capacitors offer very low ESR but have
lower capacitance density than other types. Tantalum
capacitors have the highest capacitance density but it is
important to only use types that have been surge tested
for use in switching power supplies. Aluminum electrolytic
capacitors have significantly higher ESR, but can be used
in cost-sensitive applications provided that consideration
is given to ripple current ratings and long term reliability.
Ceramic capacitors have excellent low ESR characteristics
and small footprints. Their relatively low value of bulk
capacitance may require multiples in parallel.
Using Ceramic Input and Output Capacitors
Higher values, lower cost ceramic capacitors are now
becoming available in smaller case sizes. Their high ripple
current, high voltage rating and low ESR make them ideal
for switching regulator applications. However, care must
be taken when these capacitors are used at the input and
output. When a ceramic capacitor is used at the input
and the power is supplied by a wall adapter through long
wires, a load step at the output can induce ringing at the
VIN input. At best, this ringing can couple to the output and
be mistaken as loop instability. At worst, a sudden inrush
of current through the long wires can potentially cause a
voltage spike at VIN large enough to damage the part.
When choosing the input and output ceramic capacitors,
choose the X5R or X7R dielectric formulations. These
dielectrics have the best temperature and voltage characteristics of all the ceramics for a given value and size.
The output ripple is highest at maximum input voltage
since ΔIL increases with input voltage. Multiple capacitors placed in parallel may be needed to meet the ESR
3415fa
18
LTC3415
APPLICATIONS INFORMATION
Inductor Selection
Given the desired input and output voltages, the inductor value and operating frequency determine the ripple
current:
V V IL = OUT 1– OUT VIN fL Lower ripple current reduces cores losses in the inductor,
ESR losses in the output capacitors, and output voltage
ripple. Highest efficiency operation is obtained at low
frequency with small ripple current. However, achieving
this requires a large inductor. There is a tradeoff between
component size, efficiency, and operating frequency.
A reasonable starting point is to choose a ripple current
that is about 40% of IOUT(MAX). Note that the largest ripple
current occurs at the highest VIN. To guarantee that ripple
current does not exceed a specified maximum, the inductance should be chosen according to:
V
V
L = OUT 1– OUT fIL(MAX) VIN(MAX) Once the value for L is known, the type of inductor must
be selected. Actual core loss is independent of core size for
a fixed inductor value, but is very dependent on the
inductance selected. As the inductance increases, core
losses decrease. Unfortunately, increased inductance
requires more turns of wire and therefore copper losses
will increase.
Ferrite designs have very low core losses and are preferred at high switching frequencies, so design goals can
concentrate on copper loss and preventing saturation.
Ferrite core material saturates “hard,” which means that
inductance collapses abruptly when the peak design current
is exceeded. This results in an abrupt increase in inductor
ripple current and consequent output voltage ripple. Do
not allow the core to saturate!
Different core materials and shapes will change the size/current and price/current relationship of an inductor. Toroid
or shielded pot cores in ferrite or permalloy materials are
small and don’t radiate much energy, but generally cost
more than powdered iron core inductors with similar
characteristics. The choice of which style inductor to use
mainly depends on the price versus size requirements
and any radiated field/EMI requirements. New designs for
surface mount inductors are available from Coiltronics,
Coilcraft, Toko, and Sumida.
Checking Transient Response
The OPTI-LOOP compensation allows the transient response to be optimized for a wide range of loads and
output capacitors. The availability of the ITH pin not only
allows optimization of the control loop behavior but also
provides a DC-coupled and AC filtered closed loop response
test point. The DC step, rise time and settling at this test
point truly reflects the closed loop response. Assuming a
predominantly second order system, phase margin and/or
damping factor can be estimated using the percentage of
overshoot seen at this pin. The bandwidth can also be
estimated by examining the rise time at the pin.
The ITH external components shown in the Figure 12 circuit
will provide an adequate starting point for most applications. The series R-C filter sets the dominant pole-zero
loop compensation. The values can be modified slightly
(from 0.5 to 2 times their suggested values) to optimize
transient response once the final PC layout is done and
the particular output capacitor type and value have been
determined. The output capacitors need to be selected
because their various types and values determine the
loop feedback factor gain and phase. An output current
pulse of 20% to 100% of full load current having a rise
time of 1μs to 10μs will produce output voltage and ITH
pin waveforms that will give a sense of the overall loop
stability without breaking the feedback loop.
3415fa
19
LTC3415
APPLICATIONS INFORMATION
Switching regulators take several cycles to respond to a
step in load current. When a load step occurs, VOUT immediately shifts by an amount equal to ΔILOAD • ESR, where
ESR is the effective series resistance of COUT. ΔILOAD also
begins to charge or discharge COUT generating a feedback
error signal used by the regulator to return VOUT to its
steady-state value. During this recovery time, VOUT can
be monitored for overshoot or ringing that would indicate
a stability problem.
The initial output voltage step may not be within the
bandwidth of the feedback loop, so the standard second
order overshoot/DC ratio cannot be used to determine
phase margin. The gain of the loop increases with the R
and the bandwidth of the loop increases with decreasing
C. If R is increased by the same factor that C is decreased,
the zero frequency will be kept the same, thereby keeping
the phase the same in the most critical frequency range of
the feedback loop. In addition, a feed forward capacitor CF
can be added to improve the high frequency response, as
shown in Figure 9. Capacitor CF provides phase lead by
creating a high frequency zero with R2 which improves
the phase margin.
The output voltage settling behavior is related to the stability
of the closed-loop system and will demonstrate the actual
overall supply performance. For a detailed explanation of
optimizing the compensation components, including a
review of control loop theory, refer to Linear Technology
Application Note 76.
Although a buck regulator is capable of providing the full
output current in dropout, it should be noted that as the
input voltage VIN drops toward VOUT, the load step capability
does decrease due to the decreasing voltage across the
inductor. Applications that require large load step capability near dropout should use a different topology such as
SEPIC, Zeta, or single inductor, positive buck/boost.
In some applications, a more severe transient can be
caused by switching in loads with large (>10μF) input
capacitors. The discharged input capacitors are effectively put in parallel with COUT, causing a rapid drop in
VOUT. No regulator can deliver enough current to prevent
this problem, if the switch connecting the load has low
resistance and is driven quickly. The solution is to limit
the turn-on speed of the load switch driver. A Hot Swap™
controller is designed specifically for this purpose and
usually incorporates current limiting, short-circuit protection, and soft-starting.
Efficiency Considerations
The percent efficiency of a switching regulator is equal to
the output power divided by the input power times 100%.
It is often useful to analyze individual losses to determine
what is limiting the efficiency and which change would
produce the most improvement. Percent efficiency can
be expressed as:
% Efficiency = 100% – (L1 + L2 + l3 + …)
where L1, L2, etc. are the individual losses as a percentage of input power.
Although all dissipative elements in the circuit produce
losses, four main sources usually account for most of
the losses in LTC3415 circuits: 1) LTC3415 VIN current,
2) switching losses, 3) I2R losses, 4) other losses.
1) The VIN current is the DC supply current given in the
Electrical Characteristics which excludes MOSFET driver
and control currents. VIN current results in a small
(<1%) loss that increases with VIN, even at no-load.
2) The switching current is the sum of the MOSFET driver
and control currents. The MOSFET driver current results from switching the gate capacitance of the power
MOSFETs. Each time a MOSFET gate is switched from
low to high to low again, a packet of charge dQ moves
from VIN to ground. The resulting dQ/dt is a current
out of VIN that is typically much larger than the DC bias
current. In continuous mode, IGATECHG = f (QT + QB),
where QT and QB are the gate charges of the internal
top and bottom MOSFET switches and f is the operating frequency. The gate charge losses are proportional
to VIN and thus their effects will be more pronounced
at higher supply voltages and higher switching
frequencies.
Hot Swap is a trademark of Linear Technology Corporation.
3415fa
20
LTC3415
APPLICATIONS INFORMATION
3) I2R losses are calculated from the DC resistances of
the internal switches, RSW, and external inductor, RL.
In continuous mode, the average output current flows
through inductor L but is “chopped” between the internal
top and bottom switches. Thus, the series resistance
looking into the SW pin is a function of both top and
bottom MOSFET RDS(ON) and the duty cycle (DC) as
follows:
RSW = (RDS(ON) TOP)(DC) + (RDS(ON)BOT)(1-DC)
The RDS(ON) for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. Thus, to obtain I2R losses:
I2R losses = IOUT2(RSW + RL)
4) Other “hidden” losses such as copper trace and internal battery resistances can account for additional
efficiency degradations in portable systems. It is very
important to include these “system” level losses in
the design of a system. The internal battery and fuse
resistance losses can be minimized by ensuring that
CIN has adequate charge storage and very low ESR at
the switching frequency. Other losses including diode
conduction losses during dead-time and inductor
core losses generally account for less than 2% total
additional loss.
Thermal Considerations
In the majority of applications, the LTC3415 does not
dissipate much heat due to its high efficiency. However,
in applications where the LTC3415 is running at high
ambient temperature with low supply voltage and high
duty cycles, such as in dropout, the heat dissipated may
exceed the maximum junction temperature of the part. If
the junction temperature reaches approximately 150°C,
both power switches will be turned off and the SW node
will become high impedance.
To avoid the LTC3415 from exceeding the maximum junction temperature, the user will need to do some thermal
analysis. The goal of the thermal analysis is to determine
whether the power dissipated exceeds the maximum
junction temperature of the part. The temperature rise is
given by:
TRISE = PD • θJA
where PD is the power dissipated by the regulator and θJA
is the thermal resistance from the junction of the die to
the ambient temperature.
The junction temperature, TJ, is given by:
TJ = TRISE + TAMBIENT
As an example, consider the case when the LTC3415 is in
dropout at an input voltage of 3.3V with a load current of
5A. From the Typical Performance Characteristics graph
of Switch Resistance, the RDS(ON) resistance of the Pchannel switch is 0.03. Therefore, power dissipated by
the part is:
PD = I2 • RDS(ON) = 750mW
The QFN 5mm × 7mm package junction-to-ambient thermal
resistance, θJA, is around 34°C/W. Therefore, the junction
temperature of the regulator operating in a 50°C ambient
temperature is approximately:
TJ = 0.75 • 34 + 50 = 75.5°C
Remembering that the above junction temperature is
obtained from an RDS(ON) at 25°C, we might recalculate
the junction temperature based on a higher RDS(ON) since
it increases with temperature. However, we can safely assume that the actual junction temperature will not exceed
the absolute maximum junction temperature of 125°C.
Solder the LTC3415’s bottom exposed pad to ground for
optimal thermal performance.
3415fa
21
LTC3415
APPLICATIONS INFORMATION
Board Layout Considerations
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of
the LTC3415. Check the following in your layout:
1) Do the capacitors CIN connect to the power PVIN and
power PGND as closely as possible? These capacitors
provide the AC current to the internal power MOSFETs
and their drivers.
2) Are the COUT and L1 closely connected? The (–) plate
of COUT returns current to PGND and the (–) plate of
CIN.
3) The resistive divider, R1 and R2, must be connected
between the (+) plate of COUT and a ground line terminated near SGND. The feedback signal VFB should be
routed away from noisy components and traces, such
as the SW line, and its trace should be minimized.
4) Keep sensitive components away from the SW pin. The
input capacitor CIN, the compensation capacitor CC and
CITH and all the resistors R1, R2, RC should be routed
away from the SW trace and the inductor L1.
5) A ground plane is preferred, but if not available, keep
the signal and power grounds segregated with small
signal components returning to the SGND pin at one
point which is then connected to the PGND pin.
Flood all unused areas on all layers with copper. Flooding
with copper will reduce the temperature rise of power
components. These copper areas should be connected to
one of the input supplies: PVIN, PGND, SVIN, or SGND.
Design Example
As a design example, consider using the LTC3415 in an
application with the following specifications:
VIN = 3.3V, VOUT = 1.8V, IOUT(MAX) = 7A,
IOUT(MIN) = 500mA, f = 1.5MHz
Because efficiency is important at both high and low load
current, Burst Mode operation or pulse-skipping operation
will be utilized. First calculate the inductor value for about
40% ripple current at maximum VIN:
1.8V 1.8V
L=
1–
= 0.2μH
1.5MHz • 2.8A 3.3V COUT will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, two
100μF ceramic capacitors will be used.
CIN should be sized for a maximum current rating of:
2.5V 4.2V
IRMS = 7A – 1 = 3.43A
4.2V 2.5V
Decoupling the PVIN pins with three 47μF ceramic capacitors is adequate for most applications.
3415fa
22
LTC3415
TYPICAL APPLICATIONS
0.1μF
1Ω
VIN
47μF
6.3V
3x
10k
100pF
38
SGND
10pF
MODE
CLKIN
PHMODE
37
36
35
34
33
32
CLKOUT RUN PVIN PVIN SVIN ITHM ITH
1
NC
NC
2
TRACK
SGND
3
PLLLPF
VFB
4
PVIN
PVIN
5
PVIN
PVIN
6
SW
SW
LTC3415EUHF
7
SW
SW
8
SW
SW
9
SW
SW
10
PGOOD
MODE
PGND (39)
11
BSEL
CLKIN
12
MGN
PHMODE
PGND PGND PGND PGND PGND PGND PGND
13
14
15
16
17
18
31
30
29
15k
SVIN
28
27
30.5k
26
25
24
23
22
21
20
10k
SVIN
BSEL
MGN
19
100μF, 6.3V
2x
3415 TA02
VOUT
1.8V/7A
0.2μH
Figure 13. 3.3V to 1.8V/7A Application
3415fa
23
LTC3415
TYPICAL APPLICATIONS
Dual LTC3415 Dual Output Sequencing Application
SHDNB
0.01μF
0.1μF
10k
1Ω
100pF
1000pF
VIN
38
22μF
3x
10k
100k
100pF
10pF
SGND
CLKIN
SVIN
37
36
35
34
33
32
CLKOUT RUN PVIN PVIN SVIN ITHM ITH
1
NC
NC
2
SGND
TRACK
3
PLLLPF
VFB
4
PVIN
PVIN
5
PVIN
PVIN
6
SW
SW
LTC3415EUHF
7
SW
SW
8
SW
SW
9
SW
SW
10
MODE
PGOOD
PGND (39)
11
CLKIN
BSEL
12
PHMODE
MGN
PGND PGND PGND PGND PGND PGND PGND
13
14
15
16
17
18
31
30
29
9.53k
SVIN
28
27
30.5k
26
25
24
23
22
21
20
100k
SVIN
BSEL
MGN
19
47μF
3x
OUTPUT SEQUENCING
VOUT (2.5V)
SHDNB
0.2μH
100k
VOUT1 = 2.5V
SHDNB
VOUT2 = 1.8V
0.1μF
10k
1Ω
100pF
1000pF
VIN
38
22μF
3x
1
10k
SGND
2
3
4
100pF
10pF
5
6
7
8
9
CLKIN2
SGND
PHMODE
10
11
12
37
CLKOUT RUN
NC
36
PVIN
35
PVIN
34
SVIN
33
ITHM
32
ITH
NC
TRACK
SGND
PLLLPF
VFB
PVIN
PVIN
PVIN
PVIN
SW
SW
LTC3415EUHF
SW
SW
SW
SW
SW
SW
MODE
PGOOD
PGND (39)
BSEL
CLKIN
MGN
PHMODE
PGND PGND PGND PGND PGND PGND PGND
13
14
15
16
17
18
31
30
29
15k
SVIN
28
27
30.5k
26
25
24
23
22
21
20
100k
SVIN
BSEL
MGN
19
47μF
3x
VOUT (1.8V)
VOUT (1.8V)
0.2μH
3415 TA05
3415fa
24
SVIN
SGND
0.1μF
37
36
1Ω
35
34
33
32
10k
13
14
15
16
17
18
19
CLKOUT RUN PVIN PVIN SVIN ITHM ITH
1
NC
NC
2
TRACK
SGND
3
PLLLPF
VFB
4
PVIN
PVIN
5
PVIN
PVIN
6
SW
SW
LTC3415EUHF
7
SW
SW
8
SW
SW
9
SW
SW
10
PGOOD
MODE
PGND (39)
11
BSEL
CLKIN
12
MGN
PHMODE
PGND PGND PGND PGND PGND PGND PGND
38
RUN
20
21
22
23
24
25
26
27
28
29
30
31
100pF
MGN
BSEL
10k
0.2μH
SVIN
VTRACK
30.5k
15k
1000pF
SVIN
10pF
SGND
0.2μH
VOUT
1.8V/14A
100μF
6.3V
2x
100pF
10k
22μF
6x
VIN
0.1μF
Dual LTC3415 Single Output 14A Application
37
36
35
34
33
32
13
14
15
16
17
18
19
CLKOUT2 RUN PVIN PVIN SVIN ITHM ITH
1
NC
NC
2
TRACK
SGND
3
PLLLPF
VFB
4
PVIN
PVIN
5
PVIN
PVIN
6
SW
SW
LTC3415EUHF
7
SW
SW
8
SW
SW
9
SW
SW
10
PGOOD
MODE
PGND (39)
11
BSEL
CLKIN
12
MGN
PHMODE
PGND PGND PGND PGND PGND PGND PGND
38
1Ω
3415 TA03
20
21
22
23
24
25
26
27
28
29
30
31
MGN
BSEL
VIN
LTC3415
TYPICAL APPLICATIONS
3415fa
25
LTC3415
TYPICAL APPLICATIONS
Dual LTC3415 Dual Output Tracking Application
0.1μF
RUN
10k
1Ω
100pF
1000pF
VIN
38
22μF
6.3V
3x
10k
100pF
10pF
CLKIN
SVIN
37
36
35
34
33
32
CLKOUT RUN PVIN PVIN SVIN ITHM ITH
1
NC
NC
2
SGND
TRACK
3
PLLLPF
VFB
4
PVIN
PVIN
5
PVIN
PVIN
6
SW
SW
LTC3415EUHF
7
SW
SW
8
SW
SW
9
SW
SW
10
MODE
PGOOD
PGND (39)
11
CLKIN
BSEL
12
PHMODE
MGN
PGND PGND PGND PGND PGND PGND PGND
13
14
15
16
17
18
31
30
29
9.53k
SVIN
28
27
3.7k
26
25
24
23
22
21
20
26.7k
10k
SVIN
BSEL
MGN
19
47μF, 6.3V
3x
VOUT
2.5V/7A
0.2μH
0.1μF
RUN
10k
1Ω
100pF
1000pF
VIN
38
22μF
6.3V
3x
10k
100pF
SGND
10pF
CLKIN2
PHMODE
37
36
35
34
33
32
CLKOUT RUN PVIN PVIN SVIN ITHM ITH
1
NC
NC
2
TRACK
SGND
3
PLLLPF
VFB
4
PVIN
PVIN
5
PVIN
PVIN
6
SW
SW
LTC3415EUHF
7
SW
SW
8
SW
SW
9
SW
SW
10
PGOOD
MODE
PGND (39)
11
BSEL
CLKIN
12
MGN
PHMODE
PGND PGND PGND PGND PGND PGND PGND
13
14
15
16
17
18
31
15k
30
29
28
27
30.5k
26
25
24
23
22
21
20
10k
SVIN
BSEL
MGN
19
47μF, 6.3V
3x
3415 TA04
VOUT
1.8V/7A
0.2μH
3415fa
26
LTC3415
PACKAGE DESCRIPTION
UHF Package
38-Lead Plastic QFN (5mm × 7mm)
(Reference LTC DWG # 05-08-1701)
0.70 p 0.05
5.50 p 0.05
5.15 ± 0.05
4.10 p 0.05
3.00 REF
3.15 ± 0.05
PACKAGE
OUTLINE
0.25 p 0.05
0.50 BSC
5.5 REF
6.10 p 0.05
7.50 p 0.05
RECOMMENDED SOLDER PAD LAYOUT
APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED
5.00 p 0.10
0.75 p 0.05
PIN 1 NOTCH
R = 0.30 TYP OR
0.35 s 45o CHAMFER
3.00 REF
37
0.00 – 0.05
38
0.40 p0.10
PIN 1
TOP MARK
(SEE NOTE 6)
1
2
5.15 ± 0.10
7.00 p 0.10
5.50 REF
3.15 ± 0.10
(UH) QFN REF C 1107
0.200 REF 0.25 p 0.05
0.50 BSC
R = 0.125
TYP
R = 0.10
TYP
BOTTOM VIEW—EXPOSED PAD
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE
OUTLINE M0-220 VARIATION WHKD
2. DRAWING NOT TO SCALE
3. ALL DIMENSIONS ARE IN MILLIMETERS
4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE
5. EXPOSED PAD SHALL BE SOLDER PLATED
6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION
ON THE TOP AND BOTTOM OF PACKAGE
3415fa
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that
the interconnection of its circuits as described herein will not infringe on existing patent rights.
27
LTC3415
RELATED PARTS
PART NUMBER DESCRIPTION
COMMENTS
LTC3404
600mA IOUT, 1.4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.7V to 6V, VOUT(MIN) = 0.8V, IQ = 10μA,
ISD = <1μA, MS8 Package
LTC3405/
LTC3405A
300mA IOUT, 1.5MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 20μA,
ISD = <1μA, ThinSOT Package
LTC3406/
LTC3406B
600mA IOUT, 1.5MHz, Synchronous Step-Down DC/DC Converter
96% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 20μA,
ISD = <1μA, ThinSOT Package
LTC3407
Dual 600mA IOUT, 1.5MHz, Synchronous Step-Down
DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.6V, IQ = 40μA,
ISD = <1μA, MS10E Package
LTC3411
1.25A IOUT, 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,
ISD = <1μA, MS10 Package
LTC3412
2.5A IOUT, 4MHz, Synchronous Step-Down DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 0.8V, IQ = 60μA,
ISD = <1μA, TSSOP16E Package
LTC3413
3A IOUT Sink/Source, 2MHz, Monolithic Synchronous Regulator
for DDR/QDR Memory Termination
90% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = VREF/2,
IQ = 280μA, ISD = <1μA, TSSOP16E Package
LTC3414
4A IOUT, 4MHz, Synchronous Monolithic Step-Down Regulator
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA,
ISD = <1μA, TSSOP20E Package
LTC3416
4A IOUT, 4MHz, Synchronous Monolithic Step-Down
Regulator with Tracking
95% Efficiency, VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, IQ = 64μA,
ISD = <1μA, TSSOP20E Package
LTC3418
8A IOUT, 4MHz, Synchronous Monolithic Step-Down Regulator
VIN: 2.25V to 5.5V, VOUT(MIN) = 0.8V, 5mm × 7mm GFN Package
LTC3425
5A IOUT, 8MHz, 4-Phase Synchronous Step-Up DC/DC Converter
5% Efficiency, VIN: 0.5V to 4.5V, VOUT(MAX) = 5.25V, IQ = 12μA,
ISD = <1μA, QFN Package
LTC3428
4A IOUT, 2MHz, Dual Phase Step-Up DC/DC Converter
92% Efficiency, VIN: 1.6V to 4.5V, VOUT(MAX) = 5.25V,
IQ = 1.3mA, ISD = <1μA, DFN Package
LT3430
60V, 2.75A IOUT, 200kHz, High Efficiency Step-Down DC/DC
Converter
90% Efficiency, VIN: 5.5V to 60V, VOUT(MIN) = 1.20V, IQ = 2.5mA,
ISD = 25μA, TSSOP16E Package
LTC3440
600mA IOUT, 2MHz, Synchronous Buck-Boost DC/DC Converter
95% Efficiency, VIN: 2.5V to 5.5V, VOUT(MIN) = 2.5V, IQ = 25μA,
ISD = <1μA, MS-10 Package
LTM4600
10A, DC/DC μModule
Complete Synchronous Power Supply in LGA; 4.5V ≤ VIN ≤ 28V;
15mm × 15mm × 2.8mm LGA Package
3415fa
28 Linear Technology Corporation
LT 0508 REV A • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
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