ISL78268 Datasheet

DATASHEET
55V Synchronous Buck Controller with Integrated 3A
Driver
ISL78268
Features
The ISL78268 is a grade 1, automotive, synchronous buck
controller with integrated high/low side MOSFET drivers. It
supports a wide operating input voltage range of 5V to 55V
and up to 60V at VIN when not switching. The integrated driver
offers adaptive dead-time control and is capable of supplying
up to 2A sourcing and 3A sinking current, allowing the
ISL78268 to support power stages designed for a wide range
of loads, from under 1A to over 25A.
• Wide input range 5V to 55V (switching); withstand 60V
(non-switching)
• Integrated 2A sourcing, 3A sinking MOSFET drivers
• Constant current regulation/limiting - dedicated average
current control loop
• Adjustable switching frequency or external synchronization
from 50kHz up to 1.1MHz
• Low shutdown current, IQ <1µA
• Peak current mode control with adjustable slope
compensation
• Selectable diode emulation mode for high efficiency at light
load
• Input and output OVP, cycle-by-cycle current limiting,
average current OCP, OTP
• Selectable hiccup or latch-off fault responses
• Pb-free 24 Ld 4x4 QFN package (RoHS compliant)
ISL78268’s fully synchronous architecture enables power
conversion with very high efficiency and improved thermal
performance over standard buck converters. The ISL78268 also
offers diode emulation mode for improved light load efficiency.
While ISL78268 is a peak current mode PWM controller, it
also includes a dedicated average output current modulation
loop, which achieves constant output current limiting for
applications such as battery charging, super-cap charging, and
temperature control systems where a constant current must
be provided.
• AEC-Q100 qualified
Applications
The ISL78268 supports switching frequencies from 50kHz to
1.1MHz allowing the user the flexibility to trade-off switching
frequency and efficiency against the size of external
components.
•
•
•
•
The ISL78268 offers comprehensive protection features. It
includes robust current protection with cycle-by-cycle peak
current limiting, average current limiting, and a selectable
hiccup or latch-off fault responses. In addition, it offers
protection against over-temperature, as well as input and
output overvoltages.
Automotive power
Telecom and industrial power supplies
General purpose power
Supercap charging
Related Literature
• AN1946, “ISL78268EVAL1Z Evaluation Board User Guide”
VIN
VIN
EN_IC
EN
PVCC
VCC
100
ISEN1P
95
ISEN1N
PVCC
90
BOOT
85
UG
FSYNC
PLL_COMP
ISL78268
VOUT
PH
LG
SLOPE
SS
SGND PGND
VIN = 36V
75
70
VIN = 55V
55
VCC
HIC/LATCH
VIN = 15V
60
FB
CLKOUT
VIN = 24V
80
65
ISEN2P
ISEN2N
COMP
EFFICIENCY (%)
IMON/DE
PVCC
POWER GOOD
PGOOD
50
VOUT = 12V, TA = +25°C
0
1
2
3
4
5
IOUT (A)
FIGURE 1. SIMPLIFIED TYPICAL APPLICATION SCHEMATIC
December 12, 2014
FN8657.3
1
FIGURE 2. EFFICIENCY CURVES (ISL78268EVAL1Z/DE MODE)
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL78268
Table of Contents
Related Literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Typical Application Schematics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Typical Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Operation Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synchronous Buck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adaptive Dead-Time Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Initialization and Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator and Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Soft-Start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap for High-side NMOS Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PWM Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Adjustable Slope Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Light Load Efficiency Enhancement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Average Constant Current Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Fault Monitoring and Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Internal 5.2V LDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20
20
20
20
21
21
22
22
23
23
24
25
25
26
27
Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Voltage Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Switching Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Inductor Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bootstrap Capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Loop Compensation Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
VCC Input Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Current Sense Circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
27
27
27
28
28
28
29
29
29
31
31
Layout Consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
About Intersil . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Package Outline Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
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FN8657.3
December 12, 2014
ISL78268
Pin Configuration
VCC
ISEN2P
ISEN2N
ISEN1P
ISEN1N
VIN
ISL78268
(24 LD 4x4 QFN)
TOP VIEW
24
23
22
21
20
19
SLOPE
1
18 BOOT
FB
2
17 UG
COMP
3
SS
4
15 LG
IMON/DE
5
14 PVCC
PGOOD
6
13 PGND
16 PH
7
8
9
10
11
12
FSYNC
SGND
EN
PLL_COMP
HIC/LATCH
CLKOUT
EPAD
Functional Pin Description
PIN NAME PIN #
DESCRIPTION
SLOPE
1
This pin programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE pin to GND. Please refer
to “Adjustable Slope Compensation” on page 24 for how to choose this resistor value.
FB
2
The inverting input of the transconductance amplifier. A resistor divider must be placed between the FB pin and the output rail to
set the output voltage.
COMP
3
The output of the transconductance amplifier. Place the compensation network between the COMP pin and GND for compensation loop
design.
SS
4
Use this pin to set up the desired soft-start time. A capacitor placed from SS to GND will set up the soft-start ramp rate and in turn
determine the soft-start time.
IMON/DE is a bifunctional pin as either the average current monitor/protection or switching mode selection (Diode Emulation (DE)
mode or Forced PWM mode).
1. If IMON/DE pin is connected to VCC (higher than VCC - 0.7V), the device operates in Forced PWM mode and the average current
monitoring/limiting feature is disabled.
2. If a resistor (and a filter capacitor in parallel) is connected between IMON/DE and GND, the device operates in DE mode and
the average current monitoring/limiting feature is enabled. A current which is proportional to the current sensed at ISEN2 is
sourced from the IMON/DE pin. With an R/C network at the IMON/DE pin to GND, the voltage at IMON/DE pin describes
average output current.
When average current monitoring/limiting feature is enabled and DE mode is selected;
1. If IMON/DE is higher than 2V, the device enters Average Current Protection mode with the hiccup/latch-off as the fault response.
2. If IMON/DE reaches to 1.6V, the device enters the Average Constant Current control loop.
3. If the IMON/DE pin voltage is lower than 1.6V (typ), the device operates as a normal buck regulator in DE mode.
IMON/DE
5
PGOOD
6
Provides an open-drain Power-Good signal. When the output voltage is within +15/-12% of the nominal output regulation point and
soft-start is completed, the internal PGOOD open-drain transistor is open. It will be pulled low once output UV/OV or input OV conditions
are detected. Requires pull-up resistor connecting to VCC.
FSYNC
7
The oscillator switching frequency is adjusted with a resistor from this pin to GND. The internal oscillator locks to the rising edge of
a square pulse waveform if this pin is driven by an external clock. There is a 325ns delay from the FSYNC pin’s input clock rising
edge to UG rising edge.
SGND
8
Signal ground pin; the reference of internal analog circuits. Connect this pin to a large quiet copper ground plane. In PCB layout
planning, avoid having switching current flowing into the SGND area (including the IC PAD that is connected to the quiet large copper
ground plane also).
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December 12, 2014
ISL78268
Functional Pin Description (Continued)
PIN NAME PIN #
DESCRIPTION
EN
9
This pin is a threshold-sensitive enable input for the controller. Connecting the power supply input to the EN pin through an
appropriate resistor divider provides a means to have input voltage UVLO. When EN pin is driven above 1.2V, the ISL78268 is active
depending on status of the internal POR, and pending fault states. Driving the EN pin below 1.1V will clear all fault states and the
ISL78268 will soft-start when reenabled.
PLL_COMP
10
This pin serves as the compensation node for the PLL. A second order passive loop filter connected between the PLL_COMP pin and
GND compensates the PLL feedback loop.
11
This pin is used to select either HICCUP or LATCHOFF response for faults including output overvoltage, VIN overvoltage, peak
overcurrent protection (OC2) and average overcurrent protection.
HIC/LATCH = HIGH to activate HICCUP fault response,
HIC/LATCH = LOW to have LATCHOFF fault response.
Either toggling EN pin or recycling VCC POR can reset the IC from LATCHOFF status.
12
This pin provides a clock signal to synchronize with another ISL78268. The rising edge signal on the CLKOUT pin is delayed 180° from the
rising edge of UG to facilitate 2-phase interleaved operation using two ICs.
HIC/LATCH
CLKOUT
PGND
13
This Power GND pin provides the return path for the low-side MOSFET drive. Note this pin carries the noisy driving current and the
trace connected to the low-side MOSFET and PVCC decoupling capacitors should be as short as possible. Any sensitive analog signal
trace should not share common traces with this driving return path. Connect this pin directly to the ground copper plane and put
several vias as close as possible to this pin.
PVCC
14
Output of the internal linear regulator that provides bias for both high-side and low-side drives. The PVCC operating range is 4.75V
to 5.5V. A minimum 4.7µF ceramic capacitor should be used between PVCC and PGND for noise decoupling purpose. This capacitor
provides a noisy driving current and its ground pad should have several vias connecting to the ground copper plane.
LG
15
The low-side MOSFET gate drive output.
PH
16
Phase node. Connect this pin to the source of the high-side MOSFETs and the drain of the low-side MOSFETs. This pin represents the
return path for the high-side gate drive.
UG
17
High-side MOSFET gate drive output.
BOOT
18
This pin provides bias voltage to the high-side MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive the external
N-channel MOSFET. Place a 1µF ceramic capacitor between the BOOT and PH pins, and a switching diode from PVCC to BOOT.
VIN
19
Connect input rail to this pin. This pin is connected to the input of the internal linear regulator, generating the power necessary to
operate the chip. It is recommended the DC voltage applied to the VIN pin does not exceed 55V when the IC is switching. VIN can
stand up to 60V when IC is not switching.
ISEN1N
20
The ISEN1N pin is a negative potential input pin of the first current sense amplifier (CSA1). This amplifier senses the signal on the
current-sense resistor placed in series with the high-side MOSFET. The sensed current information is used for peak current mode
control and overcurrent protection.
ISEN1P
21
The ISEN1P pin is a positive potential input pin of the first current sense amplifier (CSA1).
ISEN2N
22
The ISEN2N pin is a negative potential input pin of the second current sense amplifier (CSA2). This amplifier senses the continuous
output inductor current either by DCR sensing method or using a sense resistor in series with the inductor for more accurate sensing.
The sensed current signal is used for 3 functions:
- Accurately limiting the average output current for constant output current control
- Achieve diode emulation
- Achieve average OCP (comparator at IMON/DE pin with 2V reference)
ISEN2P
23
The ISEN2P pin is a positive potential input pin of the second current-sense amplifier (CSA2).
VCC
24
This pin provides bias power for the IC analog circuitry. An RC filter is recommended between this pin and the bias supply (range of
4.75V to 5.5V, typically from PVCC). A minimum 1µF ceramic capacitor should be used between VCC and GND for noise decoupling
purposes.
EPAD
Bottom thermal pad. It is not connected to any electrical potential of the IC. In layout it must be connected to a PCB large ground copper
plane that doesn’t contain noisy power flows. Put multiple vias (as many as possible) in this pad connecting to the ground copper plane
to help reduce the IC’s JA.
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December 12, 2014
ISL78268
Ordering Information
PART NUMBER
(Notes 1, 2, 3)
PART
MARKING
ISL78268ARZ
782 68ARZ
ISL78268EVAL1Z
Evaluation Board
TEMP. RANGE
(°C)
-40 to +125
PACKAGE
(RoHS Compliant)
24 Ld 4x4 QFN
PKG.
DWG. #
L24.4x4H
NOTES:
1. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL78268. For more information on MSL please see techbrief TB363.
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December 12, 2014
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Block Diagram
PGOOD
VIN/30
1/30
VIN
VREF_VINOV
5.2V
LDO
PVCC
+
Vin_OV
1.15VREF
-
+
-
VCC
PLL
POR
OVER
TEMP
Vo_OV
-
FB
0.87VREF
Vo_UV
HIC/LATCH
+
6
SS_DONE
EN
1.2V
FSYNC
EN_SW
CLOCK
INITIALIZATION
DELAY
3.4V
CLKOUT
ISLOPE
OC_AVG
SGND
VREF = 1.6V
+
+
+ Gm
-
-
FB
OC1
1.6V
ISEN1_OC2
93µA
+
-
ISEN1N
BOOT
112µA
ISEN1_OC1
UG
PH
PVCC
Q
PWM CONTROL
LG
R2
PGND
+
-
Gm
PGND
ZERO
CROSS
DETECTION
ISEN2_ZCD
SGND
IMON/DE
CSA1
112µA
S
R1
OC1
FAULT
AV = 1
70µA
CLOCK
VCC - 0.7V
+
-
SLOPE
ISEN1P
ISEN1
OC2
SLOPE
COMPENSATION
OC_AVG
FN8657.3
December 12, 2014
NEGATIVE
OC
2V
(ISEN2+68µA)/8
ISEN2P
AV = 1
ISEN2
ISEN2_Neg
-50µA
ISEN2N
CSA2
112µA
112µA
N.C.
EPAD
ISL78268
SOFT-START
LOGIC
SS
SGND
PLL_COMP
EN_SS
5µA
COMP
VCO
HICCUP/
LATCHOFF
ISL78268
Typical Application Schematics
VIN
CIN
VIN
EN
EN_IC
RSVCC
RSEN1
ISEN1N
CVCC
RBIAS1B
IMON/DE
CPVCC
DBT
CIMON
RBIAS1A
PVCC
PVCC
RIMON
RSET1A
CISEN1
VCC
PVCC
RSET1B
ISEN1P
BOOT
RFSYNC
CBOOT
FSYNC
Q1
UG
ISL78268
PLL_COMP
RPLLCMP
CPLLCMP2
L
PH
CPLLCMP1
SLOPE
ISEN2P
RCMP
FB
CSS
VCC
CLKOUT
RBIAS2B
RFB1
RBIAS2A
VCC
RPG
HIC/LATCH: Connect to
HIC/LATCH
: Connect
to
either
VCC for Hiccup
mode
eitherfor
VCC
for Latch-off
or GND
Latch-off
mode
mode or GND for Hiccup
mode
COUT
RSET2A
ISEN2N
SS
CCMP
RSET2B
CISEN2
COMP
VOUT
Q2
LG
RSLOPE
RSEN2
HIC/LATCH
RFB0
PGOOD
SGND
PGND
POWER GOOD
FIGURE 3. SYNCHRONOUS BUCK WITH CONSTANT AVERAGE I OUT
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FN8657.3
December 12, 2014
ISL78268
Typical Application Schematics
(Continued)
VIN
CIN
VIN
EN
EN_IC
RSVCC
RBIAS1B
BOOT
CBOOT
FSYNC
ISL78268
PLL_COMP
CPLLCMP1
SLOPE
ISEN2P
SS
FB
CSS
CLKOUT
RSET2B
HIC/LATCH
SGND
mode or GND for Hiccup
mode
VOUT
COUT
RSET2A
RBIAS2B
RFB1
RBIAS2A
VCC
RPG
HIC/LATCH: Connect to
HIC/LATCH
: Connect
to
either
VCC for Hiccup
mode
for Latch-off
VCC
or either
GND for
Latch-off
mode
RSEN2
Q2
CISEN2
ISEN2N
RCMP
VCC
L
LG
COMP
CCMP
Q1
UG
PH
RPLLCMP
RSLOPE
CPVCC
DBT
IMON/DE
CPLLCMP2
RBIAS1A
PVCC
PVCC
RFSYNC
RSEN1
ISEN1N
CVCC
VCC
IMON/DE : Connect to
VCC for forced PWM
mode
RSET1A
CISEN1
VCC
PVCC
RSET1B
ISEN1P
RFB0
PGOOD
PGND
POWER-GOOD
FIGURE 4. SYNCHRONOUS BUCK (FORCED PWM)
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FN8657.3
December 12, 2014
ISL78268
Typical Application Schematics
(Continued)
VIN
CIN
RSET1B
VIN
EN
EN_IC
RSVCC
CISEN1
VCC
PVCC
RSET1A
ISEN1P
CVCC
RBIAS1B
VCC
RBIAS1A
PVCC
PVCC
IMON/DE : Connect to VCC
for forced PWM mode
RSEN1
ISEN1N
CPVCC
DBT
IMON/DE
BOOT
RFSYNC
CBOOT
FSYNC
Q1
UG
ISL78268
PLL_COMP
RPLLCMP
CPLLCMP2
L
CPLLCMP1
SLOPE
ISEN2P
COMP
ISEN2N
RCMP
SS
VCC
Q2
LG
RSLOPE
CCMP
RDCRS
CDCRS
COUT
RSET2
RFB1
RBIAS2
FB
CSS
CLKOUT
VCC
RPG
HIC/LATCH: Connect to
HIC/LATCH : Connect to
either VCC for Hiccup mode
either V for Latch-off
or GND forCCLatch-off mode
mode or GND for Hiccup
mode
VOUT
PH
HIC/LATCH
RFB0
PGOOD
SGND
PGND
POWER-GOOD
FIGURE 5. SYNCHRONOUS BUCK WITH DCR SENSING
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FN8657.3
December 12, 2014
ISL78268
Absolute Maximum Ratings
Thermal Information
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V
PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V
BOOT, UG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +65V
Upper Driver Supply Voltage, VBOOT - VPH . . . . . . . . . . . . . . - 0.3V to +6.5V
PVCC, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to +6.5V
VISENxP - VISENxP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±0.6V
ISEN1P, ISEN1N, ISEN2P, ISEN2N . . . . . . . . . . . . . . . . . . . . . - 0.3V to +60V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3V to VCC + 0.3V
ESD Rating
Human Body Model (Tested per AEC-Q100-002) . . . . . . . . . . . . . . . . 2kV
Machine Model (Tested per AEC-Q100-003) . . . . . . . . . . . . . . . . . . . 200V
Charged Device Model (Tested per AEC-Q100-011). . . . . . . . . . . . . 750V
Latchup Rating (Tested per AEC-Q100-004) . . . . . . . . . . . . . . . . . . . 100mA
Thermal Resistance
JA (°C/W) JC (°C/W)
24 Ld 4x4 QFN Package (Notes 4, 5) . . . . . . . . .
39
3.5
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . . . . +150°C
Maximum Storage Temperature Range. . . . . . . . . . . . . . . . . -65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see TB493
Recommended Operating Conditions
VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V to 55V
PH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 55V
PVCC, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.75V to 5.5V
Upper Driver Supply Voltage, VBOOT - VPH . . . . . . . . . . . . . . . . . . 3.5V to 6V
ISEN1P, ISEN1N, ISEN2P, ISEN2N Common Mode Voltage . . . . 4V to 55V
ISEN1P to ISEN1N and ISEN2P to ISEN2N Differential Voltage . . . . ± 0.3V
Operational Ambient Temperature Range (Automotive). . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For JC, the “case temp” location is the center of the exposed metal pad on the package underside.
6. Unless otherwise noted, all voltages specified in this specification are refer to GND.
Electrical Specifications Refer to the Block Diagram (page 6) and Typical Application Schematics (page 7). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, EN = 5.0V, TA = -40°C to +125°C. Typicals are at TA = +25°C.
Boldface limits apply across the operating temperature range, -40°C to +125°C.
P
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
SUPPLY INPUT
Input Voltage Range
VIN
Input Supply Current (ENABLED Mode) to VIN
Pin
Input Supply Current (Shutdown Mode) to VIN
Pin
Input Leakage Current (Shutdown Mode) to
each of ISEN1P/ISEN1N/ISEN2P/ISEN2N Pins
IQ_SW
For VIN = 5V, the internal LDO dropout
(VIN - PVCC) <0.25V
5
RFSYNC = 40.2kΩ (fSW = 300kHz), LG = OPEN,
UG = OPEN
55
V
5
7
mA
IQ_NON-SW
FSYNC = 5V, LG = OPEN, UG = OPEN
2.7
3.5
mA
IQ_SD_VIN
EN = GND, VIN = 12V
0.15
0.5
µA
EN = GND, VIN = 55V
0.2
1
µA
0
1
µA
56
57.5
59.5
V
52.5
54.5
57
V
IQ_SD_ISENxP/N EN = GND, ISEN1P
(or ISEN1N/ISEN2P/ISEN2N) = 55V, VIN = 55V
-1
INPUT OVERVOLTAGE PROTECTION
VIN Switching-Disabled Threshold
EN = 5V, VIN rising
VIN Overvoltage Recovery Threshold
VIN Switching-Disabled Threshold Hysteresis
VIN Overvoltage Hiccup Retry Delay
From the time fault is removed to initiation of
soft-start
3
V
500
ms
INTERNAL LINEAR REGULATOR
LDO Output Voltage (PVCC Pin)
VPVCC
LDO Dropout Voltage (PVCC pin)
VDROPOUT
LDO Current Foldback Limit (PVCC Pin)
LDO Output Short Current (PVCC pin)
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10
VIN = 6V to 55V, CPVCC = 4.7µF from PVCC to
PGND, IPVCC = 10mA
5
VIN = 4.9V, CPVCC = 4.7µF from PVCC to PGND,
IVCC = 80mA
5.2
5.4
0.3
V
V
IOC_LDO
VIN = 6V, CPVCC = 4.7µF from PVCC to PGND
VPVCC = 2.5V
150
230
280
mA
IOCFB_LDO
VIN = 6V, CPVCC = 4.7µF from PVCC to PGND
VPVCC = 0V
100
150
220
mA
FN8657.3
December 12, 2014
ISL78268
Electrical Specifications Refer to the Block Diagram (page 6) and Typical Application Schematics (page 7). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, EN = 5.0V, TA = -40°C to +125°C. Typicals are at TA = +25°C.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
POWER-ON RESET (for both PVCC and VCC)
Rising VPVCC/VCC POR Threshold
VPORH_RISE
4.35
4.55
4.75
Falling VPVCC/VCC POR Threshold
VPORL_FALL
4.1
4.15
4.3
VPVCC/VCC POR Hysteresis
VPORL_HYS
Phase Lock Loop Locking Time
tPLL_DLY
From POR to Initiation of soft-start.
RPLLCMP = 3.24k, CPLLCMP1 = 6.8nF,
CPLLCMP2 = 1nF, RFSYNC = 40.2k, fSW = 300kHz
V
V
0.4
V
0.8
ms
EN
Enable Threshold
VENH
Rising
1.1
1.2
1.3
V
VENL
Falling
1.04
1.14
1.24
V
VEN_HYS
Input Resistance
Hysteresis
EN = 4V
60
3000
EN = 6V
5000
mV
8000
5
kΩ
kΩ
OSCILLATOR
PWM Switching Frequency
FOSC
RFSYNC = 249kΩ (0.1%)
47.5
50
52.5
kHz
RFSYNC = 40.2kΩ (0.1%)
285
300
315
kHz
1100
RFSYNC = 10kΩ (0.1%)
1036
1155
kHz
Switching Frequency Range
TA = +25°C, VIN = 12V
50
1100
kHz
Synchronization Range at FSYNC
TA = +25°C, VIN = 12V
50
1100
kHz
CLKOUT
High Level CLKOUT Output Voltage
CLKOUTH
Low Level CLKOUT Output Voltage
CLKOUTL
ICLKOUT = 500µA
VCC-0.4 VCC-0.1
V
ICLKOUT = -500µA
0.1
Output Pulse Width
CCLKOUT = 100pF
270
0.4
ns
V
Phase Shift from UG Rising Edge to CLKOUT
Pulse Rising Edge
UG = OPEN, CCLKOUT = OPEN
180
°
SYNCHRONIZATION (FSYNC pin)
Input High Threshold
VIH
Input Low Threshold
VIL
3.5
V
1.5
V
Input Pulse Width - Rise_To_Fall
20
20,000
ns
Input Pulse Width - Fall_To_Rise
20
20,000
ns
Delay from Input Pulse Rising to UG Rising Edge
UG = OPEN
325
ns
SOFT-START
Soft-Start Current
ISS
Soft-Start Pin PreBias Voltage Range
VSS_PRE
In prebias output condition; VSS_PRE = VFB
VFB = 500mV
Soft-Start PreBias Voltage Accuracy
Soft-Start Clamp Voltage
VSS = 0V
VSSCLAMP
4.5
5
5.5
µA
0
1.6
V
-25
25
mV
3
3.4
3.8
V
1.6
1.616
V
0.05
µA
REFERENCE VOLTAGE
Reference Accuracy
Measured at FB pin
1.584
FB Pin Input Bias Current
VFB = 1.6V
-0.05
ERROR AMPLIFIER
Transconductance Gain
2
COMP Output Impedance
CCMP = 100pF from COMP pin to GND
Unity Gain Bandwidth
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11
ms
10
MΩ
11
MHz
FN8657.3
December 12, 2014
ISL78268
Electrical Specifications Refer to the Block Diagram (page 6) and Typical Application Schematics (page 7). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, EN = 5.0V, TA = -40°C to +125°C. Typicals are at TA = +25°C.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
Slew Rate
TEST CONDITIONS
MIN
(Note 7)
CCMP = 100pF from COMP pin to GND
COMP Output Current Capability
TYP
MAX
(Note 7) UNITS
±2.5
V/µs
±300
COMP Output Voltage High
3.5
3.7
COMP Output Voltage Low
µA
3.9
V
0.3
V
SLOPE COMPENSATION SETTING
SLOPE Pin Voltage
500
SLOPE Accuracy
mV
RSLOPE = 20k (0.1%)
-30
30
%
RSLOPE = 40.2k (0.1%)
-30
30
%
Sinking into pin, EN = 5V,
VISENxN = VISENxP = 4V to 55V
90
CURRENT SENSE AMPLIFIER
ISENxN, ISENxP Common Mode Voltage Range
ISENxN, ISENxP Bias Current
4
ISENxBIAS
112
55
V
130
µA
ZERO CROSSING DETECTION
Zero Crossing Detection (ZCD) Threshold
VZCD_TH
RSEN Differential Voltage
RSET2A +RSET2B = 665Ω (0.1%)
RBIAS2A +RBIAS2B = 665Ω (0.1%)
See page 7 for RSET resistors
VOC1
RSEN Differential Voltage
RSET1A +RSET1B = 665Ω (0.1%)
RBIAS2A +RBIAS2B = 665Ω (0.1%)
See page 7 for RSET resistors
1.3
mV
OVERCURRENT PROTECTION
Peak Current Cycle-by-Cycle Limit Voltage
Threshold
47
45
62
UG = OPEN, from VOC1 threshold to UG falling
Peak Current Cycle-by-Cycle Limit Delay
Peak Current Hiccup/Latch-off Voltage
Threshold
32
VOC2
OC2 Hiccup/Latch-off Blanking Time
RSEN Differential Voltage
RSET1A +RSET1B = 665Ω (0.1%)
RBIAS2A +RBIAS2B = 665Ω (0.1%)
See page 7 for RSET resistors
60
mV
75
mV
50
Consecutive OC2 switching cycles
OC2 Hiccup Retry Delay
ns
3
cycles
500
ms
AVERAGE OVERCURRENT PROTECTION AND CONSTANT CURRENT LIMITING LOOP
VRSEN-CSA2 = 0mV, VISEN2N = 4V to 55V,
RSET2A +RSET2B = 665Ω (0.1%)
RBIAS2A +RBIAS2B = 665Ω (0.1%)
7.0
8.5
10.0
µA
IMONCSA2
VRSEN-CSA2 = 25mV, VISEN2N = 4V to 55V,
RSET2A +RSET2B = 665Ω (0.1%)
RBIAS2A +RBIAS2B = 665Ω (0.1%)
12
13.2
15
µA
IMONCSA2
VRSEN-CSA2 = 76mV, VISEN2N = 4V to 55V,
RSET2A +RSET2B = 665Ω (0.1%)
RBIAS2A +RBIAS2B = 665Ω (0.1%)
21
22.8
26
µA
Selected LATCHOFF/HICCUP response
1.9
2.0
2.1
IMON Offset Current
IMON Current Accuracy
Fault Threshold at IMON/DE Pin
OC_AVG Hiccup Retry Delay
500
Constant Current Limit Reference Accuracy
VREFCC
V
ms
1.584
1.6
1.616
V
240
300
360
ns
PWM CONTROLLER
Minimum UGATE ON Time
tMINON_UG
UGATE pulse width, UG = OPEN, LG = OPEN
Minimum UGATE OFF Time
tMINOFF_UG
VCOMP = 3.5V, UG = OPEN, LG = OPEN
Minimum LGATE ON Time
tMINON_LG
VCOMP = 3.5V, UG = OPEN, LG = OPEN
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12
285
140
175
ns
210
ns
FN8657.3
December 12, 2014
ISL78268
Electrical Specifications Refer to the Block Diagram (page 6) and Typical Application Schematics (page 7). Operating conditions unless
otherwise noted: VIN = 12V, VPVCC = 5.2V and VVCC = 5.2V, EN = 5.0V, TA = -40°C to +125°C. Typicals are at TA = +25°C.
Boldface limits apply across the operating temperature range, -40°C to +125°C. (Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 7)
TYP
MAX
(Note 7) UNITS
GATE DRIVERS
UG Source Resistance
RUGSRC
50mA source current; VBOOT - VPH = 4.5V
1.2
Ω
UG Source Current
IUGSRC
UG - PH = 2.5V; VBOOT - VPH = 4.5V
2.0
A
UG Sink Resistance
RUGPD
100mA sink current; VBOOT - VPH = 4.5V
0.65
Ω
IUGPD
UG - PH = 2.5V; VBOOT - VPH = 4.5V
3.0
A
LG Source Resistance
RLGSRC
50mA source current
1.0
Ω
LG Source Current
ILGSRC
LG - PGND = 2.5V
2.0
A
LG Sink Resistance
RLGPD
100mA sink current
0.55
Ω
LG Sink Current
ILGPD
LG - PGND = 2.5V
3.0
A
UG Sink Current
UG to PH Pull-Down Resistance
50
kΩ
LG to PGND Pull-Down Resistance
50
kΩ
BOOT-PH Refreshing Detection Threshold
3.1
3.3
3.5
V
BOOT-PH Refreshing Detection Threshold
Hysteresis
100
150
250
mV
Dead-Time Delay - UG Falling to LG Rising
tDT1
UG = OPEN, LG = OPEN
45
55
65
ns
Dead-Time Delay - LG Falling to UG Rising
tDT2
UG = OPEN, LG = OPEN
45
55
65
ns
111
115
118
%
108
112
115
%
OUTPUT OVERVOLTAGE DETECTION/PROTECTION (NOTE: FB_OVP response is selectable to be LATCHOFF or HICCUP)
FB Overvoltage Rising Trip Threshold
VFBOV_REF
Percentage of Reference Point, VFB = 1.6V
Selected LATCHOFF/HICCUP response.
FB Overvoltage Recovery Threshold
Overvoltage Threshold Hysteresis
FB Overvoltage Protection Delay
Overvoltage detection filter
FB_OV Hiccup Retry Delay
3
%
1
µs
500
ms
OUTPUT UNDERVOLTAGE DETECTION
FB Undervoltage Falling Threshold
VFBUV_REF
Percentage of reference point, VFB = 1.6V
FB Undervoltage Recovery Threshold
85
87.5
90
88
90.5
93
Undervoltage Hysteresis
3
%
%
%
POWER-GOOD MONITOR (OUTPUT OVERVOLTAGE, OUTPUT UNDERVOLTAGE, VIN OVERVOLTAGE)
PGOOD Leakage Current
PGOOD HIGH, VPGOOD = 5V
1
µA
PGOOD Low Voltage
PGOOD LOW, IPGOOD = 0.5mA
0.20
0.4
V
PGOOD Rising Delay -1
From VSS = 0.95*VREF to VSS = VSSCLAMP,
CSS = 15nF
5.6
ms
PGOOD Rising Delay -2
From VSS = VSSCLAMP to PGOOD HIGH
0.5
ms
PGOOD Falling Delay
Blanking filter time before transition
10
us
HIC/LATCH Pin
HIC/LATCH Input Pull-Down Current
HIC/LATCH Input High Threshold
VHIC/LATCH = 5V
0.8
1
2
2
µA
V
HIC/LATCH Input Low Threshold
0.8
V
OVER-TEMPERATURE PROTECTION
Over-Temperature Threshold
160
°C
Over-Temperature Recovery Threshold
145
°C
NOTE:
7. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
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FN8657.3
December 12, 2014
ISL78268
Typical Performance
All the performance curves are taken from the Evaluation Board (ISL78268EVAL1Z) unless otherwise noted.
1400
100
95
1200
90
EFFICIENCY (%)
fSW (kHz)
1000
800
600
85
VIN = 15V
VIN = 24V
80
VIN = 36V
75
70
VIN = 55V
65
400
60
200
0
55
0
50
100
150
200
250
50
300
VOUT = 12V, TA = +25°C
0
1
2
RFSYNC (kΩ)
95
95
90
90
VIN = 15V
EFFICIENCY (%)
EFFICIENCY (%)
100
80
VIN = 36V
75
VIN = 55V
70
65
85
65
55
2
3
4
5
VIN = 55V
70
55
1
50
0
IOUT (A)
FIGURE 8. EFFICIENCY (AT +125°C): DE MODE, VOUT = 12V,
L = 4.7µH, fSW = 300kΩ
2
3
4
5
FIGURE 9. EFFICIENCY (AT -40°C), DE MODE, VOUT = 12V,
L = 4.7µH, fSW = 300kΩ
VIN: 5V/DIV
VOUT : 2V/DIV
VOUT : 2V/DIV
PH: 10V/DIV
PH: 10V/DIV
IL: 2A/DIV
2µs/DIV
FIGURE 10. DE MODE: VIN = 36V, VOUT = 12V, IOUT = 2.5A,
L = 4.7µH, COUT = 98µF, fSW = 300kHz (CONTINUOUS
CONDUCTION OPERATION)
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1
IOUT (A)
VIN: 5V/DIV
IL: 2A/DIV
VIN = 15V
VIN = 36V
75
60
0
VIN = 25V
80
60
50
5
FIGURE 7. EFFICIENCY (AT +25°C): DE MODE, VOUT = 12V,
L = 4.7µH, fSW = 300kΩ
100
VIN = 25V
4
IOUT (A)
FIGURE 6. FREQUENCY SETTING (AT +25°C), VIN = 36V
85
3
14
2µs/DIV
FIGURE 11. DE MODE: VIN = 36V, VOUT = 12V, IOUT = 1.0A,
L = 4.7µH, COUT = 98µF, fSW = 300kHz
(DISCONTINUOUS CONDUCTION OPERATION)
FN8657.3
December 12, 2014
ISL78268
Typical Performance
All the performance curves are taken from the Evaluation Board (ISL78268EVAL1Z) unless otherwise noted. (Continued)
VIN: 5V/DIV
VIN: 5V/DIV
VOUT : 2V/DIV
VOUT : 2V/DIV
PH: 10V/DIV
PH: 10V/DIV
IL: 2A/DIV
IL: 2A/DIV
10µs/DIV
2µs/DIV
FIGURE 12. DE MODE: VIN = 36V, VOUT = 12V, IOUT = 30mA,
L = 4.7µH, COUT = 98µF, fSW = 300kHz (PULSE SKIP
OPERATION)
FIGURE 13. FORCED PWM MODE, VIN=36V, VOUT = 12V,
IOUT = 2.5A, L = 4.7µH, COUT = 98µF, fSW = 300kHz
VIN: 5V/DIV
VIN: 5V/DIV
VOUT : 2V/DIV
VOUT : 2V/DIV
PH: 10V/DIV
PH: 10V/DIV
IL: 2A/DIV
IL: 2A/DIV
2µs/DIV
FIGURE 14. FORCED PWM MODE, VIN = 36V, VOUT = 12V,
IOUT = 1.0A, L = 4.7µH, COUT = 98µF, fSW = 300kHz
10µs/DIV
FIGURE 15. FORCED PWM MODE, VIN = 36V, VOUT = 12V,
IOUT = 30mA, L = 4.7µH, COUT = 98µF, fSW = 300kHz
VCC: 5V/DIV
VCC: 5V/DIV
COMP: 1V/DIV
COMP: 1V/DIV
CLKOUT:
2V/DIV
CLKOUT:
2V/DIV
PH: 20V/DIV
PH: 20V/DIV
1ms/DIV
FIGURE 16. INITIALIZATION TO START-UP: DE MODE, VIN = 36V,
VOUT = 12V, IOUT = 2.5A, L = 4.7µH, C OUT = 98µF,
fSW = 300kHz
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1ms/DIV
FIGURE 17. INITIALIZATION TO START-UP: DE MODE, VIN = 36V,
VOUT = 12V, IOUT = 0A, L = 4.7µH, COUT = 98µF,
fSW = 300kHz
FN8657.3
December 12, 2014
ISL78268
Typical Performance
All the performance curves are taken from the Evaluation Board (ISL78268EVAL1Z) unless otherwise noted. (Continued)
VCC: 5V/DIV
VCC: 5V/DIV
COMP: 1V/DIV
COMP: 1V/DIV
CLKOUT:
2V/DIV
CLKOUT:
2V/DIV
PH: 20V/DIV
PH: 20V/DIV
1ms/DIV
1ms/DIV
FIGURE 18. INITIALIZATION TO START-UP: FORCED-PWM MODE,
VIN = 36V, VOUT = 12V, IOUT = 2.5A, L = 4.7µH,
COUT = 98µF, fSW = 300kHz
FIGURE 19. INITIALIZATION TO START-UP: FORCED-PWM MODE,
VIN = 36V, VOUT = 12V, IOUT = 0A, L = 4.7µH,
COUT = 98µF, fSW = 300kHz
VOUT : 5V/DIV
VOUT : 5V/DIV
SS: 1V/DIV
SS: 1V/DIV
FB: 1V/DIV
FB: 1V/DIV
PH: 10V/DIV
PH: 10V/DIV
500µs/DIV
500µs/DIV
FIGURE 20. SOFT-START (NON-PREBIASED): DE MODE, VIN = 36V,
VOUT = 12V, IOUT = 2.5A, L = 4.7µH, C OUT = 98µF,
fSW = 300kHz
FIGURE 21. SOFT-START (NON-PREBIASED): DE MODE, VIN = 36V,
VOUT = 12V, IOUT = 0A, L = 4.7µH, COUT = 98µF,
fSW = 300kHz
VOUT : 5V/DIV
VOUT : 5V/DIV
SS: 1V/DIV
SS: 1V/DIV
FB: 1V/DIV
FB: 1V/DIV
PH: 10V/DIV
PH: 10V/DIV
500µs/DIV
FIGURE 22. SOFT-START (NON-PREBIASED): FORCED-PWM MODE,
VIN = 36V, VOUT = 12V, IOUT = 2.5A, L = 4.7µH,
COUT = 98µF, fSW = 300kHz
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500µs/DIV
FIGURE 23. SOFT-START (NON-PREBIASED): FORCED-PWM MODE,
VIN = 36V, VOUT = 12V, IOUT = 0A, L = 4.7µH,
COUT = 98µF, fSW = 300kHz
FN8657.3
December 12, 2014
ISL78268
Typical Performance
All the performance curves are taken from the Evaluation Board (ISL78268EVAL1Z) unless otherwise noted. (Continued)
VOUT : 5V/DIV
VOUT : 5V/DIV
SS: 1V/DIV
SS: 1V/DIV
FB: 1V/DIV
FB: 1V/DIV
PH: 10V/DIV
PH: 10V/DIV
500µs/DIV
500µs/DIV
FIGURE 25. SOFT-START (PREBIASED): FORCED-PWM MODE,
VIN = 36V, VOUT = 12V, IOUT = 0A, L = 4.7µH,
COUT = 98µF, fSW = 300kHz
12.30
12.30
12.25
12.25
12.20
12.20
12.15
12.15
12.10
12.10
12.05
VOUT (V)
VOUT (V)
FIGURE 24. SOFT-START (PREBIASED): DE MODE, VIN = 36V,
VOUT = 12V, IOUT = 0A, L = 4.7µH, COUT = 98µF,
fSW = 300kHz
VIN = 55V
12.00
11.95
12.00
11.95
VIN = 36V
11.90
VIN = 24V
11.85
11.80
IOUT = 0.1A
IOUT = 1A
12.05
0
1
2
3
4
IOUT = 3A
11.90
VIN = 15V
11.85
5
11.80
10
20
30
IOUT (A)
FIGURE 26. LOAD REGULATION
VOUT (AC) : 500mV/DIV
40
50
60
VIN (V)
FIGURE 27. LINE REGULATION
VOUT (AC) :200mV/DIV
COMP:
500mV/DIV
(1.5V DC-FFSET)
COMP:
1V/DIV
IL: 2A/DIV
PH: 20V/DIV
500µs/DIV
FIGURE 28. TRANSIENT RESPONSE: DE MODE, VIN = 36V,
VOUT = 12V, IOUT = 0.1A TO 4.5A, L = 4.7µH,
COUT = 98µF
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IL: 2A/DIV
PH: 20V/DIV
500µs/DIV
FIGURE 29. TRANSIENT RESPONSE: DE MODE, VIN = 36V,
VOUT = 12V, IOUT = 1A TO 3A, L = 4.7µH, COUT = 98µF
FN8657.3
December 12, 2014
ISL78268
Typical Performance
All the performance curves are taken from the Evaluation Board (ISL78268EVAL1Z) unless otherwise noted. (Continued)
VOUT (AC) :200mV/DIV
VOUT (AC) :200mV/DIV
COMP:
500mV/DIV
(1.5V DC-OFFSET)
COMP: (1.5V DC-OFFSET)
500mV/DIV
IL: 3A/DIV
IL: 3A/DIV
PH: 10V/DIV
PH: 10V/DIV
500µs/DIV
500µs/DIV
FIGURE 30. TRANSIENT RESPONSE: FORCED-PWM MODE,
VIN = 36V, VOUT = 12V, IOUT = 0.1A TO 4.5A, L = 4.7µH,
COUT = 98µF
FIGURE 31. TRANSIENT RESPONSE: FORCED-PWM MODE,
VIN = 36V, VOUT = 12V, IOUT = 1A TO 3A, L = 4.7µH,
COUT = 98µF
6
PH:20V/DIV
560ms
5
4
VOUT (V)
SS: 2V/DIV
VOUT : 5V/DIV
3
2
1
0
IL: 3A/DIV
0
0.05
100ms/DIV
FIGURE 32. HICCUP: ACL, VIN = 30V, VOUT = 12V, RIMON = 156kΩ
IOUT: 1A/DIV
IOUT: 1A/DIV
IMON/DE: 0.5V/DIV
IMON/DE: 0.5V/DIV
PH: 20V/DIV
PH: 20V/DIV
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0.20
0.25
0.30
FIGURE 33. INTERNAL LDO LOAD REGULATION: VIN = 36V,
TA = +25°C
VOUT : 5V/DIV
20ms/DIV
0.15
IOUT (A)
VOUT : 5V/DIV
FIGURE 34. AVERAGE CONSTANT OUTPUT CURRENT CONTROL,
VIN = 20V, VOUT (SETTING) = 12V, CIMON = 1nF,
RIMON = 130kΩ, ACL = 4.05A, R L = 5.0Ω TO 2.0Ω,
FLOAD = 10Hz, DUTY OF LOAD CHANGE = 50%
0.10
20ms/DIV
FIGURE 35. AVERAGE CONSTANT OUTPUT CURRENT CONTROL,
VIN = 36V, VOUT (SETTING) = 12V, CIMON = 1nF,
RIMON = 130kΩ, ACL = 4.05A, RL = 5.0Ω TO 2.0Ω,
FLOAD = 10Hz, DUTY OF LOAD CHANGE = 50%
FN8657.3
December 12, 2014
ISL78268
Typical Performance
All the performance curves are taken from the Evaluation Board (ISL78268EVAL1Z) unless otherwise noted. (Continued)
VOUT : 5V/DIV
VOUT : 5V/DIV
IOUT: 1A/DIV
IOUT: 1A/DIV
IMON/DE: 0.5V/DIV
PH: 20V/DIV
IMON/DE: 0.5V/DIV
PH: 20V/DIV
20ms/DIV
20ms/DIV
FIGURE 36. AVERAGE CONSTANT OUTPUT CURRENT CONTROL,
VIN = 20V, VOUT (SETTING) = 12V, CIMON = 1nF,
RIMON = 130kΩ, ACL = 4.05A, R L = 2.3Ω, START-UP
WITH FIXED RL
FIGURE 37. AVERAGE CONSTANT OUTPUT CURRENT CONTROL,
VIN = 36V, VOUT (SETTING) = 12V, CIMON = 1nF,
RIMON = 130kΩ, ACL = 4.05A, RL = 2.3Ω, START-UP
WITH FIXED RL
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FN8657.3
December 12, 2014
ISL78268
Operation Description
The ISL78268 is an automotive graded (AEC-Q100 Grade-1)
single-phase synchronous buck controller with integrated
high/low side 2/3A MOSFET drivers. It supports a wide operating
input voltage range of 5V to 55V and up to 60V at VIN when not
switching. The device also provides the features of selectable
Diode Emulation mode for the higher efficiency operation in light
load conditions, average constant output current controls, and
several protection features such as input overvoltage protection,
output overvoltage protection, cycle-by-cycle current limit and
protections, and thermal protection. Details of the functions are
described in the following.
EN
1.2V
POR_R
PVCC/VCC
PLLCOMP
CLKOUT
UG
Synchronous Buck
LG
In order to improve the efficiency, the ISL78268 employs
synchronous buck architecture. In a synchronous buck, the LG
output drives the synchronous low-side MOSFET, which replaces
the freewheeling diode and improves the power losses by the
voltage drop of the freewheeling diode while the high-side
MOSFET is off. The LG signal is complementary to the UG signal.
The UG signal is powered from a charge pump that generates a
voltage between BOOT and PH. An external diode from PVCC to
BOOT charges an external capacitor between BOOT and PH when
LG is high and PH is low. The capacitor provides the power to
drive UG high. BOOT rises with PH and maintains the voltage to
drive UG as the bootstrap diode is reverse biased.
Adaptive Dead-Time Control
The UG and LG drivers are designed to have an adaptive
dead-time algorithm that optimizes operation with varying
MOSFET conditions. In this algorithm, the device detects the off
timing of external MOSFETs which is turning off via the gate
driver output voltage. The ISL78268 adds internally fixed 55ns
dead-time before turning on the target gate driver. This algorithm
helps to prevent shoot-through current at the switching of
external MOSFETs and also optimizes the total dead-time to
maximize the efficiency.
Operation Initialization and Soft-Start
Prior to the converter initialization, VIN and VCC need to be
supplied within the valid voltage range and the EN pin needs to be
biased to logic high. When these conditions are provided, the
controller begins soft-start. Once the output voltage is within the
proper window of output regulation, VPGOOD is asserted logic high.
Figure 38 shows the ISL78268 internal start-up timing diagram
from the power-up to soft-start and valid PGOOD assertion.
As shown on Figure 38, there are 5 time intervals before the
soft-start is initialized, they are specified as t1through t5. After
soft-start is initiated, there are 5 time intervals indicated as t5
through t10. The descriptions for each time interval are as
follows:
t1 - t2: The internal enable comparator holds the ISL78268 in
shutdown until the EN pin voltage (VEN) rises above 1.2V (typ) at
the time of t1. During t1 - t2 the internal LDO output voltage at the
PVCC pin (VPVCC) will gradually increase until t2 when it reaches
the internal Power-On Reset (POR) rising threshold which is
4.5V(typ).
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20
PH
COMP
COMP_Ramp_Offset
SS
VFB
VFB = 0.4V
PGOOD
t1 t2 t3
t4 t5 t6 t7
t8
t9 t10
FIGURE 38. CIRCUIT INITIALIZATION AND SOFT-START
t2 - t3: During t2 - t3 time, the ISL78268 will go through a
self-calibration process to determine the pin connections
(HIC/LATCH, IMON/DE) for the operation mode selections. The
time duration for t2 - t3 is typically 170µs.
t3 - t4: During this period, the ISL78268 will wait until the internal
PLL circuit is locked to the preset oscillator frequency set by the
resistor on FSYNC or the external clock at FSYNC. When PLL
locking is achieved at t4, the oscillator will generate output at the
CLK_OUT pin. The time duration for t3 - t4 depends on PLL_COMP
pin configuration. The PLL is compensated with a series
resistor-capacitor RPLLCMP, CPLLCMP1 from the PLL_COMP pin to
GND and a capacitor CPLLCMP2 from PLL_COMP to GND. Typical
values are RPLLCMP = 3.24kΩ, CPLLCMP1 = 6.8nF,
CPLLCMP2 = 1nF. With this PLL_COMP compensation, the time
duration for t3 - t4 is around 0.8ms.
t4 - t5: After the PLL locks the frequency at t4, the system is
preparing to soft-start. The ISL78268’s unique feature will
prebias the VSS based on VFB voltage during this time. The
duration time for t4 - t5 is around 50µs. During t4 - t5 drivers
remain off.
t5 - t6: After t5, the soft-start circuit starts to ramp up from the
prebiased VFB. At the same time, the COMP pin voltage starts to
ramp up also. The UG driver will be enabled at t5 . However,
before t6, COMP is still below the peak current mode control
ramp offset, the drivers will not be switching. During soft-start
period t5 - t10 , the device will operate with Diode Emulation
mode and keep LG driver off.
t6 - t7: If the FB voltage (VFB) is below 0.4V (typ), the device
operates at fixed minimum frequency (50kHz (typ)) with
minimum high-side MOSFET on-time. When VFB reaches
FN8657.3
December 12, 2014
ISL78268
t6 - t8: At t6, COMP is above the peak current mode control ramp
offset, the drivers starts switching. Output voltage ramps up
while FB voltage is following SS ramp during this soft-start
period. At t8, output voltage reaches the regulation level and FB
voltage reaches 1.6V (typ).
t7 - t10: SS pin voltage continues ramping up until it reaches SS
clamp voltage 3.4V (typ) at t9. The soft-start period will be
completed at t10 which is 0.5ms (typ) after the t9. When the
soft-start completes, the device operates in the operation mode
selected by the IMON/DE configuration. If the Forced PWM mode
is selected, the device operates in full synchronous rectification.
If the Diode Emulation Mode (DE Mode) is selected, the device
will be able to operate in DE mode, i.e., turn-off low-side MOSFET
when the inductor current reaches zero to prevent the negative
current and improves the efficiency. At the end of soft-start
period t10, the PGOOD open-drain follows the COMP and inductor
current ramp signal relations. Pin is released and will be pulled
up by the external resistor.
Enable
Clock Generator and Synchronization
INTERNAL CLOCK FREQUENCY SETTING
The switching frequency is determined by the selection of the
frequency-setting resistor, RFSYNC, connected from the FSYNC
pin to GND. Equation 1 and Figure 40 provide the relation
between RFSYNC and switching frequency. For stable operation of
the device, it is recommended to set the fSW between 50kHz to
1.1MHz.
R FSYNC = 2.5x  10 
10  0.5
–8
x ---------- – 5.0X10 
f

SW
(EQ. 1)
Where fSW is the switching frequency of the device.
1400
1200
1000
fSW (kHz)
0.4V (typ), the switching frequency will change to the target
frequency gradually and the high-side MOSFET on-time will be
controlled by the PWM control loop. If the prebiased FB voltage is
above 0.4V (typ), the device starts up with the target switching
frequency. If FB voltage is >0.4V the time t6 - t7 is negligible.
800
600
400
To enable the device, the EN pin needs to be driven higher than
1.2V (typ.) by the external enable signal or resistor divider
between VIN and GND. The EN pin has an internal 5MΩ (typ)
pull-down resistor. Also, this pin internally has a 5.2V (typ) clamp
circuit with 5kΩ (typ) resistor in series to prevent excess voltage
applied to the internal circuits. When applying the EN signal
using resistor divider from VIN, internal pull-down resistance
needs to be considered. Also the resistor divider ratio needs to be
adjusted as its EN pin input voltage may not exceed 5.2V.
To disable or reset all fault status, the EN pin needs to be driven
lower than 1.1V (typ). When the EN pin is driven to low, the
ISL78268 turns off all of the blocks to minimize the off-state
quiescent current.
200
0
0
50
100
150
200
250
300
RFSYNC (kΩ)
FIGURE 40. RFSYNC vs fSW
Figure 41 shows the block diagram of the Clock Generator block.
The FSYNC pin is biased at 0.5V (typ). The 0.5V at FSYNC creates
a constant current with RFSYNC. The current is fed to the internal
oscillator to generate the internal base clock. This internal base
clock is reshaped with the Phase Lock Loop (PLL) circuitry and
the output of PLL will be used as the main clock of the device.
VCC
VIN
VCC
FROM
EXTERNAL
EN CONTROL
EN
5k
5.2V
CLAMP
+
INTERNAL
OSCILLATOR
TO INTERNAL
CIRCUITS
INTERNAL BASE
CLOCK
-
+
5M
1.2V
0.5V
PLL
-
PFD
FSYNC
CLOCK
VCO
EXTERNAL
FIGURE 39. ENABLE BLOCK
RFSYNC
CLOCK
VIH(RISE) > 3.5V
VIL(FALL) < 1.5V
PLL_COMP
RPLLCMP
CPLLCMP2
CPLLCMP1
FIGURE 41. CLOCK GENERATOR AND EXTERNAL CLOCK
SYNCHRONIZATION BLOCK
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FN8657.3
December 12, 2014
ISL78268
SYNCHRONIZATION WITH EXTERNAL CLOCK
The ISL78268 contains a PLL circuitry and has frequency
synchronization capability by simply connecting the FSYNC pin to
an external square pulse waveform.
than 0.4V (typ) at the starting of soft-start, the device starts with
normal switching frequency from the beginning.
VCC
5µA
The PLL block detects the rising edge of external clock and
synchronizes it with the rising edge of UG. The delay time of UG
rising from the external clock rising edge is 325ns (typ).
SS
3.4V
CLAMP
CSS
The FSYNC pin has special thresholds to detect the external
clock. The input high level of external clock should be higher than
3.5V and low level should be lower than 1.5V.
SOFT-START
CONTROL
LOGIC
+
-
0.4V
SS_DONE
When continuous external clock pulse is applied while operating
with internal clock which is determined by RFSYNC, this device
synchronizes with the external clock gradually and continues its
switching. However, when the external clock is removed for a certain
period (~6ms), the device will stop its switching and restart from the
initialization/soft-start process after about a 50ms interval.
The PLL is compensated with a series connected resistor and
capacitor (RPLLCMP and CPLLCMP) from the PLL_COMP pin to
GND and a capacitor (CPLLCMP2) from PLL_COMP to GND. For
stable operation, recommended to set RPLLCMP = 3.24kΩ,
CPLLCMP1 = 6.8nF, CPLLCMP2 = 1nF. The typical lock time for this
case will be around 0.8ms.
The CLKOUT pin provides a square pulse waveform at the
switching frequency. The amplitude is GND to VCC with
270ns (typ) pulse width, and the rising edge is 180° shifted from
the rising edge of UG.
Soft-Start
Soft-start is implemented by an internal 5µA current source
charging the soft-start capacitor (CSS) at SS to GND. The voltage
on the SS pin controls the reference voltage for the FB pin during
soft-start. When starting up the system while the output voltage
is remaining (prebiased), a prebias circuit charges the CSS
capacitor to the same voltage as FB voltage before soft-start
begins. This allows more accurate correlation between the
soft-start ramp time and the output voltage.
Assuming no prebiased output condition, the soft-start ramp
time is:
C SS
t SS = V REF ----------5A
(EQ. 2)
Where VREF is the 1.6V reference.
Assuming no load condition, the average inductor current
IL_softstart to charge the output capacitors from 0V to final
regulation voltage within soft-start time tSS can be estimated as:
C OUT
I Lsoftstart = V OUT ------------t SS
(EQ. 3)
If start-up with full load is required, the total inductor average
current at the soft-start period is the sum of full load current and
IL_softstart. Based on this consideration, enough soft-start time
should be set to make sure overcurrent protection is not tripped.
At the beginning of soft-start, if the prebiased VFB voltage is
lower than 0.4V (typ), the device is forced to switch at 50kHz (typ)
with minimum on-time of high-side MOSFET. When VFB reaches
0.4V (typ) or higher, the device operates with normal switching
frequency and on-time. If the prebiased VFB voltage is higher
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SS_Prebias
TO PWM CONTROL
& PGOOD CONTROL
+
-
+
0.4V
VOUT
+
FB
+
COMP
Gm
TO PWM COMPARATOR
-
VREF = 1.6V
COMP
FIGURE 42. SOFT-START BLOCK
The soft-start period will be finished when the SS pin voltage
reaches its clamp voltage (3.4V typ) with a 0.5ms (typ) additional
interval. At the end of soft-start period, the pull-down of the
PGOOD pin will be released and this pin will be pulled up by
external resistor, which will be biased to VCC or external logic
supply level.
While in soft-start period, the device operates in Diode Emulation
mode to prevent undesired negative current at inductor from
output. In this period, regardless of the configuration of IMON/DE
pin, i.e., either Forced PWM mode or Diode Emulation mode is
selected, only the high-side MOSFET will be switched and
low-side MOSFET will be kept off.
Bootstrap for High-side NMOS Drive
To turn on the high-side MOSFET properly, the ISL78268 employs
a bootstrap circuit using an external boot capacitor (CBOOT) and
diode (DBT). At the time the high-side MOSFET turns off, to
maintain the current on the inductor, the PH node will go down to
GND level at low-side MOSFET turn on. While in this low-side
MOSFET on period, the diode connected from PVCC to boot
capacitor will be forward biased and charge up the boot
capacitor. When the low-side MOSFET is turned off and the
high-side MOSFET is turned on after dead-time, the PH node goes
up to VIN level and the BOOT pin bias is VIN + PVCC - VF to drive
the high-side driver circuitry.
BOOT REFRESHING
In order to keep sufficient supply voltage for the high-side driver
circuit operation, the ISL78268 has a boot-refreshing circuit.
When the boot capacitor voltage becomes lower than 3.3V (typ),
the low side transistor is forced to turn on with its minimum on
time to charge the boot capacitor. The boot refreshing will occur
at the beginning of soft-start and pulse skipping operation at very
light load conditions.
FN8657.3
December 12, 2014
ISL78268
Current Sensing
PVCC
BOOT
VIN
-
RC
+
TO BOOT
REFRESH
CONTROL
The ISL78268 has two current sense amplifiers: one for high-side
MOSFET peak current sensing for PWM control and overcurrent
protections, and the other for output inductor current sensing for
average current control and diode emulation timing control.
DBT
UG
LEVEL
SHIFT
3.3V
CBOOT
RSENSE
PH
PVCC
VOUT
L
PWM
SIGNAL
DEAD TIME
CONTROL
LG
TO CURRENT
SENSE AMP
PGND
FIGURE 43. OUTPUT BOOT CONTROL
MINIMUM OFF-TIME CONSIDERATION
To ensure the charging of the boot capacitor, the device has
internally fixed minimum off time (tminoff) for the high-side
MOSFET. Just after the high-side MOSFET turns off, the PH node
goes down to GND level and boot capacitor will be charged from
PVCC via an external diode (Schottky diode is recommended).
However, when an NMOS with large Qg is selected to support
heavy load application, the internally fixed tminoff may not be
enough to charge the boot capacitor sufficiently. For this case, it is
recommended to adjust the switching frequency or input voltage
as the system has sufficient off time of high-side transistor.
The current-sense amplifier (CSA1) is used to sense the inductor
current in the current-sense resistor placed in series with the
high-side MOSFET. The sensed current information (ISEN1) is
used for peak current mode control and overcurrent protection.
Peak current mode control is implemented using CSA1 in the
PWM control loop as described in “PWM Operation”.
The cycle-by-cycle peak current limit (OC1) is implemented by
comparing ISEN1 with an 70µA threshold. At the peak current
limit comparator threshold, the PWM pulse is terminated.
During an overload condition when ISEN1 reaches 93µA (OC2
threshold), the IC enters into latch-off or hiccup mode, which is
defined by the HIC/LATCH pin configuration. If latch-off mode is
selected, the device stops switching when OC2 is tripped and will
not restart until the EN or VIN is toggled. If Hiccup mode is
selected, the PWM is disabled for 500ms (typ) before beginning
a soft-start cycle. Three consecutive OC2 faults are required to
enter hiccup or latch-off. OC2 hiccup or latch-off is enabled
during soft-start and normal operating modes.
CURRENT SENSE AMPLIFIER 2 (CSA2)
PWM Operation
The switching cycle is defined as the time between UG pulse
initiation signals. The cycle time of the pulse initiation signal is
the inversion of the switching frequency set by the resistor
between the FSYNC pin and ground.
The ISL78268 uses peak current mode control. The PWM
operation is initialized by the clock from the oscillator. The
high-side MOSFET is turned on (UG) by the clock at the beginning
of a PWM cycle and the inductor current flows in the high-side
MOSFET and ramps up. When the sum of the current sense
signal (through ISEN1 current sense amplifier) and the slope
compensation signal reaches the error amplifier output voltage,
the PWM comparator is triggered and UG is turned off to shut
down the high-side MOSFET. The high-side MOSFET stays off until
the next clock signal comes for the next cycle.
After the high-side MOSFET is turned off, the low-side MOSFET
turns on with the fixed dead-time. The off timing of low-side
MOSFET is determined by either the next high-side on timing at
next PWM cycle or when the inductor current become zero if the
Diode Emulation mode is selected.
To prevent undesired shoot-through current at external high-side
and low-side MOSFETs, the device has adaptive dead-time
control and internally fixed dead-time. The internally fixed
dead-time is typically 55ns, for both high-side to low side and
low-side to high-side switching transition.
The output voltage is sensed by a resistor divider from VOUT to the
FB pin. The difference between the FB voltage and 1.6V (typ)
reference is amplified and compensated to generate the error
voltage signal at the COMP pin that is used for PWM generation
circuits.
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CURRENT SENSE AMPLIFIER 1 (CSA1)
23
The current-sense amplifier (CSA2) is used to sense the
continuous (not pulsing as in RSEN1) inductor current either by
DCR sensing method or using a sense resistor in series with the
inductor for more accurate sensing. The sensed current signal is
used for three functions:
• Average constant current control
• Diode emulation
• Average OC protection
The ISEN2P voltage is also used to monitor the minimum output
voltage. Under the overload condition (OC1) or under the average
constant current control, if the voltage become lower than about
1.2V (typ), the device stops switching and enters Latch-off/
Hiccup mode.
If these three functions are not required in the application, CSA2
should be connected to VCC (or VIN).
SENSE RESISTOR CURRENT SENSING
A sense resistor can be placed in series with the inductor. As
shown in Figure 44, the ISL78268 senses the voltage across the
sense resistor. CSA1 is used to sense the high-side MOSFET’s
current. The sense resistor is placed between the input
capacitors and the high-side MOSFET.
CSA2 is used to sense the inductor current. A sense resistor is
placed between the inductor and the output capacitors.
The voltage on the ISEN(n)P and ISEN(n)N of the current sense
amplifier are forced to be equal. The voltage across RSET(n) is
equivalent to the voltage drop across the RSEN(n) resistor. The
FN8657.3
December 12, 2014
ISL78268
resulting current into the ISEN(n)P pin is proportional (scaled) to
the current in RSEN(n). Equation 4 is derived as:
I SEN  n  = I R
SEN  n 
R SEN  n 
 ----------------------R SET  n 
(EQ. 4)
Where RSET(n) is the sum of RSET(n)A and RSET(n)B in Figure 44.
ISEN(n)P and ISEN(n)N have equal bias current (112µA typ)
therefore, the resistors RBIAS(n) and RSET(n) should be matched
to prevent offset.
To prevent noise injection from switching currents, it is
recommended to place a filter capacitor in between the RSET
resistors. Typically, 220pF ceramic capacitor is used when the
RSET(n) is 665Ω.
the voltage across the capacitor VCDCRS is equal to the voltage
drop across the DCR, i.e., proportional to the inductor current.
With the internal current sense amplifier, the capacitor voltage
VCDCRS is replicated across the sense resistor RSET2. Therefore,
the current flow into the ISEN2P pin is also proportional to the
inductor current. Equation 7 shows the relation between sensed
current ISEN2 and inductor current (IL) when DCR sensing is used.
DCR
I SEN2 = I L  ---------------R SET2
(EQ. 7)
VIN
CIN
+
TO
CSA1
RSEN1
-
VIN
ISEN1 + 112µA
CIN
+
RSEN1
-
RSET1A
RBIAS1A
UG
ISEN1P
RSET1B
RBIAS1B
AV = 1
ISEN1
CSA1
+
LG
DCR
ISEN1N
UG
112µA
112µA
L
L
+
RSEN2
-
+
-
IL
-
RSET2A
RBIAS2A
ISEN2P
-
R
CDCRS SET2
RBIAS2
AV = 1
ISEN2
CSA2
ISEN2N
ISEN2+112µA
VOUT
+
112µA
VOUT
LG
RDCRS
IL
ISEN2P
COUT
RSET2B
RBIAS2B
AV = 1
ISL78268 INTERNAL CIRCUITS
FIGURE 45. INDUCTOR DCR CURRENT SENSING
112µA
112µA
112µA
Adjustable Slope Compensation
ISL78268 INTERNAL CIRCUITS
FIGURE 44. SENSE RESISTOR CURRENT SENSING
INDUCTOR DCR SENSING
An inductor has a distributed resistance as measured by the DCR
(Direct Current Resistance) parameter.
The inductor DCR can be modeled as a lumped quantity, as
shown in Figure 45, Equation 5 shows the S-domain equivalent
voltage across the inductor VL.
V L = I L   s  L + DCR 
(EQ. 5)
A simple R-C network across the inductor can extract the DCR
voltage, as shown in Figure 45.
The voltage on the capacitor VCDCRS, can be shown to be
proportional to the channel current IL, see Equation 6.
L
 s  ----------- + 1   DCR  I L 
 DCR

V CDCRS = -----------------------------------------------------------------------------------1
R DCRS   ------------- + s  C DCRS + 1
R

SET
(EQ. 6)
If the CDCRS is selected so 2**fSW*CDCRS is much greater than
1/RSET, the 1/RSET will be negligible. Also, if the R-C network
components are selected such that the time constant
(RDCRS*CDCRS) matches the inductor time constant (L/DCR),
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112µA
CSA2
ISEN2N
COUT
112µA
112µA
ISEN2
24
A buck converter operating in peak current mode requires slope
compensation when the duty cycle is larger than 50%. It is
advisable to add slope compensation when the duty cycle is
approximately 30% or more since a transient load step can push
the duty cycle higher than the steady state level. When slope
compensation is too low, the converter can suffer from
subharmonic oscillation, which may result in noise emissions at
half the switching frequency. On the other hand,
overcompensation of the slope may reduce the phase margin.
Therefore, proper design of the slope compensation is needed.
The ISL78268 features adjustable slope compensation by
setting the resistor value RSLOPE from the SLOPE pin to GND.
Figure 46 shows the block diagram related to slope compensation.
For current mode control, in theory we need the compensation
slope mSL to be larger than 50% of the inductor current down
ramp slope mb.
Equation 8 shows the resistor value at SLOPE PIN to create a
compensation ramp.
6
Lx10 xR SET
R SLOPE = --------------------------------------------------   
KxV OUT xR SEN x1.5
(EQ. 8)
Where K is the selected gain of compensation slope over
inductor down slope. For example, K = 1 gives the RSLOPE value
generating a compensation slope equal to inductor current down
ramp slope. Theoretically, the K needs to be larger than 0.5 and
in general, more than 1.0 is used in the actual application.
FN8657.3
December 12, 2014
ISL78268
VIN
RSET ISEN1P
-
VRAMP
ISEN1
RSEN
+
RBIAS ISEN1N
RG
VCC
VOUT
ON WHILE
UG ON
ISL1 = n*ISLOPE
ISL
VSL
CSL
ON WHILE
LG ON
ISLOPE
+
Vrefsl = 0.5V
SLOPE
RSLOPE
mb
ISEN1
ISL
mSL
m
ma1
a1==Mam+am+SLmSL
VRAMP
VRAMP = (ISEN1+ISL)*RG
FIGURE 46. SLOPE COMPENSATION BLOCK
Light Load Efficiency Enhancement
For switching mode power supplies, the total loss is related to
both the conduction loss and the switching loss. The conduction
loss dominates at heavy load while the switching loss dominates
at light load condition. The ISL78268 has the option to be set in
cycle-by-cycle Diode Emulation mode and pulse skipping
features to enhance the light load efficiency.
IMON/DE is used to select DE (Diode Emulation) mode. When the
IMON/DE is connected to an external resistor or shorted to GND,
the DE mode is selected. Also, if IMON/DE pin is pulled up to VCC
level, the device operates in Forced PWM mode.
To achieve Diode Emulation mode, the current sense amplifier
CSA2 is used to sense the output inductor current either by DCR
sensing or an accurate current shunt resistor.
DIODE EMULATION AT LIGHT LOAD CONDITION
When DE mode is selected, if the inductor current reaches
discontinuous conduction mode (DCM) operation, the ISL78268
controller will turn off the low-side MOSFET and enter into Diode
Emulation mode.
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25
While in soft-start period until the PGOOD pull-down is released,
the low-side MOSFET is forced off (in either cases of DE mode or
Forced PWM mode is selected).
PULSE SKIPPING AT DEEP LIGHT LOAD CONDITION
If the converter enters Diode Emulation mode and the load is
further reduced, COMP voltage becomes lower than the
minimum threshold and the device skips the pulses to increase
the deep light load efficiency.
Average Constant Current Control
In normal PWM operation, the PWM pulse is terminated when
the sensed peak current reaches the error amplifier control
voltage. But some applications, such as charging a battery, may
desire constant output current control instead of output voltage
control. To support such requirements, ISL78268 provides the
average constant current control loop to control the average
current up to the FB regulated output voltage.
Average Constant Current control operates in the range of
approximately 25% to 100% of targeted output voltage. This is
due to the function described in the soft-start sequence (t6-t7)
when the FB voltage (VFB) is below 0.4V and the device operates
at 50kHz (typ) with minimum high-side MOSFET on time.
ISLOPE
ma
By utilizing the cycle-by-cycle diode emulation scheme, negative
current is prevented and the efficiency is improved from the
smaller RMS current in the power stage.
The IMON/DE pin serves to monitor the average current that is
used for average constant current control and Average
Overcurrent Protection (AVGOCP). The Current Sense Amplifier 2
(CSA2) output current, ISEN2, which is representing the output
current (see Figure 44 for RSEN and RSET positions) is sourcing
out from this pin. Equation 9 describes the relation between
output current (IOUT) and IMON/DE pin current (IIMON). An RC
network should be connected between the IMON/DE pin and
GND, such that the ripple current signal can be filtered out and
converted to a voltage signal to represent the averaged output
current. The time constant of the RC network should be on the
order of 10 to 100 times slower than the voltage loop bandwidth
so that the programmable current limit circuit does not interfere
with the control loop stability. The IMON/DE pin voltage VIMON
can be calculated as Equation 10.
R SEN

– 6
I IMON =  I OUT  -------------- + 68  10   0.125
R


SET
V IMON = I IMON  R IMON
(EQ. 9)
(EQ. 10)
When the IMON/DE pin voltage is at 1.6V (typ), the average
constant output current control loop on the device limits the on
time of high-side MOSFET to keep the output current constant.
While the average constant output current control is working, the
output voltage may become lower than preset output voltage
because of the lowered duty cycle. Equation 11 shows the RIMON
for the desired average output current.
12.8
R IMON = --------------------------------------------------------------R SEN
–6
I OUT  -------------- + 68  10
R SET
(EQ. 11)
FN8657.3
December 12, 2014
ISL78268
Fault Monitoring and Protection
OUTPUT OVERVOLTAGE DETECTION/PROTECTION
The ISL78268 actively monitors input/output voltage and current to
detect fault conditions. Fault monitors trigger protective measures
to prevent damage to the load.
The ISL78268 output overvoltage detection circuit is active after
soft-start is completed. The output voltage is monitored at the FB
pin and the output overvoltage trip point is set to 115% (typ) of
the FB reference voltage. If the output overvoltage condition is
longer than 10µs (typ) blanking time, the PGOOD pin is pulled
down and the controller moves into hiccup or latch-off mode.
PGOOD SIGNAL
The Power-Good indicator pin (PGOOD pin) is provided for fault
monitoring. The PGOOD pin is an open-drain logic output to
indicate that the soft-start period is completed and the output
voltage is within the specified range. An external pull-up resistor
(10kΩ to 100kΩ) is required to be connected between PGOOD
pin and VCC or external power supply (5.5V max). This pin is
pulled low during soft-start. The PGOOD pin is released high after
the voltage on SS pin reaches SS clamp voltage (3.4V typ) and
after a 0.5ms (typ) delay. PGOOD will be pulled low with a
10µs (typ) blanking filter when output UV, or OV fault, or VIN OV
fault occurs, or EN is pulled low. The PGOOD will be released high
after the 0.5ms (typ) delay when the above faults are removed.
HICCUP/LATCH-OFF OPERATION
As a response to fault detection, either Hiccup or Latch-off mode can
be selected by the configuration of the HIC/LATCH pin. When the
HIC/LATCH pin is pulled high (VCC), the fault response will be Hiccup
mode. When HIC/LATCH pin is pulled low (GND), the fault response
will be in Latch-off mode.
In Hiccup mode, the device will stop switching when a fault
condition is detected, and restart from soft-start after
500ms (typ). This operation will be repeated until fault conditions
are completely removed.
In Latch-off mode, the device will stop switching when a fault
condition is detected and be kept off even after fault conditions
are removed. Either toggling the EN pin or cycling VIN below the
POR threshold will restart the system.
INPUT OVERVOLTAGE PROTECTION
The recovery from output overvoltage in hiccup or latch-off is the
same as described in “Hiccup/Latch-off Operation”. If the hiccup
mode is selected, the output OV recovery threshold is 112% (typ)
of FB reference voltage.
CYCLE-BY-CYCLE PEAK OVERCURRENT
LIMITING/PROTECTION
ISL78268 features cycle-by-cycle peak overcurrent protections by
sensing the peak current at CSA1. The IC continuously compares
the CSA1 output current (ISEN1 calculated from Equation 4),
which is proportional to the current flowing at Current Sense
Resistor1 (RSEN1) with two overcurrent protection threshold,
70µA for OC1 and 93µA for OC2.
The OC1 and OC2 levels are defined as Equations 12 and 13.
I OC1 = 70  10
–6
I OC2 = 93  10
–6
R SET
 -------------R SEN
(EQ. 12)
R SET
 -------------R SEN
(EQ. 13)
If ISEN1 reaches OC1 threshold, the high-side MOSFET is turned
off. This reduces the converter duty cycle which decreases the
output voltage.
After OC1 protection has reduced the controller down to
minimum duty cycle, if the output current increases to the OC2
threshold for three consecutive switching cycles, the controller
disables the gate drivers and enters hiccup or latch-off mode.
The ISL78268 features overvoltage (OV) fault protection for the
input supply. When VIN is higher than 58V (typ), the UG and LG
gate drivers are disabled and the PGOOD pin is pulled low. There is
a 10µs (typ) transient filter to prevent noise spikes from triggering
input OV. The input OV response can be selected as latch-off or
hiccup.
The recovery from OC2 in hiccup or latch-off is the same as
described in the “Hiccup/Latch-off Operation”.
The recovery from output overvoltage in hiccup or latch-off is the
same as described in “Hiccup/Latch-off Operation”. If the hiccup
mode is selected, the input OV recovery threshold is below 55V (typ).
When the average constant current control loop is active, the IC
also provides average overcurrent protection.
OUTPUT UNDERVOLTAGE DETECTION
The ISL78268 detects the output undervoltage condition. The
output undervoltage threshold is set at 87.5% (typ) of the 1.6V FB
reference voltage. When the FB voltage is below the undervoltage
threshold for more than 10µs (typ), the PGOOD pin is pulled down.
If the output voltage rises above the undervoltage recovery
threshold of 90.5% (typ) of FB reference voltage, PGOOD is pulled
up after 0.5ms (typ) delay. During an undervoltage condition, the
device continues normal operation unless either OC2, AVGOCP,
Input OVP, or thermal shutdown protection is triggered.
The OC1 cycle-by-cycle current limiting and OC2 protection are
active during soft-start and normal operation period.
AVERAGE OVERCURRENT PROTECTION
When output current increases even the duty cycle becomes
minimum by the average constant current control loop, the
VIMON voltage rises above 1.6V. If VIMON reaches 2V (typ), the
ISL78268 stops gate drivers and enters into the hiccup mode.
This provides additional safety for the voltage regulator.
Equation 14 provides the RIMON value for the desired average
overcurrent protection level IOCPAVG.
16
R IMON = -------------------------------------------------------------------------R SEN
–6
I OCPAVG  -------------- + 68  10
R SET
(EQ. 14)
The average overcurrent protection (2V REF at IMON/DE) will not
be asserted until the soft-start period is completed.
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26
FN8657.3
December 12, 2014
ISL78268
NEGATIVE CURRENT LIMIT
When operating in Forced PWM mode operation in light load, the
negative current from the output capacitor to GND flows by the
turn on of the low-side MOSFET. The ISL78268 provides
cycle-by-cycle negative current limit to prevent excess negative
current. Equation 15 shows the peak negative current limit
(INEGLIM) threshold.
I NEGLIM = – 50  10
–6
R SET
 -------------R SEN
(EQ. 15)
The maximum LDO current can be supplemented with an
external PNP transistor as shown in Figure 48. The advantage is
that the majority of the power dissipation can be moved from the
ISL78268 to the external transistor. Choose RS to be 68Ω so that
the LDO delivers about 10mA when the external transistor begins
to turn on. The external circuit increases the minimum input
voltage to approximately 6.5V.
VIN
Rs
THERMAL PROTECTION
If the junction temperature reaches +160°C (typ), the ISL78268
switching will be disabled and enter into hiccup or latch-off
mode. When hiccup mode is selected, a 15°C (typ) hysteresis
insures that the device will not restart until the junction
temperature drops below +145°C (typ) in Hiccup mode.
VIN
ISL78268
PVCC
PVCC
Internal 5.2V LDO
The ISL78268 has an internal LDO with input at VIN and a fixed
5.2V/100mA output at PVCC. A 4.7µF, 10V or higher X5R or X7R
rated ceramic capacitor is recommended between PVCC to GND.
The output of this LDO is mainly used as the bias supply of the
internal circuitry. To provide a quiet power rail to the internal
analog circuitry, it is recommended to place RC filter between
PVCC and VCC. A 10Ω resistor between PVCC and VCC and at
least 1µF ceramic capacitor from VCC to GND are recommended.
OUTPUT CURRENT LIMITATION OF INTERNAL LDO
The internal LDO tolerates an input supply range of VIN up to 55V
(60V absolute maximum). However, the power losses at the LDO
need to be considered, especially when the gate drivers are
driving external MOSFETs with a large gate charge. At high VIN,
the LDO has significant power dissipation that may raise the
junction temperature where the thermal shutdown occurs.
Figure 47 shows the relationship between maximum allowed
LDO output current and input voltage. The curves are based on
+39°C/W thermal resistance JA of the package.
ILDO(MAX) (mA)
There are several ways to define the external components and
parameters of buck regulators. This section shows one example
of how to decide the parameters of the external components
based on the typical application schematics shown in Figure 4 on
page 8. In the actual application, the parameters may need to be
adjusted and also a few more additional components may need
to be added for the application specific noise, physical sizes,
thermal, testing and/or other requirements.
Output Voltage Setting
The output voltage (VOUT) of the regulator can be programmed by
an external resistor divider set from VOUT to FB and FB to GND.
VOUT can be defined as:
(EQ. 16)
In the actual application, the resistor value should be decided by
considering the quiescent current requirement and loop
response. Typically, between 10kΩ to 30kΩ will be used for the
RFB0.
TA = +25°C
120
Switching Frequency
100
80
TA = +75°C
60
40
TA= +125°C
20
0
Application Information
R FB1

V out = 1.6   1 + -------------
R

FB0
160
140
FIGURE 48. SUPPLEMENTING LDO CURRENT
5
10
15
20
25
30
35
VIN (V)
40
45
FIGURE 47. POWER DERATING CURVE
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27
50
55
60
Switching frequency may be determined by considering several
requirements such as system level response time, solution size,
EMC/EMI limitation, power dissipation and efficiency, ripple
noise level, minimum and maximum input voltage range, etc.
Higher frequency may improve the transient response and help
to minimize the solution size. However, this may increase the
switching losses and EMC/EMI concerns. Thus, a balance of
these parameters are needed when deciding the switching
frequency.
Once the switching frequency is decided, the frequency setting
resistor (RSYNC) can be determined by Equation 1.
FN8657.3
December 12, 2014
ISL78268
Output Inductor Selection
While the Buck Converter is operating in stable continuous
conduction mode (CCM), the output voltage and on-time of the
high-side transistor is determined by Equation 17:
t ON
V OUT = VIN  --------- = VIN  D
T
(EQ. 17)
Where T is the switching cycle (1/fSW) and D = tON/T is the
on-duty of the high-side transistor.
Under this CCM condition, the inductor ripple current can be
defined as Equation 18:
VIN – V OUT
V OUT
I L(P-P) = t ON  ----------------------------- = t OFF  ------------L
L
(EQ. 18)
(EQ. 19)
In general, once the inductor value is determined, the ripple
current varies by the input voltage. At the maximum input
voltage, the on-duty becomes minimum and the ripple current
becomes maximum. So, the minimum inductor value can be
estimated from Equation 20.
VIN max – V out V OUT
L min = --------------------------------------  -------------------f SW  IL max VIN max
(EQ. 20)
In DC/DC converter design, this ripple current will be set around
20% to 50% of maximum DC output current. A reasonable
starting point to adjust the inductor value will be around 30% of
the maximum DC output current.
Increasing the value of inductor reduces the ripple current and
thus ripple voltage. However, the large inductance value may
reduce the converter’s response time to a load transient. Also,
this reduces the ramp signal and may cause a noise sensitivity
issue.
Under stable operation, the peak current flow in the inductor will
be the sum of output current and 1/2 of ripple current.
I L(P-P)
I L = ---------------  I OUT
2
(EQ. 21)
This peak current at maximum load condition must be lower
than the saturation current rating of the inductor with enough
margin. In the actual design, the largest peak current may be
observed at the start-up or heavy load transient. Therefore, the
inductor’s size needs to be determined with the consideration of
these conditions. In addition, to avoid exceeding the inductor’s
saturation rating, it is recommended to set the OCP trip point
between the maximum peak current and the inductor’s
saturation current rating.
Output Capacitor
To filter the inductor current ripples and to have sufficient
transient response, an output capacitor is required.
The current mode control loop allows the usage of lower ESR
ceramic capacitors and thus enables smaller board layout.
Electrolytic and polymer capacitors may also be used.
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28
The following are equations for the required capacitance value to
meet the desired ripple voltage level. Additional capacitance may
be used to lower the ripple voltage and to improve transient
response.
For the ceramic capacitor (low ESR):
I L
V OUTripple = -----------------------------------8  f SW  C OUT
(EQ. 22)
Where IL is the inductor’s peak-to-peak ripple current, fSW is the
switching frequency and COUT is the output capacitor.
From the previous equations, the inductor value will be
determined as Equation 19:
VIN – V OUT V OUT
L = -----------------------------  ------------f SW
VIN
However, additional consideration may be needed to use the
ceramic capacitors. While the ceramic capacitor offers excellent
overall performance and reliability, the actual capacitance may
be considerably lower than the advertised value if used DC
biased condition. The effective capacitance can be easily 50%
lower than that of the rated value.
Required minimum output capacitance based on ripple current
will be:
I L
C OUTmin = --------------------------------------------8  f SW  V OUTmin
(EQ. 23)
If using electrolytic capacitors, the ESR will be the dominant
portion of the ripple voltage.
V OUTripple = I L  ESR
(EQ. 24)
So, to reduce the ripple voltage, reduce the ripple current with
increasing the inductor value or use multiple capacitors in
parallel to reduce the ESR.
The other factor which may affect the selection of the output
capacitor will be the transient response. To estimate the
capacitance value related to transient response, a good starting
point is to determine the allowable overshoot in VOUT if the load
is suddenly reduced. In this case, energy stored in the inductor
will be transferred to COUT and causing its voltage rise.
Equation 25 determines the required output capacitor value in
order to achieve a desired overshoot level relative to the
regulated voltage.
2
I OUT  L
C OUTtran = --------------------------------------------------------------------V OUTmax 2
2
V OUT    ------------------------ – 1
  Vout 

(EQ. 25)
Where VOUTmax/VOUT is the relative maximum overshoot
allowed during the removal of the load.
After calculating the required capacitance for both ripple and
transient needs, choose the larger of the calculated values as the
output capacitance. To keep enough capacitance over the biased
voltage and temperature range, a good quality capacitor such as
X7R or X5R is recommended.
Input Capacitor
Depending upon the system input power rail conditions, the
aluminum electrolytic type capacitor is normally used to provide
the stable input voltage and restrict the switching frequency
pulse current in small areas over the input trace for better EMC
performance. The input capacitor should be able to handle the
RMS current from the switching power devices.
FN8657.3
December 12, 2014
ISL78268
Ceramic capacitors must be used at the VIN pin of the IC and
multiple ceramic capacitors including 1µF and 0.1µF are
recommended.
Place these capacitors as close as possible to the IC.
Power MOSFET
Loop Compensation Design
The ISL78268 uses constant frequency peak current mode
control architecture with a Gm amp as the error amplifier. An
external current sense resistor is required for the peak current
sensing and overcurrent protection. Figures 49 and 50 show the
conceptual schematics and control block diagram, respectively.
The external MOSFETs that are driven by the ISL78268 controller
need to be carefully selected to optimize the design of the
synchronous buck regulator.
Since the ISL78268 input voltage can be up to 55V, the
MOSFET's BVdss rating needs to have enough voltage margin
against input voltage tolerance and PH node voltage transient
during switching.
As the UG and LG gate drivers are 5V output, the MOSFET VGS
need to be in this range.
The MOSFET should have low Total Gate Charge (Qgd), low
ON-resistance (rDS(ON)) at VGS = 4.5V (less than 10mΩ is
recommended) and small gate resistance (Rg <1.5Ω is
recommended). It is recommended that the minimum VGS
threshold should be higher than 1.2V but not exceeding 2.5V.
This is because of the consideration of large gate pull-down
current associated by gate-drain current at low side transistor
due to the high speed transition of Phase node and limitation of
maximum gate drive voltage, which is 5.2V (typ) for low-side
MOSFET and lower than 4.5V (typ) due to diode drop of boot
diode for high-side MOSFET.
FIGURE 49. CONCEPTUAL BLOCK DIAGRAM OF PEAK CURRENT
MODE CONTROLLED BUCK REGULATOR
Bootstrap Capacitor
The power required for high-side MOSFET drive is provided by the
boot capacitor connected between BOOT and PH pins. The
bootstrap capacitor can be chosen using Equation 26:
Q gate
C BOOT  -------------------dV BOOT
(EQ. 26)
FIGURE 50. CONCEPTUAL CONTROL BLOCK DIAGRAM
The output stage consists of a power stage (Gv(s)) which converts
the duty signal to output voltage and internal current loop stage
which converts duty to sense current.
Where Qgate is the total gate charge of the high-side MOSFET
and dVBOOT is the maximum droop voltage across the bootstrap
capacitor while turning on the high-side MOSFET.
POWER STAGE TRANSFER FUNCTIONS
Though the maximum charging voltage across the bootstrap
capacitor is PVCC minus the bootstrap diode drop (~4.5V), large
excursions below GND by PH node requires at least 10V rating for
this ceramic capacitor. To keep enough capacitance over the
biased voltage and temperature range, a good quality capacitor
such as X7R or X5R is recommended.
s
1
G v  s  = VIN   1 + ------------  --------------------------------------------------
 esr
s 2
s
1 + ------------------ +  -------
 
Q 
RESISTOR ON BOOTSTRAP CIRCUIT
In the actual application, sometimes a large ringing noise at the
PH node and the boot node are observed. This noise is caused by
energy stored in the body diode of the low-side MOSFET when it
is turning off, parasitic PH node capacitance due to PCB routing,
and the parasitic inductance. To reduce this noise, a resistor can
be added between the BOOT pin and the bootstrap capacitor. A
large resistor value will reduce the ringing noise at PH node but
limits the charging of the bootstrap capacitor during the low-side
MOSFET on-time, especially when the controller is operating at
very high duty cycle.
Transfer function at power stage (Gv(s)) can be expressed as
Equation 27.
p
n
(EQ. 27)
n
Where,
1
 esr = ----------------------------C OUT  R esr
C OUT
Q p  R OUT  -----------L
1
 n = ------------------------L  C OUT
Typically, up to 10Ω resistor is used for this purpose.
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ISL78268
INTERNAL CURRENT LOOP TRANSFER FUNCTIONS
Transfer function from control to inductor current (Gi(s)) is given
by Equation 28.
VIN
s
1
G i  S  = -------------   1 + -------  ----------------------------------------------------R OUT 
 o
s 2
s
1 + -------------------- +  -------

 n
Qp  n
(EQ. 28)
TOTAL TRANSFER FUNCTION FROM PWM
COMPARATOR TO POWER STAGE
The total transfer function from PWM to power stage including
internal current sense loop is expressed as Equation 31
(assuming Fm*Gi(s)*RS>>1).
s

1 + ------------
R
Fm
 esr
out
G T  s  = ----------------------------------------------  G v  s    ------------  ----------------------
 R
1 + Fm  Gi  s   Rs
s 
1 + ------- 
 s


o 
Where,
1
 o = ------------------------------C OUT  R OUT
C OUT
Q p  R OUT  -----------L
(EQ. 31)
Equation 31 shows that the system is a single order system.
Therefore, a simple Type-2 compensator can be used to stabilize
the system. In the actual application, however, an extra phase
margin will be provided by a Type-3 compensator.
1
 n = ------------------------L  C OUT
PWM COMPARATOR GAIN Fm
Vo
The PWM comparator gain Fm for peak current mode control is
given by Equation 29.
1
D
Fm = ---------------- = ------------------------------------- m a + m SL   T
V ramp
R1
RFB1
(EQ. 29)
C1
FB
Where mSL is the slew rate of the slope compensation and ma is
the inductor current slew rate while high-side MOSFET is on and
given as Equation 30.
+
-
COMP
Gm
Vref
RFB0
RCMP1
ROEA
CCMP2
CCMP1
He1
He2
VIN – V OUT
m a = R S  ----------------------------L
(EQ. 30
FIGURE 52. TYPE-3 COMPENSATOR
COMPENSATOR DESIGN
The transfer function at error amplifier and its compensation
network will be expressed as Equation 32.
Where RS is the gain of the current sense amplifier.
Vc
mSL+ma
TOTAL Vramp
g
Vramp
CONVERTED H/S
INDUCTOR CURRENT
m
ma
b
SLOPE COMPENSATION
ADDER
ton
toff
v COMP
H e2  s  = ----------------- = g m  Z COMP =
v FB
mSL
m
 1 + sR CMP C CMP1 R OEA
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------2
1 + s  R CMP C CMP1 + R EOA  C CMP1 + C CMP2   + C CMc2 C
R
R
S
CMP1 CMP OUT
If ROEA>>RCMP, CCMP1>>CCMP2, and ROEA = infinite, the
equation can be simplified as shown in Equation 33:
s
1 + ---------1
1 + s  R CMP  C CMP1
 z2
H e2  s  = g m  ------------------------------------------------------------------------------------------ = -------  -------------------s
s  C CMP1   1 + s  R CMP  C CMP2 
s
1 + --------- p2
(EQ. 33)
T
FIGURE 51. CONVERTED SENSE CURRENT WAVEFORM
(EQ. 32)
Where,
gm
 1 = -----------------C CMP1
1
 z2 = -------------------------------------R CMP  C CMP1
1
 p2 = -------------------------------------R CMP  C CMP2
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ISL78268
Current Sense Circuit
The transfer function at the feedback resistor network is:
s
1 + ---------R FB0
 z1
H e1  S  = ----------------------------------  -------------------R FB0 + R FB1
s
1 + --------- p1
(EQ. 34)
Where,
Layout Consideration
1
 z1 = ------------------------------------------C 1   R FB1 + R 1 
For DC/DC converter design, the PCB layout is a very important to
ensure the desired performance.
1
 p1 = ----------------------------------------------------------------------------------------------------------R FB1  R FB0 + R FB1  R 1 + R FB0  R 1
C 1  ----------------------------------------------------------------------------------------------R FB1 + R FB0
The total transfer function with compensation network and gain
stage will be expressed;
G open  s  = G T  s   H e1  s   H e2  s 
s

------------
R 1 + 
o
esr
G open  s  =  ------  ----------------------
R
s 
 s 1 + ------- 
o 

s

1 + ---------- 

 z1
R FB0
  ----------------------------------  --------------------
R
s 
+ R FB1
1 + ----------
 FBO
 p1

To set the current sense resistor, the voltage across the current
sense resistor should be limited to less than 0.3V. In a typical
application, it is recommended to set the voltage across the
current sense resistor between 30mV to 100mV for the typical
load current condition.
(EQ. 35)
s 

-
  1 + --------
1
z2 

 -------  ------------------- s
s 
1 + ----------

 p2

(EQ. 36)
From Equation 36, desired pole and zero locations can be
determined as in Equations 37 through 42.
o
1
f po = ----------- = ----------------------------------------------2
2    C OUT  R OUT
(EQ. 37)
 z1
1
f z1 = ----------- = ----------------------------------------------------------2
2    C 1   R FB1 + R 1 
(EQ. 38)
 z2
1
f z2 = ----------- = ----------------------------------------------------2
2    C CMc1  R CMP
(EQ. 39)
R FB1 + R FB2
 p1
f p1 = ----------- = ------------------------------------------------------------------------------------------------------------------2
2C 1  R FB1  R FB0 + R FB1  R 1 + R FB0  R 1 
(EQ. 40)
 p2
1
f p2 = ----------- = -----------------------------------------------------2
2    C CMP2  R CMP
(EQ. 41)
 esr
1
f zesr = ------------ = --------------------------------------------2
2    C OUT  R esr
(EQ. 42)
1. Place the input ceramic capacitor as close as possible to the
VIN pin and power ground connecting to the power MOSFET.
Keep this loop (input ceramic capacitor, IC VIN pin and
MOSFET) as small as possible to reduce voltage spikes
induced by the trace parasitics.
2. Place the input aluminum capacitor close to IC VIN and
ceramic capacitors.
3. Keep the phase node copper area small but large enough to
handle the load current.
4. Place the output ceramic and aluminum capacitors as close
as possible to the power stage components.
5. Place multiple vias under the thermal pad of the IC. The
thermal pad should be connected to the ground copper plane
with as large an area as possible in multiple layers to
effectively reduce the thermal impedance.
6. Place the 4.7µF decoupling ceramic capacitor at the VCC pin
and as close as possible to the IC. Put multiple vias close to
the ground pad of this capacitor.
7. Keep the bootstrap capacitor as close as possible to the IC.
8. Keep the driver traces as short as possible and try to avoid
using a via in the driver path to achieve the lowest impedance.
9. Place the current sense resistor as close as possible to the IC.
Keep the traces of current sense lines symmetric to each
other to avoid undesired switching noise injections.
In general, set fz2 and fz1 close to the fpo. Set fp2 near the
desired bandwidth. Set fp1 close to fzesr .
VCC Input Filter
To provide a quiet power rail to the internal analog circuitry, it is
recommended to place RC filter between PVCC and VCC. A 10Ω
resistor between PVCC and VCC and at least 1µF ceramic
capacitor from VCC to GND are recommended.
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to
make sure you have the latest Rev.
DATE
REVISION
December 12, 2014
FN8657.3
CHANGE
Functional Pin Description
Page 3, FSYNC description. Changed from: There is a 100ns delay from the FSYNC pin's….
To: There is a 325ns delay from the FSYNC pin's….
Page 4, PVCC description. Changed from: The PVCC operating range is 4V to 5.4V.
To: The PVCC operating range is 4.75V to 5.5V.
VCC description. Changed from: range of 4.7V to 5.5V, To: range of 4.75V to 5.5V,
Typical Application Schematics
Page 7, Left side changed from: HIC/LATCH:Connect to either Vcc for Latch-off mode or GND for Hiccup mode
To: HIC/LATCH:Connect to either Vcc for Hiccup mode or GND for Latch-off mode
Page 8, Left side changed from: HIC/LATCH:Connect to either Vcc for Latch-off mode or GND for Hiccup mode
To: HIC/LATCH:Connect to either Vcc for Hiccup mode or GND for Latch-off mode
Page 9, Left side changed from: HIC/LATCH:Connect to either Vcc for Latch-off mode or GND for Hiccup mode
To: HIC/LATCH: Connect to either Vcc for Hiccup mode or GND for Latch-off mode
Page 10, Electrical specification table, Test condition of Input Voltage range, changed from "For VIN = 5 the
internal ... " to "For VIN = 5V, the internal ..."
Elecrical Spec table, Page 11, Phase Lock Loop Locking Time
Changed in Test Conditions: Cpllcmp2=_nF to: Cpllcmp2=1nF
Page 20, Operation Description, 2nd sentence changed from: "such as input and output overvoltage protection,
output overvoltage protection" to: "input overvoltage protection, output overvoltage protection"
Page 22, SYNCHRONIZATION WITH EXTERNAL CLOCK, 2nd paragaph
Changed from : The delay time of UG rising from the external clock rising edge is 100ns (typ).
To: The delay time of UG rising from the external clock rising edge is 325ns (typ).
Page 25, Figure 46 changed: "ma1 = Ma + mSL" to: "ma1 = ma + mSL"
Page 30, EQ. 30 changed : mn=RS*…… to: ma=RS*……
Figure 51 changed: mb to: ma
August 1, 2014
FN8657.2
On page 1 in the Features section, updated the 5th bullet from “Low shutdown current, IQ<3µA” to “Low
shutdown current, IQ<1µA”.
In the “Block Diagram” on page 6, reversed the “+” and “-” Gm_Amp input polarity.
July 22, 2014
FN8657.1
Added Related Literature section on page 1 and ISL78268EVAL1Z information to the ordering information table
on page 5
June 18, 2014
FN8657.0
Initial Release.
About Intersil
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
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Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
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ISL78268
Package Outline Drawing
L24.4x4H
24 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 0, 09/11
2.50
4.00
20X 0.50
A
B
6
PIN 1
INDEX AREA
18
4.00
(4X)
6
24
19
PIN #1 INDEX AREA
1
Exp. DAP
2.50 ±0.05 Sq.
2.50
6
13
0.15
0.10 M C A B
24X 0.25 +0.07 4
-0.05
TOP VIEW
7
12
24X 0.40 ±0.10
0.25 min (4 sides)
BOTTOM VIEW
SEE DETAIL "X"
C
0.10 C
0.90 ±0.10
0 . 2 REF
5
C
SEATING PLANE
0.08 C
0 . 00 MIN.
0 . 05 MAX.
SIDE VIEW
DETAIL "X"
( 3.80 )
( 2.50)
NOTES:
1.
Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSEY14.5m-1994.
( 20X 0.50)
( 3.80 )
( 2.50 )
3.
Unless otherwise specified, tolerance : Decimal ± 0.05
4.
Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
(24X .25)
6.
( 24 X 0.60)
The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Compliant to JEDEC MO-220 VGGD-8
TYPICAL RECOMMENDED LAND PATTERN
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