UT54ACS165

Standard Products
UT54ACS165/UT54ACTS165
8-Bit Parallel Shift Registers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ Complementary outputs
‰ Direct overriding load (data) inputs
‰ Gated clock inputs
‰ Parallel-to-serial data conversions
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 16-pin DIP
- 16-lead flatpack
‰ UT54ACS165 - SMD 5962-96558
‰ UT54ACTS165 - SMD 5962-96559
PINOUTS
16-Pin DIP
Top View
The UT54ACS165 and the UT54ACTS165 are 8-bit serial shift registers that, when clocked, shift the data toward serial output QH. Parallelin access to each stage is provided by eight individual data inputs that
are enabled by a low level at the SH/LD input. The devices feature a
clock inhibit function and a complemented serial output QH .
Clocking is accomplished by a low-to-high transition of the CLK input
while SH/LD is held high and CLK INH is held low. The functions of
the CLK and CLK INH (clock inhibit) inputs are interchangeable. Since
a low CLK input and a low-to-high transition of CLK INH will also
accomplish clocking, CLK INH should be changed to the high level
only while the CLK input is high. Parallel loading is disabled when
SH/LD is held high. Parallel inputs to the registers are enabled while
SH/LD is low independently of the levels of CLK, CLK INH or SER
inputs.
CLK
2
15
CLK INH
E
3
14
D
F
4
13
C
G
5
12
B
H
QH
6
7
11
10
A
SER
VSS
8
9
QH
QB
QH
QH
h
X
L
X
L
X
X
a ... h
X
a
QA
b
QB
h
QH
QH
H
L
↑
H
X
H
QA
QG
QG
H
L
↑
L
X
L
QA
QG
QG
H
H
X
X
X
QA
QB
QH
QH
Note:
1. Qn = The state of the referenced output one setup time prior to the Low-toHigh clock transition.PINOUTS
1
16
VDD
CLK
2
15
CLK INH
E
3
14
D
F
G
4
5
13
12
C
H
QH
6
11
A
7
8
10
9
SER
QH
(1)
SH/LD
(15)
CLK INH
(2)
CLK
(10)
SER
(11)
A
(12)
B
(13)
C
(14)
D
(3)
E
(4)
F
(5)
G
(6)
H
INTERNAL OUTPUTS
OUTPUTS
QA
SH/LD
B
LOGIC SYMBOL
FUNCTION TABLE
L
H
VDD
VSS
The devices are characterized over full military temperature range of
-55°C to +125°C.
SH/ CLK CLK SER PARALLEL
LD INH
A ... H
16
16-Lead Flatpack
Top View
DESCRIPTION
INPUTS
1
SH/LD
SRG8
C1 (LOAD)
≥1
C2/
2D
1D
1D
1D
(9)
Q
(7) H
QH
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
1
LOGIC DIAGRAM
A
B
(11)
SH/LD
CLK INH
CLK
SER
C
(12)
D
(13)
E
(14)
F
(1)
G
(4)
(3)
H
(5)
(6)
(15)
(2)
(10)
S
S
S
S
S
S
S
S
C
C
C
C
C
C
C
C
(9)
D QA
D QB
DQ
D QD
D QE
D QF
D QG
(7)
D QH
R
R
R
R
R
R
R
R
C
2
QH
QH
OPERATIONAL ENVIRONMENT1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rads(Si)
SEU Threshold 2
80
MeV-cm2/mg
SEL Threshold
120
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-.3 to VDD +.3
V
TSTG
Storage Temperature range
-65 to +150
°C
TJ
Maximum junction temperature
+175
°C
TLS
Lead temperature (soldering 5 seconds)
+300
°C
ΘJC
Thermal resistance junction to case
20
°C/W
II
DC input current
±10
mA
PD
Maximum power dissipation
1
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
°C
3
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
VIL
VIH
IIN
PARAMETER
CONDITION
MIN
Low-level input voltage 1
ACTS
ACS
High-level input voltage 1
ACTS
ACS
MAX
UNIT
0.8
.3VDD
V
.5VDD
.7VDD
V
Input leakage current
ACTS/ACS
VIN = VDD or VSS
Low-level output voltage 3
ACTS
ACS
IOL = 8.0mA
IOL = 100μA
High-level output voltage 3
ACTS
ACS
IOH = -8.0mA
IOH = -100μA
Short-circuit output current 2 ,4
ACTS/ACS
VO = VDD and VSS
-200
Output current10
VIN = VDD or VSS
8
mA
(Sink)
VOL = 0.4V
Output current10
VIN = VDD or VSS
-8
mA
(Source)
VOH = VDD - 0.4V
Ptotal
Power dissipation 2, 8, 9
CL = 50pF
2.9
mW/
MHz
IDDQ
Quiescent Supply Current
VDD = 5.5V
10
μA
Quiescent Supply Current Delta
For input under test
1.6
mA
VOL
VOH
IOS
IOL
IOH
ΔIDDQ
ACTS
-1
1
μA
0.40
0.25
V
.7VDD
VDD - 0.25
V
200
mA
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
CIN
COUT
Input capacitance 5
ƒ = 1MHz @ 0V
15
pF
Output capacitance 5
ƒ = 1MHz @ 0V
15
pF
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All specifications valid for radiation dose ≤ 1E6 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 1, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPHL
CLK or CLK INH to QH or QH
2
21
ns
tPLH
CLK or CLK INH to QH or QH
2
18
ns
tPHL
SH/LD to QH or QH
2
21
ns
tPLH
SH/LD to QH or QH
2
18
ns
tPHL
H to QH
2
21
ns
tPLH
H to QH
2
17
ns
tPHL
H to QH
2
20
ns
tPLH
H to QH
2
18
ns
fMAX
Maximum clock frequency
71
MHz
tSU1
SER, SH/LD, CLKINH or CLK
Setup time before CLK ↑ or CLK INH ↑
7
ns
tSU2
Data setup time before SH/LD
7
ns
tH1
SER hold time after CLK or CLK INH ↑
2
ns
tH2
CLK INH hold time after CLK ↑
2
ns
tH33
Hold time for any input after SH/LD
2
ns
Minimum pulse width
CLK or CLK INH high
CLK or CLK INH low
SH/LD
7
ns
tW
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose ≤ 1E6 rads(Si).
3. Based on characterization, hold time (tH3) of 0ns for data pins A-H, can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested.
6
PACKAGING
Side-Brazed Packages
7
FLATPACK PACKAGES
8
UT54ACS165/UT54ACTS165: SMD
5962 * ***** ** * * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
C = 16-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96558 = UT54ACS165
96559 = UT54ACTS165
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-883 Test Method 1019 Condition A.
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Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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