UT54ACS193

Standard Products
UT54ACS193/UT54ACTS193
Synchronous 4-Bit Up-Down Dual Clock Counters
Datasheet
November 2010
www.aeroflex.com/logic
Similarly, the carry output (CO) produces a low-level pulse
while the count is maximum
FEATURES
‰ Look-ahead circuitry enhances cascaded counters
‰ Fully synchronous in count modes
‰ Parallel asynchronous load for modulo-N count lengths
‰ Asynchronous clear
‰ 1.2μ CMOS (ACTS193) and .6μm CRH CMOS process
(ACS193)
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 16-pin DIP
- 16-lead flatpack
‰ UT54ACS193 - SMD 5962-96566
‰ UT54ACTS193 - SMD 5962-96567
PINOUTS
16-Pin DIP
Top View
B
1
16
VDD
QB
2
15
A
QA
3
14
CLR
DOWN
UP
4
5
13
12
BO
CO
QC
QD
6
7
11
10
LOAD
C
VSS
8
9
D
16-Lead Flatpack
Top View
DESCRIPTION
The UT54ACS193 and the UT54ACTS193 are synchronous 4bit, binary reversible up-down binary counters. Synchronous
operation is provided by having all flip-flops clocked
simultaneously so that the outputs change coincident with each
other when instructed. Synchronous operation eliminates the
output counting spikes normally associated with asynchronous
counters.
The outputs of the four flip-flops are triggered on a low-to-highlevel transition of either count input (Up or Down). The direction of the counting is determined by which count input is pulsed
while the other count input is high.
B
1
16
VDD
QB
2
15
A
QA
3
14
CLR
DOWN
UP
4
5
13
12
BO
CO
QC
6
11
LOAD
QD
VSS
7
8
10
9
C
D
FUNCTION TABLE
The counters are fully programmable. The outputs may be preset
to either level by placing a low on the load input and entering
the desired data at the data inputs. The output will change to
agree with the data inputs independently of the count pulses.
Asynchronous loading allows the counters to be used as moduloN dividers by simply modifying the count length with the preset
inputs.
A clear input has been provided that forces all outputs to the low
level when a high level is applied. The clear function is independent of the count and the load inputs.
The counter is designed for efficient cascading without the need
for external circuitry. The borrow output (BO) produces a lowlevel pulse while the count is zero and the down input is low.
1
FUNCTION
CLOCK
UP
CLOCK
DOWN
CLR
LOAD
Count Up
↑
H
L
H
Count Down
H
↑
L
H
Reset
X
X
H
X
Load Preset
Input
X
X
L
L
LOGIC SYMBOL
(14)
CLR
(5)
UP
DOWN
LOAD
A
(4)
(11)
(15)
(1)
B
(10)
C
(9)
D
CTRDIV 16
CT=0
1CT=15
2+
G1
1G2
C3
2CT=0
(1)
3D
(2)
(4)
(8)
(12)
(13)
(3)
(2)
CO
BO
QA
QB
(6)
QC
(7)
QD
Note:
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM
(13)
(12)
A
BO
CO
(15)
DOWN (4)
SQ
C
RQ
UP (5)
(3) Q
A
B (1)
SQ
C
RQ
C
(2) Q
B
(10)
SQ
C
RQ
D (9)
CLR (14)
LOAD (11)
SQ
C
RQ
2
(6) Q
(7) Q
C
D
OPERATIONAL ENVIRONMENT1
PARAMETER
LIMIT
UNITS
Total Dose
1.0E6
rads(Si)
SEU Threshold 2
80
MeV-cm2/mg
SEL Threshold
120
MeV-cm2/mg
Neutron Fluence
1.0E14
n/cm2
Notes:
1. Logic will not latchup during radiation exposure within the limits defined in the table.
2. Device storage elements are immune to SEU affects.
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
-0.3 to 7.0
V
VI/O
Voltage any pin
-.3 to VDD +.3
V
TSTG
Storage Temperature range
-65 to +150
°C
TJ
Maximum junction temperature
+175
°C
TLS
Lead temperature (soldering 5 seconds)
+300
°C
ΘJC
Thermal resistance junction to case
20
°C/W
II
DC input current
±10
mA
PD
Maximum power dissipation
1
W
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the device at
these or any other conditions beyond limits indicated in the operational sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMIT
UNITS
VDD
Supply voltage
4.5 to 5.5
V
VIN
Input voltage any pin
0 to VDD
V
TC
Temperature range
-55 to + 125
°C
3
DC ELECTRICAL CHARACTERISTICS 7
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
VIL
VIH
IIN
PARAMETER
CONDITION
MIN
Low-level input voltage 1
ACTS
ACS
High-level input voltage 1
ACTS
ACS
MAX
UNIT
0.8
.3VDD
V
.5VDD
.7VDD
V
Input leakage current
ACTS/ACS
VIN = VDD or VSS
Low-level output voltage 3
ACTS
ACS
IOL = 8.0mA
IOL = 100μA
High-level output voltage 3
ACTS
ACS
IOH = -8.0mA
IOH = -100μA
Short-circuit output current 2 ,4
ACTS/ACS
VO = VDD and VSS
-200
Output current10
VIN = VDD or VSS
8
mA
(Sink)
VOL = 0.4V
Output current10
VIN = VDD or VSS
-8
mA
(Source)
VOH = VDD - 0.4V
Ptotal
Power dissipation 2, 8, 9
CL = 50pF
2.1
mW/
MHz
IDDQ
Quiescent Supply Current
VDD = 5.5V
10
μA
Quiescent Supply Current Delta
For input under test
1.6
mA
VOL
VOH
IOS
IOL
IOH
ΔIDDQ
ACTS
-1
1
μA
0.40
0.25
V
.7VDD
VDD - 0.25
V
200
mA
VIN = VDD - 2.1V
For all other inputs
VIN = VDD or VSS
VDD = 5.5V
CIN
COUT
Input capacitance 5
ƒ = 1MHz @ 0V
15
pF
Output capacitance 5
ƒ = 1MHz @ 0V
15
pF
4
Notes:
1. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, 50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
2. Supplied as a design limit but not guaranteed or tested.
3. Per MIL-PRF-38535, for current density ≤ 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF/MHz.
4. Not more than one output may be shorted at a time for maximum duration of one second.
5. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS at
frequency of 1MHz and a signal amplitude of 50mV rms maximum.
6. Maximum allowable relative shift equals 50mV.
7. All ACTS specifications are valid for radiation dose ≤ 1E6 rads(Si) and all ACS specifications are valid for radiation dose ≤ 5E5 rads(Si).
8. Power does not include power contribution of any TTL output sink current.
9. Power dissipation specified per switching output.
10. This value is guaranteed based on characterization data, but not tested.
5
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V 6, -55°C < TC < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPLH
UP to Qn
2
20
ns
tPHL
UP to Qn
2
24
ns
tPLH
UP to CO
2
13
ns
tPHL
UP to CO
2
16
ns
tPLH
DOWN to BO
2
13
ns
tPHL
DOWN to BO
2
16
ns
tPLH
DOWN to Qn
2
20
ns
tPHL
DOWN to Qn
2
24
ns
tPLH
LOAD to Qn
2
22
ns
tPHL
LOAD to Qn
2
23
ns
tPHL
CLR to Qn
2
22
ns
fMAX
Maximum clock frequency
56
MHz
tSU1
LOAD inactive setup time before UP or DOWN ↑
3
ns
tSU2
CLR inactive setup time before UP or DOWN↑
3
ns
tSU3
A, B, C, D setup time before LOAD ↑
6
ns
tH1
UP high hold time after DOWN ↑
20
ns
tH2
DOWN high hold time after UP ↑
20
ns
tH33
A, B, C, D hold time after LOAD ↑
2
ns
Minimum pulse width
UP high or low
DOWN high or low
LOAD low
CLR high
9
ns
tW
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All ACTS specifications are valid for radiation dose ≤ 1E6 rads(Si) and all ACS specifications are valid for radiation dose ≤ 5E5 rads(Si).
3. Based on characterization, data hold time (tH3) of 0ns can be assumed if data setup time (tSU3) is >10ns. This is guaranteed, but not tested.
6
PACKAGING
Side-Brazed Packages
7
FLATPACK PACKAGES
8
UT54ACS193/UT54ACTS193: SMD
5962 * ***** ** * * *
Lead Finish: (Notes 1 & 2)
A = Solder
C = Gold
X = Optional
Package Type:
X = 16-lead ceramic bottom-brazed dual-in-line Flatpack
C = 16-lead ceramic side-brazed dip
Class Designator:
Q = QML Class Q
V = QML Class V
Device Type:
01
Drawing Number:
96566 = UT54ACS193
96567 = UT54ACTS193
Total Dose: (Notes 3 & 4)
R = 1E5 rads(Si)
F = 3E5 rads(Si)
G = 5E5 rads(Si)
H = 1E6 rads(Si)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening. For prototype inquiries, contact factory.
4. Device type 02 is only offered with a TID tolerance guarantee of 3E5 rads(Si) or 1E6 rads(Si) and is tested in accordance with MIL-STD-883 Test Method 1019
Condition A and section 3.11.2. Device type 03 is only offered with a TID tolerance guarantee of 1E5 rads(Si), 3E5 rads(Si), and 5E5 rads(Si), and is tested in
accordance with MIL-STD-883 Test Method 1019 Condition A.
9
Aeroflex Colorado Springs - Datasheet Definition
Advanced Datasheet - Product In Development
Preliminary Datasheet - Shipping Prototype
Datasheet - Shipping QML & Reduced Hi-Rel
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