April 29, 2013 Radiation Performance Data Package RHD5900, RHD5901, RHD5902 Rev 2.0 DLA SMD Number: 5962-10241 Quad operational amplifiers Radiation Hardened by Design ELDRS: CMOS Immune Total dose: > 1 Mrad(Si) SEL Immune >100 MeV-cm /mg Neutron Displacement Damage >10 2 14 neutrons/cm 2 Prepared by: Aeroflex Plainview, Inc. 35 South Service Road Plainview, NY 11803 “Approved for release by DoD OSR under case number 12-S-1083” “Technical data exported in accordance with and under the authority of 22 CFR 125.4(b)(13),diversion contrary to U.S. law is prohibited” 1. Part Descriptions: 1.1 RHD5900: RadHard-by-Design Quad operational amplifier 1.1.1 Single power supply operation: 3.3V to 5.0V 1.1.2 Rail-to-Rail input and output range. 1.1.3 Gain Bandwidth: 5 MHz 1.2 RHD5901: RadHard-by-Design Quad operational amplifier 1.2.1 Single power supply operation: 3.3V to 5.0V 1.2.2 Rail-to-Rail input and output range 1.2.3 Enable pin for Hi-Z Output Control in amplifier pairs. 1.2.4 Gain Bandwidth: 5 MHz 1.3 RHD5902: RadHard-by-Design Quad operational amplifier, Fast 1.3.1 Single power supply operation: 3.3V to 5.0V 1.3.2 Rail-to-Rail input and output range 1.3.3 Enable pin for Hi-Z Output Control in amplifier pairs. 1.3.4 Gain Bandwidth: 35 MHz 2. Applicable Documents 2.1 2.2 2.3 Appendix A: Data Sheets: SCD5900 SCD5901 SCD5902 Quad Operational Amplifier Quad Operational Amplifier, Hi-Z Output Control Quad Operational Amplifier, Fast 2.4 Appendix B: Rad Report 11/30/2011 RADIATION TEST RESULTS Air Force Research Laboratory (AFRL) Low Energy X-Ray (LEXR) facility 2.5 Appendix C: DLA SMD: 5962-10241 MICROCIRCUIT, HYBRID, QUAD OPERATIONAL AMPLIFIER, RADIATION HARDENED 3. Radiation Performance 3.1 3.1.1 3.1.2 3.1.3 Version 3.0 Total Dose: 1 Mrads(Si), Dose rate = 50 - 300 rads(Si)/s The RHD Series utilizes a consistent set of design and layout techniques that achieve Total Ionizing Dose (TID) hardness in excess of 10 MRad(SiO2). The product line addresses the three main TID vulnerabilities: parasitic edge transistors, parasitic field transistors, and main transistor parameter shift. See Appendix B: RADIATION TEST RESULTS Every wafer lot is subjected to RLAT testing to 2 Mrad(Si) at dose rate of 50 - 300 rads(Si)/s. PAGE 2 3.2 ELDRS: Immune 3.2.1 The RHD5901-S is 100% CMOS and is ELDRS-free. 3.3 Neutron Displacement Damage: Immune 14 3.3.1 The RHD5901-S is 100% CMOS and is neutron displacement damage immune greater than 10 2 neutrons/cm . 3.4 Single Event Latchup (SEL): Immune 2 3.4.1 Single Event Latchup (SEL) immunity to greater than 100 MeV- cm /mg is achieved by using full 3.4.2 guardrings around all nMOS and pMOS devices. 2 Testing completed to 100 MeV- cm /mg with no latchup. 3.5 Single Event Upset (SEU): Immune 3.5.1 Analog IC’s have little or no latch content, making Single Event Upsets (SEU) either nonexistent, or present with negligible cross section. In complex mixed signal functions with appreciable sensitive area due to digital logic/latches, SEU are addressed with spatial redundancy techniques. Version 3.0 PAGE 3 Standard Products RadHard-by-Design RHD5900 Quad Operational Amplifier www.aeroflex.com/RHDseries April 8, 2013 FEATURES Single power supply operation (3.3V to 5.0V) or dual power supply operation (±1.65 to ±2.5V) Radiation performance - Total dose: >1Mrad(Si); Dose rate = 50 - 300 rads(Si)/s - ELDRS Immune - SEL Immune >100 MeV-cm2/mg - Neutron Displacement Damage >1014 neutrons/cm2 Rail-to-Rail input and output range Short Circuit Tolerant Full military temperature range Designed for aerospace and high reliability space applications Packaging – Hermetic ceramic SOIC - 16-pin, .411"L x .293"W x .105"Ht - Weight - 0.8 grams max Aeroflex Plainview’s Radiation Hardness Assurance Plan is DLA Certified to MIL-PRF-38534, Appendix G. GENERAL DESCRIPTION Aeroflex’s RHD5900 is a radiation hardened, single supply, quad operational amplifier in a 16-pin SOIC package. The RHD5900 design uses specific circuit topology and layout methods to mitigate total ionizing dose effects and single event latchup. These characteristics make the RHD5900 especially suited for the harsh environment encountered in Deep Space missions. It is guaranteed operational from -55°C to +125°C. Available screened in accordance with MIL-PRF-38534 Class K, the RHD5900 is ideal for demanding military and space applications. ORGANIZATION AND APPLICATION The RHD5900 amplifiers are capable of rail-to-rail input and outputs. Performance characteristics listed are for general purpose operational 5V CMOS amplifier applications. The amplifiers will drive substantial resistive or capacitive loads and are unity gain stable under normal conditions. Resistive loads in the low kohm range can be handled without gain derating and capacitive loads of several nF can be tolerated. CMOS device drive has a negative temperature coefficient and the devices are therefore inherently tolerant to momentary shorts, although on chip thermal shutdown is not provided. All inputs and outputs are diode protected. The devices will not latch with SEU events to above 100 MeV-cm2/mg. Total dose degradation is minimal to above 1Mrad(Si). Displacement damage environments to neutron fluence equivalents in the mid 1014 neutrons per cm2 range are readily tolerated. There is no sensitivity to low-dose rate (ELDRS) effects. SEU effects are application dependent. SCD5900 Rev G VCC +IN_A -IN_A +IN_B 4 3 A 7 OUT_B 10 OUT_C 16 OUT_D 5 6 +IN_C 12 -IN_C OUT_A 2 B -IN_B 1 C 11 +IN_D 14 D -IN_D 15 13 VEE FIGURE 1: BLOCK DIAGRAM OUT_A 1 16 OUT_D -IN_A 2 15 -IN_D +IN_A 3 14 +IN_D VCC 4 13 VEE +IN_B 5 12 +IN_C -IN_B 6 11 -IN_C OUT_B 7 10 OUT_C N/C 8 9 RHD5900 N/C 16-Pin SOIC FIGURE 2: PACKAGE PIN-OUT Notes: 1. Package and lid are electrically isolated from signal pads. 2. It is recommended that N/C or no connect pins (pins 8 and 9) and lid be grounded. This eliminates or minimizes any ESD or static buildup. SCD5900 Rev G 4/8/13 2 Aeroflex Plainview ABSOLUTE MAXIMUM RATINGS Parameter Range Units Case Operating Temperature Range -55 to +125 °C Storage Temperature Range -65 to +150 °C +150 °C Junction Temperature VCC - VEE +6.0 V VCC +0.4 VEE -0.4 V Lead Temperature (soldering, 10 seconds) 300 °C Thermal Resistance, Junction to Case,jc 7 °C/W 2,000 - 3,999 V 200 mW Supply Voltage Input Voltage ESD Rating (MIL-STD-883, Method 3015, class 2) Power @25°C NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating only; functional operation beyond the “Operation Conditions” is not recommended and extended exposure beyond the “Operation Conditions” may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter +VCC Power Supply Voltage VCM Input Common Mode Range Typical Units 3.3 to 5.0 V VCC to VEE V ELECTRICAL PERFORMANCE CHARACTERISTICS (TC = -55°C TO +125°C, +VCC = +5.0V -- UNLESS OTHERWISE SPECIFIED) Parameter Quiescent Supply Current Symbol 1/ ICCQ Conditions Min No Load Typ Max Units 4.7 5.5 mA Input Offset Voltage 1/ VOS -3 0.80 3 mV Input Offset Current 1/ IOS -100 10 100 pA TC = +25°C, -55°C 1/ -100 10 100 TC = +125°C -1000 100 1000 Input Bias Current IB pA Common Mode Rejection Ratio CMRR 70 90 dB Power Supply Rejection Ratio PSRR 70 90 dB Output Voltage High VOH ROUT=3.6K to GND Output Voltage Low VOL ROUT=3.6K to VCC Short Circuit Output Current 2/ Slew Rate 1/ Open Loop Gain 1/ Unity Gain Bandwidth 1/ V 4.9 0.1 V IO(SINK) VOUT to VCC -30 -75 mA IO(SOURCE) VOUT to VEE 45 55 mA SR RL = 8K, Gain = 1 2.0 3.3 V/uS AOL No Load 90 100 dB UGBW RL = 10K 4 6.5 MHz RL = 2K, f = 1.0KHz 84 Channel Separation 2/ Input-Referred Voltage Noise 2/ en F = 5 kHz Phase Margin 2/ m TC 25 °C, No Load dB 15 30 nV/ Hz Deg Notes: 1/ Specification derated to reflect Total Dose exposure to 1 Mrad(Si) @ +25°C. 2/ Not Tested. Shall be guaranteed by design, characterization, or correlation to other test parameters. SCD5900 Rev G 4/8/13 3 Aeroflex Plainview RHD5900 QUAD OPERATIONAL AMPLIFIER APPLICATION NOTES APPLICATION NOTE 1: DUAL POWER SUPPLY AMPLIFIER Inverting Amplifier Non Inverting Amplifier R2 VOUT = – VIN ------- R1 R2 VOUT = VIN 1 + ------- R1 +2.5V R1 R2 VIN VIN VOUT +2.5V R2 -2.5V VOUT -2.5V R1 APPLICATION NOTE 2: SINGLE POWER SUPPLY AMPLIFIER Inverting Amplifier Non Inverting Amplifier R2 VOUT = – VIN ------- R1 R2 VOUT = VIN 1 + ------- R1 R2 R1 +5V R3 +5V VIN VIN R3 +5V VBIAS +5V VBIAS VOUT VOUT R4 R2 R4 R1 Note: For VOUT DC @ mid range of common mode voltage range, VBIAS = 2.5/(1+R2/R1), VBIAS = +5*R4/(R3+R4) SCD5900 Rev G 4/8/13 4 Aeroflex Plainview APPLICATION NOTE 3: DIFFERENTIAL INPUT AMPLIFIER Differential Input Amplifier R4 R2 R2 VOUT = V2 --------------------- 1 + ------- – V1 ------- R3 + R4 R1 R1 R2 R1 V1 VCC VOUT R3 V2 VEE R4 Note: Package and lid are electrically isolated from signal pads. FIGURE 3: PACKAGE OUTLINE SCD5900 Rev G 4/8/13 5 Aeroflex Plainview ORDERING INFORMATION Model DLA SMD # Screening RHD5900-7 - Commercial Flow, +25°C testing only RHD5900-S - Military Temperature, -55°C to +125°C Screened in accordance with the individual Test Methods of MIL-STD-883 for Space Applications RHD5900-201-1S 5962-1024101KXC RHD5900-201-2S 5962-1024101KXA RHD5900-901-1S 5962H1024101KXC RHD5900-901-2S 5962H1024101KXA In accordance with DLA SMD Package 16-pin SOIC Package In accordance with DLA Certified RHA Program Plan to RHA Level "H", 1Mrad(Si) EXPORT CONTROL: EXPORT WARNING: This product is controlled for export under the International Traffic in Arms Regulations (ITAR). A license from the U.S. Department of State is required prior to the export of this product from the United States. Aeroflex’s military and space products are controlled for export under the International Traffic in Arms Regulations (ITAR) and may not be sold or proposed or offered for sale to certain countries. (See ITAR 126.1 for complete information.) PLAINVIEW, NEW YORK Toll Free: 800-THE-1553 Fax: 516-694-6715 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied. SCD5900 Rev G 4/8/13 Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 6 Standard Products RadHard-by-Design RHD5901 Quad Operational Amplifier Hi-Z Output Control www.aeroflex.com/RHDseries April 8, 2013 FEATURES Single power supply operation (3.3V to 5.0V) or dual power supply operation (±1.65 to ±2.5V) Radiation performance - Total dose: >1Mrad(Si); Dose rate = 50 - 300 rads(Si)/s - ELDRS Immune - SEL Immune >100 MeV-cm2/mg - Neutron Displacement Damage >1014 neutrons/cm2 Rail-to-Rail input and output range Enable pin to Enable/Disable amplifiers in pairs. Short Circuit Tolerant Full military temperature range Designed for aerospace and high reliability space applications Packaging – Hermetic ceramic SOIC - 16-pin, .411"L x .293"W x .105"Ht - Weight - 0.8 grams max Aeroflex Plainview’s Radiation Hardness Assurance Plan is DLA Certified to MIL-PRF-38534, Appendix G. GENERAL DESCRIPTION Aeroflex’s RHD5901 is a radiation hardened, single supply, quad operational amplifier with enable in a 16-pin SOIC package. The RHD5901 design uses specific circuit topology and layout methods to mitigate total ionizing dose effects and single event latchup. These characteristics make the RHD5901 especially suited for the harsh environment encountered in Deep Space missions. It is guaranteed operational from -55°C to +125°C. Available screened in accordance with MIL-PRF-38534 Class K, the RHD5901 is ideal for demanding military and space applications. ORGANIZATION AND APPLICATION The RHD5901 amplifiers are capable of rail-to-rail input and outputs. Performance characteristics listed are for general purpose operational 5V CMOS amplifier applications. The amplifiers will drive substantial resistive or capacitive loads and are unity gain stable under normal conditions. Resistive loads in the low kohm range can be handled without gain derating and capacitive loads of several nF can be tolerated. CMOS device drive has a negative temperature coefficient and the devices are therefore inherently tolerant to momentary shorts, although on chip thermal shutdown is not provided. All inputs and outputs are diode protected. The devices will not latch with SEU events to above 100 MeV-cm2/mg. Total dose degradation is minimal to above 1Mrad(Si). Displacement damage environments to neutron fluence equivalents in the mid 1014 neutrons per cm2 range are readily tolerated. There is no sensitivity to low-dose rate (ELDRS) effects. SEU effects are application dependent. The RHD5901 is configured with enable/disable control. Pairs of amplifiers are put in a power-down condition with their outputs in a high impedance state. Several useful operational amplifier configurations are supported where more than one amplifier can feed an output with others disabled. SCD5901 Rev F VCC +IN_A 3 -IN_A 2 4 1 A EN_AB OUT_A 8 5 +IN_B 6 -IN_B 7 B OUT_B 12 +IN_C 11 -IN_C C EN_CD 10 OUT_C 16 OUT_D 9 +IN_D 14 -IN_D 15 D 13 VEE FIGURE 1: BLOCK DIAGRAM OUT_A 1 16 OUT_D -IN_A 2 15 -IN_D +IN_A 3 14 +IN_D VCC 4 13 VEE +IN_B 5 12 +IN_C -IN_B 6 11 -IN_C OUT_B 7 10 OUT_C EN_AB 8 9 EN_CD RHD5901 16-Pin SOIC FIGURE 2: PACKAGE PIN-OUT Notes: 1. Package and lid are electrically isolated from signal pads. 2. EN_AB enables amplifiers A & B. EN_CD enables amplifiers C & D. SCD5901 Rev F 4/8/13 2 Aeroflex Plainview ABSOLUTE MAXIMUM RATINGS Parameter Range Units Case Operating Temperature Range -55 to +125 °C Storage Temperature Range -65 to +150 °C Junction Temperature +150 °C Supply Voltage VCC - VEE +6.0 V VCC +0.4 VEE -0.4 V Lead Temperature (soldering, 10 seconds) 300 °C Thermal Resistance, Junction to Case,jc 7 °C/W 2,000 - 3,999 V 200 mW Input Voltage ESD Rating (MIL-STD-883, Method 3015, class 2) Power @ 25°C NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating only; functional operation beyond the “Operation Conditions” is not recommended and extended exposure beyond the “Operation Conditions” may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter +VCC Power Supply Voltage VCM Input Common Mode Range Typical Units 3.3 to 5.0 V VCC to VEE V ELECTRICAL PERFORMANCE CHARACTERISTICS (TC = -55°C TO +125°C, +VCC = +5.0V -- UNLESS OTHERWISE SPECIFIED) Parameter Symbol Quiescent Supply Current 1/ ICCQ Conditions Min EN = 1, No Load EN = 0, Typ Max Units 4.7 5.5 mA 300 nA 2/ Input Offset Voltage 1/ VOS -3 0.80 3 mV Input Offset Current IOS -100 10 100 pA Tc = +25°C, -55°C 1/ -100 10 100 Tc = +125°C -1000 100 1000 1/ Input Bias Current IB pA Common Mode Rejection Ratio CMRR 70 90 dB Power Supply Rejection Ratio PSRR 70 90 dB Output Voltage High VOH ROUT = 3.6 Kohms to GND Output Voltage Low VOL ROUT = 3.6 Kohms to VCC Short Circuit Output Current Slew Rate 2/ 1/ SCD5901 Rev F 4/8/13 V 4.9 0.1 V IO(SINK) VOUT to VCC -30 -75 mA IO(SOURCE) VOUT to VEE 45 55 mA RL = 8K, Gain = 1 2.0 SR 3 3.3 V/uS Aeroflex Plainview ELECTRICAL PERFORMANCE CHARACTERISTICS (continued) (TC = -55°C TO +125°C, +VCC = +5.0V -- UNLESS OTHERWISE SPECIFIED) Parameter Symbol Open Loop Gain 1/ AOL UGBW Unity Gain Bandwidth 1/ Input Voltage - Enable (EN_AB, EN_CD) Input Current - Enable (EN_AB, EN_CD) Conditions Min Typ No Load 90 100 dB RL = 10K 4 6.5 MHz VHI High (Enabled) VLO Low (Disabled) Max V 3.5 IEN Channel Separation 2/ RL = 2K, f = 1.0KHz Input-Referred Voltage Noise 2/ en F = 5 kHz Phase Margin 2/ m Tc = +25°C, No load Units 1.5 V 10 nA dB 84 15 nV/ Hz Deg 30 Notes: 1/ Specification derated to reflect Total Dose exposure to 1 Mrad(Si) @ +25°C. 2/ Not tested. Shall be guaranteed by design, characterization, or correlation to other test parameters. SWITCHING CHARACTERISTICS (TC = -55°C TO +125°C, +VCC = +5.0V -- UNLESS OTHERWISE SPECIFIED) Symbol Parameter Conditions Min Max Units Output Delay (Enabled) 2/ tONEN 500 ns Output Delay (Disabled) 2/ tOFFEN 100 ns VCC ENABLES (EN_AB or EN_CD) 50% GND tONEN VOUT (VOUT_A&B or VOUT_C&D) VCC HI Z HI Z GND tOFFEN FIGURE 3: RHD5901 SWITCHING DIAGRAM SCD5901 Rev F 4/8/13 4 Aeroflex Plainview RHD5901 QUAD OPERATIONAL AMPLIFIER APPLICATION NOTES APPLICATION NOTE 1: DUAL POWER SUPPLY AMPLIFIER Inverting Amplifier Non Inverting Amplifier R2 VOUT = – VIN ------- R1 R2 VOUT = VIN 1 + ------- R1 EN R1 R2 +2.5V VIN VIN EN VOUT +2.5V R2 -2.5V VOUT -2.5V R1 APPLICATION NOTE 2: SINGLE POWER SUPPLY AMPLIFIER Inverting Amplifier Non Inverting Amplifier R2 VOUT = – VIN ------- R1 R2 VOUT = VIN 1 + ------- R1 R2 +5V EN R1 R3 +5V VIN VIN R3 +5V Vbias EN +5V Vbias VOUT VOUT R4 R2 R4 R1 Note: For VOUT DC @ mid range of common mode voltage range, VBIAS = 2.5/(1+R2/R1), VBIAS = +5*R4/(R3+R4) SCD5901 Rev F 4/8/13 5 Aeroflex Plainview APPLICATION NOTE 3: DIFFERENTIAL INPUT AMPLIFIER APPLICATION NOTE 4: MULTIPLE AMPLIFIERS Differential Input Amplifier Multiple Amplifiers - Selectable Output R4 R2 R2 VOUT = V2 --------------------- 1 + ------- – V1 ------- R3 + R4 R1 R1 +5V R2 R1 V1 A/B VCC V1 VOUT R3 ENV1 V2 VOUT VEE R4 V2 EN C/D Note: Package and lid are electrically isolated from signal pads. FIGURE 4: PACKAGE OUTLINE SCD5901 Rev F 4/8/13 6 Aeroflex Plainview ORDERING INFORMATION Model DLA SMD # Screening RHD5901-7 - Commercial Flow, +25°C testing only RHD5901-S - Military Temperature, -55°C to +125°C Screened in accordance with the individual Test Methods of MIL-STD-883 for Space Applications RHD5901-201-1S 5962-1024102KXC RHD5901-201-2S 5962-1024102KXA RHD5901-901-1S 5962H1024102KXC RHD5901-901-2S 5962H1024102KXA In accordance with DLA SMD Package 16-pin SOIC Package In accordance with DLA Certified RHA Program Plan to RHA Level "H", 1Mrad(Si) EXPORT CONTROL: EXPORT WARNING: This product is controlled for export under the International Traffic in Arms Regulations (ITAR). A license from the U.S. Department of State is required prior to the export of this product from the United States. Aeroflex’s military and space products are controlled for export under the International Traffic in Arms Regulations (ITAR) and may not be sold or proposed or offered for sale to certain countries. (See ITAR 126.1 for complete information.) PLAINVIEW, NEW YORK Toll Free: 800-THE-1553 Fax: 516-694-6715 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied. SCD5901 Rev F 4/8/13 Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 7 Standard Products RadHard-by-Design RHD5902 Quad Operational Amplifier High Speed with Enables www.aeroflex.com/RHDseries March 25, 2013 FEATURES Single power supply operation (3.3V to 5.0V) or dual power supply operation (±1.65 to ±2.5V) Radiation performance - Total dose: > 1 Mrad(Si); Dose rate = 50 - 300 rads(Si)/s - ELDRS Immune - SEL Immune > 100 MeV-cm2/mg - Neutron Displacement Damage > 1014 neutrons/cm2 Unity Gain Bandwidth 35 MHz Typical Rail-to-Rail input and output range Enable pin to Enable/Disable amplifiers in pairs. Short Circuit Tolerant Full military temperature range Designed for aerospace and high reliability space applications Packaging – Hermetic ceramic SOIC - 16-pin, .411"L x .293"W x .105"Ht - Weight - 0.8 grams max Aeroflex Plainview’s Radiation Hardness Assurance Plan is DLA Certified to MIL-PRF-38534, Appendix G. GENERAL DESCRIPTION Aeroflex RHD5902 is a radiation hardened, single supply, high speed quad operational amplifier with enable in a 16-pin SOIC package. The RHD5902 design uses specific circuit topology and layout methods to mitigate total ionizing dose effects and single event latchup. These characteristics make the RHD5902 especially suited for the harsh environment encountered in Deep Space missions. It is guaranteed operational from -55°C to +125°C. Available screened in accordance with MIL-PRF-38534 Class K, the RHD5902 is ideal for demanding military and space applications. ORGANIZATION AND APPLICATION The RHD5902 amplifiers are capable of rail-to-rail input and outputs. Performance characteristics listed are for general purpose operational 5V CMOS amplifier applications. The amplifiers will drive substantial resistive or capacitive loads and are unity gain stable under normal conditions. Resistive loads in the low kohm range can be handled without gain derating and capacitive loads of several nF can be tolerated. CMOS device drive has a negative temperature coefficient and the devices are therefore inherently tolerant to momentary shorts, although on chip thermal shutdown is not provided. All inputs and outputs are diode protected. The devices will not latch with SEU events to above 100 MeV-cm2/mg. Total dose degradation is minimal to above 1 Mrad(Si). Displacement damage environments to neutron fluence equivalents in the mid 1014 neutrons per cm2 range are readily tolerated. There is no sensitivity to low-dose rate (ELDRS) effects. SEU effects are application Dependant. The RHD5902 is configured with enable/disable control. Pairs of amplifiers are put in a power-down condition with their outputs in a high impedance state. Several useful operational amplifier configurations are supported where more than one amplifier can feed an output with others disabled. SCD5902 Rev B VCC +IN_A 3 -IN_A 2 EN_AB +IN_B -IN_B +IN_C -IN_C 4 1 A OUT_A OUT_A 1 16 OUT_D -IN_A 2 15 -IN_D +IN_A 3 14 +IN_D VCC 4 13 VEE +IN_B 5 12 +IN_C -IN_B 6 11 -IN_C OUT_B 7 10 OUT_C EN_AB 8 9 EN_CD 8 5 6 7 B OUT_B 12 11 EN_CD 10 C OUT_C 9 +IN_D 14 -IN_D 15 16 D OUT_D RHD5902 13 16-Pin SOIC VEE FIGURE 1: BLOCK DIAGRAM FIGURE 2: PACKAGE PIN-OUT Notes: 1. Package and Lid are electrically isolated from signal pads. 2. It is recommended that the Lid be grounded to prevent any ESD or static buildup. 3. EN_AB enables amplifiers A & B. EN_CD enables amplifiers C & D. Pin Signal Name Definition 1 OUT_A Output of Amplifier A. 2 -IN_A Inverting input of Amplifier A. 3 +IN_A Non-Inverting input of Amplifier A. 4 VCC + Voltage Supply. 5 +IN_B Non-Inverting input of Amplifier B. 6 -IN_B Inverting input of Amplifier B. 7 OUT_B Output of Amplifier B. 8 EN_AB A Logic Low will disable Amplifiers A & B so that the outputs are high impedance. 9 EN_CD A Logic Low will disable Amplifiers C & D so that the outputs are high impedance. 10 OUT_C Output of Amplifier C. 11 -IN_C Inverting input of Amplifier C. 12 +IN_C Non-Inverting input of Amplifier C. 13 VEE - Voltage Supply. 14 +IN_D Non-Inverting input of Amplifier D. 15 -IN_D Inverting input of Amplifier D. 16 OUT_D Output of Amplifier D. TABLE 1: PIN-OUT DESCRIPTION SCD5902 Rev B 3/25/13 2 Aeroflex Plainview ABSOLUTE MAXIMUM RATINGS Parameter Range Units Case Operating Temperature Range -55 to +125 °C Storage Temperature Range -65 to +150 °C Junction Temperature +150 °C Supply Voltage VCC - VEE +6.0 V VCC +0.4 VEE -0.4 V Lead Temperature (soldering, 10 seconds) 300 °C Thermal Resistance, Junction to Case,jc 7 °C/W 2,000 - 3,999 V 200 mW Input Voltage ESD Rating (MIL-STD-883, Method 3015, Class 2) Power @ 25°C NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress rating only; functional operation beyond the “Operation Conditions” is not recommended and extended exposure beyond the “Operation Conditions” may affect device reliability. RECOMMENDED OPERATING CONDITIONS Symbol Parameter +VCC Power Supply Voltage Vcm Input Common Mode Range Typical Units 3.3 to 5.0 V VCC to VEE V ELECTRICAL PERFORMANCE CHARACTERISTICS (TC = -55°C TO +125°C, +VCC = +5.0V -- UNLESS OTHERWISE SPECIFIED) Parameter Symbol Conditions Min Max Units Input Offset Voltage 1/ VOS -4 4 mV Input Offset Current IOS -100 100 pA TC = +25°C, -55°C -100 100 TC = +125°C -1000 1000 Input Bias Current 1/ 1/ IB pA Common Mode Rejection Ratio CMRR 60 dB Power Supply Rejection Ratio PSRR 70 dB 4.9 V Output Voltage High VOH ROUT = 720 ohms to GND Output Voltage Low VOL ROUT = 720 ohms to VCC Short Circuit Output Current 2/ 0.1 V IO(SINK) VOUT to VCC -130 -290 mA IO(SOURCE) VOUT to VEE 110 210 mA Slew Rate 1/ SR RL = 8K, Gain = 1 12 V/uS Open Loop Gain 1/ AOL No Load 90 dB 35 Typical @ RL = 10K 23 MHz Unity Gain Bandwidth 1/ SCD5902 Rev B 3/25/13 UGBW 3 Aeroflex Plainview ELECTRICAL PERFORMANCE CHARACTERISTICS (continued) (TC = -55°C TO +125°C, +VCC = +5.0V -- UNLESS OTHERWISE SPECIFIED) Parameter Symbol Input Voltage - Enable 2/ (EN_AB, EN_CD) Input Current - Enable 2/ (EN_AB, EN_CD) Conditions VHI High (Enabled) VLO Low (Disabled) Min Max V 3.5 1.5 V 10 nA All Amplifiers Enabled, No Load 5.5 mA All Amplifier Disabled 2/ 300 nA IEN ICCQ Quiescent Supply Current 1/ RL = 2K, f = 1.0KHz Channel Separation 2/ Input-Referred Voltage Noise 2/ en Phase Margin 2/ m Units dB 84 46 Typical @ F = 5 kHz nV/ Hz Deg 30 Notes: 1/ Specification derated to reflect Total Dose exposure to 1 Mrad(Si) @ +25°C. 2/ Not tested. Shall be guaranteed by design, characterization, or correlation to other test parameters. SWITCHING CHARACTERISTICS (TC = -55°C TO +125°C, +VCC = +5.0V -- UNLESS OTHERWISE SPECIFIED) Symbol Parameter Conditions Min Max Units Output Delay (Enabled) 2/ tONEN 500 ns Output Delay (Disabled) 2/ tOFFEN 100 ns VCC ENABLES (EN_AB or EN_CD) 50% GND tONEN VOUT (VOUT_A&B or VOUT_C&D) VCC HI Z HI Z GND tOFFEN FIGURE 3: RHD5902 SWITCHING DIAGRAM SCD5902 Rev B 3/25/13 4 Aeroflex Plainview RHD5902 QUAD OPERATIONAL AMPLIFIER APPLICATION NOTES APPLICATION NOTE 1: DUAL POWER SUPPLY AMPLIFIER Inverting Amplifier Non Inverting Amplifier R2 VOUT = – VIN ------- R1 R2 VOUT = VIN 1 + ------- R1 EN R1 R2 +2.5V VIN VIN EN VOUT +2.5V R2 -2.5V VOUT -2.5V R1 APPLICATION NOTE 2: SINGLE POWER SUPPLY AMPLIFIER Inverting Amplifier Non Inverting Amplifier R2 VOUT = – VIN ------- R1 R2 VOUT = VIN 1 + ------- R1 R2 +5V EN R1 R3 +5V VIN VIN R3 +5V Vbias EN +5V Vbias VOUT VOUT R4 R2 R4 R1 Note: For VOUT DC @ mid range of common mode voltage range, VBIAS = 2.5/(1+R2/R1), VBIAS = +5*R4/(R3+R4) SCD5902 Rev B 3/25/13 5 Aeroflex Plainview APPLICATION NOTE 3: DIFFERENTIAL INPUT AMPLIFIER APPLICATION NOTE 4: MULTIPLE AMPLIFIERS Differential Input Amplifier Multiple Amplifiers - Selectable Output R4 R2 R2 VOUT = V2 --------------------- 1 + ------- – V1 ------- R3 + R4 R1 R1 +5V R2 R1 V1 A/B VCC V1 VOUT R3 ENV1 V2 VOUT VEE R4 V2 EN C/D Note: Package and lid are electrically isolated from signal pads. FIGURE 4: PACKAGE OUTLINE SCD5902 Rev B 3/25/13 6 Aeroflex Plainview ORDERING INFORMATION Model DLA SMD # Screening RHD5902-7 - Commercial Flow, +25°C testing only RHD5902-S - Military Temperature, -55°C to +125°C Screened in accordance with the individual Test Methods of MIL-STD-883 for Space Applications RHD5902-201-1S 5962-1024103KXC RHD5902-201-2S 5962-1024103KXA RHD5902-901-1S 5962H1024103KXC RHD5902-901-2S 5962H1024103KXA DLA SMD Package 16-pin SOIC Package DLA SMD and Radiation Certification EXPORT CONTROL: EXPORT WARNING: This product is controlled for export under the International Traffic in Arms Regulations (ITAR). A license from the U.S. Department of State is required prior to the export of this product from the United States. Aeroflex’s military and space products are controlled for export under the International Traffic in Arms Regulations (ITAR) and may not be sold or proposed or offered for sale to certain countries. (See ITAR 126.1 for complete information.) PLAINVIEW, NEW YORK Toll Free: 800-THE-1553 Fax: 516-694-6715 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied. SCD5902 Rev B 3/25/13 Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused 7 Aeroflex Microelectronic Solutions Aeroflex Plainview RadHard-by-Design Analog Series Radiation Test Report RHD5900/5901 Quad Operational Amplifiers Performed at: Air Force Research Laboratory (AFRL) Low Energy X-Ray (LEXR) facility Albuquerque, NM June 1-2, 2011 The Aeroflex RHD5900/5901 Quad Operational Amplifier The Aeroflex RHD5900/5901 is a Quad CMOS Operational Amplifier with Rail-To-Rail input/output capability. Several key characteristics of the Opamp are: – Low voltage (3.3V to 5V), and Low Power (20mW) – 2mV Offset Voltage – 2V/μS Slew Rate – 4MHz GBW – Unity Gain Stable – Deep Space Radiation Performance 1MRad (Si) Total Ionizing Dose (TID) Advertised but 10MRad (SiO2) TID Tested Radiation Hardness Non-Critical for non-Deep Space missions ELDRS Immune SEL Immunity > 100 MeV-cm2/mg Neutron displacement damage immunity > 1014 neutrons/cm2 ESD protection qualified at 2kV Body Model Levels 2 The Aeroflex RHD5900/5901 Quad Operational Amplifier Sleep Mode by means of Enable Pins – Power Savings Tri-State – Offers logically controlled redundancy by Wire “ORing” outputs and inputs. Output Drive Flexibility – Amplifiers can be wired in parallel to multiply output drive capability Radiation Hardened by Design using 0.5μm commercial CMOS technology. – Edgeless/Annular nFET topology – Full (Double) Guard Rings Full military temperature range (-55°C to 125°C) Ideal for all orbits (LEO, GEO, MEO) and deep space. – Competitively priced 3 Radiation Performance Explanation The 5901 opamp (and all parts in the series) are characterized by rigorous application of annular nFETs and double guardrings – Annular nFETs eliminate total dose induced edge leakage – Degenerately doped guardrings around both nFETs and pFETs eliminate inter-device leakage – Guardrings also produce excellent single event and prompt dose latchup immunity These layout techniques produce multi-MRad TID hardness; the data reported here indicate the RHD5901 opamp is good to at least 10 MRad(SiO2) – RHD Series parts are “hardness non-critical” for typical space applications and are uniquely suited for strategic and/or deep space missions. The design is CMOS-only and consequently ELDRS immune and robust to neutron displacement damage to fluencies on the order of 1014 n/cm2. 4 The RHD5900 and 5901 Layout RHD5900 RHD5901 5 4 + D28 + D24 D30 + D32 + + + + D36 D27 + D29 D31 + + + D33 VCC D35 + + D40 D39 1 R09 PIN4 + IN50D VCC + VEE IN - VEE + U04 EN UGAMP + - EN UGAMP U02 + - D17 IN IN50B VCC + D18 R06 1 + D37 + D19 + D38 D25 + D23 + D20 + PIN2 8 R08 1 + D21 7 A D34 R07 1 B NIN2I NIN4I PIN2I PIN4I B VCC VEE + + 1 R11 D46 + + - VCC IN50C IN D45 VEE + VEE R04 1 IN + U03 UGAMP EN + - C UGAMP EN U01 + - + VCC IN50A D11 + D42 1 R10 + IN3I NIN1I D12 PIN3 D44 D13 PIN3I + D14 + ENBI ENAI PIN1I D43 R05 1 PIN1 + D41 IN50A IN50B IN50C IN50D D15 BIASET VCC IN50A ENA IN50B ENB IN50C VEE IN50D U05 + + D16 VCC VCC ENAI ENBI VEE C + + + D04 + D01 D06 + + + + D02 + + 1 R12 + D03 D49 + D53 1 R03 D08 D51 + D55 D52 + D56 D54 D50 + + OUT3 D05 + ENB D07 D48 + D47 D09 D10 + NIN3 + NIN1 OUT1 D D26 + D22 6 OUT2 NIN2 PAD LOCATIONS FOR ILLUSTRATION ONLY ACTUAL LOCATIONS WILL BE DETERMINED DURING LAYOUT 5 NIN4 3 OUT4 2 ENA 1 + A Top Level Block D TECHNOLOGY APPLICATION GROUP 351 W. Country Hills Dr. La Habra, CA 90631 . 4OP_PS Date: 6/8/2011 Name: 6 4OP_PS 11:10:10 PM Sheet 01 of 01 RHD5900/5901 Functionality N and P Input stages are superimposed Quiescent currents and voltages for matching transistors are equal, swings are very small. For a common mode input near the negative rail, the N input stage is “Starved”/Inactive. For a common mode input near the positive rail, the P input stage is “Starved”/Inactive. Capacitors/Bias-levels determine slew rate and bandwidth. Virtually all voltage gain occurs in the output stage. 7 RHD5900/5901 TID Test Background Radiation testing was performed using the Low Energy X-Ray (LEXR) facility at AFRL in Albuquerque, NM. – LEXR energy ~ 0.01 MeV Exposures were done to a dose of 18 MRad(Si) – Dosimetry performed by AFRL using a Silicon diode dosimeter – Assuming Charged Particle Equilibrium*, A LEXR exposure to 18 Mrad(Si) corresponds to a dose of 10MRad(SiO2) for the device oxide layers. 18𝑀𝑅𝑎𝑑 𝑆𝑖 /1.793 𝑆𝑖 𝑆𝑖𝑂2 ~ 10MRad(SiO2) * Charged Particle Equilibrium is an approximation. Actual dose in device oxide layers depends on proximity to other materials, interface and other non-equilibrium effects – and may in fact be higher than 10MRad(SiO2) in some areas. 8 RHD5900/5901 TID Characterization Five packaged parts (20 amplifiers) were exposed to the XRay Environment provided by the Low Energy X-Ray (LEXR) Facility at Kirtland Air Force Base. Four packages (16 amplifiers) were irradiated in a functional gain of -5 (or -4). Half (eight) of the amplifiers (two from each package) were irradiated in a small signal linear configuration. The other two amplifiers from each package were irradiated in an extreme input overload condition…to apply an extreme worst case bias mismatch condition. One package (four amplifiers) were irradiated in an unpowered configuration. 9 RHD5900/5901 TID Procedure Data was taken from a total of 8 packages (32 amplifiers) including 16 amplifiers irradiated in operating conditions, 4 unpowered amplifiers, and 12 spares/controls. Data taken at levels of: Pre-Rad, 10k, 30k, 50k, 100k, 300k, 500k, 1M, 2M, 5M and 10MRad SiO2 and after a powered anneal (100°C for 168 hours). Standard Kirtland Air Force Base dosimetry was employed and all parts were exposed de-lidded. Operation of the parts was observed during radiation and parts and boards were transported from the exposure area to the characterization test apparatus after each incremental exposure. LEXR source exposure area was calibrated using special photo paper. 10 LEXR Calibration Paper Calibration paper used for LEXR Source: 11 RHD5900/5901 TID Exposure Board #1 Exposure board #1 (Original) picture: 12 RHD5900/5901 TID Exposure Board #1 Exposure board schematic (Original): 13 RHD5900/5901 TID Exposure Board #2 Exposure board #2 (Rev A) picture: 14 RHD5900/5901 TID Exposure Board #2 Exposure board schematic (Rev A): 15 RHD5900/5901 TID Test Board Test Board Picture: 16 RHD5900/5901 TID Test Board Schematic 17 RHD5900/5901 TID Exposure Board Radiation exposure cell: 18 LEXR Facility at AFRL 19 RHD5900/5901 TID Test Results Exposure to 10MRad(SiO2) required two days of test time. No hard failures occurred. Discontinuity in data at 2MRad(SiO2) occurred because of overnight anneal. The most significant parameter shifts measured for devices irradiated in small signal conditions were offset changes on the order of 2-3mV, operating supply current variations of approx 30% (lower than operating temperature variations). “Sleep” current rose from a value beyond the noise floor of the test equipment to a maximum of < 10µA at 10MRad(SiO2). “Sleep” current annealed back to very small values at room temperature or 100°C. 20 RHD5900/5901 TID Test Results Intentional “ABUSIVE” input overload bias conditions were included during the irradiation conditions. “Quality” device performance is obtained even under “ABUSIVE” bias to levels of 300kRads(SiO2). Moderate attention to application configuration allows the amplifiers to perform at levels typical of high performance commercial operational amplifiers to 10MRad(SiO2) and beyond. Input stage overload bias conditions are detailed on the following slide. 21 Input Stage Overload Bias Conditions + 100U I_8 IDC 100U + 5 VDC I_10 IDC 5 VDC (-) 1.0 VDC 1.0 VDC (-) 1.5 VDC (-) (+) - INPUT I_4 10K 2.5 VDC + INPUT (-) 1.7 VDC (+) I_3 10K 0.8 VDC (-) 0.8 VDC (-) (-) 4.3 VDC + LEFT RIGHT AMPLIFIER OFFSET P - 1.0 VDC + 1.5 VDC GOES POSITIVE N - 1.7 VDC + 0.8 VDC GOES POSITIVE NEGATIVE INPUT OVERLOAD I_6 10K 2.5 VDC + INPUT - INPUT 100U 100U + 0.9 VDC (-) I_7 IDC 1.7 VDC (+) (+) 1.6 VDC (+) (+) 3.4 VDC I_5 10K 1.8 VDC (+) I_9 IDC (+) LEFT RIGHT AMPLIFIER OFFSET P + 1.6 VDC - 0.9 VDC GOES NEGATIVE N + 0.8 VDC - 1.8 VDC GOES NEGATIVE POSITIVE INPUT OVERLOAD 22 RHD5900/5901 TID Supply Currents All devices active and each half of the devices active are plotted in one graph. The bias generator curve is the classic nFET VTH curve Four conditions are reported for supply voltages of 5, 4 and 3.3 volts. They are: – All Devices Active – Half of the devices inactive – The opposite half of the devices inactive – Sleep 23 RHD5900/5901 TID Supply Currents The amplifiers share a common bias current generation in each package. The current reference elements are two diode connected nFETs in series. Bias current levels follow the two FET “Diode Drops” The bias current level can be used as a dosimeter and to serve the threshold shift behavior of the nFETs. The form of the supply variation exactly follows the class nFET threshold shift and “Turn Around”. 24 IDD (Vcc = 5) vs Rads (SiO2) POWER SUPPLY CURRENT (m A) v s RADS (Si 02) ALL DEVI CES ACTI VE; HALF ACTI VE 5. 0 SUPPLY CURRENT ( m A) 4. 0 3. 0 2. 0 1. 0 0. 0 0. 01 KAFB LEXR JUNE 2, 2011 VDD = 5; T = 25C 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 25 Sleep Current (Vcc = 5) vs Rads (SiO2) POWER SUPPLY SLEEP CURRENT (uA) v s RADS (Si02) 10. 0 9. 0 8. 0 SUPPLY CURRENT ( uA) 7. 0 6. 0 5. 0 4. 0 3. 0 2. 0 1. 0 0. 0 0. 01 KAFB LEXR JUNE 2, 2011 VDD = 5; T = 25C 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 26 IDD (Vcc = 4) vs Rads (SiO2) POWER SUPPLY CURRENT (m A) v s RADS (Si 02) ALL DEVI CES ACTI VE; HALF ACTI VE 5. 0 SUPPLY CURRENT ( m A) 4. 0 3. 0 2. 0 1. 0 0. 0 0. 01 KAFB LEXR JUNE 2, 2011 VDD = 4; T = 25C 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 27 Sleep Current (Vcc = 4) vs Rads (SiO2) POWER SUPPLY SLEEP CURRENT (uA) v s RADS (Si02) 10. 0 9. 0 8. 0 SUPPLY CURRENT ( uA) 7. 0 6. 0 5. 0 4. 0 3. 0 2. 0 1. 0 0. 0 0. 01 KAFB LEXR JUNE 2, 2011 VDD = 4; T = 25C 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 28 IDD (Vcc = 3.3) vs Rads (SiO2) POWER SUPPLY CURRENT (m A) v s RADS (Si 02) ALL DEVI CES ACTI VE; HALF ACTI VE 5. 0 SUPPLY CURRENT ( m A) 4. 0 3. 0 2. 0 1. 0 0. 0 0. 01 KAFB LEXR JUNE 2, 2011 VDD = 3. 3; T = 25C 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 29 Sleep Current (Vcc = 3.3) vs Rads (SiO2) POWER SUPPLY SLEEP CURRENT (uA) v s RADS (Si02) 10. 0 9. 0 8. 0 SUPPLY CURRENT ( uA) 7. 0 6. 0 5. 0 4. 0 3. 0 2. 0 1. 0 0. 0 0. 01 KAFB LEXR JUNE 2, 2011 VDD = 3. 3; T = 25C 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 30 RHD5900/5901 TID Input Leakage Currents Input leakage is generated only by the diodes and diffused resistors used in the input protection structures. The currents are NOT “bias currents”. They are bulk and surface leakage. Measuring currents in the 10pA are difficult to measure due to noise. Leakage typical behavior: – Initial leakage currents are at noise floor limits of the test equipment – Leakages rise to hundreds of pA when large doses are accumulated in times extremely short compared to system lifetimes. – Leakages anneal back to immeasurable or, at worst, 10-20pA levels at room temperature or 100°C. – Input leakage will remain in the 10pA range for any system accumulated dose including and beyond 10MRad(SiO2) under any bias conditions. – Offset leakage currents are in the pA range for any dose. 31 Input leakage: Radiation biases measured at Vdd = 5,VCM = 2.5 INPUT LEAKAGE (pA) v s RADS (Si02) ALL BI AS CONDI TI ONS, VCM = 2. 5 1000 800 LEAKAG E CURRENT ( pA) 600 400 (- I NPUT) 200 0 - 200 - 400 (+ I NPUT) - 600 - 800 - 1000 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 5; VCM = 2. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 16 AM PLI FI ERS, 32 LEADS 32 Input Leakage Current Measurement Problems Input leakage was measured by closing an operational amplifier server loop around the device under test. A resistor was inserted in one or the other (or both) input leads. The voltage required to return the output of the device under test to a set voltage was measured with resistors present or shorted. The feedback voltage plus/minus the amplifier voltage offset and the resistor value was used to device the input leakage. Leakage measurements were compromised for two reasons: – Scale factors had been chosen to allow for considerably higher initial and radiation caused leakage. – The offset voltage was measured at common mode voltage increments 0.5 volts away from the common mode input where current was measured. The correction for offset was then improper and when combined with the scale factor caused leakage measurements for any common mode other than Vdd/2 to be incorrect and high. Post test action: – All parts were annealed at 100°C for 168 hours following irradiation. – Post anneal leakage currents for all parts (irradiated to 10MRad(SiO2)) were measured over the rail-to-rail common mode range – The resulting data is shown in the following chart – Leakages are well behaved and very low 33 Input leakage: Radiation biases vs VCM = 2.5, 10MRad(SiO2) Post Anneal 34 RHD5900/5901 Offset Voltage Shift The amplifiers are designed with matched transistors and bias voltages to optimize nominal performance parameters and total dose radiation tolerance. Initial offsets have a 3-Sigma distribution of approximately +/- 2mV Under normal closed loop conditions (input not in overload), the changes in offset is less than 2mV to at least 10MRad(SiO2). The data for eight amplifiers (four packages) are shown in the following charts. For most applications, minimal device derating is required to 10MRad(SiO2) or more. For maximum hardness, devices should only be allowed to incur input overload for a small percentage of their system lifetime (by system design). Input overload behavior is described in subsequent pages. 35 Offset (Small Signal Bias), VDD = 5, VCM = 4.5 OFFSET VOLTAGE (m V) v s RADS (Si02) SMALL SI GNAL BI AS DURI NG I RRADI ATI ON 4. 0 O FFSET VO LTAG E ( m V) 3. 0 2. 0 1. 0 0. 0 - 1. 0 - 2. 0 - 3. 0 - 4. 0 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 5; VCM = 4. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 36 Offset (Small Signal Bias), VDD = 5, VCM = 2.5 OFFSET VOLTAGE (m V) v s RADS (Si02) SMALL SI GNAL BI AS DURI NG I RRADI ATI ON 4. 0 O FFSET VO LTAG E ( m V) 3. 0 2. 0 1. 0 0. 0 - 1. 0 - 2. 0 - 3. 0 - 4. 0 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 5; VCM = 2. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 37 Offset (Small Signal Bias), VDD = 5, VCM = 0.5 OFFSET VOLTAGE (m V) v s RADS (Si02) SMALL SI GNAL BI AS DURI NG I RRADI ATI ON 4. 0 O FFSET VO LTAG E ( m V) 3. 0 2. 0 1. 0 0. 0 - 1. 0 - 2. 0 - 3. 0 - 4. 0 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 5; VCM = 0. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 38 Offset (Small Signal Bias), VDD = 4, VCM = 3.5 OFFSET VOLTAGE (m V) v s RADS (Si02) SMALL SI GNAL BI AS DURI NG I RRADI ATI ON 4. 0 O FFSET VO LTAG E ( m V) 3. 0 2. 0 1. 0 0. 0 - 1. 0 - 2. 0 - 3. 0 - 4. 0 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 4; VCM = 3. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 39 Offset (Small Signal Bias), VDD = 4, VCM = 2 OFFSET VOLTAGE (m V) v s RADS (Si02) SMALL SI GNAL BI AS DURI NG I RRADI ATI ON 4. 0 O FFSET VO LTAG E ( m V) 3. 0 2. 0 1. 0 0. 0 - 1. 0 - 2. 0 - 3. 0 - 4. 0 0. 01 0. 10 KAFB LEXR JUNE 2, 2011 VDD = 4; VCM = 2, T = 25C 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 40 Offset (Small Signal Bias), VDD = 4, VCM = 0.5 OFFSET VOLTAGE (m V) v s RADS (Si02) SMALL SI GNAL BI AS DURI NG I RRADI ATI ON 4. 0 O FFSET VO LTAG E ( m V) 3. 0 2. 0 1. 0 0. 0 - 1. 0 - 2. 0 - 3. 0 - 4. 0 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 4; VCM = 0. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 41 Offset (Small Signal Bias) VDD = 3.3, VCM = 2.8 OFFSET VOLTAGE (m V) v s RADS (Si02) SMALL SI GNAL BI AS DURI NG I RRADI ATI ON 4. 0 O FFSET VO LTAG E ( m V) 3. 0 2. 0 1. 0 0. 0 - 1. 0 - 2. 0 - 3. 0 - 4. 0 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 3. 3; VCM = 2. 8, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 42 Offset (Small Signal Bias) VDD = 3.3, VCM = 1.65 OFFSET VOLTAGE (m V) v s RADS (Si02) SMALL SI GNAL BI AS DURI NG I RRADI ATI ON 4. 0 O FFSET VO LTAG E ( m V) 3. 0 2. 0 1. 0 0. 0 - 1. 0 - 2. 0 - 3. 0 - 4. 0 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 3. 3; VCM = 1. 65, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 43 Offset (Small Signal Bias) VDD = 3.3, VCM = 1.5 OFFSET VOLTAGE (m V) v s RADS (Si02) SMALL SI GNAL BI AS DURI NG I RRADI ATI ON 4. 0 O FFSET VO LTAG E ( m V) 3. 0 2. 0 1. 0 0. 0 - 1. 0 - 2. 0 - 3. 0 - 4. 0 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 3. 3; VCM = 0. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 44 Average Offset (Small Signal Bias) 10 MRad(SiO2) Post Anneal 45 RHD5900/5901 TID Offset vs Bias Overload input voltage conditions maximizes input stage shift mismatch. Two input stages are active for V(Pin) = 2.5. A pFET and an nFET stage with summed currents. The offset is the difference of the differences. The input stage transistors operate with small Vg-Vth. Since threshold shifts nearing 200mV will occur at 1MRad(SiO2) under high input overload, the input stage will lose control of the circuit under abusive bias conditions. Even under the worst conditions, operation to above 100kRad(SiO2) is possible. Limiting or eliminating overload makes operation to 10MRad(SiO2) or more without appreciable derating a real option. The following chart illustrates the extreme overload conditions. During “normal” operation, all FET voltages are equal and remain equal regardless of parameter changes. 46 Offset (Overload Bias), VDD = 5, VCM = 4.5 OFFSET VOLTAGE (m V) v s RADS (Si02) OVERLOAD BI AS DURI NG I RRADI ATI ON 25. 0 O FFSET VO LTAG E ( m V) 0. 0 - 25. 0 B (+) - 50. 0 - 75. 0 C (-) - 100. - 125. - 150. 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 5; VCM = 4. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 47 Offset (Overload Bias), VDD = 5, VCM = 2.5 OFFSET VOLTAGE (m V) v s RADS (Si02) OVERLOAD BI AS DURI NG I RRADI ATI ON 50. 0 O FFSET VO LTAG E ( m V) C (-) 0. 0 - 50. 0 B (+) - 100. - 150. 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 5; VCM = 2. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 48 Offset (Overload Bias), VDD = 5, VCM = 0.5 OFFSET VOLTAGE (m V) v s RADS (Si02) OVERLOAD BI AS DURI NG I RRADI ATI ON 100. 0 O FFSET VO LTAG E ( m V) 50. 0 C (-) 0. 0 - 50. 0 B (+) - 100. - 150. 0. 01 KAFB LEXR JUNE 2, 2011 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) VDD = 5; VCM = 0. 5, T = 25C 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 49 Average Offset (Overload Bias) 10MRad(SiO2) Post-Anneal 50 Input Overload Avoidance Non-inverting unity gain amplifiers do not experience overload. Servo systems in linear controls do not experience prolonged overload Scaling amplifiers do not experience overload Filters, power supplies, signal processing systems do no experience prolonged overload. Sensor systems do not experience prolonged overload Clipping/clamping/signal-scaling can eliminate overload in most cases System engineering is the best solution for avoiding overload. 51 Offset Voltage vs Overload Voltage During Irradiation Half of the samples were irradiated with +/- Vdd/2 input voltage overload. The overload condition is highly unrealistic for operating small signal linear circuits. The amplifiers are not intended to be comparators. However, good performance can be obtained to several hundred kRad(SiO2) even with large input overload and if the input overload duty cycle is less than 100%, the offset as a comparator is the same as that presented for an amplifier. 52 Open Loop Gain Gain is load dependent. For loads above 100K, open loop gain approaches 120dB. Open loop gain measurement is difficult for levels above 100dB due to reading uncertainty. Data shown on following slides shows open loop gain for loads from “moderate” to “heavy” loading. Gain is shown as a function of Rads (SiO2) for Vdd = 5, 4 and 3.3. 53 Open Loop Gain (VCC = 5) vs Rads (SiO2) OPEN LOOP GAIN v s RADS (Si02) LOADS: 75K, 10K 120 75K 110 O PEN LO O P G AI N ( db) 100 90 80 10K 70 60 50 40 30 20 10 0 0. 01 KAFB LEXR JUNE 2, 2011 VDD = 5; T = 25C 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 54 Open Loop Gain (VCC = 4) vs Rads (SiO2) OPEN LOOP GAIN v s RADS (Si02) LOADS: 75K, 10K 120 75K 110 O PEN LO O P G AI N ( db) 100 90 80 10K 70 60 50 40 30 20 10 0 0. 01 KAFB LEXR JUNE 2, 2011 VDD = 4; T = 25C 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 55 Open Loop Gain (VCC = 3.3) vs Rads (SiO2) OPEN LOOP GAIN v s RADS (Si02) LOADS: 75K, 10K 120 75K 110 O PEN LO O P G AI N ( db) 100 90 80 10K 70 60 50 40 30 20 10 0 0. 01 KAFB LEXR JUNE 2, 2011 VDD = 3. 3; T = 25C 0. 10 1. 00 TO TAL DO SE ( M EG ARADS SiO 2) 10. 00 20. 00 PO ST RAD ANNEAL 100C FO R 168 HO URS FO UR PACKAG ES, 8 AM PLI FI ERS 56 RHD5900/5901 TID Power Supply Rejection Ratio Power supply rejection ration was measured by stepping the power supply from 5.0V to 3.3V. While this method is pessimistic, it results in a value which is representative of the rejection ratio for the full range of Vdd (5 to 3.3V). The average value of the PSRR for eight amplifiers is plotted. 57 Power Supply Rejection Ratio vs Rads (SiO2) (VCC Step: 5.0 to 3.3) 58 RHD5900/5901 TID Common Mode Rejection Ratio Methodology: The common mode input voltage was stepped from 0.5 to 4.5Vdc for Vdd = 5, 0.5 to 3.5 for Vdd = 4 and 0.5 to 2.8 for Vdd=3.3 This method causes the common mode range to cross the maximum large signal swings of Vos. The resulting CMRR is very pessimistic compared to a small signal measurement. The average value of the CMRR for eight amplifiers and three power supply voltages is plotted. 59 Common Mode Rejection Ratio vs Rads (SiO2) 60 RHD5900/5901 TID Gain Compression For voltages near the power supplies, resistive loads result in the A/B output stage transistors in the “linear” region. The output is just a resistor and the Vgs is large compared to the threshold shift with radiation. The data are for 0.02, 0.05 and 0.1 volts away from the rails and for pull-up and pull-down 2k loads respectively. Eight devices are averaged for each plotted point. Points are plotted for 10k, 100k, 1M and 10M. The input-output error is proportionately smaller for larger load resistance values. Pre-rad data can be used for any total dose. 61 Gain Compression (2K Up/Down Load) INPUT/OUTPUT ERROR (VOLTS) GAI N COMPRESSI ON NEAR THE RAI LS (0. 01, 0. 1, 1, 10 MEGARADS) 0. 15 O UTPUT - I NPUT ( VO LTS) 0. 10 0. 05 0. 00 - 0. 05 - 0. 10 - 0. 15 0. 0 0. 1 KAFB LEXR JUNE 2, 2011 VDD = 5; T = 25C 0. 24. 8 I NPUT VO LTAG E ( VO LTS) 4. 9 5. 0 AVERAG E O F EI G HT AM PLI FI ERS 62 RHD5900/5901 TID Pulse Test The device current drain is nearly proportional to both bandwidth and slew rate. Total dose changes in bandwidth and slew rate are no more than those caused by temperature extremes. High quality operational amplifier performance is obtained to 10MRad(SiO2) and beyond. Input overload should be avoided, eliminated or the duty cycle should be minimized to avoid offset voltage shift. The following pre/post 10MRad(SiO2) pulse waveforms are shown for a closed loop gain of -67(inverting) configuration. 63 RHD5900/5901 TID Pulse/Slew Rate Test Pulse response: – Pulse response is shown pre-rad and post for inverting gains of 67 and 4.36 – Gain values were “convenient” for characterization purposes – High gain demonstrates GBW limited rise time – Low gain demonstrates slew-rate limit and “Ring” Slew Rate: – An input signal sufficient to cause the amplifier to step from overload at one supply to overload at the other supply. – A time cursor is placed at 0.5 or 4.5 volts. – A second time cursor is places 1µS later in time than the 0.5 or 4.5 volt crossing. – The delta V between the two cursors is reported as slew rate in Volts per μS. 64 Pre and Post 10 MRad(SiO2) Pulse Response Inverting 67x Pre-Irradiation Post-Irradiation 10 MRad (SiO2) 65 Pre and Post 10 MRad(SiO2) Step Response (4.36X) + STEP - STEP Pre-Irradiation Post-Irradiation 10 MRad (SiO2) 66 Pre and Post 10MRad(SiO2) Slew Rate + STEP - STEP Pre-Irradiation Post- Irradiation 10 MRad (SiO2) 67 RHD5900/5901 TID Second Test A second test was conducted at AFRL for the RHD5900/5901. The second test emphasized the following: – Improved input leakage measurement – Offset characterization as a % of time in overload – Improved Gain, CMRR and PSRR measurements – Post radiation annealing (Room temp operating followed by time-temperature steps) 68 RHD5900/5901 TID Input Leakage The following chart shows input leakage current before annealing and following 10MRad(SiO2) leakage as a function of the common mode input voltage. The offset current reflects approximately 10% matching in terminal currents. Previous data indicated that nearly a 10x reduction in leakage will occur with annealing. This data must be accompanies with temperature data. Elevated temperatures cause leakages to increase yet encourage annealing. The effects will compete. Likewise, irradiation temperatures will exaggerate effects but will lower leakage. 69 Input Leakage After 10 MRad(SiO2) Pre-Anneal 70 Input Leakage After 10 MRad(SiO2) Pre-Anneal Averaged and Polynomial Fit 71 Input Leakage After 10 MRad(SiO2) Pre-Anneal Averaged and Polynomial Fit 72 RHD5900/5901 TID Offset Voltage The following chart shows offset voltage vs total dose for six amplifiers (three packages) operating under small signal conditions during irradiation 10 MRad(SiO2). The three trace colors delineate two amplifiers in a common package. 73 Offset Voltage After 10 MRad(SiO2) Pre-Anneal Small Signal Conditions During Irradiation 74 RHD5900/5901 TID Offset Voltage (% of time in overload) The following chart shows offset voltage vs total dose for six amplifiers (three packages) operating under overload conditions for a percentage of time. The three trace colors delineate two amplifiers in a common package. The solid and broken lines are for positive and negative overload. The black curves for 0.1% of total time in overload, Red 1% and Green 10%. Less effect was observed than might be deduced from precious data indicating that well above 10 MRad(SiO2) applications can be supported for realistic operating conditions. 75 Offset Voltage After 10 MRad(SiO2) Pre-Anneal 0.1, 1 and 10% Duty Cycle Plus Minus Overload 76 RHD5900/5901 TID Offset Voltage (% of time in overload) The rail-to-rail input common mode range of the amplifier has three regions of operation: – Both input pairs operating – N-Side Operating, P-Side Starved – P-Side Operating, N-Side Starved Offset voltage will change as the regions are traversed. The offset change is a measure of how well the three modes of operation overlap and transition. Radiation in overload affects the offset voltages in the starved regions The following five charts illustrate the offset vs common mode voltage and total dose phenomena. No more than approximately 2mV in offset variation is caused by radiation and only at the “ends” of the common mode input range at 10MRad(SiO2). 77 Pre- Rad Offset Voltage vs Common Mode Voltage 78 Offset Voltage at 1 MRad(SiO2) vs Common Mode Voltage (Small Signal Bias) 79 Offset Voltage at 1 MRad(SiO2) vs Common Mode Voltage (Overload Signal Bias) 80 Offset Voltage at 10MRad(SiO2) vs Common Mode Voltage (Small Signal Bias) 81 Offset Voltage at 10MRad(SiO2) vs Common Mode Voltage (Overload Signal Bias) 82 RHD5900/5901 TID Gain, CMRR and PSRR Voltage step conditions were changed to avoid extreme large signal swings for gain, PSRR, and CMRR characterization. For CMRR and gain measurement, step sizes of 1V were used. PSRR was calculated by stepping the supply voltage from 5.0V to 3.3V. This simulated a worst case test. 83 Open Loop Gain (Test #2: Improved Methodology) 84 Common Mode Rejection Ratio (CMRR) (Test #2: Improved Methodology) 85 Power Supply Rejection Ratio (PSRR) (Test #2: Improved Methodology) 86 RHD5900/5901 TID GBW and Slew Rate vs Total Dose The amplifiers are designed to be “programmable” with bias current. That is: power, gain-bandwidth and slew rate is proportional to bias current level and bias current can be set with a single resistor or reference voltage. The bias current level is set by the sum of the drain/source drops of the two nFETs. The bias current is effectively an nFET dosimeter. More complex (higher level of integration) circuits use a bandgap reference to set bias currents. Gain bandwidth and slew rate track chip current. Normalized current and gain bandwidth plots emphasize the tracking. 87 Power Supply Current vs Total Dose 88 Gain Bandwidth vs Total Dose 89 Normalized Amplifier Bias Current and Gain Bandwidth vs Total Dose 90 Slew Rate vs Total Dose 91 RHD5900/5901 TID Performance Test Summary The quad operation amplifier is capable of applications to and above 10MRad(SiO2) under linear (non-overload conditions). Prolonged overload conditions should be avoided but applications with 10% or less of the operating time in overload can be supported to above 1MRad(SiO2). The most significant performance parameter shifts are a maximum change in offset voltage of 2 to 3mV and a decrease in unity gain bandwidth and slew rate of approximately 25% between 1 and 10 MRad(SiO2). A statistically significant number of devices were characterized in total dose environments. More than 32 amplifiers. A pre-post total dose table follows. 92 Pre/Post Parameters (Excel Table) PARAMETER OFFSET VOLTAGE OFFSET VOLTAGE OFFSET VOLTAGE OFFSET VOLTAGE OFFSET VOLTAGE OFFSET VOLTAGE OFFSET VOLTAGE OFFSET VOLTAGE OFFSET VOLTAGE INPUT LEAKAGE LEAKAGE OFFSET SUPPLY CURRENT SLEEP CURRENT GAIN-BANDWIDTH SLEW-RATE OPEN LOOP GAIN OPEN LOOP GAIN PSRR CMRR UNITS mV mV mV mV mV mV mV mV mV pA pA mA nA MHz V/uS db db db db PRE-RAD +/- 2mV TYP +10/-5 pA +10/-5 pA 4.5 TYP 40nA MAX 6.5 TYP 3.0 MIN >100 db MIN 90 db MIN 80 db MIN 80 db MIN TOTAL DOSE POST-RAD RADS (Si02) BASIS 44 AMPLIFIERS +4/-4 mV MAX 10 MEG 14 AMPLIFIERS +3/-2 mV MAX 1 MEG 14 AMPLIFIERS +2/-2 mV MAX 0.1 MEG 14 AMPLIFIERS +2/-2 mV MAX 10 MEG 6 AMPLIFIERS +2/-2 mV MAX 10 MEG 6 AMPLIFIERS +2/-2 mV MAX 10 MEG 6 AMPLIFIERS +4/-2 mV MAX 0.1 MEG 8 AMPLIFIERS +15/-40 mV MAX 1.0 MEG 8 AMPLIFIERS +10/-30 pA 10 MEG 28 AMPLIFIERS, 56 LEADS +10/-5 pA 10 MEG 12 AMPLIFIERS 3.5 MIN 10 MEG 12 PKGS, 48 AMPLIFIERS 200nA MAX 10 MEG 7 PKGS 4.0 MIN 10 MEG 28 AMPLIFIERS 2.5 MIN 10 MEG 28 AMPLIFIERS >100 db MIN 10 MEG 28/6 AMPLIFIERS 90 db MIN 10 MEG 6 AMPLIFIERS 80 db MIN 10 MEG 6 AMPLIFIERS 80 db MIN 10 MEG 6 AMPLIFIERS PRE-POST RADIATION PARAMETERS CONDITIONS SMALL SIGNAL SMALL SIGNAL SMALL SIGNAL 0.1% OVERLOAD 1.0% OVERLOAD 10% OVERLOAD 100% OVRELOAD 100% OVRELOAD ALL ALL ALL SAMPLES 11x4 4x2 + 3x2 4x2 + 3x2 4x2 + 3x2 3x2 3x2 3x2 4x2 4x2 7x4 3x4 3x4 4+3 7x4 7x4 OPEN (EXTRAPOLATED) 75K LOAD 3x2 5 TO 3.3 VOLTS 3x2 3x2 RHD5900/5901 TID Annealing An annealing cycle of 168 hours at 100°C following irradiation is an industry standard. Annealing is performed: – Historically: To reveal nFET threshold shift turn around or rebound phenomenon which caused reduced hardness for long-term radiation environments (space). – More recently 100°C annealing has been performed to modify high dose rate characterization data to correspond more closely with that expected in long term space environments. In general, data reported here is for worst case conditions (e.g. Before or after anneal. No “forced anneals” were performed to “improve” parameters). The very low leakage input terminal numbers are reported after one week operating at room temperature. The peak leakage numbers are shown in the individual plots although the post operating anneal numbers are far more realistic. 94 RHD5900/5901 Annealing/Operating Temperature Total dose effects increase (in general) in CMOS with depressed temperatures. Threshold shifts at Liquid Nitrogen (77K) are as much as 100 times those at room temperature. It is difficult to predict behavior at depressed temperatures and to rationalize characterization data under practical source dose rates with that which will occur over long times at low temperatures. However, data presenting in this report are encouraging even for systems operating and irradiated at cryogenic temperatures because of the very large operating margins. 95 REVISIONS LTR DESCRIPTION DATE (YR-MO-DA) APPROVED REV SHEET REV SHEET 15 REV STATUS REV OF SHEETS SHEET PMIC N/A PREPARED BY Steve L.Duncan STANDARD MICROCIRCUIT DRAWING THIS DRAWING IS AVAILABLE FOR USE BY ALL DEPARTMENTS AND AGENCIES OF THE DEPARTMENT OF DEFENSE AMSC N/A 1 2 3 4 5 DRAWING APPROVAL DATE 13-03-26 REVISION LEVEL 7 9 10 11 12 13 MICROCIRCUIT, CMOS, OPERATIONAL AMPLIFIER, QUAD, MONOLITHIC SILICON SIZE CAGE CODE A 67268 SHEET DSCC FORM 2233 APR 97 8 DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 http://www.landandmaritime.dla.mil/ CHECKED BY Greg Cecil APPROVED BY Charles F. Saffle 6 5962-10241 1 OF 15 5962-E334-12 14 1. SCOPE 1.1 Scope. This drawing documents five product assurance classes as defined in paragraph 1.2.3 and MIL-PRF-38534. A choice of case outlines and lead finishes which are available and are reflected in the Part or Identifying Number (PIN). When available, a choice of radiation hardness assurance levels are reflected in the PIN. 1.2 PIN. The PIN shall be as shown in the following example: 5962 H Federal stock class designator \ RHA designator (see 1.2.1) 10241 01 K X X Device type (see 1.2.2) Device class designator (see 1.2.3) Case outline (see 1.2.4) Lead finish (see 1.2.5) / \/ Drawing number 1.2.1 Radiation hardness assurance (RHA) designator. RHA marked devices shall meet the MIL-PRF-38534 specified RHA levels and shall be marked with the appropriate RHA designator. A dash (-) indicates a non-RHA device. 1.2.2 Device type(s). The device type(s) identify the circuit function as follows: Device type 01 02 03 Generic number RHD5900 RHD5901 RHD5902 Circuit function Quad operational amplifier Quad operational amplifier, Hi-Z output control Quad operational amplifier, High speed, Hi-Z output control 1.2.3 Device class designator. This device class designator shall be a single letter identifying the product assurance level. All levels are defined by the requirements of MIL-PRF-38534 and require QML Certification as well as qualification (Class H, K, and E) or QML Listing (Class G and D). The product assurance levels are as follows: Device class Device performance documentation K Highest reliability class available. This level is intended for use in space applications. H Standard military quality class level. This level is intended for use in applications where non-space high reliability devices are required. G Reduced testing version of the standard military quality class. This level uses the Class H screening and In-Process Inspections with a possible limited temperature range, manufacturer specified incoming flow, and the manufacturer guarantees (but may not test) periodic and conformance inspections (Group A, B, C and D). E Designates devices which are based upon one of the other classes (K, H, or G) with exception(s) taken to the requirements of that class. These exception(s) must be specified in the device acquisition document; therefore the acquisition document should be reviewed to ensure that the exception(s) taken will not adversely affect system performance. D Manufacturer specified quality class. Quality level is defined by the manufacturers internal, QML certified flow. This product may have a limited temperature range. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 2 1.2.4 Case outline(s). The case outline(s) are as designated in MIL-STD-1835 and as follows: Outline letter Descriptive designator X See figure 1 Terminals Package style 16 Flat package with formed leads 1.2.5 Lead finish. The lead finish shall be as specified in MIL-PRF-38534. 1.3 Absolute maximum ratings. 1/ Supply voltage (VCC) ............................................................................. Input voltage (VIN) range ....................................................................... Junction temperature (TJ) ..................................................................... Power @ +25°C .................................................................................... Thermal resistance, Junction to Case (ӨJC) .......................................... Storage temperature range ................................................................... Lead temperature (soldering, 10 seconds) ........................................... +7.0 V dc VCC +0.4 V, VEE -0.4 V +150°C 200 mW 7° C/W -65°C to +150°C +300°C 1.4 Recommended operating conditions. Supply voltage (VCC) range .................................................................... Input Common Mode (VCM) range .......................................................... Case operating temperature range (TC) ................................................. +3.0 V dc to +5.5 V dc VCC to VEE -55°C to +125°C 1.5 Radiation features. 2/ Maximum Total Ionizing Dose (TID) ..(dose rate = 50 - 300 rad(Si)/s): In accordance with MIL-STD-883, method 1019, condition A............ Enhanced Low Dose Rate Sensitvity (ELDRS)..................................... Single Event Phenomenon (SEP) effective linear energy transfer (LET): No Single Event Latchup (SEL) ......................................................... Single Event Transient (SET) ............................................................ 14 2 Neutron Displacement Damage (> 1 x 10 neutrons/cm ) ................... 1 Mrad(Si) 3/ ≤ 100 MeV-cm /mg 4/ 5/ ≤ 59 MeV-cm2/mg 4/ 5/ 3/ 2 2. APPLICABLE DOCUMENTS 2.1 Government specification, standards, and handbooks. The following specification, standards, and handbooks form a part of this drawing to the extent specified herein. Unless otherwise specified, the issues of these documents are those cited in the solicitation or contract. DEPARTMENT OF DEFENSE SPECIFICATIONS MIL-PRF-38534 - Hybrid Microcircuits, General Specification for. DEPARTMENT OF DEFENSE STANDARDS MIL-STD-883 - Test Method Standard Microcircuits. MIL-STD-1835 - Interface Standard for Electronic Component Case Outlines. DEPARTMENT OF DEFENSE HANDBOOKS MIL-HDBK-103 - List of Standard Microcircuit Drawings. MIL-HDBK-780 - Standard Microcircuit Drawings. _________ 1/ 2/ 3/ 4/ 5/ Stresses above the absolute maximum ratings may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. See section 4.3.5 for the manufacturer's radiation hardness assurance analysis and testing. Not tested, Immune by 100 percent CMOS technology. 2 2 Single event testing performed at 100 Mev-cm /mg with no latch-up and up to 59 Mev-cm /mg with single event transients (voltage) limited as specified in Table IB. See table IB. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 3 (Copies of these documents are available online at https://assist.dla.mil/quicksearch/ or from the Standardization Document Order Desk, 700 Robbins Avenue, Building 4D, Philadelphia, PA 19111-5094.) 2.2 Non-Government publications. The following documents form a part of this document to the extent specified herein. AMERICAN SOCIETY FOR TESTING AND MATERIALS (ASTM) ASTM F1192 - Standard Guide for the Measurement of Single Event Phenomena (SEP) Induced by Heavy Ion Irradiation of Semiconductor Devices. (Copies of these documents are available online at http://www.astm.org or from the American Society for Testing and Materials, P O Box C700, 100 Barr Harbor Drive, West Conshohocken, PA 19428-2959) 2.3 Order of precedence. In the event of a conflict between the text of this drawing and the references cited herein, the text of this drawing takes precedence. Nothing in this document, however, supersedes applicable laws and regulations unless a specific exemption has been obtained. 3. REQUIREMENTS 3.1 Item requirements. The individual item performance requirements for device classes D, E, G, H, and K shall be in accordance with MIL-PRF-38534. Compliance with MIL-PRF-38534 shall include the performance of all tests herein or as designated in the device manufacturer's Quality Management (QM) plan or as designated for the applicable device class. The manufacturer may eliminate, modify or optimize the tests and inspections herein, however the performance requirements as defined in MIL-PRF-38534 shall be met for the applicable device class. In addition, the modification in the QM plan shall not affect the form, fit, or function of the device for the applicable device class. 3.2 Design, construction, and physical dimensions. The design, construction, and physical dimensions shall be as specified in MIL-PRF-38534 and herein. 3.2.1 Case outline(s). The case outline(s) shall be in accordance with 1.2.4 herein and and as specified on figure 1. 3.2.2 Terminal connections. The terminal connections shall be as specified on figure 2. 3.2.3 Logic diagram(s). The logic diagram(s) shall be as specified on figure 3. 3.2.4 Switching diagram(s). The switching diagram(s) shall be as specified on figure 4. 3.2.5 Radiation exposure circuits. The radiation exposure circuits shall be maintained by the manufacturer under document revision level control and shall be made available to the preparing and acquiring activity upon request. 3.3 Electrical performance characteristics. Unless otherwise specified herein, the electrical performance characteristics are as specified in table IA and shall apply over the full specified operating temperature range. 3.4 Electrical test requirements. The electrical test requirements shall be the subgroups specified in table II. The electrical tests for each subgroup are defined in table IA. 3.5 Marking of device(s). Marking of device(s) shall be in accordance with MIL-PRF-38534. The device shall be marked with the PIN listed in 1.2 herein. In addition, the manufacturer's vendor similar PIN may also be marked. 3.6 Data. In addition to the general performance requirements of MIL-PRF-38534, the manufacturer of the device described herein shall maintain the electrical test data (variables format) from the initial quality conformance inspection group A lot sample, for each device type listed herein. Also, the data should include a summary of all parameters manually tested, and for those which, if any, are guaranteed. This data shall be maintained under document revision level control by the manufacturer and be made available to the preparing activity (DLA Land and Maritime -VA) upon request. 3.7 Certificate of compliance. A certificate of compliance shall be required from a manufacturer in order to supply to this drawing. The certificate of compliance (original copy) submitted to DLA Land and Maritime -VA shall affirm that the manufacturer's product meets the performance requirements of MIL-PRF-38534 and herein. 3.8 Certificate of conformance. A certificate of conformance as required in MIL-PRF-38534 shall be provided with each lot of microcircuits delivered to this drawing. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 4 TABLE IA. Electrical performance characteristics. Test Input offset voltage 1/ Symbol Conditions -55°C ≤ TC ≤ +125°C VCC = +5.0 V, VEE = GND unless otherwise specified VOS Group A Device subgroups types 1,2,3 Limits Unit Min Max 01,02 -3 3 03 -4 4 mV Input offset current 1/ IOS 1,2,3 All -100 100 pA Input bias current 1/ IB 1,3 All -100 100 pA -1 1 nA 2 Common Mode Rejection Ratio CMRR 4,5,6 01,02 70 03 60 4,5,6 All 70 dB 4.90 V Power supply rejection ratio PSRR Output voltage high VOH ROUT = 3.6 kΩ to GND 1,2,3 All Output voltage low VOL ROUT = 3.6 kΩ to VCC 1,2,3 All Short circuit output current 2/ IO(SINK) VOUT to VCC 1,2,3 01,02 IO(SOURCE) Slew rate 1/ SR VOUT to VEE RL = 8 kΩ, Gain = +1 9,10,11 dB 0.1 V -30 -75 mA 03 -130 -290 01,02 45 55 03 110 210 01,02 2.0 03 12.0 V/µs Open loop gain 1/ AOL RL = 100 kΩ 4,5,6 All 90 dB Unity gain bandwidth 1/ UGBW RL = 10 kΩ 4,5,6 01,02 4 MHz 03 23 Quiescent supply current 1/ ICCQ All amplifiers enabled, no loads 1,2,3 All amplifiers disabled All 5.5 mA 02,03 300 nA Channel separation 2/ CHSEP RL = 2 kΩ, f = 1.0 kHz 4,5,6 All 84 dB Enable input voltage high 2/ VHI HI = enabled 1,2,3 02,03 3.5 V Enable input voltage low 2/ VLO LO = disabled 1,2,3 02,03 1.5 V Enable input current 2/ IEN 1,2,3 02,03 10 nA Output enable delay 2/ tONEN 9,10,11 02,03 500 ns Output disable delay 2/ tOFFEN 9,10,11 02,03 100 ns 1/ 2/ See figure 4 These devices have been tested to (2 Mrad(Si)) to Method 1019, condition A of MIL-STD-883 at +25°C for these parameters to assure the requirements of RHA designator level "H” (1Mrad(Si)) are met. Not tested. Shall be guaranteed by design, characterization, or correlation to other test parameters. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 5 TABLE IB. SEP test limits. 1/ Device types 01,02,03 SEP 01,02,03 SET (transient voltage) SEL Temperature (TC) +125°C +25°C Conditions Results VCC = +5.5 V and VEE = +0 V VCC = +2.75 V and VEE = -2.75 V VCC = +5.0 V and VEE = +0 V No SEL No SEL Maximum voltage 240 mV Maximum duration 3.5 µS Maximum voltage 240 mV Maximum duration 4.0 µS VCC = +2.5 V and VEE = -2.5 V Effective linear energy transfer (LET) 2 < 100 MeV-cm /mg 2 < 59 MeV-cm /mg 1/ For SEP test conditions, see 4.3.5.1.2.2 herein. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 6 Case X Symbol Inches Min A A1 A2 A3 b c D e e1 E E1 E2 Max .105 .030 REF .017 .027 .012 .015 .019 .007 .009 .417 .050 BSC .350 BSC .300 .394 .419 .346 REF Millimeters Min Max 2.68 0.76 REF 0.43 0.69 0.30 0.38 0.48 0.18 0.23 10.59 1.27 BSC 8.90 BSC 7.62 10.01 10.64 8.79 REF NOTE: 1. Location of the pin 1 marking. The ESD symbol may be used as the pin 1 marking. 2. The U.S. preferred system of measurement is the metric SI. This item was designed using inch-pound units of measurement. In case of problems involving conflicts between the metric and inch-pound units, the inch-pound units shall rule. 3. Package and lid are electrically isolated from signal pads. FIGURE 1. Case outline. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 7 Device types 01 02 and 03 Case outline X Terminal number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Terminal symbol OUT_A -IN_A +IN_A VCC +IN_B -IN_B OUT_B NC_GND (See note 1) NC_GND (See note 1) OUT_C -IN_C +IN_C VEE +IN_D -IN_D OUT_D OUT_A -IN_A +IN_A VCC +IN_B -IN_B OUT_B EN_AB (See note 2) EN_CD (See note 2) OUT_C -IN_C +IN_C VEE +IN_D -IN_D OUT_D NOTE: 1. NC_GND (pins 8 and 9) should be grounded to eliminate or minimize electrostatic discharge (ESD) or static buildup. 2. EN_AB enables amplifiers A and B, EN_CD enables amplifiers C and D. FIGURE 2. Terminal connections. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 8 FIGURE 3. Logic diagram(s). STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 9 FIGURE 4. Switching diagrams. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 10 TABLE II. Electrical test requirements. MIL-PRF-38534 test requirements Subgroups (in accordance with MIL-PRF-38534, group A test table) Interim electrical parameters 1,4,9 Final electrical parameters 1*2,3,4,5,6,9,10,11 Group A test requirements 1,2,3,4,5,6,9,10,11 Group C end-point electrical parameters 1,2,3,4,5,6,9,10,11 End-point electrical parameters for Radiation Hardness Assurance (RHA) devices 1,4,9 * PDA applies to subgroup 1. 4. VERIFICATION 4.1 Sampling and inspection. Sampling and inspection procedures shall be in accordance with MIL-PRF-38534 or as modified in the device manufacturer's Quality Management (QM) plan. The modification in the QM plan shall not affect the form, fit, or function as described herein. 4.2 Screening. Screening shall be in accordance with MIL-PRF-38534. The following additional criteria shall apply: a. b. Burn-in test, method 1015 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DLA Land and Maritime -VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1015 of MIL-STD-883. (2) TA as specified in accordance with table I of method 1015 of MIL-STD-883. Interim and final electrical test parameters shall be as specified in table II herein, except interim electrical parameter tests prior to burn-in are optional at the discretion of the manufacturer. 4.3 Conformance and periodic inspections. Conformance inspection (CI) and periodic inspection (PI) shall be in accordance with MIL-PRF-38534 and as specified herein. 4.3.1 Group A inspection (CI). Group A inspection shall be in accordance with MIL-PRF-38534 and as follows: a. Tests shall be as specified in table II herein. b. Subgroups 7, 8A , and 8B shall be omitted. 4.3.2 Group B inspection (PI). Group B inspection shall be in accordance with MIL-PRF-38534. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 11 4.3.3 Group C inspection (PI). Group C inspection shall be in accordance with MIL-PRF-38534 and as follows: a. End-point electrical parameters shall be as specified in table II herein. b. Steady-state life test, method 1005 of MIL-STD-883. (1) Test condition A, B, C, or D. The test circuit shall be maintained by the manufacturer under document revision level control and shall be made available to either DLA Land and Maritime -VA or the acquiring activity upon request. Also, the test circuit shall specify the inputs, outputs, biases, and power dissipation, as applicable, in accordance with the intent specified in method 1005 of MIL-STD-883. (2) TA as specified in accordance with table I of method 1005 of MIL-STD-883. (3) Test duration: 1,000 hours, except as permitted by method 1005 of MIL-STD-883. 4.3.4 Group D inspection (PI). Group D inspection shall be in accordance with MIL-PRF-38534. 4.3.5. Radiation hardness assurance (RHA). RHA qualification is required only for those devices with the RHA designator as specified herein. See table IIIA and table IIIB. Table IIIA. Radiation Hardness Assurance Method Table. RHA method employed NOTES: X = G = (N) = N/A = Testing at 2X rated total dose of (1 Mrad) Element Level Hybrid Device Level Yes Yes (See 4.3.5.1.1) Worst Case Analysis Performed No End point electricals after total dose Includes Combines Combines End-of-life temperature temperature total dose effects and and radiation displacement effects effects Element Level Hybrid device level TC = +25°C TC = +25°C N/A N/A N/A N/A Yes Yes Radiation testing done (Level) Guaranteed by design or process Not yet tested Not applicable for this SMD Table IIIB. Hybrid level and element level test table. Total Dose Low Dose Rate High Dose Rate (LDR) (HDR) CMOS IC NOTES: X = G = (N) = N/A = G X (2 Mrad) (See 4.3.5.1.1) ELDRS G Radiation Test Heavy Ion SET SEL (transient) (latch-up) X 59 MeV2 cm /mg X 100 MeV2 cm /mg Proton Low High Energy Energy (N) (N) SEE (upset) Neutron Displacement Damage (DD) (N) G Radiation testing done (Level) Guaranteed by design or process Not yet tested Not applicable for this SMD STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 12 4.3.5.1 Radiation Hardness Assurance (RHA) inspection. RHA qualification is required for those devices with the RHA designator as specified herein. End-point electrical parameters for radiation hardness assurance (RHA) devices shall be specified in table II. Radiation testing will be in accordance with the qualifying activity (DLA Land and Maritime -VQ) approved plan and with MIL-PRF-38534, Appendix G. a. The hybrid device manufacturer shall establish procedures controlling component radiation testing, and shall establish radiation test plans used to implement component lot qualification during procurement. Test plans and test reports shall be filed and controlled in accordance with the manufacturer's configuration management system. b. The hybrid device manufacturer shall designate a RHA program manager to oversee component lot qualification, and to monitor design changes for continued compliance to RHA requirements. 4.3.5.1.1 Hybrid level RHA qualification. Hybrid level and element level testing are the same for the devices on this Standard Microcircuit Drawing (SMD) since the active element is accessible to the device leads for test. 4.3.5.1.1.1 Qualification by similarity. The devices on this (SMD) are considered similar for the purpose of RHA testing. Device type 5962H1024102KXC was RHA tested, therefore the other device types on this SMD are qualified by similarity. 4.3.5.1.2 Element level qualification. 4.3.5.1.2.1 Total ionizing dose irradiation testing. A minimum of 5 biased devices of the active element used will be tested every wafer lot. These active element will be tested at HDR in accordance with condition A of method 1019 of MIL-STD-883 to 2 Mrad(Si) to assure 1 Mrad(Si) for the device parameters as specified in table IA herein. 4.3.5.1.2.1.1 Accelerated annealing test. Accelerated annealing tests shall be performed on all devices requiring a RHA level greater than 5k rads (Si). The post-anneal end-point electrical parameter limits shall be as specified in table IA herein and shall be the pre-irradiation end-point electrical parameter limit at 25°C ±5°C. Testing shall be performed at initial qualification and after any design or process changes which may affect the RHA response of the device. 4.3.5.1.2.2 Single Event Phenomena (SEP). A minimum of one representative hybrid from this SMD shall be characterized for SEL and SET responses at initial qualification and after any design or process change which may affect the RHA response of the devices on this SMD. Testing shall be performed in accordance with ASTM F1192. Test conditions are as follows: a. The ion beam angles of incidence for SEL shall be normal and 55 degrees to the die surface and for SET shall be normal. No shadowing of the ion beam due to fixturing is allowed. b. The fluence shall be ≥ 1x10 particles/cm . c. The flux shall be between 10 and 10 ions/cm /s. d. The particle range shall be ≥ 60 micron in silicon. e. The transient test temperature shall be +25° ±10°C and the latchup test temperature shall be +125°C ±10°C. f. For SEP test limits, see table IB herein. 7 2 2 5 2 4.3.5.2 RHA Lot Acceptance. Each wafer lot of the active element shall be evaluated for acceptance in accordance with MILPRF-38534 and herein. 4.3.5.2.1 Total Ionizing Dose (TID). See paragraph 4.3.5.1.2.1 and 4.3.5.1.2.1.1 herein. 4.3.5.2.2 Enhanced Element Evaluation. Enhanced Element Evaluation per Table IV herein including 45 devices subjected to Group C2, 1000 hours life testing, is required only for those devices with the RHA designator as specified herein. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 13 Table IV. Enhanced Element Evaluation For Microcircuit Die. Subgroup 2 Class K X Test MIL-STD-883 Method Condition 2010 1 3 4 X X X Element visual Assembled into package as specified in 1.2.4 herein. Element electrical Internal visual Temperature cycling X Constant acceleration 2001 X Burn-in 1015 X X Interim electrical Burn-in 1015 X X Post burn-in Final Electrical, Group A Steady-state life 1005 5 X X Final electrical Wire bond evaluation 3/ 2011 6 X SEM 2018 2017 1010 C Quantity (accept number) 100 percent 100 percent Reference Paragraph 1/ C.3.3.2 100 percent 100 percent C.3.3.1 C.5.5 C.3.3.3 100 percent 3000g’s, Y1 direction 160 hours minimum at +125°C C.5.6 C.3.3.4.3 160 hours minimum at +125°C C.5.10 1000 hours minimum at +125°C 45(0) 2/ 10(0) wires or 20(1) wires See method 2018 of MIL-STD-883 C.3.3.4.3 C.3.3.3 C.3.3.5 C.3.3.6 1/ See MIL-PRF-38534. 2/ Die shall be traceable to the wafer and wafer lot. The sample size shall consist of a minimum of 3 die from each wafer and a minimum of 45 die from each wafer lot. 3/ The devices herein is manufactured with aluminum wires and aluminum bond sites on the IC. No bimetallic bonds. 5. PACKAGING 5.1 Packaging requirements. The requirements for packaging shall be in accordance with MIL-PRF-38534. 6. NOTES 6.1 Intended use. Microcircuits conforming to this drawing are intended for use for Government microcircuit applications (original equipment), design applications, and logistics purposes. 6.2 Replaceability. Microcircuits covered by this drawing will replace the same generic device covered by a contractorprepared specification or drawing. 6.3 Configuration control of SMD's. All proposed changes to existing SMD's will be coordinated as specified in MIL-PRF38534. 6.4 Record of users. Military and industrial users shall inform DLA Land and Maritime when a system application requires configuration control and the applicable SMD to that system. DLA Land and Maritime will maintain a record of users and this list will be used for coordination and distribution of changes to the drawings. Users of drawings covering microelectronic devices (FSC 5962) should contact DLA Land and Maritime-VA, telephone (614) 692-8108. STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 14 6.5 Comments. Comments on this drawing should be directed to DLA Land and Maritime-VA, Columbus, Ohio 43218-3990, or telephone (614) 692-1081. 6.6 Sources of supply. Sources of supply are listed in MIL-HDBK-103 and QML-38534. The vendors listed in MIL-HDBK-103 and QML-38534 have submitted a certificate of compliance (see 3.7 herein) to DLA Land and Maritime-VA and have agreed to this drawing. 6.7 Additional information. When applicable, a copy of the following additional data shall be maintained and available from the device manufacturer. a. RHA upset levels. b. Test conditions (SEP). c. Number of transients (SEP). d. Occurance of latchup (SEP). STANDARD MICROCIRCUIT DRAWING DLA LAND AND MARITIME COLUMBUS, OHIO 43218-3990 DSCC FORM 2234 APR 97 SIZE 5962-10241 A REVISION LEVEL SHEET 15 STANDARD MICROCIRCUIT DRAWING BULLETIN DATE: 13-03-26 Approved sources of supply for SMD 5962-10241 are listed below for immediate acquisition information only and shall be added to MIL-HDBK-103 and QML-38534 during the next revisions. MIL-HDBK-103 and QML-38534 will be revised to include the addition or deletion of sources. The vendors listed below have agreed to this drawing and a certificate of compliance has been submitted to and accepted by DLA Land and Maritime -VA. This information bulletin is superseded by the next dated revisions of MIL-HDBK-103 and QML-38534. DLA Land and Maritime maintains an online database of all current sources of supply at http://www.landandmaritime.dla.mil/Programs/Smcr/. Standard microcircuit drawing PIN 1/ Vendor CAGE number Vendor similar PIN 2/ 5962-1024101KXA 5962H1024101KXA 5962-1024101KXC 5962H1024101KXC 88379 88379 88379 88379 RHD5900-201-2S RHD5900-901-2S RHD5900-201-1S RHD5900-901-1S 5962-1024102KXA 5962H1024102KXA 5962-1024102KXC 5962H1024102KXC 88379 88379 88379 88379 RHD5901-201-2S RHD5901-901-2S RHD5901-201-1S RHD5901-901-1S 5962-1024103KXA 5962H1024103KXA 5962-1024103KXC 5962H1024103KXC 88379 88379 88379 88379 RHD5902-201-2S RHD5902-901-2S RHD5902-201-1S RHD5902-901-1S 1/ The lead finish shown for each PIN representing a hermetic package is the most readily available from the manufacturer listed for that part. If the desired lead finish is not listed contact the Vendor to determine its availability. 2/ Caution. Do not use this number for item acquisition. Items acquired to this number may not satisfy the performance requirements of this drawing. Vendor CAGE number 88379 Vendor name and address Aeroflex Plainview Incorporated, (Aeroflex Microelectronic Solutions) 35 South Service Road Plainview, NY 11803-4193 The information contained herein is disseminated for convenience only and the Government assumes no liability whatsoever for any inaccuracies in the information bulletin.