Standard Products ACT5271SC Multichip Module Microprocessor with 2MB Secondary Cache www.aeroflex.com/Avionics May 5, 2005 FEATURES ❑ Footprint Compatible with Aeroflex-Plainview original ACT4431SC 1MB Secondary Cache MCM in a 280 lead Ceramic Quad Flat Pack (CQFP) ❑ QED RM5271 Dual Issue superscalar microprocessor - can issue one integer and one floating-point instruction per cycle - Max system clock – 25MHz, Max Secondary Cache (SC) clock 75MHz, Max pipeline 150MHz ❑ High performance system interface compatible with R4400 - Internal PLL generates selectable 2x/3x SC bus speed operation vs external system bus speed - Generates R4400 style system clocks - CPU cycle rate buffering FIFO implemented in FPGA - 64-bit multiplexed system address/data bus for optimum price/performance - High performance write protocols maximize uncached write bandwidth - Operates at processor clock multipliers 2, 2.5 & 3 ❑ Integrated on-chip Primary Caches - 32KB instruction - 2 way set associative - 32KB data - 2 way set associative - Virtually indexed, physically tagged - Write-back and write-through on per page basis - Pipeline restart on first double for data cache misses ❑ Integrated in-module Secondary Cache - 2MB shared write-through - 4-128K x 36 Synchronous SRAM and 1-64K x 18 Tag RAM ❑ Integrated memory management unit - Fully associative joint TLB (shared by I and D translations) - 48 dual entries map 96 pages - Variable page size (4KB to 16MB in 4x increments) ❑ High-performance floating point unit - Single cycle repeat rate for common single precision operations and some double precision operations - Two cycle repeat rate for double precision multiply and double precision combined multiply-add operations - Single cycle repeat rate for single precision combined multiply-add operation ❑ MIPS IV instruction set - Floating point multiply-add instruction increases performance in signal processing and graphics applications - Conditional moves to reduce branch frequency - Index address modes (register + register) ❑ Embedded application enhancements - Specialized DSP integer Multiply-Accumulate instruction and 3 operand multiply instruction - I and D cache locking by set - Optional dedicated exception vector for interrupts SCD5271SC Rev B SCD5271SC Rev B 2 Clks Int* SysCmd SysAD CPU Cycle FIFO Parity Invert SyncIn Int* ACT-5271SC SIMPLIFIED BLOCK DIAGRAM Reset = VccOk, ModeClk, ModeData, ColdReset*, Reset* Clks = TClock (1:0), RClock (1:0), MasterOut, SyncOut FPGA Control Clock Gen 2MB Secondary Cache Read Data/Cmd Reg. CPU SysAD S-Cache Control Multiplied CLK (2x or 3x) Clks RM5271 CPU Control = ValidOut*, Release*, RdRdy*, WrRdy*, ValidIn*, ExtRqst*, CPUMULT MasterClock Reset Control Control CPLD CPU SysCmd CPU Reset CPU Control DESCRIPTION sequence is followed via ModeClock, ModeIn, ColdResetB up to when ResetB is deasserted The RM5271 will, in turn, start its initialization when the internal PLL is Locked and ColdResetB is deasserted. The CPUs resetb is released with ResetB after checking to see that the FPGAs have configured. The actual mode bit stream sent to the RM5271 is created by the internal CPLD with a few pertinent bits stripped off the incoming stream: Endianness and Secondary Cache enable. For this design, the interface XmitDatPat is fixed at DDDD. The ACT-5271SC MCM consists of a QED RM5271 MIPS microprocessor with 2 MByte of shared, write-through Secondary Cache. The MCM translates the R4400 style clocking, bus and modebit information to what the RM5271 expects. This is accomplished by means of a PLL clock generator, a control CPLD and an FPGA based cycle FIFO. PINOUT COMPATIBILITY The ACT-5271SC was designed as a high performance upgrade replacement for the ACT-4431SC. The 280 lead flatpack package outline was retained and the pinout is compatible, with the following exceptions: ■ ■ ■ ■ ■ CYCLE FIFO The FIFO, implemented in an FPGA, accepts RM5271 CPU read and write cycle information direct from the CPU SysAD bus at the CPU clock rate and retransmits it to the MCM SysAD at the board’s clock rate. Since the RM5271 does not normally output parity information on the address phase or the command bus, the parity information is added to the data captured from the CPU before it is entered into the FIFO. For Read data, if bad data is indicated by the Command bus (bit 5), the parity output to the RM5271 is inverted for that item, and all remaining ones in the case of a burst. Read cycles that hit in the Secondary Cache are not entered into the FIFO. The reassignment of twenty-six - 3.3 volt supply pins to a core voltage of 2.5 volts. VccP, the quiet PLL supply is now 2.5 volts Ten previously unused pins are now used for test modes and programmable device configuration. They are pins 171-175, 177, 183, 184, 195 and 196. They should remain no connects (NC) at the board level. Certain special R4400 and ACT-4431SC function signals are not available and are no connects (NC) within the module substrate. These signals include IO_IN, IO_OUT, Status[7:0], IVDErrb, IVDAckb, 256K/1MB and FaultB. The JTAG port does not support complete boundary scan for the module. The JTAG is used to initialize the CPLD, which is one component in a chain of four. CLOCKING AND SPEEDS The design is tailored towards replacing an ACT-4431SC device running with a 50 MHz MasterClock (100 MHz Pipeline Clock) and a TClock /RClock divisor of 4 (25 MHz). In order to mitigate the speed limitation of a 25 MHz SysAD bus, the ACT-5271SC utilizes a PLL clock multiplier and CPU cycle FIFO to run the RM5271 and the Secondary Cache connected to its SysAD bus at a higher rate. For a 25 MHz external bus, the cache bus can run at 50 MHz or 75 MHz (2x or 3x). The RM5271 pipeline can be 2, 2.5 or 3 times the cache speed. Specifically, the R4400 style MasterClock is buffered and output as MasterOut. ModeClock is a divide by 256 of MasterOut. MasterClock is also divided by 2 to produce RClock, TClock and SyncOut. TClock and SyncOut are delayed from RClock by one buffer. SyncIn feeds the internal PLL multiplier circuit which drives the RM5271’s SysClock and Secondary Cache RAMs at 2x or 3x. The RM5271’s pipeline frequency is then determined by the modebit settings generated by the internal CPLD. The two Secondary Cache multiplier variations are selectable at module pin 195, for experimentation purposes. For additional Detail Information regarding the operation of the Quantum Effect Devices (QED) RISCMark™ RM5271SC™, 64-Bit Superscalar Microprocessor see the latest QED datasheet (Revision 1.3 2/2000). START UP SEQUENCE The process begins with the SRAM based FPGAs loading from an on-module serial EEPROM when VDDOK is asserted. At the same time, the standard R4400 startup SCD5271SC Rev B 3 TClock(1:0) RClock(1:0) MasterClock MasterOut SyncOut SyncIn VccP VssP 2 Interrupt Interface SysAD(63:0) SysADC(7:0) SysCmd(8:0) SysCmdP ValidIn* ValidOut* ExtRqst* Release* RdRdy* WrRdy* 64 CPUInt(5:0)* NMI* 8 ACT-5271SC Multichip Module 280 Lead CQFP JTDI JTDO JTMS JTCK JTAG Interface ModeClock ModeIn VccOk ColdReset* Reset* VccInt Vcc Vss Initialization Interface 9 Power Clock/Control Interface System Interface 6 2 26 40 68 32 Case Ground NC MODULE SYMBOLIC INTERFACE CONNECTIONS SCD5271SC Rev B 4 ABSOLUTE MAXIMUM RATING 1 PARAMETER SYMBOL Terminal Voltage with respect to VSS VTERM Input Voltage Range VIN LIMITS UNITS -0.5 2 to +3.9 V -0.5 2 to Vcc+0.5 V TBIAS Case Operating Temperature under Bias -55 to +125 °C TSTG Storage Temperature -65 to +150 °C PD Maximum Power Dissipation 10 W ØJC Thermal Resistance (Junction to Case) 2.5 °C/W TL Maximum Lead Temperature (10 seconds) 300 °C Note 1: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Note 2: VIN minimum = -2.0V for pulse width less than 15ns. VIN should not exceed 3.9 Volts. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER VSS Supply Ground VCC Supply Voltage VCCInt VCCP MIN MAX UNITS 0 V 3.1 3.5 V Supply Voltage for RM5271 Core 2.4 2.6 V Quiet VCC for PLL 2.4 2.6 V VIH High Level Input Voltage 2.0 Vcc + 0.5 V VIL Low Level Input Voltage -0.5 +0.66 V TC Case Operating Temperature -55 +125 °C Note: 1. VCC I/O should not exceed VccInt by greater than 1.2V during the power-up sequence. 2. Applying a logic high state to any I/O pin before VccInt becomes stable is not recommended. 3. As specified in IEEE 1149.1 (JTAG), the JTMS pin must be held low during reset to avoid entering JTAG test mode. Refer to the RM5200 Family Users Manual, Appendix F. SCD5271SC Rev B 5 SIGNAL DESCRIPTIONS System Interface SysADy(63:0) SysADC (7:0) SysCmd (8:0) SysCmdP I/O System address/data bus: A 64 bit address and data bus for communication between the processor and an external agent I/O System address/data check bus: An 8 bit bus containing check bits for the SysAD bus bus during data cycles I/O System command/identifier bus parity: A 9 bit bus for command and data identifier transmission between the processor and an external agent I/O System command /data identifier bus parity: A single, even parity bit for thr SysCmd bus Validin* I Valid Input: An external agent asserts ValidIn* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SysCmd bus O Valid Output: The processor asserts ValidOut* when it is driving a valid address or data on the SysAD bus and a valid command or data identifier on the SYSCMD bus I External Request: An external agent asserts ExtRqst* to request the use of the system interface. The processor grants the request by asserting Release* O Release Interface: In response to the assertion of ExtRqst*, the processor asserts Release* to signal the requesting device that the system interface is available I Read ready: The external agent asserts RdRdy* to indicate that it can accept processor read I Write ready: An external agent asserts WrRdy* when it can accept a processor write request ValidOut* ExtRqst* Release* RdRdy* WrRdy* SCD5271SC Rev B 6 SIGNAL DESCRIPTIONS con’t Clock/Control Interface TClock (1:0) O Transmit clocks: Two identical transmit clocks that establish the system interface frequency O Receive clocks: Two identical receive clocks that establish the system interface frequency MasterClock I Master clock: Master clock input supplied by system MasterOut O Master clock out: Clock output buffered MasterClock O Synchronization clock out: Synchronization clock output must be connected to SyncIn through an interconnect that models the interconnect between MasterOut, TClock, RClock, and the external agent SyncIn I Synchronization clock in: Synchronization clock input VccP I Quiet Vcc for the PLL: Quiet Vcc for the internal phase lock loop VssP I Quiet Vss for the PLL: Quiet Vss for the internal phase lock loop RClock (1:0) SyncOut SCD5271SC Rev B 7 SIGNAL DESCRIPTIONS con’t Interrupt Interface: These signals comprise the interface used by external agents to interrupt the RM5271 processor CPUInt (5:0) NMI* I Interrupt: Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register I Nonmaskable interrupt: Nonmaskable interrupt ORed with bit 6 of the interrupt register Initialization Interface: These signals comprise the interface by which an external agent initializes the RM5271 operating parameters ColdReset* ModeClock ModeIn I Cold Reset: This signal must be asserted for a power on reset or a cold reset O Boot Mode Clock: Serial boot-mode data clock output at the system clock frequency divided by 256 I Boot mode data in: Serial boot-mode data input I Reset: This signal must be asserted for any reset sequence. It may be asserted synchronously or asynchronously for a cold reset, or synchronously to initate a warm reset I Vcc is OK: When asserted, this signal tells the RM5271 that the 3.3 Volt power supply has been above 3.15 Volts for more than 100 milliseconds & will remain stable. Assertion of VccOK starts initialization sequence. Reset* VccOk JTAG Interface Signals JTDI I JTAG data in: Data is serial, scanned in thru this pin I JTAG clock input: On the rising edge of JTCK, both JTDI and JTMS are sampled. JTDO O JTAG data out: Data is serial, scanned out thru this pin JTMS I JTAG: Test mode select VccInt I Supply voltage for RM5271 core Vcc I Supply voltage Vss I Supply ground JTCK Power SCD5271SC Rev B 8 ACT5271SC MICROPROCESSOR CQFP PINOUTS – "F10" Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Function TClock0 Vss SysAD45 Vss TClock1 Vss SysAD13 Vss SysAD14 Vcc JTMS **VccInt SysAD46 Vcc JTDO **VccInt SysAD15 Vcc SysAD47 Vss NC Vcc JTDI Vss SysADC1 **VccInt SysADC5 Vcc NC **VccInt NC Vcc JTCK Vss SyncIn Vss NC Vss NC Vss MasterClock Vss NC Vcc NC **VccInt NC Pin # 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 Function Vss VssP Vcc NC Vss VccP **VccInt NC Vss NC Vcc NC **VccInt SysADC7 Vcc SysADC3 **VccInt VccOk Vcc SysAD63 Vss MasterOut Vss SysAD31 Vcc SysAD30 Vcc SysAD62 Vss SyncOut Vss SysAD29 Vss RClock1 Vss Sys AD61 Vss RClock0 Vss Vcc Reset* **VccInt SysAD60 Vss SysAD28 Vcc ColdReset* ** These 26 VccInt pins may be 1.8V in future higher performance modules. SCD5271SC Rev B 9 Pin # 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 Function Vss SysAD59 **VccInt SysAD27 Vss NC Vcc SysAD58 Vss SysAD26 Vcc NC Vss SysAD57 **VccInt SysAD25 Vss NC Vcc SysAD56 Vss SysAD24 **VccInt NC Vss SysADC6 Vcc SysADC2 Vss NMI* Vcc SysAD55 Vss SysAD23 **VccInt Release* Vss SysAD22 Vcc SysAD54 Vss ModeIn **VccInt RdRdy* Vss SysAD53 SysAD21 ACT5271SC MICROPROCESSOR CQFP PINOUTS – "F10" con’t Pin # 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 Function Vss ExtRqst* Vcc SysAD52 Vss ValidOut* Vcc SysAD20 Vss SysAD19 **VccInt SysAD51 Vss ValidIn* Vcc SysAD18 Vss SysAD50 **VccInt CPUInt0 Vss SysAD49 Vcc SysAD17 Vss SysAD16 Vcc SysAD48 Vss NC (SP_SER_EN) NC (SP_OE) NC (SP_CE) NC (SP_CCCK) NC (SP_DATA) NC NC (ISP_EN) Vss CPUInt1 Vcc CPUInt2 Vss NC (IN_P5064) NC (DCD_SEL) CPUInt3 NC NC Vss Pin # Function Pin # 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 CPUInt4 **VccInt CPUInt5 Vss **VccInt NC (256K/1MB) NC (CPUMULT) NC (Prog_FPGA) NC CASE GROUND Vss SysAD32 Vcc SysAD0 Vss SysAD1 **VccInt SysAD33 Vss SysAD34 Vcc SysAD2 Vss SysCmd0 **VccInt SysAD35 Vss SysAD3 Vcc SysAD4 Vss SysCmd1 Vcc SysAD36 Vss SysCmd2 **VccInt SysAD5 SysAD37 Vss ModeClock Vcc WrRdy* Vss SysAD6 **VccInt SysAD38 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 ** These 26 VccInt pins may be 1.8V in future higher performance modules. SCD5271SC Rev B 10 Function Vss SysCmd3 Vcc SysAD7 Vss SysAD39 Vcc SysCmd4 Vss SysADC0 Vcc SysADC4 Vss SysCmd5 **VccInt SysAD8 Vss SysAD40 Vcc SysCmd6 Vss SysAD9 **VccInt SysAD41 Vss SysCmd7 Vcc SysAD10 Vss SysAD42 **VccInt SysCmd8 Vss SysAD11 Vcc SysAD43 Vss SysCmdP **VccInt SysAD12 Vss SysAD44 Vcc NC Vss PACKAGE INFORMATION – "F10" – CQFP 280 LEADS 2.525 MAX 2.125 86 Leads @ .025 Spacing Pin 141 Pin 226 Pin 227 1.325 54 Leads @ .025 Spacing Pin 140 ACT-5271SC 1.768 MAX .012 .009 Pin 280 Pin 87 Pin 1 Pin 86 .175 MAX .072 ±.010 (Dimensions are in inches) SCD5271SC Rev B 11 .008 .005 Note: Outside ceramic tie bars not shown for clarity. Contact factory for details SAMPLE ORDERING INFORMATION PART NUMBER SCREENING SPEED (MHZ) PACKAGE ACT-5271SC-150F10C Commercial Temperature 150 280 Lead CQFP ACT-5271SC-150F10I Industrial Temperature ACT-5271SC-150F10T Military Temperature ACT-5271SC-150F10M Military Screening AEROFLEX PART NUMBER BREAKDOWN ACT– 5271 SC – 150 F10 M Aeroflex Plainview Screening Base Processor Type C = Commercial Temp, 0°C to +70°C I = Industrial Temp, -40°C to +85°C T = Military Temp, -55°C to +125°C M = Military Temp, -55°C to +125°C, Screened * Cache Style SC = Secondary Cache Maximum Pipeline Freq. Package Type & Size Surface Mount Package F10 = 2.525" x 1.768" x 280 Lead CQFP 150 = 150MHz * Screened to the individual test methods of MIL-STD-883 PLAINVIEW, NEW YORK Toll Free: 800-THE-1553 Fax: 516-694-6715 INTERNATIONAL Tel: 805-778-9229 Fax: 805-778-1980 NORTHEAST Tel: 603-888-3975 Fax: 603-888-4585 SE AND MID-ATLANTIC Tel: 321-951-4164 Fax: 321-951-4254 WEST COAST Tel: 949-362-2260 Fax: 949-362-2266 CENTRAL Tel: 719-594-8017 Fax: 719-594-8468 www.aeroflex.com [email protected] Aeroflex Microelectronic Solutions reserves the right to change at any time without notice the specifications, design, function, or form of its products described herein. All parameters must be validated for each customer's application by engineering. No liability is assumed as a result of use of this product. No patent licenses are implied. All trademarks are acknowledged. Parent company Aeroflex, Inc. 2003. SCD5271SC Rev B 12 Our passion for performance is defined by three attributes represented by these three icons: solution-minded, performance-driven and customer-focused