FUNCTIONAL BLOCK DIAGRAM PDWN DRVDD 14 VIN+A VIN–A 14 VIN+B DIGITAL SERIALIZER PIPELINE ADC VIN–B RBIAS VREF SENSE 1V REF SELECT VIN+D VIN–D PIPELINE ADC DIGITAL SERIALIZER 14 DIGITAL SERIALIZER CLK– CLK+ CLOCK MANAGEMENT SYNC SERIAL PORT INTERFACE SCLK/DTP VCM D0+B D0–B SERIAL LVDS SERIAL LVDS D1+B D1–B FCO+ FCO– D0+C D0–C D1+C D1–C SERIAL LVDS D0+D D0–D SERIAL LVDS D1+D D1–D DCO+ DCO– SERIAL LVDS 14 PIPELINE ADC SERIAL LVDS AD9253-EP AGND VIN+C VIN–C SERIAL LVDS D0+A D0–A D1+A D1–A SERIAL LVDS DIGITAL SERIALIZER PIPELINE ADC Figure 1. designed to maximize flexibility and minimize system cost, such as programmable output clock and data alignment and digital test pattern generation. The available digital test patterns include built-in deterministic and pseudorandom patterns, along with custom user-defined test patterns entered via the serial port interface (SPI). APPLICATIONS Medical ultrasound High speed imaging Quadrature radio receivers Diversity radio receivers Test equipment GENERAL DESCRIPTION The AD9253-EP is a quad, 14-bit, 125 MSPS analog-to-digital converter (ADC) with an on-chip, sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 125 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes less than 2 mW when all channels are disabled. The ADC contains several features Rev. A AVDD CSB 1.8 V supply operation Military temperature range (−55°C to +125°C) Controlled manufacturing baseline Qualification data available on request Low power: 110 mW per channel at 125 MSPS SNR = 74 dB (to Nyquist) SFDR = 90 dBc (to Nyquist) DNL = ±0.8 LSB (typical); INL = ±2.0 LSB (typical) Serial LVDS (ANSI-644, default) and low power, reduced signal option (similar to IEEE 1596.3) 650 MHz full power analog bandwidth 2 V p-p input voltage range Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built-in and custom digital test pattern generation Multichip sync and clock divider Programmable output clock and data alignment Programmable output resolution Standby mode 10065-001 FEATURES SDIO/OLM Enhanced Product Quad, 14-Bit, 125 MSPS Serial LVDS 1.8 V Analog-to-Digital Converter AD9253-EP The AD9253-EP is available in a RoHS-compliant, 48-lead LFCSP and is specified over an extended temperature range of −55°C to +125°C. This product is protected by a U.S. patent. Additional application and technical information can be found in the AD9253 data sheet. PRODUCT HIGHLIGHTS 1. 2. 3. 4. Small Footprint. Four ADCs are contained in a small, spacesaving package. Low power of 110 mW/channel at 125 MSPS with scalable power options. Ease of Use. A DCO operates at frequencies of up to 500 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2013–2015 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com AD9253-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Digital Specifications ....................................................................5 Applications ....................................................................................... 1 Switching Specifications ...............................................................6 General Description ......................................................................... 1 Absolute Maximum Ratings ............................................................7 Functional Block Diagram .............................................................. 1 Thermal Resistance .......................................................................7 Product Highlights ........................................................................... 1 ESD Caution...................................................................................7 Revision History ............................................................................... 2 Pin Configuration and Function Descriptions..............................8 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 10 DC Specifications ......................................................................... 3 Ordering Guide .......................................................................... 10 AC Specifications.......................................................................... 4 REVISION HISTORY 10/15—Rev. 0 to Rev. A Added Note 4, Table 4 ...................................................................... 6 Added Note 1, Table 7 ...................................................................... 9 Updated Outline Dimensions ....................................................... 10 2/13—Revision 0: Initial Version Rev. A | Page 2 of 10 Enhanced Product AD9253-EP SPECIFICATIONS DC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 1. Parameter1 RESOLUTION ACCURACY No Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Temp Full Full Full Full Full Full 25°C Integral Nonlinearity (INL) Full 25°C TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage (1 V Mode) Load Regulation at 1.0 mA (VREF = 1 V) Input Resistance INPUT-REFERRED NOISE VREF = 1.0 V ANALOG INPUTS Differential Input Voltage (VREF = 1 V) Common-Mode Voltage Differential Input Resistance Differential Input Capacitance POWER SUPPLY AVDD DRVDD IAVDD2 IDRVDD (ANSI-644 Mode)2 IDRVDD (Reduced Range Mode)2 TOTAL POWER CONSUMPTION DC Input Min 14 Guaranteed −0.3 +0.1 +0.2 +0.6 −3 +2 1.1 1.6 −0.8 +1.9 ±0.8 −4.5 0.98 +4.5 ±2.0 LSB LSB ±2 ±50 ppm/°C ppm/°C 1.0 2 7.5 1.02 Rev. A | Page 3 of 10 V mV kΩ LSB rms Full Full 2 0.9 5.2 3.5 V p-p V kΩ pF 1.7 1.7 1.8 1.8 183 61 53 Full 403 Full 25°C Full Full 440 425 2 235 1.9 1.9 205 63 V V mA mA mA 480 mW mW mW mW mW See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured with a low input frequency, full-scale sine wave on all four channels. 3 It can be controlled via the SPI. 2 % FSR % FSR % FSR % FSR LSB LSB 0.94 Full Full Full Full 25°C 1 Unit Bits 25°C Full Sine Wave Input (Four Channels Including Output Drivers ANSI-644 Mode) Sine Wave Input (Four Channels Including Output Drivers Reduced Range Mode) Power-Down Mode Standby Mode3 Max −0.8 −0.6 −12 Full Full Full Full Full Typ AD9253-EP Enhanced Product AC SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 2. Parameter1 SIGNAL-TO-NOISE RATIO (SNR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz EFFECTIVE NUMBER OF BITS (ENOB) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz SPURIOUS-FREE DYNAMIC RANGE (SFDR) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz WORST HARMONIC (SECOND OR THIRD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz WORST OTHER HARMONIC (EXCLUDING SECOND OR THIRD) fIN = 9.7 MHz fIN = 30.5 MHz fIN = 70 MHz fIN = 140 MHz fIN = 200 MHz TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS fIN1 = 70.5 MHz, fIN2 = 72.5 MHz CROSSTALK2 CROSSTALK (OVERRANGE CONDITION)3 POWER SUPPLY REJECTION RATIO (PSRR)4 AVDD DRVDD ANALOG INPUT BANDWIDTH, FULL POWER Temp Min Typ 72 75.3 75.2 74.1 72.2 70.7 dBFS dBFS dBFS dBFS dBFS 71.7 75.2 75.1 74.0 71.9 70.4 dBFS dBFS dBFS dBFS dBFS 25°C 25°C Full 25°C 25°C 12.2 12.2 12.0 11.7 11.4 Bits Bits Bits Bits Bits 25°C 25°C Full 25°C 25°C 98 92 90 85 83 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C −98 −92 −90 −85 −83 −76 dBc dBc dBc dBc dBc 25°C 25°C Full 25°C 25°C −101 −100 −95 −96 −92 −83 dBFS dBFS dBFS dBFS dBFS 25°C Full 25°C 86 −95 −89 dBc dB dB 25°C 25°C 25°C 48 75 650 dB dB MHz 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 76 Max Unit See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Crosstalk is measured at 70 MHz with an −1.0 dBFS analog input on one channel and no input on the adjacent channel. The overrange condition is specified with 3 dB of the full-scale input range. 4 PSRR is measured by injecting a sinusoidal signal at 10 MHz to the power supply pin and measuring the output spur on the FFT. PSRR is calculated as the ratio of the amplitudes of the spur voltage over the pin voltage, expressed in decibels. 1 2 3 Rev. A | Page 4 of 10 Enhanced Product AD9253-EP DIGITAL SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 3. Parameter1 CLOCK INPUTS (CLK+, CLK−) Logic Compliance Differential Input Voltage2 Input Voltage Range Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SYNC, SCLK) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/OLM) Logic 1 Voltage Logic 0 Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/OLM)3 Logic 1 Voltage (IOH = 800 μA) Logic 0 Voltage (IOL = 50 µA) DIGITAL OUTPUTS (D0±x, D1±x), ANSI-644 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D0±x, D1±x), LOW POWER, REDUCED SIGNAL OPTION Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) Temp Min Full Full Full 25°C 25°C CMOS/LVDS/LVPECL 0.2 3.6 AGND − 0.2 AVDD + 0.2 0.9 15 4 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Full Full 25°C 25°C 1.2 0 Typ Max V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF AVDD + 0.2 0.8 V V kΩ pF 26 2 26 5 1.79 0.05 2 Rev. A | Page 5 of 10 V V Full Full 290 1.15 LVDS 345 400 1.25 1.35 Twos complement mV V Full Full 160 1.15 LVDS 200 230 1.25 1.35 Twos complement mV V See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. This is specified for LVDS and LVPECL only. 3 This is specified for 13 SDIO/OLM pins sharing the same connection. 1 V p-p V V kΩ pF AVDD + 0.2 0.8 30 2 Full Full Unit AD9253-EP Enhanced Product SWITCHING SPECIFICATIONS AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −1.0 dBFS, unless otherwise noted. Table 4. Parameter1, 2 CLOCK3 Input Clock Rate Conversion Rate4 Clock Pulse Width High (tEH) Clock Pulse Width Low (tEL) OUTPUT PARAMETERS3 Propagation Delay (tPD) Rise Time (tR) (20% to 80%) Fall Time (tF) (20% to 80%) FCO Propagation Delay (tFCO) DCO Propagation Delay (tCPD)5 DCO-to-Data Delay (tDATA)5 DCO-to-FCO Delay (tFRAME)5 Lane Delay (tLD) Data to Data Skew (tDATA-MAX − tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power-Down)6 Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter, tJ) Out-of-Range Recovery Time Temp Min Full Full Full Full 10 10 Max Unit 1000 125 4.00 4.00 MHz MSPS ns ns Full 25°C 25°C Full 2.3 300 300 2.3 tFCO + (tSAMPLE/16) (tSAMPLE/16) (tSAMPLE/16) 90 ±50 250 375 16 ns ps ps ns ns ps ps ps ps ns μs Clock cycles 25°C 25°C 25°C 1 135 1 Full Full Full Full Full Full Full 1.5 (tSAMPLE/16) − 300 (tSAMPLE/16) − 300 Typ 3.1 (tSAMPLE/16) + 300 (tSAMPLE/16) + 300 ±200 ns fs rms Clock cycles See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. Measured on standard FR-4 material. 3 Can be adjusted via the SPI. The conversion rate is the clock rate after the divider. 4 The maximum conversion rate is based on two-lane output mode. See the Digital Outputs and Timing section of the AD9253 data sheet for the maximum conversion rate in one-lane output mode. 5 tSAMPLE/16 is based on the number of bits in two LVDS data lanes. tSAMPLE = 1/fS. 6 Wake-up time is defined as the time required to return to normal operation from power-down mode. 1 2 Rev. A | Page 6 of 10 Enhanced Product AD9253-EP ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 5. Parameter Electrical AVDD to AGND DRVDD to AGND Digital Outputs (D0±x, D1±x, DCO+, DCO−, FCO+, FCO−) to AGND CLK+, CLK− to AGND VIN+x, VIN−x to AGND SCLK/DTP, SDIO/OLM, CSB to AGND SYNC, PDWN to AGND RBIAS to AGND VREF, SENSE to AGND Environmental Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, 10 sec) Storage Temperature Range (Ambient) Rating Table 6. −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V Package Type 48-Lead LFCSP −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V −0.3 V to +2.0 V Air Flow Velocity (m/sec) 0.0 1.0 2.5 1 θJA1 20.3 17.6 16.5 ΨJT 0.10 0.16 0.20 ΨJB 5.9 N/A2 N/A2 θJC θJC TOP BOTTOM 6.1 N/A2 N/A2 1.0 N/A2 N/A2 Unit °C/W °C/W °C/W θJA for a 4-layer printed circuit board (PCB) with solid ground plane (simulated). Exposed pad soldered to PCB. 2 N/A = not applicable. ESD CAUTION −55°C to +125°C 150°C 300°C −65°C to +150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Rev. A | Page 7 of 10 AD9253-EP Enhanced Product 48 47 46 45 44 43 42 41 40 39 38 37 VIN+C VIN–C AVDD AVDD SYNC VCM VREF SENSE RBIAS AVDD VIN–B VIN+B PIN CONFIGURATION AND FUNCTION DESCRIPTIONS AD9253-EP TOP VIEW (Not to Scale) 36 35 34 33 32 31 30 29 28 27 26 25 VIN+A VIN–A AVDD PDWN CSB SDIO/OLM SCLK/DTP DRVDD D0+A D0–A D1+A D1–A NOTES 1. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE PACKAGE PROVIDES THE ANALOG GROUND FOR THE PART. THIS EXPOSED PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION. 10065-007 D1–C D1+C D0–C D0+C DCO– DCO+ FCO– FCO+ D1–B D1+B D0–B D0+B 13 14 15 16 17 18 19 20 21 22 23 24 VIN+D 1 VIN–D 2 AVDD 3 AVDD 4 CLK– 5 CLK+ 6 AVDD 7 DRVDD 8 D1–D 9 D1+D 10 D0–D 11 D0+D 12 Figure 2. Pin Configuration, Top View Table 7. Pin Function Descriptions1 Pin No. 0 1 2 3, 4, 7, 34, 39, 45, 46 5, 6 8, 29 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Mnemonic AGND, Exposed Pad VIN+D VIN−D AVDD CLK−, CLK+ DRVDD D1−D D1+D D0−D D0+D D1−C D1+C D0−C D0+C DCO− DCO+ FCO− FCO+ D1−B D1+B D0−B D0+B D1−A D1+A D0−A D0+A Description Analog Ground, Exposed Pad. The exposed thermal pad on the bottom of the package provides the analog ground for the part. This exposed pad must be connected to ground for proper operation. ADC D Analog Input True. ADC D Analog Input Complement. 1.8 V Analog Supply Pins. Differential Encode Clock. PECL, LVDS, or 1.8 V CMOS inputs. Digital Output Driver Supply. Channel D Digital Output 1 Complement. Channel D Digital Output 1 True. Channel D Digital Output 0 Complement. Channel D Digital Output 0 True. Channel C Digital Output 1 Complement. Channel C Digital Output 1 True. Channel C Digital Output 0 Complement. Channel C Digital Output 0 True. Data Clock Output Complement. Data Clock Output True. Frame Clock Output Complement. Frame Clock Output True. Channel B Digital Output 1 Complement. Channel B Digital Output 1 True. Channel B Digital Output 0 Complement. Channel B Digital Output 0 True. Channel A Digital Output 1 Complement. Channel A Digital Output 1 True. Channel A Digital Output 0 Complement. Channel A Digital Output 0 True. Rev. A | Page 8 of 10 Enhanced Product Pin No. 30 31 32 33 Mnemonic SCLK/DTP SDIO/OLM CSB PDWN 35 36 37 38 40 41 42 43 44 47 48 VIN−A VIN+A VIN+B VIN−B RBIAS SENSE VREF VCM SYNC VIN−C VIN+C 1 AD9253-EP Description SPI Clock Input/Digital Test Pattern. SPI Data Input and Output Bidirectional SPI Data/Output Lane Mode. SPI Chip Select Bar. Active low enable; 30 kΩ internal pull-up. Digital Input, 30 kΩ Internal Pull-Down. PDWN high = power-down device. PDWN low = run device, normal operation. ADC A Analog Input Complement. ADC A Analog Input True. ADC B Analog Input True. ADC B Analog Input Complement. Sets Analog Current Bias. Connect to 10 kΩ (1% tolerance) resistor to ground. Reference Mode Selection. Voltage Reference Input and Output. Analog Input Common-Mode Voltage. Digital Input. SYNC input to clock divider. ADC C Analog Input Complement. ADC C Analog Input True. These pin descriptions are for two-lane mode (default). For the one-lane mode pin descriptions, see the AD9253 data sheet. Rev. A | Page 9 of 10 AD9253-EP Enhanced Product OUTLINE DIMENSIONS 0.30 0.25 0.20 PIN 1 INDICATOR 37 36 48 1 0.50 BSC TOP VIEW 0.80 0.75 0.70 0.50 0.40 0.30 13 BOTTOM VIEW 0.05 MAX 0.02 NOM COPLANARITY 0.08 0.203 REF SEATING PLANE *5.70 5.60 SQ 5.50 EXPOSED PAD 24 PIN 1 INDICATOR 0.20 MIN FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. *COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-2 WITH THE EXCEPTION OF THE EXPOSED PAD DIMENSION. 10-24-2013-D 7.10 7.00 SQ 6.90 Figure 3. 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 7 mm × 7 mm Body, Very Very Thin Quad (CP-48-13) Dimensions shown in millimeters ORDERING GUIDE Model1 AD9253TCPZ-125EP AD9253TCPZR7-125EP 1 Temperature Range −55°C to +125°C −55°C to +125°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_WQ] Z = RoHS Compliant Part. ©2013–2015 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D11074-0-10/15(A) Rev. A | Page 10 of 10 Package Option CP-48-13 CP-48-13